system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //headers
#include <stdio.h>
#include <cuda.h>
#define imin(a, b) ((a < b) ? a : b)
#define sum_squares(x) (x * (x + 1) * (2 * x + 1) / 6)
//global variables
float *hostA = NULL;
float *hostB = NULL;
float *partial_hostC = NULL;
float *deviceA = NULL;
float *deviceB = NULL;
float *partial_deviceC = NULL;
const int iNumberOfArrayElements = 33 * 1024;
const int threadsPerBlock = 256;
const int blocksPerGrid = imin(32, (iNumberOfArrayElements + threadsPerBlock - 1) / threadsPerBlock);
// *** CUDA KERNEL DEFINITION ***
__global__ void vecDotProduct(float *input1, float *input2, float *output)
{
//variable declaration
//shared across all threads within block
__shared__ float cache[threadsPerBlock];
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int cacheIndex = threadIdx.x;
float temp = 0;
//code
while(tid < iNumberOfArrayElements)
{
temp += input1[tid] * input2[tid];
tid += blockDim.x * gridDim.x;
}
//set the cache values
cache[cacheIndex] = temp;
//synchronize threads in the block
__syncthreads();
//summation reduction
int i = blockDim.x / 2;
while(i != 0)
{
if(cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
//copy to output memory
if(cacheIndex == 0)
output[blockIdx.x] = cache[0];
}
int main(void)
{
//function declaration
void cleanup(void);
//code
//allocate memory on host
hostA = (float *)malloc(iNumberOfArrayElements * sizeof(float));
if(hostA == NULL)
{
printf("CPU Memory Fatal Error - Can Not Allocate Enough Memory For Host Input Array 1.\nExiting Now ...\n");
exit(EXIT_FAILURE);
}
hostB = (float *)malloc(iNumberOfArrayElements * sizeof(float));
if(hostB == NULL)
{
printf("CPU Memory Fatal Error - Can Not Allocate Enough Memory For Host Input Array 2.\nExiting Now ...\n");
cleanup();
exit(EXIT_FAILURE);
}
partial_hostC = (float *)malloc(blocksPerGrid * sizeof(float));
if(partial_hostC == NULL)
{
printf("CPU Memory Fatal Error - Can Not Allocate Enough Memory For Host Output Array.\nExiting Now ...\n");
cleanup();
exit(EXIT_FAILURE);
}
//allocate memory on device
cudaError_t err = cudaSuccess;
err = cudaMalloc((void **)&deviceA, iNumberOfArrayElements * sizeof(float));
if(err != cudaSuccess)
{
printf("GPU Memory Fatal Error - %s In The File Name %s At Line No %d.\nExiting Now ...\n", cudaGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
err = cudaMalloc((void **)&deviceB, iNumberOfArrayElements * sizeof(float));
if(err != cudaSuccess)
{
printf("GPU Memory Fatal Error - %s In The File Name %s At Line No %d.\nExiting Now ...\n", cudaGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
err = cudaMalloc((void **)&partial_deviceC, blocksPerGrid * sizeof(float));
if(err != cudaSuccess)
{
printf("GPU Memory Fatal Error - %s In The File Name %s At Line No %d.\nExiting Now ...\n", cudaGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
//fill the host input array
for(int i = 0; i < iNumberOfArrayElements; i++)
{
hostA[i] = i;
hostB[i] = i * 2;
}
//copy the host input array to device input
err = cudaMemcpy(deviceA, hostA, iNumberOfArrayElements * sizeof(float), cudaMemcpyHostToDevice);
if(err != cudaSuccess)
{
printf("GPU Memory Fatal Error - %s In The File Name %s At Line No %d.\nExiting Now ...\n", cudaGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
err = cudaMemcpy(deviceB, hostB, iNumberOfArrayElements * sizeof(float), cudaMemcpyHostToDevice);
if(err != cudaSuccess)
{
printf("GPU Memory Fatal Error - %s In The File Name %s At Line No %d.\nExiting Now ...\n", cudaGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
//launch the kernel
vecDotProduct<<<blocksPerGrid, threadsPerBlock>>>(deviceA, deviceB, partial_deviceC);
//copy the device output array back to host
err = cudaMemcpy(partial_hostC, partial_deviceC, blocksPerGrid * sizeof(float), cudaMemcpyDeviceToHost);
if(err != cudaSuccess)
{
printf("GPU Memory Fatal Error - %s In The File Name %s At Line No %d.\nExiting Now ...\n", cudaGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
//calculate final result on host
float finalC = 0.0f;
for(int i = 0; i < blocksPerGrid; i++)
{
finalC += partial_hostC[i];
}
//check if the final value is correct
if(finalC == (2 * sum_squares((float)(iNumberOfArrayElements - 1))))
printf("Dot Product Calculated On Device Is Accurate.\n");
else
printf("Dot Product Calculated On Device Is Not Accurate.\n");
printf("Dot Product = %0.6.\n", finalC);
printf("Expected Product = %0.6f.\n", 2 * sum_squares((float)(iNumberOfArrayElements - 1)));
//total cleanup
cleanup();
return (0);
}
void cleanup(void)
{
//code
//free device memory
if(partial_deviceC)
{
cudaFree(partial_deviceC);
partial_deviceC = NULL;
}
if(deviceB)
{
cudaFree(deviceB);
deviceB = NULL;
}
if(deviceA)
{
cudaFree(deviceA);
deviceA = NULL;
}
//free host memory
if(partial_hostC)
{
free(partial_hostC);
partial_hostC = NULL;
}
if(hostB)
{
free(hostB);
hostB = NULL;
}
if(hostA)
{
free(hostA);
hostA = NULL;
}
} | //headers
#include <stdio.h>
#include <hip/hip_runtime.h>
#define imin(a, b) ((a < b) ? a : b)
#define sum_squares(x) (x * (x + 1) * (2 * x + 1) / 6)
//global variables
float *hostA = NULL;
float *hostB = NULL;
float *partial_hostC = NULL;
float *deviceA = NULL;
float *deviceB = NULL;
float *partial_deviceC = NULL;
const int iNumberOfArrayElements = 33 * 1024;
const int threadsPerBlock = 256;
const int blocksPerGrid = imin(32, (iNumberOfArrayElements + threadsPerBlock - 1) / threadsPerBlock);
// *** CUDA KERNEL DEFINITION ***
__global__ void vecDotProduct(float *input1, float *input2, float *output)
{
//variable declaration
//shared across all threads within block
__shared__ float cache[threadsPerBlock];
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int cacheIndex = threadIdx.x;
float temp = 0;
//code
while(tid < iNumberOfArrayElements)
{
temp += input1[tid] * input2[tid];
tid += blockDim.x * gridDim.x;
}
//set the cache values
cache[cacheIndex] = temp;
//synchronize threads in the block
__syncthreads();
//summation reduction
int i = blockDim.x / 2;
while(i != 0)
{
if(cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
//copy to output memory
if(cacheIndex == 0)
output[blockIdx.x] = cache[0];
}
int main(void)
{
//function declaration
void cleanup(void);
//code
//allocate memory on host
hostA = (float *)malloc(iNumberOfArrayElements * sizeof(float));
if(hostA == NULL)
{
printf("CPU Memory Fatal Error - Can Not Allocate Enough Memory For Host Input Array 1.\nExiting Now ...\n");
exit(EXIT_FAILURE);
}
hostB = (float *)malloc(iNumberOfArrayElements * sizeof(float));
if(hostB == NULL)
{
printf("CPU Memory Fatal Error - Can Not Allocate Enough Memory For Host Input Array 2.\nExiting Now ...\n");
cleanup();
exit(EXIT_FAILURE);
}
partial_hostC = (float *)malloc(blocksPerGrid * sizeof(float));
if(partial_hostC == NULL)
{
printf("CPU Memory Fatal Error - Can Not Allocate Enough Memory For Host Output Array.\nExiting Now ...\n");
cleanup();
exit(EXIT_FAILURE);
}
//allocate memory on device
hipError_t err = hipSuccess;
err = hipMalloc((void **)&deviceA, iNumberOfArrayElements * sizeof(float));
if(err != hipSuccess)
{
printf("GPU Memory Fatal Error - %s In The File Name %s At Line No %d.\nExiting Now ...\n", hipGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
err = hipMalloc((void **)&deviceB, iNumberOfArrayElements * sizeof(float));
if(err != hipSuccess)
{
printf("GPU Memory Fatal Error - %s In The File Name %s At Line No %d.\nExiting Now ...\n", hipGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
err = hipMalloc((void **)&partial_deviceC, blocksPerGrid * sizeof(float));
if(err != hipSuccess)
{
printf("GPU Memory Fatal Error - %s In The File Name %s At Line No %d.\nExiting Now ...\n", hipGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
//fill the host input array
for(int i = 0; i < iNumberOfArrayElements; i++)
{
hostA[i] = i;
hostB[i] = i * 2;
}
//copy the host input array to device input
err = hipMemcpy(deviceA, hostA, iNumberOfArrayElements * sizeof(float), hipMemcpyHostToDevice);
if(err != hipSuccess)
{
printf("GPU Memory Fatal Error - %s In The File Name %s At Line No %d.\nExiting Now ...\n", hipGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
err = hipMemcpy(deviceB, hostB, iNumberOfArrayElements * sizeof(float), hipMemcpyHostToDevice);
if(err != hipSuccess)
{
printf("GPU Memory Fatal Error - %s In The File Name %s At Line No %d.\nExiting Now ...\n", hipGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
//launch the kernel
vecDotProduct<<<blocksPerGrid, threadsPerBlock>>>(deviceA, deviceB, partial_deviceC);
//copy the device output array back to host
err = hipMemcpy(partial_hostC, partial_deviceC, blocksPerGrid * sizeof(float), hipMemcpyDeviceToHost);
if(err != hipSuccess)
{
printf("GPU Memory Fatal Error - %s In The File Name %s At Line No %d.\nExiting Now ...\n", hipGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
//calculate final result on host
float finalC = 0.0f;
for(int i = 0; i < blocksPerGrid; i++)
{
finalC += partial_hostC[i];
}
//check if the final value is correct
if(finalC == (2 * sum_squares((float)(iNumberOfArrayElements - 1))))
printf("Dot Product Calculated On Device Is Accurate.\n");
else
printf("Dot Product Calculated On Device Is Not Accurate.\n");
printf("Dot Product = %0.6.\n", finalC);
printf("Expected Product = %0.6f.\n", 2 * sum_squares((float)(iNumberOfArrayElements - 1)));
//total cleanup
cleanup();
return (0);
}
void cleanup(void)
{
//code
//free device memory
if(partial_deviceC)
{
hipFree(partial_deviceC);
partial_deviceC = NULL;
}
if(deviceB)
{
hipFree(deviceB);
deviceB = NULL;
}
if(deviceA)
{
hipFree(deviceA);
deviceA = NULL;
}
//free host memory
if(partial_hostC)
{
free(partial_hostC);
partial_hostC = NULL;
}
if(hostB)
{
free(hostB);
hostB = NULL;
}
if(hostA)
{
free(hostA);
hostA = NULL;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //headers
#include <stdio.h>
#include <hip/hip_runtime.h>
#define imin(a, b) ((a < b) ? a : b)
#define sum_squares(x) (x * (x + 1) * (2 * x + 1) / 6)
//global variables
float *hostA = NULL;
float *hostB = NULL;
float *partial_hostC = NULL;
float *deviceA = NULL;
float *deviceB = NULL;
float *partial_deviceC = NULL;
const int iNumberOfArrayElements = 33 * 1024;
const int threadsPerBlock = 256;
const int blocksPerGrid = imin(32, (iNumberOfArrayElements + threadsPerBlock - 1) / threadsPerBlock);
// *** CUDA KERNEL DEFINITION ***
__global__ void vecDotProduct(float *input1, float *input2, float *output)
{
//variable declaration
//shared across all threads within block
__shared__ float cache[threadsPerBlock];
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int cacheIndex = threadIdx.x;
float temp = 0;
//code
while(tid < iNumberOfArrayElements)
{
temp += input1[tid] * input2[tid];
tid += blockDim.x * gridDim.x;
}
//set the cache values
cache[cacheIndex] = temp;
//synchronize threads in the block
__syncthreads();
//summation reduction
int i = blockDim.x / 2;
while(i != 0)
{
if(cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
//copy to output memory
if(cacheIndex == 0)
output[blockIdx.x] = cache[0];
}
int main(void)
{
//function declaration
void cleanup(void);
//code
//allocate memory on host
hostA = (float *)malloc(iNumberOfArrayElements * sizeof(float));
if(hostA == NULL)
{
printf("CPU Memory Fatal Error - Can Not Allocate Enough Memory For Host Input Array 1.\nExiting Now ...\n");
exit(EXIT_FAILURE);
}
hostB = (float *)malloc(iNumberOfArrayElements * sizeof(float));
if(hostB == NULL)
{
printf("CPU Memory Fatal Error - Can Not Allocate Enough Memory For Host Input Array 2.\nExiting Now ...\n");
cleanup();
exit(EXIT_FAILURE);
}
partial_hostC = (float *)malloc(blocksPerGrid * sizeof(float));
if(partial_hostC == NULL)
{
printf("CPU Memory Fatal Error - Can Not Allocate Enough Memory For Host Output Array.\nExiting Now ...\n");
cleanup();
exit(EXIT_FAILURE);
}
//allocate memory on device
hipError_t err = hipSuccess;
err = hipMalloc((void **)&deviceA, iNumberOfArrayElements * sizeof(float));
if(err != hipSuccess)
{
printf("GPU Memory Fatal Error - %s In The File Name %s At Line No %d.\nExiting Now ...\n", hipGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
err = hipMalloc((void **)&deviceB, iNumberOfArrayElements * sizeof(float));
if(err != hipSuccess)
{
printf("GPU Memory Fatal Error - %s In The File Name %s At Line No %d.\nExiting Now ...\n", hipGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
err = hipMalloc((void **)&partial_deviceC, blocksPerGrid * sizeof(float));
if(err != hipSuccess)
{
printf("GPU Memory Fatal Error - %s In The File Name %s At Line No %d.\nExiting Now ...\n", hipGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
//fill the host input array
for(int i = 0; i < iNumberOfArrayElements; i++)
{
hostA[i] = i;
hostB[i] = i * 2;
}
//copy the host input array to device input
err = hipMemcpy(deviceA, hostA, iNumberOfArrayElements * sizeof(float), hipMemcpyHostToDevice);
if(err != hipSuccess)
{
printf("GPU Memory Fatal Error - %s In The File Name %s At Line No %d.\nExiting Now ...\n", hipGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
err = hipMemcpy(deviceB, hostB, iNumberOfArrayElements * sizeof(float), hipMemcpyHostToDevice);
if(err != hipSuccess)
{
printf("GPU Memory Fatal Error - %s In The File Name %s At Line No %d.\nExiting Now ...\n", hipGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
//launch the kernel
vecDotProduct<<<blocksPerGrid, threadsPerBlock>>>(deviceA, deviceB, partial_deviceC);
//copy the device output array back to host
err = hipMemcpy(partial_hostC, partial_deviceC, blocksPerGrid * sizeof(float), hipMemcpyDeviceToHost);
if(err != hipSuccess)
{
printf("GPU Memory Fatal Error - %s In The File Name %s At Line No %d.\nExiting Now ...\n", hipGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
//calculate final result on host
float finalC = 0.0f;
for(int i = 0; i < blocksPerGrid; i++)
{
finalC += partial_hostC[i];
}
//check if the final value is correct
if(finalC == (2 * sum_squares((float)(iNumberOfArrayElements - 1))))
printf("Dot Product Calculated On Device Is Accurate.\n");
else
printf("Dot Product Calculated On Device Is Not Accurate.\n");
printf("Dot Product = %0.6.\n", finalC);
printf("Expected Product = %0.6f.\n", 2 * sum_squares((float)(iNumberOfArrayElements - 1)));
//total cleanup
cleanup();
return (0);
}
void cleanup(void)
{
//code
//free device memory
if(partial_deviceC)
{
hipFree(partial_deviceC);
partial_deviceC = NULL;
}
if(deviceB)
{
hipFree(deviceB);
deviceB = NULL;
}
if(deviceA)
{
hipFree(deviceA);
deviceA = NULL;
}
//free host memory
if(partial_hostC)
{
free(partial_hostC);
partial_hostC = NULL;
}
if(hostB)
{
free(hostB);
hostB = NULL;
}
if(hostA)
{
free(hostA);
hostA = NULL;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13vecDotProductPfS_S_
.globl _Z13vecDotProductPfS_S_
.p2align 8
.type _Z13vecDotProductPfS_S_,@function
_Z13vecDotProductPfS_S_:
s_load_b32 s3, s[0:1], 0x24
s_add_u32 s4, s0, 24
s_mov_b32 s2, s15
s_addc_u32 s5, s1, 0
v_mov_b32_e32 v3, 0
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_cmpx_gt_i32_e32 0x8400, v1
s_cbranch_execz .LBB0_4
s_load_b32 s10, s[4:5], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v3, 0
s_mov_b32 s9, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s10, s10, s3
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_nc_u32_e32 v1, s10, v1
v_add_co_u32 v6, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, 0x83ff, v1
global_load_b32 v2, v[6:7], off
global_load_b32 v4, v[4:5], off
s_or_b32 s9, vcc_lo, s9
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, v2, v4
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s9
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s8
v_lshlrev_b32_e32 v1, 2, v0
s_cmp_lt_u32 s3, 2
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_9
.LBB0_5:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.p2align 6
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s5
s_cmp_gt_u32 s3, 3
s_mov_b32 s3, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_5
.LBB0_9:
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_8
v_add_lshl_u32 v2, s4, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_branch .LBB0_8
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13vecDotProductPfS_S_
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13vecDotProductPfS_S_, .Lfunc_end0-_Z13vecDotProductPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13vecDotProductPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13vecDotProductPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //headers
#include <stdio.h>
#include <hip/hip_runtime.h>
#define imin(a, b) ((a < b) ? a : b)
#define sum_squares(x) (x * (x + 1) * (2 * x + 1) / 6)
//global variables
float *hostA = NULL;
float *hostB = NULL;
float *partial_hostC = NULL;
float *deviceA = NULL;
float *deviceB = NULL;
float *partial_deviceC = NULL;
const int iNumberOfArrayElements = 33 * 1024;
const int threadsPerBlock = 256;
const int blocksPerGrid = imin(32, (iNumberOfArrayElements + threadsPerBlock - 1) / threadsPerBlock);
// *** CUDA KERNEL DEFINITION ***
__global__ void vecDotProduct(float *input1, float *input2, float *output)
{
//variable declaration
//shared across all threads within block
__shared__ float cache[threadsPerBlock];
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int cacheIndex = threadIdx.x;
float temp = 0;
//code
while(tid < iNumberOfArrayElements)
{
temp += input1[tid] * input2[tid];
tid += blockDim.x * gridDim.x;
}
//set the cache values
cache[cacheIndex] = temp;
//synchronize threads in the block
__syncthreads();
//summation reduction
int i = blockDim.x / 2;
while(i != 0)
{
if(cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
//copy to output memory
if(cacheIndex == 0)
output[blockIdx.x] = cache[0];
}
int main(void)
{
//function declaration
void cleanup(void);
//code
//allocate memory on host
hostA = (float *)malloc(iNumberOfArrayElements * sizeof(float));
if(hostA == NULL)
{
printf("CPU Memory Fatal Error - Can Not Allocate Enough Memory For Host Input Array 1.\nExiting Now ...\n");
exit(EXIT_FAILURE);
}
hostB = (float *)malloc(iNumberOfArrayElements * sizeof(float));
if(hostB == NULL)
{
printf("CPU Memory Fatal Error - Can Not Allocate Enough Memory For Host Input Array 2.\nExiting Now ...\n");
cleanup();
exit(EXIT_FAILURE);
}
partial_hostC = (float *)malloc(blocksPerGrid * sizeof(float));
if(partial_hostC == NULL)
{
printf("CPU Memory Fatal Error - Can Not Allocate Enough Memory For Host Output Array.\nExiting Now ...\n");
cleanup();
exit(EXIT_FAILURE);
}
//allocate memory on device
hipError_t err = hipSuccess;
err = hipMalloc((void **)&deviceA, iNumberOfArrayElements * sizeof(float));
if(err != hipSuccess)
{
printf("GPU Memory Fatal Error - %s In The File Name %s At Line No %d.\nExiting Now ...\n", hipGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
err = hipMalloc((void **)&deviceB, iNumberOfArrayElements * sizeof(float));
if(err != hipSuccess)
{
printf("GPU Memory Fatal Error - %s In The File Name %s At Line No %d.\nExiting Now ...\n", hipGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
err = hipMalloc((void **)&partial_deviceC, blocksPerGrid * sizeof(float));
if(err != hipSuccess)
{
printf("GPU Memory Fatal Error - %s In The File Name %s At Line No %d.\nExiting Now ...\n", hipGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
//fill the host input array
for(int i = 0; i < iNumberOfArrayElements; i++)
{
hostA[i] = i;
hostB[i] = i * 2;
}
//copy the host input array to device input
err = hipMemcpy(deviceA, hostA, iNumberOfArrayElements * sizeof(float), hipMemcpyHostToDevice);
if(err != hipSuccess)
{
printf("GPU Memory Fatal Error - %s In The File Name %s At Line No %d.\nExiting Now ...\n", hipGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
err = hipMemcpy(deviceB, hostB, iNumberOfArrayElements * sizeof(float), hipMemcpyHostToDevice);
if(err != hipSuccess)
{
printf("GPU Memory Fatal Error - %s In The File Name %s At Line No %d.\nExiting Now ...\n", hipGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
//launch the kernel
vecDotProduct<<<blocksPerGrid, threadsPerBlock>>>(deviceA, deviceB, partial_deviceC);
//copy the device output array back to host
err = hipMemcpy(partial_hostC, partial_deviceC, blocksPerGrid * sizeof(float), hipMemcpyDeviceToHost);
if(err != hipSuccess)
{
printf("GPU Memory Fatal Error - %s In The File Name %s At Line No %d.\nExiting Now ...\n", hipGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
//calculate final result on host
float finalC = 0.0f;
for(int i = 0; i < blocksPerGrid; i++)
{
finalC += partial_hostC[i];
}
//check if the final value is correct
if(finalC == (2 * sum_squares((float)(iNumberOfArrayElements - 1))))
printf("Dot Product Calculated On Device Is Accurate.\n");
else
printf("Dot Product Calculated On Device Is Not Accurate.\n");
printf("Dot Product = %0.6.\n", finalC);
printf("Expected Product = %0.6f.\n", 2 * sum_squares((float)(iNumberOfArrayElements - 1)));
//total cleanup
cleanup();
return (0);
}
void cleanup(void)
{
//code
//free device memory
if(partial_deviceC)
{
hipFree(partial_deviceC);
partial_deviceC = NULL;
}
if(deviceB)
{
hipFree(deviceB);
deviceB = NULL;
}
if(deviceA)
{
hipFree(deviceA);
deviceA = NULL;
}
//free host memory
if(partial_hostC)
{
free(partial_hostC);
partial_hostC = NULL;
}
if(hostB)
{
free(hostB);
hostB = NULL;
}
if(hostA)
{
free(hostA);
hostA = NULL;
}
} | .text
.file "VectorDotProduct.hip"
.globl _Z28__device_stub__vecDotProductPfS_S_ # -- Begin function _Z28__device_stub__vecDotProductPfS_S_
.p2align 4, 0x90
.type _Z28__device_stub__vecDotProductPfS_S_,@function
_Z28__device_stub__vecDotProductPfS_S_: # @_Z28__device_stub__vecDotProductPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13vecDotProductPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z28__device_stub__vecDotProductPfS_S_, .Lfunc_end0-_Z28__device_stub__vecDotProductPfS_S_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x55bb29e0 # float 2.57235658E+13
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_1:
.quad 0x42b7653c00000000 # double 25723565768704
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl $135168, %edi # imm = 0x21000
callq malloc
movq %rax, hostA(%rip)
testq %rax, %rax
je .LBB1_26
# %bb.1:
movl $135168, %edi # imm = 0x21000
callq malloc
movq %rax, hostB(%rip)
testq %rax, %rax
je .LBB1_2
# %bb.5:
movl $128, %edi
callq malloc
movq %rax, partial_hostC(%rip)
testq %rax, %rax
je .LBB1_6
# %bb.7:
movl $deviceA, %edi
movl $135168, %esi # imm = 0x21000
callq hipMalloc
testl %eax, %eax
jne .LBB1_8
# %bb.10:
movl $deviceB, %edi
movl $135168, %esi # imm = 0x21000
callq hipMalloc
testl %eax, %eax
jne .LBB1_11
# %bb.12:
movl $partial_deviceC, %edi
movl $128, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_27
# %bb.13: # %.preheader46
movq hostA(%rip), %rax
xorl %ecx, %ecx
movq hostB(%rip), %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_14: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %esi, %xmm0
movss %xmm0, (%rax,%rsi,4)
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%rdx,%rsi,4)
incq %rsi
addl $2, %ecx
cmpq $33792, %rsi # imm = 0x8400
jne .LBB1_14
# %bb.15:
movq deviceA(%rip), %rdi
movq hostA(%rip), %rsi
movl $135168, %edx # imm = 0x21000
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_16
# %bb.17:
movq deviceB(%rip), %rdi
movq hostB(%rip), %rsi
movl $135168, %edx # imm = 0x21000
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_18
# %bb.19:
movabsq $4294967328, %rdi # imm = 0x100000020
leaq 224(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_21
# %bb.20:
movq deviceA(%rip), %rax
movq deviceB(%rip), %rcx
movq partial_deviceC(%rip), %rdx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13vecDotProductPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_21:
movq partial_hostC(%rip), %rdi
movq partial_deviceC(%rip), %rsi
movl $128, %edx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_25
# %bb.22: # %.preheader
xorps %xmm0, %xmm0
movq partial_hostC(%rip), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_23: # =>This Inner Loop Header: Depth=1
addss (%rax,%rcx,4), %xmm0
incq %rcx
cmpq $32, %rcx
jne .LBB1_23
# %bb.24:
ucomiss .LCPI1_0(%rip), %xmm0
movl $.Lstr, %eax
movl $.Lstr.1, %edi
cmovneq %rax, %rdi
cmovpq %rax, %rdi
movss %xmm0, 4(%rsp) # 4-byte Spill
callq puts@PLT
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movsd .LCPI1_1(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.8, %edi
movb $1, %al
callq printf
callq _Z7cleanupv
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 8
retq
.LBB1_26:
.cfi_def_cfa_offset 112
movl $.Lstr.4, %edi
callq puts@PLT
movl $1, %edi
callq exit
.LBB1_2:
movl $.Lstr.3, %edi
jmp .LBB1_3
.LBB1_6:
movl $.Lstr.2, %edi
.LBB1_3:
callq puts@PLT
jmp .LBB1_4
.LBB1_8:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movl $.L.str.4, %edx
movq %rax, %rsi
movl $96, %ecx
jmp .LBB1_9
.LBB1_11:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movl $.L.str.4, %edx
movq %rax, %rsi
movl $104, %ecx
jmp .LBB1_9
.LBB1_27:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movl $.L.str.4, %edx
movq %rax, %rsi
movl $112, %ecx
jmp .LBB1_9
.LBB1_16:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movl $.L.str.4, %edx
movq %rax, %rsi
movl $128, %ecx
jmp .LBB1_9
.LBB1_18:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movl $.L.str.4, %edx
movq %rax, %rsi
movl $136, %ecx
jmp .LBB1_9
.LBB1_25:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movl $.L.str.4, %edx
movq %rax, %rsi
movl $148, %ecx
.LBB1_9:
xorl %eax, %eax
callq printf
.LBB1_4:
callq _Z7cleanupv
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z7cleanupv # -- Begin function _Z7cleanupv
.p2align 4, 0x90
.type _Z7cleanupv,@function
_Z7cleanupv: # @_Z7cleanupv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq partial_deviceC(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
callq hipFree
movq $0, partial_deviceC(%rip)
.LBB2_2:
movq deviceB(%rip), %rdi
testq %rdi, %rdi
je .LBB2_4
# %bb.3:
callq hipFree
movq $0, deviceB(%rip)
.LBB2_4:
movq deviceA(%rip), %rdi
testq %rdi, %rdi
je .LBB2_6
# %bb.5:
callq hipFree
movq $0, deviceA(%rip)
.LBB2_6:
movq partial_hostC(%rip), %rdi
testq %rdi, %rdi
je .LBB2_8
# %bb.7:
callq free
movq $0, partial_hostC(%rip)
.LBB2_8:
movq hostB(%rip), %rdi
testq %rdi, %rdi
je .LBB2_10
# %bb.9:
callq free
movq $0, hostB(%rip)
.LBB2_10:
movq hostA(%rip), %rdi
testq %rdi, %rdi
je .LBB2_12
# %bb.11:
callq free
movq $0, hostA(%rip)
.LBB2_12:
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z7cleanupv, .Lfunc_end2-_Z7cleanupv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13vecDotProductPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type hostA,@object # @hostA
.bss
.globl hostA
.p2align 3, 0x0
hostA:
.quad 0
.size hostA, 8
.type hostB,@object # @hostB
.globl hostB
.p2align 3, 0x0
hostB:
.quad 0
.size hostB, 8
.type partial_hostC,@object # @partial_hostC
.globl partial_hostC
.p2align 3, 0x0
partial_hostC:
.quad 0
.size partial_hostC, 8
.type deviceA,@object # @deviceA
.globl deviceA
.p2align 3, 0x0
deviceA:
.quad 0
.size deviceA, 8
.type deviceB,@object # @deviceB
.globl deviceB
.p2align 3, 0x0
deviceB:
.quad 0
.size deviceB, 8
.type partial_deviceC,@object # @partial_deviceC
.globl partial_deviceC
.p2align 3, 0x0
partial_deviceC:
.quad 0
.size partial_deviceC, 8
.type _Z13vecDotProductPfS_S_,@object # @_Z13vecDotProductPfS_S_
.section .rodata,"a",@progbits
.globl _Z13vecDotProductPfS_S_
.p2align 3, 0x0
_Z13vecDotProductPfS_S_:
.quad _Z28__device_stub__vecDotProductPfS_S_
.size _Z13vecDotProductPfS_S_, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "GPU Memory Fatal Error - %s In The File Name %s At Line No %d.\nExiting Now ...\n"
.size .L.str.3, 80
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/yashPat98/HPP/master/CUDA/CUDA-by-Example/12-VectorDotProduct/VectorDotProduct.hip"
.size .L.str.4, 140
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Dot Product = %0.6.\n"
.size .L.str.7, 21
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Expected Product = %0.6f.\n"
.size .L.str.8, 27
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13vecDotProductPfS_S_"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Dot Product Calculated On Device Is Not Accurate."
.size .Lstr, 50
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Dot Product Calculated On Device Is Accurate."
.size .Lstr.1, 46
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "CPU Memory Fatal Error - Can Not Allocate Enough Memory For Host Output Array.\nExiting Now ..."
.size .Lstr.2, 95
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "CPU Memory Fatal Error - Can Not Allocate Enough Memory For Host Input Array 2.\nExiting Now ..."
.size .Lstr.3, 96
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "CPU Memory Fatal Error - Can Not Allocate Enough Memory For Host Input Array 1.\nExiting Now ..."
.size .Lstr.4, 96
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__vecDotProductPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym deviceA
.addrsig_sym deviceB
.addrsig_sym partial_deviceC
.addrsig_sym _Z13vecDotProductPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13vecDotProductPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x150 ; /* 0x0000011000007945 */
/* 0x000fe20003800000 */
/*0040*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R0, R7, c[0x0][0x0], R8 ; /* 0x0000000007007a24 */
/* 0x001fca00078e0208 */
/*0070*/ ISETP.GT.AND P0, PT, R0, 0x83ff, PT ; /* 0x000083ff0000780c */
/* 0x000fda0003f04270 */
/*0080*/ @P0 BRA 0x140 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*0090*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe400078e00ff */
/*00a0*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fca0000000f00 */
/*00b0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0205 */
/*00c0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fe400078e0205 */
/*00d0*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea8000c1e1900 */
/*00e0*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff097624 */
/* 0x000fc800078e00ff */
/*0100*/ IMAD R0, R9, c[0x0][0xc], R0 ; /* 0x0000030009007a24 */
/* 0x000fca00078e0200 */
/*0110*/ ISETP.GE.AND P0, PT, R0, 0x8400, PT ; /* 0x000084000000780c */
/* 0x000fe20003f06270 */
/*0120*/ FFMA R6, R5, R2, R6 ; /* 0x0000000205067223 */
/* 0x004fd80000000006 */
/*0130*/ @!P0 BRA 0xa0 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*0140*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0150*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0160*/ STS [R8.X4], R6 ; /* 0x0000000608007388 */
/* 0x0001e20000004800 */
/*0170*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fc60008011604 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0190*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f05270 */
/*01a0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf25270 */
/*01b0*/ @!P1 BRA 0x2a0 ; /* 0x000000e000009947 */
/* 0x000fea0003800000 */
/*01c0*/ SHF.L.U32 R0, R8, 0x2, RZ ; /* 0x0000000208007819 */
/* 0x001fe200000006ff */
/*01d0*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fca000f8e00ff */
/*01e0*/ ISETP.GE.AND P1, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x000fda0003f26270 */
/*01f0*/ @!P1 LEA R2, R3.reuse, R0, 0x2 ; /* 0x0000000003029211 */
/* 0x040fe200078e10ff */
/*0200*/ @!P1 LDS R4, [R8.X4] ; /* 0x0000000008049984 */
/* 0x000fe80000004800 */
/*0210*/ @!P1 LDS R5, [R2] ; /* 0x0000000002059984 */
/* 0x000e240000000800 */
/*0220*/ @!P1 FADD R4, R4, R5 ; /* 0x0000000504049221 */
/* 0x001fe20000000000 */
/*0230*/ IADD3 R5, R3.reuse, 0x1, RZ ; /* 0x0000000103057810 */
/* 0x040fe40007ffe0ff */
/*0240*/ LEA.HI R3, R3, R3, RZ, 0x1 ; /* 0x0000000303037211 */
/* 0x000fc400078f08ff */
/*0250*/ @!P1 STS [R8.X4], R4 ; /* 0x0000000408009388 */
/* 0x0001e80000004800 */
/*0260*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0270*/ ISETP.GT.U32.AND P1, PT, R5, 0x2, PT ; /* 0x000000020500780c */
/* 0x000fe40003f24070 */
/*0280*/ SHF.R.S32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fd60000011403 */
/*0290*/ @P1 BRA 0x1e0 ; /* 0xffffff4000001947 */
/* 0x001fea000383ffff */
/*02a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*02b0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*02c0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fc800078e00ff */
/*02d0*/ IMAD.WIDE.U32 R2, R7, R2, c[0x0][0x170] ; /* 0x00005c0007027625 */
/* 0x000fca00078e0002 */
/*02e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ BRA 0x300; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13vecDotProductPfS_S_
.globl _Z13vecDotProductPfS_S_
.p2align 8
.type _Z13vecDotProductPfS_S_,@function
_Z13vecDotProductPfS_S_:
s_load_b32 s3, s[0:1], 0x24
s_add_u32 s4, s0, 24
s_mov_b32 s2, s15
s_addc_u32 s5, s1, 0
v_mov_b32_e32 v3, 0
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_cmpx_gt_i32_e32 0x8400, v1
s_cbranch_execz .LBB0_4
s_load_b32 s10, s[4:5], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v3, 0
s_mov_b32 s9, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s10, s10, s3
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_nc_u32_e32 v1, s10, v1
v_add_co_u32 v6, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, 0x83ff, v1
global_load_b32 v2, v[6:7], off
global_load_b32 v4, v[4:5], off
s_or_b32 s9, vcc_lo, s9
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, v2, v4
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s9
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s8
v_lshlrev_b32_e32 v1, 2, v0
s_cmp_lt_u32 s3, 2
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_9
.LBB0_5:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.p2align 6
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s5
s_cmp_gt_u32 s3, 3
s_mov_b32 s3, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_5
.LBB0_9:
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_8
v_add_lshl_u32 v2, s4, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_branch .LBB0_8
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13vecDotProductPfS_S_
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13vecDotProductPfS_S_, .Lfunc_end0-_Z13vecDotProductPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13vecDotProductPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13vecDotProductPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ce620_00000000-6_VectorDotProduct.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7cleanupv
.type _Z7cleanupv, @function
_Z7cleanupv:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq partial_deviceC(%rip), %rdi
testq %rdi, %rdi
je .L4
call cudaFree@PLT
movq $0, partial_deviceC(%rip)
.L4:
movq deviceB(%rip), %rdi
testq %rdi, %rdi
je .L5
call cudaFree@PLT
movq $0, deviceB(%rip)
.L5:
movq deviceA(%rip), %rdi
testq %rdi, %rdi
je .L6
call cudaFree@PLT
movq $0, deviceA(%rip)
.L6:
movq partial_hostC(%rip), %rdi
testq %rdi, %rdi
je .L7
call free@PLT
movq $0, partial_hostC(%rip)
.L7:
movq hostB(%rip), %rdi
testq %rdi, %rdi
je .L8
call free@PLT
movq $0, hostB(%rip)
.L8:
movq hostA(%rip), %rdi
testq %rdi, %rdi
je .L3
call free@PLT
movq $0, hostA(%rip)
.L3:
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z7cleanupv, .-_Z7cleanupv
.globl _Z37__device_stub__Z13vecDotProductPfS_S_PfS_S_
.type _Z37__device_stub__Z13vecDotProductPfS_S_PfS_S_, @function
_Z37__device_stub__Z13vecDotProductPfS_S_PfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13vecDotProductPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z37__device_stub__Z13vecDotProductPfS_S_PfS_S_, .-_Z37__device_stub__Z13vecDotProductPfS_S_PfS_S_
.globl _Z13vecDotProductPfS_S_
.type _Z13vecDotProductPfS_S_, @function
_Z13vecDotProductPfS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13vecDotProductPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z13vecDotProductPfS_S_, .-_Z13vecDotProductPfS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "CPU Memory Fatal Error - Can Not Allocate Enough Memory For Host Input Array 1.\nExiting Now ...\n"
.align 8
.LC2:
.string "CPU Memory Fatal Error - Can Not Allocate Enough Memory For Host Input Array 2.\nExiting Now ...\n"
.align 8
.LC3:
.string "CPU Memory Fatal Error - Can Not Allocate Enough Memory For Host Output Array.\nExiting Now ...\n"
.align 8
.LC4:
.string "/home/ubuntu/Datasets/stackv2/train-structured/yashPat98/HPP/master/CUDA/CUDA-by-Example/12-VectorDotProduct/VectorDotProduct.cu"
.align 8
.LC5:
.string "GPU Memory Fatal Error - %s In The File Name %s At Line No %d.\nExiting Now ...\n"
.align 8
.LC7:
.string "Dot Product Calculated On Device Is Accurate.\n"
.align 8
.LC8:
.string "Dot Product Calculated On Device Is Not Accurate.\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC9:
.string "Dot Product = %0.6.\n"
.LC11:
.string "Expected Product = %0.6f.\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $135168, %edi
call malloc@PLT
movq %rax, hostA(%rip)
testq %rax, %rax
je .L39
movl $135168, %edi
call malloc@PLT
movq %rax, hostB(%rip)
testq %rax, %rax
je .L40
movl $128, %edi
call malloc@PLT
movq %rax, partial_hostC(%rip)
testq %rax, %rax
je .L41
movl $135168, %esi
leaq deviceA(%rip), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L42
movl $135168, %esi
leaq deviceB(%rip), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L43
movl $128, %esi
leaq partial_deviceC(%rip), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L44
movl $0, %eax
.L25:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movq hostA(%rip), %rdx
movss %xmm0, (%rdx,%rax,4)
leal (%rax,%rax), %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movq hostB(%rip), %rdx
movss %xmm0, (%rdx,%rax,4)
addq $1, %rax
cmpq $33792, %rax
jne .L25
movl $1, %ecx
movl $135168, %edx
movq hostA(%rip), %rsi
movq deviceA(%rip), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L45
movl $1, %ecx
movl $135168, %edx
movq hostB(%rip), %rsi
movq deviceB(%rip), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L46
movl $256, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $32, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L47
.L28:
movl $2, %ecx
movl $128, %edx
movq partial_deviceC(%rip), %rsi
movq partial_hostC(%rip), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L48
movq partial_hostC(%rip), %rax
leaq 128(%rax), %rdx
movl $0x00000000, 12(%rsp)
.L30:
movss 12(%rsp), %xmm1
addss (%rax), %xmm1
movss %xmm1, 12(%rsp)
addq $4, %rax
cmpq %rdx, %rax
jne .L30
ucomiss .LC6(%rip), %xmm1
jp .L31
jne .L31
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L33:
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd .LC10(%rip), %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call _Z7cleanupv
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
leaq .LC1(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L40:
leaq .LC2(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
call _Z7cleanupv
movl $1, %edi
call exit@PLT
.L41:
leaq .LC3(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
call _Z7cleanupv
movl $1, %edi
call exit@PLT
.L42:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $96, %r8d
leaq .LC4(%rip), %rcx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z7cleanupv
movl $1, %edi
call exit@PLT
.L43:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $104, %r8d
leaq .LC4(%rip), %rcx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z7cleanupv
movl $1, %edi
call exit@PLT
.L44:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $112, %r8d
leaq .LC4(%rip), %rcx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z7cleanupv
movl $1, %edi
call exit@PLT
.L45:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $128, %r8d
leaq .LC4(%rip), %rcx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z7cleanupv
movl $1, %edi
call exit@PLT
.L46:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $136, %r8d
leaq .LC4(%rip), %rcx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z7cleanupv
movl $1, %edi
call exit@PLT
.L47:
movq partial_deviceC(%rip), %rdx
movq deviceB(%rip), %rsi
movq deviceA(%rip), %rdi
call _Z37__device_stub__Z13vecDotProductPfS_S_PfS_S_
jmp .L28
.L48:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $148, %r8d
leaq .LC4(%rip), %rcx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z7cleanupv
movl $1, %edi
call exit@PLT
.L31:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L33
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z13vecDotProductPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z13vecDotProductPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl partial_deviceC
.bss
.align 8
.type partial_deviceC, @object
.size partial_deviceC, 8
partial_deviceC:
.zero 8
.globl deviceB
.align 8
.type deviceB, @object
.size deviceB, 8
deviceB:
.zero 8
.globl deviceA
.align 8
.type deviceA, @object
.size deviceA, 8
deviceA:
.zero 8
.globl partial_hostC
.align 8
.type partial_hostC, @object
.size partial_hostC, 8
partial_hostC:
.zero 8
.globl hostB
.align 8
.type hostB, @object
.size hostB, 8
hostB:
.zero 8
.globl hostA
.align 8
.type hostA, @object
.size hostA, 8
hostA:
.zero 8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC6:
.long 1438329312
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC10:
.long 0
.long 1119315260
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "VectorDotProduct.hip"
.globl _Z28__device_stub__vecDotProductPfS_S_ # -- Begin function _Z28__device_stub__vecDotProductPfS_S_
.p2align 4, 0x90
.type _Z28__device_stub__vecDotProductPfS_S_,@function
_Z28__device_stub__vecDotProductPfS_S_: # @_Z28__device_stub__vecDotProductPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13vecDotProductPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z28__device_stub__vecDotProductPfS_S_, .Lfunc_end0-_Z28__device_stub__vecDotProductPfS_S_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x55bb29e0 # float 2.57235658E+13
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_1:
.quad 0x42b7653c00000000 # double 25723565768704
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl $135168, %edi # imm = 0x21000
callq malloc
movq %rax, hostA(%rip)
testq %rax, %rax
je .LBB1_26
# %bb.1:
movl $135168, %edi # imm = 0x21000
callq malloc
movq %rax, hostB(%rip)
testq %rax, %rax
je .LBB1_2
# %bb.5:
movl $128, %edi
callq malloc
movq %rax, partial_hostC(%rip)
testq %rax, %rax
je .LBB1_6
# %bb.7:
movl $deviceA, %edi
movl $135168, %esi # imm = 0x21000
callq hipMalloc
testl %eax, %eax
jne .LBB1_8
# %bb.10:
movl $deviceB, %edi
movl $135168, %esi # imm = 0x21000
callq hipMalloc
testl %eax, %eax
jne .LBB1_11
# %bb.12:
movl $partial_deviceC, %edi
movl $128, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_27
# %bb.13: # %.preheader46
movq hostA(%rip), %rax
xorl %ecx, %ecx
movq hostB(%rip), %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_14: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %esi, %xmm0
movss %xmm0, (%rax,%rsi,4)
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%rdx,%rsi,4)
incq %rsi
addl $2, %ecx
cmpq $33792, %rsi # imm = 0x8400
jne .LBB1_14
# %bb.15:
movq deviceA(%rip), %rdi
movq hostA(%rip), %rsi
movl $135168, %edx # imm = 0x21000
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_16
# %bb.17:
movq deviceB(%rip), %rdi
movq hostB(%rip), %rsi
movl $135168, %edx # imm = 0x21000
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_18
# %bb.19:
movabsq $4294967328, %rdi # imm = 0x100000020
leaq 224(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_21
# %bb.20:
movq deviceA(%rip), %rax
movq deviceB(%rip), %rcx
movq partial_deviceC(%rip), %rdx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13vecDotProductPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_21:
movq partial_hostC(%rip), %rdi
movq partial_deviceC(%rip), %rsi
movl $128, %edx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_25
# %bb.22: # %.preheader
xorps %xmm0, %xmm0
movq partial_hostC(%rip), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_23: # =>This Inner Loop Header: Depth=1
addss (%rax,%rcx,4), %xmm0
incq %rcx
cmpq $32, %rcx
jne .LBB1_23
# %bb.24:
ucomiss .LCPI1_0(%rip), %xmm0
movl $.Lstr, %eax
movl $.Lstr.1, %edi
cmovneq %rax, %rdi
cmovpq %rax, %rdi
movss %xmm0, 4(%rsp) # 4-byte Spill
callq puts@PLT
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movsd .LCPI1_1(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.8, %edi
movb $1, %al
callq printf
callq _Z7cleanupv
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 8
retq
.LBB1_26:
.cfi_def_cfa_offset 112
movl $.Lstr.4, %edi
callq puts@PLT
movl $1, %edi
callq exit
.LBB1_2:
movl $.Lstr.3, %edi
jmp .LBB1_3
.LBB1_6:
movl $.Lstr.2, %edi
.LBB1_3:
callq puts@PLT
jmp .LBB1_4
.LBB1_8:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movl $.L.str.4, %edx
movq %rax, %rsi
movl $96, %ecx
jmp .LBB1_9
.LBB1_11:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movl $.L.str.4, %edx
movq %rax, %rsi
movl $104, %ecx
jmp .LBB1_9
.LBB1_27:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movl $.L.str.4, %edx
movq %rax, %rsi
movl $112, %ecx
jmp .LBB1_9
.LBB1_16:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movl $.L.str.4, %edx
movq %rax, %rsi
movl $128, %ecx
jmp .LBB1_9
.LBB1_18:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movl $.L.str.4, %edx
movq %rax, %rsi
movl $136, %ecx
jmp .LBB1_9
.LBB1_25:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movl $.L.str.4, %edx
movq %rax, %rsi
movl $148, %ecx
.LBB1_9:
xorl %eax, %eax
callq printf
.LBB1_4:
callq _Z7cleanupv
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z7cleanupv # -- Begin function _Z7cleanupv
.p2align 4, 0x90
.type _Z7cleanupv,@function
_Z7cleanupv: # @_Z7cleanupv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq partial_deviceC(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
callq hipFree
movq $0, partial_deviceC(%rip)
.LBB2_2:
movq deviceB(%rip), %rdi
testq %rdi, %rdi
je .LBB2_4
# %bb.3:
callq hipFree
movq $0, deviceB(%rip)
.LBB2_4:
movq deviceA(%rip), %rdi
testq %rdi, %rdi
je .LBB2_6
# %bb.5:
callq hipFree
movq $0, deviceA(%rip)
.LBB2_6:
movq partial_hostC(%rip), %rdi
testq %rdi, %rdi
je .LBB2_8
# %bb.7:
callq free
movq $0, partial_hostC(%rip)
.LBB2_8:
movq hostB(%rip), %rdi
testq %rdi, %rdi
je .LBB2_10
# %bb.9:
callq free
movq $0, hostB(%rip)
.LBB2_10:
movq hostA(%rip), %rdi
testq %rdi, %rdi
je .LBB2_12
# %bb.11:
callq free
movq $0, hostA(%rip)
.LBB2_12:
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z7cleanupv, .Lfunc_end2-_Z7cleanupv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13vecDotProductPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type hostA,@object # @hostA
.bss
.globl hostA
.p2align 3, 0x0
hostA:
.quad 0
.size hostA, 8
.type hostB,@object # @hostB
.globl hostB
.p2align 3, 0x0
hostB:
.quad 0
.size hostB, 8
.type partial_hostC,@object # @partial_hostC
.globl partial_hostC
.p2align 3, 0x0
partial_hostC:
.quad 0
.size partial_hostC, 8
.type deviceA,@object # @deviceA
.globl deviceA
.p2align 3, 0x0
deviceA:
.quad 0
.size deviceA, 8
.type deviceB,@object # @deviceB
.globl deviceB
.p2align 3, 0x0
deviceB:
.quad 0
.size deviceB, 8
.type partial_deviceC,@object # @partial_deviceC
.globl partial_deviceC
.p2align 3, 0x0
partial_deviceC:
.quad 0
.size partial_deviceC, 8
.type _Z13vecDotProductPfS_S_,@object # @_Z13vecDotProductPfS_S_
.section .rodata,"a",@progbits
.globl _Z13vecDotProductPfS_S_
.p2align 3, 0x0
_Z13vecDotProductPfS_S_:
.quad _Z28__device_stub__vecDotProductPfS_S_
.size _Z13vecDotProductPfS_S_, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "GPU Memory Fatal Error - %s In The File Name %s At Line No %d.\nExiting Now ...\n"
.size .L.str.3, 80
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/yashPat98/HPP/master/CUDA/CUDA-by-Example/12-VectorDotProduct/VectorDotProduct.hip"
.size .L.str.4, 140
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Dot Product = %0.6.\n"
.size .L.str.7, 21
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Expected Product = %0.6f.\n"
.size .L.str.8, 27
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13vecDotProductPfS_S_"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Dot Product Calculated On Device Is Not Accurate."
.size .Lstr, 50
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Dot Product Calculated On Device Is Accurate."
.size .Lstr.1, 46
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "CPU Memory Fatal Error - Can Not Allocate Enough Memory For Host Output Array.\nExiting Now ..."
.size .Lstr.2, 95
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "CPU Memory Fatal Error - Can Not Allocate Enough Memory For Host Input Array 2.\nExiting Now ..."
.size .Lstr.3, 96
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "CPU Memory Fatal Error - Can Not Allocate Enough Memory For Host Input Array 1.\nExiting Now ..."
.size .Lstr.4, 96
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__vecDotProductPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym deviceA
.addrsig_sym deviceB
.addrsig_sym partial_deviceC
.addrsig_sym _Z13vecDotProductPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cstdio>
#include <cmath>
#define DIM 5
#define COUNT (DIM * DIM)
cudaEvent_t ev0;
cudaEvent_t ev1;
/******** Helpers ************************************************************/
#define CHECK_ERROR(msg) (checkCUDAError((msg), __LINE__))
/// Check for CUDA errors. From Part1.
void checkCUDAError(const char *msg, int line)
{
cudaError_t err = cudaGetLastError();
if (cudaSuccess != err) {
fprintf(stderr, "line %d: CUDA error: %s - %s\n",
line, msg, cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
}
/******** GPU implementations ************************************************/
/// Add two matrices.
__global__ void mat_add(float *dst, float *A, float *B)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x > DIM || y > DIM) { return; }
int i = y * DIM + x;
dst[i] = A[i] + B[i];
}
/// Subtract two matrices.
__global__ void mat_sub(float *dst, float *A, float *B)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x > DIM || y > DIM) { return; }
int i = y * DIM + x;
dst[i] = A[i] - B[i];
}
/// Multiply two matrices.
__global__ void mat_mul(float *dst, float *A, float *B)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x > DIM || y > DIM) { return; }
int i = y * DIM + x;
float sum = 0;
for (int j = 0; j < DIM; ++j) {
float Aj = A[y * DIM + j];
float Bj = B[j * DIM + x];
sum += Aj * Bj;
}
dst[i] = sum;
}
/******** CPU implementations ************************************************/
void mat_add_cpu(float *dst, float *A, float *B)
{
for (int i = 0; i < COUNT; ++i) {
dst[i] = A[i] + B[i];
}
}
void mat_sub_cpu(float *dst, float *A, float *B)
{
for (int i = 0; i < COUNT; ++i) {
dst[i] = A[i] - B[i];
}
}
void mat_mul_cpu(float *dst, float *A, float *B)
{
for (int x = 0; x < DIM; ++x) {
for (int y = 0; y < DIM; ++y) {
float sum = 0;
for (int j = 0; j < DIM; ++j) {
float a = A[y * DIM + j];
float b = B[j * DIM + x];
sum += a * b;
}
dst[y * DIM + x] = sum;
}
}
}
/******** Main functions *****************************************************/
float *hst_A, *hst_C, *hst_D;
float *dev_A, *dev_C;
bool test_impl(
void (*gpu)(float *, float *, float *),
void (*cpu)(float *, float *, float *))
{
// Calculate grid/block sizes
dim3 dimGrid(1, 1);
dim3 dimBlock(DIM, DIM);
// Run on GPU
cudaMemcpy(dev_A, hst_A, COUNT * sizeof(*dev_A), cudaMemcpyHostToDevice);
CHECK_ERROR("memcpy");
(*gpu)<<<dimGrid, dimBlock>>>(dev_C, dev_A, dev_A);
CHECK_ERROR("function");
cudaMemcpy(hst_C, dev_C, COUNT * sizeof(*hst_C), cudaMemcpyDeviceToHost);
CHECK_ERROR("memcpy");
// Run on CPU
(*cpu)(hst_D, hst_A, hst_A);
// Check results
for (int i = 0; i < COUNT; ++i) {
if (hst_C[i] != hst_D[i]) {
return false;
}
}
return true;
}
float perf_test_one(dim3 grid, dim3 block, int iters,
void (*f)(float *, float *, float *))
{
// cudaEvent stuff reference: http://choorucode.com/2011/04/28/cuda-timer/
float t = 0;
for (int i = 0; i < iters; ++i) {
cudaEventRecord(ev0, 0);
(*f)<<<grid, block>>>(dev_C, dev_A, dev_A);
cudaEventRecord(ev1, 0);
cudaMemcpy(hst_C, dev_C, COUNT * sizeof(*hst_C), cudaMemcpyDeviceToHost);
cudaEventSynchronize(ev1);
float timeValue;
cudaEventElapsedTime(&timeValue, ev0, ev1);
t += timeValue;
}
return t;
}
void perf_test(const char *name, void (*f)(float *, float *, float *))
{
const int iters = 10000;
for (int g = 1; g <= DIM; ++g) {
for (int b = 1; b <= DIM; ++b) {
float t = perf_test_one(g, b, iters, f);
printf("%s %d %d %f\n", name, g, b, t);
}
}
}
int main()
{
// Allocate matrices
hst_A = (float *) malloc(COUNT * sizeof(*hst_A));
hst_C = (float *) malloc(COUNT * sizeof(*hst_C));
hst_D = (float *) malloc(COUNT * sizeof(*hst_D));
cudaMalloc(&dev_A, COUNT * sizeof(*dev_A));
cudaMalloc(&dev_C, COUNT * sizeof(*dev_C));
CHECK_ERROR("malloc");
// Initialize host/device matrices
for (int i = 0; i < COUNT; ++i) {
hst_A[i] = (float) i;
}
cudaMemcpy(dev_A, hst_A, COUNT * sizeof(*dev_A), cudaMemcpyHostToDevice);
// Test GPU implementations
printf("%s mat_add\n", test_impl(mat_add, mat_add_cpu) ? "pass" : "FAIL");
printf("%s mat_sub\n", test_impl(mat_sub, mat_sub_cpu) ? "pass" : "FAIL");
printf("%s mat_mul\n", test_impl(mat_mul, mat_mul_cpu) ? "pass" : "FAIL");
// Performance timing tests
// cudaEvent stuff reference: http://choorucode.com/2011/04/28/cuda-timer/
cudaEventCreate(&ev0);
cudaEventCreate(&ev1);
perf_test("mat_add", mat_add);
perf_test("mat_sub", mat_sub);
perf_test("mat_mul", mat_mul);
cudaEventDestroy(ev0);
cudaEventDestroy(ev1);
return 0;
} | code for sm_80
Function : _Z7mat_mulPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002600 */
/*0020*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x4], R5 ; /* 0x0000010002027a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GT.AND P0, PT, R2, 0x5, PT ; /* 0x000000050200780c */
/* 0x000fe20003f04270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GT.OR P0, PT, R0, 0x5, P0 ; /* 0x000000050000780c */
/* 0x000fda0000704670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R16, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff107435 */
/* 0x000fe200000001ff */
/*00b0*/ LEA R7, R2, R2, 0x2 ; /* 0x0000000202077211 */
/* 0x000fe200078e10ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R4, R0, R16, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fc800078e0210 */
/*00e0*/ IMAD.WIDE R2, R7, R16, c[0x0][0x168] ; /* 0x00005a0007027625 */
/* 0x000fe200078e0210 */
/*00f0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040402087981 */
/* 0x000ee8000c1e1900 */
/*0120*/ LDG.E R11, [R4.64+0x14] ; /* 0x00001404040b7981 */
/* 0x000ee8000c1e1900 */
/*0130*/ LDG.E R13, [R4.64+0x28] ; /* 0x00002804040d7981 */
/* 0x000f28000c1e1900 */
/*0140*/ LDG.E R10, [R2.64+0x8] ; /* 0x00000804020a7981 */
/* 0x000f28000c1e1900 */
/*0150*/ LDG.E R15, [R4.64+0x3c] ; /* 0x00003c04040f7981 */
/* 0x000f68000c1e1900 */
/*0160*/ LDG.E R12, [R2.64+0xc] ; /* 0x00000c04020c7981 */
/* 0x000f68000c1e1900 */
/*0170*/ LDG.E R17, [R4.64+0x50] ; /* 0x0000500404117981 */
/* 0x000f68000c1e1900 */
/*0180*/ LDG.E R14, [R2.64+0x10] ; /* 0x00001004020e7981 */
/* 0x000f62000c1e1900 */
/*0190*/ IADD3 R7, R0, R7, RZ ; /* 0x0000000700077210 */
/* 0x000fe20007ffe0ff */
/*01a0*/ FFMA R6, R6, R9, RZ ; /* 0x0000000906067223 */
/* 0x004fc800000000ff */
/*01b0*/ FFMA R6, R11, R8, R6 ; /* 0x000000080b067223 */
/* 0x008fc80000000006 */
/*01c0*/ FFMA R6, R13, R10, R6 ; /* 0x0000000a0d067223 */
/* 0x010fc80000000006 */
/*01d0*/ FFMA R12, R15, R12, R6 ; /* 0x0000000c0f0c7223 */
/* 0x020fe40000000006 */
/*01e0*/ IMAD.WIDE R6, R7, R16, c[0x0][0x160] ; /* 0x0000580007067625 */
/* 0x000fc800078e0210 */
/*01f0*/ FFMA R17, R17, R14, R12 ; /* 0x0000000e11117223 */
/* 0x000fca000000000c */
/*0200*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x000fe2000c101904 */
/*0210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0220*/ BRA 0x220; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7mat_subPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GT.AND P0, PT, R3, 0x5, PT ; /* 0x000000050300780c */
/* 0x000fe20003f04270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GT.OR P0, PT, R0, 0x5, P0 ; /* 0x000000050000780c */
/* 0x000fda0000704670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R3, 0x5, R0 ; /* 0x0000000503007824 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x0c0fe400078e0207 */
/*00f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R6, R0, R7, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fc800078e0207 */
/*0120*/ FADD R9, -R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000100 */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7mat_addPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GT.AND P0, PT, R3, 0x5, PT ; /* 0x000000050300780c */
/* 0x000fe20003f04270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GT.OR P0, PT, R0, 0x5, P0 ; /* 0x000000050000780c */
/* 0x000fda0000704670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R3, 0x5, R0 ; /* 0x0000000503007824 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x0c0fe400078e0207 */
/*00f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R6, R0, R7, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fc800078e0207 */
/*0120*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cstdio>
#include <cmath>
#define DIM 5
#define COUNT (DIM * DIM)
cudaEvent_t ev0;
cudaEvent_t ev1;
/******** Helpers ************************************************************/
#define CHECK_ERROR(msg) (checkCUDAError((msg), __LINE__))
/// Check for CUDA errors. From Part1.
void checkCUDAError(const char *msg, int line)
{
cudaError_t err = cudaGetLastError();
if (cudaSuccess != err) {
fprintf(stderr, "line %d: CUDA error: %s - %s\n",
line, msg, cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
}
/******** GPU implementations ************************************************/
/// Add two matrices.
__global__ void mat_add(float *dst, float *A, float *B)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x > DIM || y > DIM) { return; }
int i = y * DIM + x;
dst[i] = A[i] + B[i];
}
/// Subtract two matrices.
__global__ void mat_sub(float *dst, float *A, float *B)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x > DIM || y > DIM) { return; }
int i = y * DIM + x;
dst[i] = A[i] - B[i];
}
/// Multiply two matrices.
__global__ void mat_mul(float *dst, float *A, float *B)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x > DIM || y > DIM) { return; }
int i = y * DIM + x;
float sum = 0;
for (int j = 0; j < DIM; ++j) {
float Aj = A[y * DIM + j];
float Bj = B[j * DIM + x];
sum += Aj * Bj;
}
dst[i] = sum;
}
/******** CPU implementations ************************************************/
void mat_add_cpu(float *dst, float *A, float *B)
{
for (int i = 0; i < COUNT; ++i) {
dst[i] = A[i] + B[i];
}
}
void mat_sub_cpu(float *dst, float *A, float *B)
{
for (int i = 0; i < COUNT; ++i) {
dst[i] = A[i] - B[i];
}
}
void mat_mul_cpu(float *dst, float *A, float *B)
{
for (int x = 0; x < DIM; ++x) {
for (int y = 0; y < DIM; ++y) {
float sum = 0;
for (int j = 0; j < DIM; ++j) {
float a = A[y * DIM + j];
float b = B[j * DIM + x];
sum += a * b;
}
dst[y * DIM + x] = sum;
}
}
}
/******** Main functions *****************************************************/
float *hst_A, *hst_C, *hst_D;
float *dev_A, *dev_C;
bool test_impl(
void (*gpu)(float *, float *, float *),
void (*cpu)(float *, float *, float *))
{
// Calculate grid/block sizes
dim3 dimGrid(1, 1);
dim3 dimBlock(DIM, DIM);
// Run on GPU
cudaMemcpy(dev_A, hst_A, COUNT * sizeof(*dev_A), cudaMemcpyHostToDevice);
CHECK_ERROR("memcpy");
(*gpu)<<<dimGrid, dimBlock>>>(dev_C, dev_A, dev_A);
CHECK_ERROR("function");
cudaMemcpy(hst_C, dev_C, COUNT * sizeof(*hst_C), cudaMemcpyDeviceToHost);
CHECK_ERROR("memcpy");
// Run on CPU
(*cpu)(hst_D, hst_A, hst_A);
// Check results
for (int i = 0; i < COUNT; ++i) {
if (hst_C[i] != hst_D[i]) {
return false;
}
}
return true;
}
float perf_test_one(dim3 grid, dim3 block, int iters,
void (*f)(float *, float *, float *))
{
// cudaEvent stuff reference: http://choorucode.com/2011/04/28/cuda-timer/
float t = 0;
for (int i = 0; i < iters; ++i) {
cudaEventRecord(ev0, 0);
(*f)<<<grid, block>>>(dev_C, dev_A, dev_A);
cudaEventRecord(ev1, 0);
cudaMemcpy(hst_C, dev_C, COUNT * sizeof(*hst_C), cudaMemcpyDeviceToHost);
cudaEventSynchronize(ev1);
float timeValue;
cudaEventElapsedTime(&timeValue, ev0, ev1);
t += timeValue;
}
return t;
}
void perf_test(const char *name, void (*f)(float *, float *, float *))
{
const int iters = 10000;
for (int g = 1; g <= DIM; ++g) {
for (int b = 1; b <= DIM; ++b) {
float t = perf_test_one(g, b, iters, f);
printf("%s %d %d %f\n", name, g, b, t);
}
}
}
int main()
{
// Allocate matrices
hst_A = (float *) malloc(COUNT * sizeof(*hst_A));
hst_C = (float *) malloc(COUNT * sizeof(*hst_C));
hst_D = (float *) malloc(COUNT * sizeof(*hst_D));
cudaMalloc(&dev_A, COUNT * sizeof(*dev_A));
cudaMalloc(&dev_C, COUNT * sizeof(*dev_C));
CHECK_ERROR("malloc");
// Initialize host/device matrices
for (int i = 0; i < COUNT; ++i) {
hst_A[i] = (float) i;
}
cudaMemcpy(dev_A, hst_A, COUNT * sizeof(*dev_A), cudaMemcpyHostToDevice);
// Test GPU implementations
printf("%s mat_add\n", test_impl(mat_add, mat_add_cpu) ? "pass" : "FAIL");
printf("%s mat_sub\n", test_impl(mat_sub, mat_sub_cpu) ? "pass" : "FAIL");
printf("%s mat_mul\n", test_impl(mat_mul, mat_mul_cpu) ? "pass" : "FAIL");
// Performance timing tests
// cudaEvent stuff reference: http://choorucode.com/2011/04/28/cuda-timer/
cudaEventCreate(&ev0);
cudaEventCreate(&ev1);
perf_test("mat_add", mat_add);
perf_test("mat_sub", mat_sub);
perf_test("mat_mul", mat_mul);
cudaEventDestroy(ev0);
cudaEventDestroy(ev1);
return 0;
} | .file "tmpxft_0017d47d_00000000-6_matrix_math.cudafe1.cpp"
.text
#APP
#NO_APP
.globl _Z11mat_add_cpuPfS_S_
.type _Z11mat_add_cpuPfS_S_, @function
_Z11mat_add_cpuPfS_S_:
.LFB2058:
.cfi_startproc
endbr64
movl $0, %eax
.L2:
movss (%rsi,%rax), %xmm0
addss (%rdx,%rax), %xmm0
movss %xmm0, (%rdi,%rax)
addq $4, %rax
cmpq $100, %rax
jne .L2
ret
.cfi_endproc
.LFE2058:
.size _Z11mat_add_cpuPfS_S_, .-_Z11mat_add_cpuPfS_S_
.globl _Z11mat_sub_cpuPfS_S_
.type _Z11mat_sub_cpuPfS_S_, @function
_Z11mat_sub_cpuPfS_S_:
.LFB2059:
.cfi_startproc
endbr64
movl $0, %eax
.L5:
movss (%rsi,%rax), %xmm0
subss (%rdx,%rax), %xmm0
movss %xmm0, (%rdi,%rax)
addq $4, %rax
cmpq $100, %rax
jne .L5
ret
.cfi_endproc
.LFE2059:
.size _Z11mat_sub_cpuPfS_S_, .-_Z11mat_sub_cpuPfS_S_
.globl _Z11mat_mul_cpuPfS_S_
.type _Z11mat_mul_cpuPfS_S_, @function
_Z11mat_mul_cpuPfS_S_:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rsi, %rbx
leaq 100(%rdx), %r8
movl $0, %esi
leaq 100(%rbx), %r11
.L8:
movq %rbx, %r9
movq %rdi, %r10
.L12:
movq %rdx, %rax
movq %r9, %rcx
pxor %xmm1, %xmm1
.L9:
movss (%rcx), %xmm0
mulss (%rax), %xmm0
addss %xmm0, %xmm1
addq $4, %rcx
addq $20, %rax
cmpq %r8, %rax
jne .L9
movss %xmm1, (%r10)
addq $20, %r10
addq $20, %r9
cmpq %r11, %r9
jne .L12
addl $1, %esi
addq $4, %rdx
addq $4, %r8
addq $4, %rdi
cmpl $5, %esi
jne .L8
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z11mat_mul_cpuPfS_S_, .-_Z11mat_mul_cpuPfS_S_
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2067:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2067:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "line %d: CUDA error: %s - %s\n"
.text
.globl _Z14checkCUDAErrorPKci
.type _Z14checkCUDAErrorPKci, @function
_Z14checkCUDAErrorPKci:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbp
movl %esi, %ebx
call cudaGetLastError@PLT
testl %eax, %eax
jne .L20
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movq %rbp, %r8
movl %ebx, %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z14checkCUDAErrorPKci, .-_Z14checkCUDAErrorPKci
.section .rodata.str1.1
.LC2:
.string "memcpy"
.LC3:
.string "function"
.text
.globl _Z9test_implPFvPfS_S_ES1_
.type _Z9test_implPFvPfS_S_ES1_, @function
_Z9test_implPFvPfS_S_ES1_:
.LFB2061:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movq %rsi, %rbx
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $5, 20(%rsp)
movl $5, 24(%rsp)
movl $1, 28(%rsp)
movl $1, %ecx
movl $100, %edx
movq hst_A(%rip), %rsi
movq dev_A(%rip), %rdi
call cudaMemcpy@PLT
movl $116, %esi
leaq .LC2(%rip), %rdi
call _Z14checkCUDAErrorPKci
movl 28(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movq 8(%rsp), %rdi
movl 16(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L22
movq dev_A(%rip), %rsi
movq %rsi, %rdx
movq dev_C(%rip), %rdi
call *%rbp
.L22:
movl $118, %esi
leaq .LC3(%rip), %rdi
call _Z14checkCUDAErrorPKci
movl $2, %ecx
movl $100, %edx
movq dev_C(%rip), %rsi
movq hst_C(%rip), %rdi
call cudaMemcpy@PLT
movl $120, %esi
leaq .LC2(%rip), %rdi
call _Z14checkCUDAErrorPKci
movq hst_A(%rip), %rsi
movq %rsi, %rdx
movq hst_D(%rip), %rdi
call *%rbx
movq hst_C(%rip), %rcx
movq hst_D(%rip), %rdx
movl $0, %eax
.L25:
movss (%rcx,%rax), %xmm0
ucomiss (%rdx,%rax), %xmm0
jp .L26
jne .L26
addq $4, %rax
cmpq $100, %rax
jne .L25
movl $1, %eax
jmp .L21
.L26:
movl $0, %eax
.L21:
addq $40, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z9test_implPFvPfS_S_ES1_, .-_Z9test_implPFvPfS_S_ES1_
.globl _Z13perf_test_one4dim3S_iPFvPfS0_S0_E
.type _Z13perf_test_one4dim3S_iPFvPfS0_S0_E, @function
_Z13perf_test_one4dim3S_iPFvPfS0_S0_E:
.LFB2062:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
movl %esi, 24(%rsp)
movq %rdx, (%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
testl %r8d, %r8d
jle .L35
movl %r8d, %r12d
movq %r9, %r14
movl $0, %ebx
movl $0x00000000, %ebp
leaq 36(%rsp), %r13
jmp .L33
.L32:
movl $0, %esi
movq ev1(%rip), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $100, %edx
movq dev_C(%rip), %rsi
movq hst_C(%rip), %rdi
call cudaMemcpy@PLT
movq ev1(%rip), %rdi
call cudaEventSynchronize@PLT
movq ev1(%rip), %rdx
movq ev0(%rip), %rsi
movq %r13, %rdi
call cudaEventElapsedTime@PLT
movd %ebp, %xmm1
addss 36(%rsp), %xmm1
movd %xmm1, %ebp
addl $1, %ebx
cmpl %ebx, %r12d
je .L30
.L33:
movl $0, %esi
movq ev0(%rip), %rdi
call cudaEventRecord@PLT
movl 8(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq (%rsp), %rdx
movq 16(%rsp), %rdi
movl 24(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L32
movq dev_A(%rip), %rsi
movq %rsi, %rdx
movq dev_C(%rip), %rdi
call *%r14
jmp .L32
.L35:
movl $0x00000000, %ebp
.L30:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L38
movd %ebp, %xmm0
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size _Z13perf_test_one4dim3S_iPFvPfS0_S0_E, .-_Z13perf_test_one4dim3S_iPFvPfS0_S0_E
.section .rodata.str1.1
.LC4:
.string "%s %d %d %f\n"
.text
.globl _Z9perf_testPKcPFvPfS1_S1_E
.type _Z9perf_testPKcPFvPfS1_S1_E, @function
_Z9perf_testPKcPFvPfS1_S1_E:
.LFB2063:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r13
movq %rsi, %r12
movl $1, %ebp
leaq .LC4(%rip), %r14
.L40:
movl $1, %ebx
.L41:
movl %ebx, 20(%rsp)
movl $1, 24(%rsp)
movl %ebp, 8(%rsp)
movl $1, 12(%rsp)
movq %r12, %r9
movl $10000, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call _Z13perf_test_one4dim3S_iPFvPfS0_S0_E
cvtss2sd %xmm0, %xmm0
movl %ebx, %r8d
movl %ebp, %ecx
movq %r13, %rdx
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl $6, %ebx
jne .L41
addl $1, %ebp
cmpl $6, %ebp
jne .L40
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _Z9perf_testPKcPFvPfS1_S1_E, .-_Z9perf_testPKcPFvPfS1_S1_E
.section .rodata.str1.1
.LC5:
.string "pass"
.LC6:
.string "FAIL"
.LC7:
.string "malloc"
.LC8:
.string "%s mat_add\n"
.LC9:
.string "%s mat_sub\n"
.LC10:
.string "%s mat_mul\n"
.LC11:
.string "mat_add"
.LC12:
.string "mat_sub"
.LC13:
.string "mat_mul"
.text
.globl main
.type main, @function
main:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $100, %edi
call malloc@PLT
movq %rax, hst_A(%rip)
movl $100, %edi
call malloc@PLT
movq %rax, hst_C(%rip)
movl $100, %edi
call malloc@PLT
movq %rax, hst_D(%rip)
movl $100, %esi
leaq dev_A(%rip), %rdi
call cudaMalloc@PLT
movl $100, %esi
leaq dev_C(%rip), %rdi
call cudaMalloc@PLT
movl $172, %esi
leaq .LC7(%rip), %rdi
call _Z14checkCUDAErrorPKci
movl $0, %eax
.L46:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movq hst_A(%rip), %rdx
movss %xmm0, (%rdx,%rax,4)
addq $1, %rax
cmpq $25, %rax
jne .L46
movl $1, %ecx
movl $100, %edx
movq hst_A(%rip), %rsi
movq dev_A(%rip), %rdi
call cudaMemcpy@PLT
leaq _Z11mat_add_cpuPfS_S_(%rip), %rsi
leaq _Z7mat_addPfS_S_(%rip), %rdi
call _Z9test_implPFvPfS_S_ES1_
testb %al, %al
leaq .LC6(%rip), %rdx
leaq .LC5(%rip), %rax
cmovne %rax, %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq _Z11mat_sub_cpuPfS_S_(%rip), %rsi
leaq _Z7mat_subPfS_S_(%rip), %rdi
call _Z9test_implPFvPfS_S_ES1_
testb %al, %al
leaq .LC6(%rip), %rdx
leaq .LC5(%rip), %rax
cmovne %rax, %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq _Z11mat_mul_cpuPfS_S_(%rip), %rsi
leaq _Z7mat_mulPfS_S_(%rip), %rdi
call _Z9test_implPFvPfS_S_ES1_
testb %al, %al
leaq .LC6(%rip), %rdx
leaq .LC5(%rip), %rax
cmovne %rax, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq ev0(%rip), %rdi
call cudaEventCreate@PLT
leaq ev1(%rip), %rdi
call cudaEventCreate@PLT
leaq _Z7mat_addPfS_S_(%rip), %rsi
leaq .LC11(%rip), %rdi
call _Z9perf_testPKcPFvPfS1_S1_E
leaq _Z7mat_subPfS_S_(%rip), %rsi
leaq .LC12(%rip), %rdi
call _Z9perf_testPKcPFvPfS1_S1_E
leaq _Z7mat_mulPfS_S_(%rip), %rsi
leaq .LC13(%rip), %rdi
call _Z9perf_testPKcPFvPfS1_S1_E
movq ev0(%rip), %rdi
call cudaEventDestroy@PLT
movq ev1(%rip), %rdi
call cudaEventDestroy@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size main, .-main
.globl _Z30__device_stub__Z7mat_addPfS_S_PfS_S_
.type _Z30__device_stub__Z7mat_addPfS_S_PfS_S_, @function
_Z30__device_stub__Z7mat_addPfS_S_PfS_S_:
.LFB2089:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L59
.L55:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L60
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L59:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7mat_addPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L55
.L60:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z30__device_stub__Z7mat_addPfS_S_PfS_S_, .-_Z30__device_stub__Z7mat_addPfS_S_PfS_S_
.globl _Z7mat_addPfS_S_
.type _Z7mat_addPfS_S_, @function
_Z7mat_addPfS_S_:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7mat_addPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z7mat_addPfS_S_, .-_Z7mat_addPfS_S_
.globl _Z30__device_stub__Z7mat_subPfS_S_PfS_S_
.type _Z30__device_stub__Z7mat_subPfS_S_PfS_S_, @function
_Z30__device_stub__Z7mat_subPfS_S_PfS_S_:
.LFB2091:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L67
.L63:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L68
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L67:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7mat_subPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L63
.L68:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2091:
.size _Z30__device_stub__Z7mat_subPfS_S_PfS_S_, .-_Z30__device_stub__Z7mat_subPfS_S_PfS_S_
.globl _Z7mat_subPfS_S_
.type _Z7mat_subPfS_S_, @function
_Z7mat_subPfS_S_:
.LFB2092:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7mat_subPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _Z7mat_subPfS_S_, .-_Z7mat_subPfS_S_
.globl _Z30__device_stub__Z7mat_mulPfS_S_PfS_S_
.type _Z30__device_stub__Z7mat_mulPfS_S_PfS_S_, @function
_Z30__device_stub__Z7mat_mulPfS_S_PfS_S_:
.LFB2093:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L75
.L71:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L76
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L75:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7mat_mulPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L71
.L76:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2093:
.size _Z30__device_stub__Z7mat_mulPfS_S_PfS_S_, .-_Z30__device_stub__Z7mat_mulPfS_S_PfS_S_
.globl _Z7mat_mulPfS_S_
.type _Z7mat_mulPfS_S_, @function
_Z7mat_mulPfS_S_:
.LFB2094:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7mat_mulPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2094:
.size _Z7mat_mulPfS_S_, .-_Z7mat_mulPfS_S_
.section .rodata.str1.1
.LC14:
.string "_Z7mat_mulPfS_S_"
.LC15:
.string "_Z7mat_subPfS_S_"
.LC16:
.string "_Z7mat_addPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2096:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z7mat_mulPfS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z7mat_subPfS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z7mat_addPfS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl dev_C
.bss
.align 8
.type dev_C, @object
.size dev_C, 8
dev_C:
.zero 8
.globl dev_A
.align 8
.type dev_A, @object
.size dev_A, 8
dev_A:
.zero 8
.globl hst_D
.align 8
.type hst_D, @object
.size hst_D, 8
hst_D:
.zero 8
.globl hst_C
.align 8
.type hst_C, @object
.size hst_C, 8
hst_C:
.zero 8
.globl hst_A
.align 8
.type hst_A, @object
.size hst_A, 8
hst_A:
.zero 8
.globl ev1
.align 8
.type ev1, @object
.size ev1, 8
ev1:
.zero 8
.globl ev0
.align 8
.type ev0, @object
.size ev0, 8
ev0:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cstdio>
#include <cmath>
#define DIM 5
#define COUNT (DIM * DIM)
cudaEvent_t ev0;
cudaEvent_t ev1;
/******** Helpers ************************************************************/
#define CHECK_ERROR(msg) (checkCUDAError((msg), __LINE__))
/// Check for CUDA errors. From Part1.
void checkCUDAError(const char *msg, int line)
{
cudaError_t err = cudaGetLastError();
if (cudaSuccess != err) {
fprintf(stderr, "line %d: CUDA error: %s - %s\n",
line, msg, cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
}
/******** GPU implementations ************************************************/
/// Add two matrices.
__global__ void mat_add(float *dst, float *A, float *B)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x > DIM || y > DIM) { return; }
int i = y * DIM + x;
dst[i] = A[i] + B[i];
}
/// Subtract two matrices.
__global__ void mat_sub(float *dst, float *A, float *B)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x > DIM || y > DIM) { return; }
int i = y * DIM + x;
dst[i] = A[i] - B[i];
}
/// Multiply two matrices.
__global__ void mat_mul(float *dst, float *A, float *B)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x > DIM || y > DIM) { return; }
int i = y * DIM + x;
float sum = 0;
for (int j = 0; j < DIM; ++j) {
float Aj = A[y * DIM + j];
float Bj = B[j * DIM + x];
sum += Aj * Bj;
}
dst[i] = sum;
}
/******** CPU implementations ************************************************/
void mat_add_cpu(float *dst, float *A, float *B)
{
for (int i = 0; i < COUNT; ++i) {
dst[i] = A[i] + B[i];
}
}
void mat_sub_cpu(float *dst, float *A, float *B)
{
for (int i = 0; i < COUNT; ++i) {
dst[i] = A[i] - B[i];
}
}
void mat_mul_cpu(float *dst, float *A, float *B)
{
for (int x = 0; x < DIM; ++x) {
for (int y = 0; y < DIM; ++y) {
float sum = 0;
for (int j = 0; j < DIM; ++j) {
float a = A[y * DIM + j];
float b = B[j * DIM + x];
sum += a * b;
}
dst[y * DIM + x] = sum;
}
}
}
/******** Main functions *****************************************************/
float *hst_A, *hst_C, *hst_D;
float *dev_A, *dev_C;
bool test_impl(
void (*gpu)(float *, float *, float *),
void (*cpu)(float *, float *, float *))
{
// Calculate grid/block sizes
dim3 dimGrid(1, 1);
dim3 dimBlock(DIM, DIM);
// Run on GPU
cudaMemcpy(dev_A, hst_A, COUNT * sizeof(*dev_A), cudaMemcpyHostToDevice);
CHECK_ERROR("memcpy");
(*gpu)<<<dimGrid, dimBlock>>>(dev_C, dev_A, dev_A);
CHECK_ERROR("function");
cudaMemcpy(hst_C, dev_C, COUNT * sizeof(*hst_C), cudaMemcpyDeviceToHost);
CHECK_ERROR("memcpy");
// Run on CPU
(*cpu)(hst_D, hst_A, hst_A);
// Check results
for (int i = 0; i < COUNT; ++i) {
if (hst_C[i] != hst_D[i]) {
return false;
}
}
return true;
}
float perf_test_one(dim3 grid, dim3 block, int iters,
void (*f)(float *, float *, float *))
{
// cudaEvent stuff reference: http://choorucode.com/2011/04/28/cuda-timer/
float t = 0;
for (int i = 0; i < iters; ++i) {
cudaEventRecord(ev0, 0);
(*f)<<<grid, block>>>(dev_C, dev_A, dev_A);
cudaEventRecord(ev1, 0);
cudaMemcpy(hst_C, dev_C, COUNT * sizeof(*hst_C), cudaMemcpyDeviceToHost);
cudaEventSynchronize(ev1);
float timeValue;
cudaEventElapsedTime(&timeValue, ev0, ev1);
t += timeValue;
}
return t;
}
void perf_test(const char *name, void (*f)(float *, float *, float *))
{
const int iters = 10000;
for (int g = 1; g <= DIM; ++g) {
for (int b = 1; b <= DIM; ++b) {
float t = perf_test_one(g, b, iters, f);
printf("%s %d %d %f\n", name, g, b, t);
}
}
}
int main()
{
// Allocate matrices
hst_A = (float *) malloc(COUNT * sizeof(*hst_A));
hst_C = (float *) malloc(COUNT * sizeof(*hst_C));
hst_D = (float *) malloc(COUNT * sizeof(*hst_D));
cudaMalloc(&dev_A, COUNT * sizeof(*dev_A));
cudaMalloc(&dev_C, COUNT * sizeof(*dev_C));
CHECK_ERROR("malloc");
// Initialize host/device matrices
for (int i = 0; i < COUNT; ++i) {
hst_A[i] = (float) i;
}
cudaMemcpy(dev_A, hst_A, COUNT * sizeof(*dev_A), cudaMemcpyHostToDevice);
// Test GPU implementations
printf("%s mat_add\n", test_impl(mat_add, mat_add_cpu) ? "pass" : "FAIL");
printf("%s mat_sub\n", test_impl(mat_sub, mat_sub_cpu) ? "pass" : "FAIL");
printf("%s mat_mul\n", test_impl(mat_mul, mat_mul_cpu) ? "pass" : "FAIL");
// Performance timing tests
// cudaEvent stuff reference: http://choorucode.com/2011/04/28/cuda-timer/
cudaEventCreate(&ev0);
cudaEventCreate(&ev1);
perf_test("mat_add", mat_add);
perf_test("mat_sub", mat_sub);
perf_test("mat_mul", mat_mul);
cudaEventDestroy(ev0);
cudaEventDestroy(ev1);
return 0;
} | #include <hip/hip_runtime.h>
#include <cstdio>
#include <cmath>
#define DIM 5
#define COUNT (DIM * DIM)
hipEvent_t ev0;
hipEvent_t ev1;
/******** Helpers ************************************************************/
#define CHECK_ERROR(msg) (checkCUDAError((msg), __LINE__))
/// Check for CUDA errors. From Part1.
void checkCUDAError(const char *msg, int line)
{
hipError_t err = hipGetLastError();
if (hipSuccess != err) {
fprintf(stderr, "line %d: CUDA error: %s - %s\n",
line, msg, hipGetErrorString(err));
exit(EXIT_FAILURE);
}
}
/******** GPU implementations ************************************************/
/// Add two matrices.
__global__ void mat_add(float *dst, float *A, float *B)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x > DIM || y > DIM) { return; }
int i = y * DIM + x;
dst[i] = A[i] + B[i];
}
/// Subtract two matrices.
__global__ void mat_sub(float *dst, float *A, float *B)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x > DIM || y > DIM) { return; }
int i = y * DIM + x;
dst[i] = A[i] - B[i];
}
/// Multiply two matrices.
__global__ void mat_mul(float *dst, float *A, float *B)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x > DIM || y > DIM) { return; }
int i = y * DIM + x;
float sum = 0;
for (int j = 0; j < DIM; ++j) {
float Aj = A[y * DIM + j];
float Bj = B[j * DIM + x];
sum += Aj * Bj;
}
dst[i] = sum;
}
/******** CPU implementations ************************************************/
void mat_add_cpu(float *dst, float *A, float *B)
{
for (int i = 0; i < COUNT; ++i) {
dst[i] = A[i] + B[i];
}
}
void mat_sub_cpu(float *dst, float *A, float *B)
{
for (int i = 0; i < COUNT; ++i) {
dst[i] = A[i] - B[i];
}
}
void mat_mul_cpu(float *dst, float *A, float *B)
{
for (int x = 0; x < DIM; ++x) {
for (int y = 0; y < DIM; ++y) {
float sum = 0;
for (int j = 0; j < DIM; ++j) {
float a = A[y * DIM + j];
float b = B[j * DIM + x];
sum += a * b;
}
dst[y * DIM + x] = sum;
}
}
}
/******** Main functions *****************************************************/
float *hst_A, *hst_C, *hst_D;
float *dev_A, *dev_C;
bool test_impl(
void (*gpu)(float *, float *, float *),
void (*cpu)(float *, float *, float *))
{
// Calculate grid/block sizes
dim3 dimGrid(1, 1);
dim3 dimBlock(DIM, DIM);
// Run on GPU
hipMemcpy(dev_A, hst_A, COUNT * sizeof(*dev_A), hipMemcpyHostToDevice);
CHECK_ERROR("memcpy");
(*gpu)<<<dimGrid, dimBlock>>>(dev_C, dev_A, dev_A);
CHECK_ERROR("function");
hipMemcpy(hst_C, dev_C, COUNT * sizeof(*hst_C), hipMemcpyDeviceToHost);
CHECK_ERROR("memcpy");
// Run on CPU
(*cpu)(hst_D, hst_A, hst_A);
// Check results
for (int i = 0; i < COUNT; ++i) {
if (hst_C[i] != hst_D[i]) {
return false;
}
}
return true;
}
float perf_test_one(dim3 grid, dim3 block, int iters,
void (*f)(float *, float *, float *))
{
// cudaEvent stuff reference: http://choorucode.com/2011/04/28/cuda-timer/
float t = 0;
for (int i = 0; i < iters; ++i) {
hipEventRecord(ev0, 0);
(*f)<<<grid, block>>>(dev_C, dev_A, dev_A);
hipEventRecord(ev1, 0);
hipMemcpy(hst_C, dev_C, COUNT * sizeof(*hst_C), hipMemcpyDeviceToHost);
hipEventSynchronize(ev1);
float timeValue;
hipEventElapsedTime(&timeValue, ev0, ev1);
t += timeValue;
}
return t;
}
void perf_test(const char *name, void (*f)(float *, float *, float *))
{
const int iters = 10000;
for (int g = 1; g <= DIM; ++g) {
for (int b = 1; b <= DIM; ++b) {
float t = perf_test_one(g, b, iters, f);
printf("%s %d %d %f\n", name, g, b, t);
}
}
}
int main()
{
// Allocate matrices
hst_A = (float *) malloc(COUNT * sizeof(*hst_A));
hst_C = (float *) malloc(COUNT * sizeof(*hst_C));
hst_D = (float *) malloc(COUNT * sizeof(*hst_D));
hipMalloc(&dev_A, COUNT * sizeof(*dev_A));
hipMalloc(&dev_C, COUNT * sizeof(*dev_C));
CHECK_ERROR("malloc");
// Initialize host/device matrices
for (int i = 0; i < COUNT; ++i) {
hst_A[i] = (float) i;
}
hipMemcpy(dev_A, hst_A, COUNT * sizeof(*dev_A), hipMemcpyHostToDevice);
// Test GPU implementations
printf("%s mat_add\n", test_impl(mat_add, mat_add_cpu) ? "pass" : "FAIL");
printf("%s mat_sub\n", test_impl(mat_sub, mat_sub_cpu) ? "pass" : "FAIL");
printf("%s mat_mul\n", test_impl(mat_mul, mat_mul_cpu) ? "pass" : "FAIL");
// Performance timing tests
// cudaEvent stuff reference: http://choorucode.com/2011/04/28/cuda-timer/
hipEventCreate(&ev0);
hipEventCreate(&ev1);
perf_test("mat_add", mat_add);
perf_test("mat_sub", mat_sub);
perf_test("mat_mul", mat_mul);
hipEventDestroy(ev0);
hipEventDestroy(ev1);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
#include <cmath>
#define DIM 5
#define COUNT (DIM * DIM)
hipEvent_t ev0;
hipEvent_t ev1;
/******** Helpers ************************************************************/
#define CHECK_ERROR(msg) (checkCUDAError((msg), __LINE__))
/// Check for CUDA errors. From Part1.
void checkCUDAError(const char *msg, int line)
{
hipError_t err = hipGetLastError();
if (hipSuccess != err) {
fprintf(stderr, "line %d: CUDA error: %s - %s\n",
line, msg, hipGetErrorString(err));
exit(EXIT_FAILURE);
}
}
/******** GPU implementations ************************************************/
/// Add two matrices.
__global__ void mat_add(float *dst, float *A, float *B)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x > DIM || y > DIM) { return; }
int i = y * DIM + x;
dst[i] = A[i] + B[i];
}
/// Subtract two matrices.
__global__ void mat_sub(float *dst, float *A, float *B)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x > DIM || y > DIM) { return; }
int i = y * DIM + x;
dst[i] = A[i] - B[i];
}
/// Multiply two matrices.
__global__ void mat_mul(float *dst, float *A, float *B)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x > DIM || y > DIM) { return; }
int i = y * DIM + x;
float sum = 0;
for (int j = 0; j < DIM; ++j) {
float Aj = A[y * DIM + j];
float Bj = B[j * DIM + x];
sum += Aj * Bj;
}
dst[i] = sum;
}
/******** CPU implementations ************************************************/
void mat_add_cpu(float *dst, float *A, float *B)
{
for (int i = 0; i < COUNT; ++i) {
dst[i] = A[i] + B[i];
}
}
void mat_sub_cpu(float *dst, float *A, float *B)
{
for (int i = 0; i < COUNT; ++i) {
dst[i] = A[i] - B[i];
}
}
void mat_mul_cpu(float *dst, float *A, float *B)
{
for (int x = 0; x < DIM; ++x) {
for (int y = 0; y < DIM; ++y) {
float sum = 0;
for (int j = 0; j < DIM; ++j) {
float a = A[y * DIM + j];
float b = B[j * DIM + x];
sum += a * b;
}
dst[y * DIM + x] = sum;
}
}
}
/******** Main functions *****************************************************/
float *hst_A, *hst_C, *hst_D;
float *dev_A, *dev_C;
bool test_impl(
void (*gpu)(float *, float *, float *),
void (*cpu)(float *, float *, float *))
{
// Calculate grid/block sizes
dim3 dimGrid(1, 1);
dim3 dimBlock(DIM, DIM);
// Run on GPU
hipMemcpy(dev_A, hst_A, COUNT * sizeof(*dev_A), hipMemcpyHostToDevice);
CHECK_ERROR("memcpy");
(*gpu)<<<dimGrid, dimBlock>>>(dev_C, dev_A, dev_A);
CHECK_ERROR("function");
hipMemcpy(hst_C, dev_C, COUNT * sizeof(*hst_C), hipMemcpyDeviceToHost);
CHECK_ERROR("memcpy");
// Run on CPU
(*cpu)(hst_D, hst_A, hst_A);
// Check results
for (int i = 0; i < COUNT; ++i) {
if (hst_C[i] != hst_D[i]) {
return false;
}
}
return true;
}
float perf_test_one(dim3 grid, dim3 block, int iters,
void (*f)(float *, float *, float *))
{
// cudaEvent stuff reference: http://choorucode.com/2011/04/28/cuda-timer/
float t = 0;
for (int i = 0; i < iters; ++i) {
hipEventRecord(ev0, 0);
(*f)<<<grid, block>>>(dev_C, dev_A, dev_A);
hipEventRecord(ev1, 0);
hipMemcpy(hst_C, dev_C, COUNT * sizeof(*hst_C), hipMemcpyDeviceToHost);
hipEventSynchronize(ev1);
float timeValue;
hipEventElapsedTime(&timeValue, ev0, ev1);
t += timeValue;
}
return t;
}
void perf_test(const char *name, void (*f)(float *, float *, float *))
{
const int iters = 10000;
for (int g = 1; g <= DIM; ++g) {
for (int b = 1; b <= DIM; ++b) {
float t = perf_test_one(g, b, iters, f);
printf("%s %d %d %f\n", name, g, b, t);
}
}
}
int main()
{
// Allocate matrices
hst_A = (float *) malloc(COUNT * sizeof(*hst_A));
hst_C = (float *) malloc(COUNT * sizeof(*hst_C));
hst_D = (float *) malloc(COUNT * sizeof(*hst_D));
hipMalloc(&dev_A, COUNT * sizeof(*dev_A));
hipMalloc(&dev_C, COUNT * sizeof(*dev_C));
CHECK_ERROR("malloc");
// Initialize host/device matrices
for (int i = 0; i < COUNT; ++i) {
hst_A[i] = (float) i;
}
hipMemcpy(dev_A, hst_A, COUNT * sizeof(*dev_A), hipMemcpyHostToDevice);
// Test GPU implementations
printf("%s mat_add\n", test_impl(mat_add, mat_add_cpu) ? "pass" : "FAIL");
printf("%s mat_sub\n", test_impl(mat_sub, mat_sub_cpu) ? "pass" : "FAIL");
printf("%s mat_mul\n", test_impl(mat_mul, mat_mul_cpu) ? "pass" : "FAIL");
// Performance timing tests
// cudaEvent stuff reference: http://choorucode.com/2011/04/28/cuda-timer/
hipEventCreate(&ev0);
hipEventCreate(&ev1);
perf_test("mat_add", mat_add);
perf_test("mat_sub", mat_sub);
perf_test("mat_mul", mat_mul);
hipEventDestroy(ev0);
hipEventDestroy(ev1);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7mat_addPfS_S_
.globl _Z7mat_addPfS_S_
.p2align 8
.type _Z7mat_addPfS_S_,@function
_Z7mat_addPfS_S_:
s_load_b32 s2, s[0:1], 0x24
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 6, v2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, 5, v[0:1]
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7mat_addPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7mat_addPfS_S_, .Lfunc_end0-_Z7mat_addPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7mat_subPfS_S_
.globl _Z7mat_subPfS_S_
.p2align 8
.type _Z7mat_subPfS_S_,@function
_Z7mat_subPfS_S_:
s_load_b32 s2, s[0:1], 0x24
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 6, v2
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, 5, v[0:1]
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_sub_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7mat_subPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7mat_subPfS_S_, .Lfunc_end1-_Z7mat_subPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7mat_mulPfS_S_
.globl _Z7mat_mulPfS_S_
.p2align 8
.type _Z7mat_mulPfS_S_,@function
_Z7mat_mulPfS_S_:
s_load_b32 s2, s[0:1], 0x24
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 6, v2
s_cbranch_execz .LBB2_4
s_load_b128 s[4:7], s[0:1], 0x8
v_lshl_add_u32 v1, v1, 2, v1
v_mov_b32_e32 v4, 0
s_mov_b32 s2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB2_2:
v_add_nc_u32_e32 v5, s2, v0
s_add_i32 s2, s2, 5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s2, 25
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v5, vcc_lo, s6, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
global_load_b32 v7, v[2:3], off
global_load_b32 v5, v[5:6], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v4, v7, v5
s_cbranch_scc0 .LBB2_2
s_load_b64 s[0:1], s[0:1], 0x0
v_add_nc_u32_e32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB2_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7mat_mulPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z7mat_mulPfS_S_, .Lfunc_end2-_Z7mat_mulPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7mat_addPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7mat_addPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7mat_subPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7mat_subPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7mat_mulPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7mat_mulPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
#include <cmath>
#define DIM 5
#define COUNT (DIM * DIM)
hipEvent_t ev0;
hipEvent_t ev1;
/******** Helpers ************************************************************/
#define CHECK_ERROR(msg) (checkCUDAError((msg), __LINE__))
/// Check for CUDA errors. From Part1.
void checkCUDAError(const char *msg, int line)
{
hipError_t err = hipGetLastError();
if (hipSuccess != err) {
fprintf(stderr, "line %d: CUDA error: %s - %s\n",
line, msg, hipGetErrorString(err));
exit(EXIT_FAILURE);
}
}
/******** GPU implementations ************************************************/
/// Add two matrices.
__global__ void mat_add(float *dst, float *A, float *B)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x > DIM || y > DIM) { return; }
int i = y * DIM + x;
dst[i] = A[i] + B[i];
}
/// Subtract two matrices.
__global__ void mat_sub(float *dst, float *A, float *B)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x > DIM || y > DIM) { return; }
int i = y * DIM + x;
dst[i] = A[i] - B[i];
}
/// Multiply two matrices.
__global__ void mat_mul(float *dst, float *A, float *B)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x > DIM || y > DIM) { return; }
int i = y * DIM + x;
float sum = 0;
for (int j = 0; j < DIM; ++j) {
float Aj = A[y * DIM + j];
float Bj = B[j * DIM + x];
sum += Aj * Bj;
}
dst[i] = sum;
}
/******** CPU implementations ************************************************/
void mat_add_cpu(float *dst, float *A, float *B)
{
for (int i = 0; i < COUNT; ++i) {
dst[i] = A[i] + B[i];
}
}
void mat_sub_cpu(float *dst, float *A, float *B)
{
for (int i = 0; i < COUNT; ++i) {
dst[i] = A[i] - B[i];
}
}
void mat_mul_cpu(float *dst, float *A, float *B)
{
for (int x = 0; x < DIM; ++x) {
for (int y = 0; y < DIM; ++y) {
float sum = 0;
for (int j = 0; j < DIM; ++j) {
float a = A[y * DIM + j];
float b = B[j * DIM + x];
sum += a * b;
}
dst[y * DIM + x] = sum;
}
}
}
/******** Main functions *****************************************************/
float *hst_A, *hst_C, *hst_D;
float *dev_A, *dev_C;
bool test_impl(
void (*gpu)(float *, float *, float *),
void (*cpu)(float *, float *, float *))
{
// Calculate grid/block sizes
dim3 dimGrid(1, 1);
dim3 dimBlock(DIM, DIM);
// Run on GPU
hipMemcpy(dev_A, hst_A, COUNT * sizeof(*dev_A), hipMemcpyHostToDevice);
CHECK_ERROR("memcpy");
(*gpu)<<<dimGrid, dimBlock>>>(dev_C, dev_A, dev_A);
CHECK_ERROR("function");
hipMemcpy(hst_C, dev_C, COUNT * sizeof(*hst_C), hipMemcpyDeviceToHost);
CHECK_ERROR("memcpy");
// Run on CPU
(*cpu)(hst_D, hst_A, hst_A);
// Check results
for (int i = 0; i < COUNT; ++i) {
if (hst_C[i] != hst_D[i]) {
return false;
}
}
return true;
}
float perf_test_one(dim3 grid, dim3 block, int iters,
void (*f)(float *, float *, float *))
{
// cudaEvent stuff reference: http://choorucode.com/2011/04/28/cuda-timer/
float t = 0;
for (int i = 0; i < iters; ++i) {
hipEventRecord(ev0, 0);
(*f)<<<grid, block>>>(dev_C, dev_A, dev_A);
hipEventRecord(ev1, 0);
hipMemcpy(hst_C, dev_C, COUNT * sizeof(*hst_C), hipMemcpyDeviceToHost);
hipEventSynchronize(ev1);
float timeValue;
hipEventElapsedTime(&timeValue, ev0, ev1);
t += timeValue;
}
return t;
}
void perf_test(const char *name, void (*f)(float *, float *, float *))
{
const int iters = 10000;
for (int g = 1; g <= DIM; ++g) {
for (int b = 1; b <= DIM; ++b) {
float t = perf_test_one(g, b, iters, f);
printf("%s %d %d %f\n", name, g, b, t);
}
}
}
int main()
{
// Allocate matrices
hst_A = (float *) malloc(COUNT * sizeof(*hst_A));
hst_C = (float *) malloc(COUNT * sizeof(*hst_C));
hst_D = (float *) malloc(COUNT * sizeof(*hst_D));
hipMalloc(&dev_A, COUNT * sizeof(*dev_A));
hipMalloc(&dev_C, COUNT * sizeof(*dev_C));
CHECK_ERROR("malloc");
// Initialize host/device matrices
for (int i = 0; i < COUNT; ++i) {
hst_A[i] = (float) i;
}
hipMemcpy(dev_A, hst_A, COUNT * sizeof(*dev_A), hipMemcpyHostToDevice);
// Test GPU implementations
printf("%s mat_add\n", test_impl(mat_add, mat_add_cpu) ? "pass" : "FAIL");
printf("%s mat_sub\n", test_impl(mat_sub, mat_sub_cpu) ? "pass" : "FAIL");
printf("%s mat_mul\n", test_impl(mat_mul, mat_mul_cpu) ? "pass" : "FAIL");
// Performance timing tests
// cudaEvent stuff reference: http://choorucode.com/2011/04/28/cuda-timer/
hipEventCreate(&ev0);
hipEventCreate(&ev1);
perf_test("mat_add", mat_add);
perf_test("mat_sub", mat_sub);
perf_test("mat_mul", mat_mul);
hipEventDestroy(ev0);
hipEventDestroy(ev1);
return 0;
} | .text
.file "matrix_math.hip"
.globl _Z14checkCUDAErrorPKci # -- Begin function _Z14checkCUDAErrorPKci
.p2align 4, 0x90
.type _Z14checkCUDAErrorPKci,@function
_Z14checkCUDAErrorPKci: # @_Z14checkCUDAErrorPKci
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
callq hipGetLastError
testl %eax, %eax
jne .LBB0_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 32
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movq %r14, %rdi
movl %ebp, %edx
movq %rbx, %rcx
movq %rax, %r8
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z14checkCUDAErrorPKci, .Lfunc_end0-_Z14checkCUDAErrorPKci
.cfi_endproc
# -- End function
.globl _Z22__device_stub__mat_addPfS_S_ # -- Begin function _Z22__device_stub__mat_addPfS_S_
.p2align 4, 0x90
.type _Z22__device_stub__mat_addPfS_S_,@function
_Z22__device_stub__mat_addPfS_S_: # @_Z22__device_stub__mat_addPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7mat_addPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z22__device_stub__mat_addPfS_S_, .Lfunc_end1-_Z22__device_stub__mat_addPfS_S_
.cfi_endproc
# -- End function
.globl _Z22__device_stub__mat_subPfS_S_ # -- Begin function _Z22__device_stub__mat_subPfS_S_
.p2align 4, 0x90
.type _Z22__device_stub__mat_subPfS_S_,@function
_Z22__device_stub__mat_subPfS_S_: # @_Z22__device_stub__mat_subPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7mat_subPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z22__device_stub__mat_subPfS_S_, .Lfunc_end2-_Z22__device_stub__mat_subPfS_S_
.cfi_endproc
# -- End function
.globl _Z22__device_stub__mat_mulPfS_S_ # -- Begin function _Z22__device_stub__mat_mulPfS_S_
.p2align 4, 0x90
.type _Z22__device_stub__mat_mulPfS_S_,@function
_Z22__device_stub__mat_mulPfS_S_: # @_Z22__device_stub__mat_mulPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7mat_mulPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z22__device_stub__mat_mulPfS_S_, .Lfunc_end3-_Z22__device_stub__mat_mulPfS_S_
.cfi_endproc
# -- End function
.globl _Z11mat_add_cpuPfS_S_ # -- Begin function _Z11mat_add_cpuPfS_S_
.p2align 4, 0x90
.type _Z11mat_add_cpuPfS_S_,@function
_Z11mat_add_cpuPfS_S_: # @_Z11mat_add_cpuPfS_S_
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_1: # =>This Inner Loop Header: Depth=1
movss (%rsi,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rdx,%rax,4), %xmm0
movss %xmm0, (%rdi,%rax,4)
incq %rax
cmpq $25, %rax
jne .LBB4_1
# %bb.2:
retq
.Lfunc_end4:
.size _Z11mat_add_cpuPfS_S_, .Lfunc_end4-_Z11mat_add_cpuPfS_S_
.cfi_endproc
# -- End function
.globl _Z11mat_sub_cpuPfS_S_ # -- Begin function _Z11mat_sub_cpuPfS_S_
.p2align 4, 0x90
.type _Z11mat_sub_cpuPfS_S_,@function
_Z11mat_sub_cpuPfS_S_: # @_Z11mat_sub_cpuPfS_S_
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB5_1: # =>This Inner Loop Header: Depth=1
movss (%rsi,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss (%rdx,%rax,4), %xmm0
movss %xmm0, (%rdi,%rax,4)
incq %rax
cmpq $25, %rax
jne .LBB5_1
# %bb.2:
retq
.Lfunc_end5:
.size _Z11mat_sub_cpuPfS_S_, .Lfunc_end5-_Z11mat_sub_cpuPfS_S_
.cfi_endproc
# -- End function
.globl _Z11mat_mul_cpuPfS_S_ # -- Begin function _Z11mat_mul_cpuPfS_S_
.p2align 4, 0x90
.type _Z11mat_mul_cpuPfS_S_,@function
_Z11mat_mul_cpuPfS_S_: # @_Z11mat_mul_cpuPfS_S_
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB6_1: # %.preheader21
# =>This Loop Header: Depth=1
# Child Loop BB6_2 Depth 2
# Child Loop BB6_3 Depth 3
leaq (%rdi,%rax,4), %rcx
movq %rsi, %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB6_2: # %.preheader
# Parent Loop BB6_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB6_3 Depth 3
xorps %xmm0, %xmm0
movq %rdx, %r10
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB6_3: # Parent Loop BB6_1 Depth=1
# Parent Loop BB6_2 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r8,%r11,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r10), %xmm1
addss %xmm1, %xmm0
incq %r11
addq $20, %r10
cmpq $5, %r11
jne .LBB6_3
# %bb.4: # in Loop: Header=BB6_2 Depth=2
leaq (%r9,%r9,4), %r10
movss %xmm0, (%rcx,%r10,4)
incq %r9
addq $20, %r8
cmpq $5, %r9
jne .LBB6_2
# %bb.5: # in Loop: Header=BB6_1 Depth=1
incq %rax
addq $4, %rdx
cmpq $5, %rax
jne .LBB6_1
# %bb.6:
retq
.Lfunc_end6:
.size _Z11mat_mul_cpuPfS_S_, .Lfunc_end6-_Z11mat_mul_cpuPfS_S_
.cfi_endproc
# -- End function
.globl _Z9test_implPFvPfS_S_ES1_ # -- Begin function _Z9test_implPFvPfS_S_ES1_
.p2align 4, 0x90
.type _Z9test_implPFvPfS_S_ES1_,@function
_Z9test_implPFvPfS_S_ES1_: # @_Z9test_implPFvPfS_S_ES1_
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %rbx
movq %rdi, %r14
movq dev_A(%rip), %rdi
movq hst_A(%rip), %rsi
movl $100, %edx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB7_1
# %bb.3: # %_Z14checkCUDAErrorPKci.exit
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $21474836485, %rdx # imm = 0x500000005
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_5
# %bb.4:
movq dev_C(%rip), %rdi
movq dev_A(%rip), %rdx
movq %rdx, %rsi
callq *(%r14)
.LBB7_5:
callq hipGetLastError
testl %eax, %eax
jne .LBB7_6
# %bb.7: # %_Z14checkCUDAErrorPKci.exit16
movq hst_C(%rip), %rdi
movq dev_C(%rip), %rsi
movl $100, %edx
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB7_8
# %bb.9: # %_Z14checkCUDAErrorPKci.exit18
movq hst_D(%rip), %rdi
movq hst_A(%rip), %rdx
movq %rdx, %rsi
callq *%rbx
movq hst_C(%rip), %rax
movq hst_D(%rip), %rcx
movss (%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss (%rcx), %xmm0
jne .LBB7_10
jnp .LBB7_11
.LBB7_10:
xorl %eax, %eax
jmp .LBB7_15
.LBB7_11: # %.lr.ph.preheader
xorl %esi, %esi
.p2align 4, 0x90
.LBB7_12: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %rsi, %rdx
cmpq $24, %rsi
je .LBB7_14
# %bb.13: # in Loop: Header=BB7_12 Depth=1
movss 4(%rax,%rdx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
leaq 1(%rdx), %rsi
ucomiss 4(%rcx,%rdx,4), %xmm0
jne .LBB7_14
jnp .LBB7_12
.LBB7_14: # %.critedge.loopexit
cmpq $24, %rdx
setae %al
.LBB7_15: # %.critedge
# kill: def $al killed $al killed $eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB7_1:
.cfi_def_cfa_offset 32
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movl $118, %edx
jmp .LBB7_2
.LBB7_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movl $120, %edx
jmp .LBB7_2
.LBB7_8:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movl $122, %edx
.LBB7_2:
movq %rax, %r8
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end7:
.size _Z9test_implPFvPfS_S_ES1_, .Lfunc_end7-_Z9test_implPFvPfS_S_ES1_
.cfi_endproc
# -- End function
.globl _Z13perf_test_one4dim3S_iPFvPfS0_S0_E # -- Begin function _Z13perf_test_one4dim3S_iPFvPfS0_S0_E
.p2align 4, 0x90
.type _Z13perf_test_one4dim3S_iPFvPfS0_S0_E,@function
_Z13perf_test_one4dim3S_iPFvPfS0_S0_E: # @_Z13perf_test_one4dim3S_iPFvPfS0_S0_E
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, 16(%rsp) # 8-byte Spill
testl %r8d, %r8d
jle .LBB8_1
# %bb.3: # %.lr.ph.preheader
movl %r8d, %ebp
movl %ecx, %r14d
movq %rdx, %r15
movl %esi, %r12d
movq %rdi, %r13
xorps %xmm0, %xmm0
leaq 12(%rsp), %rbx
jmp .LBB8_4
.p2align 4, 0x90
.LBB8_6: # in Loop: Header=BB8_4 Depth=1
movq ev1(%rip), %rdi
xorl %esi, %esi
callq hipEventRecord
movq hst_C(%rip), %rdi
movq dev_C(%rip), %rsi
movl $100, %edx
movl $2, %ecx
callq hipMemcpy
movq ev1(%rip), %rdi
callq hipEventSynchronize
movq ev0(%rip), %rsi
movq ev1(%rip), %rdx
movq %rbx, %rdi
callq hipEventElapsedTime
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
addss 12(%rsp), %xmm0
decl %ebp
je .LBB8_2
.LBB8_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss %xmm0, 8(%rsp) # 4-byte Spill
movq ev0(%rip), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r13, %rdi
movl %r12d, %esi
movq %r15, %rdx
movl %r14d, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB8_6
# %bb.5: # in Loop: Header=BB8_4 Depth=1
movq dev_C(%rip), %rdi
movq dev_A(%rip), %rdx
movq %rdx, %rsi
movq 16(%rsp), %rax # 8-byte Reload
callq *(%rax)
jmp .LBB8_6
.LBB8_1:
xorps %xmm0, %xmm0
.LBB8_2: # %._crit_edge
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size _Z13perf_test_one4dim3S_iPFvPfS0_S0_E, .Lfunc_end8-_Z13perf_test_one4dim3S_iPFvPfS0_S0_E
.cfi_endproc
# -- End function
.globl _Z9perf_testPKcPFvPfS1_S1_E # -- Begin function _Z9perf_testPKcPFvPfS1_S1_E
.p2align 4, 0x90
.type _Z9perf_testPKcPFvPfS1_S1_E,@function
_Z9perf_testPKcPFvPfS1_S1_E: # @_Z9perf_testPKcPFvPfS1_S1_E
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq %rdi, %r14
movl $1, %r15d
movabsq $4294967296, %rbp # imm = 0x100000000
.p2align 4, 0x90
.LBB9_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB9_2 Depth 2
movq %r15, %r12
orq %rbp, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB9_2: # Parent Loop BB9_1 Depth=1
# => This Inner Loop Header: Depth=2
leaq 1(,%rbp), %rdx
addq %r13, %rdx
movq %r12, %rdi
movl $1, %esi
movl $1, %ecx
movl $10000, %r8d # imm = 0x2710
movq %rbx, %r9
callq _Z13perf_test_one4dim3S_iPFvPfS0_S0_E
cvtss2sd %xmm0, %xmm0
incq %r13
movl $.L.str.3, %edi
movq %r14, %rsi
movl %r15d, %edx
movl %r13d, %ecx
movb $1, %al
callq printf
cmpq $5, %r13
jne .LBB9_2
# %bb.3: # in Loop: Header=BB9_1 Depth=1
incq %r15
cmpq $6, %r15
jne .LBB9_1
# %bb.4:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end9:
.size _Z9perf_testPKcPFvPfS1_S1_E, .Lfunc_end9-_Z9perf_testPKcPFvPfS1_S1_E
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $100, %edi
callq malloc
movq %rax, hst_A(%rip)
movl $100, %edi
callq malloc
movq %rax, hst_C(%rip)
movl $100, %edi
callq malloc
movq %rax, hst_D(%rip)
movl $dev_A, %edi
movl $100, %esi
callq hipMalloc
movl $dev_C, %edi
movl $100, %esi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB10_16
# %bb.1: # %_Z14checkCUDAErrorPKci.exit.preheader
movq hst_A(%rip), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB10_2: # %_Z14checkCUDAErrorPKci.exit
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $25, %rcx
jne .LBB10_2
# %bb.3:
movabsq $4294967296, %r12 # imm = 0x100000000
movq dev_A(%rip), %rdi
movq hst_A(%rip), %rsi
movl $100, %edx
movl $1, %ecx
callq hipMemcpy
movl $_Z7mat_addPfS_S_, %edi
movl $_Z11mat_add_cpuPfS_S_, %esi
callq _Z9test_implPFvPfS_S_ES1_
movl $.L.str.6, %r14d
movl $.L.str.7, %ebx
testb %al, %al
movl $.L.str.7, %esi
cmovneq %r14, %rsi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl $_Z7mat_subPfS_S_, %edi
movl $_Z11mat_sub_cpuPfS_S_, %esi
callq _Z9test_implPFvPfS_S_ES1_
testb %al, %al
movl $.L.str.7, %esi
cmovneq %r14, %rsi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movl $_Z7mat_mulPfS_S_, %edi
movl $_Z11mat_mul_cpuPfS_S_, %esi
callq _Z9test_implPFvPfS_S_ES1_
testb %al, %al
cmovneq %r14, %rbx
movl $.L.str.9, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl $ev0, %edi
callq hipEventCreate
movl $ev1, %edi
callq hipEventCreate
movl $1, %ebx
.p2align 4, 0x90
.LBB10_4: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB10_5 Depth 2
movq %rbx, %r14
orq %r12, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB10_5: # Parent Loop BB10_4 Depth=1
# => This Inner Loop Header: Depth=2
leaq (%r15,%r12), %rdx
incq %rdx
movl $_Z7mat_addPfS_S_, %r9d
movq %r14, %rdi
movl $1, %esi
movl $1, %ecx
movl $10000, %r8d # imm = 0x2710
callq _Z13perf_test_one4dim3S_iPFvPfS0_S0_E
cvtss2sd %xmm0, %xmm0
incq %r15
movl $.L.str.3, %edi
movl $.L.str.10, %esi
movl %ebx, %edx
movl %r15d, %ecx
movb $1, %al
callq printf
cmpq $5, %r15
jne .LBB10_5
# %bb.6: # in Loop: Header=BB10_4 Depth=1
incq %rbx
cmpq $6, %rbx
jne .LBB10_4
# %bb.7: # %.preheader.i4.preheader
movl $1, %ebx
.p2align 4, 0x90
.LBB10_8: # %.preheader.i4
# =>This Loop Header: Depth=1
# Child Loop BB10_9 Depth 2
movq %rbx, %r14
orq %r12, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB10_9: # Parent Loop BB10_8 Depth=1
# => This Inner Loop Header: Depth=2
leaq (%r15,%r12), %rdx
incq %rdx
movl $_Z7mat_subPfS_S_, %r9d
movq %r14, %rdi
movl $1, %esi
movl $1, %ecx
movl $10000, %r8d # imm = 0x2710
callq _Z13perf_test_one4dim3S_iPFvPfS0_S0_E
cvtss2sd %xmm0, %xmm0
incq %r15
movl $.L.str.3, %edi
movl $.L.str.11, %esi
movl %ebx, %edx
movl %r15d, %ecx
movb $1, %al
callq printf
cmpq $5, %r15
jne .LBB10_9
# %bb.10: # in Loop: Header=BB10_8 Depth=1
incq %rbx
cmpq $6, %rbx
jne .LBB10_8
# %bb.11: # %.preheader.i14.preheader
movl $1, %ebx
.p2align 4, 0x90
.LBB10_12: # %.preheader.i14
# =>This Loop Header: Depth=1
# Child Loop BB10_13 Depth 2
movq %rbx, %r14
orq %r12, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB10_13: # Parent Loop BB10_12 Depth=1
# => This Inner Loop Header: Depth=2
leaq (%r15,%r12), %rdx
incq %rdx
movl $_Z7mat_mulPfS_S_, %r9d
movq %r14, %rdi
movl $1, %esi
movl $1, %ecx
movl $10000, %r8d # imm = 0x2710
callq _Z13perf_test_one4dim3S_iPFvPfS0_S0_E
cvtss2sd %xmm0, %xmm0
incq %r15
movl $.L.str.3, %edi
movl $.L.str.12, %esi
movl %ebx, %edx
movl %r15d, %ecx
movb $1, %al
callq printf
cmpq $5, %r15
jne .LBB10_13
# %bb.14: # in Loop: Header=BB10_12 Depth=1
incq %rbx
cmpq $6, %rbx
jne .LBB10_12
# %bb.15: # %_Z9perf_testPKcPFvPfS1_S1_E.exit23
movq ev0(%rip), %rdi
callq hipEventDestroy
movq ev1(%rip), %rdi
callq hipEventDestroy
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB10_16:
.cfi_def_cfa_offset 48
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.4, %ecx
movq %rbx, %rdi
movl $174, %edx
movq %rax, %r8
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end10:
.size main, .Lfunc_end10-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB11_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB11_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7mat_addPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7mat_subPfS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7mat_mulPfS_S_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end11:
.size __hip_module_ctor, .Lfunc_end11-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB12_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB12_2:
retq
.Lfunc_end12:
.size __hip_module_dtor, .Lfunc_end12-__hip_module_dtor
.cfi_endproc
# -- End function
.type ev0,@object # @ev0
.bss
.globl ev0
.p2align 3, 0x0
ev0:
.quad 0
.size ev0, 8
.type ev1,@object # @ev1
.globl ev1
.p2align 3, 0x0
ev1:
.quad 0
.size ev1, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "line %d: CUDA error: %s - %s\n"
.size .L.str, 30
.type _Z7mat_addPfS_S_,@object # @_Z7mat_addPfS_S_
.section .rodata,"a",@progbits
.globl _Z7mat_addPfS_S_
.p2align 3, 0x0
_Z7mat_addPfS_S_:
.quad _Z22__device_stub__mat_addPfS_S_
.size _Z7mat_addPfS_S_, 8
.type _Z7mat_subPfS_S_,@object # @_Z7mat_subPfS_S_
.globl _Z7mat_subPfS_S_
.p2align 3, 0x0
_Z7mat_subPfS_S_:
.quad _Z22__device_stub__mat_subPfS_S_
.size _Z7mat_subPfS_S_, 8
.type _Z7mat_mulPfS_S_,@object # @_Z7mat_mulPfS_S_
.globl _Z7mat_mulPfS_S_
.p2align 3, 0x0
_Z7mat_mulPfS_S_:
.quad _Z22__device_stub__mat_mulPfS_S_
.size _Z7mat_mulPfS_S_, 8
.type hst_A,@object # @hst_A
.bss
.globl hst_A
.p2align 3, 0x0
hst_A:
.quad 0
.size hst_A, 8
.type hst_C,@object # @hst_C
.globl hst_C
.p2align 3, 0x0
hst_C:
.quad 0
.size hst_C, 8
.type hst_D,@object # @hst_D
.globl hst_D
.p2align 3, 0x0
hst_D:
.quad 0
.size hst_D, 8
.type dev_A,@object # @dev_A
.globl dev_A
.p2align 3, 0x0
dev_A:
.quad 0
.size dev_A, 8
.type dev_C,@object # @dev_C
.globl dev_C
.p2align 3, 0x0
dev_C:
.quad 0
.size dev_C, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "memcpy"
.size .L.str.1, 7
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "function"
.size .L.str.2, 9
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%s %d %d %f\n"
.size .L.str.3, 13
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "malloc"
.size .L.str.4, 7
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%s mat_add\n"
.size .L.str.5, 13
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "pass"
.size .L.str.6, 5
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "FAIL"
.size .L.str.7, 5
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%s mat_sub\n"
.size .L.str.8, 13
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%s mat_mul\n"
.size .L.str.9, 13
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "mat_add"
.size .L.str.10, 8
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "mat_sub"
.size .L.str.11, 8
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "mat_mul"
.size .L.str.12, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7mat_addPfS_S_"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7mat_subPfS_S_"
.size .L__unnamed_2, 17
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z7mat_mulPfS_S_"
.size .L__unnamed_3, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__mat_addPfS_S_
.addrsig_sym _Z22__device_stub__mat_subPfS_S_
.addrsig_sym _Z22__device_stub__mat_mulPfS_S_
.addrsig_sym _Z11mat_add_cpuPfS_S_
.addrsig_sym _Z11mat_sub_cpuPfS_S_
.addrsig_sym _Z11mat_mul_cpuPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym ev0
.addrsig_sym ev1
.addrsig_sym _Z7mat_addPfS_S_
.addrsig_sym _Z7mat_subPfS_S_
.addrsig_sym _Z7mat_mulPfS_S_
.addrsig_sym dev_A
.addrsig_sym dev_C
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7mat_mulPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002600 */
/*0020*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x4], R5 ; /* 0x0000010002027a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GT.AND P0, PT, R2, 0x5, PT ; /* 0x000000050200780c */
/* 0x000fe20003f04270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GT.OR P0, PT, R0, 0x5, P0 ; /* 0x000000050000780c */
/* 0x000fda0000704670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R16, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff107435 */
/* 0x000fe200000001ff */
/*00b0*/ LEA R7, R2, R2, 0x2 ; /* 0x0000000202077211 */
/* 0x000fe200078e10ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R4, R0, R16, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fc800078e0210 */
/*00e0*/ IMAD.WIDE R2, R7, R16, c[0x0][0x168] ; /* 0x00005a0007027625 */
/* 0x000fe200078e0210 */
/*00f0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040402087981 */
/* 0x000ee8000c1e1900 */
/*0120*/ LDG.E R11, [R4.64+0x14] ; /* 0x00001404040b7981 */
/* 0x000ee8000c1e1900 */
/*0130*/ LDG.E R13, [R4.64+0x28] ; /* 0x00002804040d7981 */
/* 0x000f28000c1e1900 */
/*0140*/ LDG.E R10, [R2.64+0x8] ; /* 0x00000804020a7981 */
/* 0x000f28000c1e1900 */
/*0150*/ LDG.E R15, [R4.64+0x3c] ; /* 0x00003c04040f7981 */
/* 0x000f68000c1e1900 */
/*0160*/ LDG.E R12, [R2.64+0xc] ; /* 0x00000c04020c7981 */
/* 0x000f68000c1e1900 */
/*0170*/ LDG.E R17, [R4.64+0x50] ; /* 0x0000500404117981 */
/* 0x000f68000c1e1900 */
/*0180*/ LDG.E R14, [R2.64+0x10] ; /* 0x00001004020e7981 */
/* 0x000f62000c1e1900 */
/*0190*/ IADD3 R7, R0, R7, RZ ; /* 0x0000000700077210 */
/* 0x000fe20007ffe0ff */
/*01a0*/ FFMA R6, R6, R9, RZ ; /* 0x0000000906067223 */
/* 0x004fc800000000ff */
/*01b0*/ FFMA R6, R11, R8, R6 ; /* 0x000000080b067223 */
/* 0x008fc80000000006 */
/*01c0*/ FFMA R6, R13, R10, R6 ; /* 0x0000000a0d067223 */
/* 0x010fc80000000006 */
/*01d0*/ FFMA R12, R15, R12, R6 ; /* 0x0000000c0f0c7223 */
/* 0x020fe40000000006 */
/*01e0*/ IMAD.WIDE R6, R7, R16, c[0x0][0x160] ; /* 0x0000580007067625 */
/* 0x000fc800078e0210 */
/*01f0*/ FFMA R17, R17, R14, R12 ; /* 0x0000000e11117223 */
/* 0x000fca000000000c */
/*0200*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x000fe2000c101904 */
/*0210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0220*/ BRA 0x220; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7mat_subPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GT.AND P0, PT, R3, 0x5, PT ; /* 0x000000050300780c */
/* 0x000fe20003f04270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GT.OR P0, PT, R0, 0x5, P0 ; /* 0x000000050000780c */
/* 0x000fda0000704670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R3, 0x5, R0 ; /* 0x0000000503007824 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x0c0fe400078e0207 */
/*00f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R6, R0, R7, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fc800078e0207 */
/*0120*/ FADD R9, -R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000100 */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7mat_addPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GT.AND P0, PT, R3, 0x5, PT ; /* 0x000000050300780c */
/* 0x000fe20003f04270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GT.OR P0, PT, R0, 0x5, P0 ; /* 0x000000050000780c */
/* 0x000fda0000704670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R3, 0x5, R0 ; /* 0x0000000503007824 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x0c0fe400078e0207 */
/*00f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R6, R0, R7, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fc800078e0207 */
/*0120*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7mat_addPfS_S_
.globl _Z7mat_addPfS_S_
.p2align 8
.type _Z7mat_addPfS_S_,@function
_Z7mat_addPfS_S_:
s_load_b32 s2, s[0:1], 0x24
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 6, v2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, 5, v[0:1]
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7mat_addPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7mat_addPfS_S_, .Lfunc_end0-_Z7mat_addPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7mat_subPfS_S_
.globl _Z7mat_subPfS_S_
.p2align 8
.type _Z7mat_subPfS_S_,@function
_Z7mat_subPfS_S_:
s_load_b32 s2, s[0:1], 0x24
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 6, v2
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, 5, v[0:1]
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_sub_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7mat_subPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7mat_subPfS_S_, .Lfunc_end1-_Z7mat_subPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7mat_mulPfS_S_
.globl _Z7mat_mulPfS_S_
.p2align 8
.type _Z7mat_mulPfS_S_,@function
_Z7mat_mulPfS_S_:
s_load_b32 s2, s[0:1], 0x24
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 6, v2
s_cbranch_execz .LBB2_4
s_load_b128 s[4:7], s[0:1], 0x8
v_lshl_add_u32 v1, v1, 2, v1
v_mov_b32_e32 v4, 0
s_mov_b32 s2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB2_2:
v_add_nc_u32_e32 v5, s2, v0
s_add_i32 s2, s2, 5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s2, 25
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v5, vcc_lo, s6, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
global_load_b32 v7, v[2:3], off
global_load_b32 v5, v[5:6], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v4, v7, v5
s_cbranch_scc0 .LBB2_2
s_load_b64 s[0:1], s[0:1], 0x0
v_add_nc_u32_e32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB2_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7mat_mulPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z7mat_mulPfS_S_, .Lfunc_end2-_Z7mat_mulPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7mat_addPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7mat_addPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7mat_subPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7mat_subPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7mat_mulPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7mat_mulPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0017d47d_00000000-6_matrix_math.cudafe1.cpp"
.text
#APP
#NO_APP
.globl _Z11mat_add_cpuPfS_S_
.type _Z11mat_add_cpuPfS_S_, @function
_Z11mat_add_cpuPfS_S_:
.LFB2058:
.cfi_startproc
endbr64
movl $0, %eax
.L2:
movss (%rsi,%rax), %xmm0
addss (%rdx,%rax), %xmm0
movss %xmm0, (%rdi,%rax)
addq $4, %rax
cmpq $100, %rax
jne .L2
ret
.cfi_endproc
.LFE2058:
.size _Z11mat_add_cpuPfS_S_, .-_Z11mat_add_cpuPfS_S_
.globl _Z11mat_sub_cpuPfS_S_
.type _Z11mat_sub_cpuPfS_S_, @function
_Z11mat_sub_cpuPfS_S_:
.LFB2059:
.cfi_startproc
endbr64
movl $0, %eax
.L5:
movss (%rsi,%rax), %xmm0
subss (%rdx,%rax), %xmm0
movss %xmm0, (%rdi,%rax)
addq $4, %rax
cmpq $100, %rax
jne .L5
ret
.cfi_endproc
.LFE2059:
.size _Z11mat_sub_cpuPfS_S_, .-_Z11mat_sub_cpuPfS_S_
.globl _Z11mat_mul_cpuPfS_S_
.type _Z11mat_mul_cpuPfS_S_, @function
_Z11mat_mul_cpuPfS_S_:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rsi, %rbx
leaq 100(%rdx), %r8
movl $0, %esi
leaq 100(%rbx), %r11
.L8:
movq %rbx, %r9
movq %rdi, %r10
.L12:
movq %rdx, %rax
movq %r9, %rcx
pxor %xmm1, %xmm1
.L9:
movss (%rcx), %xmm0
mulss (%rax), %xmm0
addss %xmm0, %xmm1
addq $4, %rcx
addq $20, %rax
cmpq %r8, %rax
jne .L9
movss %xmm1, (%r10)
addq $20, %r10
addq $20, %r9
cmpq %r11, %r9
jne .L12
addl $1, %esi
addq $4, %rdx
addq $4, %r8
addq $4, %rdi
cmpl $5, %esi
jne .L8
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z11mat_mul_cpuPfS_S_, .-_Z11mat_mul_cpuPfS_S_
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2067:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2067:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "line %d: CUDA error: %s - %s\n"
.text
.globl _Z14checkCUDAErrorPKci
.type _Z14checkCUDAErrorPKci, @function
_Z14checkCUDAErrorPKci:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbp
movl %esi, %ebx
call cudaGetLastError@PLT
testl %eax, %eax
jne .L20
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movq %rbp, %r8
movl %ebx, %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z14checkCUDAErrorPKci, .-_Z14checkCUDAErrorPKci
.section .rodata.str1.1
.LC2:
.string "memcpy"
.LC3:
.string "function"
.text
.globl _Z9test_implPFvPfS_S_ES1_
.type _Z9test_implPFvPfS_S_ES1_, @function
_Z9test_implPFvPfS_S_ES1_:
.LFB2061:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movq %rsi, %rbx
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $5, 20(%rsp)
movl $5, 24(%rsp)
movl $1, 28(%rsp)
movl $1, %ecx
movl $100, %edx
movq hst_A(%rip), %rsi
movq dev_A(%rip), %rdi
call cudaMemcpy@PLT
movl $116, %esi
leaq .LC2(%rip), %rdi
call _Z14checkCUDAErrorPKci
movl 28(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movq 8(%rsp), %rdi
movl 16(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L22
movq dev_A(%rip), %rsi
movq %rsi, %rdx
movq dev_C(%rip), %rdi
call *%rbp
.L22:
movl $118, %esi
leaq .LC3(%rip), %rdi
call _Z14checkCUDAErrorPKci
movl $2, %ecx
movl $100, %edx
movq dev_C(%rip), %rsi
movq hst_C(%rip), %rdi
call cudaMemcpy@PLT
movl $120, %esi
leaq .LC2(%rip), %rdi
call _Z14checkCUDAErrorPKci
movq hst_A(%rip), %rsi
movq %rsi, %rdx
movq hst_D(%rip), %rdi
call *%rbx
movq hst_C(%rip), %rcx
movq hst_D(%rip), %rdx
movl $0, %eax
.L25:
movss (%rcx,%rax), %xmm0
ucomiss (%rdx,%rax), %xmm0
jp .L26
jne .L26
addq $4, %rax
cmpq $100, %rax
jne .L25
movl $1, %eax
jmp .L21
.L26:
movl $0, %eax
.L21:
addq $40, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z9test_implPFvPfS_S_ES1_, .-_Z9test_implPFvPfS_S_ES1_
.globl _Z13perf_test_one4dim3S_iPFvPfS0_S0_E
.type _Z13perf_test_one4dim3S_iPFvPfS0_S0_E, @function
_Z13perf_test_one4dim3S_iPFvPfS0_S0_E:
.LFB2062:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
movl %esi, 24(%rsp)
movq %rdx, (%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
testl %r8d, %r8d
jle .L35
movl %r8d, %r12d
movq %r9, %r14
movl $0, %ebx
movl $0x00000000, %ebp
leaq 36(%rsp), %r13
jmp .L33
.L32:
movl $0, %esi
movq ev1(%rip), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $100, %edx
movq dev_C(%rip), %rsi
movq hst_C(%rip), %rdi
call cudaMemcpy@PLT
movq ev1(%rip), %rdi
call cudaEventSynchronize@PLT
movq ev1(%rip), %rdx
movq ev0(%rip), %rsi
movq %r13, %rdi
call cudaEventElapsedTime@PLT
movd %ebp, %xmm1
addss 36(%rsp), %xmm1
movd %xmm1, %ebp
addl $1, %ebx
cmpl %ebx, %r12d
je .L30
.L33:
movl $0, %esi
movq ev0(%rip), %rdi
call cudaEventRecord@PLT
movl 8(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq (%rsp), %rdx
movq 16(%rsp), %rdi
movl 24(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L32
movq dev_A(%rip), %rsi
movq %rsi, %rdx
movq dev_C(%rip), %rdi
call *%r14
jmp .L32
.L35:
movl $0x00000000, %ebp
.L30:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L38
movd %ebp, %xmm0
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size _Z13perf_test_one4dim3S_iPFvPfS0_S0_E, .-_Z13perf_test_one4dim3S_iPFvPfS0_S0_E
.section .rodata.str1.1
.LC4:
.string "%s %d %d %f\n"
.text
.globl _Z9perf_testPKcPFvPfS1_S1_E
.type _Z9perf_testPKcPFvPfS1_S1_E, @function
_Z9perf_testPKcPFvPfS1_S1_E:
.LFB2063:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r13
movq %rsi, %r12
movl $1, %ebp
leaq .LC4(%rip), %r14
.L40:
movl $1, %ebx
.L41:
movl %ebx, 20(%rsp)
movl $1, 24(%rsp)
movl %ebp, 8(%rsp)
movl $1, 12(%rsp)
movq %r12, %r9
movl $10000, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call _Z13perf_test_one4dim3S_iPFvPfS0_S0_E
cvtss2sd %xmm0, %xmm0
movl %ebx, %r8d
movl %ebp, %ecx
movq %r13, %rdx
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl $6, %ebx
jne .L41
addl $1, %ebp
cmpl $6, %ebp
jne .L40
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _Z9perf_testPKcPFvPfS1_S1_E, .-_Z9perf_testPKcPFvPfS1_S1_E
.section .rodata.str1.1
.LC5:
.string "pass"
.LC6:
.string "FAIL"
.LC7:
.string "malloc"
.LC8:
.string "%s mat_add\n"
.LC9:
.string "%s mat_sub\n"
.LC10:
.string "%s mat_mul\n"
.LC11:
.string "mat_add"
.LC12:
.string "mat_sub"
.LC13:
.string "mat_mul"
.text
.globl main
.type main, @function
main:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $100, %edi
call malloc@PLT
movq %rax, hst_A(%rip)
movl $100, %edi
call malloc@PLT
movq %rax, hst_C(%rip)
movl $100, %edi
call malloc@PLT
movq %rax, hst_D(%rip)
movl $100, %esi
leaq dev_A(%rip), %rdi
call cudaMalloc@PLT
movl $100, %esi
leaq dev_C(%rip), %rdi
call cudaMalloc@PLT
movl $172, %esi
leaq .LC7(%rip), %rdi
call _Z14checkCUDAErrorPKci
movl $0, %eax
.L46:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movq hst_A(%rip), %rdx
movss %xmm0, (%rdx,%rax,4)
addq $1, %rax
cmpq $25, %rax
jne .L46
movl $1, %ecx
movl $100, %edx
movq hst_A(%rip), %rsi
movq dev_A(%rip), %rdi
call cudaMemcpy@PLT
leaq _Z11mat_add_cpuPfS_S_(%rip), %rsi
leaq _Z7mat_addPfS_S_(%rip), %rdi
call _Z9test_implPFvPfS_S_ES1_
testb %al, %al
leaq .LC6(%rip), %rdx
leaq .LC5(%rip), %rax
cmovne %rax, %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq _Z11mat_sub_cpuPfS_S_(%rip), %rsi
leaq _Z7mat_subPfS_S_(%rip), %rdi
call _Z9test_implPFvPfS_S_ES1_
testb %al, %al
leaq .LC6(%rip), %rdx
leaq .LC5(%rip), %rax
cmovne %rax, %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq _Z11mat_mul_cpuPfS_S_(%rip), %rsi
leaq _Z7mat_mulPfS_S_(%rip), %rdi
call _Z9test_implPFvPfS_S_ES1_
testb %al, %al
leaq .LC6(%rip), %rdx
leaq .LC5(%rip), %rax
cmovne %rax, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq ev0(%rip), %rdi
call cudaEventCreate@PLT
leaq ev1(%rip), %rdi
call cudaEventCreate@PLT
leaq _Z7mat_addPfS_S_(%rip), %rsi
leaq .LC11(%rip), %rdi
call _Z9perf_testPKcPFvPfS1_S1_E
leaq _Z7mat_subPfS_S_(%rip), %rsi
leaq .LC12(%rip), %rdi
call _Z9perf_testPKcPFvPfS1_S1_E
leaq _Z7mat_mulPfS_S_(%rip), %rsi
leaq .LC13(%rip), %rdi
call _Z9perf_testPKcPFvPfS1_S1_E
movq ev0(%rip), %rdi
call cudaEventDestroy@PLT
movq ev1(%rip), %rdi
call cudaEventDestroy@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size main, .-main
.globl _Z30__device_stub__Z7mat_addPfS_S_PfS_S_
.type _Z30__device_stub__Z7mat_addPfS_S_PfS_S_, @function
_Z30__device_stub__Z7mat_addPfS_S_PfS_S_:
.LFB2089:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L59
.L55:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L60
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L59:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7mat_addPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L55
.L60:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z30__device_stub__Z7mat_addPfS_S_PfS_S_, .-_Z30__device_stub__Z7mat_addPfS_S_PfS_S_
.globl _Z7mat_addPfS_S_
.type _Z7mat_addPfS_S_, @function
_Z7mat_addPfS_S_:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7mat_addPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z7mat_addPfS_S_, .-_Z7mat_addPfS_S_
.globl _Z30__device_stub__Z7mat_subPfS_S_PfS_S_
.type _Z30__device_stub__Z7mat_subPfS_S_PfS_S_, @function
_Z30__device_stub__Z7mat_subPfS_S_PfS_S_:
.LFB2091:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L67
.L63:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L68
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L67:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7mat_subPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L63
.L68:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2091:
.size _Z30__device_stub__Z7mat_subPfS_S_PfS_S_, .-_Z30__device_stub__Z7mat_subPfS_S_PfS_S_
.globl _Z7mat_subPfS_S_
.type _Z7mat_subPfS_S_, @function
_Z7mat_subPfS_S_:
.LFB2092:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7mat_subPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _Z7mat_subPfS_S_, .-_Z7mat_subPfS_S_
.globl _Z30__device_stub__Z7mat_mulPfS_S_PfS_S_
.type _Z30__device_stub__Z7mat_mulPfS_S_PfS_S_, @function
_Z30__device_stub__Z7mat_mulPfS_S_PfS_S_:
.LFB2093:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L75
.L71:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L76
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L75:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7mat_mulPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L71
.L76:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2093:
.size _Z30__device_stub__Z7mat_mulPfS_S_PfS_S_, .-_Z30__device_stub__Z7mat_mulPfS_S_PfS_S_
.globl _Z7mat_mulPfS_S_
.type _Z7mat_mulPfS_S_, @function
_Z7mat_mulPfS_S_:
.LFB2094:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7mat_mulPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2094:
.size _Z7mat_mulPfS_S_, .-_Z7mat_mulPfS_S_
.section .rodata.str1.1
.LC14:
.string "_Z7mat_mulPfS_S_"
.LC15:
.string "_Z7mat_subPfS_S_"
.LC16:
.string "_Z7mat_addPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2096:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z7mat_mulPfS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z7mat_subPfS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z7mat_addPfS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl dev_C
.bss
.align 8
.type dev_C, @object
.size dev_C, 8
dev_C:
.zero 8
.globl dev_A
.align 8
.type dev_A, @object
.size dev_A, 8
dev_A:
.zero 8
.globl hst_D
.align 8
.type hst_D, @object
.size hst_D, 8
hst_D:
.zero 8
.globl hst_C
.align 8
.type hst_C, @object
.size hst_C, 8
hst_C:
.zero 8
.globl hst_A
.align 8
.type hst_A, @object
.size hst_A, 8
hst_A:
.zero 8
.globl ev1
.align 8
.type ev1, @object
.size ev1, 8
ev1:
.zero 8
.globl ev0
.align 8
.type ev0, @object
.size ev0, 8
ev0:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrix_math.hip"
.globl _Z14checkCUDAErrorPKci # -- Begin function _Z14checkCUDAErrorPKci
.p2align 4, 0x90
.type _Z14checkCUDAErrorPKci,@function
_Z14checkCUDAErrorPKci: # @_Z14checkCUDAErrorPKci
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
callq hipGetLastError
testl %eax, %eax
jne .LBB0_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 32
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movq %r14, %rdi
movl %ebp, %edx
movq %rbx, %rcx
movq %rax, %r8
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z14checkCUDAErrorPKci, .Lfunc_end0-_Z14checkCUDAErrorPKci
.cfi_endproc
# -- End function
.globl _Z22__device_stub__mat_addPfS_S_ # -- Begin function _Z22__device_stub__mat_addPfS_S_
.p2align 4, 0x90
.type _Z22__device_stub__mat_addPfS_S_,@function
_Z22__device_stub__mat_addPfS_S_: # @_Z22__device_stub__mat_addPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7mat_addPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z22__device_stub__mat_addPfS_S_, .Lfunc_end1-_Z22__device_stub__mat_addPfS_S_
.cfi_endproc
# -- End function
.globl _Z22__device_stub__mat_subPfS_S_ # -- Begin function _Z22__device_stub__mat_subPfS_S_
.p2align 4, 0x90
.type _Z22__device_stub__mat_subPfS_S_,@function
_Z22__device_stub__mat_subPfS_S_: # @_Z22__device_stub__mat_subPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7mat_subPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z22__device_stub__mat_subPfS_S_, .Lfunc_end2-_Z22__device_stub__mat_subPfS_S_
.cfi_endproc
# -- End function
.globl _Z22__device_stub__mat_mulPfS_S_ # -- Begin function _Z22__device_stub__mat_mulPfS_S_
.p2align 4, 0x90
.type _Z22__device_stub__mat_mulPfS_S_,@function
_Z22__device_stub__mat_mulPfS_S_: # @_Z22__device_stub__mat_mulPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7mat_mulPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z22__device_stub__mat_mulPfS_S_, .Lfunc_end3-_Z22__device_stub__mat_mulPfS_S_
.cfi_endproc
# -- End function
.globl _Z11mat_add_cpuPfS_S_ # -- Begin function _Z11mat_add_cpuPfS_S_
.p2align 4, 0x90
.type _Z11mat_add_cpuPfS_S_,@function
_Z11mat_add_cpuPfS_S_: # @_Z11mat_add_cpuPfS_S_
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_1: # =>This Inner Loop Header: Depth=1
movss (%rsi,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rdx,%rax,4), %xmm0
movss %xmm0, (%rdi,%rax,4)
incq %rax
cmpq $25, %rax
jne .LBB4_1
# %bb.2:
retq
.Lfunc_end4:
.size _Z11mat_add_cpuPfS_S_, .Lfunc_end4-_Z11mat_add_cpuPfS_S_
.cfi_endproc
# -- End function
.globl _Z11mat_sub_cpuPfS_S_ # -- Begin function _Z11mat_sub_cpuPfS_S_
.p2align 4, 0x90
.type _Z11mat_sub_cpuPfS_S_,@function
_Z11mat_sub_cpuPfS_S_: # @_Z11mat_sub_cpuPfS_S_
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB5_1: # =>This Inner Loop Header: Depth=1
movss (%rsi,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss (%rdx,%rax,4), %xmm0
movss %xmm0, (%rdi,%rax,4)
incq %rax
cmpq $25, %rax
jne .LBB5_1
# %bb.2:
retq
.Lfunc_end5:
.size _Z11mat_sub_cpuPfS_S_, .Lfunc_end5-_Z11mat_sub_cpuPfS_S_
.cfi_endproc
# -- End function
.globl _Z11mat_mul_cpuPfS_S_ # -- Begin function _Z11mat_mul_cpuPfS_S_
.p2align 4, 0x90
.type _Z11mat_mul_cpuPfS_S_,@function
_Z11mat_mul_cpuPfS_S_: # @_Z11mat_mul_cpuPfS_S_
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB6_1: # %.preheader21
# =>This Loop Header: Depth=1
# Child Loop BB6_2 Depth 2
# Child Loop BB6_3 Depth 3
leaq (%rdi,%rax,4), %rcx
movq %rsi, %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB6_2: # %.preheader
# Parent Loop BB6_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB6_3 Depth 3
xorps %xmm0, %xmm0
movq %rdx, %r10
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB6_3: # Parent Loop BB6_1 Depth=1
# Parent Loop BB6_2 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r8,%r11,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r10), %xmm1
addss %xmm1, %xmm0
incq %r11
addq $20, %r10
cmpq $5, %r11
jne .LBB6_3
# %bb.4: # in Loop: Header=BB6_2 Depth=2
leaq (%r9,%r9,4), %r10
movss %xmm0, (%rcx,%r10,4)
incq %r9
addq $20, %r8
cmpq $5, %r9
jne .LBB6_2
# %bb.5: # in Loop: Header=BB6_1 Depth=1
incq %rax
addq $4, %rdx
cmpq $5, %rax
jne .LBB6_1
# %bb.6:
retq
.Lfunc_end6:
.size _Z11mat_mul_cpuPfS_S_, .Lfunc_end6-_Z11mat_mul_cpuPfS_S_
.cfi_endproc
# -- End function
.globl _Z9test_implPFvPfS_S_ES1_ # -- Begin function _Z9test_implPFvPfS_S_ES1_
.p2align 4, 0x90
.type _Z9test_implPFvPfS_S_ES1_,@function
_Z9test_implPFvPfS_S_ES1_: # @_Z9test_implPFvPfS_S_ES1_
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %rbx
movq %rdi, %r14
movq dev_A(%rip), %rdi
movq hst_A(%rip), %rsi
movl $100, %edx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB7_1
# %bb.3: # %_Z14checkCUDAErrorPKci.exit
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $21474836485, %rdx # imm = 0x500000005
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_5
# %bb.4:
movq dev_C(%rip), %rdi
movq dev_A(%rip), %rdx
movq %rdx, %rsi
callq *(%r14)
.LBB7_5:
callq hipGetLastError
testl %eax, %eax
jne .LBB7_6
# %bb.7: # %_Z14checkCUDAErrorPKci.exit16
movq hst_C(%rip), %rdi
movq dev_C(%rip), %rsi
movl $100, %edx
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB7_8
# %bb.9: # %_Z14checkCUDAErrorPKci.exit18
movq hst_D(%rip), %rdi
movq hst_A(%rip), %rdx
movq %rdx, %rsi
callq *%rbx
movq hst_C(%rip), %rax
movq hst_D(%rip), %rcx
movss (%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss (%rcx), %xmm0
jne .LBB7_10
jnp .LBB7_11
.LBB7_10:
xorl %eax, %eax
jmp .LBB7_15
.LBB7_11: # %.lr.ph.preheader
xorl %esi, %esi
.p2align 4, 0x90
.LBB7_12: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %rsi, %rdx
cmpq $24, %rsi
je .LBB7_14
# %bb.13: # in Loop: Header=BB7_12 Depth=1
movss 4(%rax,%rdx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
leaq 1(%rdx), %rsi
ucomiss 4(%rcx,%rdx,4), %xmm0
jne .LBB7_14
jnp .LBB7_12
.LBB7_14: # %.critedge.loopexit
cmpq $24, %rdx
setae %al
.LBB7_15: # %.critedge
# kill: def $al killed $al killed $eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB7_1:
.cfi_def_cfa_offset 32
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movl $118, %edx
jmp .LBB7_2
.LBB7_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movl $120, %edx
jmp .LBB7_2
.LBB7_8:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movl $122, %edx
.LBB7_2:
movq %rax, %r8
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end7:
.size _Z9test_implPFvPfS_S_ES1_, .Lfunc_end7-_Z9test_implPFvPfS_S_ES1_
.cfi_endproc
# -- End function
.globl _Z13perf_test_one4dim3S_iPFvPfS0_S0_E # -- Begin function _Z13perf_test_one4dim3S_iPFvPfS0_S0_E
.p2align 4, 0x90
.type _Z13perf_test_one4dim3S_iPFvPfS0_S0_E,@function
_Z13perf_test_one4dim3S_iPFvPfS0_S0_E: # @_Z13perf_test_one4dim3S_iPFvPfS0_S0_E
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, 16(%rsp) # 8-byte Spill
testl %r8d, %r8d
jle .LBB8_1
# %bb.3: # %.lr.ph.preheader
movl %r8d, %ebp
movl %ecx, %r14d
movq %rdx, %r15
movl %esi, %r12d
movq %rdi, %r13
xorps %xmm0, %xmm0
leaq 12(%rsp), %rbx
jmp .LBB8_4
.p2align 4, 0x90
.LBB8_6: # in Loop: Header=BB8_4 Depth=1
movq ev1(%rip), %rdi
xorl %esi, %esi
callq hipEventRecord
movq hst_C(%rip), %rdi
movq dev_C(%rip), %rsi
movl $100, %edx
movl $2, %ecx
callq hipMemcpy
movq ev1(%rip), %rdi
callq hipEventSynchronize
movq ev0(%rip), %rsi
movq ev1(%rip), %rdx
movq %rbx, %rdi
callq hipEventElapsedTime
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
addss 12(%rsp), %xmm0
decl %ebp
je .LBB8_2
.LBB8_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss %xmm0, 8(%rsp) # 4-byte Spill
movq ev0(%rip), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r13, %rdi
movl %r12d, %esi
movq %r15, %rdx
movl %r14d, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB8_6
# %bb.5: # in Loop: Header=BB8_4 Depth=1
movq dev_C(%rip), %rdi
movq dev_A(%rip), %rdx
movq %rdx, %rsi
movq 16(%rsp), %rax # 8-byte Reload
callq *(%rax)
jmp .LBB8_6
.LBB8_1:
xorps %xmm0, %xmm0
.LBB8_2: # %._crit_edge
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size _Z13perf_test_one4dim3S_iPFvPfS0_S0_E, .Lfunc_end8-_Z13perf_test_one4dim3S_iPFvPfS0_S0_E
.cfi_endproc
# -- End function
.globl _Z9perf_testPKcPFvPfS1_S1_E # -- Begin function _Z9perf_testPKcPFvPfS1_S1_E
.p2align 4, 0x90
.type _Z9perf_testPKcPFvPfS1_S1_E,@function
_Z9perf_testPKcPFvPfS1_S1_E: # @_Z9perf_testPKcPFvPfS1_S1_E
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq %rdi, %r14
movl $1, %r15d
movabsq $4294967296, %rbp # imm = 0x100000000
.p2align 4, 0x90
.LBB9_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB9_2 Depth 2
movq %r15, %r12
orq %rbp, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB9_2: # Parent Loop BB9_1 Depth=1
# => This Inner Loop Header: Depth=2
leaq 1(,%rbp), %rdx
addq %r13, %rdx
movq %r12, %rdi
movl $1, %esi
movl $1, %ecx
movl $10000, %r8d # imm = 0x2710
movq %rbx, %r9
callq _Z13perf_test_one4dim3S_iPFvPfS0_S0_E
cvtss2sd %xmm0, %xmm0
incq %r13
movl $.L.str.3, %edi
movq %r14, %rsi
movl %r15d, %edx
movl %r13d, %ecx
movb $1, %al
callq printf
cmpq $5, %r13
jne .LBB9_2
# %bb.3: # in Loop: Header=BB9_1 Depth=1
incq %r15
cmpq $6, %r15
jne .LBB9_1
# %bb.4:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end9:
.size _Z9perf_testPKcPFvPfS1_S1_E, .Lfunc_end9-_Z9perf_testPKcPFvPfS1_S1_E
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $100, %edi
callq malloc
movq %rax, hst_A(%rip)
movl $100, %edi
callq malloc
movq %rax, hst_C(%rip)
movl $100, %edi
callq malloc
movq %rax, hst_D(%rip)
movl $dev_A, %edi
movl $100, %esi
callq hipMalloc
movl $dev_C, %edi
movl $100, %esi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB10_16
# %bb.1: # %_Z14checkCUDAErrorPKci.exit.preheader
movq hst_A(%rip), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB10_2: # %_Z14checkCUDAErrorPKci.exit
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $25, %rcx
jne .LBB10_2
# %bb.3:
movabsq $4294967296, %r12 # imm = 0x100000000
movq dev_A(%rip), %rdi
movq hst_A(%rip), %rsi
movl $100, %edx
movl $1, %ecx
callq hipMemcpy
movl $_Z7mat_addPfS_S_, %edi
movl $_Z11mat_add_cpuPfS_S_, %esi
callq _Z9test_implPFvPfS_S_ES1_
movl $.L.str.6, %r14d
movl $.L.str.7, %ebx
testb %al, %al
movl $.L.str.7, %esi
cmovneq %r14, %rsi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl $_Z7mat_subPfS_S_, %edi
movl $_Z11mat_sub_cpuPfS_S_, %esi
callq _Z9test_implPFvPfS_S_ES1_
testb %al, %al
movl $.L.str.7, %esi
cmovneq %r14, %rsi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movl $_Z7mat_mulPfS_S_, %edi
movl $_Z11mat_mul_cpuPfS_S_, %esi
callq _Z9test_implPFvPfS_S_ES1_
testb %al, %al
cmovneq %r14, %rbx
movl $.L.str.9, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl $ev0, %edi
callq hipEventCreate
movl $ev1, %edi
callq hipEventCreate
movl $1, %ebx
.p2align 4, 0x90
.LBB10_4: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB10_5 Depth 2
movq %rbx, %r14
orq %r12, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB10_5: # Parent Loop BB10_4 Depth=1
# => This Inner Loop Header: Depth=2
leaq (%r15,%r12), %rdx
incq %rdx
movl $_Z7mat_addPfS_S_, %r9d
movq %r14, %rdi
movl $1, %esi
movl $1, %ecx
movl $10000, %r8d # imm = 0x2710
callq _Z13perf_test_one4dim3S_iPFvPfS0_S0_E
cvtss2sd %xmm0, %xmm0
incq %r15
movl $.L.str.3, %edi
movl $.L.str.10, %esi
movl %ebx, %edx
movl %r15d, %ecx
movb $1, %al
callq printf
cmpq $5, %r15
jne .LBB10_5
# %bb.6: # in Loop: Header=BB10_4 Depth=1
incq %rbx
cmpq $6, %rbx
jne .LBB10_4
# %bb.7: # %.preheader.i4.preheader
movl $1, %ebx
.p2align 4, 0x90
.LBB10_8: # %.preheader.i4
# =>This Loop Header: Depth=1
# Child Loop BB10_9 Depth 2
movq %rbx, %r14
orq %r12, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB10_9: # Parent Loop BB10_8 Depth=1
# => This Inner Loop Header: Depth=2
leaq (%r15,%r12), %rdx
incq %rdx
movl $_Z7mat_subPfS_S_, %r9d
movq %r14, %rdi
movl $1, %esi
movl $1, %ecx
movl $10000, %r8d # imm = 0x2710
callq _Z13perf_test_one4dim3S_iPFvPfS0_S0_E
cvtss2sd %xmm0, %xmm0
incq %r15
movl $.L.str.3, %edi
movl $.L.str.11, %esi
movl %ebx, %edx
movl %r15d, %ecx
movb $1, %al
callq printf
cmpq $5, %r15
jne .LBB10_9
# %bb.10: # in Loop: Header=BB10_8 Depth=1
incq %rbx
cmpq $6, %rbx
jne .LBB10_8
# %bb.11: # %.preheader.i14.preheader
movl $1, %ebx
.p2align 4, 0x90
.LBB10_12: # %.preheader.i14
# =>This Loop Header: Depth=1
# Child Loop BB10_13 Depth 2
movq %rbx, %r14
orq %r12, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB10_13: # Parent Loop BB10_12 Depth=1
# => This Inner Loop Header: Depth=2
leaq (%r15,%r12), %rdx
incq %rdx
movl $_Z7mat_mulPfS_S_, %r9d
movq %r14, %rdi
movl $1, %esi
movl $1, %ecx
movl $10000, %r8d # imm = 0x2710
callq _Z13perf_test_one4dim3S_iPFvPfS0_S0_E
cvtss2sd %xmm0, %xmm0
incq %r15
movl $.L.str.3, %edi
movl $.L.str.12, %esi
movl %ebx, %edx
movl %r15d, %ecx
movb $1, %al
callq printf
cmpq $5, %r15
jne .LBB10_13
# %bb.14: # in Loop: Header=BB10_12 Depth=1
incq %rbx
cmpq $6, %rbx
jne .LBB10_12
# %bb.15: # %_Z9perf_testPKcPFvPfS1_S1_E.exit23
movq ev0(%rip), %rdi
callq hipEventDestroy
movq ev1(%rip), %rdi
callq hipEventDestroy
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB10_16:
.cfi_def_cfa_offset 48
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.4, %ecx
movq %rbx, %rdi
movl $174, %edx
movq %rax, %r8
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end10:
.size main, .Lfunc_end10-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB11_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB11_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7mat_addPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7mat_subPfS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7mat_mulPfS_S_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end11:
.size __hip_module_ctor, .Lfunc_end11-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB12_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB12_2:
retq
.Lfunc_end12:
.size __hip_module_dtor, .Lfunc_end12-__hip_module_dtor
.cfi_endproc
# -- End function
.type ev0,@object # @ev0
.bss
.globl ev0
.p2align 3, 0x0
ev0:
.quad 0
.size ev0, 8
.type ev1,@object # @ev1
.globl ev1
.p2align 3, 0x0
ev1:
.quad 0
.size ev1, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "line %d: CUDA error: %s - %s\n"
.size .L.str, 30
.type _Z7mat_addPfS_S_,@object # @_Z7mat_addPfS_S_
.section .rodata,"a",@progbits
.globl _Z7mat_addPfS_S_
.p2align 3, 0x0
_Z7mat_addPfS_S_:
.quad _Z22__device_stub__mat_addPfS_S_
.size _Z7mat_addPfS_S_, 8
.type _Z7mat_subPfS_S_,@object # @_Z7mat_subPfS_S_
.globl _Z7mat_subPfS_S_
.p2align 3, 0x0
_Z7mat_subPfS_S_:
.quad _Z22__device_stub__mat_subPfS_S_
.size _Z7mat_subPfS_S_, 8
.type _Z7mat_mulPfS_S_,@object # @_Z7mat_mulPfS_S_
.globl _Z7mat_mulPfS_S_
.p2align 3, 0x0
_Z7mat_mulPfS_S_:
.quad _Z22__device_stub__mat_mulPfS_S_
.size _Z7mat_mulPfS_S_, 8
.type hst_A,@object # @hst_A
.bss
.globl hst_A
.p2align 3, 0x0
hst_A:
.quad 0
.size hst_A, 8
.type hst_C,@object # @hst_C
.globl hst_C
.p2align 3, 0x0
hst_C:
.quad 0
.size hst_C, 8
.type hst_D,@object # @hst_D
.globl hst_D
.p2align 3, 0x0
hst_D:
.quad 0
.size hst_D, 8
.type dev_A,@object # @dev_A
.globl dev_A
.p2align 3, 0x0
dev_A:
.quad 0
.size dev_A, 8
.type dev_C,@object # @dev_C
.globl dev_C
.p2align 3, 0x0
dev_C:
.quad 0
.size dev_C, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "memcpy"
.size .L.str.1, 7
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "function"
.size .L.str.2, 9
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%s %d %d %f\n"
.size .L.str.3, 13
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "malloc"
.size .L.str.4, 7
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%s mat_add\n"
.size .L.str.5, 13
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "pass"
.size .L.str.6, 5
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "FAIL"
.size .L.str.7, 5
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%s mat_sub\n"
.size .L.str.8, 13
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%s mat_mul\n"
.size .L.str.9, 13
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "mat_add"
.size .L.str.10, 8
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "mat_sub"
.size .L.str.11, 8
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "mat_mul"
.size .L.str.12, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7mat_addPfS_S_"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7mat_subPfS_S_"
.size .L__unnamed_2, 17
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z7mat_mulPfS_S_"
.size .L__unnamed_3, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__mat_addPfS_S_
.addrsig_sym _Z22__device_stub__mat_subPfS_S_
.addrsig_sym _Z22__device_stub__mat_mulPfS_S_
.addrsig_sym _Z11mat_add_cpuPfS_S_
.addrsig_sym _Z11mat_sub_cpuPfS_S_
.addrsig_sym _Z11mat_mul_cpuPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym ev0
.addrsig_sym ev1
.addrsig_sym _Z7mat_addPfS_S_
.addrsig_sym _Z7mat_subPfS_S_
.addrsig_sym _Z7mat_mulPfS_S_
.addrsig_sym dev_A
.addrsig_sym dev_C
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/generate.h>
#include <thrust/sort.h>
#include <thrust/copy.h>
#include <algorithm>
#include <cstdlib>
void basic() {
// generate 32M random numbers serially
thrust::host_vector<int> h_vec(32 << 20);
std::generate(h_vec.begin(), h_vec.end(), rand);
std::cout << "before data=" << h_vec[0] << ","<< h_vec[1] << ","<< h_vec[2] << ","<< h_vec[3] << std::endl;
// transfer data to the device
thrust::device_vector<int> d_vec = h_vec;
// sort data on the device (846M keys per second on GeForce GTX 480)
thrust::sort(d_vec.begin(), d_vec.end());
// transfer data back to host
thrust::copy(d_vec.begin(), d_vec.end(), h_vec.begin());
std::cout << "after data=" << h_vec[0] << ","<< h_vec[1] << ","<< h_vec[2] << ","<< h_vec[3] << std::endl;
}
void reverse_sort() {
thrust::host_vector<int> h_vec(32 << 20);
std::generate(h_vec.begin(), h_vec.end(), rand);
std::cout << "before data=" << h_vec[0] << ","<< h_vec[1] << ","<< h_vec[2] << ","<< h_vec[3] << std::endl;
// transfer data to the device
thrust::device_vector<int> d_vec = h_vec;
thrust::sort(d_vec.begin(), d_vec.end(), thrust::greater<int>());
// transfer data back to host
thrust::copy(d_vec.begin(), d_vec.end(), h_vec.begin());
std::cout << "after reverse_sort data=" << h_vec[0] << ","<< h_vec[1] << ","<< h_vec[2] << ","<< h_vec[3] << std::endl;
}
void key_sort() {
thrust::device_vector<int> d_keys(2 << 16);
thrust::device_vector<int> d_values(2 << 16);
std::generate(d_keys.begin(), d_keys.end(), rand);
std::generate(d_values.begin(), d_values.end(), rand);
std::cout << "before key=" << d_keys[0] << ","<< d_keys[1] << ","<< d_keys[2] << ","<< d_keys[3] << std::endl;
std::cout << "before data=" << d_values[0] << ","<< d_values[1] << ","<< d_values[2] << ","<< d_values[3] << std::endl;
thrust::sort_by_key(d_keys.begin(), d_keys.end(), d_values.begin());
std::cout << "after key_sort key=" << d_keys[0] << ","<< d_keys[1] << ","<< d_keys[2] << ","<< d_keys[3] << std::endl;
std::cout << "after key_sort data=" << d_values[0] << ","<< d_values[1] << ","<< d_values[2] << ","<< d_values[3] << std::endl;
}
int main()
{
basic();
reverse_sort();
key_sort();
return 0;
} | #include <hip/hip_runtime.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/generate.h>
#include <thrust/sort.h>
#include <thrust/copy.h>
#include <algorithm>
#include <cstdlib>
void basic() {
// generate 32M random numbers serially
thrust::host_vector<int> h_vec(32 << 20);
std::generate(h_vec.begin(), h_vec.end(), rand);
std::cout << "before data=" << h_vec[0] << ","<< h_vec[1] << ","<< h_vec[2] << ","<< h_vec[3] << std::endl;
// transfer data to the device
thrust::device_vector<int> d_vec = h_vec;
// sort data on the device (846M keys per second on GeForce GTX 480)
thrust::sort(d_vec.begin(), d_vec.end());
// transfer data back to host
thrust::copy(d_vec.begin(), d_vec.end(), h_vec.begin());
std::cout << "after data=" << h_vec[0] << ","<< h_vec[1] << ","<< h_vec[2] << ","<< h_vec[3] << std::endl;
}
void reverse_sort() {
thrust::host_vector<int> h_vec(32 << 20);
std::generate(h_vec.begin(), h_vec.end(), rand);
std::cout << "before data=" << h_vec[0] << ","<< h_vec[1] << ","<< h_vec[2] << ","<< h_vec[3] << std::endl;
// transfer data to the device
thrust::device_vector<int> d_vec = h_vec;
thrust::sort(d_vec.begin(), d_vec.end(), thrust::greater<int>());
// transfer data back to host
thrust::copy(d_vec.begin(), d_vec.end(), h_vec.begin());
std::cout << "after reverse_sort data=" << h_vec[0] << ","<< h_vec[1] << ","<< h_vec[2] << ","<< h_vec[3] << std::endl;
}
void key_sort() {
thrust::device_vector<int> d_keys(2 << 16);
thrust::device_vector<int> d_values(2 << 16);
std::generate(d_keys.begin(), d_keys.end(), rand);
std::generate(d_values.begin(), d_values.end(), rand);
std::cout << "before key=" << d_keys[0] << ","<< d_keys[1] << ","<< d_keys[2] << ","<< d_keys[3] << std::endl;
std::cout << "before data=" << d_values[0] << ","<< d_values[1] << ","<< d_values[2] << ","<< d_values[3] << std::endl;
thrust::sort_by_key(d_keys.begin(), d_keys.end(), d_values.begin());
std::cout << "after key_sort key=" << d_keys[0] << ","<< d_keys[1] << ","<< d_keys[2] << ","<< d_keys[3] << std::endl;
std::cout << "after key_sort data=" << d_values[0] << ","<< d_values[1] << ","<< d_values[2] << ","<< d_values[3] << std::endl;
}
int main()
{
basic();
reverse_sort();
key_sort();
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void row_sums(const float *A, float *sums, size_t ds){
int idx = threadIdx.x+blockDim.x*blockIdx.x; // create typical 1D thread index from built-in variables
if (idx < ds){
float sum = 0.0f;
for (size_t i = 0; i < ds; i++)
sum += A[idx*ds+i]; // write a for loop that will cause the thread to iterate across a row, keeeping a running sum, and write the result to sums
sums[idx] = sum;
}} | code for sm_80
Function : _Z8row_sumsPKfPfm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R6, RZ, 0x1f, R3 ; /* 0x0000001fff067819 */
/* 0x000fc80000011403 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R6, c[0x0][0x174], PT, P0 ; /* 0x00005d0006007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff007624 */
/* 0x000fe200078e00ff */
/*0090*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff027624 */
/* 0x000fe200078e00ff */
/*00b0*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe20008000000 */
/*00c0*/ IMAD R8, R6, c[0x0][0x170], RZ ; /* 0x00005c0006087a24 */
/* 0x000fe200078e02ff */
/*00d0*/ IADD3 R4, P0, R0.reuse, -0x1, RZ ; /* 0xffffffff00047810 */
/* 0x040fe20007f1e0ff */
/*00e0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00f0*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe200078ec0ff */
/*0100*/ IMAD R17, R3.reuse, c[0x0][0x174], R8 ; /* 0x00005d0003117a24 */
/* 0x040fe200078e0208 */
/*0110*/ ISETP.GE.U32.AND P1, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f26070 */
/*0120*/ IMAD.WIDE.U32 R4, R3, c[0x0][0x170], RZ ; /* 0x00005c0003047a25 */
/* 0x000fe200078e00ff */
/*0130*/ IADD3.X R2, R2, -0x1, RZ, P0, !PT ; /* 0xffffffff02027810 */
/* 0x000fc400007fe4ff */
/*0140*/ ISETP.NE.U32.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05070 */
/*0150*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*0160*/ ISETP.GE.U32.AND.EX P1, PT, R2, RZ, PT, P1 ; /* 0x000000ff0200720c */
/* 0x000fe20003f26110 */
/*0170*/ IMAD.IADD R17, R5, 0x1, R17 ; /* 0x0000000105117824 */
/* 0x000fe200078e0211 */
/*0180*/ LEA R2, P2, R3.reuse, c[0x0][0x168], 0x2 ; /* 0x00005a0003027a11 */
/* 0x040fe400078410ff */
/*0190*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fe40003f05300 */
/*01a0*/ LEA.HI.X R3, R3, c[0x0][0x16c], R6, 0x2, P2 ; /* 0x00005b0003037a11 */
/* 0x000fce00010f1406 */
/*01b0*/ @!P1 BRA 0x370 ; /* 0x000001b000009947 */
/* 0x000fea0003800000 */
/*01c0*/ LEA R10, P1, R4, c[0x0][0x160], 0x2 ; /* 0x00005800040a7a11 */
/* 0x000fe200078210ff */
/*01d0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*01e0*/ IADD3 R12, P3, R0, -c[0x0][0x170], RZ ; /* 0x80005c00000c7a10 */
/* 0x000fe20007f7e0ff */
/*01f0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0200*/ IADD3 R10, P2, R10, 0x8, RZ ; /* 0x000000080a0a7810 */
/* 0x000fe20007f5e0ff */
/*0210*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe20008000000 */
/*0220*/ LEA.HI.X R7, R4, c[0x0][0x164], R17, 0x2, P1 ; /* 0x0000590004077a11 */
/* 0x000fe200008f1411 */
/*0230*/ IMAD.X R14, RZ, RZ, ~c[0x0][0x174], P3 ; /* 0x80005d00ff0e7624 */
/* 0x000fc800018e06ff */
/*0240*/ IMAD.X R7, RZ, RZ, R7, P2 ; /* 0x000000ffff077224 */
/* 0x000fe400010e0607 */
/*0250*/ IMAD.MOV.U32 R6, RZ, RZ, R10 ; /* 0x000000ffff067224 */
/* 0x000fca00078e000a */
/*0260*/ LDG.E R8, [R6.64+-0x8] ; /* 0xfffff80606087981 */
/* 0x000ea8000c1e1900 */
/*0270*/ LDG.E R11, [R6.64+-0x4] ; /* 0xfffffc06060b7981 */
/* 0x000ee8000c1e1900 */
/*0280*/ LDG.E R13, [R6.64] ; /* 0x00000006060d7981 */
/* 0x000f28000c1e1900 */
/*0290*/ LDG.E R15, [R6.64+0x4] ; /* 0x00000406060f7981 */
/* 0x000162000c1e1900 */
/*02a0*/ UIADD3 UR4, UP0, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fc8000ff1e03f */
/*02b0*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe400087fe43f */
/*02c0*/ IADD3 R10, P2, R12, UR4, RZ ; /* 0x000000040c0a7c10 */
/* 0x000fc8000ff5e0ff */
/*02d0*/ ISETP.NE.U32.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f25070 */
/*02e0*/ FADD R8, R8, R9 ; /* 0x0000000908087221 */
/* 0x004fe20000000000 */
/*02f0*/ IADD3.X R9, R14, UR5, RZ, P2, !PT ; /* 0x000000050e097c10 */
/* 0x000fe400097fe4ff */
/*0300*/ IADD3 R10, P2, R6, 0x10, RZ ; /* 0x00000010060a7810 */
/* 0x000fe20007f5e0ff */
/*0310*/ FADD R8, R8, R11 ; /* 0x0000000b08087221 */
/* 0x008fe20000000000 */
/*0320*/ ISETP.NE.AND.EX P1, PT, R9, RZ, PT, P1 ; /* 0x000000ff0900720c */
/* 0x000fc60003f25310 */
/*0330*/ FADD R8, R8, R13 ; /* 0x0000000d08087221 */
/* 0x010fe40000000000 */
/*0340*/ IMAD.X R7, RZ, RZ, R7, P2 ; /* 0x000000ffff077224 */
/* 0x001fe400010e0607 */
/*0350*/ FADD R9, R8, R15 ; /* 0x0000000f08097221 */
/* 0x020fcc0000000000 */
/*0360*/ @P1 BRA 0x250 ; /* 0xfffffee000001947 */
/* 0x000fea000383ffff */
/*0370*/ @!P0 BRA 0x470 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0380*/ IADD3 R5, P0, R4, UR4, RZ ; /* 0x0000000404057c10 */
/* 0x000fe4000ff1e0ff */
/*0390*/ IADD3 R6, P2, RZ, -R0, RZ ; /* 0x80000000ff067210 */
/* 0x000fe40007f5e0ff */
/*03a0*/ LEA R4, P1, R5, c[0x0][0x160], 0x2 ; /* 0x0000580005047a11 */
/* 0x000fe400078210ff */
/*03b0*/ IADD3.X R0, R17, UR5, RZ, P0, !PT ; /* 0x0000000511007c10 */
/* 0x000fe200087fe4ff */
/*03c0*/ IMAD.X R7, RZ, RZ, -0x1, P2 ; /* 0xffffffffff077424 */
/* 0x000fc600010e06ff */
/*03d0*/ LEA.HI.X R5, R5, c[0x0][0x164], R0, 0x2, P1 ; /* 0x0000590005057a11 */
/* 0x000fca00008f1400 */
/*03e0*/ LDG.E R0, [R4.64] ; /* 0x0000000604007981 */
/* 0x0000a2000c1e1900 */
/*03f0*/ IADD3 R6, P0, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fca0007f1e0ff */
/*0400*/ IMAD.X R7, RZ, RZ, R7, P0 ; /* 0x000000ffff077224 */
/* 0x000fe200000e0607 */
/*0410*/ ISETP.NE.U32.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f05070 */
/*0420*/ IADD3 R4, P1, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x001fe40007f3e0ff */
/*0430*/ ISETP.NE.AND.EX P0, PT, R7, RZ, PT, P0 ; /* 0x000000ff0700720c */
/* 0x000fc60003f05300 */
/*0440*/ IMAD.X R5, RZ, RZ, R5, P1 ; /* 0x000000ffff057224 */
/* 0x000fe400008e0605 */
/*0450*/ FADD R9, R0, R9 ; /* 0x0000000900097221 */
/* 0x004fd00000000000 */
/*0460*/ @P0 BRA 0x3e0 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0470*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101906 */
/*0480*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0490*/ BRA 0x490; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void row_sums(const float *A, float *sums, size_t ds){
int idx = threadIdx.x+blockDim.x*blockIdx.x; // create typical 1D thread index from built-in variables
if (idx < ds){
float sum = 0.0f;
for (size_t i = 0; i < ds; i++)
sum += A[idx*ds+i]; // write a for loop that will cause the thread to iterate across a row, keeeping a running sum, and write the result to sums
sums[idx] = sum;
}} | .file "tmpxft_00101e9a_00000000-6_row_sums.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z8row_sumsPKfPfmPKfPfm
.type _Z31__device_stub__Z8row_sumsPKfPfmPKfPfm, @function
_Z31__device_stub__Z8row_sumsPKfPfmPKfPfm:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8row_sumsPKfPfm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z8row_sumsPKfPfmPKfPfm, .-_Z31__device_stub__Z8row_sumsPKfPfmPKfPfm
.globl _Z8row_sumsPKfPfm
.type _Z8row_sumsPKfPfm, @function
_Z8row_sumsPKfPfm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8row_sumsPKfPfmPKfPfm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8row_sumsPKfPfm, .-_Z8row_sumsPKfPfm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8row_sumsPKfPfm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8row_sumsPKfPfm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void row_sums(const float *A, float *sums, size_t ds){
int idx = threadIdx.x+blockDim.x*blockIdx.x; // create typical 1D thread index from built-in variables
if (idx < ds){
float sum = 0.0f;
for (size_t i = 0; i < ds; i++)
sum += A[idx*ds+i]; // write a for loop that will cause the thread to iterate across a row, keeeping a running sum, and write the result to sums
sums[idx] = sum;
}} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void row_sums(const float *A, float *sums, size_t ds){
int idx = threadIdx.x+blockDim.x*blockIdx.x; // create typical 1D thread index from built-in variables
if (idx < ds){
float sum = 0.0f;
for (size_t i = 0; i < ds; i++)
sum += A[idx*ds+i]; // write a for loop that will cause the thread to iterate across a row, keeeping a running sum, and write the result to sums
sums[idx] = sum;
}} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void row_sums(const float *A, float *sums, size_t ds){
int idx = threadIdx.x+blockDim.x*blockIdx.x; // create typical 1D thread index from built-in variables
if (idx < ds){
float sum = 0.0f;
for (size_t i = 0; i < ds; i++)
sum += A[idx*ds+i]; // write a for loop that will cause the thread to iterate across a row, keeeping a running sum, and write the result to sums
sums[idx] = sum;
}} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8row_sumsPKfPfm
.globl _Z8row_sumsPKfPfm
.p2align 8
.type _Z8row_sumsPKfPfm,@function
_Z8row_sumsPKfPfm:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_mov_b32 s4, exec_lo
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_4
s_load_b64 s[4:5], s[0:1], 0x0
v_mul_lo_u32 v0, v2, s2
v_mul_lo_u32 v5, v1, s3
v_mad_u64_u32 v[3:4], null, v1, s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add3_u32 v4, v4, v5, v0
v_mov_b32_e32 v0, 0
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
.LBB0_2:
global_load_b32 v5, v[3:4], off
v_add_co_u32 v3, vcc_lo, v3, 4
s_add_u32 s2, s2, -1
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_addc_u32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u64 s[2:3], 0
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v5
s_cbranch_scc0 .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8row_sumsPKfPfm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8row_sumsPKfPfm, .Lfunc_end0-_Z8row_sumsPKfPfm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8row_sumsPKfPfm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8row_sumsPKfPfm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void row_sums(const float *A, float *sums, size_t ds){
int idx = threadIdx.x+blockDim.x*blockIdx.x; // create typical 1D thread index from built-in variables
if (idx < ds){
float sum = 0.0f;
for (size_t i = 0; i < ds; i++)
sum += A[idx*ds+i]; // write a for loop that will cause the thread to iterate across a row, keeeping a running sum, and write the result to sums
sums[idx] = sum;
}} | .text
.file "row_sums.hip"
.globl _Z23__device_stub__row_sumsPKfPfm # -- Begin function _Z23__device_stub__row_sumsPKfPfm
.p2align 4, 0x90
.type _Z23__device_stub__row_sumsPKfPfm,@function
_Z23__device_stub__row_sumsPKfPfm: # @_Z23__device_stub__row_sumsPKfPfm
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8row_sumsPKfPfm, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z23__device_stub__row_sumsPKfPfm, .Lfunc_end0-_Z23__device_stub__row_sumsPKfPfm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8row_sumsPKfPfm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8row_sumsPKfPfm,@object # @_Z8row_sumsPKfPfm
.section .rodata,"a",@progbits
.globl _Z8row_sumsPKfPfm
.p2align 3, 0x0
_Z8row_sumsPKfPfm:
.quad _Z23__device_stub__row_sumsPKfPfm
.size _Z8row_sumsPKfPfm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8row_sumsPKfPfm"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__row_sumsPKfPfm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8row_sumsPKfPfm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8row_sumsPKfPfm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R6, RZ, 0x1f, R3 ; /* 0x0000001fff067819 */
/* 0x000fc80000011403 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R6, c[0x0][0x174], PT, P0 ; /* 0x00005d0006007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff007624 */
/* 0x000fe200078e00ff */
/*0090*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff027624 */
/* 0x000fe200078e00ff */
/*00b0*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe20008000000 */
/*00c0*/ IMAD R8, R6, c[0x0][0x170], RZ ; /* 0x00005c0006087a24 */
/* 0x000fe200078e02ff */
/*00d0*/ IADD3 R4, P0, R0.reuse, -0x1, RZ ; /* 0xffffffff00047810 */
/* 0x040fe20007f1e0ff */
/*00e0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00f0*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe200078ec0ff */
/*0100*/ IMAD R17, R3.reuse, c[0x0][0x174], R8 ; /* 0x00005d0003117a24 */
/* 0x040fe200078e0208 */
/*0110*/ ISETP.GE.U32.AND P1, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f26070 */
/*0120*/ IMAD.WIDE.U32 R4, R3, c[0x0][0x170], RZ ; /* 0x00005c0003047a25 */
/* 0x000fe200078e00ff */
/*0130*/ IADD3.X R2, R2, -0x1, RZ, P0, !PT ; /* 0xffffffff02027810 */
/* 0x000fc400007fe4ff */
/*0140*/ ISETP.NE.U32.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05070 */
/*0150*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*0160*/ ISETP.GE.U32.AND.EX P1, PT, R2, RZ, PT, P1 ; /* 0x000000ff0200720c */
/* 0x000fe20003f26110 */
/*0170*/ IMAD.IADD R17, R5, 0x1, R17 ; /* 0x0000000105117824 */
/* 0x000fe200078e0211 */
/*0180*/ LEA R2, P2, R3.reuse, c[0x0][0x168], 0x2 ; /* 0x00005a0003027a11 */
/* 0x040fe400078410ff */
/*0190*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fe40003f05300 */
/*01a0*/ LEA.HI.X R3, R3, c[0x0][0x16c], R6, 0x2, P2 ; /* 0x00005b0003037a11 */
/* 0x000fce00010f1406 */
/*01b0*/ @!P1 BRA 0x370 ; /* 0x000001b000009947 */
/* 0x000fea0003800000 */
/*01c0*/ LEA R10, P1, R4, c[0x0][0x160], 0x2 ; /* 0x00005800040a7a11 */
/* 0x000fe200078210ff */
/*01d0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*01e0*/ IADD3 R12, P3, R0, -c[0x0][0x170], RZ ; /* 0x80005c00000c7a10 */
/* 0x000fe20007f7e0ff */
/*01f0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0200*/ IADD3 R10, P2, R10, 0x8, RZ ; /* 0x000000080a0a7810 */
/* 0x000fe20007f5e0ff */
/*0210*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe20008000000 */
/*0220*/ LEA.HI.X R7, R4, c[0x0][0x164], R17, 0x2, P1 ; /* 0x0000590004077a11 */
/* 0x000fe200008f1411 */
/*0230*/ IMAD.X R14, RZ, RZ, ~c[0x0][0x174], P3 ; /* 0x80005d00ff0e7624 */
/* 0x000fc800018e06ff */
/*0240*/ IMAD.X R7, RZ, RZ, R7, P2 ; /* 0x000000ffff077224 */
/* 0x000fe400010e0607 */
/*0250*/ IMAD.MOV.U32 R6, RZ, RZ, R10 ; /* 0x000000ffff067224 */
/* 0x000fca00078e000a */
/*0260*/ LDG.E R8, [R6.64+-0x8] ; /* 0xfffff80606087981 */
/* 0x000ea8000c1e1900 */
/*0270*/ LDG.E R11, [R6.64+-0x4] ; /* 0xfffffc06060b7981 */
/* 0x000ee8000c1e1900 */
/*0280*/ LDG.E R13, [R6.64] ; /* 0x00000006060d7981 */
/* 0x000f28000c1e1900 */
/*0290*/ LDG.E R15, [R6.64+0x4] ; /* 0x00000406060f7981 */
/* 0x000162000c1e1900 */
/*02a0*/ UIADD3 UR4, UP0, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fc8000ff1e03f */
/*02b0*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe400087fe43f */
/*02c0*/ IADD3 R10, P2, R12, UR4, RZ ; /* 0x000000040c0a7c10 */
/* 0x000fc8000ff5e0ff */
/*02d0*/ ISETP.NE.U32.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f25070 */
/*02e0*/ FADD R8, R8, R9 ; /* 0x0000000908087221 */
/* 0x004fe20000000000 */
/*02f0*/ IADD3.X R9, R14, UR5, RZ, P2, !PT ; /* 0x000000050e097c10 */
/* 0x000fe400097fe4ff */
/*0300*/ IADD3 R10, P2, R6, 0x10, RZ ; /* 0x00000010060a7810 */
/* 0x000fe20007f5e0ff */
/*0310*/ FADD R8, R8, R11 ; /* 0x0000000b08087221 */
/* 0x008fe20000000000 */
/*0320*/ ISETP.NE.AND.EX P1, PT, R9, RZ, PT, P1 ; /* 0x000000ff0900720c */
/* 0x000fc60003f25310 */
/*0330*/ FADD R8, R8, R13 ; /* 0x0000000d08087221 */
/* 0x010fe40000000000 */
/*0340*/ IMAD.X R7, RZ, RZ, R7, P2 ; /* 0x000000ffff077224 */
/* 0x001fe400010e0607 */
/*0350*/ FADD R9, R8, R15 ; /* 0x0000000f08097221 */
/* 0x020fcc0000000000 */
/*0360*/ @P1 BRA 0x250 ; /* 0xfffffee000001947 */
/* 0x000fea000383ffff */
/*0370*/ @!P0 BRA 0x470 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0380*/ IADD3 R5, P0, R4, UR4, RZ ; /* 0x0000000404057c10 */
/* 0x000fe4000ff1e0ff */
/*0390*/ IADD3 R6, P2, RZ, -R0, RZ ; /* 0x80000000ff067210 */
/* 0x000fe40007f5e0ff */
/*03a0*/ LEA R4, P1, R5, c[0x0][0x160], 0x2 ; /* 0x0000580005047a11 */
/* 0x000fe400078210ff */
/*03b0*/ IADD3.X R0, R17, UR5, RZ, P0, !PT ; /* 0x0000000511007c10 */
/* 0x000fe200087fe4ff */
/*03c0*/ IMAD.X R7, RZ, RZ, -0x1, P2 ; /* 0xffffffffff077424 */
/* 0x000fc600010e06ff */
/*03d0*/ LEA.HI.X R5, R5, c[0x0][0x164], R0, 0x2, P1 ; /* 0x0000590005057a11 */
/* 0x000fca00008f1400 */
/*03e0*/ LDG.E R0, [R4.64] ; /* 0x0000000604007981 */
/* 0x0000a2000c1e1900 */
/*03f0*/ IADD3 R6, P0, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fca0007f1e0ff */
/*0400*/ IMAD.X R7, RZ, RZ, R7, P0 ; /* 0x000000ffff077224 */
/* 0x000fe200000e0607 */
/*0410*/ ISETP.NE.U32.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f05070 */
/*0420*/ IADD3 R4, P1, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x001fe40007f3e0ff */
/*0430*/ ISETP.NE.AND.EX P0, PT, R7, RZ, PT, P0 ; /* 0x000000ff0700720c */
/* 0x000fc60003f05300 */
/*0440*/ IMAD.X R5, RZ, RZ, R5, P1 ; /* 0x000000ffff057224 */
/* 0x000fe400008e0605 */
/*0450*/ FADD R9, R0, R9 ; /* 0x0000000900097221 */
/* 0x004fd00000000000 */
/*0460*/ @P0 BRA 0x3e0 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0470*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101906 */
/*0480*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0490*/ BRA 0x490; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8row_sumsPKfPfm
.globl _Z8row_sumsPKfPfm
.p2align 8
.type _Z8row_sumsPKfPfm,@function
_Z8row_sumsPKfPfm:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_mov_b32 s4, exec_lo
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_4
s_load_b64 s[4:5], s[0:1], 0x0
v_mul_lo_u32 v0, v2, s2
v_mul_lo_u32 v5, v1, s3
v_mad_u64_u32 v[3:4], null, v1, s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add3_u32 v4, v4, v5, v0
v_mov_b32_e32 v0, 0
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
.LBB0_2:
global_load_b32 v5, v[3:4], off
v_add_co_u32 v3, vcc_lo, v3, 4
s_add_u32 s2, s2, -1
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_addc_u32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u64 s[2:3], 0
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v5
s_cbranch_scc0 .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8row_sumsPKfPfm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8row_sumsPKfPfm, .Lfunc_end0-_Z8row_sumsPKfPfm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8row_sumsPKfPfm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8row_sumsPKfPfm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00101e9a_00000000-6_row_sums.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z8row_sumsPKfPfmPKfPfm
.type _Z31__device_stub__Z8row_sumsPKfPfmPKfPfm, @function
_Z31__device_stub__Z8row_sumsPKfPfmPKfPfm:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8row_sumsPKfPfm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z8row_sumsPKfPfmPKfPfm, .-_Z31__device_stub__Z8row_sumsPKfPfmPKfPfm
.globl _Z8row_sumsPKfPfm
.type _Z8row_sumsPKfPfm, @function
_Z8row_sumsPKfPfm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8row_sumsPKfPfmPKfPfm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8row_sumsPKfPfm, .-_Z8row_sumsPKfPfm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8row_sumsPKfPfm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8row_sumsPKfPfm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "row_sums.hip"
.globl _Z23__device_stub__row_sumsPKfPfm # -- Begin function _Z23__device_stub__row_sumsPKfPfm
.p2align 4, 0x90
.type _Z23__device_stub__row_sumsPKfPfm,@function
_Z23__device_stub__row_sumsPKfPfm: # @_Z23__device_stub__row_sumsPKfPfm
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8row_sumsPKfPfm, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z23__device_stub__row_sumsPKfPfm, .Lfunc_end0-_Z23__device_stub__row_sumsPKfPfm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8row_sumsPKfPfm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8row_sumsPKfPfm,@object # @_Z8row_sumsPKfPfm
.section .rodata,"a",@progbits
.globl _Z8row_sumsPKfPfm
.p2align 3, 0x0
_Z8row_sumsPKfPfm:
.quad _Z23__device_stub__row_sumsPKfPfm
.size _Z8row_sumsPKfPfm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8row_sumsPKfPfm"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__row_sumsPKfPfm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8row_sumsPKfPfm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void applyFilter(const unsigned char *input, unsigned char *output, const unsigned int width, const unsigned int height, const float *kernel, const unsigned int kernelWidth) {
const unsigned int col = threadIdx.x + blockIdx.x * blockDim.x;
const unsigned int row = threadIdx.y + blockIdx.y * blockDim.y;
if(row < height && col < width) {
const int half = kernelWidth / 2;
float blur = 0.0;
for(int i = -half; i <= half; i++) {
for(int j = -half; j <= half; j++) {
const unsigned int y = max(0, min(height - 1, row + i));
const unsigned int x = max(0, min(width - 1, col + j));
const float w = kernel[(j + half) + (i + half) * kernelWidth];
blur += w * input[x + y * width];
}
}
output[col + row * width] = static_cast<unsigned char>(blur);
}
} | code for sm_80
Function : _Z11applyFilterPKhPhjjPKfj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e680000002500 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.U32.OR P0, PT, R3, c[0x0][0x170], P0 ; /* 0x00005c0003007a0c */
/* 0x000fda0000706470 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff067624 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD.MOV.U32 R29, RZ, RZ, RZ ; /* 0x000000ffff1d7224 */
/* 0x000fc600078e00ff */
/*00d0*/ SHF.R.U32.HI R2, RZ, 0x1, R6 ; /* 0x00000001ff027819 */
/* 0x000fca0000011606 */
/*00e0*/ IMAD.MOV R5, RZ, RZ, -R2 ; /* 0x000000ffff057224 */
/* 0x000fca00078e0a02 */
/*00f0*/ ISETP.GE.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x000fda0003f06270 */
/*0100*/ @!P0 BRA 0x7d0 ; /* 0x000006c000008947 */
/* 0x000fea0003800000 */
/*0110*/ IADD3 R8, -R2, 0x1, RZ ; /* 0x0000000102087810 */
/* 0x000fe20007ffe1ff */
/*0120*/ ULDC.64 UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe20000000a00 */
/*0130*/ LOP3.LUT R6, R6, 0xfffffffe, RZ, 0xc0, !PT ; /* 0xfffffffe06067812 */
/* 0x000fe200078ec0ff */
/*0140*/ UIADD3 UR5, UR6, -0x1, URZ ; /* 0xffffffff06057890 */
/* 0x000fe2000fffe03f */
/*0150*/ IMAD.IADD R19, R3.reuse, 0x1, -R2 ; /* 0x0000000103137824 */
/* 0x040fe200078e0a02 */
/*0160*/ IADD3 R7, -R2, 0x3, RZ ; /* 0x0000000302077810 */
/* 0x000fe20007ffe1ff */
/*0170*/ IMAD.IADD R11, R3, 0x1, R8 ; /* 0x00000001030b7824 */
/* 0x000fe200078e0208 */
/*0180*/ LOP3.LUT R18, R6, 0x1, RZ, 0xfc, !PT ; /* 0x0000000106127812 */
/* 0x000fe200078efcff */
/*0190*/ IMAD.MOV.U32 R29, RZ, RZ, RZ ; /* 0x000000ffff1d7224 */
/* 0x000fe200078e00ff */
/*01a0*/ IADD3 R9, R2, 0x3, RZ ; /* 0x0000000302097810 */
/* 0x000fe20007ffe0ff */
/*01b0*/ UIADD3 UR4, UR7, -0x1, URZ ; /* 0xffffffff07047890 */
/* 0x000fe2000fffe03f */
/*01c0*/ IADD3 R24, R11, 0x1, RZ ; /* 0x000000010b187810 */
/* 0x000fc40007ffe0ff */
/*01d0*/ IADD3 R10, R3, 0x3, RZ ; /* 0x00000003030a7810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ IMNMX.U32 R11, R11, UR5, PT ; /* 0x000000050b0b7c17 */
/* 0x000fe4000b800000 */
/*01f0*/ LOP3.LUT R18, R18, 0x3, RZ, 0xc0, !PT ; /* 0x0000000312127812 */
/* 0x000fe400078ec0ff */
/*0200*/ IMNMX.U32 R19, R19, UR5, PT ; /* 0x0000000513137c17 */
/* 0x000fe4000b800000 */
/*0210*/ IMNMX.U32 R24, R24, UR5, PT ; /* 0x0000000518187c17 */
/* 0x000fe4000b800000 */
/*0220*/ IMAD.IADD R26, R0, 0x1, R5 ; /* 0x00000001001a7824 */
/* 0x000fe200078e0205 */
/*0230*/ ISETP.NE.AND P1, PT, R18, 0x1, PT ; /* 0x000000011200780c */
/* 0x000fc80003f25270 */
/*0240*/ IMNMX.U32 R26, R26, UR4, PT ; /* 0x000000041a1a7c17 */
/* 0x000fca000b800000 */
/*0250*/ IMAD R16, R26, c[0x0][0x170], R19 ; /* 0x00005c001a107a24 */
/* 0x000fc800078e0213 */
/*0260*/ @P1 IMAD R14, R26, c[0x0][0x170], R11 ; /* 0x00005c001a0e1a24 */
/* 0x000fe200078e020b */
/*0270*/ IADD3 R16, P2, R16, c[0x0][0x160], RZ ; /* 0x0000580010107a10 */
/* 0x000fe20007f5e0ff */
/*0280*/ @P1 IMAD R12, R26, c[0x0][0x170], R24 ; /* 0x00005c001a0c1a24 */
/* 0x000fc600078e0218 */
/*0290*/ @P1 IADD3 R14, P0, R14, c[0x0][0x160], RZ ; /* 0x000058000e0e1a10 */
/* 0x000fe20007f1e0ff */
/*02a0*/ IMAD.X R17, RZ, RZ, c[0x0][0x164], P2 ; /* 0x00005900ff117624 */
/* 0x000fe200010e06ff */
/*02b0*/ @P1 IADD3 R12, P2, R12, c[0x0][0x160], RZ ; /* 0x000058000c0c1a10 */
/* 0x000fe20007f5e0ff */
/*02c0*/ IMAD.IADD R27, R2, 0x1, R5 ; /* 0x00000001021b7824 */
/* 0x000fe400078e0205 */
/*02d0*/ @P1 IMAD.X R15, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff0f1624 */
/* 0x000fe200000e06ff */
/*02e0*/ LDG.E.U8 R4, [R16.64] ; /* 0x0000000810047981 */
/* 0x0000a2000c1e1100 */
/*02f0*/ @P1 IMAD.X R13, RZ, RZ, c[0x0][0x164], P2 ; /* 0x00005900ff0d1624 */
/* 0x000fe400010e06ff */
/*0300*/ IMAD R27, R27, c[0x0][0x180], RZ ; /* 0x000060001b1b7a24 */
/* 0x000fe200078e02ff */
/*0310*/ @P1 LDG.E.U8 R14, [R14.64] ; /* 0x000000080e0e1981 */
/* 0x000ee2000c1e1100 */
/*0320*/ IMAD.MOV.U32 R25, RZ, RZ, 0x4 ; /* 0x00000004ff197424 */
/* 0x000fc600078e00ff */
/*0330*/ @P1 LDG.E.U8 R12, [R12.64] ; /* 0x000000080c0c1981 */
/* 0x000f22000c1e1100 */
/*0340*/ @P1 IADD3 R20, R27.reuse, 0x1, RZ ; /* 0x000000011b141810 */
/* 0x040fe20007ffe0ff */
/*0350*/ IMAD.WIDE.U32 R22, R27.reuse, R25, c[0x0][0x178] ; /* 0x00005e001b167625 */
/* 0x040fe200078e0019 */
/*0360*/ @P1 IADD3 R28, R27, 0x2, RZ ; /* 0x000000021b1c1810 */
/* 0x000fc60007ffe0ff */
/*0370*/ @P1 IMAD.WIDE.U32 R20, R20, R25.reuse, c[0x0][0x178] ; /* 0x00005e0014141625 */
/* 0x080fe400078e0019 */
/*0380*/ LDG.E R22, [R22.64] ; /* 0x0000000816167981 */
/* 0x000f64000c1e1900 */
/*0390*/ @P1 IMAD.WIDE.U32 R16, R28, R25, c[0x0][0x178] ; /* 0x00005e001c101625 */
/* 0x001fe400078e0019 */
/*03a0*/ @P1 LDG.E R20, [R20.64] ; /* 0x0000000814141981 */
/* 0x000f68000c1e1900 */
/*03b0*/ @P1 LDG.E R16, [R16.64] ; /* 0x0000000810101981 */
/* 0x000f62000c1e1900 */
/*03c0*/ ISETP.GE.U32.AND P2, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fc40003f46070 */
/*03d0*/ ISETP.GE.AND P0, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x000fe20003f06270 */
/*03e0*/ I2F.U16 R4, R4 ; /* 0x0000000400047306 */
/* 0x004f700000101000 */
/*03f0*/ @P1 I2F.U16 R14, R14 ; /* 0x0000000e000e1306 */
/* 0x008e300000101000 */
/*0400*/ @P1 I2F.U16 R12, R12 ; /* 0x0000000c000c1306 */
/* 0x010e620000101000 */
/*0410*/ FFMA R29, R4, R22, R29 ; /* 0x00000016041d7223 */
/* 0x020fc4000000001d */
/*0420*/ IMAD.MOV.U32 R22, RZ, RZ, R8 ; /* 0x000000ffff167224 */
/* 0x000fe400078e0008 */
/*0430*/ @P1 IMAD.MOV.U32 R22, RZ, RZ, R7 ; /* 0x000000ffff161224 */
/* 0x000fe400078e0007 */
/*0440*/ @P1 FFMA R13, R14, R20, R29 ; /* 0x000000140e0d1223 */
/* 0x001fc8000000001d */
/*0450*/ @P1 FFMA R29, R12, R16, R13 ; /* 0x000000100c1d1223 */
/* 0x002fe2000000000d */
/*0460*/ @!P2 BRA 0x7b0 ; /* 0x000003400000a947 */
/* 0x000fea0003800000 */
/*0470*/ IADD3 R28, R27.reuse, R9, R22.reuse ; /* 0x000000091b1c7210 */
/* 0x140fe20007ffe016 */
/*0480*/ IMAD.IADD R4, R10, 0x1, R22.reuse ; /* 0x000000010a047824 */
/* 0x100fe200078e0216 */
/*0490*/ IADD3 R14, R27, R2, R22 ; /* 0x000000021b0e7210 */
/* 0x000fe40007ffe016 */
/*04a0*/ IADD3 R27, R22, -0x1, RZ ; /* 0xffffffff161b7810 */
/* 0x000fe40007ffe0ff */
/*04b0*/ IADD3 R12, R4, -0x3, RZ ; /* 0xfffffffd040c7810 */
/* 0x000fc80007ffe0ff */
/*04c0*/ IMNMX.U32 R13, R12, UR5, PT ; /* 0x000000050c0d7c17 */
/* 0x000fca000b800000 */
/*04d0*/ IMAD R13, R26, c[0x0][0x170], R13 ; /* 0x00005c001a0d7a24 */
/* 0x000fca00078e020d */
/*04e0*/ IADD3 R12, P1, R13, c[0x0][0x160], RZ ; /* 0x000058000d0c7a10 */
/* 0x000fca0007f3e0ff */
/*04f0*/ IMAD.X R13, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff0d7624 */
/* 0x000fca00008e06ff */
/*0500*/ LDG.E.U8 R20, [R12.64] ; /* 0x000000080c147981 */
/* 0x0000a2000c1e1100 */
/*0510*/ IMAD.WIDE.U32 R14, R14, R25, c[0x0][0x178] ; /* 0x00005e000e0e7625 */
/* 0x000fca00078e0019 */
/*0520*/ LDG.E R16, [R14.64] ; /* 0x000000080e107981 */
/* 0x0002e2000c1e1900 */
/*0530*/ IADD3 R17, R4.reuse, -0x2, RZ ; /* 0xfffffffe04117810 */
/* 0x040fe40007ffe0ff */
/*0540*/ IADD3 R22, R4, -0x1, RZ ; /* 0xffffffff04167810 */
/* 0x000fe40007ffe0ff */
/*0550*/ IMNMX.U32 R21, R17, UR5, PT ; /* 0x0000000511157c17 */
/* 0x000fe4000b800000 */
/*0560*/ IMNMX.U32 R23, R22, UR5, PT ; /* 0x0000000516177c17 */
/* 0x000fe4000b800000 */
/*0570*/ IMNMX.U32 R22, R4, UR5, PT ; /* 0x0000000504167c17 */
/* 0x000fe2000b800000 */
/*0580*/ IMAD R21, R26, c[0x0][0x170], R21 ; /* 0x00005c001a157a24 */
/* 0x000fc400078e0215 */
/*0590*/ IMAD R23, R26.reuse, c[0x0][0x170], R23 ; /* 0x00005c001a177a24 */
/* 0x040fe400078e0217 */
/*05a0*/ IMAD R22, R26, c[0x0][0x170], R22 ; /* 0x00005c001a167a24 */
/* 0x000fe200078e0216 */
/*05b0*/ IADD3 R12, P2, R21, c[0x0][0x160], RZ ; /* 0x00005800150c7a10 */
/* 0x001fe40007f5e0ff */
/*05c0*/ IADD3 R14, P1, R23, c[0x0][0x160], RZ ; /* 0x00005800170e7a10 */
/* 0x002fc60007f3e0ff */
/*05d0*/ IMAD.X R13, RZ, RZ, c[0x0][0x164], P2 ; /* 0x00005900ff0d7624 */
/* 0x000fe400010e06ff */
/*05e0*/ IMAD.X R15, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff0f7624 */
/* 0x000fc600008e06ff */
/*05f0*/ LDG.E.U8 R12, [R12.64] ; /* 0x000000080c0c7981 */
/* 0x000128000c1e1100 */
/*0600*/ LDG.E.U8 R13, [R14.64] ; /* 0x000000080e0d7981 */
/* 0x001162000c1e1100 */
/*0610*/ I2F.U16 R17, R20 ; /* 0x0000001400117306 */
/* 0x0042e40000101000 */
/*0620*/ IADD3 R20, R28, -0x2, RZ ; /* 0xfffffffe1c147810 */
/* 0x002fe20007ffe0ff */
/*0630*/ FFMA R29, R17, R16, R29 ; /* 0x00000010111d7223 */
/* 0x008fe2000000001d */
/*0640*/ IADD3 R16, P2, R22, c[0x0][0x160], RZ ; /* 0x0000580016107a10 */
/* 0x000fca0007f5e0ff */
/*0650*/ IMAD.X R17, RZ, RZ, c[0x0][0x164], P2 ; /* 0x00005900ff117624 */
/* 0x000fe400010e06ff */
/*0660*/ IMAD.WIDE.U32 R14, R20, R25.reuse, c[0x0][0x178] ; /* 0x00005e00140e7625 */
/* 0x081fe200078e0019 */
/*0670*/ IADD3 R20, R28, -0x1, RZ ; /* 0xffffffff1c147810 */
/* 0x000fe40007ffe0ff */
/*0680*/ LDG.E.U8 R16, [R16.64] ; /* 0x0000000810107981 */
/* 0x000ea6000c1e1100 */
/*0690*/ IMAD.WIDE.U32 R20, R20, R25.reuse, c[0x0][0x178] ; /* 0x00005e0014147625 */
/* 0x080fe200078e0019 */
/*06a0*/ LDG.E R14, [R14.64] ; /* 0x000000080e0e7981 */
/* 0x0000e6000c1e1900 */
/*06b0*/ IMAD.WIDE.U32 R22, R28, R25, c[0x0][0x178] ; /* 0x00005e001c167625 */
/* 0x000fc400078e0019 */
/*06c0*/ LDG.E R20, [R20.64] ; /* 0x0000000814147981 */
/* 0x000ee8000c1e1900 */
/*06d0*/ LDG.E R22, [R22.64] ; /* 0x0000000816167981 */
/* 0x000ee2000c1e1900 */
/*06e0*/ I2F.U16 R12, R12 ; /* 0x0000000c000c7306 */
/* 0x010ee20000101000 */
/*06f0*/ IADD3 R27, R27, 0x4, RZ ; /* 0x000000041b1b7810 */
/* 0x000fce0007ffe0ff */
/*0700*/ I2F.U16 R13, R13 ; /* 0x0000000d000d7306 */
/* 0x020e620000101000 */
/*0710*/ ISETP.GE.AND P1, PT, R27, R2, PT ; /* 0x000000021b00720c */
/* 0x000fe40003f26270 */
/*0720*/ IADD3 R15, R28, 0x4, RZ ; /* 0x000000041c0f7810 */
/* 0x001fe40007ffe0ff */
/*0730*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0740*/ I2F.U16 R16, R16 ; /* 0x0000001000107306 */
/* 0x004e220000101000 */
/*0750*/ FFMA R29, R12, R14, R29 ; /* 0x0000000e0c1d7223 */
/* 0x008fe2000000001d */
/*0760*/ IADD3 R14, R28, 0x1, RZ ; /* 0x000000011c0e7810 */
/* 0x000fc60007ffe0ff */
/*0770*/ FFMA R29, R13, R20, R29 ; /* 0x000000140d1d7223 */
/* 0x002fe4000000001d */
/*0780*/ IMAD.MOV.U32 R28, RZ, RZ, R15 ; /* 0x000000ffff1c7224 */
/* 0x000fe400078e000f */
/*0790*/ FFMA R29, R16, R22, R29 ; /* 0x00000016101d7223 */
/* 0x001fe2000000001d */
/*07a0*/ @!P1 BRA 0x4b0 ; /* 0xfffffd0000009947 */
/* 0x000fea000383ffff */
/*07b0*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fe20007ffe0ff */
/*07c0*/ @!P0 BRA 0x220 ; /* 0xfffffa5000008947 */
/* 0x000fea000383ffff */
/*07d0*/ F2I.U32.TRUNC.NTZ R29, R29 ; /* 0x0000001d001d7305 */
/* 0x000e22000020f000 */
/*07e0*/ IMAD R3, R0, c[0x0][0x170], R3 ; /* 0x00005c0000037a24 */
/* 0x000fca00078e0203 */
/*07f0*/ IADD3 R2, P0, R3, c[0x0][0x168], RZ ; /* 0x00005a0003027a10 */
/* 0x000fca0007f1e0ff */
/*0800*/ IMAD.X R3, RZ, RZ, c[0x0][0x16c], P0 ; /* 0x00005b00ff037624 */
/* 0x000fca00000e06ff */
/*0810*/ STG.E.U8 [R2.64], R29 ; /* 0x0000001d02007986 */
/* 0x001fe2000c101108 */
/*0820*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0830*/ BRA 0x830; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void applyFilter(const unsigned char *input, unsigned char *output, const unsigned int width, const unsigned int height, const float *kernel, const unsigned int kernelWidth) {
const unsigned int col = threadIdx.x + blockIdx.x * blockDim.x;
const unsigned int row = threadIdx.y + blockIdx.y * blockDim.y;
if(row < height && col < width) {
const int half = kernelWidth / 2;
float blur = 0.0;
for(int i = -half; i <= half; i++) {
for(int j = -half; j <= half; j++) {
const unsigned int y = max(0, min(height - 1, row + i));
const unsigned int x = max(0, min(width - 1, col + j));
const float w = kernel[(j + half) + (i + half) * kernelWidth];
blur += w * input[x + y * width];
}
}
output[col + row * width] = static_cast<unsigned char>(blur);
}
} | .file "tmpxft_00183577_00000000-6_gaussian_blur.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z11applyFilterPKhPhjjPKfjPKhPhjjPKfj
.type _Z40__device_stub__Z11applyFilterPKhPhjjPKfjPKhPhjjPKfj, @function
_Z40__device_stub__Z11applyFilterPKhPhjjPKfjPKhPhjjPKfj:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movq %r8, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11applyFilterPKhPhjjPKfj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z11applyFilterPKhPhjjPKfjPKhPhjjPKfj, .-_Z40__device_stub__Z11applyFilterPKhPhjjPKfjPKhPhjjPKfj
.globl _Z11applyFilterPKhPhjjPKfj
.type _Z11applyFilterPKhPhjjPKfj, @function
_Z11applyFilterPKhPhjjPKfj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z11applyFilterPKhPhjjPKfjPKhPhjjPKfj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11applyFilterPKhPhjjPKfj, .-_Z11applyFilterPKhPhjjPKfj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11applyFilterPKhPhjjPKfj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11applyFilterPKhPhjjPKfj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void applyFilter(const unsigned char *input, unsigned char *output, const unsigned int width, const unsigned int height, const float *kernel, const unsigned int kernelWidth) {
const unsigned int col = threadIdx.x + blockIdx.x * blockDim.x;
const unsigned int row = threadIdx.y + blockIdx.y * blockDim.y;
if(row < height && col < width) {
const int half = kernelWidth / 2;
float blur = 0.0;
for(int i = -half; i <= half; i++) {
for(int j = -half; j <= half; j++) {
const unsigned int y = max(0, min(height - 1, row + i));
const unsigned int x = max(0, min(width - 1, col + j));
const float w = kernel[(j + half) + (i + half) * kernelWidth];
blur += w * input[x + y * width];
}
}
output[col + row * width] = static_cast<unsigned char>(blur);
}
} | #include <hip/hip_runtime.h>
__global__ void applyFilter(const unsigned char *input, unsigned char *output, const unsigned int width, const unsigned int height, const float *kernel, const unsigned int kernelWidth) {
const unsigned int col = threadIdx.x + blockIdx.x * blockDim.x;
const unsigned int row = threadIdx.y + blockIdx.y * blockDim.y;
if(row < height && col < width) {
const int half = kernelWidth / 2;
float blur = 0.0;
for(int i = -half; i <= half; i++) {
for(int j = -half; j <= half; j++) {
const unsigned int y = max(0, min(height - 1, row + i));
const unsigned int x = max(0, min(width - 1, col + j));
const float w = kernel[(j + half) + (i + half) * kernelWidth];
blur += w * input[x + y * width];
}
}
output[col + row * width] = static_cast<unsigned char>(blur);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void applyFilter(const unsigned char *input, unsigned char *output, const unsigned int width, const unsigned int height, const float *kernel, const unsigned int kernelWidth) {
const unsigned int col = threadIdx.x + blockIdx.x * blockDim.x;
const unsigned int row = threadIdx.y + blockIdx.y * blockDim.y;
if(row < height && col < width) {
const int half = kernelWidth / 2;
float blur = 0.0;
for(int i = -half; i <= half; i++) {
for(int j = -half; j <= half; j++) {
const unsigned int y = max(0, min(height - 1, row + i));
const unsigned int x = max(0, min(width - 1, col + j));
const float w = kernel[(j + half) + (i + half) * kernelWidth];
blur += w * input[x + y * width];
}
}
output[col + row * width] = static_cast<unsigned char>(blur);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11applyFilterPKhPhjjPKfj
.globl _Z11applyFilterPKhPhjjPKfj
.p2align 8
.type _Z11applyFilterPKhPhjjPKfj,@function
_Z11applyFilterPKhPhjjPKfj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[4:5], s[0:1], 0x10
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_mul_i32 s14, s14, s3
v_mad_u64_u32 v[0:1], null, s15, s2, v[2:3]
v_add_nc_u32_e32 v1, s14, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_u32_e64 s2, s4, v1
v_cmp_gt_u32_e32 vcc_lo, s5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_7
s_clause 0x2
s_load_b32 s10, s[0:1], 0x20
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[6:7], s[0:1], 0x18
v_mov_b32_e32 v2, 0
s_mov_b32 s9, 0
s_add_i32 s5, s5, -1
s_add_i32 s12, s4, -1
s_mov_b32 s15, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s11, s10, 1
s_or_b32 s14, s10, 1
v_subrev_nc_u32_e32 v3, s11, v1
s_sub_i32 s13, 0, s11
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
v_add_nc_u32_e32 v4, s13, v0
s_mov_b32 s8, s15
s_mov_b32 s16, s14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_u32_e32 v4, s5, v4
v_cvt_f64_u32_e32 v[4:5], v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_f64 v[4:5], v[4:5], 0
v_cvt_u32_f64_e32 v4, v[4:5]
v_mov_b32_e32 v5, v3
s_delay_alu instid0(VALU_DEP_2)
v_mul_lo_u32 v4, v4, s4
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_min_u32_e32 v6, s12, v5
s_lshl_b64 s[18:19], s[8:9], 2
s_add_u32 s18, s6, s18
s_addc_u32 s19, s7, s19
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_cvt_f64_u32_e32 v[6:7], v6
s_load_b32 s17, s[18:19], 0x0
s_add_i32 s16, s16, -1
s_add_i32 s8, s8, 1
s_cmp_eq_u32 s16, 0
v_max_f64 v[6:7], v[6:7], 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f64_e32 v6, v[6:7]
v_add_nc_u32_e32 v6, v4, v6
global_load_u8 v6, v6, s[2:3]
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v6, v6
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_dual_fmac_f32 v2, s17, v6 :: v_dual_add_nc_u32 v5, 1, v5
s_cbranch_scc0 .LBB0_3
s_add_i32 s8, s13, 1
s_add_i32 s15, s15, s10
s_cmp_eq_u32 s13, s11
s_cbranch_scc1 .LBB0_6
s_mov_b32 s13, s8
s_branch .LBB0_2
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x8
v_mad_u64_u32 v[3:4], null, v0, s4, v[1:2]
v_cvt_i32_f32_e32 v0, v2
s_waitcnt lgkmcnt(0)
global_store_b8 v3, v0, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11applyFilterPKhPhjjPKfj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11applyFilterPKhPhjjPKfj, .Lfunc_end0-_Z11applyFilterPKhPhjjPKfj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11applyFilterPKhPhjjPKfj
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z11applyFilterPKhPhjjPKfj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void applyFilter(const unsigned char *input, unsigned char *output, const unsigned int width, const unsigned int height, const float *kernel, const unsigned int kernelWidth) {
const unsigned int col = threadIdx.x + blockIdx.x * blockDim.x;
const unsigned int row = threadIdx.y + blockIdx.y * blockDim.y;
if(row < height && col < width) {
const int half = kernelWidth / 2;
float blur = 0.0;
for(int i = -half; i <= half; i++) {
for(int j = -half; j <= half; j++) {
const unsigned int y = max(0, min(height - 1, row + i));
const unsigned int x = max(0, min(width - 1, col + j));
const float w = kernel[(j + half) + (i + half) * kernelWidth];
blur += w * input[x + y * width];
}
}
output[col + row * width] = static_cast<unsigned char>(blur);
}
} | .text
.file "gaussian_blur.hip"
.globl _Z26__device_stub__applyFilterPKhPhjjPKfj # -- Begin function _Z26__device_stub__applyFilterPKhPhjjPKfj
.p2align 4, 0x90
.type _Z26__device_stub__applyFilterPKhPhjjPKfj,@function
_Z26__device_stub__applyFilterPKhPhjjPKfj: # @_Z26__device_stub__applyFilterPKhPhjjPKfj
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movq %r8, 72(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11applyFilterPKhPhjjPKfj, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z26__device_stub__applyFilterPKhPhjjPKfj, .Lfunc_end0-_Z26__device_stub__applyFilterPKhPhjjPKfj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11applyFilterPKhPhjjPKfj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11applyFilterPKhPhjjPKfj,@object # @_Z11applyFilterPKhPhjjPKfj
.section .rodata,"a",@progbits
.globl _Z11applyFilterPKhPhjjPKfj
.p2align 3, 0x0
_Z11applyFilterPKhPhjjPKfj:
.quad _Z26__device_stub__applyFilterPKhPhjjPKfj
.size _Z11applyFilterPKhPhjjPKfj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11applyFilterPKhPhjjPKfj"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__applyFilterPKhPhjjPKfj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11applyFilterPKhPhjjPKfj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11applyFilterPKhPhjjPKfj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e680000002500 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.U32.OR P0, PT, R3, c[0x0][0x170], P0 ; /* 0x00005c0003007a0c */
/* 0x000fda0000706470 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff067624 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD.MOV.U32 R29, RZ, RZ, RZ ; /* 0x000000ffff1d7224 */
/* 0x000fc600078e00ff */
/*00d0*/ SHF.R.U32.HI R2, RZ, 0x1, R6 ; /* 0x00000001ff027819 */
/* 0x000fca0000011606 */
/*00e0*/ IMAD.MOV R5, RZ, RZ, -R2 ; /* 0x000000ffff057224 */
/* 0x000fca00078e0a02 */
/*00f0*/ ISETP.GE.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x000fda0003f06270 */
/*0100*/ @!P0 BRA 0x7d0 ; /* 0x000006c000008947 */
/* 0x000fea0003800000 */
/*0110*/ IADD3 R8, -R2, 0x1, RZ ; /* 0x0000000102087810 */
/* 0x000fe20007ffe1ff */
/*0120*/ ULDC.64 UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe20000000a00 */
/*0130*/ LOP3.LUT R6, R6, 0xfffffffe, RZ, 0xc0, !PT ; /* 0xfffffffe06067812 */
/* 0x000fe200078ec0ff */
/*0140*/ UIADD3 UR5, UR6, -0x1, URZ ; /* 0xffffffff06057890 */
/* 0x000fe2000fffe03f */
/*0150*/ IMAD.IADD R19, R3.reuse, 0x1, -R2 ; /* 0x0000000103137824 */
/* 0x040fe200078e0a02 */
/*0160*/ IADD3 R7, -R2, 0x3, RZ ; /* 0x0000000302077810 */
/* 0x000fe20007ffe1ff */
/*0170*/ IMAD.IADD R11, R3, 0x1, R8 ; /* 0x00000001030b7824 */
/* 0x000fe200078e0208 */
/*0180*/ LOP3.LUT R18, R6, 0x1, RZ, 0xfc, !PT ; /* 0x0000000106127812 */
/* 0x000fe200078efcff */
/*0190*/ IMAD.MOV.U32 R29, RZ, RZ, RZ ; /* 0x000000ffff1d7224 */
/* 0x000fe200078e00ff */
/*01a0*/ IADD3 R9, R2, 0x3, RZ ; /* 0x0000000302097810 */
/* 0x000fe20007ffe0ff */
/*01b0*/ UIADD3 UR4, UR7, -0x1, URZ ; /* 0xffffffff07047890 */
/* 0x000fe2000fffe03f */
/*01c0*/ IADD3 R24, R11, 0x1, RZ ; /* 0x000000010b187810 */
/* 0x000fc40007ffe0ff */
/*01d0*/ IADD3 R10, R3, 0x3, RZ ; /* 0x00000003030a7810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ IMNMX.U32 R11, R11, UR5, PT ; /* 0x000000050b0b7c17 */
/* 0x000fe4000b800000 */
/*01f0*/ LOP3.LUT R18, R18, 0x3, RZ, 0xc0, !PT ; /* 0x0000000312127812 */
/* 0x000fe400078ec0ff */
/*0200*/ IMNMX.U32 R19, R19, UR5, PT ; /* 0x0000000513137c17 */
/* 0x000fe4000b800000 */
/*0210*/ IMNMX.U32 R24, R24, UR5, PT ; /* 0x0000000518187c17 */
/* 0x000fe4000b800000 */
/*0220*/ IMAD.IADD R26, R0, 0x1, R5 ; /* 0x00000001001a7824 */
/* 0x000fe200078e0205 */
/*0230*/ ISETP.NE.AND P1, PT, R18, 0x1, PT ; /* 0x000000011200780c */
/* 0x000fc80003f25270 */
/*0240*/ IMNMX.U32 R26, R26, UR4, PT ; /* 0x000000041a1a7c17 */
/* 0x000fca000b800000 */
/*0250*/ IMAD R16, R26, c[0x0][0x170], R19 ; /* 0x00005c001a107a24 */
/* 0x000fc800078e0213 */
/*0260*/ @P1 IMAD R14, R26, c[0x0][0x170], R11 ; /* 0x00005c001a0e1a24 */
/* 0x000fe200078e020b */
/*0270*/ IADD3 R16, P2, R16, c[0x0][0x160], RZ ; /* 0x0000580010107a10 */
/* 0x000fe20007f5e0ff */
/*0280*/ @P1 IMAD R12, R26, c[0x0][0x170], R24 ; /* 0x00005c001a0c1a24 */
/* 0x000fc600078e0218 */
/*0290*/ @P1 IADD3 R14, P0, R14, c[0x0][0x160], RZ ; /* 0x000058000e0e1a10 */
/* 0x000fe20007f1e0ff */
/*02a0*/ IMAD.X R17, RZ, RZ, c[0x0][0x164], P2 ; /* 0x00005900ff117624 */
/* 0x000fe200010e06ff */
/*02b0*/ @P1 IADD3 R12, P2, R12, c[0x0][0x160], RZ ; /* 0x000058000c0c1a10 */
/* 0x000fe20007f5e0ff */
/*02c0*/ IMAD.IADD R27, R2, 0x1, R5 ; /* 0x00000001021b7824 */
/* 0x000fe400078e0205 */
/*02d0*/ @P1 IMAD.X R15, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff0f1624 */
/* 0x000fe200000e06ff */
/*02e0*/ LDG.E.U8 R4, [R16.64] ; /* 0x0000000810047981 */
/* 0x0000a2000c1e1100 */
/*02f0*/ @P1 IMAD.X R13, RZ, RZ, c[0x0][0x164], P2 ; /* 0x00005900ff0d1624 */
/* 0x000fe400010e06ff */
/*0300*/ IMAD R27, R27, c[0x0][0x180], RZ ; /* 0x000060001b1b7a24 */
/* 0x000fe200078e02ff */
/*0310*/ @P1 LDG.E.U8 R14, [R14.64] ; /* 0x000000080e0e1981 */
/* 0x000ee2000c1e1100 */
/*0320*/ IMAD.MOV.U32 R25, RZ, RZ, 0x4 ; /* 0x00000004ff197424 */
/* 0x000fc600078e00ff */
/*0330*/ @P1 LDG.E.U8 R12, [R12.64] ; /* 0x000000080c0c1981 */
/* 0x000f22000c1e1100 */
/*0340*/ @P1 IADD3 R20, R27.reuse, 0x1, RZ ; /* 0x000000011b141810 */
/* 0x040fe20007ffe0ff */
/*0350*/ IMAD.WIDE.U32 R22, R27.reuse, R25, c[0x0][0x178] ; /* 0x00005e001b167625 */
/* 0x040fe200078e0019 */
/*0360*/ @P1 IADD3 R28, R27, 0x2, RZ ; /* 0x000000021b1c1810 */
/* 0x000fc60007ffe0ff */
/*0370*/ @P1 IMAD.WIDE.U32 R20, R20, R25.reuse, c[0x0][0x178] ; /* 0x00005e0014141625 */
/* 0x080fe400078e0019 */
/*0380*/ LDG.E R22, [R22.64] ; /* 0x0000000816167981 */
/* 0x000f64000c1e1900 */
/*0390*/ @P1 IMAD.WIDE.U32 R16, R28, R25, c[0x0][0x178] ; /* 0x00005e001c101625 */
/* 0x001fe400078e0019 */
/*03a0*/ @P1 LDG.E R20, [R20.64] ; /* 0x0000000814141981 */
/* 0x000f68000c1e1900 */
/*03b0*/ @P1 LDG.E R16, [R16.64] ; /* 0x0000000810101981 */
/* 0x000f62000c1e1900 */
/*03c0*/ ISETP.GE.U32.AND P2, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fc40003f46070 */
/*03d0*/ ISETP.GE.AND P0, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x000fe20003f06270 */
/*03e0*/ I2F.U16 R4, R4 ; /* 0x0000000400047306 */
/* 0x004f700000101000 */
/*03f0*/ @P1 I2F.U16 R14, R14 ; /* 0x0000000e000e1306 */
/* 0x008e300000101000 */
/*0400*/ @P1 I2F.U16 R12, R12 ; /* 0x0000000c000c1306 */
/* 0x010e620000101000 */
/*0410*/ FFMA R29, R4, R22, R29 ; /* 0x00000016041d7223 */
/* 0x020fc4000000001d */
/*0420*/ IMAD.MOV.U32 R22, RZ, RZ, R8 ; /* 0x000000ffff167224 */
/* 0x000fe400078e0008 */
/*0430*/ @P1 IMAD.MOV.U32 R22, RZ, RZ, R7 ; /* 0x000000ffff161224 */
/* 0x000fe400078e0007 */
/*0440*/ @P1 FFMA R13, R14, R20, R29 ; /* 0x000000140e0d1223 */
/* 0x001fc8000000001d */
/*0450*/ @P1 FFMA R29, R12, R16, R13 ; /* 0x000000100c1d1223 */
/* 0x002fe2000000000d */
/*0460*/ @!P2 BRA 0x7b0 ; /* 0x000003400000a947 */
/* 0x000fea0003800000 */
/*0470*/ IADD3 R28, R27.reuse, R9, R22.reuse ; /* 0x000000091b1c7210 */
/* 0x140fe20007ffe016 */
/*0480*/ IMAD.IADD R4, R10, 0x1, R22.reuse ; /* 0x000000010a047824 */
/* 0x100fe200078e0216 */
/*0490*/ IADD3 R14, R27, R2, R22 ; /* 0x000000021b0e7210 */
/* 0x000fe40007ffe016 */
/*04a0*/ IADD3 R27, R22, -0x1, RZ ; /* 0xffffffff161b7810 */
/* 0x000fe40007ffe0ff */
/*04b0*/ IADD3 R12, R4, -0x3, RZ ; /* 0xfffffffd040c7810 */
/* 0x000fc80007ffe0ff */
/*04c0*/ IMNMX.U32 R13, R12, UR5, PT ; /* 0x000000050c0d7c17 */
/* 0x000fca000b800000 */
/*04d0*/ IMAD R13, R26, c[0x0][0x170], R13 ; /* 0x00005c001a0d7a24 */
/* 0x000fca00078e020d */
/*04e0*/ IADD3 R12, P1, R13, c[0x0][0x160], RZ ; /* 0x000058000d0c7a10 */
/* 0x000fca0007f3e0ff */
/*04f0*/ IMAD.X R13, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff0d7624 */
/* 0x000fca00008e06ff */
/*0500*/ LDG.E.U8 R20, [R12.64] ; /* 0x000000080c147981 */
/* 0x0000a2000c1e1100 */
/*0510*/ IMAD.WIDE.U32 R14, R14, R25, c[0x0][0x178] ; /* 0x00005e000e0e7625 */
/* 0x000fca00078e0019 */
/*0520*/ LDG.E R16, [R14.64] ; /* 0x000000080e107981 */
/* 0x0002e2000c1e1900 */
/*0530*/ IADD3 R17, R4.reuse, -0x2, RZ ; /* 0xfffffffe04117810 */
/* 0x040fe40007ffe0ff */
/*0540*/ IADD3 R22, R4, -0x1, RZ ; /* 0xffffffff04167810 */
/* 0x000fe40007ffe0ff */
/*0550*/ IMNMX.U32 R21, R17, UR5, PT ; /* 0x0000000511157c17 */
/* 0x000fe4000b800000 */
/*0560*/ IMNMX.U32 R23, R22, UR5, PT ; /* 0x0000000516177c17 */
/* 0x000fe4000b800000 */
/*0570*/ IMNMX.U32 R22, R4, UR5, PT ; /* 0x0000000504167c17 */
/* 0x000fe2000b800000 */
/*0580*/ IMAD R21, R26, c[0x0][0x170], R21 ; /* 0x00005c001a157a24 */
/* 0x000fc400078e0215 */
/*0590*/ IMAD R23, R26.reuse, c[0x0][0x170], R23 ; /* 0x00005c001a177a24 */
/* 0x040fe400078e0217 */
/*05a0*/ IMAD R22, R26, c[0x0][0x170], R22 ; /* 0x00005c001a167a24 */
/* 0x000fe200078e0216 */
/*05b0*/ IADD3 R12, P2, R21, c[0x0][0x160], RZ ; /* 0x00005800150c7a10 */
/* 0x001fe40007f5e0ff */
/*05c0*/ IADD3 R14, P1, R23, c[0x0][0x160], RZ ; /* 0x00005800170e7a10 */
/* 0x002fc60007f3e0ff */
/*05d0*/ IMAD.X R13, RZ, RZ, c[0x0][0x164], P2 ; /* 0x00005900ff0d7624 */
/* 0x000fe400010e06ff */
/*05e0*/ IMAD.X R15, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff0f7624 */
/* 0x000fc600008e06ff */
/*05f0*/ LDG.E.U8 R12, [R12.64] ; /* 0x000000080c0c7981 */
/* 0x000128000c1e1100 */
/*0600*/ LDG.E.U8 R13, [R14.64] ; /* 0x000000080e0d7981 */
/* 0x001162000c1e1100 */
/*0610*/ I2F.U16 R17, R20 ; /* 0x0000001400117306 */
/* 0x0042e40000101000 */
/*0620*/ IADD3 R20, R28, -0x2, RZ ; /* 0xfffffffe1c147810 */
/* 0x002fe20007ffe0ff */
/*0630*/ FFMA R29, R17, R16, R29 ; /* 0x00000010111d7223 */
/* 0x008fe2000000001d */
/*0640*/ IADD3 R16, P2, R22, c[0x0][0x160], RZ ; /* 0x0000580016107a10 */
/* 0x000fca0007f5e0ff */
/*0650*/ IMAD.X R17, RZ, RZ, c[0x0][0x164], P2 ; /* 0x00005900ff117624 */
/* 0x000fe400010e06ff */
/*0660*/ IMAD.WIDE.U32 R14, R20, R25.reuse, c[0x0][0x178] ; /* 0x00005e00140e7625 */
/* 0x081fe200078e0019 */
/*0670*/ IADD3 R20, R28, -0x1, RZ ; /* 0xffffffff1c147810 */
/* 0x000fe40007ffe0ff */
/*0680*/ LDG.E.U8 R16, [R16.64] ; /* 0x0000000810107981 */
/* 0x000ea6000c1e1100 */
/*0690*/ IMAD.WIDE.U32 R20, R20, R25.reuse, c[0x0][0x178] ; /* 0x00005e0014147625 */
/* 0x080fe200078e0019 */
/*06a0*/ LDG.E R14, [R14.64] ; /* 0x000000080e0e7981 */
/* 0x0000e6000c1e1900 */
/*06b0*/ IMAD.WIDE.U32 R22, R28, R25, c[0x0][0x178] ; /* 0x00005e001c167625 */
/* 0x000fc400078e0019 */
/*06c0*/ LDG.E R20, [R20.64] ; /* 0x0000000814147981 */
/* 0x000ee8000c1e1900 */
/*06d0*/ LDG.E R22, [R22.64] ; /* 0x0000000816167981 */
/* 0x000ee2000c1e1900 */
/*06e0*/ I2F.U16 R12, R12 ; /* 0x0000000c000c7306 */
/* 0x010ee20000101000 */
/*06f0*/ IADD3 R27, R27, 0x4, RZ ; /* 0x000000041b1b7810 */
/* 0x000fce0007ffe0ff */
/*0700*/ I2F.U16 R13, R13 ; /* 0x0000000d000d7306 */
/* 0x020e620000101000 */
/*0710*/ ISETP.GE.AND P1, PT, R27, R2, PT ; /* 0x000000021b00720c */
/* 0x000fe40003f26270 */
/*0720*/ IADD3 R15, R28, 0x4, RZ ; /* 0x000000041c0f7810 */
/* 0x001fe40007ffe0ff */
/*0730*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0740*/ I2F.U16 R16, R16 ; /* 0x0000001000107306 */
/* 0x004e220000101000 */
/*0750*/ FFMA R29, R12, R14, R29 ; /* 0x0000000e0c1d7223 */
/* 0x008fe2000000001d */
/*0760*/ IADD3 R14, R28, 0x1, RZ ; /* 0x000000011c0e7810 */
/* 0x000fc60007ffe0ff */
/*0770*/ FFMA R29, R13, R20, R29 ; /* 0x000000140d1d7223 */
/* 0x002fe4000000001d */
/*0780*/ IMAD.MOV.U32 R28, RZ, RZ, R15 ; /* 0x000000ffff1c7224 */
/* 0x000fe400078e000f */
/*0790*/ FFMA R29, R16, R22, R29 ; /* 0x00000016101d7223 */
/* 0x001fe2000000001d */
/*07a0*/ @!P1 BRA 0x4b0 ; /* 0xfffffd0000009947 */
/* 0x000fea000383ffff */
/*07b0*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fe20007ffe0ff */
/*07c0*/ @!P0 BRA 0x220 ; /* 0xfffffa5000008947 */
/* 0x000fea000383ffff */
/*07d0*/ F2I.U32.TRUNC.NTZ R29, R29 ; /* 0x0000001d001d7305 */
/* 0x000e22000020f000 */
/*07e0*/ IMAD R3, R0, c[0x0][0x170], R3 ; /* 0x00005c0000037a24 */
/* 0x000fca00078e0203 */
/*07f0*/ IADD3 R2, P0, R3, c[0x0][0x168], RZ ; /* 0x00005a0003027a10 */
/* 0x000fca0007f1e0ff */
/*0800*/ IMAD.X R3, RZ, RZ, c[0x0][0x16c], P0 ; /* 0x00005b00ff037624 */
/* 0x000fca00000e06ff */
/*0810*/ STG.E.U8 [R2.64], R29 ; /* 0x0000001d02007986 */
/* 0x001fe2000c101108 */
/*0820*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0830*/ BRA 0x830; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11applyFilterPKhPhjjPKfj
.globl _Z11applyFilterPKhPhjjPKfj
.p2align 8
.type _Z11applyFilterPKhPhjjPKfj,@function
_Z11applyFilterPKhPhjjPKfj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[4:5], s[0:1], 0x10
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_mul_i32 s14, s14, s3
v_mad_u64_u32 v[0:1], null, s15, s2, v[2:3]
v_add_nc_u32_e32 v1, s14, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_u32_e64 s2, s4, v1
v_cmp_gt_u32_e32 vcc_lo, s5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_7
s_clause 0x2
s_load_b32 s10, s[0:1], 0x20
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[6:7], s[0:1], 0x18
v_mov_b32_e32 v2, 0
s_mov_b32 s9, 0
s_add_i32 s5, s5, -1
s_add_i32 s12, s4, -1
s_mov_b32 s15, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s11, s10, 1
s_or_b32 s14, s10, 1
v_subrev_nc_u32_e32 v3, s11, v1
s_sub_i32 s13, 0, s11
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
v_add_nc_u32_e32 v4, s13, v0
s_mov_b32 s8, s15
s_mov_b32 s16, s14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_u32_e32 v4, s5, v4
v_cvt_f64_u32_e32 v[4:5], v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_f64 v[4:5], v[4:5], 0
v_cvt_u32_f64_e32 v4, v[4:5]
v_mov_b32_e32 v5, v3
s_delay_alu instid0(VALU_DEP_2)
v_mul_lo_u32 v4, v4, s4
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_min_u32_e32 v6, s12, v5
s_lshl_b64 s[18:19], s[8:9], 2
s_add_u32 s18, s6, s18
s_addc_u32 s19, s7, s19
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_cvt_f64_u32_e32 v[6:7], v6
s_load_b32 s17, s[18:19], 0x0
s_add_i32 s16, s16, -1
s_add_i32 s8, s8, 1
s_cmp_eq_u32 s16, 0
v_max_f64 v[6:7], v[6:7], 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f64_e32 v6, v[6:7]
v_add_nc_u32_e32 v6, v4, v6
global_load_u8 v6, v6, s[2:3]
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v6, v6
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_dual_fmac_f32 v2, s17, v6 :: v_dual_add_nc_u32 v5, 1, v5
s_cbranch_scc0 .LBB0_3
s_add_i32 s8, s13, 1
s_add_i32 s15, s15, s10
s_cmp_eq_u32 s13, s11
s_cbranch_scc1 .LBB0_6
s_mov_b32 s13, s8
s_branch .LBB0_2
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x8
v_mad_u64_u32 v[3:4], null, v0, s4, v[1:2]
v_cvt_i32_f32_e32 v0, v2
s_waitcnt lgkmcnt(0)
global_store_b8 v3, v0, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11applyFilterPKhPhjjPKfj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11applyFilterPKhPhjjPKfj, .Lfunc_end0-_Z11applyFilterPKhPhjjPKfj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11applyFilterPKhPhjjPKfj
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z11applyFilterPKhPhjjPKfj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00183577_00000000-6_gaussian_blur.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z11applyFilterPKhPhjjPKfjPKhPhjjPKfj
.type _Z40__device_stub__Z11applyFilterPKhPhjjPKfjPKhPhjjPKfj, @function
_Z40__device_stub__Z11applyFilterPKhPhjjPKfjPKhPhjjPKfj:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movq %r8, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11applyFilterPKhPhjjPKfj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z11applyFilterPKhPhjjPKfjPKhPhjjPKfj, .-_Z40__device_stub__Z11applyFilterPKhPhjjPKfjPKhPhjjPKfj
.globl _Z11applyFilterPKhPhjjPKfj
.type _Z11applyFilterPKhPhjjPKfj, @function
_Z11applyFilterPKhPhjjPKfj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z11applyFilterPKhPhjjPKfjPKhPhjjPKfj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11applyFilterPKhPhjjPKfj, .-_Z11applyFilterPKhPhjjPKfj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11applyFilterPKhPhjjPKfj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11applyFilterPKhPhjjPKfj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gaussian_blur.hip"
.globl _Z26__device_stub__applyFilterPKhPhjjPKfj # -- Begin function _Z26__device_stub__applyFilterPKhPhjjPKfj
.p2align 4, 0x90
.type _Z26__device_stub__applyFilterPKhPhjjPKfj,@function
_Z26__device_stub__applyFilterPKhPhjjPKfj: # @_Z26__device_stub__applyFilterPKhPhjjPKfj
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movq %r8, 72(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11applyFilterPKhPhjjPKfj, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z26__device_stub__applyFilterPKhPhjjPKfj, .Lfunc_end0-_Z26__device_stub__applyFilterPKhPhjjPKfj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11applyFilterPKhPhjjPKfj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11applyFilterPKhPhjjPKfj,@object # @_Z11applyFilterPKhPhjjPKfj
.section .rodata,"a",@progbits
.globl _Z11applyFilterPKhPhjjPKfj
.p2align 3, 0x0
_Z11applyFilterPKhPhjjPKfj:
.quad _Z26__device_stub__applyFilterPKhPhjjPKfj
.size _Z11applyFilterPKhPhjjPKfj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11applyFilterPKhPhjjPKfj"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__applyFilterPKhPhjjPKfj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11applyFilterPKhPhjjPKfj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* Copyright 2017-2022 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*
*/
#include <cuda_runtime.h>
#include <stdint.h>
#include <stdio.h>
static __global__ void ConvertUInt8ToUInt16Kernel(uint8_t *dpUInt8, uint16_t *dpUInt16, int nSrcPitch, int nDestPitch, int nWidth, int nHeight)
{
int x = blockIdx.x * blockDim.x + threadIdx.x,
y = blockIdx.y * blockDim.y + threadIdx.y;
if (x >= nWidth || y >= nHeight)
{
return;
}
int destStrideInPixels = nDestPitch / (sizeof(uint16_t));
*(uchar2 *)&dpUInt16[y * destStrideInPixels + x] = uchar2{ 0, dpUInt8[y * nSrcPitch + x] };
}
static __global__ void ConvertUInt16ToUInt8Kernel(uint16_t *dpUInt16, uint8_t *dpUInt8, int nSrcPitch, int nDestPitch, int nWidth, int nHeight)
{
int x = blockIdx.x * blockDim.x + threadIdx.x,
y = blockIdx.y * blockDim.y + threadIdx.y;
if (x >= nWidth || y >= nHeight)
{
return;
}
int srcStrideInPixels = nSrcPitch / (sizeof(uint16_t));
dpUInt8[y * nDestPitch + x] = ((uchar2 *)&dpUInt16[y * srcStrideInPixels + x])->y;
}
void ConvertUInt8ToUInt16(uint8_t *dpUInt8, uint16_t *dpUInt16, int nSrcPitch, int nDestPitch, int nWidth, int nHeight)
{
dim3 blockSize(16, 16, 1);
dim3 gridSize(((uint32_t)nWidth + blockSize.x - 1) / blockSize.x, ((uint32_t)nHeight + blockSize.y - 1) / blockSize.y, 1);
ConvertUInt8ToUInt16Kernel <<< gridSize, blockSize >>>(dpUInt8, dpUInt16, nSrcPitch, nDestPitch, nWidth, nHeight);
}
void ConvertUInt16ToUInt8(uint16_t *dpUInt16, uint8_t *dpUInt8, int nSrcPitch, int nDestPitch, int nWidth, int nHeight)
{
dim3 blockSize(16, 16, 1);
dim3 gridSize(((uint32_t)nWidth + blockSize.x - 1) / blockSize.x, ((uint32_t)nHeight + blockSize.y - 1) / blockSize.y, 1);
ConvertUInt16ToUInt8Kernel <<<gridSize, blockSize >>>(dpUInt16, dpUInt8, nSrcPitch, nDestPitch, nWidth, nHeight);
} | code for sm_80
Function : _Z26ConvertUInt16ToUInt8KernelPtPhiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x17c], PT ; /* 0x00005f0005007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000800 */
/*00b0*/ HFMA2.MMA R3, -RZ, RZ, 0, 1.1920928955078125e-07 ; /* 0x00000002ff037435 */
/* 0x000fe200000001ff */
/*00c0*/ USHF.R.S32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011404 */
/*00d0*/ IMAD R2, R5, UR4, R0 ; /* 0x0000000405027c24 */
/* 0x000fe2000f8e0200 */
/*00e0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00f0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0203 */
/*0100*/ LDG.E.U8 R3, [R2.64+0x1] ; /* 0x0000010402037981 */
/* 0x000ea2000c1e1100 */
/*0110*/ IMAD R0, R5, c[0x0][0x174], R0 ; /* 0x00005d0005007a24 */
/* 0x000fca00078e0200 */
/*0120*/ IADD3 R4, P0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000047a10 */
/* 0x000fc80007f1e0ff */
/*0130*/ LEA.HI.X.SX32 R5, R0, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0000057a11 */
/* 0x000fca00000f0eff */
/*0140*/ STG.E.U8 [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101104 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z26ConvertUInt8ToUInt16KernelPhPtiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x17c], PT ; /* 0x00005f0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD R2, R3, c[0x0][0x170], R0 ; /* 0x00005c0003027a24 */
/* 0x000fe200078e0200 */
/*00b0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc80000000a00 */
/*00c0*/ IADD3 R4, P0, R2, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x000fc80007f1e0ff */
/*00d0*/ LEA.HI.X.SX32 R5, R2, c[0x0][0x164], 0x1, P0 ; /* 0x0000590002057a11 */
/* 0x000fca00000f0eff */
/*00e0*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1100 */
/*00f0*/ ULDC UR4, c[0x0][0x174] ; /* 0x00005d0000047ab9 */
/* 0x000fe20000000800 */
/*0100*/ HFMA2.MMA R2, -RZ, RZ, 0, 1.1920928955078125e-07 ; /* 0x00000002ff027435 */
/* 0x000fe200000001ff */
/*0110*/ USHF.R.S32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011404 */
/*0120*/ IMAD R3, R3, UR4, R0 ; /* 0x0000000403037c24 */
/* 0x000fc8000f8e0200 */
/*0130*/ IMAD.WIDE R2, R3, R2, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fe200078e0202 */
/*0140*/ PRMT R7, R4, 0x7604, RZ ; /* 0x0000760404077816 */
/* 0x004fca00000000ff */
/*0150*/ STG.E.U16 [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101506 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* Copyright 2017-2022 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*
*/
#include <cuda_runtime.h>
#include <stdint.h>
#include <stdio.h>
static __global__ void ConvertUInt8ToUInt16Kernel(uint8_t *dpUInt8, uint16_t *dpUInt16, int nSrcPitch, int nDestPitch, int nWidth, int nHeight)
{
int x = blockIdx.x * blockDim.x + threadIdx.x,
y = blockIdx.y * blockDim.y + threadIdx.y;
if (x >= nWidth || y >= nHeight)
{
return;
}
int destStrideInPixels = nDestPitch / (sizeof(uint16_t));
*(uchar2 *)&dpUInt16[y * destStrideInPixels + x] = uchar2{ 0, dpUInt8[y * nSrcPitch + x] };
}
static __global__ void ConvertUInt16ToUInt8Kernel(uint16_t *dpUInt16, uint8_t *dpUInt8, int nSrcPitch, int nDestPitch, int nWidth, int nHeight)
{
int x = blockIdx.x * blockDim.x + threadIdx.x,
y = blockIdx.y * blockDim.y + threadIdx.y;
if (x >= nWidth || y >= nHeight)
{
return;
}
int srcStrideInPixels = nSrcPitch / (sizeof(uint16_t));
dpUInt8[y * nDestPitch + x] = ((uchar2 *)&dpUInt16[y * srcStrideInPixels + x])->y;
}
void ConvertUInt8ToUInt16(uint8_t *dpUInt8, uint16_t *dpUInt16, int nSrcPitch, int nDestPitch, int nWidth, int nHeight)
{
dim3 blockSize(16, 16, 1);
dim3 gridSize(((uint32_t)nWidth + blockSize.x - 1) / blockSize.x, ((uint32_t)nHeight + blockSize.y - 1) / blockSize.y, 1);
ConvertUInt8ToUInt16Kernel <<< gridSize, blockSize >>>(dpUInt8, dpUInt16, nSrcPitch, nDestPitch, nWidth, nHeight);
}
void ConvertUInt16ToUInt8(uint16_t *dpUInt16, uint8_t *dpUInt8, int nSrcPitch, int nDestPitch, int nWidth, int nHeight)
{
dim3 blockSize(16, 16, 1);
dim3 gridSize(((uint32_t)nWidth + blockSize.x - 1) / blockSize.x, ((uint32_t)nHeight + blockSize.y - 1) / blockSize.y, 1);
ConvertUInt16ToUInt8Kernel <<<gridSize, blockSize >>>(dpUInt16, dpUInt8, nSrcPitch, nDestPitch, nWidth, nHeight);
} | .file "tmpxft_000fed76_00000000-6_BitDepth.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL52__device_stub__Z26ConvertUInt8ToUInt16KernelPhPtiiiiPhPtiiii, @function
_ZL52__device_stub__Z26ConvertUInt8ToUInt16KernelPhPtiiiiPhPtiiii:
.LFB2083:
.cfi_startproc
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZL26ConvertUInt8ToUInt16KernelPhPtiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _ZL52__device_stub__Z26ConvertUInt8ToUInt16KernelPhPtiiiiPhPtiiii, .-_ZL52__device_stub__Z26ConvertUInt8ToUInt16KernelPhPtiiiiPhPtiiii
.type _ZL26ConvertUInt8ToUInt16KernelPhPtiiii, @function
_ZL26ConvertUInt8ToUInt16KernelPhPtiiii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL52__device_stub__Z26ConvertUInt8ToUInt16KernelPhPtiiiiPhPtiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL26ConvertUInt8ToUInt16KernelPhPtiiii, .-_ZL26ConvertUInt8ToUInt16KernelPhPtiiii
.type _ZL52__device_stub__Z26ConvertUInt16ToUInt8KernelPtPhiiiiPtPhiiii, @function
_ZL52__device_stub__Z26ConvertUInt16ToUInt8KernelPtPhiiiiPtPhiiii:
.LFB2085:
.cfi_startproc
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZL26ConvertUInt16ToUInt8KernelPtPhiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _ZL52__device_stub__Z26ConvertUInt16ToUInt8KernelPtPhiiiiPtPhiiii, .-_ZL52__device_stub__Z26ConvertUInt16ToUInt8KernelPtPhiiiiPtPhiiii
.type _ZL26ConvertUInt16ToUInt8KernelPtPhiiii, @function
_ZL26ConvertUInt16ToUInt8KernelPtPhiiii:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL52__device_stub__Z26ConvertUInt16ToUInt8KernelPtPhiiiiPtPhiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL26ConvertUInt16ToUInt8KernelPtPhiiii, .-_ZL26ConvertUInt16ToUInt8KernelPtPhiiii
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z20ConvertUInt8ToUInt16PhPtiiii
.type _Z20ConvertUInt8ToUInt16PhPtiiii, @function
_Z20ConvertUInt8ToUInt16PhPtiiii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r12
movq %rsi, %r13
movl %edx, %r14d
movl %ecx, %r15d
movl %r8d, %ebx
movl %r9d, %ebp
leal 15(%r8), %eax
shrl $4, %eax
movl %eax, 20(%rsp)
leal 15(%r9), %eax
shrl $4, %eax
movl %eax, 24(%rsp)
movl $16, 8(%rsp)
movl $16, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L19:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movl %ebp, %r9d
movl %ebx, %r8d
movl %r15d, %ecx
movl %r14d, %edx
movq %r13, %rsi
movq %r12, %rdi
call _ZL52__device_stub__Z26ConvertUInt8ToUInt16KernelPhPtiiiiPhPtiiii
jmp .L19
.cfi_endproc
.LFE2057:
.size _Z20ConvertUInt8ToUInt16PhPtiiii, .-_Z20ConvertUInt8ToUInt16PhPtiiii
.globl _Z20ConvertUInt16ToUInt8PtPhiiii
.type _Z20ConvertUInt16ToUInt8PtPhiiii, @function
_Z20ConvertUInt16ToUInt8PtPhiiii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r12
movq %rsi, %r13
movl %edx, %r14d
movl %ecx, %r15d
movl %r8d, %ebx
movl %r9d, %ebp
leal 15(%r8), %eax
shrl $4, %eax
movl %eax, 20(%rsp)
leal 15(%r9), %eax
shrl $4, %eax
movl %eax, 24(%rsp)
movl $16, 8(%rsp)
movl $16, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L23:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movl %ebp, %r9d
movl %ebx, %r8d
movl %r15d, %ecx
movl %r14d, %edx
movq %r13, %rsi
movq %r12, %rdi
call _ZL52__device_stub__Z26ConvertUInt16ToUInt8KernelPtPhiiiiPtPhiiii
jmp .L23
.cfi_endproc
.LFE2058:
.size _Z20ConvertUInt16ToUInt8PtPhiiii, .-_Z20ConvertUInt16ToUInt8PtPhiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26ConvertUInt16ToUInt8KernelPtPhiiii"
.align 8
.LC1:
.string "_Z26ConvertUInt8ToUInt16KernelPhPtiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL26ConvertUInt16ToUInt8KernelPtPhiiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL26ConvertUInt8ToUInt16KernelPhPtiiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* Copyright 2017-2022 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*
*/
#include <cuda_runtime.h>
#include <stdint.h>
#include <stdio.h>
static __global__ void ConvertUInt8ToUInt16Kernel(uint8_t *dpUInt8, uint16_t *dpUInt16, int nSrcPitch, int nDestPitch, int nWidth, int nHeight)
{
int x = blockIdx.x * blockDim.x + threadIdx.x,
y = blockIdx.y * blockDim.y + threadIdx.y;
if (x >= nWidth || y >= nHeight)
{
return;
}
int destStrideInPixels = nDestPitch / (sizeof(uint16_t));
*(uchar2 *)&dpUInt16[y * destStrideInPixels + x] = uchar2{ 0, dpUInt8[y * nSrcPitch + x] };
}
static __global__ void ConvertUInt16ToUInt8Kernel(uint16_t *dpUInt16, uint8_t *dpUInt8, int nSrcPitch, int nDestPitch, int nWidth, int nHeight)
{
int x = blockIdx.x * blockDim.x + threadIdx.x,
y = blockIdx.y * blockDim.y + threadIdx.y;
if (x >= nWidth || y >= nHeight)
{
return;
}
int srcStrideInPixels = nSrcPitch / (sizeof(uint16_t));
dpUInt8[y * nDestPitch + x] = ((uchar2 *)&dpUInt16[y * srcStrideInPixels + x])->y;
}
void ConvertUInt8ToUInt16(uint8_t *dpUInt8, uint16_t *dpUInt16, int nSrcPitch, int nDestPitch, int nWidth, int nHeight)
{
dim3 blockSize(16, 16, 1);
dim3 gridSize(((uint32_t)nWidth + blockSize.x - 1) / blockSize.x, ((uint32_t)nHeight + blockSize.y - 1) / blockSize.y, 1);
ConvertUInt8ToUInt16Kernel <<< gridSize, blockSize >>>(dpUInt8, dpUInt16, nSrcPitch, nDestPitch, nWidth, nHeight);
}
void ConvertUInt16ToUInt8(uint16_t *dpUInt16, uint8_t *dpUInt8, int nSrcPitch, int nDestPitch, int nWidth, int nHeight)
{
dim3 blockSize(16, 16, 1);
dim3 gridSize(((uint32_t)nWidth + blockSize.x - 1) / blockSize.x, ((uint32_t)nHeight + blockSize.y - 1) / blockSize.y, 1);
ConvertUInt16ToUInt8Kernel <<<gridSize, blockSize >>>(dpUInt16, dpUInt8, nSrcPitch, nDestPitch, nWidth, nHeight);
} | /*
* Copyright 2017-2022 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*
*/
#include <hip/hip_runtime.h>
#include <stdint.h>
#include <stdio.h>
static __global__ void ConvertUInt8ToUInt16Kernel(uint8_t *dpUInt8, uint16_t *dpUInt16, int nSrcPitch, int nDestPitch, int nWidth, int nHeight)
{
int x = blockIdx.x * blockDim.x + threadIdx.x,
y = blockIdx.y * blockDim.y + threadIdx.y;
if (x >= nWidth || y >= nHeight)
{
return;
}
int destStrideInPixels = nDestPitch / (sizeof(uint16_t));
*(uchar2 *)&dpUInt16[y * destStrideInPixels + x] = uchar2{ 0, dpUInt8[y * nSrcPitch + x] };
}
static __global__ void ConvertUInt16ToUInt8Kernel(uint16_t *dpUInt16, uint8_t *dpUInt8, int nSrcPitch, int nDestPitch, int nWidth, int nHeight)
{
int x = blockIdx.x * blockDim.x + threadIdx.x,
y = blockIdx.y * blockDim.y + threadIdx.y;
if (x >= nWidth || y >= nHeight)
{
return;
}
int srcStrideInPixels = nSrcPitch / (sizeof(uint16_t));
dpUInt8[y * nDestPitch + x] = ((uchar2 *)&dpUInt16[y * srcStrideInPixels + x])->y;
}
void ConvertUInt8ToUInt16(uint8_t *dpUInt8, uint16_t *dpUInt16, int nSrcPitch, int nDestPitch, int nWidth, int nHeight)
{
dim3 blockSize(16, 16, 1);
dim3 gridSize(((uint32_t)nWidth + blockSize.x - 1) / blockSize.x, ((uint32_t)nHeight + blockSize.y - 1) / blockSize.y, 1);
ConvertUInt8ToUInt16Kernel <<< gridSize, blockSize >>>(dpUInt8, dpUInt16, nSrcPitch, nDestPitch, nWidth, nHeight);
}
void ConvertUInt16ToUInt8(uint16_t *dpUInt16, uint8_t *dpUInt8, int nSrcPitch, int nDestPitch, int nWidth, int nHeight)
{
dim3 blockSize(16, 16, 1);
dim3 gridSize(((uint32_t)nWidth + blockSize.x - 1) / blockSize.x, ((uint32_t)nHeight + blockSize.y - 1) / blockSize.y, 1);
ConvertUInt16ToUInt8Kernel <<<gridSize, blockSize >>>(dpUInt16, dpUInt8, nSrcPitch, nDestPitch, nWidth, nHeight);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* Copyright 2017-2022 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*
*/
#include <hip/hip_runtime.h>
#include <stdint.h>
#include <stdio.h>
static __global__ void ConvertUInt8ToUInt16Kernel(uint8_t *dpUInt8, uint16_t *dpUInt16, int nSrcPitch, int nDestPitch, int nWidth, int nHeight)
{
int x = blockIdx.x * blockDim.x + threadIdx.x,
y = blockIdx.y * blockDim.y + threadIdx.y;
if (x >= nWidth || y >= nHeight)
{
return;
}
int destStrideInPixels = nDestPitch / (sizeof(uint16_t));
*(uchar2 *)&dpUInt16[y * destStrideInPixels + x] = uchar2{ 0, dpUInt8[y * nSrcPitch + x] };
}
static __global__ void ConvertUInt16ToUInt8Kernel(uint16_t *dpUInt16, uint8_t *dpUInt8, int nSrcPitch, int nDestPitch, int nWidth, int nHeight)
{
int x = blockIdx.x * blockDim.x + threadIdx.x,
y = blockIdx.y * blockDim.y + threadIdx.y;
if (x >= nWidth || y >= nHeight)
{
return;
}
int srcStrideInPixels = nSrcPitch / (sizeof(uint16_t));
dpUInt8[y * nDestPitch + x] = ((uchar2 *)&dpUInt16[y * srcStrideInPixels + x])->y;
}
void ConvertUInt8ToUInt16(uint8_t *dpUInt8, uint16_t *dpUInt16, int nSrcPitch, int nDestPitch, int nWidth, int nHeight)
{
dim3 blockSize(16, 16, 1);
dim3 gridSize(((uint32_t)nWidth + blockSize.x - 1) / blockSize.x, ((uint32_t)nHeight + blockSize.y - 1) / blockSize.y, 1);
ConvertUInt8ToUInt16Kernel <<< gridSize, blockSize >>>(dpUInt8, dpUInt16, nSrcPitch, nDestPitch, nWidth, nHeight);
}
void ConvertUInt16ToUInt8(uint16_t *dpUInt16, uint8_t *dpUInt8, int nSrcPitch, int nDestPitch, int nWidth, int nHeight)
{
dim3 blockSize(16, 16, 1);
dim3 gridSize(((uint32_t)nWidth + blockSize.x - 1) / blockSize.x, ((uint32_t)nHeight + blockSize.y - 1) / blockSize.y, 1);
ConvertUInt16ToUInt8Kernel <<<gridSize, blockSize >>>(dpUInt16, dpUInt8, nSrcPitch, nDestPitch, nWidth, nHeight);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL26ConvertUInt8ToUInt16KernelPhPtiiii,"axG",@progbits,_ZL26ConvertUInt8ToUInt16KernelPhPtiiii,comdat
.globl _ZL26ConvertUInt8ToUInt16KernelPhPtiiii
.p2align 8
.type _ZL26ConvertUInt8ToUInt16KernelPhPtiiii,@function
_ZL26ConvertUInt8ToUInt16KernelPhPtiiii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_add_co_u32 v2, vcc_lo, s0, v2
s_ashr_i32 s0, s5, 1
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_u8 v4, v[2:3], off
v_mad_u64_u32 v[2:3], null, v1, s0, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 1, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
v_lshlrev_b16 v2, 8, v4
global_store_b16 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL26ConvertUInt8ToUInt16KernelPhPtiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL26ConvertUInt8ToUInt16KernelPhPtiiii,"axG",@progbits,_ZL26ConvertUInt8ToUInt16KernelPhPtiiii,comdat
.Lfunc_end0:
.size _ZL26ConvertUInt8ToUInt16KernelPhPtiiii, .Lfunc_end0-_ZL26ConvertUInt8ToUInt16KernelPhPtiiii
.section .AMDGPU.csdata,"",@progbits
.section .text._ZL26ConvertUInt16ToUInt8KernelPtPhiiii,"axG",@progbits,_ZL26ConvertUInt16ToUInt8KernelPtPhiiii,comdat
.globl _ZL26ConvertUInt16ToUInt8KernelPtPhiiii
.p2align 8
.type _ZL26ConvertUInt16ToUInt8KernelPtPhiiii,@function
_ZL26ConvertUInt16ToUInt8KernelPtPhiiii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 1, v[2:3]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_u8 v4, v[2:3], off offset:1
v_mad_u64_u32 v[2:3], null, v1, s5, v[0:1]
v_ashrrev_i32_e32 v1, 31, v2
v_add_co_u32 v0, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b8 v[0:1], v4, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL26ConvertUInt16ToUInt8KernelPtPhiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL26ConvertUInt16ToUInt8KernelPtPhiiii,"axG",@progbits,_ZL26ConvertUInt16ToUInt8KernelPtPhiiii,comdat
.Lfunc_end1:
.size _ZL26ConvertUInt16ToUInt8KernelPtPhiiii, .Lfunc_end1-_ZL26ConvertUInt16ToUInt8KernelPtPhiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL26ConvertUInt8ToUInt16KernelPhPtiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZL26ConvertUInt8ToUInt16KernelPhPtiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL26ConvertUInt16ToUInt8KernelPtPhiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZL26ConvertUInt16ToUInt8KernelPtPhiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* Copyright 2017-2022 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*
*/
#include <hip/hip_runtime.h>
#include <stdint.h>
#include <stdio.h>
static __global__ void ConvertUInt8ToUInt16Kernel(uint8_t *dpUInt8, uint16_t *dpUInt16, int nSrcPitch, int nDestPitch, int nWidth, int nHeight)
{
int x = blockIdx.x * blockDim.x + threadIdx.x,
y = blockIdx.y * blockDim.y + threadIdx.y;
if (x >= nWidth || y >= nHeight)
{
return;
}
int destStrideInPixels = nDestPitch / (sizeof(uint16_t));
*(uchar2 *)&dpUInt16[y * destStrideInPixels + x] = uchar2{ 0, dpUInt8[y * nSrcPitch + x] };
}
static __global__ void ConvertUInt16ToUInt8Kernel(uint16_t *dpUInt16, uint8_t *dpUInt8, int nSrcPitch, int nDestPitch, int nWidth, int nHeight)
{
int x = blockIdx.x * blockDim.x + threadIdx.x,
y = blockIdx.y * blockDim.y + threadIdx.y;
if (x >= nWidth || y >= nHeight)
{
return;
}
int srcStrideInPixels = nSrcPitch / (sizeof(uint16_t));
dpUInt8[y * nDestPitch + x] = ((uchar2 *)&dpUInt16[y * srcStrideInPixels + x])->y;
}
void ConvertUInt8ToUInt16(uint8_t *dpUInt8, uint16_t *dpUInt16, int nSrcPitch, int nDestPitch, int nWidth, int nHeight)
{
dim3 blockSize(16, 16, 1);
dim3 gridSize(((uint32_t)nWidth + blockSize.x - 1) / blockSize.x, ((uint32_t)nHeight + blockSize.y - 1) / blockSize.y, 1);
ConvertUInt8ToUInt16Kernel <<< gridSize, blockSize >>>(dpUInt8, dpUInt16, nSrcPitch, nDestPitch, nWidth, nHeight);
}
void ConvertUInt16ToUInt8(uint16_t *dpUInt16, uint8_t *dpUInt8, int nSrcPitch, int nDestPitch, int nWidth, int nHeight)
{
dim3 blockSize(16, 16, 1);
dim3 gridSize(((uint32_t)nWidth + blockSize.x - 1) / blockSize.x, ((uint32_t)nHeight + blockSize.y - 1) / blockSize.y, 1);
ConvertUInt16ToUInt8Kernel <<<gridSize, blockSize >>>(dpUInt16, dpUInt8, nSrcPitch, nDestPitch, nWidth, nHeight);
} | .text
.file "BitDepth.hip"
.globl _Z20ConvertUInt8ToUInt16PhPtiiii # -- Begin function _Z20ConvertUInt8ToUInt16PhPtiiii
.p2align 4, 0x90
.type _Z20ConvertUInt8ToUInt16PhPtiiii,@function
_Z20ConvertUInt8ToUInt16PhPtiiii: # @_Z20ConvertUInt8ToUInt16PhPtiiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %ebx
movl %r8d, %r14d
movl %ecx, %ebp
movl %edx, %r15d
movq %rsi, %r12
movq %rdi, %r13
leal 15(%r14), %eax
shrl $4, %eax
leal 15(%rbx), %edi
shrl $4, %edi
shlq $32, %rdi
orq %rax, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
movq %r13, 72(%rsp)
movq %r12, 64(%rsp)
movl %r15d, 12(%rsp)
movl %ebp, 8(%rsp)
movl %r14d, 4(%rsp)
movl %ebx, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZL26ConvertUInt8ToUInt16KernelPhPtiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_2:
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z20ConvertUInt8ToUInt16PhPtiiii, .Lfunc_end0-_Z20ConvertUInt8ToUInt16PhPtiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL41__device_stub__ConvertUInt8ToUInt16KernelPhPtiiii
.type _ZL41__device_stub__ConvertUInt8ToUInt16KernelPhPtiiii,@function
_ZL41__device_stub__ConvertUInt8ToUInt16KernelPhPtiiii: # @_ZL41__device_stub__ConvertUInt8ToUInt16KernelPhPtiiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZL26ConvertUInt8ToUInt16KernelPhPtiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end1:
.size _ZL41__device_stub__ConvertUInt8ToUInt16KernelPhPtiiii, .Lfunc_end1-_ZL41__device_stub__ConvertUInt8ToUInt16KernelPhPtiiii
.cfi_endproc
# -- End function
.globl _Z20ConvertUInt16ToUInt8PtPhiiii # -- Begin function _Z20ConvertUInt16ToUInt8PtPhiiii
.p2align 4, 0x90
.type _Z20ConvertUInt16ToUInt8PtPhiiii,@function
_Z20ConvertUInt16ToUInt8PtPhiiii: # @_Z20ConvertUInt16ToUInt8PtPhiiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %ebx
movl %r8d, %r14d
movl %ecx, %ebp
movl %edx, %r15d
movq %rsi, %r12
movq %rdi, %r13
leal 15(%r14), %eax
shrl $4, %eax
leal 15(%rbx), %edi
shrl $4, %edi
shlq $32, %rdi
orq %rax, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq %r13, 72(%rsp)
movq %r12, 64(%rsp)
movl %r15d, 12(%rsp)
movl %ebp, 8(%rsp)
movl %r14d, 4(%rsp)
movl %ebx, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZL26ConvertUInt16ToUInt8KernelPtPhiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z20ConvertUInt16ToUInt8PtPhiiii, .Lfunc_end2-_Z20ConvertUInt16ToUInt8PtPhiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL41__device_stub__ConvertUInt16ToUInt8KernelPtPhiiii
.type _ZL41__device_stub__ConvertUInt16ToUInt8KernelPtPhiiii,@function
_ZL41__device_stub__ConvertUInt16ToUInt8KernelPtPhiiii: # @_ZL41__device_stub__ConvertUInt16ToUInt8KernelPtPhiiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZL26ConvertUInt16ToUInt8KernelPtPhiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end3:
.size _ZL41__device_stub__ConvertUInt16ToUInt8KernelPtPhiiii, .Lfunc_end3-_ZL41__device_stub__ConvertUInt16ToUInt8KernelPtPhiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZL26ConvertUInt8ToUInt16KernelPhPtiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZL26ConvertUInt16ToUInt8KernelPtPhiiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _ZL26ConvertUInt8ToUInt16KernelPhPtiiii,@object # @_ZL26ConvertUInt8ToUInt16KernelPhPtiiii
.section .rodata,"a",@progbits
.p2align 3, 0x0
_ZL26ConvertUInt8ToUInt16KernelPhPtiiii:
.quad _ZL41__device_stub__ConvertUInt8ToUInt16KernelPhPtiiii
.size _ZL26ConvertUInt8ToUInt16KernelPhPtiiii, 8
.type _ZL26ConvertUInt16ToUInt8KernelPtPhiiii,@object # @_ZL26ConvertUInt16ToUInt8KernelPtPhiiii
.p2align 3, 0x0
_ZL26ConvertUInt16ToUInt8KernelPtPhiiii:
.quad _ZL41__device_stub__ConvertUInt16ToUInt8KernelPtPhiiii
.size _ZL26ConvertUInt16ToUInt8KernelPtPhiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_ZL26ConvertUInt8ToUInt16KernelPhPtiiii"
.size .L__unnamed_1, 40
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_ZL26ConvertUInt16ToUInt8KernelPtPhiiii"
.size .L__unnamed_2, 40
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZL41__device_stub__ConvertUInt8ToUInt16KernelPhPtiiii
.addrsig_sym _ZL41__device_stub__ConvertUInt16ToUInt8KernelPtPhiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZL26ConvertUInt8ToUInt16KernelPhPtiiii
.addrsig_sym _ZL26ConvertUInt16ToUInt8KernelPtPhiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z26ConvertUInt16ToUInt8KernelPtPhiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x17c], PT ; /* 0x00005f0005007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000800 */
/*00b0*/ HFMA2.MMA R3, -RZ, RZ, 0, 1.1920928955078125e-07 ; /* 0x00000002ff037435 */
/* 0x000fe200000001ff */
/*00c0*/ USHF.R.S32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011404 */
/*00d0*/ IMAD R2, R5, UR4, R0 ; /* 0x0000000405027c24 */
/* 0x000fe2000f8e0200 */
/*00e0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00f0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0203 */
/*0100*/ LDG.E.U8 R3, [R2.64+0x1] ; /* 0x0000010402037981 */
/* 0x000ea2000c1e1100 */
/*0110*/ IMAD R0, R5, c[0x0][0x174], R0 ; /* 0x00005d0005007a24 */
/* 0x000fca00078e0200 */
/*0120*/ IADD3 R4, P0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000047a10 */
/* 0x000fc80007f1e0ff */
/*0130*/ LEA.HI.X.SX32 R5, R0, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0000057a11 */
/* 0x000fca00000f0eff */
/*0140*/ STG.E.U8 [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101104 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z26ConvertUInt8ToUInt16KernelPhPtiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x17c], PT ; /* 0x00005f0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD R2, R3, c[0x0][0x170], R0 ; /* 0x00005c0003027a24 */
/* 0x000fe200078e0200 */
/*00b0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc80000000a00 */
/*00c0*/ IADD3 R4, P0, R2, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x000fc80007f1e0ff */
/*00d0*/ LEA.HI.X.SX32 R5, R2, c[0x0][0x164], 0x1, P0 ; /* 0x0000590002057a11 */
/* 0x000fca00000f0eff */
/*00e0*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1100 */
/*00f0*/ ULDC UR4, c[0x0][0x174] ; /* 0x00005d0000047ab9 */
/* 0x000fe20000000800 */
/*0100*/ HFMA2.MMA R2, -RZ, RZ, 0, 1.1920928955078125e-07 ; /* 0x00000002ff027435 */
/* 0x000fe200000001ff */
/*0110*/ USHF.R.S32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011404 */
/*0120*/ IMAD R3, R3, UR4, R0 ; /* 0x0000000403037c24 */
/* 0x000fc8000f8e0200 */
/*0130*/ IMAD.WIDE R2, R3, R2, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fe200078e0202 */
/*0140*/ PRMT R7, R4, 0x7604, RZ ; /* 0x0000760404077816 */
/* 0x004fca00000000ff */
/*0150*/ STG.E.U16 [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101506 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL26ConvertUInt8ToUInt16KernelPhPtiiii,"axG",@progbits,_ZL26ConvertUInt8ToUInt16KernelPhPtiiii,comdat
.globl _ZL26ConvertUInt8ToUInt16KernelPhPtiiii
.p2align 8
.type _ZL26ConvertUInt8ToUInt16KernelPhPtiiii,@function
_ZL26ConvertUInt8ToUInt16KernelPhPtiiii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_add_co_u32 v2, vcc_lo, s0, v2
s_ashr_i32 s0, s5, 1
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_u8 v4, v[2:3], off
v_mad_u64_u32 v[2:3], null, v1, s0, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 1, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
v_lshlrev_b16 v2, 8, v4
global_store_b16 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL26ConvertUInt8ToUInt16KernelPhPtiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL26ConvertUInt8ToUInt16KernelPhPtiiii,"axG",@progbits,_ZL26ConvertUInt8ToUInt16KernelPhPtiiii,comdat
.Lfunc_end0:
.size _ZL26ConvertUInt8ToUInt16KernelPhPtiiii, .Lfunc_end0-_ZL26ConvertUInt8ToUInt16KernelPhPtiiii
.section .AMDGPU.csdata,"",@progbits
.section .text._ZL26ConvertUInt16ToUInt8KernelPtPhiiii,"axG",@progbits,_ZL26ConvertUInt16ToUInt8KernelPtPhiiii,comdat
.globl _ZL26ConvertUInt16ToUInt8KernelPtPhiiii
.p2align 8
.type _ZL26ConvertUInt16ToUInt8KernelPtPhiiii,@function
_ZL26ConvertUInt16ToUInt8KernelPtPhiiii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 1, v[2:3]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_u8 v4, v[2:3], off offset:1
v_mad_u64_u32 v[2:3], null, v1, s5, v[0:1]
v_ashrrev_i32_e32 v1, 31, v2
v_add_co_u32 v0, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b8 v[0:1], v4, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL26ConvertUInt16ToUInt8KernelPtPhiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL26ConvertUInt16ToUInt8KernelPtPhiiii,"axG",@progbits,_ZL26ConvertUInt16ToUInt8KernelPtPhiiii,comdat
.Lfunc_end1:
.size _ZL26ConvertUInt16ToUInt8KernelPtPhiiii, .Lfunc_end1-_ZL26ConvertUInt16ToUInt8KernelPtPhiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL26ConvertUInt8ToUInt16KernelPhPtiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZL26ConvertUInt8ToUInt16KernelPhPtiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL26ConvertUInt16ToUInt8KernelPtPhiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZL26ConvertUInt16ToUInt8KernelPtPhiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000fed76_00000000-6_BitDepth.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL52__device_stub__Z26ConvertUInt8ToUInt16KernelPhPtiiiiPhPtiiii, @function
_ZL52__device_stub__Z26ConvertUInt8ToUInt16KernelPhPtiiiiPhPtiiii:
.LFB2083:
.cfi_startproc
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZL26ConvertUInt8ToUInt16KernelPhPtiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _ZL52__device_stub__Z26ConvertUInt8ToUInt16KernelPhPtiiiiPhPtiiii, .-_ZL52__device_stub__Z26ConvertUInt8ToUInt16KernelPhPtiiiiPhPtiiii
.type _ZL26ConvertUInt8ToUInt16KernelPhPtiiii, @function
_ZL26ConvertUInt8ToUInt16KernelPhPtiiii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL52__device_stub__Z26ConvertUInt8ToUInt16KernelPhPtiiiiPhPtiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL26ConvertUInt8ToUInt16KernelPhPtiiii, .-_ZL26ConvertUInt8ToUInt16KernelPhPtiiii
.type _ZL52__device_stub__Z26ConvertUInt16ToUInt8KernelPtPhiiiiPtPhiiii, @function
_ZL52__device_stub__Z26ConvertUInt16ToUInt8KernelPtPhiiiiPtPhiiii:
.LFB2085:
.cfi_startproc
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZL26ConvertUInt16ToUInt8KernelPtPhiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _ZL52__device_stub__Z26ConvertUInt16ToUInt8KernelPtPhiiiiPtPhiiii, .-_ZL52__device_stub__Z26ConvertUInt16ToUInt8KernelPtPhiiiiPtPhiiii
.type _ZL26ConvertUInt16ToUInt8KernelPtPhiiii, @function
_ZL26ConvertUInt16ToUInt8KernelPtPhiiii:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL52__device_stub__Z26ConvertUInt16ToUInt8KernelPtPhiiiiPtPhiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL26ConvertUInt16ToUInt8KernelPtPhiiii, .-_ZL26ConvertUInt16ToUInt8KernelPtPhiiii
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z20ConvertUInt8ToUInt16PhPtiiii
.type _Z20ConvertUInt8ToUInt16PhPtiiii, @function
_Z20ConvertUInt8ToUInt16PhPtiiii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r12
movq %rsi, %r13
movl %edx, %r14d
movl %ecx, %r15d
movl %r8d, %ebx
movl %r9d, %ebp
leal 15(%r8), %eax
shrl $4, %eax
movl %eax, 20(%rsp)
leal 15(%r9), %eax
shrl $4, %eax
movl %eax, 24(%rsp)
movl $16, 8(%rsp)
movl $16, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L19:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movl %ebp, %r9d
movl %ebx, %r8d
movl %r15d, %ecx
movl %r14d, %edx
movq %r13, %rsi
movq %r12, %rdi
call _ZL52__device_stub__Z26ConvertUInt8ToUInt16KernelPhPtiiiiPhPtiiii
jmp .L19
.cfi_endproc
.LFE2057:
.size _Z20ConvertUInt8ToUInt16PhPtiiii, .-_Z20ConvertUInt8ToUInt16PhPtiiii
.globl _Z20ConvertUInt16ToUInt8PtPhiiii
.type _Z20ConvertUInt16ToUInt8PtPhiiii, @function
_Z20ConvertUInt16ToUInt8PtPhiiii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r12
movq %rsi, %r13
movl %edx, %r14d
movl %ecx, %r15d
movl %r8d, %ebx
movl %r9d, %ebp
leal 15(%r8), %eax
shrl $4, %eax
movl %eax, 20(%rsp)
leal 15(%r9), %eax
shrl $4, %eax
movl %eax, 24(%rsp)
movl $16, 8(%rsp)
movl $16, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L23:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movl %ebp, %r9d
movl %ebx, %r8d
movl %r15d, %ecx
movl %r14d, %edx
movq %r13, %rsi
movq %r12, %rdi
call _ZL52__device_stub__Z26ConvertUInt16ToUInt8KernelPtPhiiiiPtPhiiii
jmp .L23
.cfi_endproc
.LFE2058:
.size _Z20ConvertUInt16ToUInt8PtPhiiii, .-_Z20ConvertUInt16ToUInt8PtPhiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26ConvertUInt16ToUInt8KernelPtPhiiii"
.align 8
.LC1:
.string "_Z26ConvertUInt8ToUInt16KernelPhPtiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL26ConvertUInt16ToUInt8KernelPtPhiiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL26ConvertUInt8ToUInt16KernelPhPtiiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "BitDepth.hip"
.globl _Z20ConvertUInt8ToUInt16PhPtiiii # -- Begin function _Z20ConvertUInt8ToUInt16PhPtiiii
.p2align 4, 0x90
.type _Z20ConvertUInt8ToUInt16PhPtiiii,@function
_Z20ConvertUInt8ToUInt16PhPtiiii: # @_Z20ConvertUInt8ToUInt16PhPtiiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %ebx
movl %r8d, %r14d
movl %ecx, %ebp
movl %edx, %r15d
movq %rsi, %r12
movq %rdi, %r13
leal 15(%r14), %eax
shrl $4, %eax
leal 15(%rbx), %edi
shrl $4, %edi
shlq $32, %rdi
orq %rax, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
movq %r13, 72(%rsp)
movq %r12, 64(%rsp)
movl %r15d, 12(%rsp)
movl %ebp, 8(%rsp)
movl %r14d, 4(%rsp)
movl %ebx, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZL26ConvertUInt8ToUInt16KernelPhPtiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_2:
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z20ConvertUInt8ToUInt16PhPtiiii, .Lfunc_end0-_Z20ConvertUInt8ToUInt16PhPtiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL41__device_stub__ConvertUInt8ToUInt16KernelPhPtiiii
.type _ZL41__device_stub__ConvertUInt8ToUInt16KernelPhPtiiii,@function
_ZL41__device_stub__ConvertUInt8ToUInt16KernelPhPtiiii: # @_ZL41__device_stub__ConvertUInt8ToUInt16KernelPhPtiiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZL26ConvertUInt8ToUInt16KernelPhPtiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end1:
.size _ZL41__device_stub__ConvertUInt8ToUInt16KernelPhPtiiii, .Lfunc_end1-_ZL41__device_stub__ConvertUInt8ToUInt16KernelPhPtiiii
.cfi_endproc
# -- End function
.globl _Z20ConvertUInt16ToUInt8PtPhiiii # -- Begin function _Z20ConvertUInt16ToUInt8PtPhiiii
.p2align 4, 0x90
.type _Z20ConvertUInt16ToUInt8PtPhiiii,@function
_Z20ConvertUInt16ToUInt8PtPhiiii: # @_Z20ConvertUInt16ToUInt8PtPhiiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %ebx
movl %r8d, %r14d
movl %ecx, %ebp
movl %edx, %r15d
movq %rsi, %r12
movq %rdi, %r13
leal 15(%r14), %eax
shrl $4, %eax
leal 15(%rbx), %edi
shrl $4, %edi
shlq $32, %rdi
orq %rax, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq %r13, 72(%rsp)
movq %r12, 64(%rsp)
movl %r15d, 12(%rsp)
movl %ebp, 8(%rsp)
movl %r14d, 4(%rsp)
movl %ebx, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZL26ConvertUInt16ToUInt8KernelPtPhiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z20ConvertUInt16ToUInt8PtPhiiii, .Lfunc_end2-_Z20ConvertUInt16ToUInt8PtPhiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL41__device_stub__ConvertUInt16ToUInt8KernelPtPhiiii
.type _ZL41__device_stub__ConvertUInt16ToUInt8KernelPtPhiiii,@function
_ZL41__device_stub__ConvertUInt16ToUInt8KernelPtPhiiii: # @_ZL41__device_stub__ConvertUInt16ToUInt8KernelPtPhiiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZL26ConvertUInt16ToUInt8KernelPtPhiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end3:
.size _ZL41__device_stub__ConvertUInt16ToUInt8KernelPtPhiiii, .Lfunc_end3-_ZL41__device_stub__ConvertUInt16ToUInt8KernelPtPhiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZL26ConvertUInt8ToUInt16KernelPhPtiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZL26ConvertUInt16ToUInt8KernelPtPhiiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _ZL26ConvertUInt8ToUInt16KernelPhPtiiii,@object # @_ZL26ConvertUInt8ToUInt16KernelPhPtiiii
.section .rodata,"a",@progbits
.p2align 3, 0x0
_ZL26ConvertUInt8ToUInt16KernelPhPtiiii:
.quad _ZL41__device_stub__ConvertUInt8ToUInt16KernelPhPtiiii
.size _ZL26ConvertUInt8ToUInt16KernelPhPtiiii, 8
.type _ZL26ConvertUInt16ToUInt8KernelPtPhiiii,@object # @_ZL26ConvertUInt16ToUInt8KernelPtPhiiii
.p2align 3, 0x0
_ZL26ConvertUInt16ToUInt8KernelPtPhiiii:
.quad _ZL41__device_stub__ConvertUInt16ToUInt8KernelPtPhiiii
.size _ZL26ConvertUInt16ToUInt8KernelPtPhiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_ZL26ConvertUInt8ToUInt16KernelPhPtiiii"
.size .L__unnamed_1, 40
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_ZL26ConvertUInt16ToUInt8KernelPtPhiiii"
.size .L__unnamed_2, 40
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZL41__device_stub__ConvertUInt8ToUInt16KernelPhPtiiii
.addrsig_sym _ZL41__device_stub__ConvertUInt16ToUInt8KernelPtPhiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZL26ConvertUInt8ToUInt16KernelPhPtiiii
.addrsig_sym _ZL26ConvertUInt16ToUInt8KernelPtPhiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define err 0.000001
__device__
void f(float x, float *y)
{
// *y = exp(x)-5*pow(x,2); // slide
*y = ((70 + 1.463/pow(x, 2)) * (x - 0.0394)) - (0.08314 * 215);
}
__device__
void g(float x, float *y)
{
// *y = exp(x)-10*x; // slide
*y = 70 - 1.463 + 2*1.463*0.0394;
}
__global__
void newtraph()
{
float x,xS,fx,gx,fS,gS;
x = 1;
printf("%11s %11s %11s %11s\n",
"x", "f(x)", "f'(x)", "x");
do
{
xS=x;
f(x, &fx);
g(x, &gx);
f(xS, &fS);
g(xS, &gS);
x=x-fx/gx;
printf("%11.6f %11.6f %11.6f %11.6f\n",
xS,fS,gS,x);
}
while(fabs(x-xS)>err);
printf("Hasil = %.6f\n",x);
}
int main(int argc,char **argv) {
newtraph<<<1, 1>>>();
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_00007dde_00000000-6_newton-raphson.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z1ffPf
.type _Z1ffPf, @function
_Z1ffPf:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z1ffPf, .-_Z1ffPf
.globl _Z1gfPf
.type _Z1gfPf, @function
_Z1gfPf:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z1gfPf, .-_Z1gfPf
.globl _Z26__device_stub__Z8newtraphvv
.type _Z26__device_stub__Z8newtraphvv, @function
_Z26__device_stub__Z8newtraphvv:
.LFB2084:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z8newtraphv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z26__device_stub__Z8newtraphvv, .-_Z26__device_stub__Z8newtraphvv
.globl _Z8newtraphv
.type _Z8newtraphv, @function
_Z8newtraphv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z8newtraphvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z8newtraphv, .-_Z8newtraphv
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
call _Z26__device_stub__Z8newtraphvv
jmp .L16
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8newtraphv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8newtraphv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define err 0.000001
__device__
void f(float x, float *y)
{
// *y = exp(x)-5*pow(x,2); // slide
*y = ((70 + 1.463/pow(x, 2)) * (x - 0.0394)) - (0.08314 * 215);
}
__device__
void g(float x, float *y)
{
// *y = exp(x)-10*x; // slide
*y = 70 - 1.463 + 2*1.463*0.0394;
}
__global__
void newtraph()
{
float x,xS,fx,gx,fS,gS;
x = 1;
printf("%11s %11s %11s %11s\n",
"x", "f(x)", "f'(x)", "x");
do
{
xS=x;
f(x, &fx);
g(x, &gx);
f(xS, &fS);
g(xS, &gS);
x=x-fx/gx;
printf("%11.6f %11.6f %11.6f %11.6f\n",
xS,fS,gS,x);
}
while(fabs(x-xS)>err);
printf("Hasil = %.6f\n",x);
}
int main(int argc,char **argv) {
newtraph<<<1, 1>>>();
cudaDeviceSynchronize();
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define err 0.000001
__device__
void f(float x, float *y)
{
// *y = exp(x)-5*pow(x,2); // slide
*y = ((70 + 1.463/pow(x, 2)) * (x - 0.0394)) - (0.08314 * 215);
}
__device__
void g(float x, float *y)
{
// *y = exp(x)-10*x; // slide
*y = 70 - 1.463 + 2*1.463*0.0394;
}
__global__
void newtraph()
{
float x,xS,fx,gx,fS,gS;
x = 1;
printf("%11s %11s %11s %11s\n",
"x", "f(x)", "f'(x)", "x");
do
{
xS=x;
f(x, &fx);
g(x, &gx);
f(xS, &fS);
g(xS, &gS);
x=x-fx/gx;
printf("%11.6f %11.6f %11.6f %11.6f\n",
xS,fS,gS,x);
}
while(fabs(x-xS)>err);
printf("Hasil = %.6f\n",x);
}
int main(int argc,char **argv) {
newtraph<<<1, 1>>>();
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define err 0.000001
__device__
void f(float x, float *y)
{
// *y = exp(x)-5*pow(x,2); // slide
*y = ((70 + 1.463/pow(x, 2)) * (x - 0.0394)) - (0.08314 * 215);
}
__device__
void g(float x, float *y)
{
// *y = exp(x)-10*x; // slide
*y = 70 - 1.463 + 2*1.463*0.0394;
}
__global__
void newtraph()
{
float x,xS,fx,gx,fS,gS;
x = 1;
printf("%11s %11s %11s %11s\n",
"x", "f(x)", "f'(x)", "x");
do
{
xS=x;
f(x, &fx);
g(x, &gx);
f(xS, &fS);
g(xS, &gS);
x=x-fx/gx;
printf("%11.6f %11.6f %11.6f %11.6f\n",
xS,fS,gS,x);
}
while(fabs(x-xS)>err);
printf("Hasil = %.6f\n",x);
}
int main(int argc,char **argv) {
newtraph<<<1, 1>>>();
hipDeviceSynchronize();
return 0;
} | .text
.file "newton-raphson.hip"
.globl _Z23__device_stub__newtraphv # -- Begin function _Z23__device_stub__newtraphv
.p2align 4, 0x90
.type _Z23__device_stub__newtraphv,@function
_Z23__device_stub__newtraphv: # @_Z23__device_stub__newtraphv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8newtraphv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z23__device_stub__newtraphv, .Lfunc_end0-_Z23__device_stub__newtraphv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8newtraphv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8newtraphv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8newtraphv,@object # @_Z8newtraphv
.section .rodata,"a",@progbits
.globl _Z8newtraphv
.p2align 3, 0x0
_Z8newtraphv:
.quad _Z23__device_stub__newtraphv
.size _Z8newtraphv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8newtraphv"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__newtraphv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8newtraphv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00007dde_00000000-6_newton-raphson.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z1ffPf
.type _Z1ffPf, @function
_Z1ffPf:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z1ffPf, .-_Z1ffPf
.globl _Z1gfPf
.type _Z1gfPf, @function
_Z1gfPf:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z1gfPf, .-_Z1gfPf
.globl _Z26__device_stub__Z8newtraphvv
.type _Z26__device_stub__Z8newtraphvv, @function
_Z26__device_stub__Z8newtraphvv:
.LFB2084:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z8newtraphv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z26__device_stub__Z8newtraphvv, .-_Z26__device_stub__Z8newtraphvv
.globl _Z8newtraphv
.type _Z8newtraphv, @function
_Z8newtraphv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z8newtraphvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z8newtraphv, .-_Z8newtraphv
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
call _Z26__device_stub__Z8newtraphvv
jmp .L16
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8newtraphv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8newtraphv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "newton-raphson.hip"
.globl _Z23__device_stub__newtraphv # -- Begin function _Z23__device_stub__newtraphv
.p2align 4, 0x90
.type _Z23__device_stub__newtraphv,@function
_Z23__device_stub__newtraphv: # @_Z23__device_stub__newtraphv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8newtraphv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z23__device_stub__newtraphv, .Lfunc_end0-_Z23__device_stub__newtraphv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8newtraphv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8newtraphv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8newtraphv,@object # @_Z8newtraphv
.section .rodata,"a",@progbits
.globl _Z8newtraphv
.p2align 3, 0x0
_Z8newtraphv:
.quad _Z23__device_stub__newtraphv
.size _Z8newtraphv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8newtraphv"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__newtraphv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8newtraphv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
const int INF = 10000000;
int *host_D;
int *dev_D;
int n, m;
void Input(char *inFileName) {
FILE *infile = fopen(inFileName, "r");
setvbuf(infile, new char[1 << 20], _IOFBF, 1 << 20);
fscanf(infile, "%d %d", &n, &m);
host_D = (int*)malloc(n * n * sizeof(int));
for (int i = 0; i < n; ++i) {
for (int j = 0; j < n; ++j) {
if (i == j) host_D[i * n + j] = 0;
else host_D[i * n + j] = INF;
}
}
while (--m >= 0) {
int a, b, v;
fscanf(infile, "%d %d %d", &a, &b, &v);
host_D[(a - 1) * n + (b - 1)] = v;
}
fclose(infile);
}
void Output(char *outFileName) {
FILE *outfile = fopen(outFileName, "w");
setvbuf(outfile, new char[1 << 20], _IOFBF, 1 << 20);
for (int i = 0; i < n; ++i) {
for (int j = 0; j < n; ++j) {
if (host_D[i * n + j] >= INF) fprintf(outfile, "INF ");
else fprintf(outfile, "%d ", host_D[i * n + j]);
}
fprintf(outfile, "\n");
}
fclose(outfile);
}
__global__ void func1(int n, int B, int k, int* arr) {
extern __shared__ int shared_memory[];
int* dBlock = shared_memory;
int i = threadIdx.x / B;
int j = threadIdx.x % B;
int x = i + k * B;
int y = j + k * B;
dBlock[threadIdx.x] = (x < n && y < n)? arr[x * n + y]: INF;
for (int l = 0; l < B; l++) {
__syncthreads();
int temp = dBlock[(i * B) + l] + dBlock[(l * B) + j];
if (dBlock[threadIdx.x] > temp) {
dBlock[threadIdx.x] = temp;
}
}
if (x < n && y < n) arr[x * n + y] = dBlock[threadIdx.x];
}
__global__ void func2(int n, int B, int k, int* arr) {
if (blockIdx.x == k) return;
extern __shared__ int shared_memory[];
int* dBlock = shared_memory;
int* cBlock = &shared_memory[B * B];
int i = threadIdx.x / B;
int j = threadIdx.x % B;
int x = i + k * B;
int y = j + k * B;
dBlock[threadIdx.x] = (x < n && y < n)? arr[x * n + y]: INF;
if (blockIdx.y != 0) x = i + blockIdx.x * B;
if (blockIdx.y == 0) y = j + blockIdx.x * B;
cBlock[threadIdx.x] = (x < n && y < n)? arr[x * n + y]: INF;
for (int l = 0; l < B; l++) {
__syncthreads();
int temp = (blockIdx.y == 0)? dBlock[i * B + l] + cBlock[l * B + j]: cBlock[i * B + l] + dBlock[l * B + j];
if (cBlock[threadIdx.x] > temp) {
cBlock[threadIdx.x] = temp;
}
}
if (x < n && y < n) arr[x * n + y] = cBlock[threadIdx.x];
}
__global__ void func3(int n, int B, int k, int* arr) {
if (blockIdx.x == k || blockIdx.y == k) return;
extern __shared__ int shared_memory[];
int* dyBlock = shared_memory;
int* dxBlock = &shared_memory[B * B];
int i = threadIdx.x / B;
int j = threadIdx.x % B;
int x = i + k * B;
int y = j + blockIdx.y * B;
dxBlock[threadIdx.x] = (x < n && y < n)? arr[x * n + y]: INF;
x = i + blockIdx.x * B;
y = j + k * B;
dyBlock[threadIdx.x] = (x < n && y < n)? arr[x * n + y]: INF;
x = i + blockIdx.x * B;
y = j + blockIdx.y * B;
int dist = (x < n && y < n)? arr[x * n + y]: INF;
__syncthreads();
for (int l = 0; l < B; l++) {
int temp = dyBlock[i * B + l] + dxBlock[l * B + j];
if (dist > temp) {
dist = temp;
}
}
if (x < n && y < n) arr[x * n + y] = dist;
}
void Block(int B) {
cudaMalloc(&dev_D, n * n * sizeof(int));
cudaMemcpy(dev_D, host_D, n * n * sizeof(int), cudaMemcpyHostToDevice);
int round = (n + B - 1) / B;
dim3 bk1(1, 1);
dim3 bk2(round, 2);
dim3 bk3(round, round);
int gputhreads = B * B;
for (int k = 0; k < round; k++) {
func1<<<bk1, gputhreads, gputhreads * sizeof(int)>>>(n, B, k, dev_D);
func2<<<bk2, gputhreads, 2 * gputhreads * sizeof(int)>>>(n, B, k, dev_D);
func3<<<bk3, gputhreads, 2 * gputhreads * sizeof(int)>>>(n, B, k, dev_D);
}
cudaThreadSynchronize();
cudaMemcpy(host_D, dev_D, n * n * sizeof(int), cudaMemcpyDeviceToHost);
}
int main(int argc, char **argv) {
Input(argv[1]);
int B = atoi(argv[3]);
Block(B);
Output(argv[2]);
return 0;
} | .file "tmpxft_00152905_00000000-6_HW4_x1054034_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "%d %d"
.LC2:
.string "%d %d %d"
.text
.globl _Z5InputPc
.type _Z5InputPc, @function
_Z5InputPc:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
call fopen@PLT
movq %rax, %rbx
movl $1048576, %edi
call _Znam@PLT
movq %rax, %rsi
movl $1048576, %ecx
movl $0, %edx
movq %rbx, %rdi
call setvbuf@PLT
leaq m(%rip), %rcx
leaq n(%rip), %rdx
leaq .LC1(%rip), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl n(%rip), %ebp
movl %ebp, %edi
imull %ebp, %edi
movslq %edi, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, host_D(%rip)
movl $0, %ecx
testl %ebp, %ebp
jg .L4
.L5:
movl m(%rip), %eax
subl $1, %eax
movl %eax, m(%rip)
js .L10
leaq .LC2(%rip), %rbp
.L11:
leaq 16(%rsp), %rcx
leaq 12(%rsp), %rdx
leaq 20(%rsp), %r8
movq %rbp, %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 12(%rsp), %eax
subl $1, %eax
imull n(%rip), %eax
movl 16(%rsp), %edx
leal -1(%rax,%rdx), %eax
cltq
movl 20(%rsp), %ecx
movq host_D(%rip), %rdx
movl %ecx, (%rdx,%rax,4)
movl m(%rip), %eax
subl $1, %eax
movl %eax, m(%rip)
jns .L11
.L10:
movq %rbx, %rdi
call fclose@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
imull %ecx, %eax
addl %edx, %eax
cltq
movq host_D(%rip), %rsi
movl $10000000, (%rsi,%rax,4)
.L7:
addl $1, %edx
movl n(%rip), %eax
cmpl %edx, %eax
jle .L9
.L8:
cmpl %edx, %ecx
jne .L6
imull %ecx, %eax
addl %edx, %eax
cltq
movq host_D(%rip), %rsi
movl $0, (%rsi,%rax,4)
jmp .L7
.L9:
addl $1, %ecx
cmpl %ecx, n(%rip)
jle .L5
.L4:
movl n(%rip), %eax
movl $0, %edx
testl %eax, %eax
jg .L8
jmp .L9
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z5InputPc, .-_Z5InputPc
.section .rodata.str1.1
.LC3:
.string "w"
.LC4:
.string "INF "
.LC5:
.string "%d "
.LC6:
.string "\n"
.text
.globl _Z6OutputPc
.type _Z6OutputPc, @function
_Z6OutputPc:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
leaq .LC3(%rip), %rsi
call fopen@PLT
movq %rax, %r12
movl $1048576, %edi
call _Znam@PLT
movq %rax, %rsi
movl $1048576, %ecx
movl $0, %edx
movq %r12, %rdi
call setvbuf@PLT
movl $0, %ebp
leaq .LC5(%rip), %r14
leaq .LC4(%rip), %r13
leaq .LC6(%rip), %r15
cmpl $0, n(%rip)
jg .L22
.L23:
movq %r12, %rdi
call fclose@PLT
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movq %r14, %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L25:
addl $1, %ebx
movl n(%rip), %eax
cmpl %ebx, %eax
jle .L27
.L26:
imull %ebp, %eax
addl %ebx, %eax
cltq
movq host_D(%rip), %rdx
movl (%rdx,%rax,4), %ecx
cmpl $9999999, %ecx
jle .L24
movq %r13, %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L25
.L27:
movq %r15, %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addl $1, %ebp
cmpl %ebp, n(%rip)
jle .L23
.L22:
movl n(%rip), %eax
movl $0, %ebx
testl %eax, %eax
jg .L26
jmp .L27
.cfi_endproc
.LFE2058:
.size _Z6OutputPc, .-_Z6OutputPc
.globl _Z27__device_stub__Z5func1iiiPiiiiPi
.type _Z27__device_stub__Z5func1iiiPiiiiPi, @function
_Z27__device_stub__Z5func1iiiPiiiiPi:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L38
.L34:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L39
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5func1iiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L34
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z27__device_stub__Z5func1iiiPiiiiPi, .-_Z27__device_stub__Z5func1iiiPiiiiPi
.globl _Z5func1iiiPi
.type _Z5func1iiiPi, @function
_Z5func1iiiPi:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z5func1iiiPiiiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z5func1iiiPi, .-_Z5func1iiiPi
.globl _Z27__device_stub__Z5func2iiiPiiiiPi
.type _Z27__device_stub__Z5func2iiiPiiiiPi, @function
_Z27__device_stub__Z5func2iiiPiiiiPi:
.LFB2087:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L46
.L42:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L47
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5func2iiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L42
.L47:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z27__device_stub__Z5func2iiiPiiiiPi, .-_Z27__device_stub__Z5func2iiiPiiiiPi
.globl _Z5func2iiiPi
.type _Z5func2iiiPi, @function
_Z5func2iiiPi:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z5func2iiiPiiiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z5func2iiiPi, .-_Z5func2iiiPi
.globl _Z27__device_stub__Z5func3iiiPiiiiPi
.type _Z27__device_stub__Z5func3iiiPiiiiPi, @function
_Z27__device_stub__Z5func3iiiPiiiiPi:
.LFB2089:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L54
.L50:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L55
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5func3iiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L50
.L55:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z27__device_stub__Z5func3iiiPiiiiPi, .-_Z27__device_stub__Z5func3iiiPiiiiPi
.globl _Z5func3iiiPi
.type _Z5func3iiiPi, @function
_Z5func3iiiPi:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z5func3iiiPiiiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z5func3iiiPi, .-_Z5func3iiiPi
.globl _Z5Blocki
.type _Z5Blocki, @function
_Z5Blocki:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movl %edi, %r14d
movl n(%rip), %esi
imull %esi, %esi
movslq %esi, %rsi
salq $2, %rsi
leaq dev_D(%rip), %rdi
call cudaMalloc@PLT
movl n(%rip), %edx
imull %edx, %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq host_D(%rip), %rsi
movq dev_D(%rip), %rdi
call cudaMemcpy@PLT
movl %r14d, %eax
addl n(%rip), %eax
subl $1, %eax
cltd
idivl %r14d
movl $1, (%rsp)
movl $1, 4(%rsp)
movl $1, 8(%rsp)
movl %eax, 12(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl %eax, 24(%rsp)
movl %eax, 28(%rsp)
movl $1, 32(%rsp)
movl %r14d, %ebp
imull %r14d, %ebp
testl %eax, %eax
jle .L59
movl %eax, %r13d
movslq %ebp, %r15
salq $2, %r15
leal (%rbp,%rbp), %r12d
movslq %r12d, %r12
salq $2, %r12
movl $0, %ebx
jmp .L63
.L66:
movq dev_D(%rip), %rcx
movl %ebx, %edx
movl %r14d, %esi
movl n(%rip), %edi
call _Z27__device_stub__Z5func1iiiPiiiiPi
jmp .L60
.L67:
movq dev_D(%rip), %rcx
movl %ebx, %edx
movl %r14d, %esi
movl n(%rip), %edi
call _Z27__device_stub__Z5func2iiiPiiiiPi
jmp .L61
.L62:
addl $1, %ebx
cmpl %ebx, %r13d
je .L59
.L63:
movl %ebp, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movq %r15, %r8
movq 36(%rsp), %rdx
movl $1, %ecx
movq (%rsp), %rdi
movl 8(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L66
.L60:
movl %ebp, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movq %r12, %r8
movq 36(%rsp), %rdx
movl $1, %ecx
movq 12(%rsp), %rdi
movl 20(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L67
.L61:
movl %ebp, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movq %r12, %r8
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl 32(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L62
movq dev_D(%rip), %rcx
movl %ebx, %edx
movl %r14d, %esi
movl n(%rip), %edi
call _Z27__device_stub__Z5func3iiiPiiiiPi
jmp .L62
.L59:
call cudaThreadSynchronize@PLT
movl n(%rip), %edx
imull %edx, %edx
movslq %edx, %rdx
salq $2, %rdx
movl $2, %ecx
movq dev_D(%rip), %rsi
movq host_D(%rip), %rdi
call cudaMemcpy@PLT
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z5Blocki, .-_Z5Blocki
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rsi, %rbx
movq 8(%rsi), %rdi
call _Z5InputPc
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %edi
call _Z5Blocki
movq 16(%rbx), %rdi
call _Z6OutputPc
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z5func3iiiPi"
.LC8:
.string "_Z5func2iiiPi"
.LC9:
.string "_Z5func1iiiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2092:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z5func3iiiPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z5func2iiiPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z5func1iiiPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl m
.bss
.align 4
.type m, @object
.size m, 4
m:
.zero 4
.globl n
.align 4
.type n, @object
.size n, 4
n:
.zero 4
.globl dev_D
.align 8
.type dev_D, @object
.size dev_D, 8
dev_D:
.zero 8
.globl host_D
.align 8
.type host_D, @object
.size host_D, 8
host_D:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
const int INF = 10000000;
int *host_D;
int *dev_D;
int n, m;
void Input(char *inFileName) {
FILE *infile = fopen(inFileName, "r");
setvbuf(infile, new char[1 << 20], _IOFBF, 1 << 20);
fscanf(infile, "%d %d", &n, &m);
host_D = (int*)malloc(n * n * sizeof(int));
for (int i = 0; i < n; ++i) {
for (int j = 0; j < n; ++j) {
if (i == j) host_D[i * n + j] = 0;
else host_D[i * n + j] = INF;
}
}
while (--m >= 0) {
int a, b, v;
fscanf(infile, "%d %d %d", &a, &b, &v);
host_D[(a - 1) * n + (b - 1)] = v;
}
fclose(infile);
}
void Output(char *outFileName) {
FILE *outfile = fopen(outFileName, "w");
setvbuf(outfile, new char[1 << 20], _IOFBF, 1 << 20);
for (int i = 0; i < n; ++i) {
for (int j = 0; j < n; ++j) {
if (host_D[i * n + j] >= INF) fprintf(outfile, "INF ");
else fprintf(outfile, "%d ", host_D[i * n + j]);
}
fprintf(outfile, "\n");
}
fclose(outfile);
}
__global__ void func1(int n, int B, int k, int* arr) {
extern __shared__ int shared_memory[];
int* dBlock = shared_memory;
int i = threadIdx.x / B;
int j = threadIdx.x % B;
int x = i + k * B;
int y = j + k * B;
dBlock[threadIdx.x] = (x < n && y < n)? arr[x * n + y]: INF;
for (int l = 0; l < B; l++) {
__syncthreads();
int temp = dBlock[(i * B) + l] + dBlock[(l * B) + j];
if (dBlock[threadIdx.x] > temp) {
dBlock[threadIdx.x] = temp;
}
}
if (x < n && y < n) arr[x * n + y] = dBlock[threadIdx.x];
}
__global__ void func2(int n, int B, int k, int* arr) {
if (blockIdx.x == k) return;
extern __shared__ int shared_memory[];
int* dBlock = shared_memory;
int* cBlock = &shared_memory[B * B];
int i = threadIdx.x / B;
int j = threadIdx.x % B;
int x = i + k * B;
int y = j + k * B;
dBlock[threadIdx.x] = (x < n && y < n)? arr[x * n + y]: INF;
if (blockIdx.y != 0) x = i + blockIdx.x * B;
if (blockIdx.y == 0) y = j + blockIdx.x * B;
cBlock[threadIdx.x] = (x < n && y < n)? arr[x * n + y]: INF;
for (int l = 0; l < B; l++) {
__syncthreads();
int temp = (blockIdx.y == 0)? dBlock[i * B + l] + cBlock[l * B + j]: cBlock[i * B + l] + dBlock[l * B + j];
if (cBlock[threadIdx.x] > temp) {
cBlock[threadIdx.x] = temp;
}
}
if (x < n && y < n) arr[x * n + y] = cBlock[threadIdx.x];
}
__global__ void func3(int n, int B, int k, int* arr) {
if (blockIdx.x == k || blockIdx.y == k) return;
extern __shared__ int shared_memory[];
int* dyBlock = shared_memory;
int* dxBlock = &shared_memory[B * B];
int i = threadIdx.x / B;
int j = threadIdx.x % B;
int x = i + k * B;
int y = j + blockIdx.y * B;
dxBlock[threadIdx.x] = (x < n && y < n)? arr[x * n + y]: INF;
x = i + blockIdx.x * B;
y = j + k * B;
dyBlock[threadIdx.x] = (x < n && y < n)? arr[x * n + y]: INF;
x = i + blockIdx.x * B;
y = j + blockIdx.y * B;
int dist = (x < n && y < n)? arr[x * n + y]: INF;
__syncthreads();
for (int l = 0; l < B; l++) {
int temp = dyBlock[i * B + l] + dxBlock[l * B + j];
if (dist > temp) {
dist = temp;
}
}
if (x < n && y < n) arr[x * n + y] = dist;
}
void Block(int B) {
cudaMalloc(&dev_D, n * n * sizeof(int));
cudaMemcpy(dev_D, host_D, n * n * sizeof(int), cudaMemcpyHostToDevice);
int round = (n + B - 1) / B;
dim3 bk1(1, 1);
dim3 bk2(round, 2);
dim3 bk3(round, round);
int gputhreads = B * B;
for (int k = 0; k < round; k++) {
func1<<<bk1, gputhreads, gputhreads * sizeof(int)>>>(n, B, k, dev_D);
func2<<<bk2, gputhreads, 2 * gputhreads * sizeof(int)>>>(n, B, k, dev_D);
func3<<<bk3, gputhreads, 2 * gputhreads * sizeof(int)>>>(n, B, k, dev_D);
}
cudaThreadSynchronize();
cudaMemcpy(host_D, dev_D, n * n * sizeof(int), cudaMemcpyDeviceToHost);
}
int main(int argc, char **argv) {
Input(argv[1]);
int B = atoi(argv[3]);
Block(B);
Output(argv[2]);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
const int INF = 10000000;
int *host_D;
int *dev_D;
int n, m;
void Input(char *inFileName) {
FILE *infile = fopen(inFileName, "r");
setvbuf(infile, new char[1 << 20], _IOFBF, 1 << 20);
fscanf(infile, "%d %d", &n, &m);
host_D = (int*)malloc(n * n * sizeof(int));
for (int i = 0; i < n; ++i) {
for (int j = 0; j < n; ++j) {
if (i == j) host_D[i * n + j] = 0;
else host_D[i * n + j] = INF;
}
}
while (--m >= 0) {
int a, b, v;
fscanf(infile, "%d %d %d", &a, &b, &v);
host_D[(a - 1) * n + (b - 1)] = v;
}
fclose(infile);
}
void Output(char *outFileName) {
FILE *outfile = fopen(outFileName, "w");
setvbuf(outfile, new char[1 << 20], _IOFBF, 1 << 20);
for (int i = 0; i < n; ++i) {
for (int j = 0; j < n; ++j) {
if (host_D[i * n + j] >= INF) fprintf(outfile, "INF ");
else fprintf(outfile, "%d ", host_D[i * n + j]);
}
fprintf(outfile, "\n");
}
fclose(outfile);
}
__global__ void func1(int n, int B, int k, int* arr) {
extern __shared__ int shared_memory[];
int* dBlock = shared_memory;
int i = threadIdx.x / B;
int j = threadIdx.x % B;
int x = i + k * B;
int y = j + k * B;
dBlock[threadIdx.x] = (x < n && y < n)? arr[x * n + y]: INF;
for (int l = 0; l < B; l++) {
__syncthreads();
int temp = dBlock[(i * B) + l] + dBlock[(l * B) + j];
if (dBlock[threadIdx.x] > temp) {
dBlock[threadIdx.x] = temp;
}
}
if (x < n && y < n) arr[x * n + y] = dBlock[threadIdx.x];
}
__global__ void func2(int n, int B, int k, int* arr) {
if (blockIdx.x == k) return;
extern __shared__ int shared_memory[];
int* dBlock = shared_memory;
int* cBlock = &shared_memory[B * B];
int i = threadIdx.x / B;
int j = threadIdx.x % B;
int x = i + k * B;
int y = j + k * B;
dBlock[threadIdx.x] = (x < n && y < n)? arr[x * n + y]: INF;
if (blockIdx.y != 0) x = i + blockIdx.x * B;
if (blockIdx.y == 0) y = j + blockIdx.x * B;
cBlock[threadIdx.x] = (x < n && y < n)? arr[x * n + y]: INF;
for (int l = 0; l < B; l++) {
__syncthreads();
int temp = (blockIdx.y == 0)? dBlock[i * B + l] + cBlock[l * B + j]: cBlock[i * B + l] + dBlock[l * B + j];
if (cBlock[threadIdx.x] > temp) {
cBlock[threadIdx.x] = temp;
}
}
if (x < n && y < n) arr[x * n + y] = cBlock[threadIdx.x];
}
__global__ void func3(int n, int B, int k, int* arr) {
if (blockIdx.x == k || blockIdx.y == k) return;
extern __shared__ int shared_memory[];
int* dyBlock = shared_memory;
int* dxBlock = &shared_memory[B * B];
int i = threadIdx.x / B;
int j = threadIdx.x % B;
int x = i + k * B;
int y = j + blockIdx.y * B;
dxBlock[threadIdx.x] = (x < n && y < n)? arr[x * n + y]: INF;
x = i + blockIdx.x * B;
y = j + k * B;
dyBlock[threadIdx.x] = (x < n && y < n)? arr[x * n + y]: INF;
x = i + blockIdx.x * B;
y = j + blockIdx.y * B;
int dist = (x < n && y < n)? arr[x * n + y]: INF;
__syncthreads();
for (int l = 0; l < B; l++) {
int temp = dyBlock[i * B + l] + dxBlock[l * B + j];
if (dist > temp) {
dist = temp;
}
}
if (x < n && y < n) arr[x * n + y] = dist;
}
void Block(int B) {
hipMalloc(&dev_D, n * n * sizeof(int));
hipMemcpy(dev_D, host_D, n * n * sizeof(int), hipMemcpyHostToDevice);
int round = (n + B - 1) / B;
dim3 bk1(1, 1);
dim3 bk2(round, 2);
dim3 bk3(round, round);
int gputhreads = B * B;
for (int k = 0; k < round; k++) {
func1<<<bk1, gputhreads, gputhreads * sizeof(int)>>>(n, B, k, dev_D);
func2<<<bk2, gputhreads, 2 * gputhreads * sizeof(int)>>>(n, B, k, dev_D);
func3<<<bk3, gputhreads, 2 * gputhreads * sizeof(int)>>>(n, B, k, dev_D);
}
hipDeviceSynchronize();
hipMemcpy(host_D, dev_D, n * n * sizeof(int), hipMemcpyDeviceToHost);
}
int main(int argc, char **argv) {
Input(argv[1]);
int B = atoi(argv[3]);
Block(B);
Output(argv[2]);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
const int INF = 10000000;
int *host_D;
int *dev_D;
int n, m;
void Input(char *inFileName) {
FILE *infile = fopen(inFileName, "r");
setvbuf(infile, new char[1 << 20], _IOFBF, 1 << 20);
fscanf(infile, "%d %d", &n, &m);
host_D = (int*)malloc(n * n * sizeof(int));
for (int i = 0; i < n; ++i) {
for (int j = 0; j < n; ++j) {
if (i == j) host_D[i * n + j] = 0;
else host_D[i * n + j] = INF;
}
}
while (--m >= 0) {
int a, b, v;
fscanf(infile, "%d %d %d", &a, &b, &v);
host_D[(a - 1) * n + (b - 1)] = v;
}
fclose(infile);
}
void Output(char *outFileName) {
FILE *outfile = fopen(outFileName, "w");
setvbuf(outfile, new char[1 << 20], _IOFBF, 1 << 20);
for (int i = 0; i < n; ++i) {
for (int j = 0; j < n; ++j) {
if (host_D[i * n + j] >= INF) fprintf(outfile, "INF ");
else fprintf(outfile, "%d ", host_D[i * n + j]);
}
fprintf(outfile, "\n");
}
fclose(outfile);
}
__global__ void func1(int n, int B, int k, int* arr) {
extern __shared__ int shared_memory[];
int* dBlock = shared_memory;
int i = threadIdx.x / B;
int j = threadIdx.x % B;
int x = i + k * B;
int y = j + k * B;
dBlock[threadIdx.x] = (x < n && y < n)? arr[x * n + y]: INF;
for (int l = 0; l < B; l++) {
__syncthreads();
int temp = dBlock[(i * B) + l] + dBlock[(l * B) + j];
if (dBlock[threadIdx.x] > temp) {
dBlock[threadIdx.x] = temp;
}
}
if (x < n && y < n) arr[x * n + y] = dBlock[threadIdx.x];
}
__global__ void func2(int n, int B, int k, int* arr) {
if (blockIdx.x == k) return;
extern __shared__ int shared_memory[];
int* dBlock = shared_memory;
int* cBlock = &shared_memory[B * B];
int i = threadIdx.x / B;
int j = threadIdx.x % B;
int x = i + k * B;
int y = j + k * B;
dBlock[threadIdx.x] = (x < n && y < n)? arr[x * n + y]: INF;
if (blockIdx.y != 0) x = i + blockIdx.x * B;
if (blockIdx.y == 0) y = j + blockIdx.x * B;
cBlock[threadIdx.x] = (x < n && y < n)? arr[x * n + y]: INF;
for (int l = 0; l < B; l++) {
__syncthreads();
int temp = (blockIdx.y == 0)? dBlock[i * B + l] + cBlock[l * B + j]: cBlock[i * B + l] + dBlock[l * B + j];
if (cBlock[threadIdx.x] > temp) {
cBlock[threadIdx.x] = temp;
}
}
if (x < n && y < n) arr[x * n + y] = cBlock[threadIdx.x];
}
__global__ void func3(int n, int B, int k, int* arr) {
if (blockIdx.x == k || blockIdx.y == k) return;
extern __shared__ int shared_memory[];
int* dyBlock = shared_memory;
int* dxBlock = &shared_memory[B * B];
int i = threadIdx.x / B;
int j = threadIdx.x % B;
int x = i + k * B;
int y = j + blockIdx.y * B;
dxBlock[threadIdx.x] = (x < n && y < n)? arr[x * n + y]: INF;
x = i + blockIdx.x * B;
y = j + k * B;
dyBlock[threadIdx.x] = (x < n && y < n)? arr[x * n + y]: INF;
x = i + blockIdx.x * B;
y = j + blockIdx.y * B;
int dist = (x < n && y < n)? arr[x * n + y]: INF;
__syncthreads();
for (int l = 0; l < B; l++) {
int temp = dyBlock[i * B + l] + dxBlock[l * B + j];
if (dist > temp) {
dist = temp;
}
}
if (x < n && y < n) arr[x * n + y] = dist;
}
void Block(int B) {
hipMalloc(&dev_D, n * n * sizeof(int));
hipMemcpy(dev_D, host_D, n * n * sizeof(int), hipMemcpyHostToDevice);
int round = (n + B - 1) / B;
dim3 bk1(1, 1);
dim3 bk2(round, 2);
dim3 bk3(round, round);
int gputhreads = B * B;
for (int k = 0; k < round; k++) {
func1<<<bk1, gputhreads, gputhreads * sizeof(int)>>>(n, B, k, dev_D);
func2<<<bk2, gputhreads, 2 * gputhreads * sizeof(int)>>>(n, B, k, dev_D);
func3<<<bk3, gputhreads, 2 * gputhreads * sizeof(int)>>>(n, B, k, dev_D);
}
hipDeviceSynchronize();
hipMemcpy(host_D, dev_D, n * n * sizeof(int), hipMemcpyDeviceToHost);
}
int main(int argc, char **argv) {
Input(argv[1]);
int B = atoi(argv[3]);
Block(B);
Output(argv[2]);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5func1iiiPi
.globl _Z5func1iiiPi
.p2align 8
.type _Z5func1iiiPi,@function
_Z5func1iiiPi:
s_clause 0x2
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v1, s5
s_sub_i32 s0, 0, s5
s_mul_i32 s6, s6, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s0, v1
v_mul_hi_u32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v1, v2
v_mul_hi_u32 v1, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v1, s5
v_add_nc_u32_e32 v3, 1, v1
v_sub_nc_u32_e32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v4, s5, v2
v_cmp_le_u32_e32 vcc_lo, s5, v2
v_dual_cndmask_b32 v2, v2, v4 :: v_dual_cndmask_b32 v1, v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s5, v2
v_add_nc_u32_e32 v3, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, v1, v3, vcc_lo
v_mul_lo_u32 v3, v1, s5
v_add_nc_u32_e32 v2, s6, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, v0, v3
v_add_nc_u32_e32 v1, s6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v5, v2, v1
v_cmp_gt_i32_e32 vcc_lo, s4, v5
v_mov_b32_e32 v5, 0x989680
s_and_saveexec_b32 s1, vcc_lo
s_cbranch_execz .LBB0_2
v_mad_u64_u32 v[5:6], null, v2, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v5, s0, s2, v5
v_add_co_ci_u32_e64 v6, s0, s3, v6, s0
global_load_b32 v5, v[5:6], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s1
v_lshl_add_u32 v0, v0, 2, 0
s_cmp_lt_i32 s5, 1
s_waitcnt vmcnt(0)
ds_store_b32 v0, v5
s_cbranch_scc1 .LBB0_7
v_lshl_add_u32 v4, v4, 2, 0
v_lshl_add_u32 v3, v3, 2, 0
s_lshl_b32 s1, s5, 2
s_branch .LBB0_5
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s6
v_add_nc_u32_e32 v4, s1, v4
v_add_nc_u32_e32 v3, 4, v3
s_add_i32 s5, s5, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s5, 0
s_cbranch_scc1 .LBB0_7
.LBB0_5:
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v5, v3
ds_load_b32 v6, v4
ds_load_b32 v7, v0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(1)
v_add_nc_u32_e32 v5, v6, v5
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 v7, v5
s_cbranch_execz .LBB0_4
ds_store_b32 v0, v5
s_branch .LBB0_4
.LBB0_7:
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_9
v_mad_u64_u32 v[3:4], null, v2, s4, v[1:2]
ds_load_b32 v2, v0
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5func1iiiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 7
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5func1iiiPi, .Lfunc_end0-_Z5func1iiiPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z5func2iiiPi
.globl _Z5func2iiiPi
.p2align 8
.type _Z5func2iiiPi,@function
_Z5func2iiiPi:
s_load_b32 s6, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s14, s6
s_cbranch_scc1 .LBB1_16
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v1, s5
s_sub_i32 s0, 0, s5
s_mul_i32 s6, s6, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s0, v1
v_mul_hi_u32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v1, v2
v_mul_hi_u32 v1, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v1, s5
v_add_nc_u32_e32 v3, 1, v1
v_sub_nc_u32_e32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v4, s5, v2
v_cmp_le_u32_e32 vcc_lo, s5, v2
v_dual_cndmask_b32 v1, v1, v3 :: v_dual_cndmask_b32 v2, v2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, 1, v1
v_cmp_le_u32_e32 vcc_lo, s5, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v4, v1, v3, vcc_lo
v_mul_lo_u32 v6, v4, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v0, v6
v_add_nc_u32_e32 v3, s6, v5
v_add_nc_u32_e32 v1, s6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v2, v1, v3
v_cmp_gt_i32_e32 vcc_lo, s4, v2
v_mov_b32_e32 v2, 0x989680
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB1_3
v_mad_u64_u32 v[7:8], null, v1, s4, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
global_load_b32 v2, v[7:8], off
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s0
s_cmp_eq_u32 s15, 0
v_lshl_add_u32 v7, v0, 2, 0
s_cselect_b32 s0, -1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_waitcnt vmcnt(0)
ds_store_b32 v7, v2
s_cbranch_vccnz .LBB1_5
v_mad_u64_u32 v[1:2], null, s14, s5, v[4:5]
.LBB1_5:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_cbranch_vccnz .LBB1_7
v_mad_u64_u32 v[3:4], null, s14, s5, v[5:6]
.LBB1_7:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v2, v1, v3
v_cmp_gt_i32_e32 vcc_lo, s4, v2
v_mov_b32_e32 v2, 0x989680
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz .LBB1_9
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[7:8], null, v1, s4, v[3:4]
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_add_co_u32 v7, s1, s2, v7
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v8, s1, s3, v8, s1
global_load_b32 v2, v[7:8], off
.LBB1_9:
s_or_b32 exec_lo, exec_lo, s6
s_mul_i32 s1, s5, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b32 s1, s1, 2
s_add_i32 s1, s1, 0
s_cmp_lt_i32 s5, 1
v_lshl_add_u32 v0, v0, 2, s1
s_waitcnt vmcnt(0)
ds_store_b32 v0, v2
s_cbranch_scc1 .LBB1_14
v_lshlrev_b32_e32 v2, 2, v6
s_and_b32 s6, s0, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, s1, v2
v_add_nc_u32_e32 v2, 0, v2
s_cselect_b32 s1, s1, 0
v_cndmask_b32_e64 v2, v4, v2, s0
v_lshl_add_u32 v4, v5, 2, s1
s_lshl_b32 s1, s5, 2
s_branch .LBB1_12
.p2align 6
.LBB1_11:
s_or_b32 exec_lo, exec_lo, s6
v_add_nc_u32_e32 v2, 4, v2
v_add_nc_u32_e32 v4, s1, v4
s_add_i32 s5, s5, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s5, 0
s_cbranch_scc1 .LBB1_14
.LBB1_12:
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v5, v2
ds_load_b32 v6, v4
ds_load_b32 v7, v0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(1)
v_add_nc_u32_e32 v5, v6, v5
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 v7, v5
s_cbranch_execz .LBB1_11
ds_store_b32 v0, v5
s_branch .LBB1_11
.LBB1_14:
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB1_16
v_mad_u64_u32 v[4:5], null, v1, s4, v[3:4]
ds_load_b32 v2, v0
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[4:5]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB1_16:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5func2iiiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z5func2iiiPi, .Lfunc_end1-_Z5func2iiiPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z5func3iiiPi
.globl _Z5func3iiiPi
.p2align 8
.type _Z5func3iiiPi,@function
_Z5func3iiiPi:
s_load_b32 s6, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s14, s6
s_cbranch_scc1 .LBB2_13
s_cmp_eq_u32 s15, s6
s_cbranch_scc1 .LBB2_13
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_dual_mov_b32 v7, 0x989680 :: v_dual_mov_b32 v8, 0x989680
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v1, s5
s_sub_i32 s0, 0, s5
s_mul_i32 s1, s6, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s0, v1
v_mul_hi_u32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v1, v2
v_mul_hi_u32 v1, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v1, s5
v_add_nc_u32_e32 v3, 1, v1
v_sub_nc_u32_e32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v4, s5, v2
v_cmp_le_u32_e32 vcc_lo, s5, v2
v_dual_cndmask_b32 v1, v1, v3 :: v_dual_cndmask_b32 v2, v2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, 1, v1
v_cmp_le_u32_e32 vcc_lo, s5, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v5, v1, v3, vcc_lo
v_mul_lo_u32 v6, v5, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, v0, v6
v_mad_u64_u32 v[1:2], null, s15, s5, v[4:5]
v_add_nc_u32_e32 v2, s1, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e64 s0, s4, v2
v_cmp_gt_i32_e32 vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, vcc_lo
s_and_saveexec_b32 s6, s0
s_cbranch_execz .LBB2_4
v_mad_u64_u32 v[8:9], null, v2, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[2:3], 2, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v2, s0, s2, v2
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
global_load_b32 v8, v[2:3], off
.LBB2_4:
s_or_b32 exec_lo, exec_lo, s6
v_mad_u64_u32 v[2:3], null, s14, s5, v[5:6]
v_add_nc_u32_e32 v3, s1, v4
s_mul_i32 s0, s5, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b32 s0, s0, 2
s_add_i32 s6, s0, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e64 s0, s4, v2
v_cmp_gt_i32_e64 s1, s4, v3
v_lshl_add_u32 v5, v0, 2, s6
s_and_b32 s1, s0, s1
s_waitcnt vmcnt(0)
ds_store_b32 v5, v8
s_and_saveexec_b32 s7, s1
s_cbranch_execz .LBB2_6
v_mad_u64_u32 v[7:8], null, v2, s4, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v7, s1, s2, v7
v_add_co_ci_u32_e64 v8, s1, s3, v8, s1
global_load_b32 v7, v[7:8], off
.LBB2_6:
s_or_b32 exec_lo, exec_lo, s7
v_lshl_add_u32 v3, v0, 2, 0
v_mov_b32_e32 v0, 0x989680
s_and_b32 s0, s0, vcc_lo
s_waitcnt vmcnt(0)
ds_store_b32 v3, v7
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB2_8
v_mad_u64_u32 v[7:8], null, v2, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
global_load_b32 v0, v[7:8], off
.LBB2_8:
s_or_b32 exec_lo, exec_lo, s1
s_cmp_lt_i32 s5, 1
s_waitcnt vmcnt(0) lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB2_11
v_lshl_add_u32 v3, v4, 2, s6
v_lshl_add_u32 v4, v6, 2, 0
s_lshl_b32 s1, s5, 2
.LBB2_10:
ds_load_b32 v5, v4
ds_load_b32 v6, v3
v_add_nc_u32_e32 v3, s1, v3
v_add_nc_u32_e32 v4, 4, v4
s_add_i32 s5, s5, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s5, 0
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v5, v6, v5
v_min_i32_e32 v0, v0, v5
s_cbranch_scc0 .LBB2_10
.LBB2_11:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB2_13
v_mad_u64_u32 v[3:4], null, v2, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[1:2], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB2_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5func3iiiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z5func3iiiPi, .Lfunc_end2-_Z5func3iiiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5func1iiiPi
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: _Z5func1iiiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5func2iiiPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5func2iiiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5func3iiiPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5func3iiiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
const int INF = 10000000;
int *host_D;
int *dev_D;
int n, m;
void Input(char *inFileName) {
FILE *infile = fopen(inFileName, "r");
setvbuf(infile, new char[1 << 20], _IOFBF, 1 << 20);
fscanf(infile, "%d %d", &n, &m);
host_D = (int*)malloc(n * n * sizeof(int));
for (int i = 0; i < n; ++i) {
for (int j = 0; j < n; ++j) {
if (i == j) host_D[i * n + j] = 0;
else host_D[i * n + j] = INF;
}
}
while (--m >= 0) {
int a, b, v;
fscanf(infile, "%d %d %d", &a, &b, &v);
host_D[(a - 1) * n + (b - 1)] = v;
}
fclose(infile);
}
void Output(char *outFileName) {
FILE *outfile = fopen(outFileName, "w");
setvbuf(outfile, new char[1 << 20], _IOFBF, 1 << 20);
for (int i = 0; i < n; ++i) {
for (int j = 0; j < n; ++j) {
if (host_D[i * n + j] >= INF) fprintf(outfile, "INF ");
else fprintf(outfile, "%d ", host_D[i * n + j]);
}
fprintf(outfile, "\n");
}
fclose(outfile);
}
__global__ void func1(int n, int B, int k, int* arr) {
extern __shared__ int shared_memory[];
int* dBlock = shared_memory;
int i = threadIdx.x / B;
int j = threadIdx.x % B;
int x = i + k * B;
int y = j + k * B;
dBlock[threadIdx.x] = (x < n && y < n)? arr[x * n + y]: INF;
for (int l = 0; l < B; l++) {
__syncthreads();
int temp = dBlock[(i * B) + l] + dBlock[(l * B) + j];
if (dBlock[threadIdx.x] > temp) {
dBlock[threadIdx.x] = temp;
}
}
if (x < n && y < n) arr[x * n + y] = dBlock[threadIdx.x];
}
__global__ void func2(int n, int B, int k, int* arr) {
if (blockIdx.x == k) return;
extern __shared__ int shared_memory[];
int* dBlock = shared_memory;
int* cBlock = &shared_memory[B * B];
int i = threadIdx.x / B;
int j = threadIdx.x % B;
int x = i + k * B;
int y = j + k * B;
dBlock[threadIdx.x] = (x < n && y < n)? arr[x * n + y]: INF;
if (blockIdx.y != 0) x = i + blockIdx.x * B;
if (blockIdx.y == 0) y = j + blockIdx.x * B;
cBlock[threadIdx.x] = (x < n && y < n)? arr[x * n + y]: INF;
for (int l = 0; l < B; l++) {
__syncthreads();
int temp = (blockIdx.y == 0)? dBlock[i * B + l] + cBlock[l * B + j]: cBlock[i * B + l] + dBlock[l * B + j];
if (cBlock[threadIdx.x] > temp) {
cBlock[threadIdx.x] = temp;
}
}
if (x < n && y < n) arr[x * n + y] = cBlock[threadIdx.x];
}
__global__ void func3(int n, int B, int k, int* arr) {
if (blockIdx.x == k || blockIdx.y == k) return;
extern __shared__ int shared_memory[];
int* dyBlock = shared_memory;
int* dxBlock = &shared_memory[B * B];
int i = threadIdx.x / B;
int j = threadIdx.x % B;
int x = i + k * B;
int y = j + blockIdx.y * B;
dxBlock[threadIdx.x] = (x < n && y < n)? arr[x * n + y]: INF;
x = i + blockIdx.x * B;
y = j + k * B;
dyBlock[threadIdx.x] = (x < n && y < n)? arr[x * n + y]: INF;
x = i + blockIdx.x * B;
y = j + blockIdx.y * B;
int dist = (x < n && y < n)? arr[x * n + y]: INF;
__syncthreads();
for (int l = 0; l < B; l++) {
int temp = dyBlock[i * B + l] + dxBlock[l * B + j];
if (dist > temp) {
dist = temp;
}
}
if (x < n && y < n) arr[x * n + y] = dist;
}
void Block(int B) {
hipMalloc(&dev_D, n * n * sizeof(int));
hipMemcpy(dev_D, host_D, n * n * sizeof(int), hipMemcpyHostToDevice);
int round = (n + B - 1) / B;
dim3 bk1(1, 1);
dim3 bk2(round, 2);
dim3 bk3(round, round);
int gputhreads = B * B;
for (int k = 0; k < round; k++) {
func1<<<bk1, gputhreads, gputhreads * sizeof(int)>>>(n, B, k, dev_D);
func2<<<bk2, gputhreads, 2 * gputhreads * sizeof(int)>>>(n, B, k, dev_D);
func3<<<bk3, gputhreads, 2 * gputhreads * sizeof(int)>>>(n, B, k, dev_D);
}
hipDeviceSynchronize();
hipMemcpy(host_D, dev_D, n * n * sizeof(int), hipMemcpyDeviceToHost);
}
int main(int argc, char **argv) {
Input(argv[1]);
int B = atoi(argv[3]);
Block(B);
Output(argv[2]);
return 0;
} | .text
.file "HW4_x1054034_cuda.hip"
.globl _Z5InputPc # -- Begin function _Z5InputPc
.p2align 4, 0x90
.type _Z5InputPc,@function
_Z5InputPc: # @_Z5InputPc
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $24, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $.L.str, %esi
callq fopen
movq %rax, %rbx
movl $1048576, %edi # imm = 0x100000
callq _Znam
xorl %r14d, %r14d
movl $1048576, %ecx # imm = 0x100000
movq %rbx, %rdi
movq %rax, %rsi
xorl %edx, %edx
callq setvbuf
movl $.L.str.1, %esi
movl $n, %edx
movl $m, %ecx
movq %rbx, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movl n(%rip), %r15d
movl %r15d, %edi
imull %edi, %edi
shlq $2, %rdi
callq malloc
movq %rax, host_D(%rip)
testl %r15d, %r15d
jle .LBB0_6
# %bb.1: # %.preheader16.lr.ph
movl n(%rip), %ecx
xorl %edx, %edx
xorl %esi, %esi
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_5: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
incq %rsi
addl %ecx, %edx
cmpq %r15, %rsi
je .LBB0_6
.LBB0_2: # %.preheader16
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
testl %ecx, %ecx
jle .LBB0_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB0_2 Depth=1
movl %edx, %edi
leaq (%rax,%rdi,4), %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
cmpq %r8, %rsi
movl $10000000, %r9d # imm = 0x989680
cmovel %r14d, %r9d
movl %r9d, (%rdi,%r8,4)
incq %r8
cmpq %r8, %rcx
jne .LBB0_4
jmp .LBB0_5
.LBB0_6: # %.preheader
movl m(%rip), %eax
leal -1(%rax), %ecx
movl %ecx, m(%rip)
testl %eax, %eax
jle .LBB0_9
# %bb.7:
leaq 20(%rsp), %r14
leaq 16(%rsp), %r15
leaq 12(%rsp), %r12
.p2align 4, 0x90
.LBB0_8: # %.lr.ph19
# =>This Inner Loop Header: Depth=1
movl $.L.str.2, %esi
movq %rbx, %rdi
movq %r14, %rdx
movq %r15, %rcx
movq %r12, %r8
xorl %eax, %eax
callq __isoc23_fscanf
movl 12(%rsp), %eax
movq host_D(%rip), %rcx
movslq 20(%rsp), %rdx
decq %rdx
movslq n(%rip), %rsi
imulq %rdx, %rsi
movslq 16(%rsp), %rdx
addq %rsi, %rdx
movl %eax, -4(%rcx,%rdx,4)
movl m(%rip), %eax
leal -1(%rax), %ecx
movl %ecx, m(%rip)
testl %eax, %eax
jg .LBB0_8
.LBB0_9: # %._crit_edge20
movq %rbx, %rdi
callq fclose
addq $24, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z5InputPc, .Lfunc_end0-_Z5InputPc
.cfi_endproc
# -- End function
.globl _Z6OutputPc # -- Begin function _Z6OutputPc
.p2align 4, 0x90
.type _Z6OutputPc,@function
_Z6OutputPc: # @_Z6OutputPc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl $.L.str.3, %esi
callq fopen
movq %rax, %rbx
movl $1048576, %edi # imm = 0x100000
callq _Znam
movl $1048576, %ecx # imm = 0x100000
movq %rbx, %rdi
movq %rax, %rsi
xorl %edx, %edx
callq setvbuf
cmpl $0, n(%rip)
jle .LBB1_7
# %bb.1: # %.preheader.preheader
xorl %ebp, %ebp
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_6: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movl $10, %edi
movq %rbx, %rsi
callq fputc@PLT
incl %ebp
cmpl n(%rip), %ebp
jge .LBB1_7
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
movl n(%rip), %eax
testl %eax, %eax
jle .LBB1_6
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB1_2 Depth=1
xorl %r14d, %r14d
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_8: # in Loop: Header=BB1_4 Depth=2
movl $.L.str.5, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq fprintf
.LBB1_9: # in Loop: Header=BB1_4 Depth=2
movl n(%rip), %eax
incq %r14
cmpl %eax, %r14d
jge .LBB1_6
.LBB1_4: # %.lr.ph
# Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movq host_D(%rip), %rcx
imull %ebp, %eax
cltq
addq %r14, %rax
movl (%rcx,%rax,4), %edx
cmpl $10000000, %edx # imm = 0x989680
jl .LBB1_8
# %bb.5: # in Loop: Header=BB1_4 Depth=2
movl $.L.str.4, %edi
movl $4, %esi
movl $1, %edx
movq %rbx, %rcx
callq fwrite@PLT
jmp .LBB1_9
.LBB1_7: # %._crit_edge18
movq %rbx, %rdi
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end1:
.size _Z6OutputPc, .Lfunc_end1-_Z6OutputPc
.cfi_endproc
# -- End function
.globl _Z20__device_stub__func1iiiPi # -- Begin function _Z20__device_stub__func1iiiPi
.p2align 4, 0x90
.type _Z20__device_stub__func1iiiPi,@function
_Z20__device_stub__func1iiiPi: # @_Z20__device_stub__func1iiiPi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5func1iiiPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z20__device_stub__func1iiiPi, .Lfunc_end2-_Z20__device_stub__func1iiiPi
.cfi_endproc
# -- End function
.globl _Z20__device_stub__func2iiiPi # -- Begin function _Z20__device_stub__func2iiiPi
.p2align 4, 0x90
.type _Z20__device_stub__func2iiiPi,@function
_Z20__device_stub__func2iiiPi: # @_Z20__device_stub__func2iiiPi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5func2iiiPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z20__device_stub__func2iiiPi, .Lfunc_end3-_Z20__device_stub__func2iiiPi
.cfi_endproc
# -- End function
.globl _Z20__device_stub__func3iiiPi # -- Begin function _Z20__device_stub__func3iiiPi
.p2align 4, 0x90
.type _Z20__device_stub__func3iiiPi,@function
_Z20__device_stub__func3iiiPi: # @_Z20__device_stub__func3iiiPi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5func3iiiPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end4:
.size _Z20__device_stub__func3iiiPi, .Lfunc_end4-_Z20__device_stub__func3iiiPi
.cfi_endproc
# -- End function
.globl _Z5Blocki # -- Begin function _Z5Blocki
.p2align 4, 0x90
.type _Z5Blocki,@function
_Z5Blocki: # @_Z5Blocki
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edi, %ebx
movl n(%rip), %esi
imull %esi, %esi
shlq $2, %rsi
movl $dev_D, %edi
callq hipMalloc
movq dev_D(%rip), %rdi
movq host_D(%rip), %rsi
movl n(%rip), %edx
imull %edx, %edx
shlq $2, %rdx
movl $1, %ecx
callq hipMemcpy
movl n(%rip), %eax
addl %ebx, %eax
decl %eax
cltd
idivl %ebx
testl %eax, %eax
jle .LBB5_9
# %bb.1: # %.lr.ph
movq %rbx, %r12
movl %eax, %r14d
movabsq $4294967297, %rax # imm = 0x100000001
movabsq $8589934592, %rcx # imm = 0x200000000
orq %r14, %rcx
movq %rcx, 128(%rsp) # 8-byte Spill
movq %r14, %r13
shlq $32, %r13
orq %r14, %r13
movl %r12d, %ebp
imull %ebp, %ebp
leaq (%rax,%rbp), %r15
decq %r15
leaq (,%rbp,4), %rax
movq %rax, 120(%rsp) # 8-byte Spill
addl %ebp, %ebp
shlq $2, %rbp
xorl %ebx, %ebx
jmp .LBB5_2
.p2align 4, 0x90
.LBB5_8: # in Loop: Header=BB5_2 Depth=1
incl %ebx
cmpl %ebx, %r14d
je .LBB5_9
.LBB5_2: # =>This Inner Loop Header: Depth=1
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
movq 120(%rsp), %r8 # 8-byte Reload
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_4
# %bb.3: # in Loop: Header=BB5_2 Depth=1
movl n(%rip), %eax
movq dev_D(%rip), %rcx
movl %eax, 20(%rsp)
movl %r12d, 16(%rsp)
movl %ebx, 12(%rsp)
movq %rcx, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z5func1iiiPi, %edi
leaq 80(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_4: # in Loop: Header=BB5_2 Depth=1
movq 128(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
movq %rbp, %r8
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_6
# %bb.5: # in Loop: Header=BB5_2 Depth=1
movl n(%rip), %eax
movq dev_D(%rip), %rcx
movl %eax, 20(%rsp)
movl %r12d, 16(%rsp)
movl %ebx, 12(%rsp)
movq %rcx, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z5func2iiiPi, %edi
leaq 80(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_6: # in Loop: Header=BB5_2 Depth=1
movq %r13, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
movq %rbp, %r8
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_8
# %bb.7: # in Loop: Header=BB5_2 Depth=1
movl n(%rip), %eax
movq dev_D(%rip), %rcx
movl %eax, 20(%rsp)
movl %r12d, 16(%rsp)
movl %ebx, 12(%rsp)
movq %rcx, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z5func3iiiPi, %edi
leaq 80(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB5_8
.LBB5_9: # %._crit_edge
callq hipDeviceSynchronize
movq host_D(%rip), %rdi
movq dev_D(%rip), %rsi
movl n(%rip), %edx
imull %edx, %edx
shlq $2, %rdx
movl $2, %ecx
callq hipMemcpy
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z5Blocki, .Lfunc_end5-_Z5Blocki
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rsi, %rbx
movq 8(%rsi), %rdi
callq _Z5InputPc
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, %edi
callq _Z5Blocki
movq 16(%rbx), %rdi
callq _Z6OutputPc
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5func1iiiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5func2iiiPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5func3iiiPi, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type host_D,@object # @host_D
.bss
.globl host_D
.p2align 3, 0x0
host_D:
.quad 0
.size host_D, 8
.type dev_D,@object # @dev_D
.globl dev_D
.p2align 3, 0x0
dev_D:
.quad 0
.size dev_D, 8
.type n,@object # @n
.globl n
.p2align 2, 0x0
n:
.long 0 # 0x0
.size n, 4
.type m,@object # @m
.globl m
.p2align 2, 0x0
m:
.long 0 # 0x0
.size m, 4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d %d"
.size .L.str.1, 6
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d %d %d"
.size .L.str.2, 9
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "w"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "INF "
.size .L.str.4, 5
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d "
.size .L.str.5, 4
.type _Z5func1iiiPi,@object # @_Z5func1iiiPi
.section .rodata,"a",@progbits
.globl _Z5func1iiiPi
.p2align 3, 0x0
_Z5func1iiiPi:
.quad _Z20__device_stub__func1iiiPi
.size _Z5func1iiiPi, 8
.type _Z5func2iiiPi,@object # @_Z5func2iiiPi
.globl _Z5func2iiiPi
.p2align 3, 0x0
_Z5func2iiiPi:
.quad _Z20__device_stub__func2iiiPi
.size _Z5func2iiiPi, 8
.type _Z5func3iiiPi,@object # @_Z5func3iiiPi
.globl _Z5func3iiiPi
.p2align 3, 0x0
_Z5func3iiiPi:
.quad _Z20__device_stub__func3iiiPi
.size _Z5func3iiiPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5func1iiiPi"
.size .L__unnamed_1, 14
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z5func2iiiPi"
.size .L__unnamed_2, 14
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z5func3iiiPi"
.size .L__unnamed_3, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__func1iiiPi
.addrsig_sym _Z20__device_stub__func2iiiPi
.addrsig_sym _Z20__device_stub__func3iiiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym dev_D
.addrsig_sym n
.addrsig_sym m
.addrsig_sym _Z5func1iiiPi
.addrsig_sym _Z5func2iiiPi
.addrsig_sym _Z5func3iiiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00152905_00000000-6_HW4_x1054034_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "%d %d"
.LC2:
.string "%d %d %d"
.text
.globl _Z5InputPc
.type _Z5InputPc, @function
_Z5InputPc:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
call fopen@PLT
movq %rax, %rbx
movl $1048576, %edi
call _Znam@PLT
movq %rax, %rsi
movl $1048576, %ecx
movl $0, %edx
movq %rbx, %rdi
call setvbuf@PLT
leaq m(%rip), %rcx
leaq n(%rip), %rdx
leaq .LC1(%rip), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl n(%rip), %ebp
movl %ebp, %edi
imull %ebp, %edi
movslq %edi, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, host_D(%rip)
movl $0, %ecx
testl %ebp, %ebp
jg .L4
.L5:
movl m(%rip), %eax
subl $1, %eax
movl %eax, m(%rip)
js .L10
leaq .LC2(%rip), %rbp
.L11:
leaq 16(%rsp), %rcx
leaq 12(%rsp), %rdx
leaq 20(%rsp), %r8
movq %rbp, %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 12(%rsp), %eax
subl $1, %eax
imull n(%rip), %eax
movl 16(%rsp), %edx
leal -1(%rax,%rdx), %eax
cltq
movl 20(%rsp), %ecx
movq host_D(%rip), %rdx
movl %ecx, (%rdx,%rax,4)
movl m(%rip), %eax
subl $1, %eax
movl %eax, m(%rip)
jns .L11
.L10:
movq %rbx, %rdi
call fclose@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
imull %ecx, %eax
addl %edx, %eax
cltq
movq host_D(%rip), %rsi
movl $10000000, (%rsi,%rax,4)
.L7:
addl $1, %edx
movl n(%rip), %eax
cmpl %edx, %eax
jle .L9
.L8:
cmpl %edx, %ecx
jne .L6
imull %ecx, %eax
addl %edx, %eax
cltq
movq host_D(%rip), %rsi
movl $0, (%rsi,%rax,4)
jmp .L7
.L9:
addl $1, %ecx
cmpl %ecx, n(%rip)
jle .L5
.L4:
movl n(%rip), %eax
movl $0, %edx
testl %eax, %eax
jg .L8
jmp .L9
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z5InputPc, .-_Z5InputPc
.section .rodata.str1.1
.LC3:
.string "w"
.LC4:
.string "INF "
.LC5:
.string "%d "
.LC6:
.string "\n"
.text
.globl _Z6OutputPc
.type _Z6OutputPc, @function
_Z6OutputPc:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
leaq .LC3(%rip), %rsi
call fopen@PLT
movq %rax, %r12
movl $1048576, %edi
call _Znam@PLT
movq %rax, %rsi
movl $1048576, %ecx
movl $0, %edx
movq %r12, %rdi
call setvbuf@PLT
movl $0, %ebp
leaq .LC5(%rip), %r14
leaq .LC4(%rip), %r13
leaq .LC6(%rip), %r15
cmpl $0, n(%rip)
jg .L22
.L23:
movq %r12, %rdi
call fclose@PLT
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movq %r14, %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L25:
addl $1, %ebx
movl n(%rip), %eax
cmpl %ebx, %eax
jle .L27
.L26:
imull %ebp, %eax
addl %ebx, %eax
cltq
movq host_D(%rip), %rdx
movl (%rdx,%rax,4), %ecx
cmpl $9999999, %ecx
jle .L24
movq %r13, %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L25
.L27:
movq %r15, %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addl $1, %ebp
cmpl %ebp, n(%rip)
jle .L23
.L22:
movl n(%rip), %eax
movl $0, %ebx
testl %eax, %eax
jg .L26
jmp .L27
.cfi_endproc
.LFE2058:
.size _Z6OutputPc, .-_Z6OutputPc
.globl _Z27__device_stub__Z5func1iiiPiiiiPi
.type _Z27__device_stub__Z5func1iiiPiiiiPi, @function
_Z27__device_stub__Z5func1iiiPiiiiPi:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L38
.L34:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L39
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5func1iiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L34
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z27__device_stub__Z5func1iiiPiiiiPi, .-_Z27__device_stub__Z5func1iiiPiiiiPi
.globl _Z5func1iiiPi
.type _Z5func1iiiPi, @function
_Z5func1iiiPi:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z5func1iiiPiiiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z5func1iiiPi, .-_Z5func1iiiPi
.globl _Z27__device_stub__Z5func2iiiPiiiiPi
.type _Z27__device_stub__Z5func2iiiPiiiiPi, @function
_Z27__device_stub__Z5func2iiiPiiiiPi:
.LFB2087:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L46
.L42:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L47
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5func2iiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L42
.L47:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z27__device_stub__Z5func2iiiPiiiiPi, .-_Z27__device_stub__Z5func2iiiPiiiiPi
.globl _Z5func2iiiPi
.type _Z5func2iiiPi, @function
_Z5func2iiiPi:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z5func2iiiPiiiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z5func2iiiPi, .-_Z5func2iiiPi
.globl _Z27__device_stub__Z5func3iiiPiiiiPi
.type _Z27__device_stub__Z5func3iiiPiiiiPi, @function
_Z27__device_stub__Z5func3iiiPiiiiPi:
.LFB2089:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L54
.L50:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L55
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5func3iiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L50
.L55:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z27__device_stub__Z5func3iiiPiiiiPi, .-_Z27__device_stub__Z5func3iiiPiiiiPi
.globl _Z5func3iiiPi
.type _Z5func3iiiPi, @function
_Z5func3iiiPi:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z5func3iiiPiiiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z5func3iiiPi, .-_Z5func3iiiPi
.globl _Z5Blocki
.type _Z5Blocki, @function
_Z5Blocki:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movl %edi, %r14d
movl n(%rip), %esi
imull %esi, %esi
movslq %esi, %rsi
salq $2, %rsi
leaq dev_D(%rip), %rdi
call cudaMalloc@PLT
movl n(%rip), %edx
imull %edx, %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq host_D(%rip), %rsi
movq dev_D(%rip), %rdi
call cudaMemcpy@PLT
movl %r14d, %eax
addl n(%rip), %eax
subl $1, %eax
cltd
idivl %r14d
movl $1, (%rsp)
movl $1, 4(%rsp)
movl $1, 8(%rsp)
movl %eax, 12(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl %eax, 24(%rsp)
movl %eax, 28(%rsp)
movl $1, 32(%rsp)
movl %r14d, %ebp
imull %r14d, %ebp
testl %eax, %eax
jle .L59
movl %eax, %r13d
movslq %ebp, %r15
salq $2, %r15
leal (%rbp,%rbp), %r12d
movslq %r12d, %r12
salq $2, %r12
movl $0, %ebx
jmp .L63
.L66:
movq dev_D(%rip), %rcx
movl %ebx, %edx
movl %r14d, %esi
movl n(%rip), %edi
call _Z27__device_stub__Z5func1iiiPiiiiPi
jmp .L60
.L67:
movq dev_D(%rip), %rcx
movl %ebx, %edx
movl %r14d, %esi
movl n(%rip), %edi
call _Z27__device_stub__Z5func2iiiPiiiiPi
jmp .L61
.L62:
addl $1, %ebx
cmpl %ebx, %r13d
je .L59
.L63:
movl %ebp, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movq %r15, %r8
movq 36(%rsp), %rdx
movl $1, %ecx
movq (%rsp), %rdi
movl 8(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L66
.L60:
movl %ebp, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movq %r12, %r8
movq 36(%rsp), %rdx
movl $1, %ecx
movq 12(%rsp), %rdi
movl 20(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L67
.L61:
movl %ebp, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movq %r12, %r8
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl 32(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L62
movq dev_D(%rip), %rcx
movl %ebx, %edx
movl %r14d, %esi
movl n(%rip), %edi
call _Z27__device_stub__Z5func3iiiPiiiiPi
jmp .L62
.L59:
call cudaThreadSynchronize@PLT
movl n(%rip), %edx
imull %edx, %edx
movslq %edx, %rdx
salq $2, %rdx
movl $2, %ecx
movq dev_D(%rip), %rsi
movq host_D(%rip), %rdi
call cudaMemcpy@PLT
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z5Blocki, .-_Z5Blocki
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rsi, %rbx
movq 8(%rsi), %rdi
call _Z5InputPc
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %edi
call _Z5Blocki
movq 16(%rbx), %rdi
call _Z6OutputPc
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z5func3iiiPi"
.LC8:
.string "_Z5func2iiiPi"
.LC9:
.string "_Z5func1iiiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2092:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z5func3iiiPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z5func2iiiPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z5func1iiiPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl m
.bss
.align 4
.type m, @object
.size m, 4
m:
.zero 4
.globl n
.align 4
.type n, @object
.size n, 4
n:
.zero 4
.globl dev_D
.align 8
.type dev_D, @object
.size dev_D, 8
dev_D:
.zero 8
.globl host_D
.align 8
.type host_D, @object
.size host_D, 8
host_D:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "HW4_x1054034_cuda.hip"
.globl _Z5InputPc # -- Begin function _Z5InputPc
.p2align 4, 0x90
.type _Z5InputPc,@function
_Z5InputPc: # @_Z5InputPc
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $24, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $.L.str, %esi
callq fopen
movq %rax, %rbx
movl $1048576, %edi # imm = 0x100000
callq _Znam
xorl %r14d, %r14d
movl $1048576, %ecx # imm = 0x100000
movq %rbx, %rdi
movq %rax, %rsi
xorl %edx, %edx
callq setvbuf
movl $.L.str.1, %esi
movl $n, %edx
movl $m, %ecx
movq %rbx, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movl n(%rip), %r15d
movl %r15d, %edi
imull %edi, %edi
shlq $2, %rdi
callq malloc
movq %rax, host_D(%rip)
testl %r15d, %r15d
jle .LBB0_6
# %bb.1: # %.preheader16.lr.ph
movl n(%rip), %ecx
xorl %edx, %edx
xorl %esi, %esi
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_5: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
incq %rsi
addl %ecx, %edx
cmpq %r15, %rsi
je .LBB0_6
.LBB0_2: # %.preheader16
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
testl %ecx, %ecx
jle .LBB0_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB0_2 Depth=1
movl %edx, %edi
leaq (%rax,%rdi,4), %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
cmpq %r8, %rsi
movl $10000000, %r9d # imm = 0x989680
cmovel %r14d, %r9d
movl %r9d, (%rdi,%r8,4)
incq %r8
cmpq %r8, %rcx
jne .LBB0_4
jmp .LBB0_5
.LBB0_6: # %.preheader
movl m(%rip), %eax
leal -1(%rax), %ecx
movl %ecx, m(%rip)
testl %eax, %eax
jle .LBB0_9
# %bb.7:
leaq 20(%rsp), %r14
leaq 16(%rsp), %r15
leaq 12(%rsp), %r12
.p2align 4, 0x90
.LBB0_8: # %.lr.ph19
# =>This Inner Loop Header: Depth=1
movl $.L.str.2, %esi
movq %rbx, %rdi
movq %r14, %rdx
movq %r15, %rcx
movq %r12, %r8
xorl %eax, %eax
callq __isoc23_fscanf
movl 12(%rsp), %eax
movq host_D(%rip), %rcx
movslq 20(%rsp), %rdx
decq %rdx
movslq n(%rip), %rsi
imulq %rdx, %rsi
movslq 16(%rsp), %rdx
addq %rsi, %rdx
movl %eax, -4(%rcx,%rdx,4)
movl m(%rip), %eax
leal -1(%rax), %ecx
movl %ecx, m(%rip)
testl %eax, %eax
jg .LBB0_8
.LBB0_9: # %._crit_edge20
movq %rbx, %rdi
callq fclose
addq $24, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z5InputPc, .Lfunc_end0-_Z5InputPc
.cfi_endproc
# -- End function
.globl _Z6OutputPc # -- Begin function _Z6OutputPc
.p2align 4, 0x90
.type _Z6OutputPc,@function
_Z6OutputPc: # @_Z6OutputPc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl $.L.str.3, %esi
callq fopen
movq %rax, %rbx
movl $1048576, %edi # imm = 0x100000
callq _Znam
movl $1048576, %ecx # imm = 0x100000
movq %rbx, %rdi
movq %rax, %rsi
xorl %edx, %edx
callq setvbuf
cmpl $0, n(%rip)
jle .LBB1_7
# %bb.1: # %.preheader.preheader
xorl %ebp, %ebp
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_6: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movl $10, %edi
movq %rbx, %rsi
callq fputc@PLT
incl %ebp
cmpl n(%rip), %ebp
jge .LBB1_7
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
movl n(%rip), %eax
testl %eax, %eax
jle .LBB1_6
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB1_2 Depth=1
xorl %r14d, %r14d
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_8: # in Loop: Header=BB1_4 Depth=2
movl $.L.str.5, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq fprintf
.LBB1_9: # in Loop: Header=BB1_4 Depth=2
movl n(%rip), %eax
incq %r14
cmpl %eax, %r14d
jge .LBB1_6
.LBB1_4: # %.lr.ph
# Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movq host_D(%rip), %rcx
imull %ebp, %eax
cltq
addq %r14, %rax
movl (%rcx,%rax,4), %edx
cmpl $10000000, %edx # imm = 0x989680
jl .LBB1_8
# %bb.5: # in Loop: Header=BB1_4 Depth=2
movl $.L.str.4, %edi
movl $4, %esi
movl $1, %edx
movq %rbx, %rcx
callq fwrite@PLT
jmp .LBB1_9
.LBB1_7: # %._crit_edge18
movq %rbx, %rdi
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end1:
.size _Z6OutputPc, .Lfunc_end1-_Z6OutputPc
.cfi_endproc
# -- End function
.globl _Z20__device_stub__func1iiiPi # -- Begin function _Z20__device_stub__func1iiiPi
.p2align 4, 0x90
.type _Z20__device_stub__func1iiiPi,@function
_Z20__device_stub__func1iiiPi: # @_Z20__device_stub__func1iiiPi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5func1iiiPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z20__device_stub__func1iiiPi, .Lfunc_end2-_Z20__device_stub__func1iiiPi
.cfi_endproc
# -- End function
.globl _Z20__device_stub__func2iiiPi # -- Begin function _Z20__device_stub__func2iiiPi
.p2align 4, 0x90
.type _Z20__device_stub__func2iiiPi,@function
_Z20__device_stub__func2iiiPi: # @_Z20__device_stub__func2iiiPi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5func2iiiPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z20__device_stub__func2iiiPi, .Lfunc_end3-_Z20__device_stub__func2iiiPi
.cfi_endproc
# -- End function
.globl _Z20__device_stub__func3iiiPi # -- Begin function _Z20__device_stub__func3iiiPi
.p2align 4, 0x90
.type _Z20__device_stub__func3iiiPi,@function
_Z20__device_stub__func3iiiPi: # @_Z20__device_stub__func3iiiPi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5func3iiiPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end4:
.size _Z20__device_stub__func3iiiPi, .Lfunc_end4-_Z20__device_stub__func3iiiPi
.cfi_endproc
# -- End function
.globl _Z5Blocki # -- Begin function _Z5Blocki
.p2align 4, 0x90
.type _Z5Blocki,@function
_Z5Blocki: # @_Z5Blocki
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edi, %ebx
movl n(%rip), %esi
imull %esi, %esi
shlq $2, %rsi
movl $dev_D, %edi
callq hipMalloc
movq dev_D(%rip), %rdi
movq host_D(%rip), %rsi
movl n(%rip), %edx
imull %edx, %edx
shlq $2, %rdx
movl $1, %ecx
callq hipMemcpy
movl n(%rip), %eax
addl %ebx, %eax
decl %eax
cltd
idivl %ebx
testl %eax, %eax
jle .LBB5_9
# %bb.1: # %.lr.ph
movq %rbx, %r12
movl %eax, %r14d
movabsq $4294967297, %rax # imm = 0x100000001
movabsq $8589934592, %rcx # imm = 0x200000000
orq %r14, %rcx
movq %rcx, 128(%rsp) # 8-byte Spill
movq %r14, %r13
shlq $32, %r13
orq %r14, %r13
movl %r12d, %ebp
imull %ebp, %ebp
leaq (%rax,%rbp), %r15
decq %r15
leaq (,%rbp,4), %rax
movq %rax, 120(%rsp) # 8-byte Spill
addl %ebp, %ebp
shlq $2, %rbp
xorl %ebx, %ebx
jmp .LBB5_2
.p2align 4, 0x90
.LBB5_8: # in Loop: Header=BB5_2 Depth=1
incl %ebx
cmpl %ebx, %r14d
je .LBB5_9
.LBB5_2: # =>This Inner Loop Header: Depth=1
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
movq 120(%rsp), %r8 # 8-byte Reload
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_4
# %bb.3: # in Loop: Header=BB5_2 Depth=1
movl n(%rip), %eax
movq dev_D(%rip), %rcx
movl %eax, 20(%rsp)
movl %r12d, 16(%rsp)
movl %ebx, 12(%rsp)
movq %rcx, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z5func1iiiPi, %edi
leaq 80(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_4: # in Loop: Header=BB5_2 Depth=1
movq 128(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
movq %rbp, %r8
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_6
# %bb.5: # in Loop: Header=BB5_2 Depth=1
movl n(%rip), %eax
movq dev_D(%rip), %rcx
movl %eax, 20(%rsp)
movl %r12d, 16(%rsp)
movl %ebx, 12(%rsp)
movq %rcx, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z5func2iiiPi, %edi
leaq 80(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_6: # in Loop: Header=BB5_2 Depth=1
movq %r13, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
movq %rbp, %r8
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_8
# %bb.7: # in Loop: Header=BB5_2 Depth=1
movl n(%rip), %eax
movq dev_D(%rip), %rcx
movl %eax, 20(%rsp)
movl %r12d, 16(%rsp)
movl %ebx, 12(%rsp)
movq %rcx, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z5func3iiiPi, %edi
leaq 80(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB5_8
.LBB5_9: # %._crit_edge
callq hipDeviceSynchronize
movq host_D(%rip), %rdi
movq dev_D(%rip), %rsi
movl n(%rip), %edx
imull %edx, %edx
shlq $2, %rdx
movl $2, %ecx
callq hipMemcpy
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z5Blocki, .Lfunc_end5-_Z5Blocki
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rsi, %rbx
movq 8(%rsi), %rdi
callq _Z5InputPc
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, %edi
callq _Z5Blocki
movq 16(%rbx), %rdi
callq _Z6OutputPc
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5func1iiiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5func2iiiPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5func3iiiPi, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type host_D,@object # @host_D
.bss
.globl host_D
.p2align 3, 0x0
host_D:
.quad 0
.size host_D, 8
.type dev_D,@object # @dev_D
.globl dev_D
.p2align 3, 0x0
dev_D:
.quad 0
.size dev_D, 8
.type n,@object # @n
.globl n
.p2align 2, 0x0
n:
.long 0 # 0x0
.size n, 4
.type m,@object # @m
.globl m
.p2align 2, 0x0
m:
.long 0 # 0x0
.size m, 4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d %d"
.size .L.str.1, 6
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d %d %d"
.size .L.str.2, 9
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "w"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "INF "
.size .L.str.4, 5
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d "
.size .L.str.5, 4
.type _Z5func1iiiPi,@object # @_Z5func1iiiPi
.section .rodata,"a",@progbits
.globl _Z5func1iiiPi
.p2align 3, 0x0
_Z5func1iiiPi:
.quad _Z20__device_stub__func1iiiPi
.size _Z5func1iiiPi, 8
.type _Z5func2iiiPi,@object # @_Z5func2iiiPi
.globl _Z5func2iiiPi
.p2align 3, 0x0
_Z5func2iiiPi:
.quad _Z20__device_stub__func2iiiPi
.size _Z5func2iiiPi, 8
.type _Z5func3iiiPi,@object # @_Z5func3iiiPi
.globl _Z5func3iiiPi
.p2align 3, 0x0
_Z5func3iiiPi:
.quad _Z20__device_stub__func3iiiPi
.size _Z5func3iiiPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5func1iiiPi"
.size .L__unnamed_1, 14
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z5func2iiiPi"
.size .L__unnamed_2, 14
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z5func3iiiPi"
.size .L__unnamed_3, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__func1iiiPi
.addrsig_sym _Z20__device_stub__func2iiiPi
.addrsig_sym _Z20__device_stub__func3iiiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym dev_D
.addrsig_sym n
.addrsig_sym m
.addrsig_sym _Z5func1iiiPi
.addrsig_sym _Z5func2iiiPi
.addrsig_sym _Z5func3iiiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #define N 10000000
__global__ void vector_add(float *out, float *a, float *b, int n) {
for(int i = 0; i < n; i++){
out[i] = a[i] + b[i];
}
}
int main(){
float *a, *b, *out;
float *d_a;
a = (float*)malloc(sizeof(float) * N);
// Allocate device memory for a
cudaMalloc((void**)&d_a, sizeof(float) * N);
// Transfer data from host to device memory
cudaMemcpy(d_a, a, sizeof(float) * N, cudaMemcpyHostToDevice);
vector_add<<<1,1>>>(out, d_a, b, N);
// Cleanup after kernel execution
cudaFree(d_a);
free(a);
return 0;
} | code for sm_80
Function : _Z10vector_addPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007ffe0ff */
/*0050*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0060*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe200078ec0ff */
/*0070*/ ULDC.64 UR12, c[0x0][0x118] ; /* 0x00004600000c7ab9 */
/* 0x000fe20000000a00 */
/*0080*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0090*/ @!P0 BRA 0xb80 ; /* 0x00000ae000008947 */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R8, -R0, c[0x0][0x178], RZ ; /* 0x00005e0000087a10 */
/* 0x000fe20007ffe1ff */
/*00b0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00c0*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe20000000f00 */
/*00d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*00e0*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f04270 */
/*00f0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fe200078e00ff */
/*0100*/ MOV R2, c[0x0][0x170] ; /* 0x00005c0000027a02 */
/* 0x000fe20000000f00 */
/*0110*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff077624 */
/* 0x000fe200078e00ff */
/*0120*/ MOV R6, c[0x0][0x168] ; /* 0x00005a0000067a02 */
/* 0x000fd20000000f00 */
/*0130*/ @!P0 BRA 0x990 ; /* 0x0000085000008947 */
/* 0x000fea0003800000 */
/*0140*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f24270 */
/*0150*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0160*/ @!P1 BRA 0x670 ; /* 0x0000050000009947 */
/* 0x000fea0003800000 */
/*0170*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0180*/ LDG.E R9, [R2.64] ; /* 0x0000000c02097981 */
/* 0x000ea8000c1e1900 */
/*0190*/ LDG.E R10, [R6.64] ; /* 0x0000000c060a7981 */
/* 0x000ea4000c1e1900 */
/*01a0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x004fca0000000000 */
/*01b0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e8000c10190c */
/*01c0*/ LDG.E R10, [R2.64+0x4] ; /* 0x0000040c020a7981 */
/* 0x000ea8000c1e1900 */
/*01d0*/ LDG.E R11, [R6.64+0x4] ; /* 0x0000040c060b7981 */
/* 0x000ea4000c1e1900 */
/*01e0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x004fca0000000000 */
/*01f0*/ STG.E [R4.64+0x4], R11 ; /* 0x0000040b04007986 */
/* 0x0003e8000c10190c */
/*0200*/ LDG.E R10, [R2.64+0x8] ; /* 0x0000080c020a7981 */
/* 0x000ea8000c1e1900 */
/*0210*/ LDG.E R13, [R6.64+0x8] ; /* 0x0000080c060d7981 */
/* 0x000ea4000c1e1900 */
/*0220*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x004fca0000000000 */
/*0230*/ STG.E [R4.64+0x8], R13 ; /* 0x0000080d04007986 */
/* 0x0005e8000c10190c */
/*0240*/ LDG.E R10, [R2.64+0xc] ; /* 0x00000c0c020a7981 */
/* 0x000ee8000c1e1900 */
/*0250*/ LDG.E R15, [R6.64+0xc] ; /* 0x00000c0c060f7981 */
/* 0x000ee4000c1e1900 */
/*0260*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x008fca0000000000 */
/*0270*/ STG.E [R4.64+0xc], R15 ; /* 0x00000c0f04007986 */
/* 0x0007e8000c10190c */
/*0280*/ LDG.E R9, [R2.64+0x10] ; /* 0x0000100c02097981 */
/* 0x001f28000c1e1900 */
/*0290*/ LDG.E R10, [R6.64+0x10] ; /* 0x0000100c060a7981 */
/* 0x000f24000c1e1900 */
/*02a0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x010fca0000000000 */
/*02b0*/ STG.E [R4.64+0x10], R9 ; /* 0x0000100904007986 */
/* 0x0001e8000c10190c */
/*02c0*/ LDG.E R10, [R2.64+0x14] ; /* 0x0000140c020a7981 */
/* 0x000f28000c1e1900 */
/*02d0*/ LDG.E R11, [R6.64+0x14] ; /* 0x0000140c060b7981 */
/* 0x002f24000c1e1900 */
/*02e0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x010fca0000000000 */
/*02f0*/ STG.E [R4.64+0x14], R11 ; /* 0x0000140b04007986 */
/* 0x0003e8000c10190c */
/*0300*/ LDG.E R10, [R2.64+0x18] ; /* 0x0000180c020a7981 */
/* 0x000f28000c1e1900 */
/*0310*/ LDG.E R13, [R6.64+0x18] ; /* 0x0000180c060d7981 */
/* 0x004f24000c1e1900 */
/*0320*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x010fca0000000000 */
/*0330*/ STG.E [R4.64+0x18], R13 ; /* 0x0000180d04007986 */
/* 0x0005e8000c10190c */
/*0340*/ LDG.E R10, [R2.64+0x1c] ; /* 0x00001c0c020a7981 */
/* 0x000f28000c1e1900 */
/*0350*/ LDG.E R15, [R6.64+0x1c] ; /* 0x00001c0c060f7981 */
/* 0x008f24000c1e1900 */
/*0360*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x010fca0000000000 */
/*0370*/ STG.E [R4.64+0x1c], R15 ; /* 0x00001c0f04007986 */
/* 0x0007e8000c10190c */
/*0380*/ LDG.E R9, [R2.64+0x20] ; /* 0x0000200c02097981 */
/* 0x001f28000c1e1900 */
/*0390*/ LDG.E R10, [R6.64+0x20] ; /* 0x0000200c060a7981 */
/* 0x000f24000c1e1900 */
/*03a0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x010fca0000000000 */
/*03b0*/ STG.E [R4.64+0x20], R9 ; /* 0x0000200904007986 */
/* 0x0001e8000c10190c */
/*03c0*/ LDG.E R10, [R2.64+0x24] ; /* 0x0000240c020a7981 */
/* 0x000f28000c1e1900 */
/*03d0*/ LDG.E R11, [R6.64+0x24] ; /* 0x0000240c060b7981 */
/* 0x002f24000c1e1900 */
/*03e0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x010fca0000000000 */
/*03f0*/ STG.E [R4.64+0x24], R11 ; /* 0x0000240b04007986 */
/* 0x0003e8000c10190c */
/*0400*/ LDG.E R10, [R2.64+0x28] ; /* 0x0000280c020a7981 */
/* 0x000f28000c1e1900 */
/*0410*/ LDG.E R13, [R6.64+0x28] ; /* 0x0000280c060d7981 */
/* 0x004f24000c1e1900 */
/*0420*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x010fca0000000000 */
/*0430*/ STG.E [R4.64+0x28], R13 ; /* 0x0000280d04007986 */
/* 0x0005e8000c10190c */
/*0440*/ LDG.E R10, [R2.64+0x2c] ; /* 0x00002c0c020a7981 */
/* 0x000f28000c1e1900 */
/*0450*/ LDG.E R15, [R6.64+0x2c] ; /* 0x00002c0c060f7981 */
/* 0x008f24000c1e1900 */
/*0460*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x010fca0000000000 */
/*0470*/ STG.E [R4.64+0x2c], R15 ; /* 0x00002c0f04007986 */
/* 0x0007e8000c10190c */
/*0480*/ LDG.E R9, [R2.64+0x30] ; /* 0x0000300c02097981 */
/* 0x001f28000c1e1900 */
/*0490*/ LDG.E R10, [R6.64+0x30] ; /* 0x0000300c060a7981 */
/* 0x000f24000c1e1900 */
/*04a0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x010fca0000000000 */
/*04b0*/ STG.E [R4.64+0x30], R9 ; /* 0x0000300904007986 */
/* 0x000fe8000c10190c */
/*04c0*/ LDG.E R10, [R2.64+0x34] ; /* 0x0000340c020a7981 */
/* 0x000f28000c1e1900 */
/*04d0*/ LDG.E R11, [R6.64+0x34] ; /* 0x0000340c060b7981 */
/* 0x002f24000c1e1900 */
/*04e0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x010fca0000000000 */
/*04f0*/ STG.E [R4.64+0x34], R11 ; /* 0x0000340b04007986 */
/* 0x0001e8000c10190c */
/*0500*/ LDG.E R10, [R2.64+0x38] ; /* 0x0000380c020a7981 */
/* 0x000f28000c1e1900 */
/*0510*/ LDG.E R13, [R6.64+0x38] ; /* 0x0000380c060d7981 */
/* 0x004f22000c1e1900 */
/*0520*/ IADD3 R12, P1, R2, 0x40, RZ ; /* 0x00000040020c7810 */
/* 0x000fe40007f3e0ff */
/*0530*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fe20007ffe0ff */
/*0540*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x010fca0000000000 */
/*0550*/ STG.E [R4.64+0x38], R13 ; /* 0x0000380d04007986 */
/* 0x000fe8000c10190c */
/*0560*/ LDG.E R10, [R2.64+0x3c] ; /* 0x00003c0c020a7981 */
/* 0x0002a8000c1e1900 */
/*0570*/ LDG.E R15, [R6.64+0x3c] ; /* 0x00003c0c060f7981 */
/* 0x0086a2000c1e1900 */
/*0580*/ IADD3.X R11, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff0b7210 */
/* 0x001fe20000ffe4ff */
/*0590*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe2000fffe03f */
/*05a0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fc40003f24270 */
/*05b0*/ IADD3 R9, P3, R4, 0x40, RZ ; /* 0x0000004004097810 */
/* 0x000fe20007f7e0ff */
/*05c0*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x002fe200078e000c */
/*05d0*/ IADD3 R14, P2, R6, 0x40, RZ ; /* 0x00000040060e7810 */
/* 0x000fe40007f5e0ff */
/*05e0*/ MOV R3, R11 ; /* 0x0000000b00037202 */
/* 0x000fc60000000f00 */
/*05f0*/ IMAD.X R7, RZ, RZ, R7, P2 ; /* 0x000000ffff077224 */
/* 0x008fe400010e0607 */
/*0600*/ IMAD.MOV.U32 R6, RZ, RZ, R14 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000e */
/*0610*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x004fe20000000000 */
/*0620*/ IADD3.X R10, RZ, R5, RZ, P3, !PT ; /* 0x00000005ff0a7210 */
/* 0x000fc80001ffe4ff */
/*0630*/ STG.E [R4.64+0x3c], R15 ; /* 0x00003c0f04007986 */
/* 0x0001e4000c10190c */
/*0640*/ MOV R4, R9 ; /* 0x0000000900047202 */
/* 0x001fe20000000f00 */
/*0650*/ IMAD.MOV.U32 R5, RZ, RZ, R10 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000a */
/*0660*/ @P1 BRA 0x180 ; /* 0xfffffb1000001947 */
/* 0x000fea000383ffff */
/*0670*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*0680*/ @!P1 BRA 0x970 ; /* 0x000002e000009947 */
/* 0x000fea0003800000 */
/*0690*/ LDG.E R9, [R2.64] ; /* 0x0000000c02097981 */
/* 0x000ea8000c1e1900 */
/*06a0*/ LDG.E R10, [R6.64] ; /* 0x0000000c060a7981 */
/* 0x000ea4000c1e1900 */
/*06b0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x004fca0000000000 */
/*06c0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e8000c10190c */
/*06d0*/ LDG.E R10, [R2.64+0x4] ; /* 0x0000040c020a7981 */
/* 0x000ea8000c1e1900 */
/*06e0*/ LDG.E R11, [R6.64+0x4] ; /* 0x0000040c060b7981 */
/* 0x000ea4000c1e1900 */
/*06f0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x004fca0000000000 */
/*0700*/ STG.E [R4.64+0x4], R11 ; /* 0x0000040b04007986 */
/* 0x0003e8000c10190c */
/*0710*/ LDG.E R10, [R2.64+0x8] ; /* 0x0000080c020a7981 */
/* 0x000ea8000c1e1900 */
/*0720*/ LDG.E R13, [R6.64+0x8] ; /* 0x0000080c060d7981 */
/* 0x000ea4000c1e1900 */
/*0730*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x004fca0000000000 */
/*0740*/ STG.E [R4.64+0x8], R13 ; /* 0x0000080d04007986 */
/* 0x0005e8000c10190c */
/*0750*/ LDG.E R10, [R2.64+0xc] ; /* 0x00000c0c020a7981 */
/* 0x000ee8000c1e1900 */
/*0760*/ LDG.E R15, [R6.64+0xc] ; /* 0x00000c0c060f7981 */
/* 0x000ee4000c1e1900 */
/*0770*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x008fca0000000000 */
/*0780*/ STG.E [R4.64+0xc], R15 ; /* 0x00000c0f04007986 */
/* 0x0007e8000c10190c */
/*0790*/ LDG.E R9, [R2.64+0x10] ; /* 0x0000100c02097981 */
/* 0x001f28000c1e1900 */
/*07a0*/ LDG.E R10, [R6.64+0x10] ; /* 0x0000100c060a7981 */
/* 0x000f24000c1e1900 */
/*07b0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x010fca0000000000 */
/*07c0*/ STG.E [R4.64+0x10], R9 ; /* 0x0000100904007986 */
/* 0x000fe8000c10190c */
/*07d0*/ LDG.E R10, [R2.64+0x14] ; /* 0x0000140c020a7981 */
/* 0x000f28000c1e1900 */
/*07e0*/ LDG.E R11, [R6.64+0x14] ; /* 0x0000140c060b7981 */
/* 0x002f24000c1e1900 */
/*07f0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x010fca0000000000 */
/*0800*/ STG.E [R4.64+0x14], R11 ; /* 0x0000140b04007986 */
/* 0x0001e8000c10190c */
/*0810*/ LDG.E R10, [R2.64+0x18] ; /* 0x0000180c020a7981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R13, [R6.64+0x18] ; /* 0x0000180c060d7981 */
/* 0x004f24000c1e1900 */
/*0830*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x010fca0000000000 */
/*0840*/ STG.E [R4.64+0x18], R13 ; /* 0x0000180d04007986 */
/* 0x000fe8000c10190c */
/*0850*/ LDG.E R10, [R2.64+0x1c] ; /* 0x00001c0c020a7981 */
/* 0x0002a8000c1e1900 */
/*0860*/ LDG.E R15, [R6.64+0x1c] ; /* 0x00001c0c060f7981 */
/* 0x0086a2000c1e1900 */
/*0870*/ IADD3 R11, P2, R2, 0x20, RZ ; /* 0x00000020020b7810 */
/* 0x001fe20007f5e0ff */
/*0880*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0890*/ IADD3 R9, P3, R4, 0x20, RZ ; /* 0x0000002004097810 */
/* 0x000fc40007f7e0ff */
/*08a0*/ IADD3 R14, P1, R6, 0x20, RZ ; /* 0x00000020060e7810 */
/* 0x000fe20007f3e0ff */
/*08b0*/ IMAD.X R12, RZ, RZ, R3, P2 ; /* 0x000000ffff0c7224 */
/* 0x000fe200010e0603 */
/*08c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*08d0*/ IMAD.MOV.U32 R2, RZ, RZ, R11 ; /* 0x000000ffff027224 */
/* 0x002fe200078e000b */
/*08e0*/ IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808087810 */
/* 0x000fe20007ffe0ff */
/*08f0*/ IMAD.MOV.U32 R6, RZ, RZ, R14 ; /* 0x000000ffff067224 */
/* 0x008fe200078e000e */
/*0900*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe40000ffe4ff */
/*0910*/ MOV R3, R12 ; /* 0x0000000c00037202 */
/* 0x000fe20000000f00 */
/*0920*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x004fe20000000000 */
/*0930*/ IADD3.X R10, RZ, R5, RZ, P3, !PT ; /* 0x00000005ff0a7210 */
/* 0x000fc80001ffe4ff */
/*0940*/ STG.E [R4.64+0x1c], R15 ; /* 0x00001c0f04007986 */
/* 0x0001e4000c10190c */
/*0950*/ MOV R4, R9 ; /* 0x0000000900047202 */
/* 0x001fe20000000f00 */
/*0960*/ IMAD.MOV.U32 R5, RZ, RZ, R10 ; /* 0x000000ffff057224 */
/* 0x000fe400078e000a */
/*0970*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0000705670 */
/*0980*/ @!P0 BRA 0xb80 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0990*/ LDG.E R9, [R2.64] ; /* 0x0000000c02097981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ LDG.E R10, [R6.64] ; /* 0x0000000c060a7981 */
/* 0x000ea4000c1e1900 */
/*09b0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x004fca0000000000 */
/*09c0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe8000c10190c */
/*09d0*/ LDG.E R10, [R2.64+0x4] ; /* 0x0000040c020a7981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R11, [R6.64+0x4] ; /* 0x0000040c060b7981 */
/* 0x000ea4000c1e1900 */
/*09f0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x004fca0000000000 */
/*0a00*/ STG.E [R4.64+0x4], R11 ; /* 0x0000040b04007986 */
/* 0x0001e8000c10190c */
/*0a10*/ LDG.E R10, [R2.64+0x8] ; /* 0x0000080c020a7981 */
/* 0x000ea8000c1e1900 */
/*0a20*/ LDG.E R13, [R6.64+0x8] ; /* 0x0000080c060d7981 */
/* 0x000ea2000c1e1900 */
/*0a30*/ IADD3 R12, P0, R2, 0x10, RZ ; /* 0x00000010020c7810 */
/* 0x000fe40007f1e0ff */
/*0a40*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fe20007ffe0ff */
/*0a50*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x004fca0000000000 */
/*0a60*/ STG.E [R4.64+0x8], R13 ; /* 0x0000080d04007986 */
/* 0x000fe8000c10190c */
/*0a70*/ LDG.E R10, [R2.64+0xc] ; /* 0x00000c0c020a7981 */
/* 0x0002a8000c1e1900 */
/*0a80*/ LDG.E R15, [R6.64+0xc] ; /* 0x00000c0c060f7981 */
/* 0x0006a2000c1e1900 */
/*0a90*/ IADD3.X R11, RZ, R3, RZ, P0, !PT ; /* 0x00000003ff0b7210 */
/* 0x001fe200007fe4ff */
/*0aa0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0ab0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc40003f05270 */
/*0ac0*/ IADD3 R9, P2, R4, 0x10, RZ ; /* 0x0000001004097810 */
/* 0x000fe20007f5e0ff */
/*0ad0*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x002fe200078e000c */
/*0ae0*/ IADD3 R14, P1, R6, 0x10, RZ ; /* 0x00000010060e7810 */
/* 0x000fe40007f3e0ff */
/*0af0*/ MOV R3, R11 ; /* 0x0000000b00037202 */
/* 0x000fc60000000f00 */
/*0b00*/ IMAD.X R7, RZ, RZ, R7, P1 ; /* 0x000000ffff077224 */
/* 0x008fe400008e0607 */
/*0b10*/ IMAD.MOV.U32 R6, RZ, RZ, R14 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000e */
/*0b20*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x004fe20000000000 */
/*0b30*/ IADD3.X R10, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff0a7210 */
/* 0x000fc800017fe4ff */
/*0b40*/ STG.E [R4.64+0xc], R15 ; /* 0x00000c0f04007986 */
/* 0x0001e4000c10190c */
/*0b50*/ MOV R4, R9 ; /* 0x0000000900047202 */
/* 0x001fe20000000f00 */
/*0b60*/ IMAD.MOV.U32 R5, RZ, RZ, R10 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000a */
/*0b70*/ @P0 BRA 0x990 ; /* 0xfffffe1000000947 */
/* 0x000fea000383ffff */
/*0b80*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0b90*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0ba0*/ UMOV UR5, 0x4 ; /* 0x0000000400057882 */
/* 0x000fe40000000000 */
/*0bb0*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe40000000a00 */
/*0bc0*/ ULDC.64 UR8, c[0x0][0x170] ; /* 0x00005c0000087ab9 */
/* 0x000fe40000000a00 */
/*0bd0*/ ULDC.64 UR10, c[0x0][0x168] ; /* 0x00005a00000a7ab9 */
/* 0x000fe40000000a00 */
/*0be0*/ UIMAD.WIDE UR6, UR4, UR5, UR6 ; /* 0x00000005040672a5 */
/* 0x000fe4000f8e0206 */
/*0bf0*/ UIMAD.WIDE UR8, UR4, UR5, UR8 ; /* 0x00000005040872a5 */
/* 0x000fc4000f8e0208 */
/*0c00*/ UIMAD.WIDE UR4, UR4, UR5, UR10 ; /* 0x00000005040472a5 */
/* 0x000fca000f8e020a */
/*0c10*/ MOV R2, UR8 ; /* 0x0000000800027c02 */
/* 0x000fe20008000f00 */
/*0c20*/ IMAD.U32 R5, RZ, RZ, UR5 ; /* 0x00000005ff057e24 */
/* 0x000fe2000f8e00ff */
/*0c30*/ MOV R4, UR4 ; /* 0x0000000400047c02 */
/* 0x000fe20008000f00 */
/*0c40*/ IMAD.U32 R3, RZ, RZ, UR9 ; /* 0x00000009ff037e24 */
/* 0x000fc8000f8e00ff */
/*0c50*/ LDG.E R5, [R4.64] ; /* 0x0000000c04057981 */
/* 0x000ea8000c1e1900 */
/*0c60*/ LDG.E R2, [R2.64] ; /* 0x0000000c02027981 */
/* 0x000ea2000c1e1900 */
/*0c70*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fc80007ffe0ff */
/*0c80*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0c90*/ UIADD3 UR8, UP1, UR8, 0x4, URZ ; /* 0x0000000408087890 */
/* 0x000fe2000ff3e03f */
/*0ca0*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x001fe20008000f00 */
/*0cb0*/ UIADD3 UR6, UP0, UR6, 0x4, URZ ; /* 0x0000000406067890 */
/* 0x000fe2000ff1e03f */
/*0cc0*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fe20008000f00 */
/*0cd0*/ UIADD3 UR4, UP2, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe4000ff5e03f */
/*0ce0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe400087fe43f */
/*0cf0*/ UIADD3.X UR9, URZ, UR9, URZ, UP1, !UPT ; /* 0x000000093f097290 */
/* 0x000fe40008ffe43f */
/*0d00*/ UIADD3.X UR5, URZ, UR5, URZ, UP2, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200097fe43f */
/*0d10*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*0d20*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e2000c10190c */
/*0d30*/ @P0 BRA 0xc10 ; /* 0xfffffed000000947 */
/* 0x000fea000383ffff */
/*0d40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d50*/ BRA 0xd50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define N 10000000
__global__ void vector_add(float *out, float *a, float *b, int n) {
for(int i = 0; i < n; i++){
out[i] = a[i] + b[i];
}
}
int main(){
float *a, *b, *out;
float *d_a;
a = (float*)malloc(sizeof(float) * N);
// Allocate device memory for a
cudaMalloc((void**)&d_a, sizeof(float) * N);
// Transfer data from host to device memory
cudaMemcpy(d_a, a, sizeof(float) * N, cudaMemcpyHostToDevice);
vector_add<<<1,1>>>(out, d_a, b, N);
// Cleanup after kernel execution
cudaFree(d_a);
free(a);
return 0;
} | .file "tmpxft_000d45d1_00000000-6_CUDA_Basics.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
.type _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i, @function
_Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10vector_addPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i, .-_Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
.globl _Z10vector_addPfS_S_i
.type _Z10vector_addPfS_S_i, @function
_Z10vector_addPfS_S_i:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z10vector_addPfS_S_i, .-_Z10vector_addPfS_S_i
.globl main
.type main, @function
main:
.LFB2027:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $40000000, %edi
call malloc@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $40000000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $40000000, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl $10000000, %ecx
movl $0, %edx
movq 8(%rsp), %rsi
movl $0, %edi
call _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10vector_addPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10vector_addPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define N 10000000
__global__ void vector_add(float *out, float *a, float *b, int n) {
for(int i = 0; i < n; i++){
out[i] = a[i] + b[i];
}
}
int main(){
float *a, *b, *out;
float *d_a;
a = (float*)malloc(sizeof(float) * N);
// Allocate device memory for a
cudaMalloc((void**)&d_a, sizeof(float) * N);
// Transfer data from host to device memory
cudaMemcpy(d_a, a, sizeof(float) * N, cudaMemcpyHostToDevice);
vector_add<<<1,1>>>(out, d_a, b, N);
// Cleanup after kernel execution
cudaFree(d_a);
free(a);
return 0;
} | #include <hip/hip_runtime.h>
#define N 10000000
__global__ void vector_add(float *out, float *a, float *b, int n) {
for(int i = 0; i < n; i++){
out[i] = a[i] + b[i];
}
}
int main(){
float *a, *b, *out;
float *d_a;
a = (float*)malloc(sizeof(float) * N);
// Allocate device memory for a
hipMalloc((void**)&d_a, sizeof(float) * N);
// Transfer data from host to device memory
hipMemcpy(d_a, a, sizeof(float) * N, hipMemcpyHostToDevice);
vector_add<<<1,1>>>(out, d_a, b, N);
// Cleanup after kernel execution
hipFree(d_a);
free(a);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#define N 10000000
__global__ void vector_add(float *out, float *a, float *b, int n) {
for(int i = 0; i < n; i++){
out[i] = a[i] + b[i];
}
}
int main(){
float *a, *b, *out;
float *d_a;
a = (float*)malloc(sizeof(float) * N);
// Allocate device memory for a
hipMalloc((void**)&d_a, sizeof(float) * N);
// Transfer data from host to device memory
hipMemcpy(d_a, a, sizeof(float) * N, hipMemcpyHostToDevice);
vector_add<<<1,1>>>(out, d_a, b, N);
// Cleanup after kernel execution
hipFree(d_a);
free(a);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10vector_addPfS_S_i
.globl _Z10vector_addPfS_S_i
.p2align 8
.type _Z10vector_addPfS_S_i,@function
_Z10vector_addPfS_S_i:
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v0, 0
.LBB0_2:
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[6:7]
global_load_b32 v2, v0, s[0:1]
s_add_i32 s2, s2, -1
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[4:5]
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s2, 0
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10vector_addPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10vector_addPfS_S_i, .Lfunc_end0-_Z10vector_addPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10vector_addPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z10vector_addPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#define N 10000000
__global__ void vector_add(float *out, float *a, float *b, int n) {
for(int i = 0; i < n; i++){
out[i] = a[i] + b[i];
}
}
int main(){
float *a, *b, *out;
float *d_a;
a = (float*)malloc(sizeof(float) * N);
// Allocate device memory for a
hipMalloc((void**)&d_a, sizeof(float) * N);
// Transfer data from host to device memory
hipMemcpy(d_a, a, sizeof(float) * N, hipMemcpyHostToDevice);
vector_add<<<1,1>>>(out, d_a, b, N);
// Cleanup after kernel execution
hipFree(d_a);
free(a);
return 0;
} | .text
.file "CUDA_Basics.hip"
.globl _Z25__device_stub__vector_addPfS_S_i # -- Begin function _Z25__device_stub__vector_addPfS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__vector_addPfS_S_i,@function
_Z25__device_stub__vector_addPfS_S_i: # @_Z25__device_stub__vector_addPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10vector_addPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__vector_addPfS_S_i, .Lfunc_end0-_Z25__device_stub__vector_addPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $128, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -16
movl $40000000, %edi # imm = 0x2625A00
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $40000000, %esi # imm = 0x2625A00
callq hipMalloc
movq 8(%rsp), %rdi
movl $40000000, %edx # imm = 0x2625A00
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $10000000, 20(%rsp) # imm = 0x989680
leaq 120(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 112(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10vector_addPfS_S_i, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10vector_addPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10vector_addPfS_S_i,@object # @_Z10vector_addPfS_S_i
.section .rodata,"a",@progbits
.globl _Z10vector_addPfS_S_i
.p2align 3, 0x0
_Z10vector_addPfS_S_i:
.quad _Z25__device_stub__vector_addPfS_S_i
.size _Z10vector_addPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10vector_addPfS_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__vector_addPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10vector_addPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10vector_addPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007ffe0ff */
/*0050*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0060*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe200078ec0ff */
/*0070*/ ULDC.64 UR12, c[0x0][0x118] ; /* 0x00004600000c7ab9 */
/* 0x000fe20000000a00 */
/*0080*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0090*/ @!P0 BRA 0xb80 ; /* 0x00000ae000008947 */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R8, -R0, c[0x0][0x178], RZ ; /* 0x00005e0000087a10 */
/* 0x000fe20007ffe1ff */
/*00b0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00c0*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe20000000f00 */
/*00d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*00e0*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f04270 */
/*00f0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fe200078e00ff */
/*0100*/ MOV R2, c[0x0][0x170] ; /* 0x00005c0000027a02 */
/* 0x000fe20000000f00 */
/*0110*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff077624 */
/* 0x000fe200078e00ff */
/*0120*/ MOV R6, c[0x0][0x168] ; /* 0x00005a0000067a02 */
/* 0x000fd20000000f00 */
/*0130*/ @!P0 BRA 0x990 ; /* 0x0000085000008947 */
/* 0x000fea0003800000 */
/*0140*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f24270 */
/*0150*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0160*/ @!P1 BRA 0x670 ; /* 0x0000050000009947 */
/* 0x000fea0003800000 */
/*0170*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0180*/ LDG.E R9, [R2.64] ; /* 0x0000000c02097981 */
/* 0x000ea8000c1e1900 */
/*0190*/ LDG.E R10, [R6.64] ; /* 0x0000000c060a7981 */
/* 0x000ea4000c1e1900 */
/*01a0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x004fca0000000000 */
/*01b0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e8000c10190c */
/*01c0*/ LDG.E R10, [R2.64+0x4] ; /* 0x0000040c020a7981 */
/* 0x000ea8000c1e1900 */
/*01d0*/ LDG.E R11, [R6.64+0x4] ; /* 0x0000040c060b7981 */
/* 0x000ea4000c1e1900 */
/*01e0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x004fca0000000000 */
/*01f0*/ STG.E [R4.64+0x4], R11 ; /* 0x0000040b04007986 */
/* 0x0003e8000c10190c */
/*0200*/ LDG.E R10, [R2.64+0x8] ; /* 0x0000080c020a7981 */
/* 0x000ea8000c1e1900 */
/*0210*/ LDG.E R13, [R6.64+0x8] ; /* 0x0000080c060d7981 */
/* 0x000ea4000c1e1900 */
/*0220*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x004fca0000000000 */
/*0230*/ STG.E [R4.64+0x8], R13 ; /* 0x0000080d04007986 */
/* 0x0005e8000c10190c */
/*0240*/ LDG.E R10, [R2.64+0xc] ; /* 0x00000c0c020a7981 */
/* 0x000ee8000c1e1900 */
/*0250*/ LDG.E R15, [R6.64+0xc] ; /* 0x00000c0c060f7981 */
/* 0x000ee4000c1e1900 */
/*0260*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x008fca0000000000 */
/*0270*/ STG.E [R4.64+0xc], R15 ; /* 0x00000c0f04007986 */
/* 0x0007e8000c10190c */
/*0280*/ LDG.E R9, [R2.64+0x10] ; /* 0x0000100c02097981 */
/* 0x001f28000c1e1900 */
/*0290*/ LDG.E R10, [R6.64+0x10] ; /* 0x0000100c060a7981 */
/* 0x000f24000c1e1900 */
/*02a0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x010fca0000000000 */
/*02b0*/ STG.E [R4.64+0x10], R9 ; /* 0x0000100904007986 */
/* 0x0001e8000c10190c */
/*02c0*/ LDG.E R10, [R2.64+0x14] ; /* 0x0000140c020a7981 */
/* 0x000f28000c1e1900 */
/*02d0*/ LDG.E R11, [R6.64+0x14] ; /* 0x0000140c060b7981 */
/* 0x002f24000c1e1900 */
/*02e0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x010fca0000000000 */
/*02f0*/ STG.E [R4.64+0x14], R11 ; /* 0x0000140b04007986 */
/* 0x0003e8000c10190c */
/*0300*/ LDG.E R10, [R2.64+0x18] ; /* 0x0000180c020a7981 */
/* 0x000f28000c1e1900 */
/*0310*/ LDG.E R13, [R6.64+0x18] ; /* 0x0000180c060d7981 */
/* 0x004f24000c1e1900 */
/*0320*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x010fca0000000000 */
/*0330*/ STG.E [R4.64+0x18], R13 ; /* 0x0000180d04007986 */
/* 0x0005e8000c10190c */
/*0340*/ LDG.E R10, [R2.64+0x1c] ; /* 0x00001c0c020a7981 */
/* 0x000f28000c1e1900 */
/*0350*/ LDG.E R15, [R6.64+0x1c] ; /* 0x00001c0c060f7981 */
/* 0x008f24000c1e1900 */
/*0360*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x010fca0000000000 */
/*0370*/ STG.E [R4.64+0x1c], R15 ; /* 0x00001c0f04007986 */
/* 0x0007e8000c10190c */
/*0380*/ LDG.E R9, [R2.64+0x20] ; /* 0x0000200c02097981 */
/* 0x001f28000c1e1900 */
/*0390*/ LDG.E R10, [R6.64+0x20] ; /* 0x0000200c060a7981 */
/* 0x000f24000c1e1900 */
/*03a0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x010fca0000000000 */
/*03b0*/ STG.E [R4.64+0x20], R9 ; /* 0x0000200904007986 */
/* 0x0001e8000c10190c */
/*03c0*/ LDG.E R10, [R2.64+0x24] ; /* 0x0000240c020a7981 */
/* 0x000f28000c1e1900 */
/*03d0*/ LDG.E R11, [R6.64+0x24] ; /* 0x0000240c060b7981 */
/* 0x002f24000c1e1900 */
/*03e0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x010fca0000000000 */
/*03f0*/ STG.E [R4.64+0x24], R11 ; /* 0x0000240b04007986 */
/* 0x0003e8000c10190c */
/*0400*/ LDG.E R10, [R2.64+0x28] ; /* 0x0000280c020a7981 */
/* 0x000f28000c1e1900 */
/*0410*/ LDG.E R13, [R6.64+0x28] ; /* 0x0000280c060d7981 */
/* 0x004f24000c1e1900 */
/*0420*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x010fca0000000000 */
/*0430*/ STG.E [R4.64+0x28], R13 ; /* 0x0000280d04007986 */
/* 0x0005e8000c10190c */
/*0440*/ LDG.E R10, [R2.64+0x2c] ; /* 0x00002c0c020a7981 */
/* 0x000f28000c1e1900 */
/*0450*/ LDG.E R15, [R6.64+0x2c] ; /* 0x00002c0c060f7981 */
/* 0x008f24000c1e1900 */
/*0460*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x010fca0000000000 */
/*0470*/ STG.E [R4.64+0x2c], R15 ; /* 0x00002c0f04007986 */
/* 0x0007e8000c10190c */
/*0480*/ LDG.E R9, [R2.64+0x30] ; /* 0x0000300c02097981 */
/* 0x001f28000c1e1900 */
/*0490*/ LDG.E R10, [R6.64+0x30] ; /* 0x0000300c060a7981 */
/* 0x000f24000c1e1900 */
/*04a0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x010fca0000000000 */
/*04b0*/ STG.E [R4.64+0x30], R9 ; /* 0x0000300904007986 */
/* 0x000fe8000c10190c */
/*04c0*/ LDG.E R10, [R2.64+0x34] ; /* 0x0000340c020a7981 */
/* 0x000f28000c1e1900 */
/*04d0*/ LDG.E R11, [R6.64+0x34] ; /* 0x0000340c060b7981 */
/* 0x002f24000c1e1900 */
/*04e0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x010fca0000000000 */
/*04f0*/ STG.E [R4.64+0x34], R11 ; /* 0x0000340b04007986 */
/* 0x0001e8000c10190c */
/*0500*/ LDG.E R10, [R2.64+0x38] ; /* 0x0000380c020a7981 */
/* 0x000f28000c1e1900 */
/*0510*/ LDG.E R13, [R6.64+0x38] ; /* 0x0000380c060d7981 */
/* 0x004f22000c1e1900 */
/*0520*/ IADD3 R12, P1, R2, 0x40, RZ ; /* 0x00000040020c7810 */
/* 0x000fe40007f3e0ff */
/*0530*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fe20007ffe0ff */
/*0540*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x010fca0000000000 */
/*0550*/ STG.E [R4.64+0x38], R13 ; /* 0x0000380d04007986 */
/* 0x000fe8000c10190c */
/*0560*/ LDG.E R10, [R2.64+0x3c] ; /* 0x00003c0c020a7981 */
/* 0x0002a8000c1e1900 */
/*0570*/ LDG.E R15, [R6.64+0x3c] ; /* 0x00003c0c060f7981 */
/* 0x0086a2000c1e1900 */
/*0580*/ IADD3.X R11, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff0b7210 */
/* 0x001fe20000ffe4ff */
/*0590*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe2000fffe03f */
/*05a0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fc40003f24270 */
/*05b0*/ IADD3 R9, P3, R4, 0x40, RZ ; /* 0x0000004004097810 */
/* 0x000fe20007f7e0ff */
/*05c0*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x002fe200078e000c */
/*05d0*/ IADD3 R14, P2, R6, 0x40, RZ ; /* 0x00000040060e7810 */
/* 0x000fe40007f5e0ff */
/*05e0*/ MOV R3, R11 ; /* 0x0000000b00037202 */
/* 0x000fc60000000f00 */
/*05f0*/ IMAD.X R7, RZ, RZ, R7, P2 ; /* 0x000000ffff077224 */
/* 0x008fe400010e0607 */
/*0600*/ IMAD.MOV.U32 R6, RZ, RZ, R14 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000e */
/*0610*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x004fe20000000000 */
/*0620*/ IADD3.X R10, RZ, R5, RZ, P3, !PT ; /* 0x00000005ff0a7210 */
/* 0x000fc80001ffe4ff */
/*0630*/ STG.E [R4.64+0x3c], R15 ; /* 0x00003c0f04007986 */
/* 0x0001e4000c10190c */
/*0640*/ MOV R4, R9 ; /* 0x0000000900047202 */
/* 0x001fe20000000f00 */
/*0650*/ IMAD.MOV.U32 R5, RZ, RZ, R10 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000a */
/*0660*/ @P1 BRA 0x180 ; /* 0xfffffb1000001947 */
/* 0x000fea000383ffff */
/*0670*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*0680*/ @!P1 BRA 0x970 ; /* 0x000002e000009947 */
/* 0x000fea0003800000 */
/*0690*/ LDG.E R9, [R2.64] ; /* 0x0000000c02097981 */
/* 0x000ea8000c1e1900 */
/*06a0*/ LDG.E R10, [R6.64] ; /* 0x0000000c060a7981 */
/* 0x000ea4000c1e1900 */
/*06b0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x004fca0000000000 */
/*06c0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e8000c10190c */
/*06d0*/ LDG.E R10, [R2.64+0x4] ; /* 0x0000040c020a7981 */
/* 0x000ea8000c1e1900 */
/*06e0*/ LDG.E R11, [R6.64+0x4] ; /* 0x0000040c060b7981 */
/* 0x000ea4000c1e1900 */
/*06f0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x004fca0000000000 */
/*0700*/ STG.E [R4.64+0x4], R11 ; /* 0x0000040b04007986 */
/* 0x0003e8000c10190c */
/*0710*/ LDG.E R10, [R2.64+0x8] ; /* 0x0000080c020a7981 */
/* 0x000ea8000c1e1900 */
/*0720*/ LDG.E R13, [R6.64+0x8] ; /* 0x0000080c060d7981 */
/* 0x000ea4000c1e1900 */
/*0730*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x004fca0000000000 */
/*0740*/ STG.E [R4.64+0x8], R13 ; /* 0x0000080d04007986 */
/* 0x0005e8000c10190c */
/*0750*/ LDG.E R10, [R2.64+0xc] ; /* 0x00000c0c020a7981 */
/* 0x000ee8000c1e1900 */
/*0760*/ LDG.E R15, [R6.64+0xc] ; /* 0x00000c0c060f7981 */
/* 0x000ee4000c1e1900 */
/*0770*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x008fca0000000000 */
/*0780*/ STG.E [R4.64+0xc], R15 ; /* 0x00000c0f04007986 */
/* 0x0007e8000c10190c */
/*0790*/ LDG.E R9, [R2.64+0x10] ; /* 0x0000100c02097981 */
/* 0x001f28000c1e1900 */
/*07a0*/ LDG.E R10, [R6.64+0x10] ; /* 0x0000100c060a7981 */
/* 0x000f24000c1e1900 */
/*07b0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x010fca0000000000 */
/*07c0*/ STG.E [R4.64+0x10], R9 ; /* 0x0000100904007986 */
/* 0x000fe8000c10190c */
/*07d0*/ LDG.E R10, [R2.64+0x14] ; /* 0x0000140c020a7981 */
/* 0x000f28000c1e1900 */
/*07e0*/ LDG.E R11, [R6.64+0x14] ; /* 0x0000140c060b7981 */
/* 0x002f24000c1e1900 */
/*07f0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x010fca0000000000 */
/*0800*/ STG.E [R4.64+0x14], R11 ; /* 0x0000140b04007986 */
/* 0x0001e8000c10190c */
/*0810*/ LDG.E R10, [R2.64+0x18] ; /* 0x0000180c020a7981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R13, [R6.64+0x18] ; /* 0x0000180c060d7981 */
/* 0x004f24000c1e1900 */
/*0830*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x010fca0000000000 */
/*0840*/ STG.E [R4.64+0x18], R13 ; /* 0x0000180d04007986 */
/* 0x000fe8000c10190c */
/*0850*/ LDG.E R10, [R2.64+0x1c] ; /* 0x00001c0c020a7981 */
/* 0x0002a8000c1e1900 */
/*0860*/ LDG.E R15, [R6.64+0x1c] ; /* 0x00001c0c060f7981 */
/* 0x0086a2000c1e1900 */
/*0870*/ IADD3 R11, P2, R2, 0x20, RZ ; /* 0x00000020020b7810 */
/* 0x001fe20007f5e0ff */
/*0880*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0890*/ IADD3 R9, P3, R4, 0x20, RZ ; /* 0x0000002004097810 */
/* 0x000fc40007f7e0ff */
/*08a0*/ IADD3 R14, P1, R6, 0x20, RZ ; /* 0x00000020060e7810 */
/* 0x000fe20007f3e0ff */
/*08b0*/ IMAD.X R12, RZ, RZ, R3, P2 ; /* 0x000000ffff0c7224 */
/* 0x000fe200010e0603 */
/*08c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*08d0*/ IMAD.MOV.U32 R2, RZ, RZ, R11 ; /* 0x000000ffff027224 */
/* 0x002fe200078e000b */
/*08e0*/ IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808087810 */
/* 0x000fe20007ffe0ff */
/*08f0*/ IMAD.MOV.U32 R6, RZ, RZ, R14 ; /* 0x000000ffff067224 */
/* 0x008fe200078e000e */
/*0900*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe40000ffe4ff */
/*0910*/ MOV R3, R12 ; /* 0x0000000c00037202 */
/* 0x000fe20000000f00 */
/*0920*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x004fe20000000000 */
/*0930*/ IADD3.X R10, RZ, R5, RZ, P3, !PT ; /* 0x00000005ff0a7210 */
/* 0x000fc80001ffe4ff */
/*0940*/ STG.E [R4.64+0x1c], R15 ; /* 0x00001c0f04007986 */
/* 0x0001e4000c10190c */
/*0950*/ MOV R4, R9 ; /* 0x0000000900047202 */
/* 0x001fe20000000f00 */
/*0960*/ IMAD.MOV.U32 R5, RZ, RZ, R10 ; /* 0x000000ffff057224 */
/* 0x000fe400078e000a */
/*0970*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0000705670 */
/*0980*/ @!P0 BRA 0xb80 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0990*/ LDG.E R9, [R2.64] ; /* 0x0000000c02097981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ LDG.E R10, [R6.64] ; /* 0x0000000c060a7981 */
/* 0x000ea4000c1e1900 */
/*09b0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x004fca0000000000 */
/*09c0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe8000c10190c */
/*09d0*/ LDG.E R10, [R2.64+0x4] ; /* 0x0000040c020a7981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R11, [R6.64+0x4] ; /* 0x0000040c060b7981 */
/* 0x000ea4000c1e1900 */
/*09f0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x004fca0000000000 */
/*0a00*/ STG.E [R4.64+0x4], R11 ; /* 0x0000040b04007986 */
/* 0x0001e8000c10190c */
/*0a10*/ LDG.E R10, [R2.64+0x8] ; /* 0x0000080c020a7981 */
/* 0x000ea8000c1e1900 */
/*0a20*/ LDG.E R13, [R6.64+0x8] ; /* 0x0000080c060d7981 */
/* 0x000ea2000c1e1900 */
/*0a30*/ IADD3 R12, P0, R2, 0x10, RZ ; /* 0x00000010020c7810 */
/* 0x000fe40007f1e0ff */
/*0a40*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fe20007ffe0ff */
/*0a50*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x004fca0000000000 */
/*0a60*/ STG.E [R4.64+0x8], R13 ; /* 0x0000080d04007986 */
/* 0x000fe8000c10190c */
/*0a70*/ LDG.E R10, [R2.64+0xc] ; /* 0x00000c0c020a7981 */
/* 0x0002a8000c1e1900 */
/*0a80*/ LDG.E R15, [R6.64+0xc] ; /* 0x00000c0c060f7981 */
/* 0x0006a2000c1e1900 */
/*0a90*/ IADD3.X R11, RZ, R3, RZ, P0, !PT ; /* 0x00000003ff0b7210 */
/* 0x001fe200007fe4ff */
/*0aa0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0ab0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc40003f05270 */
/*0ac0*/ IADD3 R9, P2, R4, 0x10, RZ ; /* 0x0000001004097810 */
/* 0x000fe20007f5e0ff */
/*0ad0*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x002fe200078e000c */
/*0ae0*/ IADD3 R14, P1, R6, 0x10, RZ ; /* 0x00000010060e7810 */
/* 0x000fe40007f3e0ff */
/*0af0*/ MOV R3, R11 ; /* 0x0000000b00037202 */
/* 0x000fc60000000f00 */
/*0b00*/ IMAD.X R7, RZ, RZ, R7, P1 ; /* 0x000000ffff077224 */
/* 0x008fe400008e0607 */
/*0b10*/ IMAD.MOV.U32 R6, RZ, RZ, R14 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000e */
/*0b20*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x004fe20000000000 */
/*0b30*/ IADD3.X R10, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff0a7210 */
/* 0x000fc800017fe4ff */
/*0b40*/ STG.E [R4.64+0xc], R15 ; /* 0x00000c0f04007986 */
/* 0x0001e4000c10190c */
/*0b50*/ MOV R4, R9 ; /* 0x0000000900047202 */
/* 0x001fe20000000f00 */
/*0b60*/ IMAD.MOV.U32 R5, RZ, RZ, R10 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000a */
/*0b70*/ @P0 BRA 0x990 ; /* 0xfffffe1000000947 */
/* 0x000fea000383ffff */
/*0b80*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0b90*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0ba0*/ UMOV UR5, 0x4 ; /* 0x0000000400057882 */
/* 0x000fe40000000000 */
/*0bb0*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe40000000a00 */
/*0bc0*/ ULDC.64 UR8, c[0x0][0x170] ; /* 0x00005c0000087ab9 */
/* 0x000fe40000000a00 */
/*0bd0*/ ULDC.64 UR10, c[0x0][0x168] ; /* 0x00005a00000a7ab9 */
/* 0x000fe40000000a00 */
/*0be0*/ UIMAD.WIDE UR6, UR4, UR5, UR6 ; /* 0x00000005040672a5 */
/* 0x000fe4000f8e0206 */
/*0bf0*/ UIMAD.WIDE UR8, UR4, UR5, UR8 ; /* 0x00000005040872a5 */
/* 0x000fc4000f8e0208 */
/*0c00*/ UIMAD.WIDE UR4, UR4, UR5, UR10 ; /* 0x00000005040472a5 */
/* 0x000fca000f8e020a */
/*0c10*/ MOV R2, UR8 ; /* 0x0000000800027c02 */
/* 0x000fe20008000f00 */
/*0c20*/ IMAD.U32 R5, RZ, RZ, UR5 ; /* 0x00000005ff057e24 */
/* 0x000fe2000f8e00ff */
/*0c30*/ MOV R4, UR4 ; /* 0x0000000400047c02 */
/* 0x000fe20008000f00 */
/*0c40*/ IMAD.U32 R3, RZ, RZ, UR9 ; /* 0x00000009ff037e24 */
/* 0x000fc8000f8e00ff */
/*0c50*/ LDG.E R5, [R4.64] ; /* 0x0000000c04057981 */
/* 0x000ea8000c1e1900 */
/*0c60*/ LDG.E R2, [R2.64] ; /* 0x0000000c02027981 */
/* 0x000ea2000c1e1900 */
/*0c70*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fc80007ffe0ff */
/*0c80*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0c90*/ UIADD3 UR8, UP1, UR8, 0x4, URZ ; /* 0x0000000408087890 */
/* 0x000fe2000ff3e03f */
/*0ca0*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x001fe20008000f00 */
/*0cb0*/ UIADD3 UR6, UP0, UR6, 0x4, URZ ; /* 0x0000000406067890 */
/* 0x000fe2000ff1e03f */
/*0cc0*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fe20008000f00 */
/*0cd0*/ UIADD3 UR4, UP2, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe4000ff5e03f */
/*0ce0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe400087fe43f */
/*0cf0*/ UIADD3.X UR9, URZ, UR9, URZ, UP1, !UPT ; /* 0x000000093f097290 */
/* 0x000fe40008ffe43f */
/*0d00*/ UIADD3.X UR5, URZ, UR5, URZ, UP2, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200097fe43f */
/*0d10*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*0d20*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e2000c10190c */
/*0d30*/ @P0 BRA 0xc10 ; /* 0xfffffed000000947 */
/* 0x000fea000383ffff */
/*0d40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d50*/ BRA 0xd50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10vector_addPfS_S_i
.globl _Z10vector_addPfS_S_i
.p2align 8
.type _Z10vector_addPfS_S_i,@function
_Z10vector_addPfS_S_i:
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v0, 0
.LBB0_2:
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[6:7]
global_load_b32 v2, v0, s[0:1]
s_add_i32 s2, s2, -1
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[4:5]
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s2, 0
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10vector_addPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10vector_addPfS_S_i, .Lfunc_end0-_Z10vector_addPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10vector_addPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z10vector_addPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d45d1_00000000-6_CUDA_Basics.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
.type _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i, @function
_Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10vector_addPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i, .-_Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
.globl _Z10vector_addPfS_S_i
.type _Z10vector_addPfS_S_i, @function
_Z10vector_addPfS_S_i:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z10vector_addPfS_S_i, .-_Z10vector_addPfS_S_i
.globl main
.type main, @function
main:
.LFB2027:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $40000000, %edi
call malloc@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $40000000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $40000000, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl $10000000, %ecx
movl $0, %edx
movq 8(%rsp), %rsi
movl $0, %edi
call _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10vector_addPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10vector_addPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "CUDA_Basics.hip"
.globl _Z25__device_stub__vector_addPfS_S_i # -- Begin function _Z25__device_stub__vector_addPfS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__vector_addPfS_S_i,@function
_Z25__device_stub__vector_addPfS_S_i: # @_Z25__device_stub__vector_addPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10vector_addPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__vector_addPfS_S_i, .Lfunc_end0-_Z25__device_stub__vector_addPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $128, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -16
movl $40000000, %edi # imm = 0x2625A00
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $40000000, %esi # imm = 0x2625A00
callq hipMalloc
movq 8(%rsp), %rdi
movl $40000000, %edx # imm = 0x2625A00
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $10000000, 20(%rsp) # imm = 0x989680
leaq 120(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 112(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10vector_addPfS_S_i, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10vector_addPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10vector_addPfS_S_i,@object # @_Z10vector_addPfS_S_i
.section .rodata,"a",@progbits
.globl _Z10vector_addPfS_S_i
.p2align 3, 0x0
_Z10vector_addPfS_S_i:
.quad _Z25__device_stub__vector_addPfS_S_i
.size _Z10vector_addPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10vector_addPfS_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__vector_addPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10vector_addPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #ifndef block_size_x
#define block_size_x 128
#endif
#ifndef threshold
#define threshold 3
#endif
/*
* Helper function that does the reduction step of the algorithm
*
* This function reduces the values in a thread block to a single value
*
*/
__device__ __forceinline__ void reduce_min_num(int *sh_min, int *sh_sum, int lmin, int lnum, int ti) {
sh_min[ti] = lmin;
sh_sum[ti] = lnum;
__syncthreads();
#pragma unroll
for (unsigned int s=block_size_x/2; s>0; s>>=1) {
if (ti < s) {
int self = sh_min[ti];
int other = sh_min[ti+s];
if (other >= threshold) {
if (self < threshold || other < self) {
sh_min[ti] = other;
}
}
sh_sum[ti] += sh_sum[ti + s];
}
__syncthreads();
}
}
/*
* This kernel recomputes the degree of each node in the graph and computes
* the minimum degree of all nodes with at least one edge.
*
* output arguments:
*
* minimum an array containing a per-thread block minimum degree
*
* num_nodes will contain the per-thread block sum of the number of nodes
* with at least 'threshold' edges
*
* degrees contains the degree of all nodes and is updated with the current degree
*
* input arguments:
*
* row_idx is the index of the node
* col_idx is the index of the node to which this node has an edge, this index
* can be -1 if the edge has been removed
*
* prefix_sum contains the start index of each row, because elements can be removed
* this subtracting two consecutive numbers no longer indicates the degree
*
* n is the number of nodes in the graph
*/
__global__ void minimum_degree(int *minimum, int *num_nodes, int *degrees, int *row_idx, int *col_idx, int *prefix_sum, int n) {
int ti = threadIdx.x;
int i = blockIdx.x * block_size_x + ti;
int degree = 0;
if (i<n) {
//obtain indices for reading col_idx
int start = 0;
if (i>0) {
start = prefix_sum[i-1];
}
int end = prefix_sum[i];
int max_degree = degrees[i];
//get the degree of this node
for (int k=start; k<end && degree < max_degree; k++) {
if (col_idx[k] != -1) {
degree++;
}
}
//update degrees array
degrees[i] = degree;
}
//start the reduce
//get the minimum value larger than 0
//and the total number of nodes with degree >= theshold (at least 'threshold' edges)
__shared__ int sh_min[block_size_x];
__shared__ int sh_sum[block_size_x];
int lnum = 0;
if (degree >= threshold) {
lnum = 1;
}
reduce_min_num(sh_min, sh_sum, degree, lnum, ti);
//write output
if (ti == 0) {
minimum[blockIdx.x] = sh_min[0];
num_nodes[blockIdx.x] = sh_sum[0];
}
}
/*
* Helper kernel to combine per-thread block results into single values
*
* call with 1 thread block, block_size_x should be sufficiently large
*/
__global__ void combine_blocked_min_num(int *minimum, int *num_nodes, int n) {
int ti = threadIdx.x;
__shared__ int sh_min[block_size_x];
__shared__ int sh_sum[block_size_x];
int lmin = 0;
int lnum = 0;
if (ti < n) {
lmin = minimum[ti];
lnum = num_nodes[ti];
}
reduce_min_num(sh_min, sh_sum, lmin, lnum, ti);
if (ti==0) {
minimum[0] = sh_min[0];
num_nodes[0] = sh_sum[0];
}
} | code for sm_80
Function : _Z23combine_blocked_min_numPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0xe0 ; /* 0x000000a000007945 */
/* 0x000fe20003800000 */
/*0040*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe400078e00ff */
/*0050*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x001fda0003f06270 */
/*0070*/ @P0 BRA 0xd0 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*0090*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0205 */
/*00a0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fe400078e0205 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000168000c1e1900 */
/*00c0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000164000c1e1900 */
/*00d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R0, 0x3f, PT ; /* 0x0000003f0000780c */
/* 0x000fe20003f04070 */
/*00f0*/ STS [R0.X4], R3 ; /* 0x0000000300007388 */
/* 0x0203e20000004800 */
/*0100*/ BSSY B0, 0x220 ; /* 0x0000011000007945 */
/* 0x000fe60003800000 */
/*0110*/ STS [R0.X4+0x200], R5 ; /* 0x0002000500007388 */
/* 0x0003e80000004800 */
/*0120*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0130*/ @P0 BRA 0x210 ; /* 0x000000d000000947 */
/* 0x000fea0003800000 */
/*0140*/ LDS R2, [R0.X4+0x200] ; /* 0x0002000000027984 */
/* 0x003fe20000004800 */
/*0150*/ BSSY B1, 0x210 ; /* 0x000000b000017945 */
/* 0x000fe60003800000 */
/*0160*/ LDS R5, [R0.X4+0x300] ; /* 0x0003000000057984 */
/* 0x000e280000004800 */
/*0170*/ LDS R3, [R0.X4+0x100] ; /* 0x0001000000037984 */
/* 0x000e620000004800 */
/*0180*/ IMAD.IADD R5, R2, 0x1, R5 ; /* 0x0000000102057824 */
/* 0x001fe200078e0205 */
/*0190*/ ISETP.GE.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x002fc80003f06270 */
/*01a0*/ STS [R0.X4+0x200], R5 ; /* 0x0002000500007388 */
/* 0x0001f20000004800 */
/*01b0*/ @!P0 BRA 0x200 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*01c0*/ LDS R2, [R0.X4] ; /* 0x0000000000027984 */
/* 0x001e240000004800 */
/*01d0*/ ISETP.GE.AND P0, PT, R3, R2, PT ; /* 0x000000020300720c */
/* 0x001fc80003f06270 */
/*01e0*/ ISETP.GT.AND P0, PT, R2, 0x2, P0 ; /* 0x000000020200780c */
/* 0x000fda0000704270 */
/*01f0*/ @!P0 STS [R0.X4], R3 ; /* 0x0000000300008388 */
/* 0x0001e40000004800 */
/*0200*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x001fea0003800000 */
/*0210*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*0220*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0230*/ ISETP.GT.U32.AND P0, PT, R0, 0x1f, PT ; /* 0x0000001f0000780c */
/* 0x000fca0003f04070 */
/*0240*/ BSSY B0, 0x340 ; /* 0x000000f000007945 */
/* 0x000ff00003800000 */
/*0250*/ @P0 BRA 0x330 ; /* 0x000000d000000947 */
/* 0x000fea0003800000 */
/*0260*/ LDS R2, [R0.X4+0x200] ; /* 0x0002000000027984 */
/* 0x001fe20000004800 */
/*0270*/ BSSY B1, 0x330 ; /* 0x000000b000017945 */
/* 0x000fe60003800000 */
/*0280*/ LDS R5, [R0.X4+0x280] ; /* 0x0002800000057984 */
/* 0x000e280000004800 */
/*0290*/ LDS R3, [R0.X4+0x80] ; /* 0x0000800000037984 */
/* 0x000e620000004800 */
/*02a0*/ IMAD.IADD R5, R2, 0x1, R5 ; /* 0x0000000102057824 */
/* 0x001fe200078e0205 */
/*02b0*/ ISETP.GE.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x002fc80003f06270 */
/*02c0*/ STS [R0.X4+0x200], R5 ; /* 0x0002000500007388 */
/* 0x0001f20000004800 */
/*02d0*/ @!P0 BRA 0x320 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*02e0*/ LDS R2, [R0.X4] ; /* 0x0000000000027984 */
/* 0x001e240000004800 */
/*02f0*/ ISETP.GE.AND P0, PT, R3, R2, PT ; /* 0x000000020300720c */
/* 0x001fc80003f06270 */
/*0300*/ ISETP.GT.AND P0, PT, R2, 0x2, P0 ; /* 0x000000020200780c */
/* 0x000fda0000704270 */
/*0310*/ @!P0 STS [R0.X4], R3 ; /* 0x0000000300008388 */
/* 0x0001e40000004800 */
/*0320*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x001fea0003800000 */
/*0330*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0340*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0350*/ ISETP.GT.U32.AND P0, PT, R0, 0xf, PT ; /* 0x0000000f0000780c */
/* 0x000fca0003f04070 */
/*0360*/ BSSY B0, 0x460 ; /* 0x000000f000007945 */
/* 0x000ff00003800000 */
/*0370*/ @P0 BRA 0x450 ; /* 0x000000d000000947 */
/* 0x000fea0003800000 */
/*0380*/ LDS R2, [R0.X4+0x200] ; /* 0x0002000000027984 */
/* 0x001fe20000004800 */
/*0390*/ BSSY B1, 0x450 ; /* 0x000000b000017945 */
/* 0x000fe60003800000 */
/*03a0*/ LDS R5, [R0.X4+0x240] ; /* 0x0002400000057984 */
/* 0x000e280000004800 */
/*03b0*/ LDS R3, [R0.X4+0x40] ; /* 0x0000400000037984 */
/* 0x000e620000004800 */
/*03c0*/ IMAD.IADD R5, R2, 0x1, R5 ; /* 0x0000000102057824 */
/* 0x001fe200078e0205 */
/*03d0*/ ISETP.GE.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x002fc80003f06270 */
/*03e0*/ STS [R0.X4+0x200], R5 ; /* 0x0002000500007388 */
/* 0x0001f20000004800 */
/*03f0*/ @!P0 BRA 0x440 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0400*/ LDS R2, [R0.X4] ; /* 0x0000000000027984 */
/* 0x001e240000004800 */
/*0410*/ ISETP.GE.AND P0, PT, R3, R2, PT ; /* 0x000000020300720c */
/* 0x001fc80003f06270 */
/*0420*/ ISETP.GT.AND P0, PT, R2, 0x2, P0 ; /* 0x000000020200780c */
/* 0x000fda0000704270 */
/*0430*/ @!P0 STS [R0.X4], R3 ; /* 0x0000000300008388 */
/* 0x0001e40000004800 */
/*0440*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x001fea0003800000 */
/*0450*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0460*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0470*/ ISETP.GT.U32.AND P0, PT, R0, 0x7, PT ; /* 0x000000070000780c */
/* 0x000fca0003f04070 */
/*0480*/ BSSY B0, 0x580 ; /* 0x000000f000007945 */
/* 0x000ff00003800000 */
/*0490*/ @P0 BRA 0x570 ; /* 0x000000d000000947 */
/* 0x000fea0003800000 */
/*04a0*/ LDS R2, [R0.X4+0x200] ; /* 0x0002000000027984 */
/* 0x001fe20000004800 */
/*04b0*/ BSSY B1, 0x570 ; /* 0x000000b000017945 */
/* 0x000fe60003800000 */
/*04c0*/ LDS R5, [R0.X4+0x220] ; /* 0x0002200000057984 */
/* 0x000e280000004800 */
/*04d0*/ LDS R3, [R0.X4+0x20] ; /* 0x0000200000037984 */
/* 0x000e620000004800 */
/*04e0*/ IMAD.IADD R5, R2, 0x1, R5 ; /* 0x0000000102057824 */
/* 0x001fe200078e0205 */
/*04f0*/ ISETP.GE.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x002fc80003f06270 */
/*0500*/ STS [R0.X4+0x200], R5 ; /* 0x0002000500007388 */
/* 0x0001f20000004800 */
/*0510*/ @!P0 BRA 0x560 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0520*/ LDS R2, [R0.X4] ; /* 0x0000000000027984 */
/* 0x001e240000004800 */
/*0530*/ ISETP.GE.AND P0, PT, R3, R2, PT ; /* 0x000000020300720c */
/* 0x001fc80003f06270 */
/*0540*/ ISETP.GT.AND P0, PT, R2, 0x2, P0 ; /* 0x000000020200780c */
/* 0x000fda0000704270 */
/*0550*/ @!P0 STS [R0.X4], R3 ; /* 0x0000000300008388 */
/* 0x0001e40000004800 */
/*0560*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x001fea0003800000 */
/*0570*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0580*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0590*/ ISETP.GT.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fca0003f04070 */
/*05a0*/ BSSY B0, 0x6a0 ; /* 0x000000f000007945 */
/* 0x000ff00003800000 */
/*05b0*/ @P0 BRA 0x690 ; /* 0x000000d000000947 */
/* 0x000fea0003800000 */
/*05c0*/ LDS R2, [R0.X4+0x200] ; /* 0x0002000000027984 */
/* 0x001fe20000004800 */
/*05d0*/ BSSY B1, 0x690 ; /* 0x000000b000017945 */
/* 0x000fe60003800000 */
/*05e0*/ LDS R5, [R0.X4+0x210] ; /* 0x0002100000057984 */
/* 0x000e280000004800 */
/*05f0*/ LDS R3, [R0.X4+0x10] ; /* 0x0000100000037984 */
/* 0x000e620000004800 */
/*0600*/ IMAD.IADD R5, R2, 0x1, R5 ; /* 0x0000000102057824 */
/* 0x001fe200078e0205 */
/*0610*/ ISETP.GE.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x002fc80003f06270 */
/*0620*/ STS [R0.X4+0x200], R5 ; /* 0x0002000500007388 */
/* 0x0001f20000004800 */
/*0630*/ @!P0 BRA 0x680 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0640*/ LDS R2, [R0.X4] ; /* 0x0000000000027984 */
/* 0x001e240000004800 */
/*0650*/ ISETP.GE.AND P0, PT, R3, R2, PT ; /* 0x000000020300720c */
/* 0x001fc80003f06270 */
/*0660*/ ISETP.GT.AND P0, PT, R2, 0x2, P0 ; /* 0x000000020200780c */
/* 0x000fda0000704270 */
/*0670*/ @!P0 STS [R0.X4], R3 ; /* 0x0000000300008388 */
/* 0x0001e40000004800 */
/*0680*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x001fea0003800000 */
/*0690*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*06b0*/ ISETP.GT.U32.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fca0003f04070 */
/*06c0*/ BSSY B0, 0x7c0 ; /* 0x000000f000007945 */
/* 0x000ff00003800000 */
/*06d0*/ @P0 BRA 0x7b0 ; /* 0x000000d000000947 */
/* 0x000fea0003800000 */
/*06e0*/ LDS R2, [R0.X4+0x200] ; /* 0x0002000000027984 */
/* 0x001fe20000004800 */
/*06f0*/ BSSY B1, 0x7b0 ; /* 0x000000b000017945 */
/* 0x000fe60003800000 */
/*0700*/ LDS R5, [R0.X4+0x208] ; /* 0x0002080000057984 */
/* 0x000e280000004800 */
/*0710*/ LDS R3, [R0.X4+0x8] ; /* 0x0000080000037984 */
/* 0x000e620000004800 */
/*0720*/ IMAD.IADD R5, R2, 0x1, R5 ; /* 0x0000000102057824 */
/* 0x001fe200078e0205 */
/*0730*/ ISETP.GE.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x002fc80003f06270 */
/*0740*/ STS [R0.X4+0x200], R5 ; /* 0x0002000500007388 */
/* 0x0001f20000004800 */
/*0750*/ @!P0 BRA 0x7a0 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0760*/ LDS R2, [R0.X4] ; /* 0x0000000000027984 */
/* 0x001e240000004800 */
/*0770*/ ISETP.GE.AND P0, PT, R3, R2, PT ; /* 0x000000020300720c */
/* 0x001fc80003f06270 */
/*0780*/ ISETP.GT.AND P0, PT, R2, 0x2, P0 ; /* 0x000000020200780c */
/* 0x000fda0000704270 */
/*0790*/ @!P0 STS [R0.X4], R3 ; /* 0x0000000300008388 */
/* 0x0001e40000004800 */
/*07a0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x001fea0003800000 */
/*07b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*07c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*07d0*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fca0003f25270 */
/*07e0*/ BSSY B0, 0x8c0 ; /* 0x000000d000007945 */
/* 0x000ff00003800000 */
/*07f0*/ @P1 BRA 0x8b0 ; /* 0x000000b000001947 */
/* 0x000fea0003800000 */
/*0800*/ LDS R3, [0x4] ; /* 0x00000400ff037984 */
/* 0x000e680000000800 */
/*0810*/ LDS R5, [R0.X4+0x200] ; /* 0x0002000000057984 */
/* 0x0004e20000004800 */
/*0820*/ ISETP.GE.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x002fda0003f06270 */
/*0830*/ @!P0 BRA 0x880 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0840*/ LDS R2, [R0.X4] ; /* 0x0000000000027984 */
/* 0x00de240000004800 */
/*0850*/ ISETP.GE.AND P0, PT, R3, R2, PT ; /* 0x000000020300720c */
/* 0x001fc80003f06270 */
/*0860*/ ISETP.GT.AND P0, PT, R2, 0x2, P0 ; /* 0x000000020200780c */
/* 0x000fda0000704270 */
/*0870*/ @!P0 STS [R0.X4], R3 ; /* 0x0000000300008388 */
/* 0x0001e40000004800 */
/*0880*/ LDS R2, [0x204] ; /* 0x00020400ff027984 */
/* 0x00de240000000800 */
/*0890*/ IMAD.IADD R5, R2, 0x1, R5 ; /* 0x0000000102057824 */
/* 0x001fca00078e0205 */
/*08a0*/ STS [R0.X4+0x200], R5 ; /* 0x0002000500007388 */
/* 0x0001e40000004800 */
/*08b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*08c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*08d0*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*08e0*/ LDS R7, [RZ] ; /* 0x00000000ff077984 */
/* 0x000e620000000800 */
/*08f0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x001fe400078e00ff */
/*0900*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*0910*/ LDS R9, [0x200] ; /* 0x00020000ff097984 */
/* 0x000e220000000800 */
/*0920*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fc400078e00ff */
/*0930*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe200078e00ff */
/*0940*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x002fe8000c101904 */
/*0950*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x001fe2000c101904 */
/*0960*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0970*/ BRA 0x970; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z14minimum_degreePiS_S_S_S_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x250 ; /* 0x0000021000007945 */
/* 0x000fe20003800000 */
/*0040*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R2, R0, 0x80, R3 ; /* 0x0000008000027824 */
/* 0x001fca00078e0203 */
/*0070*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x190], PT ; /* 0x0000640002007a0c */
/* 0x000fda0003f06270 */
/*0080*/ @P0 BRA 0x240 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0090*/ ISETP.GE.AND P0, PT, R2.reuse, 0x1, PT ; /* 0x000000010200780c */
/* 0x040fe20003f06270 */
/*00a0*/ IMAD.MOV.U32 R12, RZ, RZ, 0x4 ; /* 0x00000004ff0c7424 */
/* 0x000fe200078e00ff */
/*00b0*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*00c0*/ SHF.R.S32.HI R7, RZ, 0x1f, R2 ; /* 0x0000001fff077819 */
/* 0x000fe40000011402 */
/*00d0*/ LEA R6, P1, R2.reuse, c[0x0][0x170], 0x2 ; /* 0x00005c0002067a11 */
/* 0x040fe200078210ff */
/*00e0*/ IMAD.WIDE R4, R2, R12, c[0x0][0x188] ; /* 0x0000620002047625 */
/* 0x000fc600078e020c */
/*00f0*/ LEA.HI.X R7, R2, c[0x0][0x174], R7, 0x2, P1 ; /* 0x00005d0002077a11 */
/* 0x000fe400008f1407 */
/*0100*/ LDG.E R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea8000c1e1900 */
/*0110*/ @P0 LDG.E R9, [R4.64+-0x4] ; /* 0xfffffc0404090981 */
/* 0x000ea8000c1e1900 */
/*0120*/ LDG.E R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x000ee2000c1e1900 */
/*0130*/ BSSY B1, 0x230 ; /* 0x000000f000017945 */
/* 0x000fe20003800000 */
/*0140*/ ISETP.GE.AND P0, PT, R9, R2, PT ; /* 0x000000020900720c */
/* 0x004fc80003f06270 */
/*0150*/ ISETP.LT.OR P0, PT, R10, 0x1, P0 ; /* 0x000000010a00780c */
/* 0x008fda0000701670 */
/*0160*/ @P0 BRA 0x220 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe400078e00ff */
/*0180*/ IMAD.WIDE R4, R9, R12, c[0x0][0x180] ; /* 0x0000600009047625 */
/* 0x000fcc00078e020c */
/*0190*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*01a0*/ IADD3 R11, R8, 0x1, RZ ; /* 0x00000001080b7810 */
/* 0x000fe40007ffe0ff */
/*01b0*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ ISETP.NE.AND P0, PT, R4, -0x1, PT ; /* 0xffffffff0400780c */
/* 0x004fda0003f05270 */
/*01d0*/ @!P0 IMAD.MOV R11, RZ, RZ, R8 ; /* 0x000000ffff0b8224 */
/* 0x000fe200078e0208 */
/*01e0*/ ISETP.GE.AND P0, PT, R9, R2, PT ; /* 0x000000020900720c */
/* 0x000fc60003f06270 */
/*01f0*/ IMAD.MOV.U32 R8, RZ, RZ, R11 ; /* 0x000000ffff087224 */
/* 0x000fe200078e000b */
/*0200*/ ISETP.LT.AND P1, PT, R11, R10, PT ; /* 0x0000000a0b00720c */
/* 0x000fda0003f21270 */
/*0210*/ @!P0 BRA P1, 0x180 ; /* 0xffffff6000008947 */
/* 0x000fea000083ffff */
/*0220*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0230*/ STG.E [R6.64], R8 ; /* 0x0000000806007986 */
/* 0x0001e4000c101904 */
/*0240*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0250*/ ISETP.GT.AND P0, PT, R8, 0x2, PT ; /* 0x000000020800780c */
/* 0x000fe20003f04270 */
/*0260*/ STS [R3.X4], R8 ; /* 0x0000000803007388 */
/* 0x0003e20000004800 */
/*0270*/ BSSY B0, 0x3b0 ; /* 0x0000013000007945 */
/* 0x000fe40003800000 */
/*0280*/ SEL R2, RZ, 0x1, !P0 ; /* 0x00000001ff027807 */
/* 0x000fe40004000000 */
/*0290*/ ISETP.GT.U32.AND P0, PT, R3, 0x3f, PT ; /* 0x0000003f0300780c */
/* 0x000fc60003f04070 */
/*02a0*/ STS [R3.X4+0x200], R2 ; /* 0x0002000203007388 */
/* 0x0003e80000004800 */
/*02b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02c0*/ @P0 BRA 0x3a0 ; /* 0x000000d000000947 */
/* 0x000fea0003800000 */
/*02d0*/ LDS R4, [R3.X4+0x200] ; /* 0x0002000003047984 */
/* 0x002fe20000004800 */
/*02e0*/ BSSY B1, 0x3a0 ; /* 0x000000b000017945 */
/* 0x000fe60003800000 */
/*02f0*/ LDS R5, [R3.X4+0x300] ; /* 0x0003000003057984 */
/* 0x000e680000004800 */
/*0300*/ LDS R2, [R3.X4+0x100] ; /* 0x0001000003027984 */
/* 0x000ea20000004800 */
/*0310*/ IMAD.IADD R4, R4, 0x1, R5 ; /* 0x0000000104047824 */
/* 0x002fe200078e0205 */
/*0320*/ ISETP.GE.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x004fc80003f06270 */
/*0330*/ STS [R3.X4+0x200], R4 ; /* 0x0002000403007388 */
/* 0x0003f20000004800 */
/*0340*/ @!P0 BRA 0x390 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0350*/ LDS R5, [R3.X4] ; /* 0x0000000003057984 */
/* 0x002e640000004800 */
/*0360*/ ISETP.GE.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x002fc80003f06270 */
/*0370*/ ISETP.GT.AND P0, PT, R5, 0x2, P0 ; /* 0x000000020500780c */
/* 0x000fda0000704270 */
/*0380*/ @!P0 STS [R3.X4], R2 ; /* 0x0000000203008388 */
/* 0x0003e40000004800 */
/*0390*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x002fea0003800000 */
/*03a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*03b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*03c0*/ ISETP.GT.U32.AND P0, PT, R3, 0x1f, PT ; /* 0x0000001f0300780c */
/* 0x000fca0003f04070 */
/*03d0*/ BSSY B0, 0x4d0 ; /* 0x000000f000007945 */
/* 0x000ff00003800000 */
/*03e0*/ @P0 BRA 0x4c0 ; /* 0x000000d000000947 */
/* 0x000fea0003800000 */
/*03f0*/ LDS R4, [R3.X4+0x200] ; /* 0x0002000003047984 */
/* 0x000fe20000004800 */
/*0400*/ BSSY B1, 0x4c0 ; /* 0x000000b000017945 */
/* 0x000fe60003800000 */
/*0410*/ LDS R5, [R3.X4+0x280] ; /* 0x0002800003057984 */
/* 0x000e680000004800 */
/*0420*/ LDS R2, [R3.X4+0x80] ; /* 0x0000800003027984 */
/* 0x000ea20000004800 */
/*0430*/ IMAD.IADD R4, R4, 0x1, R5 ; /* 0x0000000104047824 */
/* 0x002fe200078e0205 */
/*0440*/ ISETP.GE.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x004fc80003f06270 */
/*0450*/ STS [R3.X4+0x200], R4 ; /* 0x0002000403007388 */
/* 0x0003f20000004800 */
/*0460*/ @!P0 BRA 0x4b0 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0470*/ LDS R5, [R3.X4] ; /* 0x0000000003057984 */
/* 0x002e640000004800 */
/*0480*/ ISETP.GE.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x002fc80003f06270 */
/*0490*/ ISETP.GT.AND P0, PT, R5, 0x2, P0 ; /* 0x000000020500780c */
/* 0x000fda0000704270 */
/*04a0*/ @!P0 STS [R3.X4], R2 ; /* 0x0000000203008388 */
/* 0x0003e40000004800 */
/*04b0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x002fea0003800000 */
/*04c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*04e0*/ ISETP.GT.U32.AND P0, PT, R3, 0xf, PT ; /* 0x0000000f0300780c */
/* 0x000fca0003f04070 */
/*04f0*/ BSSY B0, 0x5f0 ; /* 0x000000f000007945 */
/* 0x000ff00003800000 */
/*0500*/ @P0 BRA 0x5e0 ; /* 0x000000d000000947 */
/* 0x000fea0003800000 */
/*0510*/ LDS R4, [R3.X4+0x200] ; /* 0x0002000003047984 */
/* 0x000fe20000004800 */
/*0520*/ BSSY B1, 0x5e0 ; /* 0x000000b000017945 */
/* 0x000fe60003800000 */
/*0530*/ LDS R5, [R3.X4+0x240] ; /* 0x0002400003057984 */
/* 0x000e680000004800 */
/*0540*/ LDS R2, [R3.X4+0x40] ; /* 0x0000400003027984 */
/* 0x000ea20000004800 */
/*0550*/ IMAD.IADD R4, R4, 0x1, R5 ; /* 0x0000000104047824 */
/* 0x002fe200078e0205 */
/*0560*/ ISETP.GE.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x004fc80003f06270 */
/*0570*/ STS [R3.X4+0x200], R4 ; /* 0x0002000403007388 */
/* 0x0003f20000004800 */
/*0580*/ @!P0 BRA 0x5d0 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0590*/ LDS R5, [R3.X4] ; /* 0x0000000003057984 */
/* 0x002e640000004800 */
/*05a0*/ ISETP.GE.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x002fc80003f06270 */
/*05b0*/ ISETP.GT.AND P0, PT, R5, 0x2, P0 ; /* 0x000000020500780c */
/* 0x000fda0000704270 */
/*05c0*/ @!P0 STS [R3.X4], R2 ; /* 0x0000000203008388 */
/* 0x0003e40000004800 */
/*05d0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x002fea0003800000 */
/*05e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0600*/ ISETP.GT.U32.AND P0, PT, R3, 0x7, PT ; /* 0x000000070300780c */
/* 0x000fca0003f04070 */
/*0610*/ BSSY B0, 0x710 ; /* 0x000000f000007945 */
/* 0x000ff00003800000 */
/*0620*/ @P0 BRA 0x700 ; /* 0x000000d000000947 */
/* 0x000fea0003800000 */
/*0630*/ LDS R4, [R3.X4+0x200] ; /* 0x0002000003047984 */
/* 0x000fe20000004800 */
/*0640*/ BSSY B1, 0x700 ; /* 0x000000b000017945 */
/* 0x000fe60003800000 */
/*0650*/ LDS R5, [R3.X4+0x220] ; /* 0x0002200003057984 */
/* 0x000e680000004800 */
/*0660*/ LDS R2, [R3.X4+0x20] ; /* 0x0000200003027984 */
/* 0x000ea20000004800 */
/*0670*/ IMAD.IADD R4, R4, 0x1, R5 ; /* 0x0000000104047824 */
/* 0x002fe200078e0205 */
/*0680*/ ISETP.GE.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x004fc80003f06270 */
/*0690*/ STS [R3.X4+0x200], R4 ; /* 0x0002000403007388 */
/* 0x0003f20000004800 */
/*06a0*/ @!P0 BRA 0x6f0 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*06b0*/ LDS R5, [R3.X4] ; /* 0x0000000003057984 */
/* 0x002e640000004800 */
/*06c0*/ ISETP.GE.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x002fc80003f06270 */
/*06d0*/ ISETP.GT.AND P0, PT, R5, 0x2, P0 ; /* 0x000000020500780c */
/* 0x000fda0000704270 */
/*06e0*/ @!P0 STS [R3.X4], R2 ; /* 0x0000000203008388 */
/* 0x0003e40000004800 */
/*06f0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x002fea0003800000 */
/*0700*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0710*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0720*/ ISETP.GT.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fca0003f04070 */
/*0730*/ BSSY B0, 0x830 ; /* 0x000000f000007945 */
/* 0x000ff00003800000 */
/*0740*/ @P0 BRA 0x820 ; /* 0x000000d000000947 */
/* 0x000fea0003800000 */
/*0750*/ LDS R4, [R3.X4+0x200] ; /* 0x0002000003047984 */
/* 0x000fe20000004800 */
/*0760*/ BSSY B1, 0x820 ; /* 0x000000b000017945 */
/* 0x000fe60003800000 */
/*0770*/ LDS R5, [R3.X4+0x210] ; /* 0x0002100003057984 */
/* 0x000e680000004800 */
/*0780*/ LDS R2, [R3.X4+0x10] ; /* 0x0000100003027984 */
/* 0x000ea20000004800 */
/*0790*/ IMAD.IADD R4, R4, 0x1, R5 ; /* 0x0000000104047824 */
/* 0x002fe200078e0205 */
/*07a0*/ ISETP.GE.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x004fc80003f06270 */
/*07b0*/ STS [R3.X4+0x200], R4 ; /* 0x0002000403007388 */
/* 0x0003f20000004800 */
/*07c0*/ @!P0 BRA 0x810 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*07d0*/ LDS R5, [R3.X4] ; /* 0x0000000003057984 */
/* 0x002e640000004800 */
/*07e0*/ ISETP.GE.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x002fc80003f06270 */
/*07f0*/ ISETP.GT.AND P0, PT, R5, 0x2, P0 ; /* 0x000000020500780c */
/* 0x000fda0000704270 */
/*0800*/ @!P0 STS [R3.X4], R2 ; /* 0x0000000203008388 */
/* 0x0003e40000004800 */
/*0810*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x002fea0003800000 */
/*0820*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0830*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0840*/ ISETP.GT.U32.AND P0, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fca0003f04070 */
/*0850*/ BSSY B0, 0x950 ; /* 0x000000f000007945 */
/* 0x000ff00003800000 */
/*0860*/ @P0 BRA 0x940 ; /* 0x000000d000000947 */
/* 0x000fea0003800000 */
/*0870*/ LDS R4, [R3.X4+0x200] ; /* 0x0002000003047984 */
/* 0x000fe20000004800 */
/*0880*/ BSSY B1, 0x940 ; /* 0x000000b000017945 */
/* 0x000fe60003800000 */
/*0890*/ LDS R5, [R3.X4+0x208] ; /* 0x0002080003057984 */
/* 0x000e680000004800 */
/*08a0*/ LDS R2, [R3.X4+0x8] ; /* 0x0000080003027984 */
/* 0x000ea20000004800 */
/*08b0*/ IMAD.IADD R4, R4, 0x1, R5 ; /* 0x0000000104047824 */
/* 0x002fe200078e0205 */
/*08c0*/ ISETP.GE.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x004fc80003f06270 */
/*08d0*/ STS [R3.X4+0x200], R4 ; /* 0x0002000403007388 */
/* 0x0003f20000004800 */
/*08e0*/ @!P0 BRA 0x930 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*08f0*/ LDS R5, [R3.X4] ; /* 0x0000000003057984 */
/* 0x002e640000004800 */
/*0900*/ ISETP.GE.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x002fc80003f06270 */
/*0910*/ ISETP.GT.AND P0, PT, R5, 0x2, P0 ; /* 0x000000020500780c */
/* 0x000fda0000704270 */
/*0920*/ @!P0 STS [R3.X4], R2 ; /* 0x0000000203008388 */
/* 0x0003e40000004800 */
/*0930*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x002fea0003800000 */
/*0940*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0950*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0960*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fca0003f25270 */
/*0970*/ BSSY B0, 0xa50 ; /* 0x000000d000007945 */
/* 0x000ff00003800000 */
/*0980*/ @P1 BRA 0xa40 ; /* 0x000000b000001947 */
/* 0x000fea0003800000 */
/*0990*/ LDS R2, [0x4] ; /* 0x00000400ff027984 */
/* 0x000e680000000800 */
/*09a0*/ LDS R7, [R3.X4+0x200] ; /* 0x0002000003077984 */
/* 0x0010a20000004800 */
/*09b0*/ ISETP.GE.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x002fda0003f06270 */
/*09c0*/ @!P0 BRA 0xa10 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*09d0*/ LDS R5, [R3.X4] ; /* 0x0000000003057984 */
/* 0x005e240000004800 */
/*09e0*/ ISETP.GE.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x001fc80003f06270 */
/*09f0*/ ISETP.GT.AND P0, PT, R5, 0x2, P0 ; /* 0x000000020500780c */
/* 0x000fda0000704270 */
/*0a00*/ @!P0 STS [R3.X4], R2 ; /* 0x0000000203008388 */
/* 0x0001e40000004800 */
/*0a10*/ LDS R2, [0x204] ; /* 0x00020400ff027984 */
/* 0x005e240000000800 */
/*0a20*/ IMAD.IADD R2, R2, 0x1, R7 ; /* 0x0000000102027824 */
/* 0x001fca00078e0207 */
/*0a30*/ STS [R3.X4+0x200], R2 ; /* 0x0002000203007388 */
/* 0x0001e40000004800 */
/*0a40*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0a50*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0a60*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0a70*/ LDS R7, [RZ] ; /* 0x00000000ff077984 */
/* 0x001e220000000800 */
/*0a80*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc600078e00ff */
/*0a90*/ LDS R9, [0x200] ; /* 0x00020000ff097984 */
/* 0x000e620000000800 */
/*0aa0*/ IMAD.WIDE.U32 R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0005 */
/*0ab0*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fe200078e0005 */
/*0ac0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x001fe8000c101904 */
/*0ad0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x002fe2000c101904 */
/*0ae0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0af0*/ BRA 0xaf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #ifndef block_size_x
#define block_size_x 128
#endif
#ifndef threshold
#define threshold 3
#endif
/*
* Helper function that does the reduction step of the algorithm
*
* This function reduces the values in a thread block to a single value
*
*/
__device__ __forceinline__ void reduce_min_num(int *sh_min, int *sh_sum, int lmin, int lnum, int ti) {
sh_min[ti] = lmin;
sh_sum[ti] = lnum;
__syncthreads();
#pragma unroll
for (unsigned int s=block_size_x/2; s>0; s>>=1) {
if (ti < s) {
int self = sh_min[ti];
int other = sh_min[ti+s];
if (other >= threshold) {
if (self < threshold || other < self) {
sh_min[ti] = other;
}
}
sh_sum[ti] += sh_sum[ti + s];
}
__syncthreads();
}
}
/*
* This kernel recomputes the degree of each node in the graph and computes
* the minimum degree of all nodes with at least one edge.
*
* output arguments:
*
* minimum an array containing a per-thread block minimum degree
*
* num_nodes will contain the per-thread block sum of the number of nodes
* with at least 'threshold' edges
*
* degrees contains the degree of all nodes and is updated with the current degree
*
* input arguments:
*
* row_idx is the index of the node
* col_idx is the index of the node to which this node has an edge, this index
* can be -1 if the edge has been removed
*
* prefix_sum contains the start index of each row, because elements can be removed
* this subtracting two consecutive numbers no longer indicates the degree
*
* n is the number of nodes in the graph
*/
__global__ void minimum_degree(int *minimum, int *num_nodes, int *degrees, int *row_idx, int *col_idx, int *prefix_sum, int n) {
int ti = threadIdx.x;
int i = blockIdx.x * block_size_x + ti;
int degree = 0;
if (i<n) {
//obtain indices for reading col_idx
int start = 0;
if (i>0) {
start = prefix_sum[i-1];
}
int end = prefix_sum[i];
int max_degree = degrees[i];
//get the degree of this node
for (int k=start; k<end && degree < max_degree; k++) {
if (col_idx[k] != -1) {
degree++;
}
}
//update degrees array
degrees[i] = degree;
}
//start the reduce
//get the minimum value larger than 0
//and the total number of nodes with degree >= theshold (at least 'threshold' edges)
__shared__ int sh_min[block_size_x];
__shared__ int sh_sum[block_size_x];
int lnum = 0;
if (degree >= threshold) {
lnum = 1;
}
reduce_min_num(sh_min, sh_sum, degree, lnum, ti);
//write output
if (ti == 0) {
minimum[blockIdx.x] = sh_min[0];
num_nodes[blockIdx.x] = sh_sum[0];
}
}
/*
* Helper kernel to combine per-thread block results into single values
*
* call with 1 thread block, block_size_x should be sufficiently large
*/
__global__ void combine_blocked_min_num(int *minimum, int *num_nodes, int n) {
int ti = threadIdx.x;
__shared__ int sh_min[block_size_x];
__shared__ int sh_sum[block_size_x];
int lmin = 0;
int lnum = 0;
if (ti < n) {
lmin = minimum[ti];
lnum = num_nodes[ti];
}
reduce_min_num(sh_min, sh_sum, lmin, lnum, ti);
if (ti==0) {
minimum[0] = sh_min[0];
num_nodes[0] = sh_sum[0];
}
} | .file "tmpxft_000a059c_00000000-6_minimum_degree.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z14minimum_degreePiS_S_S_S_S_iPiS_S_S_S_S_i
.type _Z45__device_stub__Z14minimum_degreePiS_S_S_S_S_iPiS_S_S_S_S_i, @function
_Z45__device_stub__Z14minimum_degreePiS_S_S_S_S_iPiS_S_S_S_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z14minimum_degreePiS_S_S_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z45__device_stub__Z14minimum_degreePiS_S_S_S_S_iPiS_S_S_S_S_i, .-_Z45__device_stub__Z14minimum_degreePiS_S_S_S_S_iPiS_S_S_S_S_i
.globl _Z14minimum_degreePiS_S_S_S_S_i
.type _Z14minimum_degreePiS_S_S_S_S_i, @function
_Z14minimum_degreePiS_S_S_S_S_i:
.LFB2053:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z45__device_stub__Z14minimum_degreePiS_S_S_S_S_iPiS_S_S_S_S_i
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z14minimum_degreePiS_S_S_S_S_i, .-_Z14minimum_degreePiS_S_S_S_S_i
.globl _Z46__device_stub__Z23combine_blocked_min_numPiS_iPiS_i
.type _Z46__device_stub__Z23combine_blocked_min_numPiS_iPiS_i, @function
_Z46__device_stub__Z23combine_blocked_min_numPiS_iPiS_i:
.LFB2054:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z23combine_blocked_min_numPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z46__device_stub__Z23combine_blocked_min_numPiS_iPiS_i, .-_Z46__device_stub__Z23combine_blocked_min_numPiS_iPiS_i
.globl _Z23combine_blocked_min_numPiS_i
.type _Z23combine_blocked_min_numPiS_i, @function
_Z23combine_blocked_min_numPiS_i:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z23combine_blocked_min_numPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _Z23combine_blocked_min_numPiS_i, .-_Z23combine_blocked_min_numPiS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z23combine_blocked_min_numPiS_i"
.align 8
.LC1:
.string "_Z14minimum_degreePiS_S_S_S_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z23combine_blocked_min_numPiS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z14minimum_degreePiS_S_S_S_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #ifndef block_size_x
#define block_size_x 128
#endif
#ifndef threshold
#define threshold 3
#endif
/*
* Helper function that does the reduction step of the algorithm
*
* This function reduces the values in a thread block to a single value
*
*/
__device__ __forceinline__ void reduce_min_num(int *sh_min, int *sh_sum, int lmin, int lnum, int ti) {
sh_min[ti] = lmin;
sh_sum[ti] = lnum;
__syncthreads();
#pragma unroll
for (unsigned int s=block_size_x/2; s>0; s>>=1) {
if (ti < s) {
int self = sh_min[ti];
int other = sh_min[ti+s];
if (other >= threshold) {
if (self < threshold || other < self) {
sh_min[ti] = other;
}
}
sh_sum[ti] += sh_sum[ti + s];
}
__syncthreads();
}
}
/*
* This kernel recomputes the degree of each node in the graph and computes
* the minimum degree of all nodes with at least one edge.
*
* output arguments:
*
* minimum an array containing a per-thread block minimum degree
*
* num_nodes will contain the per-thread block sum of the number of nodes
* with at least 'threshold' edges
*
* degrees contains the degree of all nodes and is updated with the current degree
*
* input arguments:
*
* row_idx is the index of the node
* col_idx is the index of the node to which this node has an edge, this index
* can be -1 if the edge has been removed
*
* prefix_sum contains the start index of each row, because elements can be removed
* this subtracting two consecutive numbers no longer indicates the degree
*
* n is the number of nodes in the graph
*/
__global__ void minimum_degree(int *minimum, int *num_nodes, int *degrees, int *row_idx, int *col_idx, int *prefix_sum, int n) {
int ti = threadIdx.x;
int i = blockIdx.x * block_size_x + ti;
int degree = 0;
if (i<n) {
//obtain indices for reading col_idx
int start = 0;
if (i>0) {
start = prefix_sum[i-1];
}
int end = prefix_sum[i];
int max_degree = degrees[i];
//get the degree of this node
for (int k=start; k<end && degree < max_degree; k++) {
if (col_idx[k] != -1) {
degree++;
}
}
//update degrees array
degrees[i] = degree;
}
//start the reduce
//get the minimum value larger than 0
//and the total number of nodes with degree >= theshold (at least 'threshold' edges)
__shared__ int sh_min[block_size_x];
__shared__ int sh_sum[block_size_x];
int lnum = 0;
if (degree >= threshold) {
lnum = 1;
}
reduce_min_num(sh_min, sh_sum, degree, lnum, ti);
//write output
if (ti == 0) {
minimum[blockIdx.x] = sh_min[0];
num_nodes[blockIdx.x] = sh_sum[0];
}
}
/*
* Helper kernel to combine per-thread block results into single values
*
* call with 1 thread block, block_size_x should be sufficiently large
*/
__global__ void combine_blocked_min_num(int *minimum, int *num_nodes, int n) {
int ti = threadIdx.x;
__shared__ int sh_min[block_size_x];
__shared__ int sh_sum[block_size_x];
int lmin = 0;
int lnum = 0;
if (ti < n) {
lmin = minimum[ti];
lnum = num_nodes[ti];
}
reduce_min_num(sh_min, sh_sum, lmin, lnum, ti);
if (ti==0) {
minimum[0] = sh_min[0];
num_nodes[0] = sh_sum[0];
}
} | #include <hip/hip_runtime.h>
#ifndef block_size_x
#define block_size_x 128
#endif
#ifndef threshold
#define threshold 3
#endif
/*
* Helper function that does the reduction step of the algorithm
*
* This function reduces the values in a thread block to a single value
*
*/
__device__ __forceinline__ void reduce_min_num(int *sh_min, int *sh_sum, int lmin, int lnum, int ti) {
sh_min[ti] = lmin;
sh_sum[ti] = lnum;
__syncthreads();
#pragma unroll
for (unsigned int s=block_size_x/2; s>0; s>>=1) {
if (ti < s) {
int self = sh_min[ti];
int other = sh_min[ti+s];
if (other >= threshold) {
if (self < threshold || other < self) {
sh_min[ti] = other;
}
}
sh_sum[ti] += sh_sum[ti + s];
}
__syncthreads();
}
}
/*
* This kernel recomputes the degree of each node in the graph and computes
* the minimum degree of all nodes with at least one edge.
*
* output arguments:
*
* minimum an array containing a per-thread block minimum degree
*
* num_nodes will contain the per-thread block sum of the number of nodes
* with at least 'threshold' edges
*
* degrees contains the degree of all nodes and is updated with the current degree
*
* input arguments:
*
* row_idx is the index of the node
* col_idx is the index of the node to which this node has an edge, this index
* can be -1 if the edge has been removed
*
* prefix_sum contains the start index of each row, because elements can be removed
* this subtracting two consecutive numbers no longer indicates the degree
*
* n is the number of nodes in the graph
*/
__global__ void minimum_degree(int *minimum, int *num_nodes, int *degrees, int *row_idx, int *col_idx, int *prefix_sum, int n) {
int ti = threadIdx.x;
int i = blockIdx.x * block_size_x + ti;
int degree = 0;
if (i<n) {
//obtain indices for reading col_idx
int start = 0;
if (i>0) {
start = prefix_sum[i-1];
}
int end = prefix_sum[i];
int max_degree = degrees[i];
//get the degree of this node
for (int k=start; k<end && degree < max_degree; k++) {
if (col_idx[k] != -1) {
degree++;
}
}
//update degrees array
degrees[i] = degree;
}
//start the reduce
//get the minimum value larger than 0
//and the total number of nodes with degree >= theshold (at least 'threshold' edges)
__shared__ int sh_min[block_size_x];
__shared__ int sh_sum[block_size_x];
int lnum = 0;
if (degree >= threshold) {
lnum = 1;
}
reduce_min_num(sh_min, sh_sum, degree, lnum, ti);
//write output
if (ti == 0) {
minimum[blockIdx.x] = sh_min[0];
num_nodes[blockIdx.x] = sh_sum[0];
}
}
/*
* Helper kernel to combine per-thread block results into single values
*
* call with 1 thread block, block_size_x should be sufficiently large
*/
__global__ void combine_blocked_min_num(int *minimum, int *num_nodes, int n) {
int ti = threadIdx.x;
__shared__ int sh_min[block_size_x];
__shared__ int sh_sum[block_size_x];
int lmin = 0;
int lnum = 0;
if (ti < n) {
lmin = minimum[ti];
lnum = num_nodes[ti];
}
reduce_min_num(sh_min, sh_sum, lmin, lnum, ti);
if (ti==0) {
minimum[0] = sh_min[0];
num_nodes[0] = sh_sum[0];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#ifndef block_size_x
#define block_size_x 128
#endif
#ifndef threshold
#define threshold 3
#endif
/*
* Helper function that does the reduction step of the algorithm
*
* This function reduces the values in a thread block to a single value
*
*/
__device__ __forceinline__ void reduce_min_num(int *sh_min, int *sh_sum, int lmin, int lnum, int ti) {
sh_min[ti] = lmin;
sh_sum[ti] = lnum;
__syncthreads();
#pragma unroll
for (unsigned int s=block_size_x/2; s>0; s>>=1) {
if (ti < s) {
int self = sh_min[ti];
int other = sh_min[ti+s];
if (other >= threshold) {
if (self < threshold || other < self) {
sh_min[ti] = other;
}
}
sh_sum[ti] += sh_sum[ti + s];
}
__syncthreads();
}
}
/*
* This kernel recomputes the degree of each node in the graph and computes
* the minimum degree of all nodes with at least one edge.
*
* output arguments:
*
* minimum an array containing a per-thread block minimum degree
*
* num_nodes will contain the per-thread block sum of the number of nodes
* with at least 'threshold' edges
*
* degrees contains the degree of all nodes and is updated with the current degree
*
* input arguments:
*
* row_idx is the index of the node
* col_idx is the index of the node to which this node has an edge, this index
* can be -1 if the edge has been removed
*
* prefix_sum contains the start index of each row, because elements can be removed
* this subtracting two consecutive numbers no longer indicates the degree
*
* n is the number of nodes in the graph
*/
__global__ void minimum_degree(int *minimum, int *num_nodes, int *degrees, int *row_idx, int *col_idx, int *prefix_sum, int n) {
int ti = threadIdx.x;
int i = blockIdx.x * block_size_x + ti;
int degree = 0;
if (i<n) {
//obtain indices for reading col_idx
int start = 0;
if (i>0) {
start = prefix_sum[i-1];
}
int end = prefix_sum[i];
int max_degree = degrees[i];
//get the degree of this node
for (int k=start; k<end && degree < max_degree; k++) {
if (col_idx[k] != -1) {
degree++;
}
}
//update degrees array
degrees[i] = degree;
}
//start the reduce
//get the minimum value larger than 0
//and the total number of nodes with degree >= theshold (at least 'threshold' edges)
__shared__ int sh_min[block_size_x];
__shared__ int sh_sum[block_size_x];
int lnum = 0;
if (degree >= threshold) {
lnum = 1;
}
reduce_min_num(sh_min, sh_sum, degree, lnum, ti);
//write output
if (ti == 0) {
minimum[blockIdx.x] = sh_min[0];
num_nodes[blockIdx.x] = sh_sum[0];
}
}
/*
* Helper kernel to combine per-thread block results into single values
*
* call with 1 thread block, block_size_x should be sufficiently large
*/
__global__ void combine_blocked_min_num(int *minimum, int *num_nodes, int n) {
int ti = threadIdx.x;
__shared__ int sh_min[block_size_x];
__shared__ int sh_sum[block_size_x];
int lmin = 0;
int lnum = 0;
if (ti < n) {
lmin = minimum[ti];
lnum = num_nodes[ti];
}
reduce_min_num(sh_min, sh_sum, lmin, lnum, ti);
if (ti==0) {
minimum[0] = sh_min[0];
num_nodes[0] = sh_sum[0];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14minimum_degreePiS_S_S_S_S_i
.globl _Z14minimum_degreePiS_S_S_S_S_i
.p2align 8
.type _Z14minimum_degreePiS_S_S_S_S_i,@function
_Z14minimum_degreePiS_S_S_S_S_i:
s_load_b32 s2, s[0:1], 0x30
s_mov_b32 s4, s15
v_mov_b32_e32 v5, 0
v_lshl_add_u32 v1, s4, 7, v0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_8
s_load_b64 s[2:3], s[0:1], 0x28
v_mov_b32_e32 v3, 0
s_mov_b32 s6, exec_lo
v_cmpx_lt_i32_e32 0, v1
s_cbranch_execz .LBB0_3
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v3, v[2:3], off offset:-4
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s6
s_load_b64 s[6:7], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v6, v[4:5], off
global_load_b32 v7, v[1:2], off
v_mov_b32_e32 v5, 0
s_waitcnt vmcnt(1)
v_cmp_lt_i32_e32 vcc_lo, v3, v6
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e64 s2, 0, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s6, s2
s_cbranch_execz .LBB0_7
s_load_b64 s[2:3], s[0:1], 0x20
v_ashrrev_i32_e32 v4, 31, v3
v_add_nc_u32_e32 v8, 1, v3
s_mov_b32 s7, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v5, vcc_lo
v_mov_b32_e32 v5, 0
.p2align 6
.LBB0_5:
global_load_b32 v9, v[3:4], off
v_add_co_u32 v3, s3, v3, 4
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, -1, v9
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
v_cmp_ge_i32_e32 vcc_lo, v8, v6
v_add_nc_u32_e32 v8, 1, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_i32_e64 s2, v5, v7
s_or_b32 s2, vcc_lo, s2
v_add_co_ci_u32_e64 v4, vcc_lo, 0, v4, s3
s_and_b32 s2, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s7, s2, s7
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB0_5
s_or_b32 exec_lo, exec_lo, s7
.LBB0_7:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s6
global_store_b32 v[1:2], v5, off
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s5
v_lshlrev_b32_e32 v2, 2, v0
v_cmp_lt_i32_e32 vcc_lo, 2, v5
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v1, 0x200, v2
v_cndmask_b32_e64 v3, 0, 1, vcc_lo
ds_store_2addr_stride64_b32 v2, v5, v3 offset1:2
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 64, v0
s_cbranch_execz .LBB0_13
v_or_b32_e32 v3, 64, v0
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v4, 2, v3
ds_load_b32 v4, v4
s_waitcnt lgkmcnt(0)
v_cmpx_lt_i32_e32 2, v4
s_cbranch_execz .LBB0_12
ds_load_b32 v5, v2
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, 3, v5
v_cmp_lt_i32_e64 s2, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, vcc_lo, s2
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_12
ds_store_b32 v2, v4
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s5
v_lshlrev_b32_e32 v3, 2, v3
ds_load_b32 v3, v3 offset:512
ds_load_b32 v4, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v3, v4, v3
ds_store_b32 v1, v3
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB0_18
v_or_b32_e32 v3, 32, v0
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v3, 2, v3
ds_load_b32 v4, v3
s_waitcnt lgkmcnt(0)
v_cmpx_lt_i32_e32 2, v4
s_cbranch_execz .LBB0_17
ds_load_b32 v5, v2
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, 3, v5
v_cmp_lt_i32_e64 s2, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, vcc_lo, s2
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_17
ds_store_b32 v2, v4
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s5
ds_load_b32 v3, v3 offset:512
ds_load_b32 v4, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v3, v4, v3
ds_store_b32 v1, v3
.LBB0_18:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 16, v0
s_cbranch_execz .LBB0_23
v_or_b32_e32 v3, 16, v0
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v3, 2, v3
ds_load_b32 v4, v3
s_waitcnt lgkmcnt(0)
v_cmpx_lt_i32_e32 2, v4
s_cbranch_execz .LBB0_22
ds_load_b32 v5, v2
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, 3, v5
v_cmp_lt_i32_e64 s2, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, vcc_lo, s2
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_22
ds_store_b32 v2, v4
.LBB0_22:
s_or_b32 exec_lo, exec_lo, s5
ds_load_b32 v3, v3 offset:512
ds_load_b32 v4, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v3, v4, v3
ds_store_b32 v1, v3
.LBB0_23:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 8, v0
s_cbranch_execz .LBB0_28
v_or_b32_e32 v3, 8, v0
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v3, 2, v3
ds_load_b32 v4, v3
s_waitcnt lgkmcnt(0)
v_cmpx_lt_i32_e32 2, v4
s_cbranch_execz .LBB0_27
ds_load_b32 v5, v2
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, 3, v5
v_cmp_lt_i32_e64 s2, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, vcc_lo, s2
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_27
ds_store_b32 v2, v4
.LBB0_27:
s_or_b32 exec_lo, exec_lo, s5
ds_load_b32 v3, v3 offset:512
ds_load_b32 v4, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v3, v4, v3
ds_store_b32 v1, v3
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 4, v0
s_cbranch_execz .LBB0_33
v_or_b32_e32 v3, 4, v0
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v3, 2, v3
ds_load_b32 v4, v3
s_waitcnt lgkmcnt(0)
v_cmpx_lt_i32_e32 2, v4
s_cbranch_execz .LBB0_32
ds_load_b32 v5, v2
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, 3, v5
v_cmp_lt_i32_e64 s2, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, vcc_lo, s2
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_32
ds_store_b32 v2, v4
.LBB0_32:
s_or_b32 exec_lo, exec_lo, s5
ds_load_b32 v3, v3 offset:512
ds_load_b32 v4, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v3, v4, v3
ds_store_b32 v1, v3
.LBB0_33:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 2, v0
s_cbranch_execz .LBB0_38
v_or_b32_e32 v3, 2, v0
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v4, 2, v3
ds_load_b32 v4, v4
s_waitcnt lgkmcnt(0)
v_cmpx_lt_i32_e32 2, v4
s_cbranch_execz .LBB0_37
ds_load_b32 v5, v2
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, 3, v5
v_cmp_lt_i32_e64 s2, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, vcc_lo, s2
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_37
ds_store_b32 v2, v4
.LBB0_37:
s_or_b32 exec_lo, exec_lo, s5
v_lshlrev_b32_e32 v3, 2, v3
ds_load_b32 v3, v3 offset:512
ds_load_b32 v4, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v3, v4, v3
ds_store_b32 v1, v3
.LBB0_38:
s_or_b32 exec_lo, exec_lo, s3
v_cmp_eq_u32_e64 s2, 0, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s5, s2
s_cbranch_execz .LBB0_44
v_mov_b32_e32 v0, 0
ds_load_b32 v3, v0 offset:4
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, 3, v3
s_cbranch_vccnz .LBB0_43
ds_load_b32 v4, v2
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, 3, v4
v_cmp_lt_i32_e64 s3, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s6, vcc_lo, s3
s_and_saveexec_b32 s3, s6
s_cbranch_execz .LBB0_42
ds_store_b32 v2, v3
.LBB0_42:
s_or_b32 exec_lo, exec_lo, s3
.LBB0_43:
ds_load_b32 v0, v0 offset:516
ds_load_b32 v2, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v0, v2, v0
ds_store_b32 v1, v0
.LBB0_44:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_46
v_mov_b32_e32 v2, 0
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s5, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[4:5], s[4:5], 2
ds_load_2addr_stride64_b32 v[0:1], v2 offset1:2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s4
s_addc_u32 s1, s1, s5
s_add_u32 s2, s2, s4
s_addc_u32 s3, s3, s5
s_clause 0x1
global_store_b32 v2, v0, s[0:1]
global_store_b32 v2, v1, s[2:3]
.LBB0_46:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14minimum_degreePiS_S_S_S_S_i
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 52
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14minimum_degreePiS_S_S_S_S_i, .Lfunc_end0-_Z14minimum_degreePiS_S_S_S_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z23combine_blocked_min_numPiS_i
.globl _Z23combine_blocked_min_numPiS_i
.p2align 8
.type _Z23combine_blocked_min_numPiS_i,@function
_Z23combine_blocked_min_numPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x0
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, 0
s_mov_b32 s0, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s2, v0
v_lshlrev_b32_e32 v1, 2, v0
s_clause 0x1
global_load_b32 v3, v1, s[4:5]
global_load_b32 v4, v1, s[6:7]
s_or_b32 exec_lo, exec_lo, s0
v_lshlrev_b32_e32 v2, 2, v0
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v1, 0x200, v2
s_waitcnt vmcnt(0)
ds_store_2addr_stride64_b32 v2, v3, v4 offset1:2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 64, v0
s_cbranch_execz .LBB1_7
v_or_b32_e32 v3, 64, v0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v4, 2, v3
ds_load_b32 v4, v4
s_waitcnt lgkmcnt(0)
v_cmpx_lt_i32_e32 2, v4
s_cbranch_execz .LBB1_6
ds_load_b32 v5, v2
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, 3, v5
v_cmp_lt_i32_e64 s0, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s0, vcc_lo, s0
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB1_6
ds_store_b32 v2, v4
.LBB1_6:
s_or_b32 exec_lo, exec_lo, s2
v_lshlrev_b32_e32 v3, 2, v3
ds_load_b32 v3, v3 offset:512
ds_load_b32 v4, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v3, v4, v3
ds_store_b32 v1, v3
.LBB1_7:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s1, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB1_12
v_or_b32_e32 v3, 32, v0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v3, 2, v3
ds_load_b32 v4, v3
s_waitcnt lgkmcnt(0)
v_cmpx_lt_i32_e32 2, v4
s_cbranch_execz .LBB1_11
ds_load_b32 v5, v2
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, 3, v5
v_cmp_lt_i32_e64 s0, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s0, vcc_lo, s0
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB1_11
ds_store_b32 v2, v4
.LBB1_11:
s_or_b32 exec_lo, exec_lo, s2
ds_load_b32 v3, v3 offset:512
ds_load_b32 v4, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v3, v4, v3
ds_store_b32 v1, v3
.LBB1_12:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s1, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 16, v0
s_cbranch_execz .LBB1_17
v_or_b32_e32 v3, 16, v0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v3, 2, v3
ds_load_b32 v4, v3
s_waitcnt lgkmcnt(0)
v_cmpx_lt_i32_e32 2, v4
s_cbranch_execz .LBB1_16
ds_load_b32 v5, v2
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, 3, v5
v_cmp_lt_i32_e64 s0, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s0, vcc_lo, s0
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB1_16
ds_store_b32 v2, v4
.LBB1_16:
s_or_b32 exec_lo, exec_lo, s2
ds_load_b32 v3, v3 offset:512
ds_load_b32 v4, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v3, v4, v3
ds_store_b32 v1, v3
.LBB1_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s1, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 8, v0
s_cbranch_execz .LBB1_22
v_or_b32_e32 v3, 8, v0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v3, 2, v3
ds_load_b32 v4, v3
s_waitcnt lgkmcnt(0)
v_cmpx_lt_i32_e32 2, v4
s_cbranch_execz .LBB1_21
ds_load_b32 v5, v2
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, 3, v5
v_cmp_lt_i32_e64 s0, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s0, vcc_lo, s0
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB1_21
ds_store_b32 v2, v4
.LBB1_21:
s_or_b32 exec_lo, exec_lo, s2
ds_load_b32 v3, v3 offset:512
ds_load_b32 v4, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v3, v4, v3
ds_store_b32 v1, v3
.LBB1_22:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s1, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 4, v0
s_cbranch_execz .LBB1_27
v_or_b32_e32 v3, 4, v0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v3, 2, v3
ds_load_b32 v4, v3
s_waitcnt lgkmcnt(0)
v_cmpx_lt_i32_e32 2, v4
s_cbranch_execz .LBB1_26
ds_load_b32 v5, v2
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, 3, v5
v_cmp_lt_i32_e64 s0, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s0, vcc_lo, s0
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB1_26
ds_store_b32 v2, v4
.LBB1_26:
s_or_b32 exec_lo, exec_lo, s2
ds_load_b32 v3, v3 offset:512
ds_load_b32 v4, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v3, v4, v3
ds_store_b32 v1, v3
.LBB1_27:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s1, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 2, v0
s_cbranch_execz .LBB1_32
v_or_b32_e32 v3, 2, v0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v4, 2, v3
ds_load_b32 v4, v4
s_waitcnt lgkmcnt(0)
v_cmpx_lt_i32_e32 2, v4
s_cbranch_execz .LBB1_31
ds_load_b32 v5, v2
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, 3, v5
v_cmp_lt_i32_e64 s0, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s0, vcc_lo, s0
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB1_31
ds_store_b32 v2, v4
.LBB1_31:
s_or_b32 exec_lo, exec_lo, s2
v_lshlrev_b32_e32 v3, 2, v3
ds_load_b32 v3, v3 offset:512
ds_load_b32 v4, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v3, v4, v3
ds_store_b32 v1, v3
.LBB1_32:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_eq_u32_e64 s0, 0, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s2, s0
s_cbranch_execz .LBB1_38
v_mov_b32_e32 v0, 0
ds_load_b32 v3, v0 offset:4
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, 3, v3
s_cbranch_vccnz .LBB1_37
ds_load_b32 v4, v2
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, 3, v4
v_cmp_lt_i32_e64 s1, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s3, vcc_lo, s1
s_and_saveexec_b32 s1, s3
s_cbranch_execz .LBB1_36
ds_store_b32 v2, v3
.LBB1_36:
s_or_b32 exec_lo, exec_lo, s1
.LBB1_37:
ds_load_b32 v0, v0 offset:516
ds_load_b32 v2, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v0, v2, v0
ds_store_b32 v1, v0
.LBB1_38:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB1_40
v_mov_b32_e32 v2, 0
ds_load_2addr_stride64_b32 v[0:1], v2 offset1:2
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_store_b32 v2, v0, s[4:5]
global_store_b32 v2, v1, s[6:7]
.LBB1_40:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23combine_blocked_min_numPiS_i
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z23combine_blocked_min_numPiS_i, .Lfunc_end1-_Z23combine_blocked_min_numPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 52
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14minimum_degreePiS_S_S_S_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14minimum_degreePiS_S_S_S_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23combine_blocked_min_numPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z23combine_blocked_min_numPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#ifndef block_size_x
#define block_size_x 128
#endif
#ifndef threshold
#define threshold 3
#endif
/*
* Helper function that does the reduction step of the algorithm
*
* This function reduces the values in a thread block to a single value
*
*/
__device__ __forceinline__ void reduce_min_num(int *sh_min, int *sh_sum, int lmin, int lnum, int ti) {
sh_min[ti] = lmin;
sh_sum[ti] = lnum;
__syncthreads();
#pragma unroll
for (unsigned int s=block_size_x/2; s>0; s>>=1) {
if (ti < s) {
int self = sh_min[ti];
int other = sh_min[ti+s];
if (other >= threshold) {
if (self < threshold || other < self) {
sh_min[ti] = other;
}
}
sh_sum[ti] += sh_sum[ti + s];
}
__syncthreads();
}
}
/*
* This kernel recomputes the degree of each node in the graph and computes
* the minimum degree of all nodes with at least one edge.
*
* output arguments:
*
* minimum an array containing a per-thread block minimum degree
*
* num_nodes will contain the per-thread block sum of the number of nodes
* with at least 'threshold' edges
*
* degrees contains the degree of all nodes and is updated with the current degree
*
* input arguments:
*
* row_idx is the index of the node
* col_idx is the index of the node to which this node has an edge, this index
* can be -1 if the edge has been removed
*
* prefix_sum contains the start index of each row, because elements can be removed
* this subtracting two consecutive numbers no longer indicates the degree
*
* n is the number of nodes in the graph
*/
__global__ void minimum_degree(int *minimum, int *num_nodes, int *degrees, int *row_idx, int *col_idx, int *prefix_sum, int n) {
int ti = threadIdx.x;
int i = blockIdx.x * block_size_x + ti;
int degree = 0;
if (i<n) {
//obtain indices for reading col_idx
int start = 0;
if (i>0) {
start = prefix_sum[i-1];
}
int end = prefix_sum[i];
int max_degree = degrees[i];
//get the degree of this node
for (int k=start; k<end && degree < max_degree; k++) {
if (col_idx[k] != -1) {
degree++;
}
}
//update degrees array
degrees[i] = degree;
}
//start the reduce
//get the minimum value larger than 0
//and the total number of nodes with degree >= theshold (at least 'threshold' edges)
__shared__ int sh_min[block_size_x];
__shared__ int sh_sum[block_size_x];
int lnum = 0;
if (degree >= threshold) {
lnum = 1;
}
reduce_min_num(sh_min, sh_sum, degree, lnum, ti);
//write output
if (ti == 0) {
minimum[blockIdx.x] = sh_min[0];
num_nodes[blockIdx.x] = sh_sum[0];
}
}
/*
* Helper kernel to combine per-thread block results into single values
*
* call with 1 thread block, block_size_x should be sufficiently large
*/
__global__ void combine_blocked_min_num(int *minimum, int *num_nodes, int n) {
int ti = threadIdx.x;
__shared__ int sh_min[block_size_x];
__shared__ int sh_sum[block_size_x];
int lmin = 0;
int lnum = 0;
if (ti < n) {
lmin = minimum[ti];
lnum = num_nodes[ti];
}
reduce_min_num(sh_min, sh_sum, lmin, lnum, ti);
if (ti==0) {
minimum[0] = sh_min[0];
num_nodes[0] = sh_sum[0];
}
} | .text
.file "minimum_degree.hip"
.globl _Z29__device_stub__minimum_degreePiS_S_S_S_S_i # -- Begin function _Z29__device_stub__minimum_degreePiS_S_S_S_S_i
.p2align 4, 0x90
.type _Z29__device_stub__minimum_degreePiS_S_S_S_S_i,@function
_Z29__device_stub__minimum_degreePiS_S_S_S_S_i: # @_Z29__device_stub__minimum_degreePiS_S_S_S_S_i
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14minimum_degreePiS_S_S_S_S_i, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z29__device_stub__minimum_degreePiS_S_S_S_S_i, .Lfunc_end0-_Z29__device_stub__minimum_degreePiS_S_S_S_S_i
.cfi_endproc
# -- End function
.globl _Z38__device_stub__combine_blocked_min_numPiS_i # -- Begin function _Z38__device_stub__combine_blocked_min_numPiS_i
.p2align 4, 0x90
.type _Z38__device_stub__combine_blocked_min_numPiS_i,@function
_Z38__device_stub__combine_blocked_min_numPiS_i: # @_Z38__device_stub__combine_blocked_min_numPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z23combine_blocked_min_numPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z38__device_stub__combine_blocked_min_numPiS_i, .Lfunc_end1-_Z38__device_stub__combine_blocked_min_numPiS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14minimum_degreePiS_S_S_S_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23combine_blocked_min_numPiS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14minimum_degreePiS_S_S_S_S_i,@object # @_Z14minimum_degreePiS_S_S_S_S_i
.section .rodata,"a",@progbits
.globl _Z14minimum_degreePiS_S_S_S_S_i
.p2align 3, 0x0
_Z14minimum_degreePiS_S_S_S_S_i:
.quad _Z29__device_stub__minimum_degreePiS_S_S_S_S_i
.size _Z14minimum_degreePiS_S_S_S_S_i, 8
.type _Z23combine_blocked_min_numPiS_i,@object # @_Z23combine_blocked_min_numPiS_i
.globl _Z23combine_blocked_min_numPiS_i
.p2align 3, 0x0
_Z23combine_blocked_min_numPiS_i:
.quad _Z38__device_stub__combine_blocked_min_numPiS_i
.size _Z23combine_blocked_min_numPiS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14minimum_degreePiS_S_S_S_S_i"
.size .L__unnamed_1, 32
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z23combine_blocked_min_numPiS_i"
.size .L__unnamed_2, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__minimum_degreePiS_S_S_S_S_i
.addrsig_sym _Z38__device_stub__combine_blocked_min_numPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14minimum_degreePiS_S_S_S_S_i
.addrsig_sym _Z23combine_blocked_min_numPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a059c_00000000-6_minimum_degree.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z14minimum_degreePiS_S_S_S_S_iPiS_S_S_S_S_i
.type _Z45__device_stub__Z14minimum_degreePiS_S_S_S_S_iPiS_S_S_S_S_i, @function
_Z45__device_stub__Z14minimum_degreePiS_S_S_S_S_iPiS_S_S_S_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z14minimum_degreePiS_S_S_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z45__device_stub__Z14minimum_degreePiS_S_S_S_S_iPiS_S_S_S_S_i, .-_Z45__device_stub__Z14minimum_degreePiS_S_S_S_S_iPiS_S_S_S_S_i
.globl _Z14minimum_degreePiS_S_S_S_S_i
.type _Z14minimum_degreePiS_S_S_S_S_i, @function
_Z14minimum_degreePiS_S_S_S_S_i:
.LFB2053:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z45__device_stub__Z14minimum_degreePiS_S_S_S_S_iPiS_S_S_S_S_i
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z14minimum_degreePiS_S_S_S_S_i, .-_Z14minimum_degreePiS_S_S_S_S_i
.globl _Z46__device_stub__Z23combine_blocked_min_numPiS_iPiS_i
.type _Z46__device_stub__Z23combine_blocked_min_numPiS_iPiS_i, @function
_Z46__device_stub__Z23combine_blocked_min_numPiS_iPiS_i:
.LFB2054:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z23combine_blocked_min_numPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z46__device_stub__Z23combine_blocked_min_numPiS_iPiS_i, .-_Z46__device_stub__Z23combine_blocked_min_numPiS_iPiS_i
.globl _Z23combine_blocked_min_numPiS_i
.type _Z23combine_blocked_min_numPiS_i, @function
_Z23combine_blocked_min_numPiS_i:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z23combine_blocked_min_numPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _Z23combine_blocked_min_numPiS_i, .-_Z23combine_blocked_min_numPiS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z23combine_blocked_min_numPiS_i"
.align 8
.LC1:
.string "_Z14minimum_degreePiS_S_S_S_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z23combine_blocked_min_numPiS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z14minimum_degreePiS_S_S_S_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "minimum_degree.hip"
.globl _Z29__device_stub__minimum_degreePiS_S_S_S_S_i # -- Begin function _Z29__device_stub__minimum_degreePiS_S_S_S_S_i
.p2align 4, 0x90
.type _Z29__device_stub__minimum_degreePiS_S_S_S_S_i,@function
_Z29__device_stub__minimum_degreePiS_S_S_S_S_i: # @_Z29__device_stub__minimum_degreePiS_S_S_S_S_i
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14minimum_degreePiS_S_S_S_S_i, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z29__device_stub__minimum_degreePiS_S_S_S_S_i, .Lfunc_end0-_Z29__device_stub__minimum_degreePiS_S_S_S_S_i
.cfi_endproc
# -- End function
.globl _Z38__device_stub__combine_blocked_min_numPiS_i # -- Begin function _Z38__device_stub__combine_blocked_min_numPiS_i
.p2align 4, 0x90
.type _Z38__device_stub__combine_blocked_min_numPiS_i,@function
_Z38__device_stub__combine_blocked_min_numPiS_i: # @_Z38__device_stub__combine_blocked_min_numPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z23combine_blocked_min_numPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z38__device_stub__combine_blocked_min_numPiS_i, .Lfunc_end1-_Z38__device_stub__combine_blocked_min_numPiS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14minimum_degreePiS_S_S_S_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23combine_blocked_min_numPiS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14minimum_degreePiS_S_S_S_S_i,@object # @_Z14minimum_degreePiS_S_S_S_S_i
.section .rodata,"a",@progbits
.globl _Z14minimum_degreePiS_S_S_S_S_i
.p2align 3, 0x0
_Z14minimum_degreePiS_S_S_S_S_i:
.quad _Z29__device_stub__minimum_degreePiS_S_S_S_S_i
.size _Z14minimum_degreePiS_S_S_S_S_i, 8
.type _Z23combine_blocked_min_numPiS_i,@object # @_Z23combine_blocked_min_numPiS_i
.globl _Z23combine_blocked_min_numPiS_i
.p2align 3, 0x0
_Z23combine_blocked_min_numPiS_i:
.quad _Z38__device_stub__combine_blocked_min_numPiS_i
.size _Z23combine_blocked_min_numPiS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14minimum_degreePiS_S_S_S_S_i"
.size .L__unnamed_1, 32
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z23combine_blocked_min_numPiS_i"
.size .L__unnamed_2, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__minimum_degreePiS_S_S_S_S_i
.addrsig_sym _Z38__device_stub__combine_blocked_min_numPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14minimum_degreePiS_S_S_S_S_i
.addrsig_sym _Z23combine_blocked_min_numPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__device__ __host__ float cpu_applyFilter(float *image, int stride, float *matrix, int filter_dim)
{
float pixel = 0.0f;
for (int h = 0; h < filter_dim; h++)
{
int offset = h * stride;
int offset_kernel = h * filter_dim;
for (int w = 0; w < filter_dim; w++)
{
pixel += image[offset + w] * matrix[offset_kernel + w];
}
}
return pixel;
}
__global__ void gpu_gaussian(int width, int height, float *image, float *image_out)
{
float gaussian[9] = { 1.0f / 16.0f, 2.0f / 16.0f, 1.0f / 16.0f,
2.0f / 16.0f, 4.0f / 16.0f, 2.0f / 16.0f,
1.0f / 16.0f, 2.0f / 16.0f, 1.0f / 16.0f };
int index_x = blockIdx.x * blockDim.x + threadIdx.x;
int index_y = blockIdx.y * blockDim.y + threadIdx.y;
int offset_t = index_y * width + index_x; // Input for function
int offset = (index_y + 1) * width + (index_x + 1); // Output to store in result
// sh_block = handle_shared_memory(image, offset_t, index_x, index_y, width);
__shared__ float sh_block[BLOCK_SIZE_SH * BLOCK_SIZE_SH];
// Shared memory offset (for input value):
int offset_shared = threadIdx.y * BLOCK_SIZE_SH + threadIdx.x;
if (index_x != 0 && (index_x+1) % BLOCK_SIZE == 0) {
// Edge-case x-direction:
sh_block[offset_shared + 1] = image[offset_t + 1];
sh_block[offset_shared + 2] = image[offset_t + 2];
}
if (index_y != 0 && (index_y+1) % BLOCK_SIZE == 0) {
// Edge-case y-direction:
sh_block[offset_shared + BLOCK_SIZE_SH] = image[offset_t + width];
sh_block[offset_shared + 2*BLOCK_SIZE_SH] = image[offset_t + 2*width];
}
if ((index_x != 0 && (index_x+1) % BLOCK_SIZE == 0) && (index_y != 0 && (index_y+1) % BLOCK_SIZE == 0)) {
// Edge-case x & y-direction:
sh_block[offset_shared + BLOCK_SIZE_SH + 1] = image[offset_t + width + 1];
sh_block[offset_shared + BLOCK_SIZE_SH + 2] = image[offset_t + width + 2];
sh_block[offset_shared + 2*BLOCK_SIZE_SH + 1] = image[offset_t + 2*width + 1];
sh_block[offset_shared + 2*BLOCK_SIZE_SH + 2] = image[offset_t + 2*width + 2];
}
sh_block[offset_shared] = image[offset_t];
__syncthreads();
if (index_x < (width - 2) && index_y < (height - 2))
{
image_out[offset] = cpu_applyFilter(&sh_block[offset_shared],
BLOCK_SIZE_SH, gaussian, 3);
}
} | code for sm_80
Function : _Z12gpu_gaussianiiPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R29, SR_TID.X ; /* 0x00000000001d7919 */
/* 0x000e280000002100 */
/*0040*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0050*/ S2R R12, SR_TID.Y ; /* 0x00000000000c7919 */
/* 0x000e620000002200 */
/*0060*/ IMAD R2, R2, c[0x0][0x0], R29 ; /* 0x0000000002027a24 */
/* 0x001fca00078e021d */
/*0070*/ IADD3 R0, R2, 0x1, RZ ; /* 0x0000000102007810 */
/* 0x000fe20007ffe0ff */
/*0080*/ IMAD R3, R3, c[0x0][0x4], R12 ; /* 0x0000010003037a24 */
/* 0x002fc600078e020c */
/*0090*/ LOP3.LUT P0, RZ, R0, 0xf, RZ, 0xc0, !PT ; /* 0x0000000f00ff7812 */
/* 0x000fe2000780c0ff */
/*00a0*/ IMAD R9, R3.reuse, c[0x0][0x160], R2 ; /* 0x0000580003097a24 */
/* 0x040fe200078e0202 */
/*00b0*/ IADD3 R0, R3.reuse, 0x1, RZ ; /* 0x0000000103007810 */
/* 0x040fe40007ffe0ff */
/*00c0*/ ISETP.EQ.OR P2, PT, R3.reuse, RZ, P0 ; /* 0x000000ff0300720c */
/* 0x040fe40000742670 */
/*00d0*/ LOP3.LUT P1, RZ, R0, 0xf, RZ, 0xc0, !PT ; /* 0x0000000f00ff7812 */
/* 0x000fe2000782c0ff */
/*00e0*/ HFMA2.MMA R0, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff007435 */
/* 0x000fe200000001ff */
/*00f0*/ ISETP.EQ.OR P3, PT, R2, RZ, P2 ; /* 0x000000ff0200720c */
/* 0x000fe40001762670 */
/*0100*/ ISETP.EQ.OR P2, PT, R3, RZ, P1 ; /* 0x000000ff0300720c */
/* 0x000fc40000f42670 */
/*0110*/ IADD3 R11, R9.reuse, c[0x0][0x160], RZ ; /* 0x00005800090b7a10 */
/* 0x040fe40007ffe0ff */
/*0120*/ ISETP.EQ.OR P0, PT, R2, RZ, P0 ; /* 0x000000ff0200720c */
/* 0x000fe40000702670 */
/*0130*/ PLOP3.LUT P1, PT, P1, P3, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20000f27570 */
/*0140*/ IMAD.WIDE R8, R9, R0, c[0x0][0x168] ; /* 0x00005a0009087625 */
/* 0x000fe200078e0200 */
/*0150*/ IADD3 R7, R11, c[0x0][0x160], RZ ; /* 0x000058000b077a10 */
/* 0x000fc60007ffe0ff */
/*0160*/ IMAD.WIDE R10, R11, R0.reuse, c[0x0][0x168] ; /* 0x00005a000b0a7625 */
/* 0x080fe200078e0200 */
/*0170*/ LDG.E R27, [R8.64] ; /* 0x00000006081b7981 */
/* 0x0000a6000c1e1900 */
/*0180*/ IMAD.WIDE R6, R7, R0, c[0x0][0x168] ; /* 0x00005a0007067625 */
/* 0x000fe200078e0200 */
/*0190*/ @!P2 LDG.E R15, [R10.64] ; /* 0x000000060a0fa981 */
/* 0x000ee8000c1e1900 */
/*01a0*/ @!P0 LDG.E R5, [R8.64+0x4] ; /* 0x0000040608058981 */
/* 0x000128000c1e1900 */
/*01b0*/ @!P0 LDG.E R13, [R8.64+0x8] ; /* 0x00000806080d8981 */
/* 0x000168000c1e1900 */
/*01c0*/ @!P1 LDG.E R19, [R10.64+0x4] ; /* 0x000004060a139981 */
/* 0x000f68000c1e1900 */
/*01d0*/ @!P1 LDG.E R21, [R10.64+0x8] ; /* 0x000008060a159981 */
/* 0x000f68000c1e1900 */
/*01e0*/ @!P2 LDG.E R17, [R6.64] ; /* 0x000000060611a981 */
/* 0x000f68000c1e1900 */
/*01f0*/ @!P1 LDG.E R23, [R6.64+0x4] ; /* 0x0000040606179981 */
/* 0x000f68000c1e1900 */
/*0200*/ @!P1 LDG.E R25, [R6.64+0x8] ; /* 0x0000080606199981 */
/* 0x000f62000c1e1900 */
/*0210*/ IMAD R12, R12, 0x12, R29 ; /* 0x000000120c0c7824 */
/* 0x000fe200078e021d */
/*0220*/ ULDC UR4, c[0x0][0x164] ; /* 0x0000590000047ab9 */
/* 0x000fc40000000800 */
/*0230*/ UIADD3 UR4, UR4, -0x2, URZ ; /* 0xfffffffe04047890 */
/* 0x000fe2000fffe03f */
/*0240*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fc80000000f00 */
/*0250*/ IADD3 R9, R4, -0x2, RZ ; /* 0xfffffffe04097810 */
/* 0x001fe40007ffe0ff */
/*0260*/ ISETP.GE.AND P3, PT, R3, UR4, PT ; /* 0x0000000403007c0c */
/* 0x000fc8000bf66270 */
/*0270*/ ISETP.GE.OR P3, PT, R2, R9, P3 ; /* 0x000000090200720c */
/* 0x000fe20001f66670 */
/*0280*/ STS [R12.X4], R27 ; /* 0x0000001b0c007388 */
/* 0x0041e80000004800 */
/*0290*/ @!P2 STS [R12.X4+0x48], R15 ; /* 0x0000480f0c00a388 */
/* 0x0081e80000004800 */
/*02a0*/ @!P0 STS [R12.X4+0x4], R5 ; /* 0x000004050c008388 */
/* 0x0101e80000004800 */
/*02b0*/ @!P0 STS [R12.X4+0x8], R13 ; /* 0x0000080d0c008388 */
/* 0x0201e80000004800 */
/*02c0*/ @!P1 STS [R12.X4+0x4c], R19 ; /* 0x00004c130c009388 */
/* 0x0001e80000004800 */
/*02d0*/ @!P1 STS [R12.X4+0x50], R21 ; /* 0x000050150c009388 */
/* 0x0001e80000004800 */
/*02e0*/ @!P2 STS [R12.X4+0x90], R17 ; /* 0x000090110c00a388 */
/* 0x0001e80000004800 */
/*02f0*/ @!P1 STS [R12.X4+0x94], R23 ; /* 0x000094170c009388 */
/* 0x0001e80000004800 */
/*0300*/ @!P1 STS [R12.X4+0x98], R25 ; /* 0x000098190c009388 */
/* 0x0001e80000004800 */
/*0310*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0320*/ @P3 EXIT ; /* 0x000000000000394d */
/* 0x000fea0003800000 */
/*0330*/ LDS R5, [R12.X4] ; /* 0x000000000c057984 */
/* 0x001e220000004800 */
/*0340*/ IMAD R3, R3, R4, c[0x0][0x160] ; /* 0x0000580003037624 */
/* 0x000fc600078e0204 */
/*0350*/ LDS R6, [R12.X4+0x4] ; /* 0x000004000c067984 */
/* 0x000e640000004800 */
/*0360*/ IADD3 R3, R2, R3, RZ ; /* 0x0000000302037210 */
/* 0x000fe40007ffe0ff */
/*0370*/ LDS R8, [R12.X4+0x8] ; /* 0x000008000c087984 */
/* 0x000ea60000004800 */
/*0380*/ IMAD.WIDE R2, R3, R0, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fe200078e0200 */
/*0390*/ LDS R10, [R12.X4+0x48] ; /* 0x000048000c0a7984 */
/* 0x000ee80000004800 */
/*03a0*/ LDS R14, [R12.X4+0x4c] ; /* 0x00004c000c0e7984 */
/* 0x000f280000004800 */
/*03b0*/ LDS R16, [R12.X4+0x50] ; /* 0x000050000c107984 */
/* 0x000f680000004800 */
/*03c0*/ LDS R18, [R12.X4+0x90] ; /* 0x000090000c127984 */
/* 0x000f680000004800 */
/*03d0*/ LDS R20, [R12.X4+0x94] ; /* 0x000094000c147984 */
/* 0x000f680000004800 */
/*03e0*/ LDS R22, [R12.X4+0x98] ; /* 0x000098000c167984 */
/* 0x000f620000004800 */
/*03f0*/ FFMA R5, R5, 0.0625, RZ ; /* 0x3d80000005057823 */
/* 0x001fc800000000ff */
/*0400*/ FFMA R5, R6, 0.125, R5 ; /* 0x3e00000006057823 */
/* 0x002fc80000000005 */
/*0410*/ FFMA R5, R8, 0.0625, R5 ; /* 0x3d80000008057823 */
/* 0x004fc80000000005 */
/*0420*/ FFMA R5, R10, 0.125, R5 ; /* 0x3e0000000a057823 */
/* 0x008fc80000000005 */
/*0430*/ FFMA R5, R14, 0.25, R5 ; /* 0x3e8000000e057823 */
/* 0x010fc80000000005 */
/*0440*/ FFMA R5, R16, 0.125, R5 ; /* 0x3e00000010057823 */
/* 0x020fc80000000005 */
/*0450*/ FFMA R5, R18, 0.0625, R5 ; /* 0x3d80000012057823 */
/* 0x000fc80000000005 */
/*0460*/ FFMA R5, R20, 0.125, R5 ; /* 0x3e00000014057823 */
/* 0x000fc80000000005 */
/*0470*/ FFMA R5, R22, 0.0625, R5 ; /* 0x3d80000016057823 */
/* 0x000fca0000000005 */
/*0480*/ STG.E [R2.64+0x4], R5 ; /* 0x0000040502007986 */
/* 0x000fe2000c101906 */
/*0490*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04a0*/ BRA 0x4a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ __host__ float cpu_applyFilter(float *image, int stride, float *matrix, int filter_dim)
{
float pixel = 0.0f;
for (int h = 0; h < filter_dim; h++)
{
int offset = h * stride;
int offset_kernel = h * filter_dim;
for (int w = 0; w < filter_dim; w++)
{
pixel += image[offset + w] * matrix[offset_kernel + w];
}
}
return pixel;
}
__global__ void gpu_gaussian(int width, int height, float *image, float *image_out)
{
float gaussian[9] = { 1.0f / 16.0f, 2.0f / 16.0f, 1.0f / 16.0f,
2.0f / 16.0f, 4.0f / 16.0f, 2.0f / 16.0f,
1.0f / 16.0f, 2.0f / 16.0f, 1.0f / 16.0f };
int index_x = blockIdx.x * blockDim.x + threadIdx.x;
int index_y = blockIdx.y * blockDim.y + threadIdx.y;
int offset_t = index_y * width + index_x; // Input for function
int offset = (index_y + 1) * width + (index_x + 1); // Output to store in result
// sh_block = handle_shared_memory(image, offset_t, index_x, index_y, width);
__shared__ float sh_block[BLOCK_SIZE_SH * BLOCK_SIZE_SH];
// Shared memory offset (for input value):
int offset_shared = threadIdx.y * BLOCK_SIZE_SH + threadIdx.x;
if (index_x != 0 && (index_x+1) % BLOCK_SIZE == 0) {
// Edge-case x-direction:
sh_block[offset_shared + 1] = image[offset_t + 1];
sh_block[offset_shared + 2] = image[offset_t + 2];
}
if (index_y != 0 && (index_y+1) % BLOCK_SIZE == 0) {
// Edge-case y-direction:
sh_block[offset_shared + BLOCK_SIZE_SH] = image[offset_t + width];
sh_block[offset_shared + 2*BLOCK_SIZE_SH] = image[offset_t + 2*width];
}
if ((index_x != 0 && (index_x+1) % BLOCK_SIZE == 0) && (index_y != 0 && (index_y+1) % BLOCK_SIZE == 0)) {
// Edge-case x & y-direction:
sh_block[offset_shared + BLOCK_SIZE_SH + 1] = image[offset_t + width + 1];
sh_block[offset_shared + BLOCK_SIZE_SH + 2] = image[offset_t + width + 2];
sh_block[offset_shared + 2*BLOCK_SIZE_SH + 1] = image[offset_t + 2*width + 1];
sh_block[offset_shared + 2*BLOCK_SIZE_SH + 2] = image[offset_t + 2*width + 2];
}
sh_block[offset_shared] = image[offset_t];
__syncthreads();
if (index_x < (width - 2) && index_y < (height - 2))
{
image_out[offset] = cpu_applyFilter(&sh_block[offset_shared],
BLOCK_SIZE_SH, gaussian, 3);
}
} | .file "tmpxft_000e9a47_00000000-6_gpu_gaussian.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15cpu_applyFilterPfiS_i
.type _Z15cpu_applyFilterPfiS_i, @function
_Z15cpu_applyFilterPfiS_i:
.LFB2027:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L7
movslq %esi, %rsi
leaq 0(,%rsi,4), %r9
movslq %ecx, %rsi
salq $2, %rsi
movl $0, %r8d
pxor %xmm1, %xmm1
.L6:
movl $0, %eax
.L5:
movss (%rdi,%rax), %xmm0
mulss (%rdx,%rax), %xmm0
addss %xmm0, %xmm1
addq $4, %rax
cmpq %rsi, %rax
jne .L5
addl $1, %r8d
addq %r9, %rdi
addq %rsi, %rdx
cmpl %r8d, %ecx
jne .L6
.L3:
movaps %xmm1, %xmm0
ret
.L7:
pxor %xmm1, %xmm1
jmp .L3
.cfi_endproc
.LFE2027:
.size _Z15cpu_applyFilterPfiS_i, .-_Z15cpu_applyFilterPfiS_i
.globl _Z36__device_stub__Z12gpu_gaussianiiPfS_iiPfS_
.type _Z36__device_stub__Z12gpu_gaussianiiPfS_iiPfS_, @function
_Z36__device_stub__Z12gpu_gaussianiiPfS_iiPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L14
.L10:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12gpu_gaussianiiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L10
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z36__device_stub__Z12gpu_gaussianiiPfS_iiPfS_, .-_Z36__device_stub__Z12gpu_gaussianiiPfS_iiPfS_
.globl _Z12gpu_gaussianiiPfS_
.type _Z12gpu_gaussianiiPfS_, @function
_Z12gpu_gaussianiiPfS_:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12gpu_gaussianiiPfS_iiPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z12gpu_gaussianiiPfS_, .-_Z12gpu_gaussianiiPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z12gpu_gaussianiiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z12gpu_gaussianiiPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ __host__ float cpu_applyFilter(float *image, int stride, float *matrix, int filter_dim)
{
float pixel = 0.0f;
for (int h = 0; h < filter_dim; h++)
{
int offset = h * stride;
int offset_kernel = h * filter_dim;
for (int w = 0; w < filter_dim; w++)
{
pixel += image[offset + w] * matrix[offset_kernel + w];
}
}
return pixel;
}
__global__ void gpu_gaussian(int width, int height, float *image, float *image_out)
{
float gaussian[9] = { 1.0f / 16.0f, 2.0f / 16.0f, 1.0f / 16.0f,
2.0f / 16.0f, 4.0f / 16.0f, 2.0f / 16.0f,
1.0f / 16.0f, 2.0f / 16.0f, 1.0f / 16.0f };
int index_x = blockIdx.x * blockDim.x + threadIdx.x;
int index_y = blockIdx.y * blockDim.y + threadIdx.y;
int offset_t = index_y * width + index_x; // Input for function
int offset = (index_y + 1) * width + (index_x + 1); // Output to store in result
// sh_block = handle_shared_memory(image, offset_t, index_x, index_y, width);
__shared__ float sh_block[BLOCK_SIZE_SH * BLOCK_SIZE_SH];
// Shared memory offset (for input value):
int offset_shared = threadIdx.y * BLOCK_SIZE_SH + threadIdx.x;
if (index_x != 0 && (index_x+1) % BLOCK_SIZE == 0) {
// Edge-case x-direction:
sh_block[offset_shared + 1] = image[offset_t + 1];
sh_block[offset_shared + 2] = image[offset_t + 2];
}
if (index_y != 0 && (index_y+1) % BLOCK_SIZE == 0) {
// Edge-case y-direction:
sh_block[offset_shared + BLOCK_SIZE_SH] = image[offset_t + width];
sh_block[offset_shared + 2*BLOCK_SIZE_SH] = image[offset_t + 2*width];
}
if ((index_x != 0 && (index_x+1) % BLOCK_SIZE == 0) && (index_y != 0 && (index_y+1) % BLOCK_SIZE == 0)) {
// Edge-case x & y-direction:
sh_block[offset_shared + BLOCK_SIZE_SH + 1] = image[offset_t + width + 1];
sh_block[offset_shared + BLOCK_SIZE_SH + 2] = image[offset_t + width + 2];
sh_block[offset_shared + 2*BLOCK_SIZE_SH + 1] = image[offset_t + 2*width + 1];
sh_block[offset_shared + 2*BLOCK_SIZE_SH + 2] = image[offset_t + 2*width + 2];
}
sh_block[offset_shared] = image[offset_t];
__syncthreads();
if (index_x < (width - 2) && index_y < (height - 2))
{
image_out[offset] = cpu_applyFilter(&sh_block[offset_shared],
BLOCK_SIZE_SH, gaussian, 3);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ __host__ float cpu_applyFilter(float *image, int stride, float *matrix, int filter_dim)
{
float pixel = 0.0f;
for (int h = 0; h < filter_dim; h++)
{
int offset = h * stride;
int offset_kernel = h * filter_dim;
for (int w = 0; w < filter_dim; w++)
{
pixel += image[offset + w] * matrix[offset_kernel + w];
}
}
return pixel;
}
__global__ void gpu_gaussian(int width, int height, float *image, float *image_out)
{
float gaussian[9] = { 1.0f / 16.0f, 2.0f / 16.0f, 1.0f / 16.0f,
2.0f / 16.0f, 4.0f / 16.0f, 2.0f / 16.0f,
1.0f / 16.0f, 2.0f / 16.0f, 1.0f / 16.0f };
int index_x = blockIdx.x * blockDim.x + threadIdx.x;
int index_y = blockIdx.y * blockDim.y + threadIdx.y;
int offset_t = index_y * width + index_x; // Input for function
int offset = (index_y + 1) * width + (index_x + 1); // Output to store in result
// sh_block = handle_shared_memory(image, offset_t, index_x, index_y, width);
__shared__ float sh_block[BLOCK_SIZE_SH * BLOCK_SIZE_SH];
// Shared memory offset (for input value):
int offset_shared = threadIdx.y * BLOCK_SIZE_SH + threadIdx.x;
if (index_x != 0 && (index_x+1) % BLOCK_SIZE == 0) {
// Edge-case x-direction:
sh_block[offset_shared + 1] = image[offset_t + 1];
sh_block[offset_shared + 2] = image[offset_t + 2];
}
if (index_y != 0 && (index_y+1) % BLOCK_SIZE == 0) {
// Edge-case y-direction:
sh_block[offset_shared + BLOCK_SIZE_SH] = image[offset_t + width];
sh_block[offset_shared + 2*BLOCK_SIZE_SH] = image[offset_t + 2*width];
}
if ((index_x != 0 && (index_x+1) % BLOCK_SIZE == 0) && (index_y != 0 && (index_y+1) % BLOCK_SIZE == 0)) {
// Edge-case x & y-direction:
sh_block[offset_shared + BLOCK_SIZE_SH + 1] = image[offset_t + width + 1];
sh_block[offset_shared + BLOCK_SIZE_SH + 2] = image[offset_t + width + 2];
sh_block[offset_shared + 2*BLOCK_SIZE_SH + 1] = image[offset_t + 2*width + 1];
sh_block[offset_shared + 2*BLOCK_SIZE_SH + 2] = image[offset_t + 2*width + 2];
}
sh_block[offset_shared] = image[offset_t];
__syncthreads();
if (index_x < (width - 2) && index_y < (height - 2))
{
image_out[offset] = cpu_applyFilter(&sh_block[offset_shared],
BLOCK_SIZE_SH, gaussian, 3);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ __host__ float cpu_applyFilter(float *image, int stride, float *matrix, int filter_dim)
{
float pixel = 0.0f;
for (int h = 0; h < filter_dim; h++)
{
int offset = h * stride;
int offset_kernel = h * filter_dim;
for (int w = 0; w < filter_dim; w++)
{
pixel += image[offset + w] * matrix[offset_kernel + w];
}
}
return pixel;
}
__global__ void gpu_gaussian(int width, int height, float *image, float *image_out)
{
float gaussian[9] = { 1.0f / 16.0f, 2.0f / 16.0f, 1.0f / 16.0f,
2.0f / 16.0f, 4.0f / 16.0f, 2.0f / 16.0f,
1.0f / 16.0f, 2.0f / 16.0f, 1.0f / 16.0f };
int index_x = blockIdx.x * blockDim.x + threadIdx.x;
int index_y = blockIdx.y * blockDim.y + threadIdx.y;
int offset_t = index_y * width + index_x; // Input for function
int offset = (index_y + 1) * width + (index_x + 1); // Output to store in result
// sh_block = handle_shared_memory(image, offset_t, index_x, index_y, width);
__shared__ float sh_block[BLOCK_SIZE_SH * BLOCK_SIZE_SH];
// Shared memory offset (for input value):
int offset_shared = threadIdx.y * BLOCK_SIZE_SH + threadIdx.x;
if (index_x != 0 && (index_x+1) % BLOCK_SIZE == 0) {
// Edge-case x-direction:
sh_block[offset_shared + 1] = image[offset_t + 1];
sh_block[offset_shared + 2] = image[offset_t + 2];
}
if (index_y != 0 && (index_y+1) % BLOCK_SIZE == 0) {
// Edge-case y-direction:
sh_block[offset_shared + BLOCK_SIZE_SH] = image[offset_t + width];
sh_block[offset_shared + 2*BLOCK_SIZE_SH] = image[offset_t + 2*width];
}
if ((index_x != 0 && (index_x+1) % BLOCK_SIZE == 0) && (index_y != 0 && (index_y+1) % BLOCK_SIZE == 0)) {
// Edge-case x & y-direction:
sh_block[offset_shared + BLOCK_SIZE_SH + 1] = image[offset_t + width + 1];
sh_block[offset_shared + BLOCK_SIZE_SH + 2] = image[offset_t + width + 2];
sh_block[offset_shared + 2*BLOCK_SIZE_SH + 1] = image[offset_t + 2*width + 1];
sh_block[offset_shared + 2*BLOCK_SIZE_SH + 2] = image[offset_t + 2*width + 2];
}
sh_block[offset_shared] = image[offset_t];
__syncthreads();
if (index_x < (width - 2) && index_y < (height - 2))
{
image_out[offset] = cpu_applyFilter(&sh_block[offset_shared],
BLOCK_SIZE_SH, gaussian, 3);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12gpu_gaussianiiPfS_
.globl _Z12gpu_gaussianiiPfS_
.p2align 8
.type _Z12gpu_gaussianiiPfS_,@function
_Z12gpu_gaussianiiPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s6, s[0:1], 0x0
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_load_b64 s[4:5], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1)
v_mad_u32_u24 v8, v0, 18, v1
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v9, 1, v2
v_mad_u64_u32 v[4:5], null, v3, s6, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v5, 15, v9
v_cmp_eq_u32_e32 vcc_lo, 0, v5
s_delay_alu instid0(VALU_DEP_3)
v_ashrrev_i32_e32 v5, 31, v4
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[4:5]
v_lshlrev_b32_e32 v10, 2, v8
v_add_co_u32 v6, vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_load_b64 v[6:7], v[6:7], off offset:4
s_waitcnt vmcnt(0)
ds_store_2addr_b32 v10, v6, v7 offset0:1 offset1:2
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v10, 1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v6, 15, v10
v_cmp_eq_u32_e32 vcc_lo, 0, v6
v_add_nc_u32_e32 v6, s6, v4
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_4
v_lshl_add_u32 v11, s6, 1, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v7, 31, v6
v_ashrrev_i32_e32 v12, 31, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[13:14], 2, v[6:7]
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v13, vcc_lo, s4, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s5, v14, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v11, vcc_lo, s4, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
s_clause 0x1
global_load_b32 v7, v[13:14], off
global_load_b32 v11, v[11:12], off
v_lshlrev_b32_e32 v12, 2, v8
s_waitcnt vmcnt(0)
ds_store_2addr_b32 v12, v7, v11 offset0:18 offset1:36
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s2
v_or_b32_e32 v7, v10, v9
v_cmp_ne_u32_e32 vcc_lo, 0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v7, 15, v7
v_cmp_eq_u32_e64 s2, 0, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, vcc_lo, s2
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_6
v_lshl_add_u32 v11, s6, 1, v4
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b32_e32 v13, 2, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v12, 31, v11
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_add_co_u32 v6, vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
v_add_co_u32 v11, vcc_lo, s4, v11
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
s_clause 0x1
global_load_b64 v[6:7], v[6:7], off offset:4
global_load_b64 v[11:12], v[11:12], off offset:4
s_waitcnt vmcnt(1)
ds_store_2addr_b32 v13, v6, v7 offset0:19 offset1:20
s_waitcnt vmcnt(0)
ds_store_2addr_b32 v13, v11, v12 offset0:37 offset1:38
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s2
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_load_b32 s2, s[0:1], 0x4
s_add_i32 s3, s6, -2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, s3, v2
v_lshlrev_b32_e32 v2, 2, v8
global_load_b32 v4, v[4:5], off
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s2, -2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s2, v3
s_and_b32 s2, vcc_lo, s2
s_waitcnt vmcnt(0)
ds_store_b32 v2, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_12
v_mul_u32_u24_e32 v2, 18, v0
v_dual_mov_b32 v0, 0x3d800000 :: v_dual_lshlrev_b32 v3, 2, v1
v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v4, 0x3e800000
v_mov_b32_e32 v1, 0x3e000000
s_delay_alu instid0(VALU_DEP_3)
v_lshl_add_u32 v12, v2, 2, v3
s_mov_b32 s7, 0
s_mov_b64 s[2:3], 0
.p2align 6
.LBB0_8:
s_mov_b32 s8, -12
s_mov_b64 s[4:5], s[2:3]
.p2align 6
.LBB0_9:
v_dual_mov_b32 v3, v1 :: v_dual_add_nc_u32 v2, s8, v12
s_mov_b32 m0, s4
v_dual_mov_b32 v6, v0 :: v_dual_mov_b32 v7, v1
ds_load_b32 v13, v2 offset:12
v_dual_mov_b32 v2, v0 :: v_dual_mov_b32 v5, v1
v_mov_b32_e32 v8, v0
v_movrels_b32_e32 v2, v0
s_add_i32 s8, s8, 4
s_add_u32 s4, s4, 1
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s8, 0
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v11, v13, v2
s_cbranch_scc0 .LBB0_9
s_add_i32 s7, s7, 1
v_add_nc_u32_e32 v12, 0x48, v12
s_add_u32 s2, s2, 3
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s7, 3
s_cbranch_scc0 .LBB0_8
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[0:1], null, v10, s6, v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v11, off
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12gpu_gaussianiiPfS_
.amdhsa_group_segment_fixed_size 1296
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12gpu_gaussianiiPfS_, .Lfunc_end0-_Z12gpu_gaussianiiPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1296
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12gpu_gaussianiiPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12gpu_gaussianiiPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ __host__ float cpu_applyFilter(float *image, int stride, float *matrix, int filter_dim)
{
float pixel = 0.0f;
for (int h = 0; h < filter_dim; h++)
{
int offset = h * stride;
int offset_kernel = h * filter_dim;
for (int w = 0; w < filter_dim; w++)
{
pixel += image[offset + w] * matrix[offset_kernel + w];
}
}
return pixel;
}
__global__ void gpu_gaussian(int width, int height, float *image, float *image_out)
{
float gaussian[9] = { 1.0f / 16.0f, 2.0f / 16.0f, 1.0f / 16.0f,
2.0f / 16.0f, 4.0f / 16.0f, 2.0f / 16.0f,
1.0f / 16.0f, 2.0f / 16.0f, 1.0f / 16.0f };
int index_x = blockIdx.x * blockDim.x + threadIdx.x;
int index_y = blockIdx.y * blockDim.y + threadIdx.y;
int offset_t = index_y * width + index_x; // Input for function
int offset = (index_y + 1) * width + (index_x + 1); // Output to store in result
// sh_block = handle_shared_memory(image, offset_t, index_x, index_y, width);
__shared__ float sh_block[BLOCK_SIZE_SH * BLOCK_SIZE_SH];
// Shared memory offset (for input value):
int offset_shared = threadIdx.y * BLOCK_SIZE_SH + threadIdx.x;
if (index_x != 0 && (index_x+1) % BLOCK_SIZE == 0) {
// Edge-case x-direction:
sh_block[offset_shared + 1] = image[offset_t + 1];
sh_block[offset_shared + 2] = image[offset_t + 2];
}
if (index_y != 0 && (index_y+1) % BLOCK_SIZE == 0) {
// Edge-case y-direction:
sh_block[offset_shared + BLOCK_SIZE_SH] = image[offset_t + width];
sh_block[offset_shared + 2*BLOCK_SIZE_SH] = image[offset_t + 2*width];
}
if ((index_x != 0 && (index_x+1) % BLOCK_SIZE == 0) && (index_y != 0 && (index_y+1) % BLOCK_SIZE == 0)) {
// Edge-case x & y-direction:
sh_block[offset_shared + BLOCK_SIZE_SH + 1] = image[offset_t + width + 1];
sh_block[offset_shared + BLOCK_SIZE_SH + 2] = image[offset_t + width + 2];
sh_block[offset_shared + 2*BLOCK_SIZE_SH + 1] = image[offset_t + 2*width + 1];
sh_block[offset_shared + 2*BLOCK_SIZE_SH + 2] = image[offset_t + 2*width + 2];
}
sh_block[offset_shared] = image[offset_t];
__syncthreads();
if (index_x < (width - 2) && index_y < (height - 2))
{
image_out[offset] = cpu_applyFilter(&sh_block[offset_shared],
BLOCK_SIZE_SH, gaussian, 3);
}
} | .text
.file "gpu_gaussian.hip"
.globl _Z15cpu_applyFilterPfiS_i # -- Begin function _Z15cpu_applyFilterPfiS_i
.p2align 4, 0x90
.type _Z15cpu_applyFilterPfiS_i,@function
_Z15cpu_applyFilterPfiS_i: # @_Z15cpu_applyFilterPfiS_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB0_1
# %bb.3: # %.lr.ph25
movslq %esi, %rax
movl %ecx, %ecx
leaq (,%rcx,4), %rsi
shlq $2, %rax
xorps %xmm0, %xmm0
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB0_4: # %.lr.ph.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_5 Depth 2
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB0_5: # %.lr.ph
# Parent Loop BB0_4 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdi,%r9,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rdx,%r9,4), %xmm1
addss %xmm1, %xmm0
incq %r9
cmpq %r9, %rcx
jne .LBB0_5
# %bb.6: # %._crit_edge
# in Loop: Header=BB0_4 Depth=1
incq %r8
addq %rsi, %rdx
addq %rax, %rdi
cmpq %rcx, %r8
jne .LBB0_4
# %bb.2: # %._crit_edge26
retq
.LBB0_1:
xorps %xmm0, %xmm0
retq
.Lfunc_end0:
.size _Z15cpu_applyFilterPfiS_i, .Lfunc_end0-_Z15cpu_applyFilterPfiS_i
.cfi_endproc
# -- End function
.globl _Z27__device_stub__gpu_gaussianiiPfS_ # -- Begin function _Z27__device_stub__gpu_gaussianiiPfS_
.p2align 4, 0x90
.type _Z27__device_stub__gpu_gaussianiiPfS_,@function
_Z27__device_stub__gpu_gaussianiiPfS_: # @_Z27__device_stub__gpu_gaussianiiPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12gpu_gaussianiiPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z27__device_stub__gpu_gaussianiiPfS_, .Lfunc_end1-_Z27__device_stub__gpu_gaussianiiPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12gpu_gaussianiiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12gpu_gaussianiiPfS_,@object # @_Z12gpu_gaussianiiPfS_
.section .rodata,"a",@progbits
.globl _Z12gpu_gaussianiiPfS_
.p2align 3, 0x0
_Z12gpu_gaussianiiPfS_:
.quad _Z27__device_stub__gpu_gaussianiiPfS_
.size _Z12gpu_gaussianiiPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12gpu_gaussianiiPfS_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__gpu_gaussianiiPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12gpu_gaussianiiPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12gpu_gaussianiiPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R29, SR_TID.X ; /* 0x00000000001d7919 */
/* 0x000e280000002100 */
/*0040*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0050*/ S2R R12, SR_TID.Y ; /* 0x00000000000c7919 */
/* 0x000e620000002200 */
/*0060*/ IMAD R2, R2, c[0x0][0x0], R29 ; /* 0x0000000002027a24 */
/* 0x001fca00078e021d */
/*0070*/ IADD3 R0, R2, 0x1, RZ ; /* 0x0000000102007810 */
/* 0x000fe20007ffe0ff */
/*0080*/ IMAD R3, R3, c[0x0][0x4], R12 ; /* 0x0000010003037a24 */
/* 0x002fc600078e020c */
/*0090*/ LOP3.LUT P0, RZ, R0, 0xf, RZ, 0xc0, !PT ; /* 0x0000000f00ff7812 */
/* 0x000fe2000780c0ff */
/*00a0*/ IMAD R9, R3.reuse, c[0x0][0x160], R2 ; /* 0x0000580003097a24 */
/* 0x040fe200078e0202 */
/*00b0*/ IADD3 R0, R3.reuse, 0x1, RZ ; /* 0x0000000103007810 */
/* 0x040fe40007ffe0ff */
/*00c0*/ ISETP.EQ.OR P2, PT, R3.reuse, RZ, P0 ; /* 0x000000ff0300720c */
/* 0x040fe40000742670 */
/*00d0*/ LOP3.LUT P1, RZ, R0, 0xf, RZ, 0xc0, !PT ; /* 0x0000000f00ff7812 */
/* 0x000fe2000782c0ff */
/*00e0*/ HFMA2.MMA R0, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff007435 */
/* 0x000fe200000001ff */
/*00f0*/ ISETP.EQ.OR P3, PT, R2, RZ, P2 ; /* 0x000000ff0200720c */
/* 0x000fe40001762670 */
/*0100*/ ISETP.EQ.OR P2, PT, R3, RZ, P1 ; /* 0x000000ff0300720c */
/* 0x000fc40000f42670 */
/*0110*/ IADD3 R11, R9.reuse, c[0x0][0x160], RZ ; /* 0x00005800090b7a10 */
/* 0x040fe40007ffe0ff */
/*0120*/ ISETP.EQ.OR P0, PT, R2, RZ, P0 ; /* 0x000000ff0200720c */
/* 0x000fe40000702670 */
/*0130*/ PLOP3.LUT P1, PT, P1, P3, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20000f27570 */
/*0140*/ IMAD.WIDE R8, R9, R0, c[0x0][0x168] ; /* 0x00005a0009087625 */
/* 0x000fe200078e0200 */
/*0150*/ IADD3 R7, R11, c[0x0][0x160], RZ ; /* 0x000058000b077a10 */
/* 0x000fc60007ffe0ff */
/*0160*/ IMAD.WIDE R10, R11, R0.reuse, c[0x0][0x168] ; /* 0x00005a000b0a7625 */
/* 0x080fe200078e0200 */
/*0170*/ LDG.E R27, [R8.64] ; /* 0x00000006081b7981 */
/* 0x0000a6000c1e1900 */
/*0180*/ IMAD.WIDE R6, R7, R0, c[0x0][0x168] ; /* 0x00005a0007067625 */
/* 0x000fe200078e0200 */
/*0190*/ @!P2 LDG.E R15, [R10.64] ; /* 0x000000060a0fa981 */
/* 0x000ee8000c1e1900 */
/*01a0*/ @!P0 LDG.E R5, [R8.64+0x4] ; /* 0x0000040608058981 */
/* 0x000128000c1e1900 */
/*01b0*/ @!P0 LDG.E R13, [R8.64+0x8] ; /* 0x00000806080d8981 */
/* 0x000168000c1e1900 */
/*01c0*/ @!P1 LDG.E R19, [R10.64+0x4] ; /* 0x000004060a139981 */
/* 0x000f68000c1e1900 */
/*01d0*/ @!P1 LDG.E R21, [R10.64+0x8] ; /* 0x000008060a159981 */
/* 0x000f68000c1e1900 */
/*01e0*/ @!P2 LDG.E R17, [R6.64] ; /* 0x000000060611a981 */
/* 0x000f68000c1e1900 */
/*01f0*/ @!P1 LDG.E R23, [R6.64+0x4] ; /* 0x0000040606179981 */
/* 0x000f68000c1e1900 */
/*0200*/ @!P1 LDG.E R25, [R6.64+0x8] ; /* 0x0000080606199981 */
/* 0x000f62000c1e1900 */
/*0210*/ IMAD R12, R12, 0x12, R29 ; /* 0x000000120c0c7824 */
/* 0x000fe200078e021d */
/*0220*/ ULDC UR4, c[0x0][0x164] ; /* 0x0000590000047ab9 */
/* 0x000fc40000000800 */
/*0230*/ UIADD3 UR4, UR4, -0x2, URZ ; /* 0xfffffffe04047890 */
/* 0x000fe2000fffe03f */
/*0240*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fc80000000f00 */
/*0250*/ IADD3 R9, R4, -0x2, RZ ; /* 0xfffffffe04097810 */
/* 0x001fe40007ffe0ff */
/*0260*/ ISETP.GE.AND P3, PT, R3, UR4, PT ; /* 0x0000000403007c0c */
/* 0x000fc8000bf66270 */
/*0270*/ ISETP.GE.OR P3, PT, R2, R9, P3 ; /* 0x000000090200720c */
/* 0x000fe20001f66670 */
/*0280*/ STS [R12.X4], R27 ; /* 0x0000001b0c007388 */
/* 0x0041e80000004800 */
/*0290*/ @!P2 STS [R12.X4+0x48], R15 ; /* 0x0000480f0c00a388 */
/* 0x0081e80000004800 */
/*02a0*/ @!P0 STS [R12.X4+0x4], R5 ; /* 0x000004050c008388 */
/* 0x0101e80000004800 */
/*02b0*/ @!P0 STS [R12.X4+0x8], R13 ; /* 0x0000080d0c008388 */
/* 0x0201e80000004800 */
/*02c0*/ @!P1 STS [R12.X4+0x4c], R19 ; /* 0x00004c130c009388 */
/* 0x0001e80000004800 */
/*02d0*/ @!P1 STS [R12.X4+0x50], R21 ; /* 0x000050150c009388 */
/* 0x0001e80000004800 */
/*02e0*/ @!P2 STS [R12.X4+0x90], R17 ; /* 0x000090110c00a388 */
/* 0x0001e80000004800 */
/*02f0*/ @!P1 STS [R12.X4+0x94], R23 ; /* 0x000094170c009388 */
/* 0x0001e80000004800 */
/*0300*/ @!P1 STS [R12.X4+0x98], R25 ; /* 0x000098190c009388 */
/* 0x0001e80000004800 */
/*0310*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0320*/ @P3 EXIT ; /* 0x000000000000394d */
/* 0x000fea0003800000 */
/*0330*/ LDS R5, [R12.X4] ; /* 0x000000000c057984 */
/* 0x001e220000004800 */
/*0340*/ IMAD R3, R3, R4, c[0x0][0x160] ; /* 0x0000580003037624 */
/* 0x000fc600078e0204 */
/*0350*/ LDS R6, [R12.X4+0x4] ; /* 0x000004000c067984 */
/* 0x000e640000004800 */
/*0360*/ IADD3 R3, R2, R3, RZ ; /* 0x0000000302037210 */
/* 0x000fe40007ffe0ff */
/*0370*/ LDS R8, [R12.X4+0x8] ; /* 0x000008000c087984 */
/* 0x000ea60000004800 */
/*0380*/ IMAD.WIDE R2, R3, R0, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fe200078e0200 */
/*0390*/ LDS R10, [R12.X4+0x48] ; /* 0x000048000c0a7984 */
/* 0x000ee80000004800 */
/*03a0*/ LDS R14, [R12.X4+0x4c] ; /* 0x00004c000c0e7984 */
/* 0x000f280000004800 */
/*03b0*/ LDS R16, [R12.X4+0x50] ; /* 0x000050000c107984 */
/* 0x000f680000004800 */
/*03c0*/ LDS R18, [R12.X4+0x90] ; /* 0x000090000c127984 */
/* 0x000f680000004800 */
/*03d0*/ LDS R20, [R12.X4+0x94] ; /* 0x000094000c147984 */
/* 0x000f680000004800 */
/*03e0*/ LDS R22, [R12.X4+0x98] ; /* 0x000098000c167984 */
/* 0x000f620000004800 */
/*03f0*/ FFMA R5, R5, 0.0625, RZ ; /* 0x3d80000005057823 */
/* 0x001fc800000000ff */
/*0400*/ FFMA R5, R6, 0.125, R5 ; /* 0x3e00000006057823 */
/* 0x002fc80000000005 */
/*0410*/ FFMA R5, R8, 0.0625, R5 ; /* 0x3d80000008057823 */
/* 0x004fc80000000005 */
/*0420*/ FFMA R5, R10, 0.125, R5 ; /* 0x3e0000000a057823 */
/* 0x008fc80000000005 */
/*0430*/ FFMA R5, R14, 0.25, R5 ; /* 0x3e8000000e057823 */
/* 0x010fc80000000005 */
/*0440*/ FFMA R5, R16, 0.125, R5 ; /* 0x3e00000010057823 */
/* 0x020fc80000000005 */
/*0450*/ FFMA R5, R18, 0.0625, R5 ; /* 0x3d80000012057823 */
/* 0x000fc80000000005 */
/*0460*/ FFMA R5, R20, 0.125, R5 ; /* 0x3e00000014057823 */
/* 0x000fc80000000005 */
/*0470*/ FFMA R5, R22, 0.0625, R5 ; /* 0x3d80000016057823 */
/* 0x000fca0000000005 */
/*0480*/ STG.E [R2.64+0x4], R5 ; /* 0x0000040502007986 */
/* 0x000fe2000c101906 */
/*0490*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04a0*/ BRA 0x4a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12gpu_gaussianiiPfS_
.globl _Z12gpu_gaussianiiPfS_
.p2align 8
.type _Z12gpu_gaussianiiPfS_,@function
_Z12gpu_gaussianiiPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s6, s[0:1], 0x0
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_load_b64 s[4:5], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1)
v_mad_u32_u24 v8, v0, 18, v1
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v9, 1, v2
v_mad_u64_u32 v[4:5], null, v3, s6, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v5, 15, v9
v_cmp_eq_u32_e32 vcc_lo, 0, v5
s_delay_alu instid0(VALU_DEP_3)
v_ashrrev_i32_e32 v5, 31, v4
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[4:5]
v_lshlrev_b32_e32 v10, 2, v8
v_add_co_u32 v6, vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_load_b64 v[6:7], v[6:7], off offset:4
s_waitcnt vmcnt(0)
ds_store_2addr_b32 v10, v6, v7 offset0:1 offset1:2
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v10, 1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v6, 15, v10
v_cmp_eq_u32_e32 vcc_lo, 0, v6
v_add_nc_u32_e32 v6, s6, v4
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_4
v_lshl_add_u32 v11, s6, 1, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v7, 31, v6
v_ashrrev_i32_e32 v12, 31, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[13:14], 2, v[6:7]
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v13, vcc_lo, s4, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s5, v14, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v11, vcc_lo, s4, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
s_clause 0x1
global_load_b32 v7, v[13:14], off
global_load_b32 v11, v[11:12], off
v_lshlrev_b32_e32 v12, 2, v8
s_waitcnt vmcnt(0)
ds_store_2addr_b32 v12, v7, v11 offset0:18 offset1:36
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s2
v_or_b32_e32 v7, v10, v9
v_cmp_ne_u32_e32 vcc_lo, 0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v7, 15, v7
v_cmp_eq_u32_e64 s2, 0, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, vcc_lo, s2
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_6
v_lshl_add_u32 v11, s6, 1, v4
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b32_e32 v13, 2, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v12, 31, v11
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_add_co_u32 v6, vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
v_add_co_u32 v11, vcc_lo, s4, v11
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
s_clause 0x1
global_load_b64 v[6:7], v[6:7], off offset:4
global_load_b64 v[11:12], v[11:12], off offset:4
s_waitcnt vmcnt(1)
ds_store_2addr_b32 v13, v6, v7 offset0:19 offset1:20
s_waitcnt vmcnt(0)
ds_store_2addr_b32 v13, v11, v12 offset0:37 offset1:38
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s2
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_load_b32 s2, s[0:1], 0x4
s_add_i32 s3, s6, -2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, s3, v2
v_lshlrev_b32_e32 v2, 2, v8
global_load_b32 v4, v[4:5], off
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s2, -2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s2, v3
s_and_b32 s2, vcc_lo, s2
s_waitcnt vmcnt(0)
ds_store_b32 v2, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_12
v_mul_u32_u24_e32 v2, 18, v0
v_dual_mov_b32 v0, 0x3d800000 :: v_dual_lshlrev_b32 v3, 2, v1
v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v4, 0x3e800000
v_mov_b32_e32 v1, 0x3e000000
s_delay_alu instid0(VALU_DEP_3)
v_lshl_add_u32 v12, v2, 2, v3
s_mov_b32 s7, 0
s_mov_b64 s[2:3], 0
.p2align 6
.LBB0_8:
s_mov_b32 s8, -12
s_mov_b64 s[4:5], s[2:3]
.p2align 6
.LBB0_9:
v_dual_mov_b32 v3, v1 :: v_dual_add_nc_u32 v2, s8, v12
s_mov_b32 m0, s4
v_dual_mov_b32 v6, v0 :: v_dual_mov_b32 v7, v1
ds_load_b32 v13, v2 offset:12
v_dual_mov_b32 v2, v0 :: v_dual_mov_b32 v5, v1
v_mov_b32_e32 v8, v0
v_movrels_b32_e32 v2, v0
s_add_i32 s8, s8, 4
s_add_u32 s4, s4, 1
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s8, 0
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v11, v13, v2
s_cbranch_scc0 .LBB0_9
s_add_i32 s7, s7, 1
v_add_nc_u32_e32 v12, 0x48, v12
s_add_u32 s2, s2, 3
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s7, 3
s_cbranch_scc0 .LBB0_8
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[0:1], null, v10, s6, v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v11, off
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12gpu_gaussianiiPfS_
.amdhsa_group_segment_fixed_size 1296
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12gpu_gaussianiiPfS_, .Lfunc_end0-_Z12gpu_gaussianiiPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1296
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12gpu_gaussianiiPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12gpu_gaussianiiPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e9a47_00000000-6_gpu_gaussian.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15cpu_applyFilterPfiS_i
.type _Z15cpu_applyFilterPfiS_i, @function
_Z15cpu_applyFilterPfiS_i:
.LFB2027:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L7
movslq %esi, %rsi
leaq 0(,%rsi,4), %r9
movslq %ecx, %rsi
salq $2, %rsi
movl $0, %r8d
pxor %xmm1, %xmm1
.L6:
movl $0, %eax
.L5:
movss (%rdi,%rax), %xmm0
mulss (%rdx,%rax), %xmm0
addss %xmm0, %xmm1
addq $4, %rax
cmpq %rsi, %rax
jne .L5
addl $1, %r8d
addq %r9, %rdi
addq %rsi, %rdx
cmpl %r8d, %ecx
jne .L6
.L3:
movaps %xmm1, %xmm0
ret
.L7:
pxor %xmm1, %xmm1
jmp .L3
.cfi_endproc
.LFE2027:
.size _Z15cpu_applyFilterPfiS_i, .-_Z15cpu_applyFilterPfiS_i
.globl _Z36__device_stub__Z12gpu_gaussianiiPfS_iiPfS_
.type _Z36__device_stub__Z12gpu_gaussianiiPfS_iiPfS_, @function
_Z36__device_stub__Z12gpu_gaussianiiPfS_iiPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L14
.L10:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12gpu_gaussianiiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L10
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z36__device_stub__Z12gpu_gaussianiiPfS_iiPfS_, .-_Z36__device_stub__Z12gpu_gaussianiiPfS_iiPfS_
.globl _Z12gpu_gaussianiiPfS_
.type _Z12gpu_gaussianiiPfS_, @function
_Z12gpu_gaussianiiPfS_:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12gpu_gaussianiiPfS_iiPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z12gpu_gaussianiiPfS_, .-_Z12gpu_gaussianiiPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z12gpu_gaussianiiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z12gpu_gaussianiiPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gpu_gaussian.hip"
.globl _Z15cpu_applyFilterPfiS_i # -- Begin function _Z15cpu_applyFilterPfiS_i
.p2align 4, 0x90
.type _Z15cpu_applyFilterPfiS_i,@function
_Z15cpu_applyFilterPfiS_i: # @_Z15cpu_applyFilterPfiS_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB0_1
# %bb.3: # %.lr.ph25
movslq %esi, %rax
movl %ecx, %ecx
leaq (,%rcx,4), %rsi
shlq $2, %rax
xorps %xmm0, %xmm0
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB0_4: # %.lr.ph.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_5 Depth 2
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB0_5: # %.lr.ph
# Parent Loop BB0_4 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdi,%r9,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rdx,%r9,4), %xmm1
addss %xmm1, %xmm0
incq %r9
cmpq %r9, %rcx
jne .LBB0_5
# %bb.6: # %._crit_edge
# in Loop: Header=BB0_4 Depth=1
incq %r8
addq %rsi, %rdx
addq %rax, %rdi
cmpq %rcx, %r8
jne .LBB0_4
# %bb.2: # %._crit_edge26
retq
.LBB0_1:
xorps %xmm0, %xmm0
retq
.Lfunc_end0:
.size _Z15cpu_applyFilterPfiS_i, .Lfunc_end0-_Z15cpu_applyFilterPfiS_i
.cfi_endproc
# -- End function
.globl _Z27__device_stub__gpu_gaussianiiPfS_ # -- Begin function _Z27__device_stub__gpu_gaussianiiPfS_
.p2align 4, 0x90
.type _Z27__device_stub__gpu_gaussianiiPfS_,@function
_Z27__device_stub__gpu_gaussianiiPfS_: # @_Z27__device_stub__gpu_gaussianiiPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12gpu_gaussianiiPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z27__device_stub__gpu_gaussianiiPfS_, .Lfunc_end1-_Z27__device_stub__gpu_gaussianiiPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12gpu_gaussianiiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12gpu_gaussianiiPfS_,@object # @_Z12gpu_gaussianiiPfS_
.section .rodata,"a",@progbits
.globl _Z12gpu_gaussianiiPfS_
.p2align 3, 0x0
_Z12gpu_gaussianiiPfS_:
.quad _Z27__device_stub__gpu_gaussianiiPfS_
.size _Z12gpu_gaussianiiPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12gpu_gaussianiiPfS_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__gpu_gaussianiiPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12gpu_gaussianiiPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cstdio>
#include <cmath>
#include <complex>
#include <cstring>
#include <iostream>
#include <fstream>
using namespace std;
const int N = (1 << 30);
__global__ void multiply(int n, int m, char x[], char y[], int ans[]) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
if( i < n && j < m){
int a = n-1-i, b = m-1-j;
atomicAdd(&ans[a+b], (x[i]-48) * (y[j]-48));
//printf("x[%d] : %d * y[%d] : %d = %d\n", i, x[i]-48, j, y[j]-48, ans[a+b]);
}
}
int main(int argc,char *argv[]) {
char *s = new char[N];
char *t = new char[N];
int n, m, l;
FILE* fin = fopen(argv[1],"r");
fscanf(fin,"%s",s);
fclose(fin);
fin = fopen(argv[2],"r");
fscanf(fin,"%s",t);
fclose(fin);
n = strlen(s);
m = strlen(t);
l = n + m + 1;
int *ans = new int[l];
char* cuda_s;
char* cuda_t;
int* cuda_ans;
cudaMalloc(&cuda_s, n * sizeof(char));
cudaMalloc(&cuda_t, m * sizeof(char));
cudaMalloc(&cuda_ans, l * sizeof(int));
cudaMemcpy(cuda_s, s, n*sizeof(char), cudaMemcpyHostToDevice);
cudaMemcpy(cuda_t, t, m*sizeof(char), cudaMemcpyHostToDevice);
dim3 threadsPerBlock(16, 16);
dim3 numBlocks(n+16 / threadsPerBlock.x, m+16 / threadsPerBlock.y);
multiply<<<numBlocks, threadsPerBlock>>>(n, m, cuda_s, cuda_t, cuda_ans);
cudaMemcpy(ans, cuda_ans, l*sizeof(int), cudaMemcpyDeviceToHost);
for (int i = 0; i < l; ++i) {
ans[i + 1] += ans[i] / 10;
ans[i] %= 10;
}
int p = l;
for (; p && !ans[p]; --p);
for (; ~p; putchar(ans[p--] + '0'));
puts("");
return 0;
} | code for sm_80
Function : _Z8multiplyiiPcS_Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002600 */
/*0020*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x4], R5 ; /* 0x0000010002027a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x164], PT ; /* 0x0000590002007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x160], P0 ; /* 0x0000580000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R4, P0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000047a10 */
/* 0x000fe20007f1e0ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IADD3 R6, P1, R2, c[0x0][0x170], RZ ; /* 0x00005c0002067a10 */
/* 0x000fe40007f3e0ff */
/*00d0*/ LEA.HI.X.SX32 R5, R0, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0000057a11 */
/* 0x000fe400000f0eff */
/*00e0*/ LEA.HI.X.SX32 R7, R2, c[0x0][0x174], 0x1, P1 ; /* 0x00005d0002077a11 */
/* 0x000fc600008f0eff */
/*00f0*/ LDG.E.S8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1300 */
/*0100*/ LDG.E.S8 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1300 */
/*0110*/ LOP3.LUT R0, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff007212 */
/* 0x000fe400078e33ff */
/*0120*/ LOP3.LUT R3, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff037212 */
/* 0x000fc800078e33ff */
/*0130*/ IADD3 R0, R3, c[0x0][0x160], R0 ; /* 0x0000580003007a10 */
/* 0x000fe20007ffe000 */
/*0140*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc600078e00ff */
/*0150*/ IADD3 R0, R0, c[0x0][0x164], RZ ; /* 0x0000590000007a10 */
/* 0x000fca0007ffe0ff */
/*0160*/ IMAD.WIDE R2, R0, R3, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x000fe200078e0203 */
/*0170*/ IADD3 R8, R4, -0x30, RZ ; /* 0xffffffd004087810 */
/* 0x004fe40007ffe0ff */
/*0180*/ IADD3 R9, R6, -0x30, RZ ; /* 0xffffffd006097810 */
/* 0x008fca0007ffe0ff */
/*0190*/ IMAD R9, R8, R9, RZ ; /* 0x0000000908097224 */
/* 0x000fca00078e02ff */
/*01a0*/ RED.E.ADD.STRONG.GPU [R2.64], R9 ; /* 0x000000090200798e */
/* 0x000fe2000c10e184 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cstdio>
#include <cmath>
#include <complex>
#include <cstring>
#include <iostream>
#include <fstream>
using namespace std;
const int N = (1 << 30);
__global__ void multiply(int n, int m, char x[], char y[], int ans[]) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
if( i < n && j < m){
int a = n-1-i, b = m-1-j;
atomicAdd(&ans[a+b], (x[i]-48) * (y[j]-48));
//printf("x[%d] : %d * y[%d] : %d = %d\n", i, x[i]-48, j, y[j]-48, ans[a+b]);
}
}
int main(int argc,char *argv[]) {
char *s = new char[N];
char *t = new char[N];
int n, m, l;
FILE* fin = fopen(argv[1],"r");
fscanf(fin,"%s",s);
fclose(fin);
fin = fopen(argv[2],"r");
fscanf(fin,"%s",t);
fclose(fin);
n = strlen(s);
m = strlen(t);
l = n + m + 1;
int *ans = new int[l];
char* cuda_s;
char* cuda_t;
int* cuda_ans;
cudaMalloc(&cuda_s, n * sizeof(char));
cudaMalloc(&cuda_t, m * sizeof(char));
cudaMalloc(&cuda_ans, l * sizeof(int));
cudaMemcpy(cuda_s, s, n*sizeof(char), cudaMemcpyHostToDevice);
cudaMemcpy(cuda_t, t, m*sizeof(char), cudaMemcpyHostToDevice);
dim3 threadsPerBlock(16, 16);
dim3 numBlocks(n+16 / threadsPerBlock.x, m+16 / threadsPerBlock.y);
multiply<<<numBlocks, threadsPerBlock>>>(n, m, cuda_s, cuda_t, cuda_ans);
cudaMemcpy(ans, cuda_ans, l*sizeof(int), cudaMemcpyDeviceToHost);
for (int i = 0; i < l; ++i) {
ans[i + 1] += ans[i] / 10;
ans[i] %= 10;
}
int p = l;
for (; p && !ans[p]; --p);
for (; ~p; putchar(ans[p--] + '0'));
puts("");
return 0;
} | .file "tmpxft_0004651b_00000000-6_large_mutiply.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4103:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4103:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z8multiplyiiPcS_PiiiPcS_Pi
.type _Z33__device_stub__Z8multiplyiiPcS_PiiiPcS_Pi, @function
_Z33__device_stub__Z8multiplyiiPcS_PiiiPcS_Pi:
.LFB4125:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8multiplyiiPcS_Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4125:
.size _Z33__device_stub__Z8multiplyiiPcS_PiiiPcS_Pi, .-_Z33__device_stub__Z8multiplyiiPcS_PiiiPcS_Pi
.globl _Z8multiplyiiPcS_Pi
.type _Z8multiplyiiPcS_Pi, @function
_Z8multiplyiiPcS_Pi:
.LFB4126:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z8multiplyiiPcS_PiiiPcS_Pi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4126:
.size _Z8multiplyiiPcS_Pi, .-_Z8multiplyiiPcS_Pi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "%s"
.LC2:
.string ""
.text
.globl main
.type main, @function
main:
.LFB4100:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $1073741824, %edi
call _Znam@PLT
movq %rax, %r14
movl $1073741824, %edi
call _Znam@PLT
movq %rax, %r15
movq 8(%rbx), %rdi
leaq .LC0(%rip), %r13
movq %r13, %rsi
call fopen@PLT
movq %rax, %r12
movq %r14, %rdx
leaq .LC1(%rip), %rbp
movq %rbp, %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movq %r12, %rdi
call fclose@PLT
movq 16(%rbx), %rdi
movq %r13, %rsi
call fopen@PLT
movq %rax, %rbx
movq %r15, %rdx
movq %rbp, %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movq %rbx, %rdi
call fclose@PLT
movq %r14, 16(%rsp)
movq %r14, %rdi
call strlen@PLT
movq %rax, %r14
movl %eax, 40(%rsp)
movq %r15, 24(%rsp)
movq %r15, %rdi
call strlen@PLT
movq %rax, %r13
movl %eax, 44(%rsp)
leal (%rax,%r14), %r12d
leal 1(%r12), %eax
movl %eax, 36(%rsp)
movslq %eax, %rbx
movabsq $2305843009213693950, %rax
cmpq %rbx, %rax
jb .L12
leaq 0(,%rbx,4), %r15
movq %r15, %rdi
call _Znam@PLT
movq %rax, %rbp
movslq %r14d, %rax
leaq 56(%rsp), %rdi
movq %rax, (%rsp)
movq %rax, %rsi
call cudaMalloc@PLT
movslq %r13d, %rax
leaq 64(%rsp), %rdi
movq %rax, 8(%rsp)
movq %rax, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq (%rsp), %rdx
movq 16(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq 8(%rsp), %rdx
movq 24(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
addl $1, %r14d
movl %r14d, 92(%rsp)
addl $1, %r13d
movl %r13d, 96(%rsp)
movl $16, 80(%rsp)
movl $16, 84(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 92(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L13:
movl $2, %ecx
movq %r15, %rdx
movq 72(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
cmpl $0, 36(%rsp)
jle .L16
movq %rbp, %rdx
movl %r12d, %edi
leaq 4(%rbp,%rdi,4), %r8
.L17:
movl (%rdx), %ecx
movslq %ecx, %rax
imulq $1717986919, %rax, %rax
sarq $34, %rax
movl %ecx, %esi
sarl $31, %esi
subl %esi, %eax
addl %eax, 4(%rdx)
leal (%rax,%rax,4), %eax
addl %eax, %eax
subl %eax, %ecx
movl %ecx, (%rdx)
addq $4, %rdx
cmpq %r8, %rdx
jne .L17
movslq %r12d, %r12
subq %rdi, %r12
.L19:
cmpl $0, 0(%rbp,%rbx,4)
jne .L35
subq $1, %rbx
cmpq %r12, %rbx
jne .L19
.L16:
movl $0, %eax
.L20:
movslq %eax, %rdx
salq $2, %rdx
leaq 0(%rbp,%rdx), %rbx
leaq -4(%rbp,%rdx), %rbp
movl %eax, %eax
salq $2, %rax
subq %rax, %rbp
.L24:
movl (%rbx), %eax
leal 48(%rax), %edi
movq stdout(%rip), %rsi
call putc@PLT
subq $4, %rbx
cmpq %rbp, %rbx
jne .L24
.L21:
leaq .LC2(%rip), %rdi
call puts@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L36
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L15
call __stack_chk_fail@PLT
.L15:
call __cxa_throw_bad_array_new_length@PLT
.L34:
movq 72(%rsp), %r8
movq 64(%rsp), %rcx
movq 56(%rsp), %rdx
movl 44(%rsp), %esi
movl 40(%rsp), %edi
call _Z33__device_stub__Z8multiplyiiPcS_PiiiPcS_Pi
jmp .L13
.L35:
movl %ebx, %eax
cmpl $-1, %ebx
jne .L20
jmp .L21
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4100:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z8multiplyiiPcS_Pi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4128:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z8multiplyiiPcS_Pi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4128:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cstdio>
#include <cmath>
#include <complex>
#include <cstring>
#include <iostream>
#include <fstream>
using namespace std;
const int N = (1 << 30);
__global__ void multiply(int n, int m, char x[], char y[], int ans[]) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
if( i < n && j < m){
int a = n-1-i, b = m-1-j;
atomicAdd(&ans[a+b], (x[i]-48) * (y[j]-48));
//printf("x[%d] : %d * y[%d] : %d = %d\n", i, x[i]-48, j, y[j]-48, ans[a+b]);
}
}
int main(int argc,char *argv[]) {
char *s = new char[N];
char *t = new char[N];
int n, m, l;
FILE* fin = fopen(argv[1],"r");
fscanf(fin,"%s",s);
fclose(fin);
fin = fopen(argv[2],"r");
fscanf(fin,"%s",t);
fclose(fin);
n = strlen(s);
m = strlen(t);
l = n + m + 1;
int *ans = new int[l];
char* cuda_s;
char* cuda_t;
int* cuda_ans;
cudaMalloc(&cuda_s, n * sizeof(char));
cudaMalloc(&cuda_t, m * sizeof(char));
cudaMalloc(&cuda_ans, l * sizeof(int));
cudaMemcpy(cuda_s, s, n*sizeof(char), cudaMemcpyHostToDevice);
cudaMemcpy(cuda_t, t, m*sizeof(char), cudaMemcpyHostToDevice);
dim3 threadsPerBlock(16, 16);
dim3 numBlocks(n+16 / threadsPerBlock.x, m+16 / threadsPerBlock.y);
multiply<<<numBlocks, threadsPerBlock>>>(n, m, cuda_s, cuda_t, cuda_ans);
cudaMemcpy(ans, cuda_ans, l*sizeof(int), cudaMemcpyDeviceToHost);
for (int i = 0; i < l; ++i) {
ans[i + 1] += ans[i] / 10;
ans[i] %= 10;
}
int p = l;
for (; p && !ans[p]; --p);
for (; ~p; putchar(ans[p--] + '0'));
puts("");
return 0;
} | #include <hip/hip_runtime.h>
#include <cstdio>
#include <cmath>
#include <complex>
#include <cstring>
#include <iostream>
#include <fstream>
using namespace std;
const int N = (1 << 30);
__global__ void multiply(int n, int m, char x[], char y[], int ans[]) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
if( i < n && j < m){
int a = n-1-i, b = m-1-j;
atomicAdd(&ans[a+b], (x[i]-48) * (y[j]-48));
//printf("x[%d] : %d * y[%d] : %d = %d\n", i, x[i]-48, j, y[j]-48, ans[a+b]);
}
}
int main(int argc,char *argv[]) {
char *s = new char[N];
char *t = new char[N];
int n, m, l;
FILE* fin = fopen(argv[1],"r");
fscanf(fin,"%s",s);
fclose(fin);
fin = fopen(argv[2],"r");
fscanf(fin,"%s",t);
fclose(fin);
n = strlen(s);
m = strlen(t);
l = n + m + 1;
int *ans = new int[l];
char* cuda_s;
char* cuda_t;
int* cuda_ans;
hipMalloc(&cuda_s, n * sizeof(char));
hipMalloc(&cuda_t, m * sizeof(char));
hipMalloc(&cuda_ans, l * sizeof(int));
hipMemcpy(cuda_s, s, n*sizeof(char), hipMemcpyHostToDevice);
hipMemcpy(cuda_t, t, m*sizeof(char), hipMemcpyHostToDevice);
dim3 threadsPerBlock(16, 16);
dim3 numBlocks(n+16 / threadsPerBlock.x, m+16 / threadsPerBlock.y);
multiply<<<numBlocks, threadsPerBlock>>>(n, m, cuda_s, cuda_t, cuda_ans);
hipMemcpy(ans, cuda_ans, l*sizeof(int), hipMemcpyDeviceToHost);
for (int i = 0; i < l; ++i) {
ans[i + 1] += ans[i] / 10;
ans[i] %= 10;
}
int p = l;
for (; p && !ans[p]; --p);
for (; ~p; putchar(ans[p--] + '0'));
puts("");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
#include <cmath>
#include <complex>
#include <cstring>
#include <iostream>
#include <fstream>
using namespace std;
const int N = (1 << 30);
__global__ void multiply(int n, int m, char x[], char y[], int ans[]) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
if( i < n && j < m){
int a = n-1-i, b = m-1-j;
atomicAdd(&ans[a+b], (x[i]-48) * (y[j]-48));
//printf("x[%d] : %d * y[%d] : %d = %d\n", i, x[i]-48, j, y[j]-48, ans[a+b]);
}
}
int main(int argc,char *argv[]) {
char *s = new char[N];
char *t = new char[N];
int n, m, l;
FILE* fin = fopen(argv[1],"r");
fscanf(fin,"%s",s);
fclose(fin);
fin = fopen(argv[2],"r");
fscanf(fin,"%s",t);
fclose(fin);
n = strlen(s);
m = strlen(t);
l = n + m + 1;
int *ans = new int[l];
char* cuda_s;
char* cuda_t;
int* cuda_ans;
hipMalloc(&cuda_s, n * sizeof(char));
hipMalloc(&cuda_t, m * sizeof(char));
hipMalloc(&cuda_ans, l * sizeof(int));
hipMemcpy(cuda_s, s, n*sizeof(char), hipMemcpyHostToDevice);
hipMemcpy(cuda_t, t, m*sizeof(char), hipMemcpyHostToDevice);
dim3 threadsPerBlock(16, 16);
dim3 numBlocks(n+16 / threadsPerBlock.x, m+16 / threadsPerBlock.y);
multiply<<<numBlocks, threadsPerBlock>>>(n, m, cuda_s, cuda_t, cuda_ans);
hipMemcpy(ans, cuda_ans, l*sizeof(int), hipMemcpyDeviceToHost);
for (int i = 0; i < l; ++i) {
ans[i + 1] += ans[i] / 10;
ans[i] %= 10;
}
int p = l;
for (; p && !ans[p]; --p);
for (; ~p; putchar(ans[p--] + '0'));
puts("");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8multiplyiiPcS_Pi
.globl _Z8multiplyiiPcS_Pi
.p2align 8
.type _Z8multiplyiiPcS_Pi,@function
_Z8multiplyiiPcS_Pi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x0
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x18
v_ashrrev_i32_e32 v3, 31, v0
v_ashrrev_i32_e32 v5, 31, v1
s_add_i32 s2, s4, s5
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s10, v1
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
v_add_nc_u32_e32 v0, v0, v1
global_load_i8 v2, v[2:3], off
global_load_i8 v3, v[4:5], off
v_sub_nc_u32_e32 v0, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, -2, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(1)
v_subrev_nc_u32_e32 v2, 48, v2
s_waitcnt vmcnt(0)
v_subrev_nc_u32_e32 v3, 48, v3
v_mul_i32_i24_e32 v2, v3, v2
global_atomic_add_u32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8multiplyiiPcS_Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8multiplyiiPcS_Pi, .Lfunc_end0-_Z8multiplyiiPcS_Pi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8multiplyiiPcS_Pi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8multiplyiiPcS_Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
#include <cmath>
#include <complex>
#include <cstring>
#include <iostream>
#include <fstream>
using namespace std;
const int N = (1 << 30);
__global__ void multiply(int n, int m, char x[], char y[], int ans[]) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
if( i < n && j < m){
int a = n-1-i, b = m-1-j;
atomicAdd(&ans[a+b], (x[i]-48) * (y[j]-48));
//printf("x[%d] : %d * y[%d] : %d = %d\n", i, x[i]-48, j, y[j]-48, ans[a+b]);
}
}
int main(int argc,char *argv[]) {
char *s = new char[N];
char *t = new char[N];
int n, m, l;
FILE* fin = fopen(argv[1],"r");
fscanf(fin,"%s",s);
fclose(fin);
fin = fopen(argv[2],"r");
fscanf(fin,"%s",t);
fclose(fin);
n = strlen(s);
m = strlen(t);
l = n + m + 1;
int *ans = new int[l];
char* cuda_s;
char* cuda_t;
int* cuda_ans;
hipMalloc(&cuda_s, n * sizeof(char));
hipMalloc(&cuda_t, m * sizeof(char));
hipMalloc(&cuda_ans, l * sizeof(int));
hipMemcpy(cuda_s, s, n*sizeof(char), hipMemcpyHostToDevice);
hipMemcpy(cuda_t, t, m*sizeof(char), hipMemcpyHostToDevice);
dim3 threadsPerBlock(16, 16);
dim3 numBlocks(n+16 / threadsPerBlock.x, m+16 / threadsPerBlock.y);
multiply<<<numBlocks, threadsPerBlock>>>(n, m, cuda_s, cuda_t, cuda_ans);
hipMemcpy(ans, cuda_ans, l*sizeof(int), hipMemcpyDeviceToHost);
for (int i = 0; i < l; ++i) {
ans[i + 1] += ans[i] / 10;
ans[i] %= 10;
}
int p = l;
for (; p && !ans[p]; --p);
for (; ~p; putchar(ans[p--] + '0'));
puts("");
return 0;
} | .text
.file "large_mutiply.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z23__device_stub__multiplyiiPcS_Pi # -- Begin function _Z23__device_stub__multiplyiiPcS_Pi
.p2align 4, 0x90
.type _Z23__device_stub__multiplyiiPcS_Pi,@function
_Z23__device_stub__multiplyiiPcS_Pi: # @_Z23__device_stub__multiplyiiPcS_Pi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8multiplyiiPcS_Pi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__multiplyiiPcS_Pi, .Lfunc_end0-_Z23__device_stub__multiplyiiPcS_Pi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl $1073741824, %edi # imm = 0x40000000
callq _Znam
movq %rax, %r12
movl $1073741824, %edi # imm = 0x40000000
callq _Znam
movq %rax, %r15
movq %rax, 80(%rsp) # 8-byte Spill
movq 8(%rbx), %rdi
movl $.L.str, %esi
callq fopen
movq %rax, %r14
movl $.L.str.1, %esi
movq %rax, %rdi
movq %r12, %rdx
movq %r12, 72(%rsp) # 8-byte Spill
xorl %eax, %eax
callq __isoc23_fscanf
movq %r14, %rdi
callq fclose
movq 16(%rbx), %rdi
movl $.L.str, %esi
callq fopen
movq %rax, %rbx
movl $.L.str.1, %esi
movq %rax, %rdi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movq %rbx, %rdi
callq fclose
movq %r12, %rdi
callq strlen
movq %rax, %r14
movq %r15, %rdi
callq strlen
movq %rax, %r15
addl %r14d, %eax
leal 1(%r15,%r14), %r13d
movslq %r13d, %rbp
leaq (,%rbp,4), %rcx
movq %rcx, 40(%rsp) # 8-byte Spill
movl %eax, 12(%rsp) # 4-byte Spill
cmpl $-1, %eax
movq $-1, %rdi
cmovgeq %rcx, %rdi
callq _Znam
movq %rax, %rbx
movq %r14, 32(%rsp) # 8-byte Spill
movslq %r14d, %r12
leaq 64(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq %r15, %r14
shlq $32, %r14
movq %r15, 24(%rsp) # 8-byte Spill
movslq %r15d, %r15
leaq 56(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq 40(%rsp), %rsi # 8-byte Reload
callq hipMalloc
movq 64(%rsp), %rdi
movq 72(%rsp), %rsi # 8-byte Reload
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 56(%rsp), %rdi
movq 80(%rsp), %rsi # 8-byte Reload
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
incl %r12d
orq %r14, %r12
movabsq $4294967296, %rdi # imm = 0x100000000
addq %r12, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 64(%rsp), %rax
movq 56(%rsp), %rcx
movq 48(%rsp), %rdx
movq 32(%rsp), %rsi # 8-byte Reload
movl %esi, 20(%rsp)
movq 24(%rsp), %rsi # 8-byte Reload
movl %esi, 16(%rsp)
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 152(%rsp), %rax
movq %rax, 176(%rsp)
leaq 144(%rsp), %rax
movq %rax, 184(%rsp)
leaq 136(%rsp), %rax
movq %rax, 192(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z8multiplyiiPcS_Pi, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 48(%rsp), %rsi
movq %rbx, %rdi
movq 40(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
cmpl $0, 12(%rsp) # 4-byte Folded Reload
js .LBB1_5
# %bb.3: # %.lr.ph.preheader
movq 32(%rsp), %rax # 8-byte Reload
movq 24(%rsp), %rcx # 8-byte Reload
addl %ecx, %eax
incl %eax
movl (%rbx), %edx
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movslq %edx, %rsi
imulq $1717986919, %rsi, %rdi # imm = 0x66666667
movq %rdi, %rdx
shrq $63, %rdx
sarq $34, %rdi
addl %edx, %edi
movl 4(%rbx,%rcx,4), %edx
addl %edi, %edx
movl %edx, 4(%rbx,%rcx,4)
addl %edi, %edi
leal (%rdi,%rdi,4), %edi
subl %edi, %esi
movl %esi, (%rbx,%rcx,4)
leaq 1(%rcx), %rsi
movq %rsi, %rcx
cmpq %rsi, %rax
jne .LBB1_4
.LBB1_5: # %.preheader
testl %r13d, %r13d
je .LBB1_10
# %bb.6: # %.lr.ph61.preheader
decq %rbp
.p2align 4, 0x90
.LBB1_7: # %.lr.ph61
# =>This Inner Loop Header: Depth=1
cmpl $0, 4(%rbx,%rbp,4)
jne .LBB1_10
# %bb.8: # in Loop: Header=BB1_7 Depth=1
decl %r13d
movq %rbp, %rax
decq %rax
testl %ebp, %ebp
movq %rax, %rbp
jne .LBB1_7
# %bb.9:
xorl %r13d, %r13d
.LBB1_10: # %.critedge
cmpl $-1, %r13d
je .LBB1_13
# %bb.11: # %.lr.ph66.preheader
movslq %r13d, %r14
.p2align 4, 0x90
.LBB1_12: # %.lr.ph66
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %edi
addl $48, %edi
movq stdout(%rip), %rsi
callq putc
addq $-1, %r14
jb .LBB1_12
.LBB1_13: # %._crit_edge
movq stdout(%rip), %rsi
movl $10, %edi
callq putc
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8multiplyiiPcS_Pi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8multiplyiiPcS_Pi,@object # @_Z8multiplyiiPcS_Pi
.section .rodata,"a",@progbits
.globl _Z8multiplyiiPcS_Pi
.p2align 3, 0x0
_Z8multiplyiiPcS_Pi:
.quad _Z23__device_stub__multiplyiiPcS_Pi
.size _Z8multiplyiiPcS_Pi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%s"
.size .L.str.1, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8multiplyiiPcS_Pi"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__multiplyiiPcS_Pi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8multiplyiiPcS_Pi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8multiplyiiPcS_Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002600 */
/*0020*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x4], R5 ; /* 0x0000010002027a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x164], PT ; /* 0x0000590002007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x160], P0 ; /* 0x0000580000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R4, P0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000047a10 */
/* 0x000fe20007f1e0ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IADD3 R6, P1, R2, c[0x0][0x170], RZ ; /* 0x00005c0002067a10 */
/* 0x000fe40007f3e0ff */
/*00d0*/ LEA.HI.X.SX32 R5, R0, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0000057a11 */
/* 0x000fe400000f0eff */
/*00e0*/ LEA.HI.X.SX32 R7, R2, c[0x0][0x174], 0x1, P1 ; /* 0x00005d0002077a11 */
/* 0x000fc600008f0eff */
/*00f0*/ LDG.E.S8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1300 */
/*0100*/ LDG.E.S8 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1300 */
/*0110*/ LOP3.LUT R0, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff007212 */
/* 0x000fe400078e33ff */
/*0120*/ LOP3.LUT R3, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff037212 */
/* 0x000fc800078e33ff */
/*0130*/ IADD3 R0, R3, c[0x0][0x160], R0 ; /* 0x0000580003007a10 */
/* 0x000fe20007ffe000 */
/*0140*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc600078e00ff */
/*0150*/ IADD3 R0, R0, c[0x0][0x164], RZ ; /* 0x0000590000007a10 */
/* 0x000fca0007ffe0ff */
/*0160*/ IMAD.WIDE R2, R0, R3, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x000fe200078e0203 */
/*0170*/ IADD3 R8, R4, -0x30, RZ ; /* 0xffffffd004087810 */
/* 0x004fe40007ffe0ff */
/*0180*/ IADD3 R9, R6, -0x30, RZ ; /* 0xffffffd006097810 */
/* 0x008fca0007ffe0ff */
/*0190*/ IMAD R9, R8, R9, RZ ; /* 0x0000000908097224 */
/* 0x000fca00078e02ff */
/*01a0*/ RED.E.ADD.STRONG.GPU [R2.64], R9 ; /* 0x000000090200798e */
/* 0x000fe2000c10e184 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8multiplyiiPcS_Pi
.globl _Z8multiplyiiPcS_Pi
.p2align 8
.type _Z8multiplyiiPcS_Pi,@function
_Z8multiplyiiPcS_Pi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x0
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x18
v_ashrrev_i32_e32 v3, 31, v0
v_ashrrev_i32_e32 v5, 31, v1
s_add_i32 s2, s4, s5
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s10, v1
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
v_add_nc_u32_e32 v0, v0, v1
global_load_i8 v2, v[2:3], off
global_load_i8 v3, v[4:5], off
v_sub_nc_u32_e32 v0, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, -2, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(1)
v_subrev_nc_u32_e32 v2, 48, v2
s_waitcnt vmcnt(0)
v_subrev_nc_u32_e32 v3, 48, v3
v_mul_i32_i24_e32 v2, v3, v2
global_atomic_add_u32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8multiplyiiPcS_Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8multiplyiiPcS_Pi, .Lfunc_end0-_Z8multiplyiiPcS_Pi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8multiplyiiPcS_Pi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8multiplyiiPcS_Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004651b_00000000-6_large_mutiply.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4103:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4103:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z8multiplyiiPcS_PiiiPcS_Pi
.type _Z33__device_stub__Z8multiplyiiPcS_PiiiPcS_Pi, @function
_Z33__device_stub__Z8multiplyiiPcS_PiiiPcS_Pi:
.LFB4125:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8multiplyiiPcS_Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4125:
.size _Z33__device_stub__Z8multiplyiiPcS_PiiiPcS_Pi, .-_Z33__device_stub__Z8multiplyiiPcS_PiiiPcS_Pi
.globl _Z8multiplyiiPcS_Pi
.type _Z8multiplyiiPcS_Pi, @function
_Z8multiplyiiPcS_Pi:
.LFB4126:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z8multiplyiiPcS_PiiiPcS_Pi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4126:
.size _Z8multiplyiiPcS_Pi, .-_Z8multiplyiiPcS_Pi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "%s"
.LC2:
.string ""
.text
.globl main
.type main, @function
main:
.LFB4100:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $1073741824, %edi
call _Znam@PLT
movq %rax, %r14
movl $1073741824, %edi
call _Znam@PLT
movq %rax, %r15
movq 8(%rbx), %rdi
leaq .LC0(%rip), %r13
movq %r13, %rsi
call fopen@PLT
movq %rax, %r12
movq %r14, %rdx
leaq .LC1(%rip), %rbp
movq %rbp, %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movq %r12, %rdi
call fclose@PLT
movq 16(%rbx), %rdi
movq %r13, %rsi
call fopen@PLT
movq %rax, %rbx
movq %r15, %rdx
movq %rbp, %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movq %rbx, %rdi
call fclose@PLT
movq %r14, 16(%rsp)
movq %r14, %rdi
call strlen@PLT
movq %rax, %r14
movl %eax, 40(%rsp)
movq %r15, 24(%rsp)
movq %r15, %rdi
call strlen@PLT
movq %rax, %r13
movl %eax, 44(%rsp)
leal (%rax,%r14), %r12d
leal 1(%r12), %eax
movl %eax, 36(%rsp)
movslq %eax, %rbx
movabsq $2305843009213693950, %rax
cmpq %rbx, %rax
jb .L12
leaq 0(,%rbx,4), %r15
movq %r15, %rdi
call _Znam@PLT
movq %rax, %rbp
movslq %r14d, %rax
leaq 56(%rsp), %rdi
movq %rax, (%rsp)
movq %rax, %rsi
call cudaMalloc@PLT
movslq %r13d, %rax
leaq 64(%rsp), %rdi
movq %rax, 8(%rsp)
movq %rax, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq (%rsp), %rdx
movq 16(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq 8(%rsp), %rdx
movq 24(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
addl $1, %r14d
movl %r14d, 92(%rsp)
addl $1, %r13d
movl %r13d, 96(%rsp)
movl $16, 80(%rsp)
movl $16, 84(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 92(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L13:
movl $2, %ecx
movq %r15, %rdx
movq 72(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
cmpl $0, 36(%rsp)
jle .L16
movq %rbp, %rdx
movl %r12d, %edi
leaq 4(%rbp,%rdi,4), %r8
.L17:
movl (%rdx), %ecx
movslq %ecx, %rax
imulq $1717986919, %rax, %rax
sarq $34, %rax
movl %ecx, %esi
sarl $31, %esi
subl %esi, %eax
addl %eax, 4(%rdx)
leal (%rax,%rax,4), %eax
addl %eax, %eax
subl %eax, %ecx
movl %ecx, (%rdx)
addq $4, %rdx
cmpq %r8, %rdx
jne .L17
movslq %r12d, %r12
subq %rdi, %r12
.L19:
cmpl $0, 0(%rbp,%rbx,4)
jne .L35
subq $1, %rbx
cmpq %r12, %rbx
jne .L19
.L16:
movl $0, %eax
.L20:
movslq %eax, %rdx
salq $2, %rdx
leaq 0(%rbp,%rdx), %rbx
leaq -4(%rbp,%rdx), %rbp
movl %eax, %eax
salq $2, %rax
subq %rax, %rbp
.L24:
movl (%rbx), %eax
leal 48(%rax), %edi
movq stdout(%rip), %rsi
call putc@PLT
subq $4, %rbx
cmpq %rbp, %rbx
jne .L24
.L21:
leaq .LC2(%rip), %rdi
call puts@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L36
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L15
call __stack_chk_fail@PLT
.L15:
call __cxa_throw_bad_array_new_length@PLT
.L34:
movq 72(%rsp), %r8
movq 64(%rsp), %rcx
movq 56(%rsp), %rdx
movl 44(%rsp), %esi
movl 40(%rsp), %edi
call _Z33__device_stub__Z8multiplyiiPcS_PiiiPcS_Pi
jmp .L13
.L35:
movl %ebx, %eax
cmpl $-1, %ebx
jne .L20
jmp .L21
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4100:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z8multiplyiiPcS_Pi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4128:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z8multiplyiiPcS_Pi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4128:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "large_mutiply.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z23__device_stub__multiplyiiPcS_Pi # -- Begin function _Z23__device_stub__multiplyiiPcS_Pi
.p2align 4, 0x90
.type _Z23__device_stub__multiplyiiPcS_Pi,@function
_Z23__device_stub__multiplyiiPcS_Pi: # @_Z23__device_stub__multiplyiiPcS_Pi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8multiplyiiPcS_Pi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__multiplyiiPcS_Pi, .Lfunc_end0-_Z23__device_stub__multiplyiiPcS_Pi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl $1073741824, %edi # imm = 0x40000000
callq _Znam
movq %rax, %r12
movl $1073741824, %edi # imm = 0x40000000
callq _Znam
movq %rax, %r15
movq %rax, 80(%rsp) # 8-byte Spill
movq 8(%rbx), %rdi
movl $.L.str, %esi
callq fopen
movq %rax, %r14
movl $.L.str.1, %esi
movq %rax, %rdi
movq %r12, %rdx
movq %r12, 72(%rsp) # 8-byte Spill
xorl %eax, %eax
callq __isoc23_fscanf
movq %r14, %rdi
callq fclose
movq 16(%rbx), %rdi
movl $.L.str, %esi
callq fopen
movq %rax, %rbx
movl $.L.str.1, %esi
movq %rax, %rdi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movq %rbx, %rdi
callq fclose
movq %r12, %rdi
callq strlen
movq %rax, %r14
movq %r15, %rdi
callq strlen
movq %rax, %r15
addl %r14d, %eax
leal 1(%r15,%r14), %r13d
movslq %r13d, %rbp
leaq (,%rbp,4), %rcx
movq %rcx, 40(%rsp) # 8-byte Spill
movl %eax, 12(%rsp) # 4-byte Spill
cmpl $-1, %eax
movq $-1, %rdi
cmovgeq %rcx, %rdi
callq _Znam
movq %rax, %rbx
movq %r14, 32(%rsp) # 8-byte Spill
movslq %r14d, %r12
leaq 64(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq %r15, %r14
shlq $32, %r14
movq %r15, 24(%rsp) # 8-byte Spill
movslq %r15d, %r15
leaq 56(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq 40(%rsp), %rsi # 8-byte Reload
callq hipMalloc
movq 64(%rsp), %rdi
movq 72(%rsp), %rsi # 8-byte Reload
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 56(%rsp), %rdi
movq 80(%rsp), %rsi # 8-byte Reload
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
incl %r12d
orq %r14, %r12
movabsq $4294967296, %rdi # imm = 0x100000000
addq %r12, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 64(%rsp), %rax
movq 56(%rsp), %rcx
movq 48(%rsp), %rdx
movq 32(%rsp), %rsi # 8-byte Reload
movl %esi, 20(%rsp)
movq 24(%rsp), %rsi # 8-byte Reload
movl %esi, 16(%rsp)
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 152(%rsp), %rax
movq %rax, 176(%rsp)
leaq 144(%rsp), %rax
movq %rax, 184(%rsp)
leaq 136(%rsp), %rax
movq %rax, 192(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z8multiplyiiPcS_Pi, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 48(%rsp), %rsi
movq %rbx, %rdi
movq 40(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
cmpl $0, 12(%rsp) # 4-byte Folded Reload
js .LBB1_5
# %bb.3: # %.lr.ph.preheader
movq 32(%rsp), %rax # 8-byte Reload
movq 24(%rsp), %rcx # 8-byte Reload
addl %ecx, %eax
incl %eax
movl (%rbx), %edx
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movslq %edx, %rsi
imulq $1717986919, %rsi, %rdi # imm = 0x66666667
movq %rdi, %rdx
shrq $63, %rdx
sarq $34, %rdi
addl %edx, %edi
movl 4(%rbx,%rcx,4), %edx
addl %edi, %edx
movl %edx, 4(%rbx,%rcx,4)
addl %edi, %edi
leal (%rdi,%rdi,4), %edi
subl %edi, %esi
movl %esi, (%rbx,%rcx,4)
leaq 1(%rcx), %rsi
movq %rsi, %rcx
cmpq %rsi, %rax
jne .LBB1_4
.LBB1_5: # %.preheader
testl %r13d, %r13d
je .LBB1_10
# %bb.6: # %.lr.ph61.preheader
decq %rbp
.p2align 4, 0x90
.LBB1_7: # %.lr.ph61
# =>This Inner Loop Header: Depth=1
cmpl $0, 4(%rbx,%rbp,4)
jne .LBB1_10
# %bb.8: # in Loop: Header=BB1_7 Depth=1
decl %r13d
movq %rbp, %rax
decq %rax
testl %ebp, %ebp
movq %rax, %rbp
jne .LBB1_7
# %bb.9:
xorl %r13d, %r13d
.LBB1_10: # %.critedge
cmpl $-1, %r13d
je .LBB1_13
# %bb.11: # %.lr.ph66.preheader
movslq %r13d, %r14
.p2align 4, 0x90
.LBB1_12: # %.lr.ph66
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %edi
addl $48, %edi
movq stdout(%rip), %rsi
callq putc
addq $-1, %r14
jb .LBB1_12
.LBB1_13: # %._crit_edge
movq stdout(%rip), %rsi
movl $10, %edi
callq putc
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8multiplyiiPcS_Pi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8multiplyiiPcS_Pi,@object # @_Z8multiplyiiPcS_Pi
.section .rodata,"a",@progbits
.globl _Z8multiplyiiPcS_Pi
.p2align 3, 0x0
_Z8multiplyiiPcS_Pi:
.quad _Z23__device_stub__multiplyiiPcS_Pi
.size _Z8multiplyiiPcS_Pi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%s"
.size .L.str.1, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8multiplyiiPcS_Pi"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__multiplyiiPcS_Pi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8multiplyiiPcS_Pi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <string.h>
#include <stdbool.h>
#include <cuda.h>
#include <cuda_runtime_api.h>
#define V 9
#define E 14
long int* get_graph_dim(char* filename)
{
FILE* file;
file = fopen(filename, "r");
if (file == NULL)
{
printf("Unable to read the CSR file: %s.", filename);
exit(1);
}
long int* dim = (long int*)malloc(2*sizeof(long int));
fscanf(file, "%ld %ld", &dim[0], &dim[1]);
return dim;
}
long int* read_csr(char* filename, long int v, long int e)
{
FILE* file;
file = fopen(filename, "r");
if (file == NULL)
{
printf("Unable to read the CSR file: %s.", filename);
exit(1);
}
long int* csr = (long int*)malloc((v+1+(2*e))*sizeof(long int));
fscanf(file, "%ld %ld", &v, &e);
long int i;
for(i=0; i<v+1; i++)
fscanf(file, "%ld", &csr[i]);
for(; i<v+1+2*e; i++)
fscanf(file, "%ld", &csr[i]);
return csr;
}
__global__ void between_centre(double* bc, long int* R, long int* C, long int *vert, long int *edge)
{
//long int V = *vert;
//long int E = *edge;
long int idx = threadIdx.x;
long int s = blockIdx.x;
__shared__ long int d[V], sigma[V];
double dep[V];
__shared__ long int P[V][V];
__shared__ long int p_top[V];
long int k, r;
//Initialize d and sigma
// for(k=idx; k<V; k+=blockDim.x)
// {
// if(k == s)
// {
// d[k] = 0;
// sigma[k] = 1;
// }
// else
// {
// d[k] = INT_MAX;
// sigma[k] = 0;
// }
//
// p_top[k] = 0;
//
// }
//
// __shared__ long int Q[V];
// __shared__ long int Q2[V];
// __shared__ long int Q_len;
// __shared__ long int Q2_len;
//
// __shared__ long int S[V];
// __shared__ long int s_top;
//
// if(idx == 0)
// {
// Q[0] = s;
// Q_len = 1;
// Q2_len = 0;
// s_top = 0;
// }
// __syncthreads();
//
// while(1)
// {
//
// for(k=idx; k<Q_len; k+=blockDim.x)
// {
// int v = Q[k];
//
// atomicAdd((int*)&s_top, 1);
// S[s_top] = v;
//
// for(r=R[v]; r<R[v+1]; r++)
// {
// long int w = C[r];
//
// if(atomicCAS((int*)&d[w],INT_MAX,(int)d[v]+1) == INT_MAX)
// {
// int t = atomicAdd((int*)&Q2_len,1);
// Q2[t] = w;
// }
//
// if(d[w] == (d[v]+1))
// {
// atomicAdd((int*)&sigma[w],sigma[v]);
// atomicAdd((int*)&p_top[w], 1);
// atomicAdd((int*)&P[w][p_top[w]-1], v);
// }
// }
// }
// __syncthreads();
//
// if(Q2_len == 0)
// break;
//
// else
// {
// for(k=idx; k<Q2_len; k+=blockDim.x)
// Q[k] = Q2[k];
//
// __syncthreads();
//
// if(idx == 0)
// {
// Q_len = Q2_len;
// Q2_len = 0;
// }
// __syncthreads();
// }
// }
//
// while(s_top!=0)
// {
// atomicAdd((int*)&s_top, -1);
// long int w = S[s_top];
//
// for(k = 0; k < P[w][p_top[w]-1]; k++)
// dep[k] += (double)(sigma[k] * (1 + dep[w]) / sigma[w]);
//
// if(w!=s)
// atomicAdd((float*)&bc[w], (float)dep[w]);
//
// __syncthreads();
// }
}
int main()
{
long int* dim;
dim = get_graph_dim("01.txt");
printf("Hello!\n");
long int v = dim[0], e = dim[1];
long int* csr;
csr = read_csr("01.txt", v, e);
printf("Holla!!\n");
long int *r, *c;
double *bc;
r = (long int*)malloc((v+1)*sizeof(long int));
c = (long int*)malloc(2*e*sizeof(long int));
bc = (double*)malloc(v*sizeof(double));
memcpy(r, csr, (v+1)*sizeof(long int));
memcpy(c, csr+v+1, 2*e*sizeof(long int));
free(csr);
long int *d_v, *d_e;
long int *d_r, *d_c;
double *d_bc;
printf("Sui!\n");
cudaMalloc((void**)&d_v, sizeof(long int));
cudaMalloc((void**)&d_e, sizeof(long int));
cudaMalloc((void**)&d_bc, v * sizeof(double));
cudaMalloc((void**)&d_r, (v+1) * sizeof(long int));
cudaMalloc((void**)&d_c, 2*e * sizeof(long int));
cudaMemcpy(d_v, &v, sizeof(long int), cudaMemcpyHostToDevice);
cudaMemcpy(d_e, &e, sizeof(long int), cudaMemcpyHostToDevice);
cudaMemcpy(d_r, r, (v+1)*sizeof(long int), cudaMemcpyHostToDevice);
cudaMemcpy(d_c, c, 2*e*sizeof(long int), cudaMemcpyHostToDevice);
printf("Namaskara!\n");
dim3 dimGrid(v);
dim3 dimBlock(1024);
cudaEvent_t start, stop;
float timer;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
between_centre<<<dimGrid, dimBlock>>>(d_bc, d_r, d_c, d_v, d_e);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&timer, start, stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaMemcpy(bc, d_bc, v*sizeof(double), cudaMemcpyDeviceToHost);
long int k;
for(k = 0; k < v; k++)
printf("%.2f ", bc[k]);
printf("\nElapsed Time: %lf\n", timer);
cudaFree(d_v);
cudaFree(d_e);
cudaFree(d_bc);
cudaFree(d_r);
cudaFree(d_c);
free(r);
free(c);
} | code for sm_80
Function : _Z14between_centrePdPlS0_S0_S0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <string.h>
#include <stdbool.h>
#include <cuda.h>
#include <cuda_runtime_api.h>
#define V 9
#define E 14
long int* get_graph_dim(char* filename)
{
FILE* file;
file = fopen(filename, "r");
if (file == NULL)
{
printf("Unable to read the CSR file: %s.", filename);
exit(1);
}
long int* dim = (long int*)malloc(2*sizeof(long int));
fscanf(file, "%ld %ld", &dim[0], &dim[1]);
return dim;
}
long int* read_csr(char* filename, long int v, long int e)
{
FILE* file;
file = fopen(filename, "r");
if (file == NULL)
{
printf("Unable to read the CSR file: %s.", filename);
exit(1);
}
long int* csr = (long int*)malloc((v+1+(2*e))*sizeof(long int));
fscanf(file, "%ld %ld", &v, &e);
long int i;
for(i=0; i<v+1; i++)
fscanf(file, "%ld", &csr[i]);
for(; i<v+1+2*e; i++)
fscanf(file, "%ld", &csr[i]);
return csr;
}
__global__ void between_centre(double* bc, long int* R, long int* C, long int *vert, long int *edge)
{
//long int V = *vert;
//long int E = *edge;
long int idx = threadIdx.x;
long int s = blockIdx.x;
__shared__ long int d[V], sigma[V];
double dep[V];
__shared__ long int P[V][V];
__shared__ long int p_top[V];
long int k, r;
//Initialize d and sigma
// for(k=idx; k<V; k+=blockDim.x)
// {
// if(k == s)
// {
// d[k] = 0;
// sigma[k] = 1;
// }
// else
// {
// d[k] = INT_MAX;
// sigma[k] = 0;
// }
//
// p_top[k] = 0;
//
// }
//
// __shared__ long int Q[V];
// __shared__ long int Q2[V];
// __shared__ long int Q_len;
// __shared__ long int Q2_len;
//
// __shared__ long int S[V];
// __shared__ long int s_top;
//
// if(idx == 0)
// {
// Q[0] = s;
// Q_len = 1;
// Q2_len = 0;
// s_top = 0;
// }
// __syncthreads();
//
// while(1)
// {
//
// for(k=idx; k<Q_len; k+=blockDim.x)
// {
// int v = Q[k];
//
// atomicAdd((int*)&s_top, 1);
// S[s_top] = v;
//
// for(r=R[v]; r<R[v+1]; r++)
// {
// long int w = C[r];
//
// if(atomicCAS((int*)&d[w],INT_MAX,(int)d[v]+1) == INT_MAX)
// {
// int t = atomicAdd((int*)&Q2_len,1);
// Q2[t] = w;
// }
//
// if(d[w] == (d[v]+1))
// {
// atomicAdd((int*)&sigma[w],sigma[v]);
// atomicAdd((int*)&p_top[w], 1);
// atomicAdd((int*)&P[w][p_top[w]-1], v);
// }
// }
// }
// __syncthreads();
//
// if(Q2_len == 0)
// break;
//
// else
// {
// for(k=idx; k<Q2_len; k+=blockDim.x)
// Q[k] = Q2[k];
//
// __syncthreads();
//
// if(idx == 0)
// {
// Q_len = Q2_len;
// Q2_len = 0;
// }
// __syncthreads();
// }
// }
//
// while(s_top!=0)
// {
// atomicAdd((int*)&s_top, -1);
// long int w = S[s_top];
//
// for(k = 0; k < P[w][p_top[w]-1]; k++)
// dep[k] += (double)(sigma[k] * (1 + dep[w]) / sigma[w]);
//
// if(w!=s)
// atomicAdd((float*)&bc[w], (float)dep[w]);
//
// __syncthreads();
// }
}
int main()
{
long int* dim;
dim = get_graph_dim("01.txt");
printf("Hello!\n");
long int v = dim[0], e = dim[1];
long int* csr;
csr = read_csr("01.txt", v, e);
printf("Holla!!\n");
long int *r, *c;
double *bc;
r = (long int*)malloc((v+1)*sizeof(long int));
c = (long int*)malloc(2*e*sizeof(long int));
bc = (double*)malloc(v*sizeof(double));
memcpy(r, csr, (v+1)*sizeof(long int));
memcpy(c, csr+v+1, 2*e*sizeof(long int));
free(csr);
long int *d_v, *d_e;
long int *d_r, *d_c;
double *d_bc;
printf("Sui!\n");
cudaMalloc((void**)&d_v, sizeof(long int));
cudaMalloc((void**)&d_e, sizeof(long int));
cudaMalloc((void**)&d_bc, v * sizeof(double));
cudaMalloc((void**)&d_r, (v+1) * sizeof(long int));
cudaMalloc((void**)&d_c, 2*e * sizeof(long int));
cudaMemcpy(d_v, &v, sizeof(long int), cudaMemcpyHostToDevice);
cudaMemcpy(d_e, &e, sizeof(long int), cudaMemcpyHostToDevice);
cudaMemcpy(d_r, r, (v+1)*sizeof(long int), cudaMemcpyHostToDevice);
cudaMemcpy(d_c, c, 2*e*sizeof(long int), cudaMemcpyHostToDevice);
printf("Namaskara!\n");
dim3 dimGrid(v);
dim3 dimBlock(1024);
cudaEvent_t start, stop;
float timer;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
between_centre<<<dimGrid, dimBlock>>>(d_bc, d_r, d_c, d_v, d_e);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&timer, start, stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaMemcpy(bc, d_bc, v*sizeof(double), cudaMemcpyDeviceToHost);
long int k;
for(k = 0; k < v; k++)
printf("%.2f ", bc[k]);
printf("\nElapsed Time: %lf\n", timer);
cudaFree(d_v);
cudaFree(d_e);
cudaFree(d_bc);
cudaFree(d_r);
cudaFree(d_c);
free(r);
free(c);
} | .file "tmpxft_0009d357_00000000-6_bc_vert_front.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Unable to read the CSR file: %s."
.section .rodata.str1.1
.LC2:
.string "%ld %ld"
.text
.globl _Z13get_graph_dimPc
.type _Z13get_graph_dimPc, @function
_Z13get_graph_dimPc:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
leaq .LC0(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L6
movq %rax, %rbp
movl $16, %edi
call malloc@PLT
movq %rax, %rbx
leaq 8(%rax), %rcx
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movq %rbx, %rax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movq %rbx, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z13get_graph_dimPc, .-_Z13get_graph_dimPc
.section .rodata.str1.1
.LC3:
.string "%ld"
.text
.globl _Z8read_csrPcll
.type _Z8read_csrPcll, @function
_Z8read_csrPcll:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $16, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbx
movq %rsi, 8(%rsp)
movq %rdx, (%rsp)
leaq .LC0(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L17
movq %rax, %r12
movq 8(%rsp), %rax
movq (%rsp), %rdx
leaq 1(%rax,%rdx,2), %rdi
salq $3, %rdi
call malloc@PLT
movq %rax, %r13
movq %rsp, %rcx
leaq 8(%rsp), %rdx
leaq .LC2(%rip), %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpq $0, 8(%rsp)
js .L13
movq %r13, %rbp
movl $0, %ebx
leaq .LC3(%rip), %r14
.L10:
movq %rbp, %rdx
movq %r14, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $1, %rbx
addq $8, %rbp
cmpq %rbx, 8(%rsp)
jge .L10
.L9:
movq 8(%rsp), %rax
movq (%rsp), %rdx
leaq 1(%rax,%rdx,2), %rax
cmpq %rbx, %rax
jle .L7
leaq 0(%r13,%rbx,8), %rbp
leaq .LC3(%rip), %r14
.L12:
movq %rbp, %rdx
movq %r14, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $1, %rbx
addq $8, %rbp
movq 8(%rsp), %rax
movq (%rsp), %rdx
leaq 1(%rax,%rdx,2), %rax
cmpq %rbx, %rax
jg .L12
.L7:
movq %r13, %rax
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq %rbx, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L13:
movl $0, %ebx
jmp .L9
.cfi_endproc
.LFE2058:
.size _Z8read_csrPcll, .-_Z8read_csrPcll
.globl _Z45__device_stub__Z14between_centrePdPlS0_S0_S0_PdPlS0_S0_S0_
.type _Z45__device_stub__Z14between_centrePdPlS0_S0_S0_PdPlS0_S0_S0_, @function
_Z45__device_stub__Z14between_centrePdPlS0_S0_S0_PdPlS0_S0_S0_:
.LFB2084:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L22
.L18:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L23
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z14between_centrePdPlS0_S0_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L18
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z45__device_stub__Z14between_centrePdPlS0_S0_S0_PdPlS0_S0_S0_, .-_Z45__device_stub__Z14between_centrePdPlS0_S0_S0_PdPlS0_S0_S0_
.globl _Z14between_centrePdPlS0_S0_S0_
.type _Z14between_centrePdPlS0_S0_S0_, @function
_Z14between_centrePdPlS0_S0_S0_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z14between_centrePdPlS0_S0_S0_PdPlS0_S0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z14between_centrePdPlS0_S0_S0_, .-_Z14between_centrePdPlS0_S0_S0_
.section .rodata.str1.1
.LC4:
.string "01.txt"
.LC5:
.string "Hello!\n"
.LC6:
.string "Holla!!\n"
.LC7:
.string "Sui!\n"
.LC8:
.string "Namaskara!\n"
.LC9:
.string "%.2f "
.LC10:
.string "\nElapsed Time: %lf\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq .LC4(%rip), %rbp
movq %rbp, %rdi
call _Z13get_graph_dimPc
movq %rax, %rbx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rbx), %rsi
movq %rsi, 8(%rsp)
movq 8(%rbx), %rdx
movq %rdx, 16(%rsp)
movq %rbp, %rdi
call _Z8read_csrPcll
movq %rax, %r12
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rax
leaq 8(,%rax,8), %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq 16(%rsp), %r15
salq $4, %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, %r13
leaq -8(%rbx), %rdi
call malloc@PLT
movq %rax, %rbp
movq %rbx, %rcx
movq %rbx, %rdx
movq %r12, %rsi
movq %r14, %rdi
call __memcpy_chk@PLT
leaq (%r12,%rbx), %rsi
movq %r15, %rcx
movq %r15, %rdx
movq %r13, %rdi
call __memcpy_chk@PLT
movq %r12, %rdi
call free@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 24(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
movq 8(%rsp), %rax
leaq 0(,%rax,8), %rsi
leaq 56(%rsp), %rdi
call cudaMalloc@PLT
movq 8(%rsp), %rax
leaq 8(,%rax,8), %rsi
leaq 40(%rsp), %rdi
call cudaMalloc@PLT
movq 16(%rsp), %rsi
salq $4, %rsi
leaq 48(%rsp), %rdi
call cudaMalloc@PLT
leaq 8(%rsp), %rsi
movl $1, %ecx
movl $8, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rsi
movl $1, %ecx
movl $8, %edx
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rax
leaq 8(,%rax,8), %rdx
movl $1, %ecx
movq %r14, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movq 16(%rsp), %rdx
salq $4, %rdx
movl $1, %ecx
movq %r13, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rax
movl %eax, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1024, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movl 100(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movq 80(%rsp), %rdi
movl 88(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L27:
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
movq 72(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 64(%rsp), %rdi
call cudaEventDestroy@PLT
movq 72(%rsp), %rdi
call cudaEventDestroy@PLT
movq 8(%rsp), %rax
leaq 0(,%rax,8), %rdx
movl $2, %ecx
movq 56(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
cmpq $0, 8(%rsp)
jle .L28
movl $0, %ebx
leaq .LC9(%rip), %r12
.L29:
movsd 0(%rbp,%rbx,8), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %rbx, 8(%rsp)
jg .L29
.L28:
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L34
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
movq 32(%rsp), %r8
movq 24(%rsp), %rcx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z45__device_stub__Z14between_centrePdPlS0_S0_S0_PdPlS0_S0_S0_
jmp .L27
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC11:
.string "_Z14between_centrePdPlS0_S0_S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z14between_centrePdPlS0_S0_S0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <string.h>
#include <stdbool.h>
#include <cuda.h>
#include <cuda_runtime_api.h>
#define V 9
#define E 14
long int* get_graph_dim(char* filename)
{
FILE* file;
file = fopen(filename, "r");
if (file == NULL)
{
printf("Unable to read the CSR file: %s.", filename);
exit(1);
}
long int* dim = (long int*)malloc(2*sizeof(long int));
fscanf(file, "%ld %ld", &dim[0], &dim[1]);
return dim;
}
long int* read_csr(char* filename, long int v, long int e)
{
FILE* file;
file = fopen(filename, "r");
if (file == NULL)
{
printf("Unable to read the CSR file: %s.", filename);
exit(1);
}
long int* csr = (long int*)malloc((v+1+(2*e))*sizeof(long int));
fscanf(file, "%ld %ld", &v, &e);
long int i;
for(i=0; i<v+1; i++)
fscanf(file, "%ld", &csr[i]);
for(; i<v+1+2*e; i++)
fscanf(file, "%ld", &csr[i]);
return csr;
}
__global__ void between_centre(double* bc, long int* R, long int* C, long int *vert, long int *edge)
{
//long int V = *vert;
//long int E = *edge;
long int idx = threadIdx.x;
long int s = blockIdx.x;
__shared__ long int d[V], sigma[V];
double dep[V];
__shared__ long int P[V][V];
__shared__ long int p_top[V];
long int k, r;
//Initialize d and sigma
// for(k=idx; k<V; k+=blockDim.x)
// {
// if(k == s)
// {
// d[k] = 0;
// sigma[k] = 1;
// }
// else
// {
// d[k] = INT_MAX;
// sigma[k] = 0;
// }
//
// p_top[k] = 0;
//
// }
//
// __shared__ long int Q[V];
// __shared__ long int Q2[V];
// __shared__ long int Q_len;
// __shared__ long int Q2_len;
//
// __shared__ long int S[V];
// __shared__ long int s_top;
//
// if(idx == 0)
// {
// Q[0] = s;
// Q_len = 1;
// Q2_len = 0;
// s_top = 0;
// }
// __syncthreads();
//
// while(1)
// {
//
// for(k=idx; k<Q_len; k+=blockDim.x)
// {
// int v = Q[k];
//
// atomicAdd((int*)&s_top, 1);
// S[s_top] = v;
//
// for(r=R[v]; r<R[v+1]; r++)
// {
// long int w = C[r];
//
// if(atomicCAS((int*)&d[w],INT_MAX,(int)d[v]+1) == INT_MAX)
// {
// int t = atomicAdd((int*)&Q2_len,1);
// Q2[t] = w;
// }
//
// if(d[w] == (d[v]+1))
// {
// atomicAdd((int*)&sigma[w],sigma[v]);
// atomicAdd((int*)&p_top[w], 1);
// atomicAdd((int*)&P[w][p_top[w]-1], v);
// }
// }
// }
// __syncthreads();
//
// if(Q2_len == 0)
// break;
//
// else
// {
// for(k=idx; k<Q2_len; k+=blockDim.x)
// Q[k] = Q2[k];
//
// __syncthreads();
//
// if(idx == 0)
// {
// Q_len = Q2_len;
// Q2_len = 0;
// }
// __syncthreads();
// }
// }
//
// while(s_top!=0)
// {
// atomicAdd((int*)&s_top, -1);
// long int w = S[s_top];
//
// for(k = 0; k < P[w][p_top[w]-1]; k++)
// dep[k] += (double)(sigma[k] * (1 + dep[w]) / sigma[w]);
//
// if(w!=s)
// atomicAdd((float*)&bc[w], (float)dep[w]);
//
// __syncthreads();
// }
}
int main()
{
long int* dim;
dim = get_graph_dim("01.txt");
printf("Hello!\n");
long int v = dim[0], e = dim[1];
long int* csr;
csr = read_csr("01.txt", v, e);
printf("Holla!!\n");
long int *r, *c;
double *bc;
r = (long int*)malloc((v+1)*sizeof(long int));
c = (long int*)malloc(2*e*sizeof(long int));
bc = (double*)malloc(v*sizeof(double));
memcpy(r, csr, (v+1)*sizeof(long int));
memcpy(c, csr+v+1, 2*e*sizeof(long int));
free(csr);
long int *d_v, *d_e;
long int *d_r, *d_c;
double *d_bc;
printf("Sui!\n");
cudaMalloc((void**)&d_v, sizeof(long int));
cudaMalloc((void**)&d_e, sizeof(long int));
cudaMalloc((void**)&d_bc, v * sizeof(double));
cudaMalloc((void**)&d_r, (v+1) * sizeof(long int));
cudaMalloc((void**)&d_c, 2*e * sizeof(long int));
cudaMemcpy(d_v, &v, sizeof(long int), cudaMemcpyHostToDevice);
cudaMemcpy(d_e, &e, sizeof(long int), cudaMemcpyHostToDevice);
cudaMemcpy(d_r, r, (v+1)*sizeof(long int), cudaMemcpyHostToDevice);
cudaMemcpy(d_c, c, 2*e*sizeof(long int), cudaMemcpyHostToDevice);
printf("Namaskara!\n");
dim3 dimGrid(v);
dim3 dimBlock(1024);
cudaEvent_t start, stop;
float timer;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
between_centre<<<dimGrid, dimBlock>>>(d_bc, d_r, d_c, d_v, d_e);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&timer, start, stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaMemcpy(bc, d_bc, v*sizeof(double), cudaMemcpyDeviceToHost);
long int k;
for(k = 0; k < v; k++)
printf("%.2f ", bc[k]);
printf("\nElapsed Time: %lf\n", timer);
cudaFree(d_v);
cudaFree(d_e);
cudaFree(d_bc);
cudaFree(d_r);
cudaFree(d_c);
free(r);
free(c);
} | #include <stdio.h>
#include <string.h>
#include <stdbool.h>
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#define V 9
#define E 14
long int* get_graph_dim(char* filename)
{
FILE* file;
file = fopen(filename, "r");
if (file == NULL)
{
printf("Unable to read the CSR file: %s.", filename);
exit(1);
}
long int* dim = (long int*)malloc(2*sizeof(long int));
fscanf(file, "%ld %ld", &dim[0], &dim[1]);
return dim;
}
long int* read_csr(char* filename, long int v, long int e)
{
FILE* file;
file = fopen(filename, "r");
if (file == NULL)
{
printf("Unable to read the CSR file: %s.", filename);
exit(1);
}
long int* csr = (long int*)malloc((v+1+(2*e))*sizeof(long int));
fscanf(file, "%ld %ld", &v, &e);
long int i;
for(i=0; i<v+1; i++)
fscanf(file, "%ld", &csr[i]);
for(; i<v+1+2*e; i++)
fscanf(file, "%ld", &csr[i]);
return csr;
}
__global__ void between_centre(double* bc, long int* R, long int* C, long int *vert, long int *edge)
{
//long int V = *vert;
//long int E = *edge;
long int idx = threadIdx.x;
long int s = blockIdx.x;
__shared__ long int d[V], sigma[V];
double dep[V];
__shared__ long int P[V][V];
__shared__ long int p_top[V];
long int k, r;
//Initialize d and sigma
// for(k=idx; k<V; k+=blockDim.x)
// {
// if(k == s)
// {
// d[k] = 0;
// sigma[k] = 1;
// }
// else
// {
// d[k] = INT_MAX;
// sigma[k] = 0;
// }
//
// p_top[k] = 0;
//
// }
//
// __shared__ long int Q[V];
// __shared__ long int Q2[V];
// __shared__ long int Q_len;
// __shared__ long int Q2_len;
//
// __shared__ long int S[V];
// __shared__ long int s_top;
//
// if(idx == 0)
// {
// Q[0] = s;
// Q_len = 1;
// Q2_len = 0;
// s_top = 0;
// }
// __syncthreads();
//
// while(1)
// {
//
// for(k=idx; k<Q_len; k+=blockDim.x)
// {
// int v = Q[k];
//
// atomicAdd((int*)&s_top, 1);
// S[s_top] = v;
//
// for(r=R[v]; r<R[v+1]; r++)
// {
// long int w = C[r];
//
// if(atomicCAS((int*)&d[w],INT_MAX,(int)d[v]+1) == INT_MAX)
// {
// int t = atomicAdd((int*)&Q2_len,1);
// Q2[t] = w;
// }
//
// if(d[w] == (d[v]+1))
// {
// atomicAdd((int*)&sigma[w],sigma[v]);
// atomicAdd((int*)&p_top[w], 1);
// atomicAdd((int*)&P[w][p_top[w]-1], v);
// }
// }
// }
// __syncthreads();
//
// if(Q2_len == 0)
// break;
//
// else
// {
// for(k=idx; k<Q2_len; k+=blockDim.x)
// Q[k] = Q2[k];
//
// __syncthreads();
//
// if(idx == 0)
// {
// Q_len = Q2_len;
// Q2_len = 0;
// }
// __syncthreads();
// }
// }
//
// while(s_top!=0)
// {
// atomicAdd((int*)&s_top, -1);
// long int w = S[s_top];
//
// for(k = 0; k < P[w][p_top[w]-1]; k++)
// dep[k] += (double)(sigma[k] * (1 + dep[w]) / sigma[w]);
//
// if(w!=s)
// atomicAdd((float*)&bc[w], (float)dep[w]);
//
// __syncthreads();
// }
}
int main()
{
long int* dim;
dim = get_graph_dim("01.txt");
printf("Hello!\n");
long int v = dim[0], e = dim[1];
long int* csr;
csr = read_csr("01.txt", v, e);
printf("Holla!!\n");
long int *r, *c;
double *bc;
r = (long int*)malloc((v+1)*sizeof(long int));
c = (long int*)malloc(2*e*sizeof(long int));
bc = (double*)malloc(v*sizeof(double));
memcpy(r, csr, (v+1)*sizeof(long int));
memcpy(c, csr+v+1, 2*e*sizeof(long int));
free(csr);
long int *d_v, *d_e;
long int *d_r, *d_c;
double *d_bc;
printf("Sui!\n");
hipMalloc((void**)&d_v, sizeof(long int));
hipMalloc((void**)&d_e, sizeof(long int));
hipMalloc((void**)&d_bc, v * sizeof(double));
hipMalloc((void**)&d_r, (v+1) * sizeof(long int));
hipMalloc((void**)&d_c, 2*e * sizeof(long int));
hipMemcpy(d_v, &v, sizeof(long int), hipMemcpyHostToDevice);
hipMemcpy(d_e, &e, sizeof(long int), hipMemcpyHostToDevice);
hipMemcpy(d_r, r, (v+1)*sizeof(long int), hipMemcpyHostToDevice);
hipMemcpy(d_c, c, 2*e*sizeof(long int), hipMemcpyHostToDevice);
printf("Namaskara!\n");
dim3 dimGrid(v);
dim3 dimBlock(1024);
hipEvent_t start, stop;
float timer;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
between_centre<<<dimGrid, dimBlock>>>(d_bc, d_r, d_c, d_v, d_e);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&timer, start, stop);
hipEventDestroy(start);
hipEventDestroy(stop);
hipMemcpy(bc, d_bc, v*sizeof(double), hipMemcpyDeviceToHost);
long int k;
for(k = 0; k < v; k++)
printf("%.2f ", bc[k]);
printf("\nElapsed Time: %lf\n", timer);
hipFree(d_v);
hipFree(d_e);
hipFree(d_bc);
hipFree(d_r);
hipFree(d_c);
free(r);
free(c);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <string.h>
#include <stdbool.h>
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#define V 9
#define E 14
long int* get_graph_dim(char* filename)
{
FILE* file;
file = fopen(filename, "r");
if (file == NULL)
{
printf("Unable to read the CSR file: %s.", filename);
exit(1);
}
long int* dim = (long int*)malloc(2*sizeof(long int));
fscanf(file, "%ld %ld", &dim[0], &dim[1]);
return dim;
}
long int* read_csr(char* filename, long int v, long int e)
{
FILE* file;
file = fopen(filename, "r");
if (file == NULL)
{
printf("Unable to read the CSR file: %s.", filename);
exit(1);
}
long int* csr = (long int*)malloc((v+1+(2*e))*sizeof(long int));
fscanf(file, "%ld %ld", &v, &e);
long int i;
for(i=0; i<v+1; i++)
fscanf(file, "%ld", &csr[i]);
for(; i<v+1+2*e; i++)
fscanf(file, "%ld", &csr[i]);
return csr;
}
__global__ void between_centre(double* bc, long int* R, long int* C, long int *vert, long int *edge)
{
//long int V = *vert;
//long int E = *edge;
long int idx = threadIdx.x;
long int s = blockIdx.x;
__shared__ long int d[V], sigma[V];
double dep[V];
__shared__ long int P[V][V];
__shared__ long int p_top[V];
long int k, r;
//Initialize d and sigma
// for(k=idx; k<V; k+=blockDim.x)
// {
// if(k == s)
// {
// d[k] = 0;
// sigma[k] = 1;
// }
// else
// {
// d[k] = INT_MAX;
// sigma[k] = 0;
// }
//
// p_top[k] = 0;
//
// }
//
// __shared__ long int Q[V];
// __shared__ long int Q2[V];
// __shared__ long int Q_len;
// __shared__ long int Q2_len;
//
// __shared__ long int S[V];
// __shared__ long int s_top;
//
// if(idx == 0)
// {
// Q[0] = s;
// Q_len = 1;
// Q2_len = 0;
// s_top = 0;
// }
// __syncthreads();
//
// while(1)
// {
//
// for(k=idx; k<Q_len; k+=blockDim.x)
// {
// int v = Q[k];
//
// atomicAdd((int*)&s_top, 1);
// S[s_top] = v;
//
// for(r=R[v]; r<R[v+1]; r++)
// {
// long int w = C[r];
//
// if(atomicCAS((int*)&d[w],INT_MAX,(int)d[v]+1) == INT_MAX)
// {
// int t = atomicAdd((int*)&Q2_len,1);
// Q2[t] = w;
// }
//
// if(d[w] == (d[v]+1))
// {
// atomicAdd((int*)&sigma[w],sigma[v]);
// atomicAdd((int*)&p_top[w], 1);
// atomicAdd((int*)&P[w][p_top[w]-1], v);
// }
// }
// }
// __syncthreads();
//
// if(Q2_len == 0)
// break;
//
// else
// {
// for(k=idx; k<Q2_len; k+=blockDim.x)
// Q[k] = Q2[k];
//
// __syncthreads();
//
// if(idx == 0)
// {
// Q_len = Q2_len;
// Q2_len = 0;
// }
// __syncthreads();
// }
// }
//
// while(s_top!=0)
// {
// atomicAdd((int*)&s_top, -1);
// long int w = S[s_top];
//
// for(k = 0; k < P[w][p_top[w]-1]; k++)
// dep[k] += (double)(sigma[k] * (1 + dep[w]) / sigma[w]);
//
// if(w!=s)
// atomicAdd((float*)&bc[w], (float)dep[w]);
//
// __syncthreads();
// }
}
int main()
{
long int* dim;
dim = get_graph_dim("01.txt");
printf("Hello!\n");
long int v = dim[0], e = dim[1];
long int* csr;
csr = read_csr("01.txt", v, e);
printf("Holla!!\n");
long int *r, *c;
double *bc;
r = (long int*)malloc((v+1)*sizeof(long int));
c = (long int*)malloc(2*e*sizeof(long int));
bc = (double*)malloc(v*sizeof(double));
memcpy(r, csr, (v+1)*sizeof(long int));
memcpy(c, csr+v+1, 2*e*sizeof(long int));
free(csr);
long int *d_v, *d_e;
long int *d_r, *d_c;
double *d_bc;
printf("Sui!\n");
hipMalloc((void**)&d_v, sizeof(long int));
hipMalloc((void**)&d_e, sizeof(long int));
hipMalloc((void**)&d_bc, v * sizeof(double));
hipMalloc((void**)&d_r, (v+1) * sizeof(long int));
hipMalloc((void**)&d_c, 2*e * sizeof(long int));
hipMemcpy(d_v, &v, sizeof(long int), hipMemcpyHostToDevice);
hipMemcpy(d_e, &e, sizeof(long int), hipMemcpyHostToDevice);
hipMemcpy(d_r, r, (v+1)*sizeof(long int), hipMemcpyHostToDevice);
hipMemcpy(d_c, c, 2*e*sizeof(long int), hipMemcpyHostToDevice);
printf("Namaskara!\n");
dim3 dimGrid(v);
dim3 dimBlock(1024);
hipEvent_t start, stop;
float timer;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
between_centre<<<dimGrid, dimBlock>>>(d_bc, d_r, d_c, d_v, d_e);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&timer, start, stop);
hipEventDestroy(start);
hipEventDestroy(stop);
hipMemcpy(bc, d_bc, v*sizeof(double), hipMemcpyDeviceToHost);
long int k;
for(k = 0; k < v; k++)
printf("%.2f ", bc[k]);
printf("\nElapsed Time: %lf\n", timer);
hipFree(d_v);
hipFree(d_e);
hipFree(d_bc);
hipFree(d_r);
hipFree(d_c);
free(r);
free(c);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14between_centrePdPlS0_S0_S0_
.globl _Z14between_centrePdPlS0_S0_S0_
.p2align 8
.type _Z14between_centrePdPlS0_S0_S0_,@function
_Z14between_centrePdPlS0_S0_S0_:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14between_centrePdPlS0_S0_S0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14between_centrePdPlS0_S0_S0_, .Lfunc_end0-_Z14between_centrePdPlS0_S0_S0_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14between_centrePdPlS0_S0_S0_
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z14between_centrePdPlS0_S0_S0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <string.h>
#include <stdbool.h>
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#define V 9
#define E 14
long int* get_graph_dim(char* filename)
{
FILE* file;
file = fopen(filename, "r");
if (file == NULL)
{
printf("Unable to read the CSR file: %s.", filename);
exit(1);
}
long int* dim = (long int*)malloc(2*sizeof(long int));
fscanf(file, "%ld %ld", &dim[0], &dim[1]);
return dim;
}
long int* read_csr(char* filename, long int v, long int e)
{
FILE* file;
file = fopen(filename, "r");
if (file == NULL)
{
printf("Unable to read the CSR file: %s.", filename);
exit(1);
}
long int* csr = (long int*)malloc((v+1+(2*e))*sizeof(long int));
fscanf(file, "%ld %ld", &v, &e);
long int i;
for(i=0; i<v+1; i++)
fscanf(file, "%ld", &csr[i]);
for(; i<v+1+2*e; i++)
fscanf(file, "%ld", &csr[i]);
return csr;
}
__global__ void between_centre(double* bc, long int* R, long int* C, long int *vert, long int *edge)
{
//long int V = *vert;
//long int E = *edge;
long int idx = threadIdx.x;
long int s = blockIdx.x;
__shared__ long int d[V], sigma[V];
double dep[V];
__shared__ long int P[V][V];
__shared__ long int p_top[V];
long int k, r;
//Initialize d and sigma
// for(k=idx; k<V; k+=blockDim.x)
// {
// if(k == s)
// {
// d[k] = 0;
// sigma[k] = 1;
// }
// else
// {
// d[k] = INT_MAX;
// sigma[k] = 0;
// }
//
// p_top[k] = 0;
//
// }
//
// __shared__ long int Q[V];
// __shared__ long int Q2[V];
// __shared__ long int Q_len;
// __shared__ long int Q2_len;
//
// __shared__ long int S[V];
// __shared__ long int s_top;
//
// if(idx == 0)
// {
// Q[0] = s;
// Q_len = 1;
// Q2_len = 0;
// s_top = 0;
// }
// __syncthreads();
//
// while(1)
// {
//
// for(k=idx; k<Q_len; k+=blockDim.x)
// {
// int v = Q[k];
//
// atomicAdd((int*)&s_top, 1);
// S[s_top] = v;
//
// for(r=R[v]; r<R[v+1]; r++)
// {
// long int w = C[r];
//
// if(atomicCAS((int*)&d[w],INT_MAX,(int)d[v]+1) == INT_MAX)
// {
// int t = atomicAdd((int*)&Q2_len,1);
// Q2[t] = w;
// }
//
// if(d[w] == (d[v]+1))
// {
// atomicAdd((int*)&sigma[w],sigma[v]);
// atomicAdd((int*)&p_top[w], 1);
// atomicAdd((int*)&P[w][p_top[w]-1], v);
// }
// }
// }
// __syncthreads();
//
// if(Q2_len == 0)
// break;
//
// else
// {
// for(k=idx; k<Q2_len; k+=blockDim.x)
// Q[k] = Q2[k];
//
// __syncthreads();
//
// if(idx == 0)
// {
// Q_len = Q2_len;
// Q2_len = 0;
// }
// __syncthreads();
// }
// }
//
// while(s_top!=0)
// {
// atomicAdd((int*)&s_top, -1);
// long int w = S[s_top];
//
// for(k = 0; k < P[w][p_top[w]-1]; k++)
// dep[k] += (double)(sigma[k] * (1 + dep[w]) / sigma[w]);
//
// if(w!=s)
// atomicAdd((float*)&bc[w], (float)dep[w]);
//
// __syncthreads();
// }
}
int main()
{
long int* dim;
dim = get_graph_dim("01.txt");
printf("Hello!\n");
long int v = dim[0], e = dim[1];
long int* csr;
csr = read_csr("01.txt", v, e);
printf("Holla!!\n");
long int *r, *c;
double *bc;
r = (long int*)malloc((v+1)*sizeof(long int));
c = (long int*)malloc(2*e*sizeof(long int));
bc = (double*)malloc(v*sizeof(double));
memcpy(r, csr, (v+1)*sizeof(long int));
memcpy(c, csr+v+1, 2*e*sizeof(long int));
free(csr);
long int *d_v, *d_e;
long int *d_r, *d_c;
double *d_bc;
printf("Sui!\n");
hipMalloc((void**)&d_v, sizeof(long int));
hipMalloc((void**)&d_e, sizeof(long int));
hipMalloc((void**)&d_bc, v * sizeof(double));
hipMalloc((void**)&d_r, (v+1) * sizeof(long int));
hipMalloc((void**)&d_c, 2*e * sizeof(long int));
hipMemcpy(d_v, &v, sizeof(long int), hipMemcpyHostToDevice);
hipMemcpy(d_e, &e, sizeof(long int), hipMemcpyHostToDevice);
hipMemcpy(d_r, r, (v+1)*sizeof(long int), hipMemcpyHostToDevice);
hipMemcpy(d_c, c, 2*e*sizeof(long int), hipMemcpyHostToDevice);
printf("Namaskara!\n");
dim3 dimGrid(v);
dim3 dimBlock(1024);
hipEvent_t start, stop;
float timer;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
between_centre<<<dimGrid, dimBlock>>>(d_bc, d_r, d_c, d_v, d_e);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&timer, start, stop);
hipEventDestroy(start);
hipEventDestroy(stop);
hipMemcpy(bc, d_bc, v*sizeof(double), hipMemcpyDeviceToHost);
long int k;
for(k = 0; k < v; k++)
printf("%.2f ", bc[k]);
printf("\nElapsed Time: %lf\n", timer);
hipFree(d_v);
hipFree(d_e);
hipFree(d_bc);
hipFree(d_r);
hipFree(d_c);
free(r);
free(c);
} | .text
.file "bc_vert_front.hip"
.globl _Z13get_graph_dimPc # -- Begin function _Z13get_graph_dimPc
.p2align 4, 0x90
.type _Z13get_graph_dimPc,@function
_Z13get_graph_dimPc: # @_Z13get_graph_dimPc
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
movl $.L.str, %esi
callq fopen
testq %rax, %rax
je .LBB0_2
# %bb.1:
movq %rax, %r14
movl $16, %edi
callq malloc
movq %rax, %rbx
leaq 8(%rax), %rcx
movl $.L.str.2, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movq %rbx, %rax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 32
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z13get_graph_dimPc, .Lfunc_end0-_Z13get_graph_dimPc
.cfi_endproc
# -- End function
.globl _Z8read_csrPcll # -- Begin function _Z8read_csrPcll
.p2align 4, 0x90
.type _Z8read_csrPcll,@function
_Z8read_csrPcll: # @_Z8read_csrPcll
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $24, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %r14
movq %rsi, 8(%rsp)
movq %rdx, 16(%rsp)
movl $.L.str, %esi
callq fopen
testq %rax, %rax
je .LBB1_9
# %bb.1:
movq %rax, %rbx
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
shlq $4, %rcx
leaq (%rcx,%rax,8), %rdi
addq $8, %rdi
callq malloc
movq %rax, %r14
xorl %r12d, %r12d
leaq 8(%rsp), %rdx
leaq 16(%rsp), %rcx
movl $.L.str.2, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
cmpq $0, 8(%rsp)
js .LBB1_5
# %bb.2: # %.lr.ph.preheader
movq $-1, %r12
movq %r14, %r15
.p2align 4, 0x90
.LBB1_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.3, %esi
movq %rbx, %rdi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
incq %r12
addq $8, %r15
cmpq 8(%rsp), %r12
jl .LBB1_3
# %bb.4: # %.preheader.loopexit
incq %r12
.LBB1_5: # %.preheader
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
leaq (%rax,%rcx,2), %rax
incq %rax
cmpq %rax, %r12
jge .LBB1_8
# %bb.6: # %.lr.ph18.preheader
leaq (%r14,%r12,8), %r15
.p2align 4, 0x90
.LBB1_7: # %.lr.ph18
# =>This Inner Loop Header: Depth=1
movl $.L.str.3, %esi
movq %rbx, %rdi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
incq %r12
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
leaq (%rax,%rcx,2), %rax
incq %rax
addq $8, %r15
cmpq %rax, %r12
jl .LBB1_7
.LBB1_8: # %._crit_edge
movq %r14, %rax
addq $24, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_9:
.cfi_def_cfa_offset 64
movl $.L.str.1, %edi
movq %r14, %rsi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z8read_csrPcll, .Lfunc_end1-_Z8read_csrPcll
.cfi_endproc
# -- End function
.globl _Z29__device_stub__between_centrePdPlS0_S0_S0_ # -- Begin function _Z29__device_stub__between_centrePdPlS0_S0_S0_
.p2align 4, 0x90
.type _Z29__device_stub__between_centrePdPlS0_S0_S0_,@function
_Z29__device_stub__between_centrePdPlS0_S0_S0_: # @_Z29__device_stub__between_centrePdPlS0_S0_S0_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14between_centrePdPlS0_S0_S0_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end2:
.size _Z29__device_stub__between_centrePdPlS0_S0_S0_, .Lfunc_end2-_Z29__device_stub__between_centrePdPlS0_S0_S0_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str.4, %edi
movl $.L.str, %esi
callq fopen
testq %rax, %rax
je .LBB3_7
# %bb.1: # %_Z13get_graph_dimPc.exit
movq %rax, %rbx
movl $16, %edi
callq malloc
movq %rax, %r14
leaq 8(%rax), %rcx
movl $.L.str.2, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movl $.Lstr, %edi
callq puts@PLT
movq (%r14), %rsi
movq %rsi, 8(%rsp)
movq 8(%r14), %rdx
movq %rdx, 24(%rsp)
movl $.L.str.4, %edi
callq _Z8read_csrPcll
movq %rax, %r12
movl $.Lstr.1, %edi
callq puts@PLT
movq 8(%rsp), %rbx
leaq (,%rbx,8), %r15
leaq 8(,%rbx,8), %r13
movq %r13, %rdi
callq malloc
movq %rax, %r14
movq 24(%rsp), %rbp
shlq $4, %rbp
movq %rbp, %rdi
callq malloc
movq %rax, 80(%rsp) # 8-byte Spill
movq %r15, %rdi
callq malloc
movq %rax, %r15
movq %r14, %rdi
movq %r12, %rsi
movq %r13, %rdx
callq memcpy@PLT
leaq (%r12,%rbx,8), %rsi
addq $8, %rsi
movq %r14, %rbx
movq 80(%rsp), %r14 # 8-byte Reload
movq %r14, %rdi
movq %rbp, %rdx
callq memcpy@PLT
movq %r12, %rdi
callq free
movl $.Lstr.2, %edi
callq puts@PLT
leaq 72(%rsp), %rdi
movl $8, %esi
callq hipMalloc
leaq 64(%rsp), %rdi
movl $8, %esi
callq hipMalloc
movq 8(%rsp), %rsi
shlq $3, %rsi
leaq 40(%rsp), %rdi
callq hipMalloc
movq 8(%rsp), %rax
leaq 8(,%rax,8), %rsi
leaq 56(%rsp), %rdi
callq hipMalloc
movq 24(%rsp), %rsi
shlq $4, %rsi
leaq 48(%rsp), %rdi
callq hipMalloc
movq 72(%rsp), %rdi
leaq 8(%rsp), %rsi
movl $8, %edx
movl $1, %ecx
callq hipMemcpy
movq 64(%rsp), %rdi
leaq 24(%rsp), %rsi
movl $8, %edx
movl $1, %ecx
callq hipMemcpy
movq 56(%rsp), %rdi
movq 8(%rsp), %rax
leaq 8(,%rax,8), %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movq 24(%rsp), %rdx
shlq $4, %rdx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movl $.Lstr.3, %edi
callq puts@PLT
movl 8(%rsp), %r12d
movabsq $4294967296, %r13 # imm = 0x100000000
orq %r13, %r12
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
orq $1024, %r13 # imm = 0x400
movq %r12, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_3
# %bb.2:
movq 40(%rsp), %rax
movq 56(%rsp), %rcx
movq 48(%rsp), %rdx
movq 72(%rsp), %rsi
movq 64(%rsp), %rdi
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movq %rsi, 144(%rsp)
movq %rdi, 136(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 144(%rsp), %rax
movq %rax, 200(%rsp)
leaq 136(%rsp), %rax
movq %rax, 208(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z14between_centrePdPlS0_S0_S0_, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_3:
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 176(%rsp), %rdi
callq hipEventElapsedTime
movq 32(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 40(%rsp), %rsi
movq 8(%rsp), %rdx
shlq $3, %rdx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
cmpq $0, 8(%rsp)
jle .LBB3_6
# %bb.4: # %.lr.ph.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_5: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsd (%r15,%r12,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.9, %edi
movb $1, %al
callq printf
incq %r12
cmpq 8(%rsp), %r12
jl .LBB3_5
.LBB3_6: # %._crit_edge
movss 176(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.10, %edi
movb $1, %al
callq printf
movq 72(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_7:
.cfi_def_cfa_offset 272
movl $.L.str.1, %edi
movl $.L.str.4, %esi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14between_centrePdPlS0_S0_S0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Unable to read the CSR file: %s."
.size .L.str.1, 33
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%ld %ld"
.size .L.str.2, 8
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%ld"
.size .L.str.3, 4
.type _Z14between_centrePdPlS0_S0_S0_,@object # @_Z14between_centrePdPlS0_S0_S0_
.section .rodata,"a",@progbits
.globl _Z14between_centrePdPlS0_S0_S0_
.p2align 3, 0x0
_Z14between_centrePdPlS0_S0_S0_:
.quad _Z29__device_stub__between_centrePdPlS0_S0_S0_
.size _Z14between_centrePdPlS0_S0_S0_, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "01.txt"
.size .L.str.4, 7
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%.2f "
.size .L.str.9, 6
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "\nElapsed Time: %lf\n"
.size .L.str.10, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14between_centrePdPlS0_S0_S0_"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello!"
.size .Lstr, 7
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Holla!!"
.size .Lstr.1, 8
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Sui!"
.size .Lstr.2, 5
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Namaskara!"
.size .Lstr.3, 11
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__between_centrePdPlS0_S0_S0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14between_centrePdPlS0_S0_S0_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14between_centrePdPlS0_S0_S0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14between_centrePdPlS0_S0_S0_
.globl _Z14between_centrePdPlS0_S0_S0_
.p2align 8
.type _Z14between_centrePdPlS0_S0_S0_,@function
_Z14between_centrePdPlS0_S0_S0_:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14between_centrePdPlS0_S0_S0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14between_centrePdPlS0_S0_S0_, .Lfunc_end0-_Z14between_centrePdPlS0_S0_S0_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14between_centrePdPlS0_S0_S0_
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z14between_centrePdPlS0_S0_S0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009d357_00000000-6_bc_vert_front.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Unable to read the CSR file: %s."
.section .rodata.str1.1
.LC2:
.string "%ld %ld"
.text
.globl _Z13get_graph_dimPc
.type _Z13get_graph_dimPc, @function
_Z13get_graph_dimPc:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
leaq .LC0(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L6
movq %rax, %rbp
movl $16, %edi
call malloc@PLT
movq %rax, %rbx
leaq 8(%rax), %rcx
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movq %rbx, %rax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movq %rbx, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z13get_graph_dimPc, .-_Z13get_graph_dimPc
.section .rodata.str1.1
.LC3:
.string "%ld"
.text
.globl _Z8read_csrPcll
.type _Z8read_csrPcll, @function
_Z8read_csrPcll:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $16, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbx
movq %rsi, 8(%rsp)
movq %rdx, (%rsp)
leaq .LC0(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L17
movq %rax, %r12
movq 8(%rsp), %rax
movq (%rsp), %rdx
leaq 1(%rax,%rdx,2), %rdi
salq $3, %rdi
call malloc@PLT
movq %rax, %r13
movq %rsp, %rcx
leaq 8(%rsp), %rdx
leaq .LC2(%rip), %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpq $0, 8(%rsp)
js .L13
movq %r13, %rbp
movl $0, %ebx
leaq .LC3(%rip), %r14
.L10:
movq %rbp, %rdx
movq %r14, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $1, %rbx
addq $8, %rbp
cmpq %rbx, 8(%rsp)
jge .L10
.L9:
movq 8(%rsp), %rax
movq (%rsp), %rdx
leaq 1(%rax,%rdx,2), %rax
cmpq %rbx, %rax
jle .L7
leaq 0(%r13,%rbx,8), %rbp
leaq .LC3(%rip), %r14
.L12:
movq %rbp, %rdx
movq %r14, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $1, %rbx
addq $8, %rbp
movq 8(%rsp), %rax
movq (%rsp), %rdx
leaq 1(%rax,%rdx,2), %rax
cmpq %rbx, %rax
jg .L12
.L7:
movq %r13, %rax
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq %rbx, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L13:
movl $0, %ebx
jmp .L9
.cfi_endproc
.LFE2058:
.size _Z8read_csrPcll, .-_Z8read_csrPcll
.globl _Z45__device_stub__Z14between_centrePdPlS0_S0_S0_PdPlS0_S0_S0_
.type _Z45__device_stub__Z14between_centrePdPlS0_S0_S0_PdPlS0_S0_S0_, @function
_Z45__device_stub__Z14between_centrePdPlS0_S0_S0_PdPlS0_S0_S0_:
.LFB2084:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L22
.L18:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L23
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z14between_centrePdPlS0_S0_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L18
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z45__device_stub__Z14between_centrePdPlS0_S0_S0_PdPlS0_S0_S0_, .-_Z45__device_stub__Z14between_centrePdPlS0_S0_S0_PdPlS0_S0_S0_
.globl _Z14between_centrePdPlS0_S0_S0_
.type _Z14between_centrePdPlS0_S0_S0_, @function
_Z14between_centrePdPlS0_S0_S0_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z14between_centrePdPlS0_S0_S0_PdPlS0_S0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z14between_centrePdPlS0_S0_S0_, .-_Z14between_centrePdPlS0_S0_S0_
.section .rodata.str1.1
.LC4:
.string "01.txt"
.LC5:
.string "Hello!\n"
.LC6:
.string "Holla!!\n"
.LC7:
.string "Sui!\n"
.LC8:
.string "Namaskara!\n"
.LC9:
.string "%.2f "
.LC10:
.string "\nElapsed Time: %lf\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq .LC4(%rip), %rbp
movq %rbp, %rdi
call _Z13get_graph_dimPc
movq %rax, %rbx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rbx), %rsi
movq %rsi, 8(%rsp)
movq 8(%rbx), %rdx
movq %rdx, 16(%rsp)
movq %rbp, %rdi
call _Z8read_csrPcll
movq %rax, %r12
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rax
leaq 8(,%rax,8), %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq 16(%rsp), %r15
salq $4, %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, %r13
leaq -8(%rbx), %rdi
call malloc@PLT
movq %rax, %rbp
movq %rbx, %rcx
movq %rbx, %rdx
movq %r12, %rsi
movq %r14, %rdi
call __memcpy_chk@PLT
leaq (%r12,%rbx), %rsi
movq %r15, %rcx
movq %r15, %rdx
movq %r13, %rdi
call __memcpy_chk@PLT
movq %r12, %rdi
call free@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 24(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
movq 8(%rsp), %rax
leaq 0(,%rax,8), %rsi
leaq 56(%rsp), %rdi
call cudaMalloc@PLT
movq 8(%rsp), %rax
leaq 8(,%rax,8), %rsi
leaq 40(%rsp), %rdi
call cudaMalloc@PLT
movq 16(%rsp), %rsi
salq $4, %rsi
leaq 48(%rsp), %rdi
call cudaMalloc@PLT
leaq 8(%rsp), %rsi
movl $1, %ecx
movl $8, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rsi
movl $1, %ecx
movl $8, %edx
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rax
leaq 8(,%rax,8), %rdx
movl $1, %ecx
movq %r14, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movq 16(%rsp), %rdx
salq $4, %rdx
movl $1, %ecx
movq %r13, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rax
movl %eax, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1024, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movl 100(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movq 80(%rsp), %rdi
movl 88(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L27:
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
movq 72(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 64(%rsp), %rdi
call cudaEventDestroy@PLT
movq 72(%rsp), %rdi
call cudaEventDestroy@PLT
movq 8(%rsp), %rax
leaq 0(,%rax,8), %rdx
movl $2, %ecx
movq 56(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
cmpq $0, 8(%rsp)
jle .L28
movl $0, %ebx
leaq .LC9(%rip), %r12
.L29:
movsd 0(%rbp,%rbx,8), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %rbx, 8(%rsp)
jg .L29
.L28:
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L34
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
movq 32(%rsp), %r8
movq 24(%rsp), %rcx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z45__device_stub__Z14between_centrePdPlS0_S0_S0_PdPlS0_S0_S0_
jmp .L27
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC11:
.string "_Z14between_centrePdPlS0_S0_S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z14between_centrePdPlS0_S0_S0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "bc_vert_front.hip"
.globl _Z13get_graph_dimPc # -- Begin function _Z13get_graph_dimPc
.p2align 4, 0x90
.type _Z13get_graph_dimPc,@function
_Z13get_graph_dimPc: # @_Z13get_graph_dimPc
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
movl $.L.str, %esi
callq fopen
testq %rax, %rax
je .LBB0_2
# %bb.1:
movq %rax, %r14
movl $16, %edi
callq malloc
movq %rax, %rbx
leaq 8(%rax), %rcx
movl $.L.str.2, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movq %rbx, %rax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 32
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z13get_graph_dimPc, .Lfunc_end0-_Z13get_graph_dimPc
.cfi_endproc
# -- End function
.globl _Z8read_csrPcll # -- Begin function _Z8read_csrPcll
.p2align 4, 0x90
.type _Z8read_csrPcll,@function
_Z8read_csrPcll: # @_Z8read_csrPcll
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $24, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %r14
movq %rsi, 8(%rsp)
movq %rdx, 16(%rsp)
movl $.L.str, %esi
callq fopen
testq %rax, %rax
je .LBB1_9
# %bb.1:
movq %rax, %rbx
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
shlq $4, %rcx
leaq (%rcx,%rax,8), %rdi
addq $8, %rdi
callq malloc
movq %rax, %r14
xorl %r12d, %r12d
leaq 8(%rsp), %rdx
leaq 16(%rsp), %rcx
movl $.L.str.2, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
cmpq $0, 8(%rsp)
js .LBB1_5
# %bb.2: # %.lr.ph.preheader
movq $-1, %r12
movq %r14, %r15
.p2align 4, 0x90
.LBB1_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.3, %esi
movq %rbx, %rdi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
incq %r12
addq $8, %r15
cmpq 8(%rsp), %r12
jl .LBB1_3
# %bb.4: # %.preheader.loopexit
incq %r12
.LBB1_5: # %.preheader
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
leaq (%rax,%rcx,2), %rax
incq %rax
cmpq %rax, %r12
jge .LBB1_8
# %bb.6: # %.lr.ph18.preheader
leaq (%r14,%r12,8), %r15
.p2align 4, 0x90
.LBB1_7: # %.lr.ph18
# =>This Inner Loop Header: Depth=1
movl $.L.str.3, %esi
movq %rbx, %rdi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
incq %r12
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
leaq (%rax,%rcx,2), %rax
incq %rax
addq $8, %r15
cmpq %rax, %r12
jl .LBB1_7
.LBB1_8: # %._crit_edge
movq %r14, %rax
addq $24, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_9:
.cfi_def_cfa_offset 64
movl $.L.str.1, %edi
movq %r14, %rsi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z8read_csrPcll, .Lfunc_end1-_Z8read_csrPcll
.cfi_endproc
# -- End function
.globl _Z29__device_stub__between_centrePdPlS0_S0_S0_ # -- Begin function _Z29__device_stub__between_centrePdPlS0_S0_S0_
.p2align 4, 0x90
.type _Z29__device_stub__between_centrePdPlS0_S0_S0_,@function
_Z29__device_stub__between_centrePdPlS0_S0_S0_: # @_Z29__device_stub__between_centrePdPlS0_S0_S0_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14between_centrePdPlS0_S0_S0_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end2:
.size _Z29__device_stub__between_centrePdPlS0_S0_S0_, .Lfunc_end2-_Z29__device_stub__between_centrePdPlS0_S0_S0_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str.4, %edi
movl $.L.str, %esi
callq fopen
testq %rax, %rax
je .LBB3_7
# %bb.1: # %_Z13get_graph_dimPc.exit
movq %rax, %rbx
movl $16, %edi
callq malloc
movq %rax, %r14
leaq 8(%rax), %rcx
movl $.L.str.2, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movl $.Lstr, %edi
callq puts@PLT
movq (%r14), %rsi
movq %rsi, 8(%rsp)
movq 8(%r14), %rdx
movq %rdx, 24(%rsp)
movl $.L.str.4, %edi
callq _Z8read_csrPcll
movq %rax, %r12
movl $.Lstr.1, %edi
callq puts@PLT
movq 8(%rsp), %rbx
leaq (,%rbx,8), %r15
leaq 8(,%rbx,8), %r13
movq %r13, %rdi
callq malloc
movq %rax, %r14
movq 24(%rsp), %rbp
shlq $4, %rbp
movq %rbp, %rdi
callq malloc
movq %rax, 80(%rsp) # 8-byte Spill
movq %r15, %rdi
callq malloc
movq %rax, %r15
movq %r14, %rdi
movq %r12, %rsi
movq %r13, %rdx
callq memcpy@PLT
leaq (%r12,%rbx,8), %rsi
addq $8, %rsi
movq %r14, %rbx
movq 80(%rsp), %r14 # 8-byte Reload
movq %r14, %rdi
movq %rbp, %rdx
callq memcpy@PLT
movq %r12, %rdi
callq free
movl $.Lstr.2, %edi
callq puts@PLT
leaq 72(%rsp), %rdi
movl $8, %esi
callq hipMalloc
leaq 64(%rsp), %rdi
movl $8, %esi
callq hipMalloc
movq 8(%rsp), %rsi
shlq $3, %rsi
leaq 40(%rsp), %rdi
callq hipMalloc
movq 8(%rsp), %rax
leaq 8(,%rax,8), %rsi
leaq 56(%rsp), %rdi
callq hipMalloc
movq 24(%rsp), %rsi
shlq $4, %rsi
leaq 48(%rsp), %rdi
callq hipMalloc
movq 72(%rsp), %rdi
leaq 8(%rsp), %rsi
movl $8, %edx
movl $1, %ecx
callq hipMemcpy
movq 64(%rsp), %rdi
leaq 24(%rsp), %rsi
movl $8, %edx
movl $1, %ecx
callq hipMemcpy
movq 56(%rsp), %rdi
movq 8(%rsp), %rax
leaq 8(,%rax,8), %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movq 24(%rsp), %rdx
shlq $4, %rdx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movl $.Lstr.3, %edi
callq puts@PLT
movl 8(%rsp), %r12d
movabsq $4294967296, %r13 # imm = 0x100000000
orq %r13, %r12
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
orq $1024, %r13 # imm = 0x400
movq %r12, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_3
# %bb.2:
movq 40(%rsp), %rax
movq 56(%rsp), %rcx
movq 48(%rsp), %rdx
movq 72(%rsp), %rsi
movq 64(%rsp), %rdi
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movq %rsi, 144(%rsp)
movq %rdi, 136(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 144(%rsp), %rax
movq %rax, 200(%rsp)
leaq 136(%rsp), %rax
movq %rax, 208(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z14between_centrePdPlS0_S0_S0_, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_3:
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 176(%rsp), %rdi
callq hipEventElapsedTime
movq 32(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 40(%rsp), %rsi
movq 8(%rsp), %rdx
shlq $3, %rdx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
cmpq $0, 8(%rsp)
jle .LBB3_6
# %bb.4: # %.lr.ph.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_5: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsd (%r15,%r12,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.9, %edi
movb $1, %al
callq printf
incq %r12
cmpq 8(%rsp), %r12
jl .LBB3_5
.LBB3_6: # %._crit_edge
movss 176(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.10, %edi
movb $1, %al
callq printf
movq 72(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_7:
.cfi_def_cfa_offset 272
movl $.L.str.1, %edi
movl $.L.str.4, %esi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14between_centrePdPlS0_S0_S0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Unable to read the CSR file: %s."
.size .L.str.1, 33
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%ld %ld"
.size .L.str.2, 8
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%ld"
.size .L.str.3, 4
.type _Z14between_centrePdPlS0_S0_S0_,@object # @_Z14between_centrePdPlS0_S0_S0_
.section .rodata,"a",@progbits
.globl _Z14between_centrePdPlS0_S0_S0_
.p2align 3, 0x0
_Z14between_centrePdPlS0_S0_S0_:
.quad _Z29__device_stub__between_centrePdPlS0_S0_S0_
.size _Z14between_centrePdPlS0_S0_S0_, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "01.txt"
.size .L.str.4, 7
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%.2f "
.size .L.str.9, 6
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "\nElapsed Time: %lf\n"
.size .L.str.10, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14between_centrePdPlS0_S0_S0_"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello!"
.size .Lstr, 7
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Holla!!"
.size .Lstr.1, 8
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Sui!"
.size .Lstr.2, 5
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Namaskara!"
.size .Lstr.3, 11
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__between_centrePdPlS0_S0_S0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14between_centrePdPlS0_S0_S0_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void next_move_kernel(bool *mask, int *rat_count, int *healthy_rat_count, int *exposed_rat_count, int *infectious_rat_count, double *node_weight, double *sum_weight_result,int *neighbor, int *neighbor_start, int width, int height, double batch_fraction){
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int nid = y * width + x;
if (x < width && y < height){
for (int eid = neighbor_start[nid]; eid < neighbor_start[nid] + 5; eid++) { // 5 because self + up down left right
int remote_node = neighbor[eid];
double move_prob = batch_fraction * node_weight[remote_node] / sum_weight_result[nid]; // check 0
int move_rat = rat_count[nid] * move_prob;
int move_healthy = healthy_rat_count[nid] * move_prob;
int move_exposed = exposed_rat_count[nid] * move_prob;
int move_infectious = infectious_rat_count[nid] * move_prob;
atomicAdd(&rat_count[remote_node], move_rat);
atomicAdd(&healthy_rat_count[remote_node], move_healthy);
atomicAdd(&exposed_rat_count[remote_node], move_exposed);
atomicAdd(&infectious_rat_count[remote_node], move_infectious);
rat_count[nid] -= move_rat;
healthy_rat_count[nid] -= move_healthy;
exposed_rat_count[nid] -= move_exposed;
infectious_rat_count[nid] -= move_infectious;
}
}
} | code for sm_80
Function : _Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x1ac], PT ; /* 0x00006b0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x1a8], P0 ; /* 0x00006a0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD R0, R3, c[0x0][0x1a8], R0 ; /* 0x00006a0003007a24 */
/* 0x000fc800078e0200 */
/*00d0*/ IMAD.WIDE R16, R0, R9, c[0x0][0x1a0] ; /* 0x0000680000107625 */
/* 0x000fc800078e0209 */
/*00e0*/ IMAD.WIDE R14, R0.reuse, R9.reuse, c[0x0][0x180] ; /* 0x00006000000e7625 */
/* 0x0c0fe200078e0209 */
/*00f0*/ LDG.E R3, [R16.64] ; /* 0x0000000410037981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R2, [R14.64] ; /* 0x000000040e027981 */
/* 0x000162000c1e1900 */
/*0110*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fe400078e00ff */
/*0120*/ IMAD.WIDE R12, R0, R9, c[0x0][0x168] ; /* 0x00005a00000c7625 */
/* 0x000fc800078e0209 */
/*0130*/ IMAD.WIDE R10, R0, R9, c[0x0][0x170] ; /* 0x00005c00000a7625 */
/* 0x000fc800078e0209 */
/*0140*/ IMAD.WIDE R6, R0, R7, c[0x0][0x190] ; /* 0x0000640000067625 */
/* 0x000fc800078e0207 */
/*0150*/ IMAD.WIDE R4, R3.reuse, R9, c[0x0][0x198] ; /* 0x0000660003047625 */
/* 0x044fe200078e0209 */
/*0160*/ IADD3 R3, R3, -0x1, RZ ; /* 0xffffffff03037810 */
/* 0x000fc60007ffe0ff */
/*0170*/ IMAD.WIDE R8, R0, R9, c[0x0][0x178] ; /* 0x00005e0000087625 */
/* 0x001fc800078e0209 */
/*0180*/ LDG.E R32, [R4.64] ; /* 0x0000000404207981 */
/* 0x000ea8000c1e1900 */
/*0190*/ LDG.E.64 R36, [R6.64] ; /* 0x0000000406247981 */
/* 0x000ee2000c1e1b00 */
/*01a0*/ IMAD.MOV.U32 R19, RZ, RZ, 0x8 ; /* 0x00000008ff137424 */
/* 0x000fe400078e00ff */
/*01b0*/ IMAD.MOV.U32 R20, RZ, RZ, 0x1 ; /* 0x00000001ff147424 */
/* 0x000fe400078e00ff */
/*01c0*/ IMAD.WIDE R18, R32, R19, c[0x0][0x188] ; /* 0x0000620020127625 */
/* 0x004fcc00078e0213 */
/*01d0*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ea2000c1e1b00 */
/*01e0*/ MUFU.RCP64H R21, R37 ; /* 0x0000002500157308 */
/* 0x008e220000001800 */
/*01f0*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*0200*/ BSSY B0, 0x330 ; /* 0x0000012000007945 */
/* 0x000fe20003800000 */
/*0210*/ DFMA R22, -R36, R20, 1 ; /* 0x3ff000002416742b */
/* 0x001e0c0000000114 */
/*0220*/ DFMA R22, R22, R22, R22 ; /* 0x000000161616722b */
/* 0x001e0c0000000016 */
/*0230*/ DFMA R20, R20, R22, R20 ; /* 0x000000161414722b */
/* 0x001e0c0000000014 */
/*0240*/ DFMA R24, -R36, R20, 1 ; /* 0x3ff000002418742b */
/* 0x001e0c0000000114 */
/*0250*/ DFMA R24, R20, R24, R20 ; /* 0x000000181418722b */
/* 0x001fc80000000014 */
/*0260*/ DMUL R22, R18, c[0x0][0x1b0] ; /* 0x00006c0012167a28 */
/* 0x004e0c0000000000 */
/*0270*/ DMUL R20, R22, R24 ; /* 0x0000001816147228 */
/* 0x001e080000000000 */
/*0280*/ FSETP.GEU.AND P1, PT, |R23|, 6.5827683646048100446e-37, PT ; /* 0x036000001700780b */
/* 0x000fe40003f2e200 */
/*0290*/ DFMA R26, -R36, R20, R22 ; /* 0x00000014241a722b */
/* 0x001e0c0000000116 */
/*02a0*/ DFMA R18, R24, R26, R20 ; /* 0x0000001a1812722b */
/* 0x001e140000000014 */
/*02b0*/ FFMA R0, RZ, R37, R19 ; /* 0x00000025ff007223 */
/* 0x001fca0000000013 */
/*02c0*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*02d0*/ @P0 BRA P1, 0x320 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*02e0*/ MOV R0, 0x300 ; /* 0x0000030000007802 */
/* 0x000fe40000000f00 */
/*02f0*/ CALL.REL.NOINC 0x5f0 ; /* 0x000002f000007944 */
/* 0x020fea0003c00000 */
/*0300*/ IMAD.MOV.U32 R18, RZ, RZ, R26 ; /* 0x000000ffff127224 */
/* 0x000fe400078e001a */
/*0310*/ IMAD.MOV.U32 R19, RZ, RZ, R27 ; /* 0x000000ffff137224 */
/* 0x000fe400078e001b */
/*0320*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0330*/ LDG.E R30, [R12.64] ; /* 0x000000040c1e7981 */
/* 0x000ea8000c1e1900 */
/*0340*/ LDG.E R31, [R10.64] ; /* 0x000000040a1f7981 */
/* 0x000ee8000c1e1900 */
/*0350*/ LDG.E R33, [R8.64] ; /* 0x0000000408217981 */
/* 0x000f22000c1e1900 */
/*0360*/ I2F.F64 R22, R30 ; /* 0x0000001e00167312 */
/* 0x004e300000201c00 */
/*0370*/ I2F.F64 R24, R31 ; /* 0x0000001f00187312 */
/* 0x0082b00000201c00 */
/*0380*/ I2F.F64 R20, R33 ; /* 0x0000002100147312 */
/* 0x010ee20000201c00 */
/*0390*/ DMUL R26, R22, R18 ; /* 0x00000012161a7228 */
/* 0x0011220000000000 */
/*03a0*/ IMAD.MOV.U32 R31, RZ, RZ, 0x4 ; /* 0x00000004ff1f7424 */
/* 0x002fcc00078e00ff */
/*03b0*/ I2F.F64 R22, R2 ; /* 0x0000000200167312 */
/* 0x021e220000201c00 */
/*03c0*/ DMUL R24, R24, R18 ; /* 0x0000001218187228 */
/* 0x004e480000000000 */
/*03d0*/ DMUL R20, R20, R18 ; /* 0x0000001214147228 */
/* 0x008e860000000000 */
/*03e0*/ F2I.F64.TRUNC R0, R26 ; /* 0x0000001a00007311 */
/* 0x010722000030d100 */
/*03f0*/ DMUL R28, R22, R18 ; /* 0x00000012161c7228 */
/* 0x00100e0000000000 */
/*0400*/ F2I.F64.TRUNC R24, R24 ; /* 0x0000001800187311 */
/* 0x002e62000030d100 */
/*0410*/ IMAD.WIDE R18, R32, R31, c[0x0][0x168] ; /* 0x00005a0020127625 */
/* 0x001fc800078e021f */
/*0420*/ IMAD.WIDE R22, R32, R31, c[0x0][0x170] ; /* 0x00005c0020167625 */
/* 0x000fc600078e021f */
/*0430*/ F2I.F64.TRUNC R20, R20 ; /* 0x0000001400147311 */
/* 0x004e22000030d100 */
/*0440*/ IMAD.WIDE R26, R32.reuse, R31.reuse, c[0x0][0x178] ; /* 0x00005e00201a7625 */
/* 0x0c8fe200078e021f */
/*0450*/ RED.E.ADD.STRONG.GPU [R18.64], R0 ; /* 0x000000001200798e */
/* 0x0105e6000c10e184 */
/*0460*/ IMAD.WIDE R32, R32, R31, c[0x0][0x180] ; /* 0x0000600020207625 */
/* 0x000fc600078e021f */
/*0470*/ F2I.F64.TRUNC R29, R28 ; /* 0x0000001c001d7311 */
/* 0x000ee2000030d100 */
/*0480*/ RED.E.ADD.STRONG.GPU [R22.64], R24 ; /* 0x000000181600798e */
/* 0x0023e8000c10e184 */
/*0490*/ RED.E.ADD.STRONG.GPU [R26.64], R20 ; /* 0x000000141a00798e */
/* 0x0013e8000c10e184 */
/*04a0*/ RED.E.ADD.STRONG.GPU [R32.64], R29 ; /* 0x0000001d2000798e */
/* 0x0083e8000c10e184 */
/*04b0*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000ee4000c1e1900 */
/*04c0*/ IMAD.IADD R21, R21, 0x1, -R0 ; /* 0x0000000115157824 */
/* 0x008fca00078e0a00 */
/*04d0*/ STG.E [R12.64], R21 ; /* 0x000000150c007986 */
/* 0x0003e8000c101904 */
/*04e0*/ LDG.E R25, [R10.64] ; /* 0x000000040a197981 */
/* 0x000ee4000c1e1900 */
/*04f0*/ IMAD.IADD R25, R25, 0x1, -R24 ; /* 0x0000000119197824 */
/* 0x008fca00078e0a18 */
/*0500*/ STG.E [R10.64], R25 ; /* 0x000000190a007986 */
/* 0x0003e8000c101904 */
/*0510*/ LDG.E R31, [R8.64] ; /* 0x00000004081f7981 */
/* 0x000ee4000c1e1900 */
/*0520*/ IMAD.IADD R31, R31, 0x1, -R20 ; /* 0x000000011f1f7824 */
/* 0x008fca00078e0a14 */
/*0530*/ STG.E [R8.64], R31 ; /* 0x0000001f08007986 */
/* 0x0003e8000c101904 */
/*0540*/ LDG.E R2, [R14.64] ; /* 0x000000040e027981 */
/* 0x000ee4000c1e1900 */
/*0550*/ IMAD.IADD R2, R2, 0x1, -R29 ; /* 0x0000000102027824 */
/* 0x008fca00078e0a1d */
/*0560*/ STG.E [R14.64], R2 ; /* 0x000000020e007986 */
/* 0x0003e8000c101904 */
/*0570*/ LDG.E R0, [R16.64] ; /* 0x0000000410007981 */
/* 0x004ea2000c1e1900 */
/*0580*/ IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103037810 */
/* 0x000fe40007ffe0ff */
/*0590*/ IADD3 R4, P1, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fca0007f3e0ff */
/*05a0*/ IMAD.X R5, RZ, RZ, R5, P1 ; /* 0x000000ffff057224 */
/* 0x000fe200008e0605 */
/*05b0*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x004fc80007ffe0ff */
/*05c0*/ ISETP.GE.AND P0, PT, R3, R0, PT ; /* 0x000000000300720c */
/* 0x000fda0003f06270 */
/*05d0*/ @!P0 BRA 0x180 ; /* 0xfffffba000008947 */
/* 0x002fea000383ffff */
/*05e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05f0*/ FSETP.GEU.AND P0, PT, |R37|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000002500780b */
/* 0x040fe20003f0e200 */
/*0600*/ IMAD.MOV.U32 R20, RZ, RZ, R36.reuse ; /* 0x000000ffff147224 */
/* 0x100fe200078e0024 */
/*0610*/ LOP3.LUT R18, R37, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff25127812 */
/* 0x000fe200078ec0ff */
/*0620*/ IMAD.MOV.U32 R21, RZ, RZ, R37 ; /* 0x000000ffff157224 */
/* 0x000fe200078e0025 */
/*0630*/ FSETP.GEU.AND P2, PT, |R23|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000001700780b */
/* 0x040fe20003f4e200 */
/*0640*/ IMAD.MOV.U32 R34, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff227424 */
/* 0x000fe200078e00ff */
/*0650*/ LOP3.LUT R19, R18, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000012137812 */
/* 0x000fe200078efcff */
/*0660*/ IMAD.MOV.U32 R18, RZ, RZ, R36 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0024 */
/*0670*/ LOP3.LUT R33, R23, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000017217812 */
/* 0x000fe200078ec0ff */
/*0680*/ BSSY B1, 0xba0 ; /* 0x0000051000017945 */
/* 0x000fe20003800000 */
/*0690*/ LOP3.LUT R36, R37, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000025247812 */
/* 0x000fc600078ec0ff */
/*06a0*/ @!P0 DMUL R18, R20, 8.98846567431157953865e+307 ; /* 0x7fe0000014128828 */
/* 0x000e220000000000 */
/*06b0*/ ISETP.GE.U32.AND P1, PT, R33, R36, PT ; /* 0x000000242100720c */
/* 0x000fc60003f26070 */
/*06c0*/ @!P2 LOP3.LUT R24, R21, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000001518a812 */
/* 0x000fe200078ec0ff */
/*06d0*/ @!P2 IMAD.MOV.U32 R26, RZ, RZ, RZ ; /* 0x000000ffff1aa224 */
/* 0x000fe200078e00ff */
/*06e0*/ MUFU.RCP64H R25, R19 ; /* 0x0000001300197308 */
/* 0x001e220000001800 */
/*06f0*/ SEL R27, R34.reuse, 0x63400000, !P1 ; /* 0x63400000221b7807 */
/* 0x040fe40004800000 */
/*0700*/ @!P2 ISETP.GE.U32.AND P3, PT, R33, R24, PT ; /* 0x000000182100a20c */
/* 0x000fe20003f66070 */
/*0710*/ IMAD.MOV.U32 R24, RZ, RZ, 0x1 ; /* 0x00000001ff187424 */
/* 0x000fe200078e00ff */
/*0720*/ @!P0 LOP3.LUT R36, R19, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000013248812 */
/* 0x000fe400078ec0ff */
/*0730*/ @!P2 SEL R31, R34, 0x63400000, !P3 ; /* 0x63400000221fa807 */
/* 0x000fc80005800000 */
/*0740*/ @!P2 LOP3.LUT R31, R31, 0x80000000, R23, 0xf8, !PT ; /* 0x800000001f1fa812 */
/* 0x000fe200078ef817 */
/*0750*/ DFMA R28, R24, -R18, 1 ; /* 0x3ff00000181c742b */
/* 0x001e0c0000000812 */
/*0760*/ DFMA R28, R28, R28, R28 ; /* 0x0000001c1c1c722b */
/* 0x001e0c000000001c */
/*0770*/ DFMA R28, R24, R28, R24 ; /* 0x0000001c181c722b */
/* 0x0010640000000018 */
/*0780*/ LOP3.LUT R25, R27, 0x800fffff, R23, 0xf8, !PT ; /* 0x800fffff1b197812 */
/* 0x001fe200078ef817 */
/*0790*/ IMAD.MOV.U32 R24, RZ, RZ, R22 ; /* 0x000000ffff187224 */
/* 0x000fe200078e0016 */
/*07a0*/ @!P2 LOP3.LUT R27, R31, 0x100000, RZ, 0xfc, !PT ; /* 0x001000001f1ba812 */
/* 0x000fcc00078efcff */
/*07b0*/ @!P2 DFMA R24, R24, 2, -R26 ; /* 0x400000001818a82b */
/* 0x000fc8000000081a */
/*07c0*/ DFMA R26, R28, -R18, 1 ; /* 0x3ff000001c1a742b */
/* 0x002e0c0000000812 */
/*07d0*/ DFMA R26, R28, R26, R28 ; /* 0x0000001a1c1a722b */
/* 0x001e0c000000001c */
/*07e0*/ DMUL R28, R26, R24 ; /* 0x000000181a1c7228 */
/* 0x001e0c0000000000 */
/*07f0*/ DFMA R30, R28, -R18, R24 ; /* 0x800000121c1e722b */
/* 0x001e0c0000000018 */
/*0800*/ DFMA R30, R26, R30, R28 ; /* 0x0000001e1a1e722b */
/* 0x001064000000001c */
/*0810*/ IMAD.MOV.U32 R29, RZ, RZ, R33 ; /* 0x000000ffff1d7224 */
/* 0x001fe200078e0021 */
/*0820*/ @!P2 LOP3.LUT R29, R25, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000191da812 */
/* 0x000fc800078ec0ff */
/*0830*/ IADD3 R26, R29, -0x1, RZ ; /* 0xffffffff1d1a7810 */
/* 0x000fc80007ffe0ff */
/*0840*/ ISETP.GT.U32.AND P0, PT, R26, 0x7feffffe, PT ; /* 0x7feffffe1a00780c */
/* 0x000fe40003f04070 */
/*0850*/ IADD3 R26, R36, -0x1, RZ ; /* 0xffffffff241a7810 */
/* 0x000fc80007ffe0ff */
/*0860*/ ISETP.GT.U32.OR P0, PT, R26, 0x7feffffe, P0 ; /* 0x7feffffe1a00780c */
/* 0x000fda0000704470 */
/*0870*/ @P0 BRA 0xa40 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0880*/ LOP3.LUT R26, R21, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000151a7812 */
/* 0x002fc800078ec0ff */
/*0890*/ ISETP.GE.U32.AND P0, PT, R33.reuse, R26, PT ; /* 0x0000001a2100720c */
/* 0x040fe20003f06070 */
/*08a0*/ IMAD.IADD R22, R33, 0x1, -R26 ; /* 0x0000000121167824 */
/* 0x000fc600078e0a1a */
/*08b0*/ SEL R23, R34, 0x63400000, !P0 ; /* 0x6340000022177807 */
/* 0x000fe40004000000 */
/*08c0*/ IMNMX R22, R22, -0x46a00000, !PT ; /* 0xb960000016167817 */
/* 0x000fc80007800200 */
/*08d0*/ IMNMX R22, R22, 0x46a00000, PT ; /* 0x46a0000016167817 */
/* 0x000fca0003800200 */
/*08e0*/ IMAD.IADD R28, R22, 0x1, -R23 ; /* 0x00000001161c7824 */
/* 0x000fe400078e0a17 */
/*08f0*/ IMAD.MOV.U32 R22, RZ, RZ, RZ ; /* 0x000000ffff167224 */
/* 0x000fc600078e00ff */
/*0900*/ IADD3 R23, R28, 0x7fe00000, RZ ; /* 0x7fe000001c177810 */
/* 0x000fcc0007ffe0ff */
/*0910*/ DMUL R26, R30, R22 ; /* 0x000000161e1a7228 */
/* 0x000e140000000000 */
/*0920*/ FSETP.GTU.AND P0, PT, |R27|, 1.469367938527859385e-39, PT ; /* 0x001000001b00780b */
/* 0x001fda0003f0c200 */
/*0930*/ @P0 BRA 0xb90 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0940*/ DFMA R18, R30, -R18, R24 ; /* 0x800000121e12722b */
/* 0x000e220000000018 */
/*0950*/ IMAD.MOV.U32 R22, RZ, RZ, RZ ; /* 0x000000ffff167224 */
/* 0x000fd200078e00ff */
/*0960*/ FSETP.NEU.AND P0, PT, R19.reuse, RZ, PT ; /* 0x000000ff1300720b */
/* 0x041fe40003f0d000 */
/*0970*/ LOP3.LUT R21, R19, 0x80000000, R21, 0x48, !PT ; /* 0x8000000013157812 */
/* 0x000fc800078e4815 */
/*0980*/ LOP3.LUT R23, R21, R23, RZ, 0xfc, !PT ; /* 0x0000001715177212 */
/* 0x000fce00078efcff */
/*0990*/ @!P0 BRA 0xb90 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*09a0*/ IMAD.MOV R19, RZ, RZ, -R28 ; /* 0x000000ffff137224 */
/* 0x000fe200078e0a1c */
/*09b0*/ DMUL.RP R22, R30, R22 ; /* 0x000000161e167228 */
/* 0x000e220000008000 */
/*09c0*/ IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff127224 */
/* 0x000fcc00078e00ff */
/*09d0*/ DFMA R18, R26, -R18, R30 ; /* 0x800000121a12722b */
/* 0x000e46000000001e */
/*09e0*/ LOP3.LUT R21, R23, R21, RZ, 0x3c, !PT ; /* 0x0000001517157212 */
/* 0x001fc600078e3cff */
/*09f0*/ IADD3 R18, -R28, -0x43300000, RZ ; /* 0xbcd000001c127810 */
/* 0x002fc80007ffe1ff */
/*0a00*/ FSETP.NEU.AND P0, PT, |R19|, R18, PT ; /* 0x000000121300720b */
/* 0x000fc80003f0d200 */
/*0a10*/ FSEL R26, R22, R26, !P0 ; /* 0x0000001a161a7208 */
/* 0x000fe40004000000 */
/*0a20*/ FSEL R27, R21, R27, !P0 ; /* 0x0000001b151b7208 */
/* 0x000fe20004000000 */
/*0a30*/ BRA 0xb90 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0a40*/ DSETP.NAN.AND P0, PT, R22, R22, PT ; /* 0x000000161600722a */
/* 0x002e1c0003f08000 */
/*0a50*/ @P0 BRA 0xb70 ; /* 0x0000011000000947 */
/* 0x001fea0003800000 */
/*0a60*/ DSETP.NAN.AND P0, PT, R20, R20, PT ; /* 0x000000141400722a */
/* 0x000e1c0003f08000 */
/*0a70*/ @P0 BRA 0xb40 ; /* 0x000000c000000947 */
/* 0x001fea0003800000 */
/*0a80*/ ISETP.NE.AND P0, PT, R29, R36, PT ; /* 0x000000241d00720c */
/* 0x000fe20003f05270 */
/*0a90*/ IMAD.MOV.U32 R26, RZ, RZ, 0x0 ; /* 0x00000000ff1a7424 */
/* 0x000fe400078e00ff */
/*0aa0*/ IMAD.MOV.U32 R27, RZ, RZ, -0x80000 ; /* 0xfff80000ff1b7424 */
/* 0x000fd400078e00ff */
/*0ab0*/ @!P0 BRA 0xb90 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0ac0*/ ISETP.NE.AND P0, PT, R29, 0x7ff00000, PT ; /* 0x7ff000001d00780c */
/* 0x000fe40003f05270 */
/*0ad0*/ LOP3.LUT R27, R23, 0x80000000, R21, 0x48, !PT ; /* 0x80000000171b7812 */
/* 0x000fe400078e4815 */
/*0ae0*/ ISETP.EQ.OR P0, PT, R36, RZ, !P0 ; /* 0x000000ff2400720c */
/* 0x000fda0004702670 */
/*0af0*/ @P0 LOP3.LUT R18, R27, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000001b120812 */
/* 0x000fe200078efcff */
/*0b00*/ @!P0 IMAD.MOV.U32 R26, RZ, RZ, RZ ; /* 0x000000ffff1a8224 */
/* 0x000fe400078e00ff */
/*0b10*/ @P0 IMAD.MOV.U32 R26, RZ, RZ, RZ ; /* 0x000000ffff1a0224 */
/* 0x000fe400078e00ff */
/*0b20*/ @P0 IMAD.MOV.U32 R27, RZ, RZ, R18 ; /* 0x000000ffff1b0224 */
/* 0x000fe200078e0012 */
/*0b30*/ BRA 0xb90 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0b40*/ LOP3.LUT R27, R21, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000151b7812 */
/* 0x000fe200078efcff */
/*0b50*/ IMAD.MOV.U32 R26, RZ, RZ, R20 ; /* 0x000000ffff1a7224 */
/* 0x000fe200078e0014 */
/*0b60*/ BRA 0xb90 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0b70*/ LOP3.LUT R27, R23, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000171b7812 */
/* 0x000fe200078efcff */
/*0b80*/ IMAD.MOV.U32 R26, RZ, RZ, R22 ; /* 0x000000ffff1a7224 */
/* 0x000fe400078e0016 */
/*0b90*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0ba0*/ IMAD.MOV.U32 R18, RZ, RZ, R0 ; /* 0x000000ffff127224 */
/* 0x000fe400078e0000 */
/*0bb0*/ IMAD.MOV.U32 R19, RZ, RZ, 0x0 ; /* 0x00000000ff137424 */
/* 0x000fc800078e00ff */
/*0bc0*/ RET.REL.NODEC R18 0x0 ; /* 0xfffff43012007950 */
/* 0x000fea0003c3ffff */
/*0bd0*/ BRA 0xbd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void next_move_kernel(bool *mask, int *rat_count, int *healthy_rat_count, int *exposed_rat_count, int *infectious_rat_count, double *node_weight, double *sum_weight_result,int *neighbor, int *neighbor_start, int width, int height, double batch_fraction){
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int nid = y * width + x;
if (x < width && y < height){
for (int eid = neighbor_start[nid]; eid < neighbor_start[nid] + 5; eid++) { // 5 because self + up down left right
int remote_node = neighbor[eid];
double move_prob = batch_fraction * node_weight[remote_node] / sum_weight_result[nid]; // check 0
int move_rat = rat_count[nid] * move_prob;
int move_healthy = healthy_rat_count[nid] * move_prob;
int move_exposed = exposed_rat_count[nid] * move_prob;
int move_infectious = infectious_rat_count[nid] * move_prob;
atomicAdd(&rat_count[remote_node], move_rat);
atomicAdd(&healthy_rat_count[remote_node], move_healthy);
atomicAdd(&exposed_rat_count[remote_node], move_exposed);
atomicAdd(&infectious_rat_count[remote_node], move_infectious);
rat_count[nid] -= move_rat;
healthy_rat_count[nid] -= move_healthy;
exposed_rat_count[nid] -= move_exposed;
infectious_rat_count[nid] -= move_infectious;
}
}
} | .file "tmpxft_001852d2_00000000-6_next_move_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z61__device_stub__Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iidPbPiS0_S0_S0_PdS1_S0_S0_iid
.type _Z61__device_stub__Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iidPbPiS0_S0_S0_PdS1_S0_S0_iid, @function
_Z61__device_stub__Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iidPbPiS0_S0_S0_PdS1_S0_S0_iid:
.LFB2051:
.cfi_startproc
endbr64
subq $264, %rsp
.cfi_def_cfa_offset 272
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
movq %r8, 40(%rsp)
movq %r9, 32(%rsp)
movsd %xmm0, (%rsp)
movq 272(%rsp), %rax
movq %rax, 24(%rsp)
movq 280(%rsp), %rax
movq %rax, 16(%rsp)
movq 288(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 24(%rsp), %rax
movq %rax, 192(%rsp)
leaq 16(%rsp), %rax
movq %rax, 200(%rsp)
leaq 8(%rsp), %rax
movq %rax, 208(%rsp)
leaq 296(%rsp), %rax
movq %rax, 216(%rsp)
leaq 304(%rsp), %rax
movq %rax, 224(%rsp)
movq %rsp, %rax
movq %rax, 232(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 248(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 280
pushq 88(%rsp)
.cfi_def_cfa_offset 288
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 272
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z61__device_stub__Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iidPbPiS0_S0_S0_PdS1_S0_S0_iid, .-_Z61__device_stub__Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iidPbPiS0_S0_S0_PdS1_S0_S0_iid
.globl _Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid
.type _Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid, @function
_Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 56(%rsp)
.cfi_def_cfa_offset 48
pushq 56(%rsp)
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z61__device_stub__Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iidPbPiS0_S0_S0_PdS1_S0_S0_iid
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid, .-_Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void next_move_kernel(bool *mask, int *rat_count, int *healthy_rat_count, int *exposed_rat_count, int *infectious_rat_count, double *node_weight, double *sum_weight_result,int *neighbor, int *neighbor_start, int width, int height, double batch_fraction){
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int nid = y * width + x;
if (x < width && y < height){
for (int eid = neighbor_start[nid]; eid < neighbor_start[nid] + 5; eid++) { // 5 because self + up down left right
int remote_node = neighbor[eid];
double move_prob = batch_fraction * node_weight[remote_node] / sum_weight_result[nid]; // check 0
int move_rat = rat_count[nid] * move_prob;
int move_healthy = healthy_rat_count[nid] * move_prob;
int move_exposed = exposed_rat_count[nid] * move_prob;
int move_infectious = infectious_rat_count[nid] * move_prob;
atomicAdd(&rat_count[remote_node], move_rat);
atomicAdd(&healthy_rat_count[remote_node], move_healthy);
atomicAdd(&exposed_rat_count[remote_node], move_exposed);
atomicAdd(&infectious_rat_count[remote_node], move_infectious);
rat_count[nid] -= move_rat;
healthy_rat_count[nid] -= move_healthy;
exposed_rat_count[nid] -= move_exposed;
infectious_rat_count[nid] -= move_infectious;
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void next_move_kernel(bool *mask, int *rat_count, int *healthy_rat_count, int *exposed_rat_count, int *infectious_rat_count, double *node_weight, double *sum_weight_result,int *neighbor, int *neighbor_start, int width, int height, double batch_fraction){
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int nid = y * width + x;
if (x < width && y < height){
for (int eid = neighbor_start[nid]; eid < neighbor_start[nid] + 5; eid++) { // 5 because self + up down left right
int remote_node = neighbor[eid];
double move_prob = batch_fraction * node_weight[remote_node] / sum_weight_result[nid]; // check 0
int move_rat = rat_count[nid] * move_prob;
int move_healthy = healthy_rat_count[nid] * move_prob;
int move_exposed = exposed_rat_count[nid] * move_prob;
int move_infectious = infectious_rat_count[nid] * move_prob;
atomicAdd(&rat_count[remote_node], move_rat);
atomicAdd(&healthy_rat_count[remote_node], move_healthy);
atomicAdd(&exposed_rat_count[remote_node], move_exposed);
atomicAdd(&infectious_rat_count[remote_node], move_infectious);
rat_count[nid] -= move_rat;
healthy_rat_count[nid] -= move_healthy;
exposed_rat_count[nid] -= move_exposed;
infectious_rat_count[nid] -= move_infectious;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void next_move_kernel(bool *mask, int *rat_count, int *healthy_rat_count, int *exposed_rat_count, int *infectious_rat_count, double *node_weight, double *sum_weight_result,int *neighbor, int *neighbor_start, int width, int height, double batch_fraction){
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int nid = y * width + x;
if (x < width && y < height){
for (int eid = neighbor_start[nid]; eid < neighbor_start[nid] + 5; eid++) { // 5 because self + up down left right
int remote_node = neighbor[eid];
double move_prob = batch_fraction * node_weight[remote_node] / sum_weight_result[nid]; // check 0
int move_rat = rat_count[nid] * move_prob;
int move_healthy = healthy_rat_count[nid] * move_prob;
int move_exposed = exposed_rat_count[nid] * move_prob;
int move_infectious = infectious_rat_count[nid] * move_prob;
atomicAdd(&rat_count[remote_node], move_rat);
atomicAdd(&healthy_rat_count[remote_node], move_healthy);
atomicAdd(&exposed_rat_count[remote_node], move_exposed);
atomicAdd(&infectious_rat_count[remote_node], move_infectious);
rat_count[nid] -= move_rat;
healthy_rat_count[nid] -= move_healthy;
exposed_rat_count[nid] -= move_exposed;
infectious_rat_count[nid] -= move_infectious;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid
.globl _Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid
.p2align 8
.type _Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid,@function
_Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x64
s_load_b64 s[12:13], s[0:1], 0x48
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s12, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s13, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_3
s_load_b256 s[4:11], s[0:1], 0x28
v_mad_u64_u32 v[2:3], null, v1, s12, v[0:1]
s_clause 0x1
s_load_b256 s[12:19], s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x50
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[10:11], 2, v[2:3]
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s10, v10
v_add_co_ci_u32_e32 v1, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b32 v12, v[0:1], off
v_add_co_u32 v4, vcc_lo, s12, v10
v_add_co_ci_u32_e32 v5, vcc_lo, s13, v11, vcc_lo
v_add_co_u32 v6, vcc_lo, s14, v10
v_add_co_ci_u32_e32 v7, vcc_lo, s15, v11, vcc_lo
v_add_co_u32 v8, vcc_lo, s16, v10
v_add_co_ci_u32_e32 v9, vcc_lo, s17, v11, vcc_lo
v_add_co_u32 v10, vcc_lo, s18, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s19, v11, vcc_lo
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v13, 31, v12
v_add_nc_u32_e32 v14, -1, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[15:16], 2, v[12:13]
v_add_co_u32 v12, vcc_lo, s8, v15
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v13, vcc_lo, s9, v16, vcc_lo
.LBB0_2:
global_load_b32 v15, v[12:13], off
v_add_nc_u32_e32 v14, 1, v14
v_add_co_u32 v12, s0, v12, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v13, s0, 0, v13, s0
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v16, 31, v15
v_lshlrev_b64 v[17:18], 3, v[15:16]
v_lshlrev_b64 v[15:16], 2, v[15:16]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v17, vcc_lo, s4, v17
v_add_co_ci_u32_e32 v18, vcc_lo, s5, v18, vcc_lo
global_load_b64 v[17:18], v[17:18], off
global_load_b64 v[19:20], v[2:3], off
global_load_b32 v29, v[4:5], off
global_load_b32 v30, v[6:7], off
global_load_b32 v31, v[8:9], off
global_load_b32 v32, v[10:11], off
s_waitcnt vmcnt(5)
v_mul_f64 v[17:18], v[17:18], s[2:3]
s_waitcnt vmcnt(4)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f64 v[21:22], null, v[19:20], v[19:20], v[17:18]
v_div_scale_f64 v[27:28], vcc_lo, v[17:18], v[19:20], v[17:18]
v_rcp_f64_e32 v[23:24], v[21:22]
s_waitcnt_depctr 0xfff
v_fma_f64 v[25:26], -v[21:22], v[23:24], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[23:24], v[23:24], v[25:26], v[23:24]
v_fma_f64 v[25:26], -v[21:22], v[23:24], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[23:24], v[23:24], v[25:26], v[23:24]
v_mul_f64 v[25:26], v[27:28], v[23:24]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[21:22], -v[21:22], v[25:26], v[27:28]
v_div_fmas_f64 v[21:22], v[21:22], v[23:24], v[25:26]
s_waitcnt vmcnt(3)
v_cvt_f64_i32_e32 v[23:24], v29
s_waitcnt vmcnt(2)
v_cvt_f64_i32_e32 v[25:26], v30
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_div_fixup_f64 v[17:18], v[21:22], v[19:20], v[17:18]
s_waitcnt vmcnt(1)
v_cvt_f64_i32_e32 v[19:20], v31
s_waitcnt vmcnt(0)
v_cvt_f64_i32_e32 v[21:22], v32
v_mul_f64 v[23:24], v[17:18], v[23:24]
v_mul_f64 v[25:26], v[17:18], v[25:26]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_f64 v[19:20], v[17:18], v[19:20]
v_mul_f64 v[17:18], v[17:18], v[21:22]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cvt_i32_f64_e32 v23, v[23:24]
v_cvt_i32_f64_e32 v24, v[25:26]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cvt_i32_f64_e32 v25, v[19:20]
v_cvt_i32_f64_e32 v26, v[17:18]
v_add_co_u32 v17, vcc_lo, s12, v15
v_add_co_ci_u32_e32 v18, vcc_lo, s13, v16, vcc_lo
v_add_co_u32 v19, vcc_lo, s14, v15
v_add_co_ci_u32_e32 v20, vcc_lo, s15, v16, vcc_lo
v_add_co_u32 v21, vcc_lo, s16, v15
v_add_co_ci_u32_e32 v22, vcc_lo, s17, v16, vcc_lo
v_add_co_u32 v15, vcc_lo, s18, v15
v_add_co_ci_u32_e32 v16, vcc_lo, s19, v16, vcc_lo
global_atomic_add_u32 v[17:18], v23, off
global_atomic_add_u32 v[19:20], v24, off
global_atomic_add_u32 v[21:22], v25, off
global_atomic_add_u32 v[15:16], v26, off
global_load_b32 v15, v[4:5], off
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v15, v15, v23
global_store_b32 v[4:5], v15, off
global_load_b32 v15, v[6:7], off
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v15, v15, v24
global_store_b32 v[6:7], v15, off
global_load_b32 v15, v[8:9], off
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v15, v15, v25
global_store_b32 v[8:9], v15, off
global_load_b32 v15, v[10:11], off
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v15, v15, v26
global_store_b32 v[10:11], v15, off
global_load_b32 v15, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v15, 4, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ge_i32_e32 vcc_lo, v14, v15
s_or_b32 s1, vcc_lo, s1
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 344
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 33
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid, .Lfunc_end0-_Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .offset: 72
.size: 4
.value_kind: by_value
- .offset: 76
.size: 4
.value_kind: by_value
- .offset: 80
.size: 8
.value_kind: by_value
- .offset: 88
.size: 4
.value_kind: hidden_block_count_x
- .offset: 92
.size: 4
.value_kind: hidden_block_count_y
- .offset: 96
.size: 4
.value_kind: hidden_block_count_z
- .offset: 100
.size: 2
.value_kind: hidden_group_size_x
- .offset: 102
.size: 2
.value_kind: hidden_group_size_y
- .offset: 104
.size: 2
.value_kind: hidden_group_size_z
- .offset: 106
.size: 2
.value_kind: hidden_remainder_x
- .offset: 108
.size: 2
.value_kind: hidden_remainder_y
- .offset: 110
.size: 2
.value_kind: hidden_remainder_z
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 136
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 144
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 152
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 344
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 33
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void next_move_kernel(bool *mask, int *rat_count, int *healthy_rat_count, int *exposed_rat_count, int *infectious_rat_count, double *node_weight, double *sum_weight_result,int *neighbor, int *neighbor_start, int width, int height, double batch_fraction){
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int nid = y * width + x;
if (x < width && y < height){
for (int eid = neighbor_start[nid]; eid < neighbor_start[nid] + 5; eid++) { // 5 because self + up down left right
int remote_node = neighbor[eid];
double move_prob = batch_fraction * node_weight[remote_node] / sum_weight_result[nid]; // check 0
int move_rat = rat_count[nid] * move_prob;
int move_healthy = healthy_rat_count[nid] * move_prob;
int move_exposed = exposed_rat_count[nid] * move_prob;
int move_infectious = infectious_rat_count[nid] * move_prob;
atomicAdd(&rat_count[remote_node], move_rat);
atomicAdd(&healthy_rat_count[remote_node], move_healthy);
atomicAdd(&exposed_rat_count[remote_node], move_exposed);
atomicAdd(&infectious_rat_count[remote_node], move_infectious);
rat_count[nid] -= move_rat;
healthy_rat_count[nid] -= move_healthy;
exposed_rat_count[nid] -= move_exposed;
infectious_rat_count[nid] -= move_infectious;
}
}
} | .text
.file "next_move_kernel.hip"
.globl _Z31__device_stub__next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid # -- Begin function _Z31__device_stub__next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid
.p2align 4, 0x90
.type _Z31__device_stub__next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid,@function
_Z31__device_stub__next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid: # @_Z31__device_stub__next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movsd %xmm0, 56(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
leaq 56(%rsp), %rax
movq %rax, 200(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end0:
.size _Z31__device_stub__next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid, .Lfunc_end0-_Z31__device_stub__next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid,@object # @_Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid
.section .rodata,"a",@progbits
.globl _Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid
.p2align 3, 0x0
_Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid:
.quad _Z31__device_stub__next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid
.size _Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid"
.size .L__unnamed_1, 48
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x1ac], PT ; /* 0x00006b0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x1a8], P0 ; /* 0x00006a0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD R0, R3, c[0x0][0x1a8], R0 ; /* 0x00006a0003007a24 */
/* 0x000fc800078e0200 */
/*00d0*/ IMAD.WIDE R16, R0, R9, c[0x0][0x1a0] ; /* 0x0000680000107625 */
/* 0x000fc800078e0209 */
/*00e0*/ IMAD.WIDE R14, R0.reuse, R9.reuse, c[0x0][0x180] ; /* 0x00006000000e7625 */
/* 0x0c0fe200078e0209 */
/*00f0*/ LDG.E R3, [R16.64] ; /* 0x0000000410037981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R2, [R14.64] ; /* 0x000000040e027981 */
/* 0x000162000c1e1900 */
/*0110*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fe400078e00ff */
/*0120*/ IMAD.WIDE R12, R0, R9, c[0x0][0x168] ; /* 0x00005a00000c7625 */
/* 0x000fc800078e0209 */
/*0130*/ IMAD.WIDE R10, R0, R9, c[0x0][0x170] ; /* 0x00005c00000a7625 */
/* 0x000fc800078e0209 */
/*0140*/ IMAD.WIDE R6, R0, R7, c[0x0][0x190] ; /* 0x0000640000067625 */
/* 0x000fc800078e0207 */
/*0150*/ IMAD.WIDE R4, R3.reuse, R9, c[0x0][0x198] ; /* 0x0000660003047625 */
/* 0x044fe200078e0209 */
/*0160*/ IADD3 R3, R3, -0x1, RZ ; /* 0xffffffff03037810 */
/* 0x000fc60007ffe0ff */
/*0170*/ IMAD.WIDE R8, R0, R9, c[0x0][0x178] ; /* 0x00005e0000087625 */
/* 0x001fc800078e0209 */
/*0180*/ LDG.E R32, [R4.64] ; /* 0x0000000404207981 */
/* 0x000ea8000c1e1900 */
/*0190*/ LDG.E.64 R36, [R6.64] ; /* 0x0000000406247981 */
/* 0x000ee2000c1e1b00 */
/*01a0*/ IMAD.MOV.U32 R19, RZ, RZ, 0x8 ; /* 0x00000008ff137424 */
/* 0x000fe400078e00ff */
/*01b0*/ IMAD.MOV.U32 R20, RZ, RZ, 0x1 ; /* 0x00000001ff147424 */
/* 0x000fe400078e00ff */
/*01c0*/ IMAD.WIDE R18, R32, R19, c[0x0][0x188] ; /* 0x0000620020127625 */
/* 0x004fcc00078e0213 */
/*01d0*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ea2000c1e1b00 */
/*01e0*/ MUFU.RCP64H R21, R37 ; /* 0x0000002500157308 */
/* 0x008e220000001800 */
/*01f0*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*0200*/ BSSY B0, 0x330 ; /* 0x0000012000007945 */
/* 0x000fe20003800000 */
/*0210*/ DFMA R22, -R36, R20, 1 ; /* 0x3ff000002416742b */
/* 0x001e0c0000000114 */
/*0220*/ DFMA R22, R22, R22, R22 ; /* 0x000000161616722b */
/* 0x001e0c0000000016 */
/*0230*/ DFMA R20, R20, R22, R20 ; /* 0x000000161414722b */
/* 0x001e0c0000000014 */
/*0240*/ DFMA R24, -R36, R20, 1 ; /* 0x3ff000002418742b */
/* 0x001e0c0000000114 */
/*0250*/ DFMA R24, R20, R24, R20 ; /* 0x000000181418722b */
/* 0x001fc80000000014 */
/*0260*/ DMUL R22, R18, c[0x0][0x1b0] ; /* 0x00006c0012167a28 */
/* 0x004e0c0000000000 */
/*0270*/ DMUL R20, R22, R24 ; /* 0x0000001816147228 */
/* 0x001e080000000000 */
/*0280*/ FSETP.GEU.AND P1, PT, |R23|, 6.5827683646048100446e-37, PT ; /* 0x036000001700780b */
/* 0x000fe40003f2e200 */
/*0290*/ DFMA R26, -R36, R20, R22 ; /* 0x00000014241a722b */
/* 0x001e0c0000000116 */
/*02a0*/ DFMA R18, R24, R26, R20 ; /* 0x0000001a1812722b */
/* 0x001e140000000014 */
/*02b0*/ FFMA R0, RZ, R37, R19 ; /* 0x00000025ff007223 */
/* 0x001fca0000000013 */
/*02c0*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*02d0*/ @P0 BRA P1, 0x320 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*02e0*/ MOV R0, 0x300 ; /* 0x0000030000007802 */
/* 0x000fe40000000f00 */
/*02f0*/ CALL.REL.NOINC 0x5f0 ; /* 0x000002f000007944 */
/* 0x020fea0003c00000 */
/*0300*/ IMAD.MOV.U32 R18, RZ, RZ, R26 ; /* 0x000000ffff127224 */
/* 0x000fe400078e001a */
/*0310*/ IMAD.MOV.U32 R19, RZ, RZ, R27 ; /* 0x000000ffff137224 */
/* 0x000fe400078e001b */
/*0320*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0330*/ LDG.E R30, [R12.64] ; /* 0x000000040c1e7981 */
/* 0x000ea8000c1e1900 */
/*0340*/ LDG.E R31, [R10.64] ; /* 0x000000040a1f7981 */
/* 0x000ee8000c1e1900 */
/*0350*/ LDG.E R33, [R8.64] ; /* 0x0000000408217981 */
/* 0x000f22000c1e1900 */
/*0360*/ I2F.F64 R22, R30 ; /* 0x0000001e00167312 */
/* 0x004e300000201c00 */
/*0370*/ I2F.F64 R24, R31 ; /* 0x0000001f00187312 */
/* 0x0082b00000201c00 */
/*0380*/ I2F.F64 R20, R33 ; /* 0x0000002100147312 */
/* 0x010ee20000201c00 */
/*0390*/ DMUL R26, R22, R18 ; /* 0x00000012161a7228 */
/* 0x0011220000000000 */
/*03a0*/ IMAD.MOV.U32 R31, RZ, RZ, 0x4 ; /* 0x00000004ff1f7424 */
/* 0x002fcc00078e00ff */
/*03b0*/ I2F.F64 R22, R2 ; /* 0x0000000200167312 */
/* 0x021e220000201c00 */
/*03c0*/ DMUL R24, R24, R18 ; /* 0x0000001218187228 */
/* 0x004e480000000000 */
/*03d0*/ DMUL R20, R20, R18 ; /* 0x0000001214147228 */
/* 0x008e860000000000 */
/*03e0*/ F2I.F64.TRUNC R0, R26 ; /* 0x0000001a00007311 */
/* 0x010722000030d100 */
/*03f0*/ DMUL R28, R22, R18 ; /* 0x00000012161c7228 */
/* 0x00100e0000000000 */
/*0400*/ F2I.F64.TRUNC R24, R24 ; /* 0x0000001800187311 */
/* 0x002e62000030d100 */
/*0410*/ IMAD.WIDE R18, R32, R31, c[0x0][0x168] ; /* 0x00005a0020127625 */
/* 0x001fc800078e021f */
/*0420*/ IMAD.WIDE R22, R32, R31, c[0x0][0x170] ; /* 0x00005c0020167625 */
/* 0x000fc600078e021f */
/*0430*/ F2I.F64.TRUNC R20, R20 ; /* 0x0000001400147311 */
/* 0x004e22000030d100 */
/*0440*/ IMAD.WIDE R26, R32.reuse, R31.reuse, c[0x0][0x178] ; /* 0x00005e00201a7625 */
/* 0x0c8fe200078e021f */
/*0450*/ RED.E.ADD.STRONG.GPU [R18.64], R0 ; /* 0x000000001200798e */
/* 0x0105e6000c10e184 */
/*0460*/ IMAD.WIDE R32, R32, R31, c[0x0][0x180] ; /* 0x0000600020207625 */
/* 0x000fc600078e021f */
/*0470*/ F2I.F64.TRUNC R29, R28 ; /* 0x0000001c001d7311 */
/* 0x000ee2000030d100 */
/*0480*/ RED.E.ADD.STRONG.GPU [R22.64], R24 ; /* 0x000000181600798e */
/* 0x0023e8000c10e184 */
/*0490*/ RED.E.ADD.STRONG.GPU [R26.64], R20 ; /* 0x000000141a00798e */
/* 0x0013e8000c10e184 */
/*04a0*/ RED.E.ADD.STRONG.GPU [R32.64], R29 ; /* 0x0000001d2000798e */
/* 0x0083e8000c10e184 */
/*04b0*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000ee4000c1e1900 */
/*04c0*/ IMAD.IADD R21, R21, 0x1, -R0 ; /* 0x0000000115157824 */
/* 0x008fca00078e0a00 */
/*04d0*/ STG.E [R12.64], R21 ; /* 0x000000150c007986 */
/* 0x0003e8000c101904 */
/*04e0*/ LDG.E R25, [R10.64] ; /* 0x000000040a197981 */
/* 0x000ee4000c1e1900 */
/*04f0*/ IMAD.IADD R25, R25, 0x1, -R24 ; /* 0x0000000119197824 */
/* 0x008fca00078e0a18 */
/*0500*/ STG.E [R10.64], R25 ; /* 0x000000190a007986 */
/* 0x0003e8000c101904 */
/*0510*/ LDG.E R31, [R8.64] ; /* 0x00000004081f7981 */
/* 0x000ee4000c1e1900 */
/*0520*/ IMAD.IADD R31, R31, 0x1, -R20 ; /* 0x000000011f1f7824 */
/* 0x008fca00078e0a14 */
/*0530*/ STG.E [R8.64], R31 ; /* 0x0000001f08007986 */
/* 0x0003e8000c101904 */
/*0540*/ LDG.E R2, [R14.64] ; /* 0x000000040e027981 */
/* 0x000ee4000c1e1900 */
/*0550*/ IMAD.IADD R2, R2, 0x1, -R29 ; /* 0x0000000102027824 */
/* 0x008fca00078e0a1d */
/*0560*/ STG.E [R14.64], R2 ; /* 0x000000020e007986 */
/* 0x0003e8000c101904 */
/*0570*/ LDG.E R0, [R16.64] ; /* 0x0000000410007981 */
/* 0x004ea2000c1e1900 */
/*0580*/ IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103037810 */
/* 0x000fe40007ffe0ff */
/*0590*/ IADD3 R4, P1, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fca0007f3e0ff */
/*05a0*/ IMAD.X R5, RZ, RZ, R5, P1 ; /* 0x000000ffff057224 */
/* 0x000fe200008e0605 */
/*05b0*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x004fc80007ffe0ff */
/*05c0*/ ISETP.GE.AND P0, PT, R3, R0, PT ; /* 0x000000000300720c */
/* 0x000fda0003f06270 */
/*05d0*/ @!P0 BRA 0x180 ; /* 0xfffffba000008947 */
/* 0x002fea000383ffff */
/*05e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05f0*/ FSETP.GEU.AND P0, PT, |R37|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000002500780b */
/* 0x040fe20003f0e200 */
/*0600*/ IMAD.MOV.U32 R20, RZ, RZ, R36.reuse ; /* 0x000000ffff147224 */
/* 0x100fe200078e0024 */
/*0610*/ LOP3.LUT R18, R37, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff25127812 */
/* 0x000fe200078ec0ff */
/*0620*/ IMAD.MOV.U32 R21, RZ, RZ, R37 ; /* 0x000000ffff157224 */
/* 0x000fe200078e0025 */
/*0630*/ FSETP.GEU.AND P2, PT, |R23|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000001700780b */
/* 0x040fe20003f4e200 */
/*0640*/ IMAD.MOV.U32 R34, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff227424 */
/* 0x000fe200078e00ff */
/*0650*/ LOP3.LUT R19, R18, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000012137812 */
/* 0x000fe200078efcff */
/*0660*/ IMAD.MOV.U32 R18, RZ, RZ, R36 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0024 */
/*0670*/ LOP3.LUT R33, R23, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000017217812 */
/* 0x000fe200078ec0ff */
/*0680*/ BSSY B1, 0xba0 ; /* 0x0000051000017945 */
/* 0x000fe20003800000 */
/*0690*/ LOP3.LUT R36, R37, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000025247812 */
/* 0x000fc600078ec0ff */
/*06a0*/ @!P0 DMUL R18, R20, 8.98846567431157953865e+307 ; /* 0x7fe0000014128828 */
/* 0x000e220000000000 */
/*06b0*/ ISETP.GE.U32.AND P1, PT, R33, R36, PT ; /* 0x000000242100720c */
/* 0x000fc60003f26070 */
/*06c0*/ @!P2 LOP3.LUT R24, R21, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000001518a812 */
/* 0x000fe200078ec0ff */
/*06d0*/ @!P2 IMAD.MOV.U32 R26, RZ, RZ, RZ ; /* 0x000000ffff1aa224 */
/* 0x000fe200078e00ff */
/*06e0*/ MUFU.RCP64H R25, R19 ; /* 0x0000001300197308 */
/* 0x001e220000001800 */
/*06f0*/ SEL R27, R34.reuse, 0x63400000, !P1 ; /* 0x63400000221b7807 */
/* 0x040fe40004800000 */
/*0700*/ @!P2 ISETP.GE.U32.AND P3, PT, R33, R24, PT ; /* 0x000000182100a20c */
/* 0x000fe20003f66070 */
/*0710*/ IMAD.MOV.U32 R24, RZ, RZ, 0x1 ; /* 0x00000001ff187424 */
/* 0x000fe200078e00ff */
/*0720*/ @!P0 LOP3.LUT R36, R19, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000013248812 */
/* 0x000fe400078ec0ff */
/*0730*/ @!P2 SEL R31, R34, 0x63400000, !P3 ; /* 0x63400000221fa807 */
/* 0x000fc80005800000 */
/*0740*/ @!P2 LOP3.LUT R31, R31, 0x80000000, R23, 0xf8, !PT ; /* 0x800000001f1fa812 */
/* 0x000fe200078ef817 */
/*0750*/ DFMA R28, R24, -R18, 1 ; /* 0x3ff00000181c742b */
/* 0x001e0c0000000812 */
/*0760*/ DFMA R28, R28, R28, R28 ; /* 0x0000001c1c1c722b */
/* 0x001e0c000000001c */
/*0770*/ DFMA R28, R24, R28, R24 ; /* 0x0000001c181c722b */
/* 0x0010640000000018 */
/*0780*/ LOP3.LUT R25, R27, 0x800fffff, R23, 0xf8, !PT ; /* 0x800fffff1b197812 */
/* 0x001fe200078ef817 */
/*0790*/ IMAD.MOV.U32 R24, RZ, RZ, R22 ; /* 0x000000ffff187224 */
/* 0x000fe200078e0016 */
/*07a0*/ @!P2 LOP3.LUT R27, R31, 0x100000, RZ, 0xfc, !PT ; /* 0x001000001f1ba812 */
/* 0x000fcc00078efcff */
/*07b0*/ @!P2 DFMA R24, R24, 2, -R26 ; /* 0x400000001818a82b */
/* 0x000fc8000000081a */
/*07c0*/ DFMA R26, R28, -R18, 1 ; /* 0x3ff000001c1a742b */
/* 0x002e0c0000000812 */
/*07d0*/ DFMA R26, R28, R26, R28 ; /* 0x0000001a1c1a722b */
/* 0x001e0c000000001c */
/*07e0*/ DMUL R28, R26, R24 ; /* 0x000000181a1c7228 */
/* 0x001e0c0000000000 */
/*07f0*/ DFMA R30, R28, -R18, R24 ; /* 0x800000121c1e722b */
/* 0x001e0c0000000018 */
/*0800*/ DFMA R30, R26, R30, R28 ; /* 0x0000001e1a1e722b */
/* 0x001064000000001c */
/*0810*/ IMAD.MOV.U32 R29, RZ, RZ, R33 ; /* 0x000000ffff1d7224 */
/* 0x001fe200078e0021 */
/*0820*/ @!P2 LOP3.LUT R29, R25, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000191da812 */
/* 0x000fc800078ec0ff */
/*0830*/ IADD3 R26, R29, -0x1, RZ ; /* 0xffffffff1d1a7810 */
/* 0x000fc80007ffe0ff */
/*0840*/ ISETP.GT.U32.AND P0, PT, R26, 0x7feffffe, PT ; /* 0x7feffffe1a00780c */
/* 0x000fe40003f04070 */
/*0850*/ IADD3 R26, R36, -0x1, RZ ; /* 0xffffffff241a7810 */
/* 0x000fc80007ffe0ff */
/*0860*/ ISETP.GT.U32.OR P0, PT, R26, 0x7feffffe, P0 ; /* 0x7feffffe1a00780c */
/* 0x000fda0000704470 */
/*0870*/ @P0 BRA 0xa40 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0880*/ LOP3.LUT R26, R21, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000151a7812 */
/* 0x002fc800078ec0ff */
/*0890*/ ISETP.GE.U32.AND P0, PT, R33.reuse, R26, PT ; /* 0x0000001a2100720c */
/* 0x040fe20003f06070 */
/*08a0*/ IMAD.IADD R22, R33, 0x1, -R26 ; /* 0x0000000121167824 */
/* 0x000fc600078e0a1a */
/*08b0*/ SEL R23, R34, 0x63400000, !P0 ; /* 0x6340000022177807 */
/* 0x000fe40004000000 */
/*08c0*/ IMNMX R22, R22, -0x46a00000, !PT ; /* 0xb960000016167817 */
/* 0x000fc80007800200 */
/*08d0*/ IMNMX R22, R22, 0x46a00000, PT ; /* 0x46a0000016167817 */
/* 0x000fca0003800200 */
/*08e0*/ IMAD.IADD R28, R22, 0x1, -R23 ; /* 0x00000001161c7824 */
/* 0x000fe400078e0a17 */
/*08f0*/ IMAD.MOV.U32 R22, RZ, RZ, RZ ; /* 0x000000ffff167224 */
/* 0x000fc600078e00ff */
/*0900*/ IADD3 R23, R28, 0x7fe00000, RZ ; /* 0x7fe000001c177810 */
/* 0x000fcc0007ffe0ff */
/*0910*/ DMUL R26, R30, R22 ; /* 0x000000161e1a7228 */
/* 0x000e140000000000 */
/*0920*/ FSETP.GTU.AND P0, PT, |R27|, 1.469367938527859385e-39, PT ; /* 0x001000001b00780b */
/* 0x001fda0003f0c200 */
/*0930*/ @P0 BRA 0xb90 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0940*/ DFMA R18, R30, -R18, R24 ; /* 0x800000121e12722b */
/* 0x000e220000000018 */
/*0950*/ IMAD.MOV.U32 R22, RZ, RZ, RZ ; /* 0x000000ffff167224 */
/* 0x000fd200078e00ff */
/*0960*/ FSETP.NEU.AND P0, PT, R19.reuse, RZ, PT ; /* 0x000000ff1300720b */
/* 0x041fe40003f0d000 */
/*0970*/ LOP3.LUT R21, R19, 0x80000000, R21, 0x48, !PT ; /* 0x8000000013157812 */
/* 0x000fc800078e4815 */
/*0980*/ LOP3.LUT R23, R21, R23, RZ, 0xfc, !PT ; /* 0x0000001715177212 */
/* 0x000fce00078efcff */
/*0990*/ @!P0 BRA 0xb90 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*09a0*/ IMAD.MOV R19, RZ, RZ, -R28 ; /* 0x000000ffff137224 */
/* 0x000fe200078e0a1c */
/*09b0*/ DMUL.RP R22, R30, R22 ; /* 0x000000161e167228 */
/* 0x000e220000008000 */
/*09c0*/ IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff127224 */
/* 0x000fcc00078e00ff */
/*09d0*/ DFMA R18, R26, -R18, R30 ; /* 0x800000121a12722b */
/* 0x000e46000000001e */
/*09e0*/ LOP3.LUT R21, R23, R21, RZ, 0x3c, !PT ; /* 0x0000001517157212 */
/* 0x001fc600078e3cff */
/*09f0*/ IADD3 R18, -R28, -0x43300000, RZ ; /* 0xbcd000001c127810 */
/* 0x002fc80007ffe1ff */
/*0a00*/ FSETP.NEU.AND P0, PT, |R19|, R18, PT ; /* 0x000000121300720b */
/* 0x000fc80003f0d200 */
/*0a10*/ FSEL R26, R22, R26, !P0 ; /* 0x0000001a161a7208 */
/* 0x000fe40004000000 */
/*0a20*/ FSEL R27, R21, R27, !P0 ; /* 0x0000001b151b7208 */
/* 0x000fe20004000000 */
/*0a30*/ BRA 0xb90 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0a40*/ DSETP.NAN.AND P0, PT, R22, R22, PT ; /* 0x000000161600722a */
/* 0x002e1c0003f08000 */
/*0a50*/ @P0 BRA 0xb70 ; /* 0x0000011000000947 */
/* 0x001fea0003800000 */
/*0a60*/ DSETP.NAN.AND P0, PT, R20, R20, PT ; /* 0x000000141400722a */
/* 0x000e1c0003f08000 */
/*0a70*/ @P0 BRA 0xb40 ; /* 0x000000c000000947 */
/* 0x001fea0003800000 */
/*0a80*/ ISETP.NE.AND P0, PT, R29, R36, PT ; /* 0x000000241d00720c */
/* 0x000fe20003f05270 */
/*0a90*/ IMAD.MOV.U32 R26, RZ, RZ, 0x0 ; /* 0x00000000ff1a7424 */
/* 0x000fe400078e00ff */
/*0aa0*/ IMAD.MOV.U32 R27, RZ, RZ, -0x80000 ; /* 0xfff80000ff1b7424 */
/* 0x000fd400078e00ff */
/*0ab0*/ @!P0 BRA 0xb90 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0ac0*/ ISETP.NE.AND P0, PT, R29, 0x7ff00000, PT ; /* 0x7ff000001d00780c */
/* 0x000fe40003f05270 */
/*0ad0*/ LOP3.LUT R27, R23, 0x80000000, R21, 0x48, !PT ; /* 0x80000000171b7812 */
/* 0x000fe400078e4815 */
/*0ae0*/ ISETP.EQ.OR P0, PT, R36, RZ, !P0 ; /* 0x000000ff2400720c */
/* 0x000fda0004702670 */
/*0af0*/ @P0 LOP3.LUT R18, R27, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000001b120812 */
/* 0x000fe200078efcff */
/*0b00*/ @!P0 IMAD.MOV.U32 R26, RZ, RZ, RZ ; /* 0x000000ffff1a8224 */
/* 0x000fe400078e00ff */
/*0b10*/ @P0 IMAD.MOV.U32 R26, RZ, RZ, RZ ; /* 0x000000ffff1a0224 */
/* 0x000fe400078e00ff */
/*0b20*/ @P0 IMAD.MOV.U32 R27, RZ, RZ, R18 ; /* 0x000000ffff1b0224 */
/* 0x000fe200078e0012 */
/*0b30*/ BRA 0xb90 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0b40*/ LOP3.LUT R27, R21, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000151b7812 */
/* 0x000fe200078efcff */
/*0b50*/ IMAD.MOV.U32 R26, RZ, RZ, R20 ; /* 0x000000ffff1a7224 */
/* 0x000fe200078e0014 */
/*0b60*/ BRA 0xb90 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0b70*/ LOP3.LUT R27, R23, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000171b7812 */
/* 0x000fe200078efcff */
/*0b80*/ IMAD.MOV.U32 R26, RZ, RZ, R22 ; /* 0x000000ffff1a7224 */
/* 0x000fe400078e0016 */
/*0b90*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0ba0*/ IMAD.MOV.U32 R18, RZ, RZ, R0 ; /* 0x000000ffff127224 */
/* 0x000fe400078e0000 */
/*0bb0*/ IMAD.MOV.U32 R19, RZ, RZ, 0x0 ; /* 0x00000000ff137424 */
/* 0x000fc800078e00ff */
/*0bc0*/ RET.REL.NODEC R18 0x0 ; /* 0xfffff43012007950 */
/* 0x000fea0003c3ffff */
/*0bd0*/ BRA 0xbd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid
.globl _Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid
.p2align 8
.type _Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid,@function
_Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x64
s_load_b64 s[12:13], s[0:1], 0x48
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s12, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s13, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_3
s_load_b256 s[4:11], s[0:1], 0x28
v_mad_u64_u32 v[2:3], null, v1, s12, v[0:1]
s_clause 0x1
s_load_b256 s[12:19], s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x50
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[10:11], 2, v[2:3]
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s10, v10
v_add_co_ci_u32_e32 v1, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b32 v12, v[0:1], off
v_add_co_u32 v4, vcc_lo, s12, v10
v_add_co_ci_u32_e32 v5, vcc_lo, s13, v11, vcc_lo
v_add_co_u32 v6, vcc_lo, s14, v10
v_add_co_ci_u32_e32 v7, vcc_lo, s15, v11, vcc_lo
v_add_co_u32 v8, vcc_lo, s16, v10
v_add_co_ci_u32_e32 v9, vcc_lo, s17, v11, vcc_lo
v_add_co_u32 v10, vcc_lo, s18, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s19, v11, vcc_lo
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v13, 31, v12
v_add_nc_u32_e32 v14, -1, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[15:16], 2, v[12:13]
v_add_co_u32 v12, vcc_lo, s8, v15
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v13, vcc_lo, s9, v16, vcc_lo
.LBB0_2:
global_load_b32 v15, v[12:13], off
v_add_nc_u32_e32 v14, 1, v14
v_add_co_u32 v12, s0, v12, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v13, s0, 0, v13, s0
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v16, 31, v15
v_lshlrev_b64 v[17:18], 3, v[15:16]
v_lshlrev_b64 v[15:16], 2, v[15:16]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v17, vcc_lo, s4, v17
v_add_co_ci_u32_e32 v18, vcc_lo, s5, v18, vcc_lo
global_load_b64 v[17:18], v[17:18], off
global_load_b64 v[19:20], v[2:3], off
global_load_b32 v29, v[4:5], off
global_load_b32 v30, v[6:7], off
global_load_b32 v31, v[8:9], off
global_load_b32 v32, v[10:11], off
s_waitcnt vmcnt(5)
v_mul_f64 v[17:18], v[17:18], s[2:3]
s_waitcnt vmcnt(4)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f64 v[21:22], null, v[19:20], v[19:20], v[17:18]
v_div_scale_f64 v[27:28], vcc_lo, v[17:18], v[19:20], v[17:18]
v_rcp_f64_e32 v[23:24], v[21:22]
s_waitcnt_depctr 0xfff
v_fma_f64 v[25:26], -v[21:22], v[23:24], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[23:24], v[23:24], v[25:26], v[23:24]
v_fma_f64 v[25:26], -v[21:22], v[23:24], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[23:24], v[23:24], v[25:26], v[23:24]
v_mul_f64 v[25:26], v[27:28], v[23:24]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[21:22], -v[21:22], v[25:26], v[27:28]
v_div_fmas_f64 v[21:22], v[21:22], v[23:24], v[25:26]
s_waitcnt vmcnt(3)
v_cvt_f64_i32_e32 v[23:24], v29
s_waitcnt vmcnt(2)
v_cvt_f64_i32_e32 v[25:26], v30
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_div_fixup_f64 v[17:18], v[21:22], v[19:20], v[17:18]
s_waitcnt vmcnt(1)
v_cvt_f64_i32_e32 v[19:20], v31
s_waitcnt vmcnt(0)
v_cvt_f64_i32_e32 v[21:22], v32
v_mul_f64 v[23:24], v[17:18], v[23:24]
v_mul_f64 v[25:26], v[17:18], v[25:26]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_f64 v[19:20], v[17:18], v[19:20]
v_mul_f64 v[17:18], v[17:18], v[21:22]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cvt_i32_f64_e32 v23, v[23:24]
v_cvt_i32_f64_e32 v24, v[25:26]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cvt_i32_f64_e32 v25, v[19:20]
v_cvt_i32_f64_e32 v26, v[17:18]
v_add_co_u32 v17, vcc_lo, s12, v15
v_add_co_ci_u32_e32 v18, vcc_lo, s13, v16, vcc_lo
v_add_co_u32 v19, vcc_lo, s14, v15
v_add_co_ci_u32_e32 v20, vcc_lo, s15, v16, vcc_lo
v_add_co_u32 v21, vcc_lo, s16, v15
v_add_co_ci_u32_e32 v22, vcc_lo, s17, v16, vcc_lo
v_add_co_u32 v15, vcc_lo, s18, v15
v_add_co_ci_u32_e32 v16, vcc_lo, s19, v16, vcc_lo
global_atomic_add_u32 v[17:18], v23, off
global_atomic_add_u32 v[19:20], v24, off
global_atomic_add_u32 v[21:22], v25, off
global_atomic_add_u32 v[15:16], v26, off
global_load_b32 v15, v[4:5], off
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v15, v15, v23
global_store_b32 v[4:5], v15, off
global_load_b32 v15, v[6:7], off
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v15, v15, v24
global_store_b32 v[6:7], v15, off
global_load_b32 v15, v[8:9], off
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v15, v15, v25
global_store_b32 v[8:9], v15, off
global_load_b32 v15, v[10:11], off
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v15, v15, v26
global_store_b32 v[10:11], v15, off
global_load_b32 v15, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v15, 4, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ge_i32_e32 vcc_lo, v14, v15
s_or_b32 s1, vcc_lo, s1
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 344
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 33
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid, .Lfunc_end0-_Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .offset: 72
.size: 4
.value_kind: by_value
- .offset: 76
.size: 4
.value_kind: by_value
- .offset: 80
.size: 8
.value_kind: by_value
- .offset: 88
.size: 4
.value_kind: hidden_block_count_x
- .offset: 92
.size: 4
.value_kind: hidden_block_count_y
- .offset: 96
.size: 4
.value_kind: hidden_block_count_z
- .offset: 100
.size: 2
.value_kind: hidden_group_size_x
- .offset: 102
.size: 2
.value_kind: hidden_group_size_y
- .offset: 104
.size: 2
.value_kind: hidden_group_size_z
- .offset: 106
.size: 2
.value_kind: hidden_remainder_x
- .offset: 108
.size: 2
.value_kind: hidden_remainder_y
- .offset: 110
.size: 2
.value_kind: hidden_remainder_z
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 136
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 144
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 152
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 344
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 33
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001852d2_00000000-6_next_move_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z61__device_stub__Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iidPbPiS0_S0_S0_PdS1_S0_S0_iid
.type _Z61__device_stub__Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iidPbPiS0_S0_S0_PdS1_S0_S0_iid, @function
_Z61__device_stub__Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iidPbPiS0_S0_S0_PdS1_S0_S0_iid:
.LFB2051:
.cfi_startproc
endbr64
subq $264, %rsp
.cfi_def_cfa_offset 272
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
movq %r8, 40(%rsp)
movq %r9, 32(%rsp)
movsd %xmm0, (%rsp)
movq 272(%rsp), %rax
movq %rax, 24(%rsp)
movq 280(%rsp), %rax
movq %rax, 16(%rsp)
movq 288(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 24(%rsp), %rax
movq %rax, 192(%rsp)
leaq 16(%rsp), %rax
movq %rax, 200(%rsp)
leaq 8(%rsp), %rax
movq %rax, 208(%rsp)
leaq 296(%rsp), %rax
movq %rax, 216(%rsp)
leaq 304(%rsp), %rax
movq %rax, 224(%rsp)
movq %rsp, %rax
movq %rax, 232(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 248(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 280
pushq 88(%rsp)
.cfi_def_cfa_offset 288
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 272
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z61__device_stub__Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iidPbPiS0_S0_S0_PdS1_S0_S0_iid, .-_Z61__device_stub__Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iidPbPiS0_S0_S0_PdS1_S0_S0_iid
.globl _Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid
.type _Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid, @function
_Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 56(%rsp)
.cfi_def_cfa_offset 48
pushq 56(%rsp)
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z61__device_stub__Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iidPbPiS0_S0_S0_PdS1_S0_S0_iid
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid, .-_Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "next_move_kernel.hip"
.globl _Z31__device_stub__next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid # -- Begin function _Z31__device_stub__next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid
.p2align 4, 0x90
.type _Z31__device_stub__next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid,@function
_Z31__device_stub__next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid: # @_Z31__device_stub__next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movsd %xmm0, 56(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
leaq 56(%rsp), %rax
movq %rax, 200(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end0:
.size _Z31__device_stub__next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid, .Lfunc_end0-_Z31__device_stub__next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid,@object # @_Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid
.section .rodata,"a",@progbits
.globl _Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid
.p2align 3, 0x0
_Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid:
.quad _Z31__device_stub__next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid
.size _Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid"
.size .L__unnamed_1, 48
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16next_move_kernelPbPiS0_S0_S0_PdS1_S0_S0_iid
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <cuda_runtime.h>
#include <stdlib.h>
#include <time.h>
// Variables globales GPU y CPU
#define l_kernel 3
#define stride 3
/******************************
* Procesamiento Matriz CPU *
******************************/
/*
* Funcion Max
*/
float MaxCPU(float A, float B){
float result = A > B ? A : B;
return result;
}
/*
* Lectura Archivo
*/
void Read(float** R, float** G, float** B, int *M, int *N, const char *filename, int tipo) {
FILE *fp;
fp = fopen(filename, "r");
fscanf(fp, "%d %d\n", M, N);
int imsize = (*M) * (*N);
float* R1 = new float[imsize];
float* G1 = new float[imsize];
float* B1 = new float[imsize];
if (tipo == 0){ // Lectura normal
for(int i = 0; i < imsize; i++)
fscanf(fp, "%f ", &(R1[i]));
for(int i = 0; i < imsize; i++)
fscanf(fp, "%f ", &(G1[i]));
for(int i = 0; i < imsize; i++)
fscanf(fp, "%f ", &(B1[i]));
}
fclose(fp);
*R = R1; *G = G1; *B = B1;
}
/*
* Escritura Archivo
*/
void Write(float* R, float* G, float* B,
int M, int N, const char *filename) {
FILE *fp;
fp = fopen(filename, "w");
fprintf(fp, "%d %d\n", M, N);
for(int i = 0; i < M*N-1; i++)
fprintf(fp, "%f ", R[i]);
fprintf(fp, "%f\n", R[M*N-1]);
for(int i = 0; i < M*N-1; i++)
fprintf(fp, "%f ", G[i]);
fprintf(fp, "%f\n", G[M*N-1]);
for(int i = 0; i < M*N-1; i++)
fprintf(fp, "%f ", B[i]);
fprintf(fp, "%f\n", B[M*N-1]);
fclose(fp);
}
/*
* Imprimir Array como matriz
*/
void ShowMatrix(float *matrix, int N, int M) {
for(int i = 0; i < N; i++){
for(int j = 0; j < M; j++)
printf("%.1f ", matrix[j + i*M]);
printf("\n");
}
printf("\n");
}
/*
* "Producto" Matricial sub_A * kernel = C
* id: id del primer elemento de la submatriz, N: ancho matriz R,G,B
*/
float Product_Matrix(float *A, float *B, int N, int id){
int col, row, idx_kernel;
float count;
col = id%N;
row = id/N;
count = 0.0;
// Recorremos stride
idx_kernel = 0;
for(int i=row; i < row+l_kernel; i++){
for(int j=col; j< col+l_kernel; j++){
int id_casilla = j + i*N;
// printf("%.1f x %.1f\n", A[id_casilla], B[idx_kernel]);
count += A[id_casilla] * B[idx_kernel];
idx_kernel += 1;
}
}
return count;
}
__global__ void convolucion(float *f, float *f_out ,float* kernel, int N, int Nres){
int tid = threadIdx.x + blockDim.x * blockIdx.x;
int x,y;
if(tid < 800*800){ //1 thread para cada pixel de salida
x = 1 + (tid%Nres)*stride; //coordenaas del centro de cada sub_matriz
y = 1 + (tid/Nres)*stride;
float suma = 0;
int indice_sub_matriz, indice_kernel;
for (int i = -1; i<=1 ; i++){
for (int j = -1; j <= 1; j++){
indice_sub_matriz = (x+i) + (y+j)*N;
indice_kernel = (1+i) + (1+j)*3;
suma += f[indice_sub_matriz] * kernel[indice_kernel];
}
}
printf("%f\n", suma);
f_out[tid] = suma;
}
}
__device__ float max_pool(float *f, int N, int x, int y){
//recorre una sub matriz de 2x2 y encuentra el valor máximo
float valores[4] = {
f[(x+0) + (y+0)*N],
f[(x+1) + (y+0)*N],
f[(x+0) + (y+1)*N],
f[(x+1) + (y+1)*N]
};
int max = 0;
for (int i = 0; i< 4; i++){
if (valores[i] > max){
max = valores[i];
}
}
return max;
}
__global__ void pooling(float *f, float *f_out, int N){
int tid = threadIdx.x + blockDim.x * blockIdx.x;
int x,y;
if(tid < 400*400){ //1 thread para cada pixel de salida
x = 1 + (tid%N)*stride;
y = 1 + (tid/N)*stride;
f_out[tid] = max_pool(f, N , x, y);
}
}
/*
* Codigo Principal
*/
int main(int argc, char **argv){
/*
* Inicializacion
*/
int M, N;
float kernel[l_kernel*l_kernel] = {-1, 1, 0, -1, 1, 0 ,-1, 1, 0}; // filtro a usar
float *Rhost, *Ghost, *Bhost;
float *Rhostout, *Ghostout, *Bhostout;
float *R, *G, *B;
float *Rout, *Gout, *Bout;
int gs, bs = 256;
float dt;
cudaEvent_t ct1, ct2;
// Lectura de archivo
Read(&Rhost, &Ghost, &Bhost, &M, &N, "img_test.txt", 0);
int Mres = M/l_kernel;
int Nres = N/l_kernel;
Rhostout = new float[Mres*Nres];
Ghostout = new float[Mres*Nres];
Bhostout = new float[Mres*Nres];
/*
* Parte GPU
*/
gs = (int)ceil((float) Mres*Nres / bs);
cudaMalloc((void**)&R, M * N * sizeof(float));
cudaMalloc((void**)&G, M * N * sizeof(float));
cudaMalloc((void**)&B, M * N * sizeof(float));
cudaMemcpy(R, Rhost, M * N * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(G, Ghost, M * N * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(B, Bhost, M * N * sizeof(float), cudaMemcpyHostToDevice);
cudaMalloc((void**)&Rout, Mres * Nres * sizeof(float));
cudaMalloc((void**)&Gout, Mres * Nres * sizeof(float));
cudaMalloc((void**)&Bout, Mres * Nres * sizeof(float));
cudaEventCreate(&ct1);
cudaEventCreate(&ct2);
cudaEventRecord(ct1);
convolucion<<<gs, bs>>>(R, Rout, kernel, N, Nres);
convolucion<<<gs, bs>>>(G, Gout, kernel, N, Nres);
convolucion<<<gs, bs>>>(B, Bout, kernel, N, Nres);
cudaEventRecord(ct2);
cudaEventSynchronize(ct2);
cudaEventElapsedTime(&dt, ct1, ct2);
cudaMemcpy(Rhostout, Rout, M * N * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(Ghostout, Gout, M * N * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(Bhostout, Bout, M * N * sizeof(float), cudaMemcpyHostToDevice);
std::cout << "Tiempo: " << dt << "[ms]" << std::endl;
Write(Rhostout, Ghostout, Bhostout, Mres, Nres, "resultado.txt");
/*
* Memoria Global
*/
/*
* Memoria Compartida
*/
cudaFree(R); cudaFree(G); cudaFree(B);
cudaFree(Rout); cudaFree(Gout); cudaFree(Bout);
delete[] Rhost; delete[] Ghost; delete[] Bhost;
delete[] Rhostout; delete[] Ghostout; delete[] Bhostout;
return 0;
} | code for sm_80
Function : _Z7poolingPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R0, 0x270ff, PT ; /* 0x000270ff0000780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IABS R5, c[0x0][0x170] ; /* 0x00005c0000057a13 */
/* 0x000fe20000000000 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ MOV R11, 0x4 ; /* 0x00000004000b7802 */
/* 0x000fe40000000f00 */
/*0090*/ I2F.RP R4, R5 ; /* 0x0000000500047306 */
/* 0x000e300000209400 */
/*00a0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*00b0*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*00c0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00d0*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*00e0*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*00f0*/ IMAD R7, R6, R5, RZ ; /* 0x0000000506077224 */
/* 0x000fe200078e02ff */
/*0100*/ IABS R6, R0 ; /* 0x0000000000067213 */
/* 0x000fc80000000000 */
/*0110*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fe200078e0002 */
/*0120*/ LOP3.LUT R2, R0, c[0x0][0x170], RZ, 0x3c, !PT ; /* 0x00005c0000027a12 */
/* 0x000fc800078e3cff */
/*0130*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f26270 */
/*0140*/ IMAD.HI.U32 R3, R3, R6, RZ ; /* 0x0000000603037227 */
/* 0x000fc800078e00ff */
/*0150*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a03 */
/*0160*/ IMAD R4, R5, R4, R6 ; /* 0x0000000405047224 */
/* 0x000fca00078e0206 */
/*0170*/ ISETP.GT.U32.AND P2, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x000fda0003f44070 */
/*0180*/ @!P2 IADD3 R4, R4, -R5.reuse, RZ ; /* 0x800000050404a210 */
/* 0x080fe40007ffe0ff */
/*0190*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fe20003f06070 */
/*01b0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x3 ; /* 0x00000003ff047424 */
/* 0x000fe200078e00ff */
/*01c0*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fd60003f45270 */
/*01d0*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fca0007ffe0ff */
/*01e0*/ @!P1 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff039224 */
/* 0x000fe200078e0a03 */
/*01f0*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff03aa12 */
/* 0x000fc800078e33ff */
/*0200*/ IADD3 R5, -R3, RZ, RZ ; /* 0x000000ff03057210 */
/* 0x000fca0007ffe1ff */
/*0210*/ IMAD R2, R5, c[0x0][0x170], R0 ; /* 0x00005c0005027a24 */
/* 0x000fe400078e0200 */
/*0220*/ IMAD R5, R3, R4.reuse, 0x1 ; /* 0x0000000103057424 */
/* 0x080fe400078e0204 */
/*0230*/ IMAD R4, R2, R4, 0x1 ; /* 0x0000000102047424 */
/* 0x000fc800078e0204 */
/*0240*/ IMAD R2, R5, c[0x0][0x170], R4 ; /* 0x00005c0005027a24 */
/* 0x000fc800078e0204 */
/*0250*/ IMAD.WIDE R2, R2, R11, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e020b */
/*0260*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x0000a8000c1e1900 */
/*0270*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040402087981 */
/* 0x0000e2000c1e1900 */
/*0280*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff067624 */
/* 0x000fc800078e00ff */
/*0290*/ IMAD R5, R5, R6, c[0x0][0x170] ; /* 0x00005c0005057624 */
/* 0x000fca00078e0206 */
/*02a0*/ IADD3 R5, R4, R5, RZ ; /* 0x0000000504057210 */
/* 0x000fca0007ffe0ff */
/*02b0*/ IMAD.WIDE R4, R5, R11, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fca00078e020b */
/*02c0*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000f28000c1e1900 */
/*02d0*/ LDG.E R12, [R4.64+0x4] ; /* 0x00000404040c7981 */
/* 0x000f62000c1e1900 */
/*02e0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe400078e00ff */
/*02f0*/ IMAD.WIDE R2, R0, R11, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x001fe200078e020b */
/*0300*/ FSETP.GT.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720b */
/* 0x004fda0003f04000 */
/*0310*/ @P0 F2I.TRUNC.NTZ R6, R13 ; /* 0x0000000d00060305 */
/* 0x000e30000020f100 */
/*0320*/ @P0 I2F R7, R6 ; /* 0x0000000600070306 */
/* 0x001ee40000201400 */
/*0330*/ FSETP.GT.AND P0, PT, R8, R7, PT ; /* 0x000000070800720b */
/* 0x008fda0003f04000 */
/*0340*/ @P0 F2I.TRUNC.NTZ R8, R8 ; /* 0x0000000800080305 */
/* 0x000e30000020f100 */
/*0350*/ @P0 I2F R7, R8 ; /* 0x0000000800070306 */
/* 0x001f240000201400 */
/*0360*/ FSETP.GT.AND P0, PT, R10, R7, PT ; /* 0x000000070a00720b */
/* 0x010fda0003f04000 */
/*0370*/ @P0 F2I.TRUNC.NTZ R9, R10 ; /* 0x0000000a00090305 */
/* 0x000e30000020f100 */
/*0380*/ @P0 I2F R7, R9 ; /* 0x0000000900070306 */
/* 0x001f640000201400 */
/*0390*/ FSETP.GT.AND P0, PT, R12, R7, PT ; /* 0x000000070c00720b */
/* 0x020fda0003f04000 */
/*03a0*/ @P0 F2I.TRUNC.NTZ R4, R12 ; /* 0x0000000c00040305 */
/* 0x000e30000020f100 */
/*03b0*/ @P0 I2F R7, R4 ; /* 0x0000000400070306 */
/* 0x001e240000201400 */
/*03c0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x001fe2000c101904 */
/*03d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03e0*/ BRA 0x3e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11convolucionPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fc60000000f00 */
/*0010*/ S2R R17, SR_CTAID.X ; /* 0x0000000000117919 */
/* 0x000e220000002500 */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fc60007ffe0ff */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R17, R17, c[0x0][0x0], R0 ; /* 0x0000000011117a24 */
/* 0x001fca00078e0200 */
/*0050*/ ISETP.GT.AND P0, PT, R17, 0x9c3ff, PT ; /* 0x0009c3ff1100780c */
/* 0x000fda0003f04270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IABS R5, c[0x0][0x17c] ; /* 0x00005f0000057a13 */
/* 0x000fe20000000000 */
/*0080*/ ULDC.64 UR36, c[0x0][0x118] ; /* 0x0000460000247ab9 */
/* 0x000fc60000000a00 */
/*0090*/ I2F.RP R0, R5 ; /* 0x0000000500007306 */
/* 0x000e300000209400 */
/*00a0*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*00b0*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fcc0007ffe0ff */
/*00c0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00d0*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*00e0*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x002fc800078e0a03 */
/*00f0*/ IMAD R7, R4, R5, RZ ; /* 0x0000000504077224 */
/* 0x000fe200078e02ff */
/*0100*/ IABS R4, R17 ; /* 0x0000001100047213 */
/* 0x000fc80000000000 */
/*0110*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fc800078e0002 */
/*0120*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3 ; /* 0x00000003ff077424 */
/* 0x000fe400078e00ff */
/*0130*/ IMAD.HI.U32 R3, R3, R4, RZ ; /* 0x0000000403037227 */
/* 0x000fc800078e00ff */
/*0140*/ IMAD.MOV R0, RZ, RZ, -R3 ; /* 0x000000ffff007224 */
/* 0x000fc800078e0a03 */
/*0150*/ IMAD R0, R5, R0, R4 ; /* 0x0000000005007224 */
/* 0x000fe400078e0204 */
/*0160*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x000fc600078e00ff */
/*0170*/ ISETP.GT.U32.AND P2, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f44070 */
/*0180*/ @!P2 IADD3 R0, R0, -R5.reuse, RZ ; /* 0x800000050000a210 */
/* 0x080fe40007ffe0ff */
/*0190*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fe40003f06070 */
/*01b0*/ LOP3.LUT R0, R17, c[0x0][0x17c], RZ, 0x3c, !PT ; /* 0x00005f0011007a12 */
/* 0x000fe400078e3cff */
/*01c0*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fe40003f45270 */
/*01d0*/ ISETP.GE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc40003f26270 */
/*01e0*/ MOV R5, c[0x0][0x174] ; /* 0x00005d0000057a02 */
/* 0x000fca0000000f00 */
/*01f0*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fe20007ffe0ff */
/*0200*/ LDG.E R18, [R4.64] ; /* 0x0000002404127981 */
/* 0x0000a8000c1e1900 */
/*0210*/ LDG.E R20, [R4.64+0xc] ; /* 0x00000c2404147981 */
/* 0x0000e2000c1e1900 */
/*0220*/ @!P1 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff039224 */
/* 0x000fe200078e0a03 */
/*0230*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x17c], RZ, 0x33, !PT ; /* 0x00005f00ff03aa12 */
/* 0x000fe400078e33ff */
/*0240*/ LDG.E R25, [R4.64+0x18] ; /* 0x0000182404197981 */
/* 0x000124000c1e1900 */
/*0250*/ IADD3 R0, -R3.reuse, RZ, RZ ; /* 0x000000ff03007210 */
/* 0x040fe20007ffe1ff */
/*0260*/ IMAD R2, R3.reuse, c[0x0][0x178], RZ ; /* 0x00005e0003027a24 */
/* 0x040fe200078e02ff */
/*0270*/ LDG.E R16, [R4.64+0x4] ; /* 0x0000042404107981 */
/* 0x000166000c1e1900 */
/*0280*/ IMAD R0, R0, c[0x0][0x17c], R17 ; /* 0x00005f0000007a24 */
/* 0x000fe200078e0211 */
/*0290*/ LDG.E R12, [R4.64+0x10] ; /* 0x00001024040c7981 */
/* 0x0000a2000c1e1900 */
/*02a0*/ IMAD R7, R2, R7, c[0x0][0x178] ; /* 0x00005e0002077624 */
/* 0x000fe200078e0207 */
/*02b0*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*02c0*/ IMAD R8, R3, c[0x0][0x178], R0 ; /* 0x00005e0003087a24 */
/* 0x000fe200078e0200 */
/*02d0*/ LDG.E R10, [R4.64+0x8] ; /* 0x00000824040a7981 */
/* 0x0000a4000c1e1900 */
/*02e0*/ IADD3 R3, R7, c[0x0][0x178], RZ ; /* 0x00005e0007037a10 */
/* 0x000fe20007ffe0ff */
/*02f0*/ IMAD R8, R8, 0x3, RZ ; /* 0x0000000308087824 */
/* 0x000fe200078e02ff */
/*0300*/ LDG.E R14, [R4.64+0x14] ; /* 0x00001424040e7981 */
/* 0x0000a2000c1e1900 */
/*0310*/ IMAD R7, R0, 0x3, R7 ; /* 0x0000000300077824 */
/* 0x000fc400078e0207 */
/*0320*/ IMAD.WIDE R8, R8, R2.reuse, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x080fe200078e0202 */
/*0330*/ LDG.E R27, [R4.64+0x20] ; /* 0x00002024041b7981 */
/* 0x0000a6000c1e1900 */
/*0340*/ IMAD R3, R0, 0x3, R3 ; /* 0x0000000300037824 */
/* 0x000fe200078e0203 */
/*0350*/ LDG.E R23, [R8.64] ; /* 0x0000002408177981 */
/* 0x000ea2000c1e1900 */
/*0360*/ IMAD.WIDE R6, R7, R2, c[0x0][0x160] ; /* 0x0000580007067625 */
/* 0x000fc600078e0202 */
/*0370*/ LDG.E R21, [R8.64+0x4] ; /* 0x0000042408157981 */
/* 0x000f62000c1e1900 */
/*0380*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fc600078e0202 */
/*0390*/ LDG.E R22, [R6.64] ; /* 0x0000002406167981 */
/* 0x0002e8000c1e1900 */
/*03a0*/ LDG.E R24, [R2.64] ; /* 0x0000002402187981 */
/* 0x000128000c1e1900 */
/*03b0*/ LDG.E R15, [R6.64+0x4] ; /* 0x00000424060f7981 */
/* 0x000368000c1e1900 */
/*03c0*/ LDG.E R0, [R4.64+0x1c] ; /* 0x00001c2404007981 */
/* 0x000168000c1e1900 */
/*03d0*/ LDG.E R11, [R2.64+0x4] ; /* 0x00000424020b7981 */
/* 0x000168000c1e1900 */
/*03e0*/ LDG.E R13, [R8.64+0x8] ; /* 0x00000824080d7981 */
/* 0x000f68000c1e1900 */
/*03f0*/ LDG.E R19, [R6.64+0x8] ; /* 0x0000082406137981 */
/* 0x000368000c1e1900 */
/*0400*/ LDG.E R26, [R2.64+0x8] ; /* 0x00000824021a7981 */
/* 0x000164000c1e1900 */
/*0410*/ MOV R2, 0x8 ; /* 0x0000000800027802 */
/* 0x001fcc0000000f00 */
/*0420*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000e220000000a00 */
/*0430*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x002fe20007f1e0ff */
/*0440*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x4] ; /* 0x01000100ff057624 */
/* 0x000fe200078e00ff */
/*0450*/ MOV R4, c[0x4][0x0] ; /* 0x0100000000047a02 */
/* 0x000fe40000000f00 */
/*0460*/ IADD3.X R7, RZ, c[0x0][0x24], RZ, P0, !PT ; /* 0x00000900ff077a10 */
/* 0x000fe200007fe4ff */
/*0470*/ FFMA R23, R18, R23, RZ ; /* 0x0000001712177223 */
/* 0x004fc800000000ff */
/*0480*/ FFMA R20, R20, R22, R23 ; /* 0x0000001614147223 */
/* 0x008fc80000000017 */
/*0490*/ FFMA R20, R25, R24, R20 ; /* 0x0000001819147223 */
/* 0x010fc80000000014 */
/*04a0*/ FFMA R16, R16, R21, R20 ; /* 0x0000001510107223 */
/* 0x020fc80000000014 */
/*04b0*/ FFMA R12, R12, R15, R16 ; /* 0x0000000f0c0c7223 */
/* 0x000fc80000000010 */
/*04c0*/ FFMA R0, R0, R11, R12 ; /* 0x0000000b00007223 */
/* 0x000fc8000000000c */
/*04d0*/ FFMA R0, R10, R13, R0 ; /* 0x0000000d0a007223 */
/* 0x000fc80000000000 */
/*04e0*/ FFMA R0, R14, R19, R0 ; /* 0x000000130e007223 */
/* 0x000fc80000000000 */
/*04f0*/ FFMA R16, R27, R26, R0 ; /* 0x0000001a1b107223 */
/* 0x000fc80000000000 */
/*0500*/ F2F.F64.F32 R8, R16 ; /* 0x0000001000087310 */
/* 0x000e640000201800 */
/*0510*/ STL.64 [R1], R8 ; /* 0x0000000801007387 */
/* 0x0023e40000100a00 */
/*0520*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x003fe40000000000 */
/*0530*/ MOV R11, 0x5a0 ; /* 0x000005a0000b7802 */
/* 0x000fe40000000f00 */
/*0540*/ MOV R20, 0x520 ; /* 0x0000052000147802 */
/* 0x000fe40000000f00 */
/*0550*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0560*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0570*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0580*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0590*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x000fea0003c00000 */
/*05a0*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fd400000001ff */
/*05b0*/ IMAD.WIDE R2, R17, R2, c[0x0][0x168] ; /* 0x00005a0011027625 */
/* 0x000fca00078e0202 */
/*05c0*/ STG.E [R2.64], R16 ; /* 0x0000001002007986 */
/* 0x000fe2000c101924 */
/*05d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05e0*/ BRA 0x5e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <cuda_runtime.h>
#include <stdlib.h>
#include <time.h>
// Variables globales GPU y CPU
#define l_kernel 3
#define stride 3
/******************************
* Procesamiento Matriz CPU *
******************************/
/*
* Funcion Max
*/
float MaxCPU(float A, float B){
float result = A > B ? A : B;
return result;
}
/*
* Lectura Archivo
*/
void Read(float** R, float** G, float** B, int *M, int *N, const char *filename, int tipo) {
FILE *fp;
fp = fopen(filename, "r");
fscanf(fp, "%d %d\n", M, N);
int imsize = (*M) * (*N);
float* R1 = new float[imsize];
float* G1 = new float[imsize];
float* B1 = new float[imsize];
if (tipo == 0){ // Lectura normal
for(int i = 0; i < imsize; i++)
fscanf(fp, "%f ", &(R1[i]));
for(int i = 0; i < imsize; i++)
fscanf(fp, "%f ", &(G1[i]));
for(int i = 0; i < imsize; i++)
fscanf(fp, "%f ", &(B1[i]));
}
fclose(fp);
*R = R1; *G = G1; *B = B1;
}
/*
* Escritura Archivo
*/
void Write(float* R, float* G, float* B,
int M, int N, const char *filename) {
FILE *fp;
fp = fopen(filename, "w");
fprintf(fp, "%d %d\n", M, N);
for(int i = 0; i < M*N-1; i++)
fprintf(fp, "%f ", R[i]);
fprintf(fp, "%f\n", R[M*N-1]);
for(int i = 0; i < M*N-1; i++)
fprintf(fp, "%f ", G[i]);
fprintf(fp, "%f\n", G[M*N-1]);
for(int i = 0; i < M*N-1; i++)
fprintf(fp, "%f ", B[i]);
fprintf(fp, "%f\n", B[M*N-1]);
fclose(fp);
}
/*
* Imprimir Array como matriz
*/
void ShowMatrix(float *matrix, int N, int M) {
for(int i = 0; i < N; i++){
for(int j = 0; j < M; j++)
printf("%.1f ", matrix[j + i*M]);
printf("\n");
}
printf("\n");
}
/*
* "Producto" Matricial sub_A * kernel = C
* id: id del primer elemento de la submatriz, N: ancho matriz R,G,B
*/
float Product_Matrix(float *A, float *B, int N, int id){
int col, row, idx_kernel;
float count;
col = id%N;
row = id/N;
count = 0.0;
// Recorremos stride
idx_kernel = 0;
for(int i=row; i < row+l_kernel; i++){
for(int j=col; j< col+l_kernel; j++){
int id_casilla = j + i*N;
// printf("%.1f x %.1f\n", A[id_casilla], B[idx_kernel]);
count += A[id_casilla] * B[idx_kernel];
idx_kernel += 1;
}
}
return count;
}
__global__ void convolucion(float *f, float *f_out ,float* kernel, int N, int Nres){
int tid = threadIdx.x + blockDim.x * blockIdx.x;
int x,y;
if(tid < 800*800){ //1 thread para cada pixel de salida
x = 1 + (tid%Nres)*stride; //coordenaas del centro de cada sub_matriz
y = 1 + (tid/Nres)*stride;
float suma = 0;
int indice_sub_matriz, indice_kernel;
for (int i = -1; i<=1 ; i++){
for (int j = -1; j <= 1; j++){
indice_sub_matriz = (x+i) + (y+j)*N;
indice_kernel = (1+i) + (1+j)*3;
suma += f[indice_sub_matriz] * kernel[indice_kernel];
}
}
printf("%f\n", suma);
f_out[tid] = suma;
}
}
__device__ float max_pool(float *f, int N, int x, int y){
//recorre una sub matriz de 2x2 y encuentra el valor máximo
float valores[4] = {
f[(x+0) + (y+0)*N],
f[(x+1) + (y+0)*N],
f[(x+0) + (y+1)*N],
f[(x+1) + (y+1)*N]
};
int max = 0;
for (int i = 0; i< 4; i++){
if (valores[i] > max){
max = valores[i];
}
}
return max;
}
__global__ void pooling(float *f, float *f_out, int N){
int tid = threadIdx.x + blockDim.x * blockIdx.x;
int x,y;
if(tid < 400*400){ //1 thread para cada pixel de salida
x = 1 + (tid%N)*stride;
y = 1 + (tid/N)*stride;
f_out[tid] = max_pool(f, N , x, y);
}
}
/*
* Codigo Principal
*/
int main(int argc, char **argv){
/*
* Inicializacion
*/
int M, N;
float kernel[l_kernel*l_kernel] = {-1, 1, 0, -1, 1, 0 ,-1, 1, 0}; // filtro a usar
float *Rhost, *Ghost, *Bhost;
float *Rhostout, *Ghostout, *Bhostout;
float *R, *G, *B;
float *Rout, *Gout, *Bout;
int gs, bs = 256;
float dt;
cudaEvent_t ct1, ct2;
// Lectura de archivo
Read(&Rhost, &Ghost, &Bhost, &M, &N, "img_test.txt", 0);
int Mres = M/l_kernel;
int Nres = N/l_kernel;
Rhostout = new float[Mres*Nres];
Ghostout = new float[Mres*Nres];
Bhostout = new float[Mres*Nres];
/*
* Parte GPU
*/
gs = (int)ceil((float) Mres*Nres / bs);
cudaMalloc((void**)&R, M * N * sizeof(float));
cudaMalloc((void**)&G, M * N * sizeof(float));
cudaMalloc((void**)&B, M * N * sizeof(float));
cudaMemcpy(R, Rhost, M * N * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(G, Ghost, M * N * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(B, Bhost, M * N * sizeof(float), cudaMemcpyHostToDevice);
cudaMalloc((void**)&Rout, Mres * Nres * sizeof(float));
cudaMalloc((void**)&Gout, Mres * Nres * sizeof(float));
cudaMalloc((void**)&Bout, Mres * Nres * sizeof(float));
cudaEventCreate(&ct1);
cudaEventCreate(&ct2);
cudaEventRecord(ct1);
convolucion<<<gs, bs>>>(R, Rout, kernel, N, Nres);
convolucion<<<gs, bs>>>(G, Gout, kernel, N, Nres);
convolucion<<<gs, bs>>>(B, Bout, kernel, N, Nres);
cudaEventRecord(ct2);
cudaEventSynchronize(ct2);
cudaEventElapsedTime(&dt, ct1, ct2);
cudaMemcpy(Rhostout, Rout, M * N * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(Ghostout, Gout, M * N * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(Bhostout, Bout, M * N * sizeof(float), cudaMemcpyHostToDevice);
std::cout << "Tiempo: " << dt << "[ms]" << std::endl;
Write(Rhostout, Ghostout, Bhostout, Mres, Nres, "resultado.txt");
/*
* Memoria Global
*/
/*
* Memoria Compartida
*/
cudaFree(R); cudaFree(G); cudaFree(B);
cudaFree(Rout); cudaFree(Gout); cudaFree(Bout);
delete[] Rhost; delete[] Ghost; delete[] Bhost;
delete[] Rhostout; delete[] Ghostout; delete[] Bhostout;
return 0;
} | .file "tmpxft_00083b19_00000000-6_streams.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3678:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3678:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6MaxCPUff
.type _Z6MaxCPUff, @function
_Z6MaxCPUff:
.LFB3669:
.cfi_startproc
endbr64
maxss %xmm1, %xmm0
ret
.cfi_endproc
.LFE3669:
.size _Z6MaxCPUff, .-_Z6MaxCPUff
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "%d %d\n"
.LC2:
.string "%f "
.text
.globl _Z4ReadPPfS0_S0_PiS1_PKci
.type _Z4ReadPPfS0_S0_PiS1_PKci, @function
_Z4ReadPPfS0_S0_PiS1_PKci:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 24(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, %r12
movq %r8, %rbp
movq %r9, %rdi
leaq .LC0(%rip), %rsi
call fopen@PLT
movq %rax, %rbx
movq %rbp, %rcx
movq %r12, %rdx
leaq .LC1(%rip), %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl (%r12), %r15d
imull 0(%rbp), %r15d
movslq %r15d, %r12
movabsq $2305843009213693950, %rax
cmpq %r12, %rax
jb .L8
salq $2, %r12
movq %r12, %rdi
call _Znam@PLT
movq %rax, %r14
movq %rax, 16(%rsp)
movq %r12, %rdi
call _Znam@PLT
movq %rax, (%rsp)
movq %r12, %rdi
call _Znam@PLT
movq %rax, 8(%rsp)
cmpl $0, 112(%rsp)
jne .L9
movq %r14, %rbp
addq %r12, %r14
leaq .LC2(%rip), %r13
testl %r15d, %r15d
jle .L9
.L11:
movq %rbp, %rdx
movq %r13, %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $4, %rbp
cmpq %r14, %rbp
jne .L11
movq (%rsp), %rax
movq %rax, %rbp
leaq (%r12,%rax), %r14
leaq .LC2(%rip), %r13
.L12:
movq %rbp, %rdx
movq %r13, %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $4, %rbp
cmpq %r14, %rbp
jne .L12
movq 8(%rsp), %rax
movq %rax, %rbp
addq %rax, %r12
leaq .LC2(%rip), %r13
.L13:
movq %rbp, %rdx
movq %r13, %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $4, %rbp
cmpq %rbp, %r12
jne .L13
.L9:
movq %rbx, %rdi
call fclose@PLT
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rcx, (%rax)
movq 32(%rsp), %rax
movq (%rsp), %rcx
movq %rcx, (%rax)
movq 40(%rsp), %rax
movq 8(%rsp), %rcx
movq %rcx, (%rax)
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
call __cxa_throw_bad_array_new_length@PLT
.cfi_endproc
.LFE3670:
.size _Z4ReadPPfS0_S0_PiS1_PKci, .-_Z4ReadPPfS0_S0_PiS1_PKci
.section .rodata.str1.1
.LC3:
.string "w"
.LC4:
.string "%f\n"
.text
.globl _Z5WritePfS_S_iiPKc
.type _Z5WritePfS_S_iiPKc, @function
_Z5WritePfS_S_iiPKc:
.LFB3671:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r14
movq %rdi, 24(%rsp)
movq %rsi, 8(%rsp)
movq %rdx, (%rsp)
movl %ecx, %r12d
movl %r8d, %ebx
movq %r9, %rdi
leaq .LC3(%rip), %rsi
call fopen@PLT
movq %rax, %rbp
movl %ebx, %r8d
movl %r12d, %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq %rax, %rdi
movl $0, %eax
call __fprintf_chk@PLT
imull %ebx, %r12d
cmpl $1, %r12d
jle .L20
movq %r14, %rbx
leal -2(%r12), %r13d
salq $2, %r13
leaq 4(%r14,%r13), %r15
leaq .LC2(%rip), %r14
.L21:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r14, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $4, %rbx
cmpq %r15, %rbx
jne .L21
movslq %r12d, %r12
salq $2, %r12
leaq -4(%r12), %rax
movq %rax, 16(%rsp)
movq 24(%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd -4(%rax,%r12), %xmm0
leaq .LC4(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
movq 8(%rsp), %rax
movq %rax, %rbx
leaq 4(%rax,%r13), %r15
leaq .LC2(%rip), %r14
.L22:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r14, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $4, %rbx
cmpq %r15, %rbx
jne .L22
movq 8(%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd -4(%rax,%r12), %xmm0
leaq .LC4(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
movq (%rsp), %rax
movq %rax, %rbx
leaq 4(%rax,%r13), %r13
leaq .LC2(%rip), %r12
.L23:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $4, %rbx
cmpq %r13, %rbx
jne .L23
.L24:
movq (%rsp), %rax
movq 16(%rsp), %rcx
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rcx), %xmm0
leaq .LC4(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
movq %rbp, %rdi
call fclose@PLT
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movslq %r12d, %rbx
salq $2, %rbx
leaq -4(%rbx), %rax
movq %rax, 16(%rsp)
movq 24(%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd -4(%rax,%rbx), %xmm0
leaq .LC4(%rip), %r12
movq %r12, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
movq 8(%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd -4(%rax,%rbx), %xmm0
movq %r12, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
jmp .L24
.cfi_endproc
.LFE3671:
.size _Z5WritePfS_S_iiPKc, .-_Z5WritePfS_S_iiPKc
.section .rodata.str1.1
.LC5:
.string "%.1f "
.LC6:
.string "\n"
.text
.globl _Z10ShowMatrixPfii
.type _Z10ShowMatrixPfii, @function
_Z10ShowMatrixPfii:
.LFB3672:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
movl %esi, 12(%rsp)
testl %esi, %esi
jle .L31
movl %edx, %r15d
movl $0, %r14d
movl $0, %r13d
movslq %edx, %rax
movq %rax, 24(%rsp)
leaq .LC5(%rip), %r12
jmp .L32
.L34:
movslq %r14d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movq 24(%rsp), %rdx
addq %rdx, %rax
leaq (%rcx,%rax,4), %rbp
.L33:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L33
.L35:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addl %r15d, %r14d
cmpl %r13d, 12(%rsp)
je .L31
.L32:
testl %r15d, %r15d
jg .L34
jmp .L35
.L31:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _Z10ShowMatrixPfii, .-_Z10ShowMatrixPfii
.globl _Z14Product_MatrixPfS_ii
.type _Z14Product_MatrixPfS_ii, @function
_Z14Product_MatrixPfS_ii:
.LFB3673:
.cfi_startproc
endbr64
movq %rdi, %r9
movl %edx, %edi
movslq %edx, %r8
salq $2, %r8
movl %ecx, %eax
cltd
idivl %edi
movl %eax, %ecx
imull %edi, %ecx
movslq %ecx, %rax
movslq %edx, %rdx
addq %rdx, %rax
leaq (%r9,%rax,4), %rcx
movq %rsi, %rdx
pxor %xmm1, %xmm1
movl $0, %esi
jmp .L39
.L43:
addl $3, %esi
addq %r8, %rcx
addq $12, %rdx
cmpl $9, %esi
je .L38
.L39:
movl $0, %eax
.L40:
movss (%rcx,%rax), %xmm0
mulss (%rdx,%rax), %xmm0
addss %xmm0, %xmm1
addq $4, %rax
cmpq $12, %rax
jne .L40
jmp .L43
.L38:
movaps %xmm1, %xmm0
ret
.cfi_endproc
.LFE3673:
.size _Z14Product_MatrixPfS_ii, .-_Z14Product_MatrixPfS_ii
.globl _Z8max_poolPfiii
.type _Z8max_poolPfiii, @function
_Z8max_poolPfiii:
.LFB3674:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3674:
.size _Z8max_poolPfiii, .-_Z8max_poolPfiii
.globl _Z37__device_stub__Z11convolucionPfS_S_iiPfS_S_ii
.type _Z37__device_stub__Z11convolucionPfS_S_iiPfS_S_ii, @function
_Z37__device_stub__Z11convolucionPfS_S_iiPfS_S_ii:
.LFB3700:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L50
.L46:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L51
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L50:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11convolucionPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L46
.L51:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3700:
.size _Z37__device_stub__Z11convolucionPfS_S_iiPfS_S_ii, .-_Z37__device_stub__Z11convolucionPfS_S_iiPfS_S_ii
.globl _Z11convolucionPfS_S_ii
.type _Z11convolucionPfS_S_ii, @function
_Z11convolucionPfS_S_ii:
.LFB3701:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z11convolucionPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _Z11convolucionPfS_S_ii, .-_Z11convolucionPfS_S_ii
.section .rodata.str1.1
.LC10:
.string "img_test.txt"
.LC14:
.string "Tiempo: "
.LC15:
.string "[ms]"
.LC16:
.string "resultado.txt"
.text
.globl main
.type main, @function
main:
.LFB3675:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $216, %rsp
.cfi_def_cfa_offset 272
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
movss .LC8(%rip), %xmm1
movss %xmm1, 160(%rsp)
movss .LC9(%rip), %xmm0
movss %xmm0, 164(%rsp)
movl $0x00000000, 168(%rsp)
movss %xmm1, 172(%rsp)
movss %xmm0, 176(%rsp)
movl $0x00000000, 180(%rsp)
movss %xmm1, 184(%rsp)
movss %xmm0, 188(%rsp)
movl $0x00000000, 192(%rsp)
leaq 40(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdi
subq $8, %rsp
.cfi_def_cfa_offset 280
pushq $0
.cfi_def_cfa_offset 288
leaq .LC10(%rip), %r9
leaq 60(%rsp), %r8
call _Z4ReadPPfS0_S0_PiS1_PKci
movl 56(%rsp), %eax
movslq %eax, %r12
imulq $1431655766, %r12, %r12
shrq $32, %r12
sarl $31, %eax
subl %eax, %r12d
movl 60(%rsp), %eax
movslq %eax, %rbp
imulq $1431655766, %rbp, %rbp
shrq $32, %rbp
sarl $31, %eax
subl %eax, %ebp
movl %r12d, %ebx
imull %ebp, %ebx
movslq %ebx, %rbx
addq $16, %rsp
.cfi_def_cfa_offset 272
movabsq $2305843009213693950, %rax
cmpq %rbx, %rax
jb .L55
salq $2, %rbx
movq %rbx, %rdi
call _Znam@PLT
movq %rax, (%rsp)
movq %rbx, %rdi
call _Znam@PLT
movq %rax, 8(%rsp)
movq %rbx, %rdi
call _Znam@PLT
movq %rax, 16(%rsp)
pxor %xmm1, %xmm1
cvtsi2ssl %r12d, %xmm1
pxor %xmm2, %xmm2
cvtsi2ssl %ebp, %xmm2
movaps %xmm1, %xmm0
mulss %xmm2, %xmm0
mulss .LC11(%rip), %xmm0
movss %xmm0, 28(%rsp)
movss .LC17(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC12(%rip), %xmm3
ucomiss %xmm1, %xmm3
jbe .L56
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
movaps %xmm0, %xmm3
cmpnless %xmm1, %xmm3
movss .LC9(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm3, %xmm1
andnps %xmm0, %xmm2
orps %xmm2, %xmm1
movss %xmm1, 28(%rsp)
.L56:
movl 40(%rsp), %esi
imull 44(%rsp), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 72(%rsp), %rdi
call cudaMalloc@PLT
movl 40(%rsp), %esi
imull 44(%rsp), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 80(%rsp), %rdi
call cudaMalloc@PLT
movl 40(%rsp), %esi
imull 44(%rsp), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 88(%rsp), %rdi
call cudaMalloc@PLT
movq 48(%rsp), %r15
movl 40(%rsp), %edx
imull 44(%rsp), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r15, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movq 56(%rsp), %r14
movl 40(%rsp), %edx
imull 44(%rsp), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r14, %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movq 64(%rsp), %r13
movl 40(%rsp), %edx
imull 44(%rsp), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r13, %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
leaq 96(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 104(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 112(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 120(%rsp), %rdi
call cudaEventCreate@PLT
leaq 128(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 120(%rsp), %rdi
call cudaEventRecord@PLT
movl $256, 148(%rsp)
movl $1, 152(%rsp)
movl $1, 156(%rsp)
cvttss2sil 28(%rsp), %ebx
movl %ebx, 136(%rsp)
movl $1, 140(%rsp)
movl $1, 144(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 148(%rsp), %rdx
movl $1, %ecx
movq 136(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L68
.L57:
movl $256, 148(%rsp)
movl $1, 152(%rsp)
movl $1, 156(%rsp)
movl %ebx, 136(%rsp)
movl $1, 140(%rsp)
movl $1, 144(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 148(%rsp), %rdx
movl $1, %ecx
movq 136(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L69
.L60:
movl $256, 148(%rsp)
movl $1, 152(%rsp)
movl $1, 156(%rsp)
movl %ebx, 136(%rsp)
movl $1, 140(%rsp)
movl $1, 144(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 148(%rsp), %rdx
movl $1, %ecx
movq 136(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L70
.L61:
movl $0, %esi
movq 128(%rsp), %rdi
call cudaEventRecord@PLT
movq 128(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 148(%rsp), %rdi
movq 128(%rsp), %rdx
movq 120(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl 40(%rsp), %edx
imull 44(%rsp), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq 96(%rsp), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl 40(%rsp), %edx
imull 44(%rsp), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq 104(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl 40(%rsp), %edx
imull 44(%rsp), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq 112(%rsp), %rsi
movq 16(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC14(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 148(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC15(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC16(%rip), %r9
movl %ebp, %r8d
movl %r12d, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z5WritePfS_S_iiPKc
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 112(%rsp), %rdi
call cudaFree@PLT
testq %r15, %r15
je .L62
movq %r15, %rdi
call _ZdaPv@PLT
.L62:
testq %r14, %r14
je .L63
movq %r14, %rdi
call _ZdaPv@PLT
.L63:
testq %r13, %r13
je .L64
movq %r13, %rdi
call _ZdaPv@PLT
.L64:
movq (%rsp), %rdi
call _ZdaPv@PLT
movq 8(%rsp), %rdi
call _ZdaPv@PLT
movq 16(%rsp), %rdi
call _ZdaPv@PLT
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L71
movl $0, %eax
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L55:
.cfi_restore_state
movq 200(%rsp), %rax
subq %fs:40, %rax
je .L59
call __stack_chk_fail@PLT
.L59:
call __cxa_throw_bad_array_new_length@PLT
.L68:
leaq 160(%rsp), %rdx
movl %ebp, %r8d
movl 44(%rsp), %ecx
movq 96(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z37__device_stub__Z11convolucionPfS_S_iiPfS_S_ii
jmp .L57
.L69:
leaq 160(%rsp), %rdx
movl %ebp, %r8d
movl 44(%rsp), %ecx
movq 104(%rsp), %rsi
movq 80(%rsp), %rdi
call _Z37__device_stub__Z11convolucionPfS_S_iiPfS_S_ii
jmp .L60
.L70:
leaq 160(%rsp), %rdx
movl %ebp, %r8d
movl 44(%rsp), %ecx
movq 112(%rsp), %rsi
movq 88(%rsp), %rdi
call _Z37__device_stub__Z11convolucionPfS_S_iiPfS_S_ii
jmp .L61
.L71:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3675:
.size main, .-main
.globl _Z29__device_stub__Z7poolingPfS_iPfS_i
.type _Z29__device_stub__Z7poolingPfS_iPfS_i, @function
_Z29__device_stub__Z7poolingPfS_iPfS_i:
.LFB3702:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L76
.L72:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L77
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L76:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7poolingPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L72
.L77:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3702:
.size _Z29__device_stub__Z7poolingPfS_iPfS_i, .-_Z29__device_stub__Z7poolingPfS_iPfS_i
.globl _Z7poolingPfS_i
.type _Z7poolingPfS_i, @function
_Z7poolingPfS_i:
.LFB3703:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7poolingPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3703:
.size _Z7poolingPfS_i, .-_Z7poolingPfS_i
.section .rodata.str1.1
.LC18:
.string "_Z7poolingPfS_i"
.LC19:
.string "_Z11convolucionPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3705:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z7poolingPfS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z11convolucionPfS_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3705:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC8:
.long -1082130432
.align 4
.LC9:
.long 1065353216
.align 4
.LC11:
.long 998244352
.align 4
.LC12:
.long 1258291200
.align 4
.LC17:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cuda_runtime.h>
#include <stdlib.h>
#include <time.h>
// Variables globales GPU y CPU
#define l_kernel 3
#define stride 3
/******************************
* Procesamiento Matriz CPU *
******************************/
/*
* Funcion Max
*/
float MaxCPU(float A, float B){
float result = A > B ? A : B;
return result;
}
/*
* Lectura Archivo
*/
void Read(float** R, float** G, float** B, int *M, int *N, const char *filename, int tipo) {
FILE *fp;
fp = fopen(filename, "r");
fscanf(fp, "%d %d\n", M, N);
int imsize = (*M) * (*N);
float* R1 = new float[imsize];
float* G1 = new float[imsize];
float* B1 = new float[imsize];
if (tipo == 0){ // Lectura normal
for(int i = 0; i < imsize; i++)
fscanf(fp, "%f ", &(R1[i]));
for(int i = 0; i < imsize; i++)
fscanf(fp, "%f ", &(G1[i]));
for(int i = 0; i < imsize; i++)
fscanf(fp, "%f ", &(B1[i]));
}
fclose(fp);
*R = R1; *G = G1; *B = B1;
}
/*
* Escritura Archivo
*/
void Write(float* R, float* G, float* B,
int M, int N, const char *filename) {
FILE *fp;
fp = fopen(filename, "w");
fprintf(fp, "%d %d\n", M, N);
for(int i = 0; i < M*N-1; i++)
fprintf(fp, "%f ", R[i]);
fprintf(fp, "%f\n", R[M*N-1]);
for(int i = 0; i < M*N-1; i++)
fprintf(fp, "%f ", G[i]);
fprintf(fp, "%f\n", G[M*N-1]);
for(int i = 0; i < M*N-1; i++)
fprintf(fp, "%f ", B[i]);
fprintf(fp, "%f\n", B[M*N-1]);
fclose(fp);
}
/*
* Imprimir Array como matriz
*/
void ShowMatrix(float *matrix, int N, int M) {
for(int i = 0; i < N; i++){
for(int j = 0; j < M; j++)
printf("%.1f ", matrix[j + i*M]);
printf("\n");
}
printf("\n");
}
/*
* "Producto" Matricial sub_A * kernel = C
* id: id del primer elemento de la submatriz, N: ancho matriz R,G,B
*/
float Product_Matrix(float *A, float *B, int N, int id){
int col, row, idx_kernel;
float count;
col = id%N;
row = id/N;
count = 0.0;
// Recorremos stride
idx_kernel = 0;
for(int i=row; i < row+l_kernel; i++){
for(int j=col; j< col+l_kernel; j++){
int id_casilla = j + i*N;
// printf("%.1f x %.1f\n", A[id_casilla], B[idx_kernel]);
count += A[id_casilla] * B[idx_kernel];
idx_kernel += 1;
}
}
return count;
}
__global__ void convolucion(float *f, float *f_out ,float* kernel, int N, int Nres){
int tid = threadIdx.x + blockDim.x * blockIdx.x;
int x,y;
if(tid < 800*800){ //1 thread para cada pixel de salida
x = 1 + (tid%Nres)*stride; //coordenaas del centro de cada sub_matriz
y = 1 + (tid/Nres)*stride;
float suma = 0;
int indice_sub_matriz, indice_kernel;
for (int i = -1; i<=1 ; i++){
for (int j = -1; j <= 1; j++){
indice_sub_matriz = (x+i) + (y+j)*N;
indice_kernel = (1+i) + (1+j)*3;
suma += f[indice_sub_matriz] * kernel[indice_kernel];
}
}
printf("%f\n", suma);
f_out[tid] = suma;
}
}
__device__ float max_pool(float *f, int N, int x, int y){
//recorre una sub matriz de 2x2 y encuentra el valor máximo
float valores[4] = {
f[(x+0) + (y+0)*N],
f[(x+1) + (y+0)*N],
f[(x+0) + (y+1)*N],
f[(x+1) + (y+1)*N]
};
int max = 0;
for (int i = 0; i< 4; i++){
if (valores[i] > max){
max = valores[i];
}
}
return max;
}
__global__ void pooling(float *f, float *f_out, int N){
int tid = threadIdx.x + blockDim.x * blockIdx.x;
int x,y;
if(tid < 400*400){ //1 thread para cada pixel de salida
x = 1 + (tid%N)*stride;
y = 1 + (tid/N)*stride;
f_out[tid] = max_pool(f, N , x, y);
}
}
/*
* Codigo Principal
*/
int main(int argc, char **argv){
/*
* Inicializacion
*/
int M, N;
float kernel[l_kernel*l_kernel] = {-1, 1, 0, -1, 1, 0 ,-1, 1, 0}; // filtro a usar
float *Rhost, *Ghost, *Bhost;
float *Rhostout, *Ghostout, *Bhostout;
float *R, *G, *B;
float *Rout, *Gout, *Bout;
int gs, bs = 256;
float dt;
cudaEvent_t ct1, ct2;
// Lectura de archivo
Read(&Rhost, &Ghost, &Bhost, &M, &N, "img_test.txt", 0);
int Mres = M/l_kernel;
int Nres = N/l_kernel;
Rhostout = new float[Mres*Nres];
Ghostout = new float[Mres*Nres];
Bhostout = new float[Mres*Nres];
/*
* Parte GPU
*/
gs = (int)ceil((float) Mres*Nres / bs);
cudaMalloc((void**)&R, M * N * sizeof(float));
cudaMalloc((void**)&G, M * N * sizeof(float));
cudaMalloc((void**)&B, M * N * sizeof(float));
cudaMemcpy(R, Rhost, M * N * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(G, Ghost, M * N * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(B, Bhost, M * N * sizeof(float), cudaMemcpyHostToDevice);
cudaMalloc((void**)&Rout, Mres * Nres * sizeof(float));
cudaMalloc((void**)&Gout, Mres * Nres * sizeof(float));
cudaMalloc((void**)&Bout, Mres * Nres * sizeof(float));
cudaEventCreate(&ct1);
cudaEventCreate(&ct2);
cudaEventRecord(ct1);
convolucion<<<gs, bs>>>(R, Rout, kernel, N, Nres);
convolucion<<<gs, bs>>>(G, Gout, kernel, N, Nres);
convolucion<<<gs, bs>>>(B, Bout, kernel, N, Nres);
cudaEventRecord(ct2);
cudaEventSynchronize(ct2);
cudaEventElapsedTime(&dt, ct1, ct2);
cudaMemcpy(Rhostout, Rout, M * N * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(Ghostout, Gout, M * N * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(Bhostout, Bout, M * N * sizeof(float), cudaMemcpyHostToDevice);
std::cout << "Tiempo: " << dt << "[ms]" << std::endl;
Write(Rhostout, Ghostout, Bhostout, Mres, Nres, "resultado.txt");
/*
* Memoria Global
*/
/*
* Memoria Compartida
*/
cudaFree(R); cudaFree(G); cudaFree(B);
cudaFree(Rout); cudaFree(Gout); cudaFree(Bout);
delete[] Rhost; delete[] Ghost; delete[] Bhost;
delete[] Rhostout; delete[] Ghostout; delete[] Bhostout;
return 0;
} | #include <iostream>
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <time.h>
// Variables globales GPU y CPU
#define l_kernel 3
#define stride 3
/******************************
* Procesamiento Matriz CPU *
******************************/
/*
* Funcion Max
*/
float MaxCPU(float A, float B){
float result = A > B ? A : B;
return result;
}
/*
* Lectura Archivo
*/
void Read(float** R, float** G, float** B, int *M, int *N, const char *filename, int tipo) {
FILE *fp;
fp = fopen(filename, "r");
fscanf(fp, "%d %d\n", M, N);
int imsize = (*M) * (*N);
float* R1 = new float[imsize];
float* G1 = new float[imsize];
float* B1 = new float[imsize];
if (tipo == 0){ // Lectura normal
for(int i = 0; i < imsize; i++)
fscanf(fp, "%f ", &(R1[i]));
for(int i = 0; i < imsize; i++)
fscanf(fp, "%f ", &(G1[i]));
for(int i = 0; i < imsize; i++)
fscanf(fp, "%f ", &(B1[i]));
}
fclose(fp);
*R = R1; *G = G1; *B = B1;
}
/*
* Escritura Archivo
*/
void Write(float* R, float* G, float* B,
int M, int N, const char *filename) {
FILE *fp;
fp = fopen(filename, "w");
fprintf(fp, "%d %d\n", M, N);
for(int i = 0; i < M*N-1; i++)
fprintf(fp, "%f ", R[i]);
fprintf(fp, "%f\n", R[M*N-1]);
for(int i = 0; i < M*N-1; i++)
fprintf(fp, "%f ", G[i]);
fprintf(fp, "%f\n", G[M*N-1]);
for(int i = 0; i < M*N-1; i++)
fprintf(fp, "%f ", B[i]);
fprintf(fp, "%f\n", B[M*N-1]);
fclose(fp);
}
/*
* Imprimir Array como matriz
*/
void ShowMatrix(float *matrix, int N, int M) {
for(int i = 0; i < N; i++){
for(int j = 0; j < M; j++)
printf("%.1f ", matrix[j + i*M]);
printf("\n");
}
printf("\n");
}
/*
* "Producto" Matricial sub_A * kernel = C
* id: id del primer elemento de la submatriz, N: ancho matriz R,G,B
*/
float Product_Matrix(float *A, float *B, int N, int id){
int col, row, idx_kernel;
float count;
col = id%N;
row = id/N;
count = 0.0;
// Recorremos stride
idx_kernel = 0;
for(int i=row; i < row+l_kernel; i++){
for(int j=col; j< col+l_kernel; j++){
int id_casilla = j + i*N;
// printf("%.1f x %.1f\n", A[id_casilla], B[idx_kernel]);
count += A[id_casilla] * B[idx_kernel];
idx_kernel += 1;
}
}
return count;
}
__global__ void convolucion(float *f, float *f_out ,float* kernel, int N, int Nres){
int tid = threadIdx.x + blockDim.x * blockIdx.x;
int x,y;
if(tid < 800*800){ //1 thread para cada pixel de salida
x = 1 + (tid%Nres)*stride; //coordenaas del centro de cada sub_matriz
y = 1 + (tid/Nres)*stride;
float suma = 0;
int indice_sub_matriz, indice_kernel;
for (int i = -1; i<=1 ; i++){
for (int j = -1; j <= 1; j++){
indice_sub_matriz = (x+i) + (y+j)*N;
indice_kernel = (1+i) + (1+j)*3;
suma += f[indice_sub_matriz] * kernel[indice_kernel];
}
}
printf("%f\n", suma);
f_out[tid] = suma;
}
}
__device__ float max_pool(float *f, int N, int x, int y){
//recorre una sub matriz de 2x2 y encuentra el valor máximo
float valores[4] = {
f[(x+0) + (y+0)*N],
f[(x+1) + (y+0)*N],
f[(x+0) + (y+1)*N],
f[(x+1) + (y+1)*N]
};
int max = 0;
for (int i = 0; i< 4; i++){
if (valores[i] > max){
max = valores[i];
}
}
return max;
}
__global__ void pooling(float *f, float *f_out, int N){
int tid = threadIdx.x + blockDim.x * blockIdx.x;
int x,y;
if(tid < 400*400){ //1 thread para cada pixel de salida
x = 1 + (tid%N)*stride;
y = 1 + (tid/N)*stride;
f_out[tid] = max_pool(f, N , x, y);
}
}
/*
* Codigo Principal
*/
int main(int argc, char **argv){
/*
* Inicializacion
*/
int M, N;
float kernel[l_kernel*l_kernel] = {-1, 1, 0, -1, 1, 0 ,-1, 1, 0}; // filtro a usar
float *Rhost, *Ghost, *Bhost;
float *Rhostout, *Ghostout, *Bhostout;
float *R, *G, *B;
float *Rout, *Gout, *Bout;
int gs, bs = 256;
float dt;
hipEvent_t ct1, ct2;
// Lectura de archivo
Read(&Rhost, &Ghost, &Bhost, &M, &N, "img_test.txt", 0);
int Mres = M/l_kernel;
int Nres = N/l_kernel;
Rhostout = new float[Mres*Nres];
Ghostout = new float[Mres*Nres];
Bhostout = new float[Mres*Nres];
/*
* Parte GPU
*/
gs = (int)ceil((float) Mres*Nres / bs);
hipMalloc((void**)&R, M * N * sizeof(float));
hipMalloc((void**)&G, M * N * sizeof(float));
hipMalloc((void**)&B, M * N * sizeof(float));
hipMemcpy(R, Rhost, M * N * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(G, Ghost, M * N * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(B, Bhost, M * N * sizeof(float), hipMemcpyHostToDevice);
hipMalloc((void**)&Rout, Mres * Nres * sizeof(float));
hipMalloc((void**)&Gout, Mres * Nres * sizeof(float));
hipMalloc((void**)&Bout, Mres * Nres * sizeof(float));
hipEventCreate(&ct1);
hipEventCreate(&ct2);
hipEventRecord(ct1);
convolucion<<<gs, bs>>>(R, Rout, kernel, N, Nres);
convolucion<<<gs, bs>>>(G, Gout, kernel, N, Nres);
convolucion<<<gs, bs>>>(B, Bout, kernel, N, Nres);
hipEventRecord(ct2);
hipEventSynchronize(ct2);
hipEventElapsedTime(&dt, ct1, ct2);
hipMemcpy(Rhostout, Rout, M * N * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(Ghostout, Gout, M * N * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(Bhostout, Bout, M * N * sizeof(float), hipMemcpyHostToDevice);
std::cout << "Tiempo: " << dt << "[ms]" << std::endl;
Write(Rhostout, Ghostout, Bhostout, Mres, Nres, "resultado.txt");
/*
* Memoria Global
*/
/*
* Memoria Compartida
*/
hipFree(R); hipFree(G); hipFree(B);
hipFree(Rout); hipFree(Gout); hipFree(Bout);
delete[] Rhost; delete[] Ghost; delete[] Bhost;
delete[] Rhostout; delete[] Ghostout; delete[] Bhostout;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <iostream>
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <time.h>
// Variables globales GPU y CPU
#define l_kernel 3
#define stride 3
/******************************
* Procesamiento Matriz CPU *
******************************/
/*
* Funcion Max
*/
float MaxCPU(float A, float B){
float result = A > B ? A : B;
return result;
}
/*
* Lectura Archivo
*/
void Read(float** R, float** G, float** B, int *M, int *N, const char *filename, int tipo) {
FILE *fp;
fp = fopen(filename, "r");
fscanf(fp, "%d %d\n", M, N);
int imsize = (*M) * (*N);
float* R1 = new float[imsize];
float* G1 = new float[imsize];
float* B1 = new float[imsize];
if (tipo == 0){ // Lectura normal
for(int i = 0; i < imsize; i++)
fscanf(fp, "%f ", &(R1[i]));
for(int i = 0; i < imsize; i++)
fscanf(fp, "%f ", &(G1[i]));
for(int i = 0; i < imsize; i++)
fscanf(fp, "%f ", &(B1[i]));
}
fclose(fp);
*R = R1; *G = G1; *B = B1;
}
/*
* Escritura Archivo
*/
void Write(float* R, float* G, float* B,
int M, int N, const char *filename) {
FILE *fp;
fp = fopen(filename, "w");
fprintf(fp, "%d %d\n", M, N);
for(int i = 0; i < M*N-1; i++)
fprintf(fp, "%f ", R[i]);
fprintf(fp, "%f\n", R[M*N-1]);
for(int i = 0; i < M*N-1; i++)
fprintf(fp, "%f ", G[i]);
fprintf(fp, "%f\n", G[M*N-1]);
for(int i = 0; i < M*N-1; i++)
fprintf(fp, "%f ", B[i]);
fprintf(fp, "%f\n", B[M*N-1]);
fclose(fp);
}
/*
* Imprimir Array como matriz
*/
void ShowMatrix(float *matrix, int N, int M) {
for(int i = 0; i < N; i++){
for(int j = 0; j < M; j++)
printf("%.1f ", matrix[j + i*M]);
printf("\n");
}
printf("\n");
}
/*
* "Producto" Matricial sub_A * kernel = C
* id: id del primer elemento de la submatriz, N: ancho matriz R,G,B
*/
float Product_Matrix(float *A, float *B, int N, int id){
int col, row, idx_kernel;
float count;
col = id%N;
row = id/N;
count = 0.0;
// Recorremos stride
idx_kernel = 0;
for(int i=row; i < row+l_kernel; i++){
for(int j=col; j< col+l_kernel; j++){
int id_casilla = j + i*N;
// printf("%.1f x %.1f\n", A[id_casilla], B[idx_kernel]);
count += A[id_casilla] * B[idx_kernel];
idx_kernel += 1;
}
}
return count;
}
__global__ void convolucion(float *f, float *f_out ,float* kernel, int N, int Nres){
int tid = threadIdx.x + blockDim.x * blockIdx.x;
int x,y;
if(tid < 800*800){ //1 thread para cada pixel de salida
x = 1 + (tid%Nres)*stride; //coordenaas del centro de cada sub_matriz
y = 1 + (tid/Nres)*stride;
float suma = 0;
int indice_sub_matriz, indice_kernel;
for (int i = -1; i<=1 ; i++){
for (int j = -1; j <= 1; j++){
indice_sub_matriz = (x+i) + (y+j)*N;
indice_kernel = (1+i) + (1+j)*3;
suma += f[indice_sub_matriz] * kernel[indice_kernel];
}
}
printf("%f\n", suma);
f_out[tid] = suma;
}
}
__device__ float max_pool(float *f, int N, int x, int y){
//recorre una sub matriz de 2x2 y encuentra el valor máximo
float valores[4] = {
f[(x+0) + (y+0)*N],
f[(x+1) + (y+0)*N],
f[(x+0) + (y+1)*N],
f[(x+1) + (y+1)*N]
};
int max = 0;
for (int i = 0; i< 4; i++){
if (valores[i] > max){
max = valores[i];
}
}
return max;
}
__global__ void pooling(float *f, float *f_out, int N){
int tid = threadIdx.x + blockDim.x * blockIdx.x;
int x,y;
if(tid < 400*400){ //1 thread para cada pixel de salida
x = 1 + (tid%N)*stride;
y = 1 + (tid/N)*stride;
f_out[tid] = max_pool(f, N , x, y);
}
}
/*
* Codigo Principal
*/
int main(int argc, char **argv){
/*
* Inicializacion
*/
int M, N;
float kernel[l_kernel*l_kernel] = {-1, 1, 0, -1, 1, 0 ,-1, 1, 0}; // filtro a usar
float *Rhost, *Ghost, *Bhost;
float *Rhostout, *Ghostout, *Bhostout;
float *R, *G, *B;
float *Rout, *Gout, *Bout;
int gs, bs = 256;
float dt;
hipEvent_t ct1, ct2;
// Lectura de archivo
Read(&Rhost, &Ghost, &Bhost, &M, &N, "img_test.txt", 0);
int Mres = M/l_kernel;
int Nres = N/l_kernel;
Rhostout = new float[Mres*Nres];
Ghostout = new float[Mres*Nres];
Bhostout = new float[Mres*Nres];
/*
* Parte GPU
*/
gs = (int)ceil((float) Mres*Nres / bs);
hipMalloc((void**)&R, M * N * sizeof(float));
hipMalloc((void**)&G, M * N * sizeof(float));
hipMalloc((void**)&B, M * N * sizeof(float));
hipMemcpy(R, Rhost, M * N * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(G, Ghost, M * N * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(B, Bhost, M * N * sizeof(float), hipMemcpyHostToDevice);
hipMalloc((void**)&Rout, Mres * Nres * sizeof(float));
hipMalloc((void**)&Gout, Mres * Nres * sizeof(float));
hipMalloc((void**)&Bout, Mres * Nres * sizeof(float));
hipEventCreate(&ct1);
hipEventCreate(&ct2);
hipEventRecord(ct1);
convolucion<<<gs, bs>>>(R, Rout, kernel, N, Nres);
convolucion<<<gs, bs>>>(G, Gout, kernel, N, Nres);
convolucion<<<gs, bs>>>(B, Bout, kernel, N, Nres);
hipEventRecord(ct2);
hipEventSynchronize(ct2);
hipEventElapsedTime(&dt, ct1, ct2);
hipMemcpy(Rhostout, Rout, M * N * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(Ghostout, Gout, M * N * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(Bhostout, Bout, M * N * sizeof(float), hipMemcpyHostToDevice);
std::cout << "Tiempo: " << dt << "[ms]" << std::endl;
Write(Rhostout, Ghostout, Bhostout, Mres, Nres, "resultado.txt");
/*
* Memoria Global
*/
/*
* Memoria Compartida
*/
hipFree(R); hipFree(G); hipFree(B);
hipFree(Rout); hipFree(Gout); hipFree(Bout);
delete[] Rhost; delete[] Ghost; delete[] Bhost;
delete[] Rhostout; delete[] Ghostout; delete[] Bhostout;
return 0;
} | .text
.file "streams.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z6MaxCPUff # -- Begin function _Z6MaxCPUff
.p2align 4, 0x90
.type _Z6MaxCPUff,@function
_Z6MaxCPUff: # @_Z6MaxCPUff
.cfi_startproc
# %bb.0:
maxss %xmm1, %xmm0
retq
.Lfunc_end0:
.size _Z6MaxCPUff, .Lfunc_end0-_Z6MaxCPUff
.cfi_endproc
# -- End function
.globl _Z4ReadPPfS0_S0_PiS1_PKci # -- Begin function _Z4ReadPPfS0_S0_PiS1_PKci
.p2align 4, 0x90
.type _Z4ReadPPfS0_S0_PiS1_PKci,@function
_Z4ReadPPfS0_S0_PiS1_PKci: # @_Z4ReadPPfS0_S0_PiS1_PKci
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %rbx
movq %rcx, %r14
movq %rdx, 32(%rsp) # 8-byte Spill
movq %rsi, 24(%rsp) # 8-byte Spill
movq %rdi, 16(%rsp) # 8-byte Spill
movl $.L.str, %esi
movq %r9, %rdi
callq fopen
movq %rax, %r12
movl $.L.str.1, %esi
movq %rax, %rdi
movq %r14, %rdx
movq %rbx, %rcx
xorl %eax, %eax
callq __isoc23_fscanf
movslq (%r14), %rax
movslq (%rbx), %r15
imulq %rax, %r15
movq %r15, %rax
shlq $2, %rax
testl %r15d, %r15d
movq $-1, %rbx
cmovnsq %rax, %rbx
movq %rbx, %rdi
callq _Znam
movq %rax, %r14
movq %rbx, %rdi
callq _Znam
movq %rax, 8(%rsp) # 8-byte Spill
movq %rbx, %rdi
callq _Znam
movq %rax, %rbx
cmpl $0, 96(%rsp)
jne .LBB1_10
# %bb.1: # %.preheader38
movq %r14, (%rsp) # 8-byte Spill
movl %r15d, %ebp
testl %r15d, %r15d
jle .LBB1_4
# %bb.2: # %.lr.ph.preheader
movq %rbp, %r14
movq (%rsp), %r13 # 8-byte Reload
.p2align 4, 0x90
.LBB1_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.2, %esi
movq %r12, %rdi
movq %r13, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
addq $4, %r13
decq %r14
jne .LBB1_3
.LBB1_4: # %.preheader37
testl %r15d, %r15d
jle .LBB1_7
# %bb.5: # %.lr.ph41.preheader
movq %rbp, %r14
movq 8(%rsp), %r13 # 8-byte Reload
.p2align 4, 0x90
.LBB1_6: # %.lr.ph41
# =>This Inner Loop Header: Depth=1
movl $.L.str.2, %esi
movq %r12, %rdi
movq %r13, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
addq $4, %r13
decq %r14
jne .LBB1_6
.LBB1_7: # %.preheader
testl %r15d, %r15d
movq (%rsp), %r14 # 8-byte Reload
jle .LBB1_10
# %bb.8: # %.lr.ph43.preheader
movq %rbx, %r13
.p2align 4, 0x90
.LBB1_9: # %.lr.ph43
# =>This Inner Loop Header: Depth=1
movl $.L.str.2, %esi
movq %r12, %rdi
movq %r13, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
addq $4, %r13
decq %rbp
jne .LBB1_9
.LBB1_10: # %.loopexit
movq %r12, %rdi
callq fclose
movq 16(%rsp), %rax # 8-byte Reload
movq %r14, (%rax)
movq 24(%rsp), %rax # 8-byte Reload
movq 8(%rsp), %rcx # 8-byte Reload
movq %rcx, (%rax)
movq 32(%rsp), %rax # 8-byte Reload
movq %rbx, (%rax)
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z4ReadPPfS0_S0_PiS1_PKci, .Lfunc_end1-_Z4ReadPPfS0_S0_PiS1_PKci
.cfi_endproc
# -- End function
.globl _Z5WritePfS_S_iiPKc # -- Begin function _Z5WritePfS_S_iiPKc
.p2align 4, 0x90
.type _Z5WritePfS_S_iiPKc,@function
_Z5WritePfS_S_iiPKc: # @_Z5WritePfS_S_iiPKc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, %r15d
movl %ecx, %ebp
movq %rdx, %r14
movq %rsi, %r12
movq %rdi, %r13
movl $.L.str.3, %esi
movq %r9, %rdi
callq fopen
movq %rax, %rbx
movl $.L.str.1, %esi
movq %rax, %rdi
movl %ebp, %edx
movl %r15d, %ecx
xorl %eax, %eax
callq fprintf
imull %ebp, %r15d
leal -1(%r15), %eax
movl %eax, 8(%rsp) # 4-byte Spill
movl %eax, %ebp
movq %r15, 16(%rsp) # 8-byte Spill
cmpl $2, %r15d
jl .LBB2_3
# %bb.1: # %.lr.ph.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%r13,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %esi
movq %rbx, %rdi
movb $1, %al
callq fprintf
incq %r15
cmpq %r15, %rbp
jne .LBB2_2
.LBB2_3: # %._crit_edge
movslq 8(%rsp), %rax # 4-byte Folded Reload
movq %rax, 8(%rsp) # 8-byte Spill
movss (%r13,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %esi
movq %rbx, %rdi
movb $1, %al
callq fprintf
movq 16(%rsp), %r13 # 8-byte Reload
cmpl $2, %r13d
jl .LBB2_6
# %bb.4: # %.lr.ph43.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_5: # %.lr.ph43
# =>This Inner Loop Header: Depth=1
movss (%r12,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %esi
movq %rbx, %rdi
movb $1, %al
callq fprintf
incq %r15
cmpq %r15, %rbp
jne .LBB2_5
.LBB2_6: # %._crit_edge44
movq 8(%rsp), %rax # 8-byte Reload
movss (%r12,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %rax, %r12
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %esi
movq %rbx, %rdi
movb $1, %al
callq fprintf
cmpl $2, %r13d
jl .LBB2_9
# %bb.7: # %.lr.ph47.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_8: # %.lr.ph47
# =>This Inner Loop Header: Depth=1
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %esi
movq %rbx, %rdi
movb $1, %al
callq fprintf
incq %r15
cmpq %r15, %rbp
jne .LBB2_8
.LBB2_9: # %._crit_edge48
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %esi
movq %rbx, %rdi
movb $1, %al
callq fprintf
movq %rbx, %rdi
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end2:
.size _Z5WritePfS_S_iiPKc, .Lfunc_end2-_Z5WritePfS_S_iiPKc
.cfi_endproc
# -- End function
.globl _Z10ShowMatrixPfii # -- Begin function _Z10ShowMatrixPfii
.p2align 4, 0x90
.type _Z10ShowMatrixPfii,@function
_Z10ShowMatrixPfii: # @_Z10ShowMatrixPfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, 8(%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB3_6
# %bb.1: # %.preheader.lr.ph
movl %edx, %ebx
movl %esi, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %edx, %r12d
xorl %r13d, %r13d
xorl %ebp, %ebp
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_5: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %rbp
addl %ebx, %r13d
cmpq 16(%rsp), %rbp # 8-byte Folded Reload
je .LBB3_6
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
testl %ebx, %ebx
jle .LBB3_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB3_2 Depth=1
movl %r13d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_4: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r12
jne .LBB3_4
jmp .LBB3_5
.LBB3_6: # %._crit_edge14
movl $10, %edi
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp putchar@PLT # TAILCALL
.Lfunc_end3:
.size _Z10ShowMatrixPfii, .Lfunc_end3-_Z10ShowMatrixPfii
.cfi_endproc
# -- End function
.globl _Z14Product_MatrixPfS_ii # -- Begin function _Z14Product_MatrixPfS_ii
.p2align 4, 0x90
.type _Z14Product_MatrixPfS_ii,@function
_Z14Product_MatrixPfS_ii: # @_Z14Product_MatrixPfS_ii
.cfi_startproc
# %bb.0:
movl %ecx, %eax
movl %edx, %ecx
cltd
idivl %ecx
movslq %edx, %rdx
movslq %eax, %r8
movslq %ecx, %rax
leal 2(%rdx), %ecx
movslq %ecx, %rcx
leal 2(%r8), %r9d
movslq %r9d, %r9
movq %r8, %r10
imulq %rax, %r10
leaq (%rdi,%r10,4), %rdi
shlq $2, %rax
decq %rdx
xorps %xmm0, %xmm0
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB4_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_2 Depth 2
movslq %r10d, %r10
movq %rdx, %r11
.p2align 4, 0x90
.LBB4_2: # Parent Loop BB4_1 Depth=1
# => This Inner Loop Header: Depth=2
movss 4(%rdi,%r11,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rsi,%r10,4), %xmm1
addss %xmm1, %xmm0
incq %r10
incq %r11
cmpq %rcx, %r11
jl .LBB4_2
# %bb.3: # in Loop: Header=BB4_1 Depth=1
leaq 1(%r8), %r11
addq %rax, %rdi
cmpq %r9, %r8
movq %r11, %r8
jl .LBB4_1
# %bb.4:
retq
.Lfunc_end4:
.size _Z14Product_MatrixPfS_ii, .Lfunc_end4-_Z14Product_MatrixPfS_ii
.cfi_endproc
# -- End function
.globl _Z26__device_stub__convolucionPfS_S_ii # -- Begin function _Z26__device_stub__convolucionPfS_S_ii
.p2align 4, 0x90
.type _Z26__device_stub__convolucionPfS_S_ii,@function
_Z26__device_stub__convolucionPfS_S_ii: # @_Z26__device_stub__convolucionPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11convolucionPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end5:
.size _Z26__device_stub__convolucionPfS_S_ii, .Lfunc_end5-_Z26__device_stub__convolucionPfS_S_ii
.cfi_endproc
# -- End function
.globl _Z22__device_stub__poolingPfS_i # -- Begin function _Z22__device_stub__poolingPfS_i
.p2align 4, 0x90
.type _Z22__device_stub__poolingPfS_i,@function
_Z22__device_stub__poolingPfS_i: # @_Z22__device_stub__poolingPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7poolingPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end6:
.size _Z22__device_stub__poolingPfS_i, .Lfunc_end6-_Z22__device_stub__poolingPfS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI7_0:
.long 0x3b800000 # float 0.00390625
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 352
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorps %xmm0, %xmm0
movaps %xmm0, 240(%rsp)
movaps %xmm0, 256(%rsp)
movl $0, 272(%rsp)
movabsq $4575657224621260800, %rax # imm = 0x3F800000BF800000
movq %rax, 240(%rsp)
movl $-1082130432, 252(%rsp) # imm = 0xBF800000
movl $1065353216, 256(%rsp) # imm = 0x3F800000
movq %rax, 264(%rsp)
subq $8, %rsp
.cfi_adjust_cfa_offset 8
leaq 240(%rsp), %rdi
leaq 232(%rsp), %rsi
leaq 224(%rsp), %rdx
leaq 20(%rsp), %rcx
leaq 16(%rsp), %r8
movl $.L.str.7, %r9d
pushq $0
.cfi_adjust_cfa_offset 8
callq _Z4ReadPPfS0_S0_PiS1_PKci
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movslq 12(%rsp), %r14
imulq $1431655766, %r14, %r12 # imm = 0x55555556
movq %r12, %rax
shrq $63, %rax
shrq $32, %r12
addl %eax, %r12d
movslq 8(%rsp), %r15
imulq $1431655766, %r15, %r13 # imm = 0x55555556
movq %r13, %rax
shrq $63, %rax
shrq $32, %r13
addl %eax, %r13d
movl %r13d, %eax
imull %r12d, %eax
cltq
leaq (,%rax,4), %rbp
testl %eax, %eax
movq $-1, %rbx
cmovnsq %rbp, %rbx
movq %rbx, %rdi
callq _Znam
movq %rax, 288(%rsp) # 8-byte Spill
movq %rbx, %rdi
callq _Znam
movq %rax, 280(%rsp) # 8-byte Spill
movq %rbx, %rdi
callq _Znam
cvtsi2ss %r12d, %xmm1
xorps %xmm0, %xmm0
cvtsi2ss %r13d, %xmm0
movq %rax, 144(%rsp) # 8-byte Spill
mulss %xmm1, %xmm0
mulss .LCPI7_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %ebx
imull %r14d, %r15d
movslq %r15d, %rsi
shlq $2, %rsi
leaq 200(%rsp), %rdi
callq hipMalloc
movslq 12(%rsp), %rax
movslq 8(%rsp), %rsi
imulq %rax, %rsi
shlq $2, %rsi
leaq 192(%rsp), %rdi
callq hipMalloc
movslq 12(%rsp), %rax
movslq 8(%rsp), %rsi
imulq %rax, %rsi
shlq $2, %rsi
leaq 184(%rsp), %rdi
callq hipMalloc
movq 200(%rsp), %rdi
movq 232(%rsp), %rsi
movslq 12(%rsp), %rax
movslq 8(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movl $1, %ecx
callq hipMemcpy
movq 192(%rsp), %rdi
movq 224(%rsp), %rsi
movslq 12(%rsp), %rax
movslq 8(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movl $1, %ecx
callq hipMemcpy
movq 184(%rsp), %rdi
movq 216(%rsp), %rsi
movslq 12(%rsp), %rax
movslq 8(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 176(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 168(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 160(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 208(%rsp), %rdi
callq hipEventCreate
leaq 152(%rsp), %rdi
callq hipEventCreate
movq 208(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967552, %rax # imm = 0x100000100
leaq (%rbx,%rax), %rbp
addq $-256, %rbp
movq %rax, %rbx
movq %rbp, %rdi
movl $1, %esi
movq %rax, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_2
# %bb.1:
movq 200(%rsp), %rax
movq 176(%rsp), %rcx
movl 8(%rsp), %edx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 240(%rsp), %rax
movq %rax, 72(%rsp)
movl %edx, 20(%rsp)
movl %r13d, 16(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11convolucionPfS_S_ii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_2:
movq %rbp, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_4
# %bb.3:
movq 192(%rsp), %rax
movq 168(%rsp), %rcx
movl 8(%rsp), %edx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 240(%rsp), %rax
movq %rax, 72(%rsp)
movl %edx, 20(%rsp)
movl %r13d, 16(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11convolucionPfS_S_ii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_4:
movq %rbp, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
movq 288(%rsp), %r14 # 8-byte Reload
movq 280(%rsp), %r15 # 8-byte Reload
jne .LBB7_6
# %bb.5:
movq 184(%rsp), %rax
movq 160(%rsp), %rcx
movl 8(%rsp), %edx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 240(%rsp), %rax
movq %rax, 72(%rsp)
movl %edx, 20(%rsp)
movl %r13d, 16(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11convolucionPfS_S_ii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_6:
movq 152(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 152(%rsp), %rdi
callq hipEventSynchronize
movq 208(%rsp), %rsi
movq 152(%rsp), %rdx
leaq 96(%rsp), %rdi
callq hipEventElapsedTime
movq 176(%rsp), %rsi
movslq 12(%rsp), %rax
movslq 8(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %r14, %rdi
movl $1, %ecx
callq hipMemcpy
movq 168(%rsp), %rsi
movslq 12(%rsp), %rax
movslq 8(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %r15, %rdi
movl $1, %ecx
callq hipMemcpy
movq 160(%rsp), %rsi
movslq 12(%rsp), %rax
movslq 8(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq 144(%rsp), %rdi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 96(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbp
movl $.L.str.9, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbx
testq %rbx, %rbx
je .LBB7_17
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB7_9
# %bb.8:
movzbl 67(%rbx), %eax
jmp .LBB7_10
.LBB7_9:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB7_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %rbp, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $.L.str.10, %r9d
movq %r14, %rdi
movq %r15, %rsi
movq 144(%rsp), %rdx # 8-byte Reload
movl %r12d, %ecx
movl %r13d, %r8d
callq _Z5WritePfS_S_iiPKc
movq 200(%rsp), %rdi
callq hipFree
movq 192(%rsp), %rdi
callq hipFree
movq 184(%rsp), %rdi
callq hipFree
movq 176(%rsp), %rdi
callq hipFree
movq 168(%rsp), %rdi
callq hipFree
movq 160(%rsp), %rdi
callq hipFree
movq 232(%rsp), %rdi
testq %rdi, %rdi
je .LBB7_12
# %bb.11:
callq _ZdaPv
.LBB7_12:
movq 224(%rsp), %rdi
testq %rdi, %rdi
je .LBB7_14
# %bb.13:
callq _ZdaPv
.LBB7_14:
movq 216(%rsp), %rdi
testq %rdi, %rdi
je .LBB7_16
# %bb.15:
callq _ZdaPv
.LBB7_16:
movq %r14, %rdi
callq _ZdaPv
movq %r15, %rdi
callq _ZdaPv
movq 144(%rsp), %rdi # 8-byte Reload
callq _ZdaPv
xorl %eax, %eax
addq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB7_17:
.cfi_def_cfa_offset 352
callq _ZSt16__throw_bad_castv
.Lfunc_end7:
.size main, .Lfunc_end7-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11convolucionPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7poolingPfS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d %d\n"
.size .L.str.1, 7
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%f "
.size .L.str.2, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "w"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%f\n"
.size .L.str.4, 4
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%.1f "
.size .L.str.5, 6
.type _Z11convolucionPfS_S_ii,@object # @_Z11convolucionPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z11convolucionPfS_S_ii
.p2align 3, 0x0
_Z11convolucionPfS_S_ii:
.quad _Z26__device_stub__convolucionPfS_S_ii
.size _Z11convolucionPfS_S_ii, 8
.type _Z7poolingPfS_i,@object # @_Z7poolingPfS_i
.globl _Z7poolingPfS_i
.p2align 3, 0x0
_Z7poolingPfS_i:
.quad _Z22__device_stub__poolingPfS_i
.size _Z7poolingPfS_i, 8
.type .L.str.7,@object # @.str.7
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.7:
.asciz "img_test.txt"
.size .L.str.7, 13
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Tiempo: "
.size .L.str.8, 9
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "[ms]"
.size .L.str.9, 5
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "resultado.txt"
.size .L.str.10, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11convolucionPfS_S_ii"
.size .L__unnamed_1, 24
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7poolingPfS_i"
.size .L__unnamed_2, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__convolucionPfS_S_ii
.addrsig_sym _Z22__device_stub__poolingPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11convolucionPfS_S_ii
.addrsig_sym _Z7poolingPfS_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //
// Created by daniel on 10/23/20.
//
#include "brdf.cuh" | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //
// Created by daniel on 10/23/20.
//
#include "brdf.cuh" | .file "tmpxft_000f8081_00000000-6_brdf.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //
// Created by daniel on 10/23/20.
//
#include "brdf.cuh" | //
// Created by daniel on 10/23/20.
//
#ifndef POLYTOPE_BRDF_CUH
#define POLYTOPE_BRDF_CUH
#endif //POLYTOPE_BRDF_CUH |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //
// Created by daniel on 10/23/20.
//
#ifndef POLYTOPE_BRDF_CUH
#define POLYTOPE_BRDF_CUH
#endif //POLYTOPE_BRDF_CUH | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //
// Created by daniel on 10/23/20.
//
#ifndef POLYTOPE_BRDF_CUH
#define POLYTOPE_BRDF_CUH
#endif //POLYTOPE_BRDF_CUH | .text
.file "brdf.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f8081_00000000-6_brdf.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "brdf.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime_api.h>
#include <stdio.h>
#include <math.h>
#include <iostream>
__device__ float distance(float2 x1, float2 x2){
return sqrt(pow(x1.x - x2.x,2) + pow(x1.y - x2.y,2));
}
__global__ void distance_kernel(float2 *data_in, float *data_out, int n){
const int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i < n){
float2 ref;
ref.x = 0.0;
ref.y = 0.0;
data_out[i] = distance(data_in[i], ref);
}
}
void init_host_data(float2* h_in,int n){
for(int i = 0; i< n;i++){
h_in[i].x = (float)i /((n - 1) * M_PI * 100);
h_in[i].y = sin(h_in[i].x);
}
}
int main(){
float *d_out = NULL;
float2 *d_in = NULL;
float2 *h_in = NULL;
float *h_out = NULL;
int N = 4096;
int TPB = 32;
size_t in_size = N*2*sizeof(float);
size_t out_size = N*sizeof(float);
h_in = (float2*)malloc(in_size);
h_out = (float*)malloc(out_size);
//设备端分配内存
cudaMalloc((void**)&d_in, in_size);
cudaMalloc((void**)&d_out, out_size);
init_host_data(h_in, N);
//拷贝host数据到device
cudaMemcpy(d_in, h_in, in_size, cudaMemcpyHostToDevice);
distance_kernel<<<(N + TPB -1)/TPB,TPB>>>(d_in, d_out, N);
//拷贝device端计算结果到host
cudaMemcpy(h_out, d_out, out_size, cudaMemcpyDeviceToHost);
cudaFree(d_in);
cudaFree(d_out);
for(int i = 0;i < N;i++){
std::cout<<i<<":<"<<h_in[i].x<<","<<h_in[1].y<<">, dist:"<<h_out[i]<<std::endl;
}
free(h_in);
free(h_out);
return 0;
} | code for sm_80
Function : _Z15distance_kernelP6float2Pfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R4, R2, R5, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ BSSY B0, 0x130 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*00b0*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fe40000011402 */
/*00c0*/ MOV R0, 0x120 ; /* 0x0000012000007802 */
/* 0x000fe20000000f00 */
/*00d0*/ F2F.F64.F32 R6, R4 ; /* 0x0000000400067310 */
/* 0x004e240000201800 */
/*00e0*/ DADD R8, -RZ, |R6| ; /* 0x00000000ff087229 */
/* 0x001e140000000506 */
/*00f0*/ IMAD.MOV.U32 R14, RZ, RZ, R8 ; /* 0x000000ffff0e7224 */
/* 0x001fe400078e0008 */
/*0100*/ IMAD.MOV.U32 R12, RZ, RZ, R9 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0009 */
/*0110*/ CALL.REL.NOINC 0x920 ; /* 0x0000080000007944 */
/* 0x000fea0003c00000 */
/*0120*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0130*/ DADD R8, R6, 2 ; /* 0x4000000006087429 */
/* 0x000ea20000000000 */
/*0140*/ FSETP.NEU.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720b */
/* 0x000fe20003f0d000 */
/*0150*/ BSSY B0, 0x270 ; /* 0x0000011000007945 */
/* 0x000ff00003800000 */
/*0160*/ LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009087812 */
/* 0x004fe200078ec0ff */
/*0170*/ IMAD.MOV.U32 R9, RZ, RZ, R19 ; /* 0x000000ffff097224 */
/* 0x002fc600078e0013 */
/*0180*/ ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; /* 0x7ff000000800780c */
/* 0x000fe20003f25270 */
/*0190*/ IMAD.MOV.U32 R8, RZ, RZ, R18 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0012 */
/*01a0*/ @!P0 CS2R R8, SRZ ; /* 0x0000000000088805 */
/* 0x000fd6000001ff00 */
/*01b0*/ @P1 BRA 0x260 ; /* 0x000000a000001947 */
/* 0x000fea0003800000 */
/*01c0*/ DSETP.GTU.AND P0, PT, |R6|, +INF , PT ; /* 0x7ff000000600742a */
/* 0x000e5c0003f0c200 */
/*01d0*/ @P0 BRA 0x250 ; /* 0x0000007000000947 */
/* 0x002fea0003800000 */
/*01e0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f05270 */
/*01f0*/ LOP3.LUT R6, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07067812 */
/* 0x000fc800078ec0ff */
/*0200*/ ISETP.NE.OR P0, PT, R6, 0x7ff00000, P0 ; /* 0x7ff000000600780c */
/* 0x000fda0000705670 */
/*0210*/ @P0 BRA 0x260 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0220*/ IMAD.MOV.U32 R8, RZ, RZ, 0x0 ; /* 0x00000000ff087424 */
/* 0x000fe400078e00ff */
/*0230*/ IMAD.MOV.U32 R9, RZ, RZ, 0x7ff00000 ; /* 0x7ff00000ff097424 */
/* 0x000fe200078e00ff */
/*0240*/ BRA 0x260 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0250*/ DADD R8, R6, 2 ; /* 0x4000000006087429 */
/* 0x00028c0000000000 */
/*0260*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0270*/ F2F.F64.F32 R6, R5 ; /* 0x0000000500067310 */
/* 0x002e620000201800 */
/*0280*/ FSETP.NEU.AND P0, PT, R4, 1, PT ; /* 0x3f8000000400780b */
/* 0x000fe20003f0d000 */
/*0290*/ BSSY B0, 0x320 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*02a0*/ MOV R0, 0x310 ; /* 0x0000031000007802 */
/* 0x000fe40000000f00 */
/*02b0*/ FSEL R8, R8, RZ, P0 ; /* 0x000000ff08087208 */
/* 0x004fe40000000000 */
/*02c0*/ FSEL R9, R9, 1.875, P0 ; /* 0x3ff0000009097808 */
/* 0x000fe20000000000 */
/*02d0*/ DADD R10, -RZ, |R6| ; /* 0x00000000ff0a7229 */
/* 0x002e540000000506 */
/*02e0*/ IMAD.MOV.U32 R14, RZ, RZ, R10 ; /* 0x000000ffff0e7224 */
/* 0x002fe400078e000a */
/*02f0*/ IMAD.MOV.U32 R12, RZ, RZ, R11 ; /* 0x000000ffff0c7224 */
/* 0x001fe400078e000b */
/*0300*/ CALL.REL.NOINC 0x920 ; /* 0x0000061000007944 */
/* 0x000fea0003c00000 */
/*0310*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0320*/ DADD R10, R6, 2 ; /* 0x40000000060a7429 */
/* 0x000ea20000000000 */
/*0330*/ FSETP.NEU.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720b */
/* 0x000fe20003f0d000 */
/*0340*/ BSSY B0, 0x460 ; /* 0x0000011000007945 */
/* 0x000ff00003800000 */
/*0350*/ LOP3.LUT R10, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b0a7812 */
/* 0x004fe200078ec0ff */
/*0360*/ IMAD.MOV.U32 R11, RZ, RZ, R19 ; /* 0x000000ffff0b7224 */
/* 0x002fc600078e0013 */
/*0370*/ ISETP.NE.AND P1, PT, R10, 0x7ff00000, PT ; /* 0x7ff000000a00780c */
/* 0x000fe20003f25270 */
/*0380*/ IMAD.MOV.U32 R10, RZ, RZ, R18 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0012 */
/*0390*/ @!P0 CS2R R10, SRZ ; /* 0x00000000000a8805 */
/* 0x000fd6000001ff00 */
/*03a0*/ @P1 BRA 0x450 ; /* 0x000000a000001947 */
/* 0x000fea0003800000 */
/*03b0*/ DSETP.GTU.AND P0, PT, |R6|, +INF , PT ; /* 0x7ff000000600742a */
/* 0x000e5c0003f0c200 */
/*03c0*/ @P0 BRA 0x440 ; /* 0x0000007000000947 */
/* 0x002fea0003800000 */
/*03d0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f05270 */
/*03e0*/ LOP3.LUT R6, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07067812 */
/* 0x000fc800078ec0ff */
/*03f0*/ ISETP.NE.OR P0, PT, R6, 0x7ff00000, P0 ; /* 0x7ff000000600780c */
/* 0x000fda0000705670 */
/*0400*/ @P0 BRA 0x450 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0410*/ IMAD.MOV.U32 R10, RZ, RZ, 0x0 ; /* 0x00000000ff0a7424 */
/* 0x000fe400078e00ff */
/*0420*/ IMAD.MOV.U32 R11, RZ, RZ, 0x7ff00000 ; /* 0x7ff00000ff0b7424 */
/* 0x000fe200078e00ff */
/*0430*/ BRA 0x450 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0440*/ DADD R10, R6, 2 ; /* 0x40000000060a7429 */
/* 0x00028c0000000000 */
/*0450*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0460*/ FSETP.NEU.AND P0, PT, R5, 1, PT ; /* 0x3f8000000500780b */
/* 0x000fe20003f0d000 */
/*0470*/ BSSY B0, 0x5e0 ; /* 0x0000016000007945 */
/* 0x000fe60003800000 */
/*0480*/ FSEL R4, R10, RZ, P0 ; /* 0x000000ff0a047208 */
/* 0x004fe20000000000 */
/*0490*/ IMAD.MOV.U32 R10, RZ, RZ, 0x0 ; /* 0x00000000ff0a7424 */
/* 0x000fe200078e00ff */
/*04a0*/ FSEL R5, R11, 1.875, P0 ; /* 0x3ff000000b057808 */
/* 0x000fe20000000000 */
/*04b0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x3fd80000 ; /* 0x3fd80000ff0b7424 */
/* 0x000fca00078e00ff */
/*04c0*/ DADD R8, R8, R4 ; /* 0x0000000008087229 */
/* 0x000e8c0000000004 */
/*04d0*/ MUFU.RSQ64H R5, R9 ; /* 0x0000000900057308 */
/* 0x004ea80000001c00 */
/*04e0*/ IADD3 R4, R9, -0x3500000, RZ ; /* 0xfcb0000009047810 */
/* 0x000fc80007ffe0ff */
/*04f0*/ ISETP.GE.U32.AND P0, PT, R4, 0x7ca00000, PT ; /* 0x7ca000000400780c */
/* 0x000fe40003f06070 */
/*0500*/ DMUL R6, R4, R4 ; /* 0x0000000404067228 */
/* 0x006e4c0000000000 */
/*0510*/ DFMA R6, R8, -R6, 1 ; /* 0x3ff000000806742b */
/* 0x002e4c0000000806 */
/*0520*/ DFMA R10, R6, R10, 0.5 ; /* 0x3fe00000060a742b */
/* 0x002fc8000000000a */
/*0530*/ DMUL R6, R4, R6 ; /* 0x0000000604067228 */
/* 0x000e4c0000000000 */
/*0540*/ DFMA R12, R10, R6, R4 ; /* 0x000000060a0c722b */
/* 0x003e0c0000000004 */
/*0550*/ DMUL R14, R8, R12 ; /* 0x0000000c080e7228 */
/* 0x001e080000000000 */
/*0560*/ IADD3 R11, R13, -0x100000, RZ ; /* 0xfff000000d0b7810 */
/* 0x000fe20007ffe0ff */
/*0570*/ IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e000c */
/*0580*/ DFMA R16, R14, -R14, R8 ; /* 0x8000000e0e10722b */
/* 0x001e0c0000000008 */
/*0590*/ DFMA R6, R16, R10, R14 ; /* 0x0000000a1006722b */
/* 0x001062000000000e */
/*05a0*/ @!P0 BRA 0x5d0 ; /* 0x0000002000008947 */
/* 0x000fea0003800000 */
/*05b0*/ MOV R0, 0x5d0 ; /* 0x000005d000007802 */
/* 0x000fca0000000f00 */
/*05c0*/ CALL.REL.NOINC 0x630 ; /* 0x0000006000007944 */
/* 0x003fea0003c00000 */
/*05d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05e0*/ F2F.F32.F64 R7, R6 ; /* 0x0000000600077310 */
/* 0x002e620000301000 */
/*05f0*/ LEA R4, P0, R2, c[0x0][0x168], 0x2 ; /* 0x00005a0002047a11 */
/* 0x000fc800078010ff */
/*0600*/ LEA.HI.X R5, R2, c[0x0][0x16c], R3, 0x2, P0 ; /* 0x00005b0002057a11 */
/* 0x000fca00000f1403 */
/*0610*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x002fe2000c101904 */
/*0620*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0630*/ ISETP.GE.U32.AND P0, PT, R4, -0x3400000, PT ; /* 0xfcc000000400780c */
/* 0x000fe20003f06070 */
/*0640*/ BSSY B1, 0x8d0 ; /* 0x0000028000017945 */
/* 0x000fe20003800000 */
/*0650*/ IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e000c */
/*0660*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0008 */
/*0670*/ IMAD.MOV.U32 R7, RZ, RZ, R9 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0009 */
/*0680*/ IMAD.MOV.U32 R4, RZ, RZ, R16 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0010 */
/*0690*/ IMAD.MOV.U32 R5, RZ, RZ, R17 ; /* 0x000000ffff057224 */
/* 0x000fc600078e0011 */
/*06a0*/ @!P0 BRA 0x730 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*06b0*/ DFMA.RM R4, R4, R10, R14 ; /* 0x0000000a0404722b */
/* 0x000e14000000400e */
/*06c0*/ IADD3 R8, P0, R4, 0x1, RZ ; /* 0x0000000104087810 */
/* 0x001fca0007f1e0ff */
/*06d0*/ IMAD.X R9, RZ, RZ, R5, P0 ; /* 0x000000ffff097224 */
/* 0x000fcc00000e0605 */
/*06e0*/ DFMA.RP R6, -R4, R8, R6 ; /* 0x000000080406722b */
/* 0x000e0c0000008106 */
/*06f0*/ DSETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600722a */
/* 0x001e0c0003f04000 */
/*0700*/ FSEL R4, R8, R4, P0 ; /* 0x0000000408047208 */
/* 0x001fe40000000000 */
/*0710*/ FSEL R5, R9, R5, P0 ; /* 0x0000000509057208 */
/* 0x000fe20000000000 */
/*0720*/ BRA 0x8c0 ; /* 0x0000019000007947 */
/* 0x000fea0003800000 */
/*0730*/ DSETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600722a */
/* 0x000e1c0003f05000 */
/*0740*/ @!P0 BRA 0x8b0 ; /* 0x0000016000008947 */
/* 0x001fea0003800000 */
/*0750*/ ISETP.GE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f06270 */
/*0760*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, 0x0 ; /* 0x00000000ff048424 */
/* 0x000fe400078e00ff */
/*0770*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, -0x80000 ; /* 0xfff80000ff058424 */
/* 0x000fe200078e00ff */
/*0780*/ @!P0 BRA 0x8c0 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0790*/ ISETP.GT.AND P0, PT, R7, 0x7fefffff, PT ; /* 0x7fefffff0700780c */
/* 0x000fda0003f04270 */
/*07a0*/ @P0 BRA 0x8b0 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*07b0*/ DMUL R4, R6, 8.11296384146066816958e+31 ; /* 0x4690000006047828 */
/* 0x0000620000000000 */
/*07c0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x0 ; /* 0x00000000ff0a7424 */
/* 0x000fe400078e00ff */
/*07d0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe400078e00ff */
/*07e0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x3fd80000 ; /* 0x3fd80000ff0b7424 */
/* 0x000fe200078e00ff */
/*07f0*/ MUFU.RSQ64H R7, R5 ; /* 0x0000000500077308 */
/* 0x002e260000001c00 */
/*0800*/ DMUL R8, R6, R6 ; /* 0x0000000606087228 */
/* 0x001e0c0000000000 */
/*0810*/ DFMA R8, R4, -R8, 1 ; /* 0x3ff000000408742b */
/* 0x001e0c0000000808 */
/*0820*/ DFMA R10, R8, R10, 0.5 ; /* 0x3fe00000080a742b */
/* 0x001fc8000000000a */
/*0830*/ DMUL R8, R6, R8 ; /* 0x0000000806087228 */
/* 0x000e0c0000000000 */
/*0840*/ DFMA R8, R10, R8, R6 ; /* 0x000000080a08722b */
/* 0x001e0c0000000006 */
/*0850*/ DMUL R6, R4, R8 ; /* 0x0000000804067228 */
/* 0x0010480000000000 */
/*0860*/ IADD3 R9, R9, -0x100000, RZ ; /* 0xfff0000009097810 */
/* 0x001fe40007ffe0ff */
/*0870*/ DFMA R10, R6, -R6, R4 ; /* 0x80000006060a722b */
/* 0x002e0c0000000004 */
/*0880*/ DFMA R4, R8, R10, R6 ; /* 0x0000000a0804722b */
/* 0x001e140000000006 */
/*0890*/ IADD3 R5, R5, -0x3500000, RZ ; /* 0xfcb0000005057810 */
/* 0x001fe20007ffe0ff */
/*08a0*/ BRA 0x8c0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*08b0*/ DADD R4, R6, R6 ; /* 0x0000000006047229 */
/* 0x00004c0000000006 */
/*08c0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*08d0*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x003fe400078e0004 */
/*08e0*/ IMAD.MOV.U32 R7, RZ, RZ, R5 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0005 */
/*08f0*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*0900*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0910*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff6e004007950 */
/* 0x000fea0003c3ffff */
/*0920*/ SHF.R.U32.HI R28, RZ, 0x14, R12 ; /* 0x00000014ff1c7819 */
/* 0x000fe2000001160c */
/*0930*/ IMAD.MOV.U32 R10, RZ, RZ, R14 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e000e */
/*0940*/ IMAD.MOV.U32 R11, RZ, RZ, R12 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e000c */
/*0950*/ ISETP.NE.AND P0, PT, R28, RZ, PT ; /* 0x000000ff1c00720c */
/* 0x000fe20003f05270 */
/*0960*/ IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff127224 */
/* 0x000fe400078e00ff */
/*0970*/ IMAD.MOV.U32 R20, RZ, RZ, 0x7d2cafe2 ; /* 0x7d2cafe2ff147424 */
/* 0x000fe400078e00ff */
/*0980*/ IMAD.MOV.U32 R21, RZ, RZ, 0x3eb0f5ff ; /* 0x3eb0f5ffff157424 */
/* 0x000fd000078e00ff */
/*0990*/ @!P0 DMUL R10, R10, 1.80143985094819840000e+16 ; /* 0x435000000a0a8828 */
/* 0x000e140000000000 */
/*09a0*/ @!P0 IMAD.MOV.U32 R12, RZ, RZ, R11 ; /* 0x000000ffff0c8224 */
/* 0x001fe200078e000b */
/*09b0*/ @!P0 LEA.HI R28, R11, 0xffffffca, RZ, 0xc ; /* 0xffffffca0b1c8811 */
/* 0x000fe200078f60ff */
/*09c0*/ @!P0 IMAD.MOV.U32 R14, RZ, RZ, R10 ; /* 0x000000ffff0e8224 */
/* 0x000fe400078e000a */
/*09d0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x43300000 ; /* 0x43300000ff0b7424 */
/* 0x000fe200078e00ff */
/*09e0*/ LOP3.LUT R12, R12, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff0c0c7812 */
/* 0x000fe400078ec0ff */
/*09f0*/ IADD3 R10, R28, -0x3ff, RZ ; /* 0xfffffc011c0a7810 */
/* 0x000fe40007ffe0ff */
/*0a00*/ LOP3.LUT R15, R12, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff000000c0f7812 */
/* 0x000fc800078efcff */
/*0a10*/ ISETP.GE.U32.AND P1, PT, R15, 0x3ff6a09f, PT ; /* 0x3ff6a09f0f00780c */
/* 0x000fda0003f26070 */
/*0a20*/ @P1 IADD3 R13, R15, -0x100000, RZ ; /* 0xfff000000f0d1810 */
/* 0x000fe40007ffe0ff */
/*0a30*/ @P1 IADD3 R10, R28, -0x3fe, RZ ; /* 0xfffffc021c0a1810 */
/* 0x000fc60007ffe0ff */
/*0a40*/ @P1 IMAD.MOV.U32 R15, RZ, RZ, R13 ; /* 0x000000ffff0f1224 */
/* 0x000fe200078e000d */
/*0a50*/ LOP3.LUT R10, R10, 0x80000000, RZ, 0x3c, !PT ; /* 0x800000000a0a7812 */
/* 0x000fca00078e3cff */
/*0a60*/ DADD R16, R14, 1 ; /* 0x3ff000000e107429 */
/* 0x000e080000000000 */
/*0a70*/ DADD R14, R14, -1 ; /* 0xbff000000e0e7429 */
/* 0x000fe40000000000 */
/*0a80*/ MUFU.RCP64H R19, R17 ; /* 0x0000001100137308 */
/* 0x001e240000001800 */
/*0a90*/ DFMA R12, -R16, R18, 1 ; /* 0x3ff00000100c742b */
/* 0x001e0c0000000112 */
/*0aa0*/ DFMA R12, R12, R12, R12 ; /* 0x0000000c0c0c722b */
/* 0x001e0c000000000c */
/*0ab0*/ DFMA R18, R18, R12, R18 ; /* 0x0000000c1212722b */
/* 0x001e0c0000000012 */
/*0ac0*/ DMUL R12, R18, R14 ; /* 0x0000000e120c7228 */
/* 0x001e0c0000000000 */
/*0ad0*/ DFMA R12, R18, R14, R12 ; /* 0x0000000e120c722b */
/* 0x001e0c000000000c */
/*0ae0*/ DMUL R24, R12, R12 ; /* 0x0000000c0c187228 */
/* 0x001e080000000000 */
/*0af0*/ DADD R16, R14, -R12 ; /* 0x000000000e107229 */
/* 0x000e48000000080c */
/*0b00*/ DFMA R20, R24, R20, c[0x2][0x0] ; /* 0x008000001814762b */
/* 0x001e080000000014 */
/*0b10*/ DADD R16, R16, R16 ; /* 0x0000000010107229 */
/* 0x002e480000000010 */
/*0b20*/ DFMA R20, R24, R20, c[0x2][0x8] ; /* 0x008002001814762b */
/* 0x001e080000000014 */
/*0b30*/ DFMA R16, R14, -R12, R16 ; /* 0x8000000c0e10722b */
/* 0x002e480000000010 */
/*0b40*/ DFMA R20, R24, R20, c[0x2][0x10] ; /* 0x008004001814762b */
/* 0x001e080000000014 */
/*0b50*/ DMUL R16, R18, R16 ; /* 0x0000001012107228 */
/* 0x002fc80000000000 */
/*0b60*/ DFMA R22, R24, R20, c[0x2][0x18] ; /* 0x008006001816762b */
/* 0x001e080000000014 */
/*0b70*/ DMUL R18, R12, R12 ; /* 0x0000000c0c127228 */
/* 0x000fc80000000000 */
/*0b80*/ DFMA R22, R24, R22, c[0x2][0x20] ; /* 0x008008001816762b */
/* 0x001e0c0000000016 */
/*0b90*/ DFMA R22, R24, R22, c[0x2][0x28] ; /* 0x00800a001816762b */
/* 0x001e0c0000000016 */
/*0ba0*/ DFMA R14, R24, R22, c[0x2][0x30] ; /* 0x00800c00180e762b */
/* 0x001e0c0000000016 */
/*0bb0*/ DADD R20, -R14, c[0x2][0x30] ; /* 0x00800c000e147629 */
/* 0x001e0c0000000100 */
/*0bc0*/ DFMA R20, R24, R22, R20 ; /* 0x000000161814722b */
/* 0x0011e40000000014 */
/*0bd0*/ IADD3 R23, R17, 0x100000, RZ ; /* 0x0010000011177810 */
/* 0x001fe20007ffe0ff */
/*0be0*/ IMAD.MOV.U32 R22, RZ, RZ, R16 ; /* 0x000000ffff167224 */
/* 0x000fe200078e0010 */
/*0bf0*/ DFMA R24, R12, R12, -R18 ; /* 0x0000000c0c18722b */
/* 0x000e0c0000000812 */
/*0c00*/ DFMA R22, R12, R22, R24 ; /* 0x000000160c16722b */
/* 0x001fc80000000018 */
/*0c10*/ DMUL R24, R12, R18 ; /* 0x000000120c187228 */
/* 0x000e0c0000000000 */
/*0c20*/ DFMA R26, R12, R18, -R24 ; /* 0x000000120c1a722b */
/* 0x001e0c0000000818 */
/*0c30*/ DFMA R26, R16, R18, R26 ; /* 0x00000012101a722b */
/* 0x001e08000000001a */
/*0c40*/ DADD R18, RZ, R20 ; /* 0x00000000ff127229 */
/* 0x000e480000000014 */
/*0c50*/ DFMA R22, R12, R22, R26 ; /* 0x000000160c16722b */
/* 0x001fc8000000001a */
/*0c60*/ DADD R18, R18, c[0x2][0x38] ; /* 0x00800e0012127629 */
/* 0x002e0c0000000000 */
/*0c70*/ DADD R20, R14, R18 ; /* 0x000000000e147229 */
/* 0x001e0c0000000012 */
/*0c80*/ DADD R26, R14, -R20 ; /* 0x000000000e1a7229 */
/* 0x001e0c0000000814 */
/*0c90*/ DADD R26, R18, R26 ; /* 0x00000000121a7229 */
/* 0x001fc8000000001a */
/*0ca0*/ DMUL R18, R20, R24 ; /* 0x0000001814127228 */
/* 0x000e0c0000000000 */
/*0cb0*/ DFMA R14, R20, R24, -R18 ; /* 0x00000018140e722b */
/* 0x001e0c0000000812 */
/*0cc0*/ DFMA R14, R20, R22, R14 ; /* 0x00000016140e722b */
/* 0x001e0c000000000e */
/*0cd0*/ DFMA R26, R26, R24, R14 ; /* 0x000000181a1a722b */
/* 0x001e0c000000000e */
/*0ce0*/ DADD R14, R18, R26 ; /* 0x00000000120e7229 */
/* 0x001e0c000000001a */
/*0cf0*/ DADD R20, R12, R14 ; /* 0x000000000c147229 */
/* 0x001e08000000000e */
/*0d00*/ DADD R18, R18, -R14 ; /* 0x0000000012127229 */
/* 0x000e48000000080e */
/*0d10*/ DADD R12, R12, -R20 ; /* 0x000000000c0c7229 */
/* 0x001e080000000814 */
/*0d20*/ DADD R18, R26, R18 ; /* 0x000000001a127229 */
/* 0x002fc80000000012 */
/*0d30*/ DADD R12, R14, R12 ; /* 0x000000000e0c7229 */
/* 0x001e0c000000000c */
/*0d40*/ DADD R12, R18, R12 ; /* 0x00000000120c7229 */
/* 0x001e0c000000000c */
/*0d50*/ DADD R16, R16, R12 ; /* 0x0000000010107229 */
/* 0x001e08000000000c */
/*0d60*/ DADD R12, R10, c[0x2][0x40] ; /* 0x008010000a0c7629 */
/* 0x000fc80000000000 */
/*0d70*/ DADD R14, R20, R16 ; /* 0x00000000140e7229 */
/* 0x001e0c0000000010 */
/*0d80*/ DFMA R10, R12, c[0x2][0x48], R14 ; /* 0x008012000c0a7a2b */
/* 0x001e08000000000e */
/*0d90*/ DADD R20, R20, -R14 ; /* 0x0000000014147229 */
/* 0x000e48000000080e */
/*0da0*/ DFMA R18, -R12, c[0x2][0x48], R10 ; /* 0x008012000c127a2b */
/* 0x001e08000000010a */
/*0db0*/ DADD R20, R16, R20 ; /* 0x0000000010147229 */
/* 0x002fc80000000014 */
/*0dc0*/ DADD R18, -R14, R18 ; /* 0x000000000e127229 */
/* 0x001e0c0000000112 */
/*0dd0*/ DADD R18, R20, -R18 ; /* 0x0000000014127229 */
/* 0x001e0c0000000812 */
/*0de0*/ DFMA R18, R12, c[0x2][0x50], R18 ; /* 0x008014000c127a2b */
/* 0x001e0c0000000012 */
/*0df0*/ DADD R12, R10, R18 ; /* 0x000000000a0c7229 */
/* 0x001e0c0000000012 */
/*0e00*/ DADD R10, R10, -R12 ; /* 0x000000000a0a7229 */
/* 0x001e08000000080c */
/*0e10*/ DMUL R16, R12, 2 ; /* 0x400000000c107828 */
/* 0x000e480000000000 */
/*0e20*/ DADD R10, R18, R10 ; /* 0x00000000120a7229 */
/* 0x0011e4000000000a */
/*0e30*/ IMAD.MOV.U32 R18, RZ, RZ, 0x69ce2bdf ; /* 0x69ce2bdfff127424 */
/* 0x001fe400078e00ff */
/*0e40*/ DFMA R14, R12, 2, -R16 ; /* 0x400000000c0e782b */
/* 0x002e220000000810 */
/*0e50*/ IMAD.MOV.U32 R19, RZ, RZ, 0x3e5ade15 ; /* 0x3e5ade15ff137424 */
/* 0x000fca00078e00ff */
/*0e60*/ DFMA R14, R10, 2, R14 ; /* 0x400000000a0e782b */
/* 0x001064000000000e */
/*0e70*/ IMAD.MOV.U32 R10, RZ, RZ, 0x652b82fe ; /* 0x652b82feff0a7424 */
/* 0x001fe400078e00ff */
/*0e80*/ IMAD.MOV.U32 R11, RZ, RZ, 0x3ff71547 ; /* 0x3ff71547ff0b7424 */
/* 0x000fe400078e00ff */
/*0e90*/ DADD R12, R16, R14 ; /* 0x00000000100c7229 */
/* 0x002e0c000000000e */
/*0ea0*/ DFMA R10, R12, R10, 6.75539944105574400000e+15 ; /* 0x433800000c0a742b */
/* 0x001e08000000000a */
/*0eb0*/ FSETP.GEU.AND P0, PT, |R13|, 4.1917929649353027344, PT ; /* 0x4086232b0d00780b */
/* 0x000fe40003f0e200 */
/*0ec0*/ DADD R20, R10, -6.75539944105574400000e+15 ; /* 0xc33800000a147429 */
/* 0x001e0c0000000000 */
/*0ed0*/ DFMA R22, R20, c[0x2][0x58], R12 ; /* 0x0080160014167a2b */
/* 0x001e0c000000000c */
/*0ee0*/ DFMA R20, R20, c[0x2][0x60], R22 ; /* 0x0080180014147a2b */
/* 0x001e0c0000000016 */
/*0ef0*/ DFMA R18, R20, R18, c[0x2][0x68] ; /* 0x00801a001412762b */
/* 0x001e0c0000000012 */
/*0f00*/ DFMA R18, R20, R18, c[0x2][0x70] ; /* 0x00801c001412762b */
/* 0x001e0c0000000012 */
/*0f10*/ DFMA R18, R20, R18, c[0x2][0x78] ; /* 0x00801e001412762b */
/* 0x001e0c0000000012 */
/*0f20*/ DFMA R18, R20, R18, c[0x2][0x80] ; /* 0x008020001412762b */
/* 0x001e0c0000000012 */
/*0f30*/ DFMA R18, R20, R18, c[0x2][0x88] ; /* 0x008022001412762b */
/* 0x001e0c0000000012 */
/*0f40*/ DFMA R18, R20, R18, c[0x2][0x90] ; /* 0x008024001412762b */
/* 0x001e0c0000000012 */
/*0f50*/ DFMA R18, R20, R18, c[0x2][0x98] ; /* 0x008026001412762b */
/* 0x001e0c0000000012 */
/*0f60*/ DFMA R18, R20, R18, c[0x2][0xa0] ; /* 0x008028001412762b */
/* 0x001e0c0000000012 */
/*0f70*/ DFMA R18, R20, R18, c[0x2][0xa8] ; /* 0x00802a001412762b */
/* 0x001e0c0000000012 */
/*0f80*/ DFMA R18, R20, R18, 1 ; /* 0x3ff000001412742b */
/* 0x001e0c0000000012 */
/*0f90*/ DFMA R20, R20, R18, 1 ; /* 0x3ff000001414742b */
/* 0x001e140000000012 */
/*0fa0*/ IMAD R19, R10, 0x100000, R21 ; /* 0x001000000a137824 */
/* 0x001fe400078e0215 */
/*0fb0*/ IMAD.MOV.U32 R18, RZ, RZ, R20 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0014 */
/*0fc0*/ @!P0 BRA 0x1090 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0fd0*/ FSETP.GEU.AND P1, PT, |R13|, 4.2275390625, PT ; /* 0x408748000d00780b */
/* 0x000fe20003f2e200 */
/*0fe0*/ DADD R18, R12, +INF ; /* 0x7ff000000c127429 */
/* 0x000fc80000000000 */
/*0ff0*/ DSETP.GEU.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00722a */
/* 0x000e0c0003f0e000 */
/*1000*/ FSEL R18, R18, RZ, P0 ; /* 0x000000ff12127208 */
/* 0x001fe40000000000 */
/*1010*/ @!P1 LEA.HI R11, R10, R10, RZ, 0x1 ; /* 0x0000000a0a0b9211 */
/* 0x000fe400078f08ff */
/*1020*/ FSEL R19, R19, RZ, P0 ; /* 0x000000ff13137208 */
/* 0x000fe40000000000 */
/*1030*/ @!P1 SHF.R.S32.HI R11, RZ, 0x1, R11 ; /* 0x00000001ff0b9819 */
/* 0x000fca000001140b */
/*1040*/ @!P1 IMAD.IADD R10, R10, 0x1, -R11 ; /* 0x000000010a0a9824 */
/* 0x000fe400078e0a0b */
/*1050*/ @!P1 IMAD R21, R11, 0x100000, R21 ; /* 0x001000000b159824 */
/* 0x000fc600078e0215 */
/*1060*/ @!P1 LEA R11, R10, 0x3ff00000, 0x14 ; /* 0x3ff000000a0b9811 */
/* 0x000fe200078ea0ff */
/*1070*/ @!P1 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a9224 */
/* 0x000fcc00078e00ff */
/*1080*/ @!P1 DMUL R18, R20, R10 ; /* 0x0000000a14129228 */
/* 0x0000540000000000 */
/*1090*/ LOP3.LUT R10, R19, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff130a7812 */
/* 0x003fe200078ec0ff */
/*10a0*/ DADD R12, R16, -R12 ; /* 0x00000000100c7229 */
/* 0x000e22000000080c */
/*10b0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x0 ; /* 0x00000000ff0b7424 */
/* 0x000fe400078e00ff */
/*10c0*/ ISETP.NE.AND P0, PT, R10, 0x7ff00000, PT ; /* 0x7ff000000a00780c */
/* 0x000fe20003f05270 */
/*10d0*/ IMAD.MOV.U32 R10, RZ, RZ, R0 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0000 */
/*10e0*/ DADD R12, R14, R12 ; /* 0x000000000e0c7229 */
/* 0x001e22000000000c */
/*10f0*/ ISETP.EQ.AND P0, PT, R18, RZ, !P0 ; /* 0x000000ff1200720c */
/* 0x000fda0004702270 */
/*1100*/ @!P0 DFMA R18, R12, R18, R18 ; /* 0x000000120c12822b */
/* 0x0010620000000012 */
/*1110*/ RET.REL.NODEC R10 0x0 ; /* 0xffffeee00a007950 */
/* 0x000ff40003c3ffff */
/*1120*/ BRA 0x1120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime_api.h>
#include <stdio.h>
#include <math.h>
#include <iostream>
__device__ float distance(float2 x1, float2 x2){
return sqrt(pow(x1.x - x2.x,2) + pow(x1.y - x2.y,2));
}
__global__ void distance_kernel(float2 *data_in, float *data_out, int n){
const int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i < n){
float2 ref;
ref.x = 0.0;
ref.y = 0.0;
data_out[i] = distance(data_in[i], ref);
}
}
void init_host_data(float2* h_in,int n){
for(int i = 0; i< n;i++){
h_in[i].x = (float)i /((n - 1) * M_PI * 100);
h_in[i].y = sin(h_in[i].x);
}
}
int main(){
float *d_out = NULL;
float2 *d_in = NULL;
float2 *h_in = NULL;
float *h_out = NULL;
int N = 4096;
int TPB = 32;
size_t in_size = N*2*sizeof(float);
size_t out_size = N*sizeof(float);
h_in = (float2*)malloc(in_size);
h_out = (float*)malloc(out_size);
//设备端分配内存
cudaMalloc((void**)&d_in, in_size);
cudaMalloc((void**)&d_out, out_size);
init_host_data(h_in, N);
//拷贝host数据到device
cudaMemcpy(d_in, h_in, in_size, cudaMemcpyHostToDevice);
distance_kernel<<<(N + TPB -1)/TPB,TPB>>>(d_in, d_out, N);
//拷贝device端计算结果到host
cudaMemcpy(h_out, d_out, out_size, cudaMemcpyDeviceToHost);
cudaFree(d_in);
cudaFree(d_out);
for(int i = 0;i < N;i++){
std::cout<<i<<":<"<<h_in[i].x<<","<<h_in[1].y<<">, dist:"<<h_out[i]<<std::endl;
}
free(h_in);
free(h_out);
return 0;
} | .file "tmpxft_00178ddc_00000000-6_hello-cuda.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8distance6float2S_
.type _Z8distance6float2S_, @function
_Z8distance6float2S_:
.LFB3669:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z8distance6float2S_, .-_Z8distance6float2S_
.globl _Z14init_host_dataP6float2i
.type _Z14init_host_dataP6float2i, @function
_Z14init_host_dataP6float2i:
.LFB3670:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L10
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
leal -1(%rsi), %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd .LC0(%rip), %xmm0
mulsd .LC1(%rip), %xmm0
movsd %xmm0, 8(%rsp)
movslq %esi, %r12
movl $0, %ebx
.L7:
pxor %xmm0, %xmm0
cvtsi2ssl %ebx, %xmm0
cvtss2sd %xmm0, %xmm0
divsd 8(%rsp), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 0(%rbp,%rbx,8)
call sinf@PLT
movss %xmm0, 4(%rbp,%rbx,8)
addq $1, %rbx
cmpq %r12, %rbx
jne .L7
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE3670:
.size _Z14init_host_dataP6float2i, .-_Z14init_host_dataP6float2i
.globl _Z44__device_stub__Z15distance_kernelP6float2PfiP6float2Pfi
.type _Z44__device_stub__Z15distance_kernelP6float2PfiP6float2Pfi, @function
_Z44__device_stub__Z15distance_kernelP6float2PfiP6float2Pfi:
.LFB3696:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15distance_kernelP6float2Pfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z44__device_stub__Z15distance_kernelP6float2PfiP6float2Pfi, .-_Z44__device_stub__Z15distance_kernelP6float2PfiP6float2Pfi
.globl _Z15distance_kernelP6float2Pfi
.type _Z15distance_kernelP6float2Pfi, @function
_Z15distance_kernelP6float2Pfi:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z15distance_kernelP6float2PfiP6float2Pfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z15distance_kernelP6float2Pfi, .-_Z15distance_kernelP6float2Pfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string ":<"
.LC3:
.string ","
.LC4:
.string ">, dist:"
.text
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movq $0, 8(%rsp)
movl $32768, %edi
call malloc@PLT
movq %rax, %r13
movl $16384, %edi
call malloc@PLT
movq %rax, %r14
leaq 8(%rsp), %rdi
movl $32768, %esi
call cudaMalloc@PLT
movq %rsp, %rdi
movl $16384, %esi
call cudaMalloc@PLT
movl $4096, %esi
movq %r13, %rdi
call _Z14init_host_dataP6float2i
movl $1, %ecx
movl $32768, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $128, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L22:
movl $2, %ecx
movl $16384, %edx
movq (%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movl $0, %ebx
leaq _ZSt4cout(%rip), %r15
jmp .L27
.L31:
movl $4096, %edx
movq (%rsp), %rsi
movq 8(%rsp), %rdi
call _Z44__device_stub__Z15distance_kernelP6float2PfiP6float2Pfi
jmp .L22
.L34:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L32
call _ZSt16__throw_bad_castv@PLT
.L32:
call __stack_chk_fail@PLT
.L35:
movzbl 67(%r12), %esi
.L26:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %rbx
cmpq $4096, %rbx
je .L33
.L27:
movl %ebx, %esi
movq %r15, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $2, %edx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,8), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $1, %edx
leaq .LC3(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%r13), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $8, %edx
leaq .LC4(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r14,%rbx,4), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L34
cmpb $0, 56(%r12)
jne .L35
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L26
.L33:
movq %r13, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L36
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "_Z15distance_kernelP6float2Pfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z15distance_kernelP6float2Pfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 1413754136
.long 1074340347
.align 8
.LC1:
.long 0
.long 1079574528
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime_api.h>
#include <stdio.h>
#include <math.h>
#include <iostream>
__device__ float distance(float2 x1, float2 x2){
return sqrt(pow(x1.x - x2.x,2) + pow(x1.y - x2.y,2));
}
__global__ void distance_kernel(float2 *data_in, float *data_out, int n){
const int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i < n){
float2 ref;
ref.x = 0.0;
ref.y = 0.0;
data_out[i] = distance(data_in[i], ref);
}
}
void init_host_data(float2* h_in,int n){
for(int i = 0; i< n;i++){
h_in[i].x = (float)i /((n - 1) * M_PI * 100);
h_in[i].y = sin(h_in[i].x);
}
}
int main(){
float *d_out = NULL;
float2 *d_in = NULL;
float2 *h_in = NULL;
float *h_out = NULL;
int N = 4096;
int TPB = 32;
size_t in_size = N*2*sizeof(float);
size_t out_size = N*sizeof(float);
h_in = (float2*)malloc(in_size);
h_out = (float*)malloc(out_size);
//设备端分配内存
cudaMalloc((void**)&d_in, in_size);
cudaMalloc((void**)&d_out, out_size);
init_host_data(h_in, N);
//拷贝host数据到device
cudaMemcpy(d_in, h_in, in_size, cudaMemcpyHostToDevice);
distance_kernel<<<(N + TPB -1)/TPB,TPB>>>(d_in, d_out, N);
//拷贝device端计算结果到host
cudaMemcpy(h_out, d_out, out_size, cudaMemcpyDeviceToHost);
cudaFree(d_in);
cudaFree(d_out);
for(int i = 0;i < N;i++){
std::cout<<i<<":<"<<h_in[i].x<<","<<h_in[1].y<<">, dist:"<<h_out[i]<<std::endl;
}
free(h_in);
free(h_out);
return 0;
} | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <stdio.h>
#include <math.h>
#include <iostream>
__device__ float distance(float2 x1, float2 x2){
return sqrt(pow(x1.x - x2.x,2) + pow(x1.y - x2.y,2));
}
__global__ void distance_kernel(float2 *data_in, float *data_out, int n){
const int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i < n){
float2 ref;
ref.x = 0.0;
ref.y = 0.0;
data_out[i] = distance(data_in[i], ref);
}
}
void init_host_data(float2* h_in,int n){
for(int i = 0; i< n;i++){
h_in[i].x = (float)i /((n - 1) * M_PI * 100);
h_in[i].y = sin(h_in[i].x);
}
}
int main(){
float *d_out = NULL;
float2 *d_in = NULL;
float2 *h_in = NULL;
float *h_out = NULL;
int N = 4096;
int TPB = 32;
size_t in_size = N*2*sizeof(float);
size_t out_size = N*sizeof(float);
h_in = (float2*)malloc(in_size);
h_out = (float*)malloc(out_size);
//设备端分配内存
hipMalloc((void**)&d_in, in_size);
hipMalloc((void**)&d_out, out_size);
init_host_data(h_in, N);
//拷贝host数据到device
hipMemcpy(d_in, h_in, in_size, hipMemcpyHostToDevice);
distance_kernel<<<(N + TPB -1)/TPB,TPB>>>(d_in, d_out, N);
//拷贝device端计算结果到host
hipMemcpy(h_out, d_out, out_size, hipMemcpyDeviceToHost);
hipFree(d_in);
hipFree(d_out);
for(int i = 0;i < N;i++){
std::cout<<i<<":<"<<h_in[i].x<<","<<h_in[1].y<<">, dist:"<<h_out[i]<<std::endl;
}
free(h_in);
free(h_out);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <stdio.h>
#include <math.h>
#include <iostream>
__device__ float distance(float2 x1, float2 x2){
return sqrt(pow(x1.x - x2.x,2) + pow(x1.y - x2.y,2));
}
__global__ void distance_kernel(float2 *data_in, float *data_out, int n){
const int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i < n){
float2 ref;
ref.x = 0.0;
ref.y = 0.0;
data_out[i] = distance(data_in[i], ref);
}
}
void init_host_data(float2* h_in,int n){
for(int i = 0; i< n;i++){
h_in[i].x = (float)i /((n - 1) * M_PI * 100);
h_in[i].y = sin(h_in[i].x);
}
}
int main(){
float *d_out = NULL;
float2 *d_in = NULL;
float2 *h_in = NULL;
float *h_out = NULL;
int N = 4096;
int TPB = 32;
size_t in_size = N*2*sizeof(float);
size_t out_size = N*sizeof(float);
h_in = (float2*)malloc(in_size);
h_out = (float*)malloc(out_size);
//设备端分配内存
hipMalloc((void**)&d_in, in_size);
hipMalloc((void**)&d_out, out_size);
init_host_data(h_in, N);
//拷贝host数据到device
hipMemcpy(d_in, h_in, in_size, hipMemcpyHostToDevice);
distance_kernel<<<(N + TPB -1)/TPB,TPB>>>(d_in, d_out, N);
//拷贝device端计算结果到host
hipMemcpy(h_out, d_out, out_size, hipMemcpyDeviceToHost);
hipFree(d_in);
hipFree(d_out);
for(int i = 0;i < N;i++){
std::cout<<i<<":<"<<h_in[i].x<<","<<h_in[1].y<<">, dist:"<<h_out[i]<<std::endl;
}
free(h_in);
free(h_out);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15distance_kernelP15HIP_vector_typeIfLj2EEPfi
.globl _Z15distance_kernelP15HIP_vector_typeIfLj2EEPfi
.p2align 8
.type _Z15distance_kernelP15HIP_vector_typeIfLj2EEPfi,@function
_Z15distance_kernelP15HIP_vector_typeIfLj2EEPfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_mov_b32 s1, 0x3e76c4e1
global_load_b64 v[3:4], v[3:4], off
s_waitcnt vmcnt(0)
v_frexp_mant_f32_e64 v0, |v3|
v_frexp_mant_f32_e64 v5, |v4|
v_frexp_exp_i32_f32_e32 v19, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v0
v_cmp_gt_f32_e64 s0, 0x3f2aaaab, v5
v_cndmask_b32_e64 v6, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v7, 0, 1, s0
v_ldexp_f32 v0, v0, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f32 v5, v5, v7
v_dual_add_f32 v6, 1.0, v0 :: v_dual_add_f32 v7, 1.0, v5
v_dual_add_f32 v10, -1.0, v0 :: v_dual_add_f32 v11, -1.0, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v8, v6
v_rcp_f32_e32 v9, v7
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v12, v10, v8 :: v_dual_mul_f32 v13, v11, v9
v_add_f32_e32 v14, -1.0, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_add_f32 v16, -1.0, v7 :: v_dual_mul_f32 v15, v6, v12
v_dual_mul_f32 v17, v7, v13 :: v_dual_sub_f32 v0, v0, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v5, v5, v16
v_fma_f32 v6, v12, v6, -v15
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, v13, v7, -v17
v_dual_fmac_f32 v6, v12, v0 :: v_dual_fmac_f32 v7, v13, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v0, v15, v6 :: v_dual_add_f32 v5, v17, v7
v_dual_sub_f32 v14, v10, v0 :: v_dual_sub_f32 v15, v0, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v17, v5, v17
v_sub_f32_e32 v16, v11, v5
v_dual_sub_f32 v10, v10, v14 :: v_dual_sub_f32 v7, v17, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v6, v15, v6
v_sub_f32_e32 v0, v10, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v0, v6, v0
v_add_f32_e32 v0, v14, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v0, v8, v0
v_add_f32_e32 v6, v12, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v11, v11, v16 :: v_dual_mul_f32 v10, v6, v6
v_sub_f32_e32 v5, v11, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v5, v7, v5
v_add_f32_e32 v5, v16, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, v9, v5
v_add_f32_e32 v7, v13, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v9, v7, v13 :: v_dual_sub_f32 v8, v6, v12
v_dual_sub_f32 v5, v5, v9 :: v_dual_sub_f32 v0, v0, v8
v_fma_f32 v9, v6, v6, -v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_add_f32 v13, v5, v5 :: v_dual_mul_f32 v8, v7, v7
v_add_f32_e32 v11, v0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v12, v7, v7, -v8
v_dual_fmac_f32 v9, v6, v11 :: v_dual_fmac_f32 v12, v7, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v13, v8, v12
v_dual_add_f32 v11, v10, v9 :: v_dual_sub_f32 v8, v13, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_fmaak_f32 v14, s1, v11, 0x3e91f4c4 :: v_dual_fmaak_f32 v15, s1, v13, 0x3e91f4c4
v_sub_f32_e32 v10, v11, v10
v_sub_f32_e32 v8, v12, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_fmaak_f32 v14, v11, v14, 0x3ecccdef :: v_dual_fmaak_f32 v15, v13, v15, 0x3ecccdef
v_sub_f32_e32 v9, v9, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v16, v11, v14 :: v_dual_mul_f32 v17, v13, v15
v_fma_f32 v10, v11, v14, -v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v12, v13, v15, -v17
v_fmac_f32_e32 v10, v9, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_fmac_f32_e32 v12, v8, v15
v_mul_f32_e32 v15, v6, v11
v_frexp_exp_i32_f32_e32 v14, v3
v_add_f32_e32 v18, v16, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v22, v11, v6, -v15
v_add_f32_e32 v23, 0x3f2aaaaa, v18
v_add_f32_e32 v21, v17, v12
v_sub_f32_e32 v16, v18, v16
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_fmac_f32_e32 v22, v11, v0
v_ldexp_f32 v0, v0, 1
v_sub_f32_e32 v17, v21, v17
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_add_f32 v25, 0x3f2aaaaa, v21 :: v_dual_sub_f32 v10, v10, v16
v_add_f32_e32 v16, 0xbf2aaaaa, v23
v_dual_fmac_f32 v22, v9, v6 :: v_dual_sub_f32 v11, v12, v17
v_mul_f32_e32 v20, v7, v13
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_f32_e32 v12, 0xbf2aaaaa, v25
v_add_f32_e32 v10, 0x31739010, v10
v_dual_sub_f32 v16, v18, v16 :: v_dual_add_f32 v9, 0x31739010, v11
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f32 v24, v13, v7, -v20
v_sub_f32_e32 v11, v21, v12
v_subrev_co_ci_u32_e32 v12, vcc_lo, 0, v14, vcc_lo
v_ldexp_f32 v6, v6, 1
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_fmac_f32_e32 v24, v13, v5
v_subrev_co_ci_u32_e64 v13, vcc_lo, 0, v19, s0
v_ldexp_f32 v5, v5, 1
v_cmp_neq_f32_e64 s0, 0x7f800000, |v3|
v_fmac_f32_e32 v24, v8, v7
v_add_f32_e32 v8, v9, v11
v_ldexp_f32 v7, v7, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v14, v25, v8
v_dual_add_f32 v10, v10, v16 :: v_dual_sub_f32 v19, v25, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v11, v23, v10 :: v_dual_add_f32 v16, v20, v24
v_sub_f32_e32 v17, v23, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_f32_e32 v21, v16, v14
v_add_f32_e32 v8, v8, v19
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v10, v10, v17
v_fma_f32 v19, v16, v14, -v21
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v19, v16, v8
v_add_f32_e32 v9, v15, v22
v_cvt_f32_i32_e32 v8, v13
v_mul_f32_e32 v18, v9, v11
v_sub_f32_e32 v15, v9, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v17, v9, v11, -v18
v_sub_f32_e32 v15, v22, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v17, v9, v10
v_cvt_f32_i32_e32 v9, v12
v_fmac_f32_e32 v17, v15, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v11, 0x3f317218, v9 :: v_dual_sub_f32 v20, v16, v20
v_sub_f32_e32 v10, v24, v20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v19, v10, v14
v_fma_f32 v14, v9, 0x3f317218, -v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v13, v21, v19 :: v_dual_fmac_f32 v14, 0xb102e308, v9
v_sub_f32_e32 v20, v13, v21
v_add_f32_e32 v10, v18, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v16, v10, v18
v_sub_f32_e32 v16, v17, v16
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v17, v19, v20
v_dual_add_f32 v15, v6, v10 :: v_dual_add_f32 v0, v0, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v5, v5, v17
v_add_f32_e32 v18, v7, v13
v_dual_sub_f32 v7, v18, v7 :: v_dual_mul_f32 v12, 0x3f317218, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v7, v13, v7
v_dual_add_f32 v5, v5, v7 :: v_dual_sub_f32 v6, v15, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v9, v18, v5
v_sub_f32_e32 v6, v10, v6
v_fma_f32 v10, v8, 0x3f317218, -v12
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v0, v0, v6
v_add_f32_e32 v6, v11, v14
v_add_f32_e32 v7, v15, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v11, v6, v11
v_add_f32_e32 v13, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_sub_f32 v17, v13, v6 :: v_dual_fmac_f32 v10, 0xb102e308, v8
v_dual_sub_f32 v11, v14, v11 :: v_dual_sub_f32 v18, v9, v18
v_sub_f32_e32 v14, v7, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v7, v7, v17
v_sub_f32_e32 v5, v5, v18
v_add_f32_e32 v8, v12, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v16, v8, v9
v_sub_f32_e32 v12, v8, v12
v_sub_f32_e32 v15, v16, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_sub_f32_e32 v10, v10, v12
v_sub_f32_e32 v12, v13, v17
v_sub_f32_e32 v0, v0, v14
v_sub_f32_e32 v14, v16, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v9, v9, v15 :: v_dual_sub_f32 v6, v6, v12
v_dual_add_f32 v6, v7, v6 :: v_dual_add_f32 v7, v10, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v8, v8, v14
v_add_f32_e32 v8, v9, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v8, v7, v8
v_add_f32_e32 v12, v11, v0
v_dual_sub_f32 v9, v12, v11 :: v_dual_sub_f32 v14, v7, v10
v_add_f32_e32 v6, v12, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_sub_f32 v12, v12, v9 :: v_dual_sub_f32 v7, v7, v14
v_add_f32_e32 v15, v13, v6
v_sub_f32_e32 v5, v5, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_sub_f32_e32 v11, v11, v12
v_dual_sub_f32 v7, v10, v7 :: v_dual_sub_f32 v0, v0, v9
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_add_f32 v9, v16, v8 :: v_dual_sub_f32 v12, v15, v13
v_add_f32_e32 v5, v5, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v0, v0, v11
v_sub_f32_e32 v10, v9, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v7, v8, v10
v_add_f32_e32 v5, v5, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v7, v9, v5
v_sub_f32_e32 v9, v7, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_sub_f32 v5, v5, v9 :: v_dual_sub_f32 v6, v6, v12
v_mul_f32_e32 v12, 0, v7
v_add_f32_e32 v0, v0, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v12, 2.0, v5
v_add_f32_e32 v6, v15, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v8, v6, v15 :: v_dual_mul_f32 v11, 0, v6
v_sub_f32_e32 v0, v0, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v8, v7, v7 :: v_dual_fmac_f32 v11, 2.0, v0
v_fma_f32 v0, v7, 2.0, -v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v0, v0, v12
v_dual_add_f32 v7, v8, v0 :: v_dual_add_f32 v10, v6, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v6, v6, 2.0, -v10
v_cmp_class_f32_e64 vcc_lo, v10, 0x204
v_add_f32_e32 v5, v6, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v6, v10, v5
v_cndmask_b32_e32 v9, v6, v10, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v8, 0x204
v_cndmask_b32_e32 v11, v7, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v9
v_dual_sub_f32 v7, v7, v8 :: v_dual_sub_f32 v6, v6, v10
v_cndmask_b32_e64 v12, 0, 0x37000000, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v11
v_dual_sub_f32 v5, v5, v6 :: v_dual_sub_f32 v0, v0, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_sub_f32_e32 v14, v9, v12
v_cndmask_b32_e64 v13, 0, 0x37000000, vcc_lo
v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v9|
v_dual_mul_f32 v16, 0x3fb8aa3b, v14 :: v_dual_sub_f32 v15, v11, v13
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v11|
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f32 v18, v14, 0x3fb8aa3b, -v16
v_mul_f32_e32 v17, 0x3fb8aa3b, v15
v_rndne_f32_e32 v19, v16
v_cndmask_b32_e32 v0, 0, v0, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v14
v_fmac_f32_e32 v18, 0x32a5705f, v14
v_fma_f32 v20, v15, 0x3fb8aa3b, -v17
v_rndne_f32_e32 v21, v17
v_sub_f32_e32 v16, v16, v19
v_cvt_i32_f32_e32 v6, v19
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_add_f32 v5, v12, v5 :: v_dual_fmac_f32 v20, 0x32a5705f, v15
v_dual_sub_f32 v17, v17, v21 :: v_dual_add_f32 v16, v16, v18
v_cvt_i32_f32_e32 v7, v21
v_add_f32_e32 v0, v13, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f32_e32 v17, v17, v20
v_exp_f32_e32 v10, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_exp_f32_e32 v8, v17
s_waitcnt_depctr 0xfff
v_ldexp_f32 v6, v10, v6
v_ldexp_f32 v7, v8, v7
v_cndmask_b32_e32 v6, 0, v6, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v7, 0, v7, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v14
v_cndmask_b32_e32 v6, 0x7f800000, v6, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fma_f32 v5, v6, v5, v6
v_cndmask_b32_e32 v7, 0x7f800000, v7, vcc_lo
v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v6
v_fma_f32 v0, v7, v0, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v7
v_cndmask_b32_e64 v5, 0x7f800000, |v5|, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v0, v0, v7, vcc_lo
v_cmp_neq_f32_e64 s0, 0x7f800000, |v4|
v_cmp_neq_f32_e32 vcc_lo, 0, v3
v_cndmask_b32_e64 v0, 0x7f800000, |v0|, s0
v_cndmask_b32_e32 v3, 0, v5, vcc_lo
v_cmp_neq_f32_e32 vcc_lo, 0, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, 0, v0, vcc_lo
v_add_f32_e32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v3, 0x4f800000, v0
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
v_cndmask_b32_e32 v3, v0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v0, v3
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v5, 1, v0
v_add_nc_u32_e32 v4, -1, v0
v_fma_f32 v7, -v5, v0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v6, -v4, v0, v3
v_cmp_ge_f32_e64 s0, 0, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v0, v0, v4, s0
v_cmp_lt_f32_e64 s0, 0, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v0, v0, v5, s0
v_mul_f32_e32 v4, 0x37800000, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v4, v0, v4, vcc_lo
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_cmp_class_f32_e64 vcc_lo, v3, 0x260
v_cndmask_b32_e32 v2, v4, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15distance_kernelP15HIP_vector_typeIfLj2EEPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 26
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15distance_kernelP15HIP_vector_typeIfLj2EEPfi, .Lfunc_end0-_Z15distance_kernelP15HIP_vector_typeIfLj2EEPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15distance_kernelP15HIP_vector_typeIfLj2EEPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15distance_kernelP15HIP_vector_typeIfLj2EEPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 26
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <stdio.h>
#include <math.h>
#include <iostream>
__device__ float distance(float2 x1, float2 x2){
return sqrt(pow(x1.x - x2.x,2) + pow(x1.y - x2.y,2));
}
__global__ void distance_kernel(float2 *data_in, float *data_out, int n){
const int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i < n){
float2 ref;
ref.x = 0.0;
ref.y = 0.0;
data_out[i] = distance(data_in[i], ref);
}
}
void init_host_data(float2* h_in,int n){
for(int i = 0; i< n;i++){
h_in[i].x = (float)i /((n - 1) * M_PI * 100);
h_in[i].y = sin(h_in[i].x);
}
}
int main(){
float *d_out = NULL;
float2 *d_in = NULL;
float2 *h_in = NULL;
float *h_out = NULL;
int N = 4096;
int TPB = 32;
size_t in_size = N*2*sizeof(float);
size_t out_size = N*sizeof(float);
h_in = (float2*)malloc(in_size);
h_out = (float*)malloc(out_size);
//设备端分配内存
hipMalloc((void**)&d_in, in_size);
hipMalloc((void**)&d_out, out_size);
init_host_data(h_in, N);
//拷贝host数据到device
hipMemcpy(d_in, h_in, in_size, hipMemcpyHostToDevice);
distance_kernel<<<(N + TPB -1)/TPB,TPB>>>(d_in, d_out, N);
//拷贝device端计算结果到host
hipMemcpy(h_out, d_out, out_size, hipMemcpyDeviceToHost);
hipFree(d_in);
hipFree(d_out);
for(int i = 0;i < N;i++){
std::cout<<i<<":<"<<h_in[i].x<<","<<h_in[1].y<<">, dist:"<<h_out[i]<<std::endl;
}
free(h_in);
free(h_out);
return 0;
} | .text
.file "hello-cuda.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z30__device_stub__distance_kernelP15HIP_vector_typeIfLj2EEPfi # -- Begin function _Z30__device_stub__distance_kernelP15HIP_vector_typeIfLj2EEPfi
.p2align 4, 0x90
.type _Z30__device_stub__distance_kernelP15HIP_vector_typeIfLj2EEPfi,@function
_Z30__device_stub__distance_kernelP15HIP_vector_typeIfLj2EEPfi: # @_Z30__device_stub__distance_kernelP15HIP_vector_typeIfLj2EEPfi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15distance_kernelP15HIP_vector_typeIfLj2EEPfi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z30__device_stub__distance_kernelP15HIP_vector_typeIfLj2EEPfi, .Lfunc_end0-_Z30__device_stub__distance_kernelP15HIP_vector_typeIfLj2EEPfi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z14init_host_dataP15HIP_vector_typeIfLj2EEi
.LCPI1_0:
.quad 0x400921fb54442d18 # double 3.1415926535897931
.LCPI1_1:
.quad 0x4059000000000000 # double 100
.text
.globl _Z14init_host_dataP15HIP_vector_typeIfLj2EEi
.p2align 4, 0x90
.type _Z14init_host_dataP15HIP_vector_typeIfLj2EEi,@function
_Z14init_host_dataP15HIP_vector_typeIfLj2EEi: # @_Z14init_host_dataP15HIP_vector_typeIfLj2EEi
.cfi_startproc
# %bb.0:
# kill: def $esi killed $esi def $rsi
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
leal -1(%rsi), %eax
cvtsi2sd %eax, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
mulsd .LCPI1_1(%rip), %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %r15d, %xmm0
cvtss2sd %xmm0, %xmm0
divsd 8(%rsp), %xmm0 # 8-byte Folded Reload
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx,%r15,8)
callq sinf
movss %xmm0, 4(%rbx,%r15,8)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z14init_host_dataP15HIP_vector_typeIfLj2EEi, .Lfunc_end1-_Z14init_host_dataP15HIP_vector_typeIfLj2EEi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x4133a152310fa5e6 # double 1286482.1916450202
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq $0, 16(%rsp)
movq $0, 8(%rsp)
movl $32768, %edi # imm = 0x8000
callq malloc
movq %rax, %rbx
movl $16384, %edi # imm = 0x4000
callq malloc
movq %rax, %r14
leaq 8(%rsp), %rdi
movl $32768, %esi # imm = 0x8000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $16384, %esi # imm = 0x4000
callq hipMalloc
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %r15d, %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LCPI2_0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx,%r15,8)
callq sinf
movss %xmm0, 4(%rbx,%r15,8)
incq %r15
cmpq $4096, %r15 # imm = 0x1000
jne .LBB2_1
# %bb.2: # %_Z14init_host_dataP15HIP_vector_typeIfLj2EEi.exit
movq 8(%rsp), %rdi
movl $32768, %edx # imm = 0x8000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967328, %rdx # imm = 0x100000020
leaq 96(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $4096, 28(%rsp) # imm = 0x1000
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15distance_kernelP15HIP_vector_typeIfLj2EEPfi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq 16(%rsp), %rsi
movl $16384, %edx # imm = 0x4000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %r15d, %r15d
jmp .LBB2_5
.p2align 4, 0x90
.LBB2_8: # in Loop: Header=BB2_5 Depth=1
movq %r12, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB2_9: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB2_5 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r15
cmpq $4096, %r15 # imm = 0x1000
je .LBB2_10
.LBB2_5: # =>This Inner Loop Header: Depth=1
movl $_ZSt4cout, %edi
movl %r15d, %esi
callq _ZNSolsEi
movq %rax, %r12
movl $.L.str, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%rbx,%r15,8), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r12, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r12
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 12(%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r12, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r12
movl $.L.str.2, %esi
movl $8, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r12, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB2_11
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB2_5 Depth=1
cmpb $0, 56(%r12)
je .LBB2_8
# %bb.7: # in Loop: Header=BB2_5 Depth=1
movzbl 67(%r12), %ecx
jmp .LBB2_9
.LBB2_10:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_11:
.cfi_def_cfa_offset 176
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15distance_kernelP15HIP_vector_typeIfLj2EEPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15distance_kernelP15HIP_vector_typeIfLj2EEPfi,@object # @_Z15distance_kernelP15HIP_vector_typeIfLj2EEPfi
.section .rodata,"a",@progbits
.globl _Z15distance_kernelP15HIP_vector_typeIfLj2EEPfi
.p2align 3, 0x0
_Z15distance_kernelP15HIP_vector_typeIfLj2EEPfi:
.quad _Z30__device_stub__distance_kernelP15HIP_vector_typeIfLj2EEPfi
.size _Z15distance_kernelP15HIP_vector_typeIfLj2EEPfi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz ":<"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz ","
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz ">, dist:"
.size .L.str.2, 9
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15distance_kernelP15HIP_vector_typeIfLj2EEPfi"
.size .L__unnamed_1, 48
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__distance_kernelP15HIP_vector_typeIfLj2EEPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15distance_kernelP15HIP_vector_typeIfLj2EEPfi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.