system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h> | #include "hip/hip_runtime.h"
#include <stdio.h> |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h> | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h> | .text
.file "kernel.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00155c98_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <cuda.h>
#define N 1024 * 1024
#define CHECK_CUDA_ERR(x) { \
err = x; \
if (err != cudaSuccess) { \
printf("cuda error with %s in line %d\n",cudaGetErrorString(err),__LINE__); \
exit(1); \
} }
int main()
{
cudaError_t err;
cudaEvent_t start_event,stop_event;
CHECK_CUDA_ERR ( cudaEventCreate(&start_event) );
CHECK_CUDA_ERR ( cudaEventCreate(&stop_event) );
void * buf = malloc(sizeof(float) * N);
void * dBuf;
CHECK_CUDA_ERR ( cudaMalloc(&dBuf,sizeof(float) * N) );
CHECK_CUDA_ERR ( cudaEventRecord(start_event,0) ) ;
CHECK_CUDA_ERR ( cudaMemcpy(dBuf,buf,sizeof(float) * N, cudaMemcpyHostToDevice));
CHECK_CUDA_ERR ( cudaEventRecord(stop_event,0) );
CHECK_CUDA_ERR ( cudaDeviceSynchronize() );
float ms = 100.f;
CHECK_CUDA_ERR ( cudaEventElapsedTime(&ms,start_event,stop_event));
printf("%f m second cost\n",ms);
CHECK_CUDA_ERR ( cudaEventDestroy(start_event) );
CHECK_CUDA_ERR ( cudaEventDestroy(stop_event) );
free(buf);
CHECK_CUDA_ERR ( cudaFree(dBuf) );
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <cuda.h>
#define N 1024 * 1024
#define CHECK_CUDA_ERR(x) { \
err = x; \
if (err != cudaSuccess) { \
printf("cuda error with %s in line %d\n",cudaGetErrorString(err),__LINE__); \
exit(1); \
} }
int main()
{
cudaError_t err;
cudaEvent_t start_event,stop_event;
CHECK_CUDA_ERR ( cudaEventCreate(&start_event) );
CHECK_CUDA_ERR ( cudaEventCreate(&stop_event) );
void * buf = malloc(sizeof(float) * N);
void * dBuf;
CHECK_CUDA_ERR ( cudaMalloc(&dBuf,sizeof(float) * N) );
CHECK_CUDA_ERR ( cudaEventRecord(start_event,0) ) ;
CHECK_CUDA_ERR ( cudaMemcpy(dBuf,buf,sizeof(float) * N, cudaMemcpyHostToDevice));
CHECK_CUDA_ERR ( cudaEventRecord(stop_event,0) );
CHECK_CUDA_ERR ( cudaDeviceSynchronize() );
float ms = 100.f;
CHECK_CUDA_ERR ( cudaEventElapsedTime(&ms,start_event,stop_event));
printf("%f m second cost\n",ms);
CHECK_CUDA_ERR ( cudaEventDestroy(start_event) );
CHECK_CUDA_ERR ( cudaEventDestroy(stop_event) );
free(buf);
CHECK_CUDA_ERR ( cudaFree(dBuf) );
return 0;
} | .file "tmpxft_00173363_00000000-6_elapsed.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2073:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2073:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "cuda error with %s in line %d\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%f m second cost\n"
.text
.globl main
.type main, @function
main:
.LFB2070:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
testl %eax, %eax
jne .L17
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
testl %eax, %eax
jne .L18
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
leaq 32(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L19
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
testl %eax, %eax
jne .L20
movl $1, %ecx
movl $4194304, %edx
movq %rbx, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L21
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
testl %eax, %eax
jne .L22
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L23
movl $0x42c80000, 12(%rsp)
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
testl %eax, %eax
jne .L24
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
testl %eax, %eax
jne .L25
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
testl %eax, %eax
jne .L26
movq %rbx, %rdi
call free@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L27
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $23, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L18:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $24, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L19:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $32, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L20:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $34, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L21:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $35, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L22:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $36, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L23:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $37, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L24:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $40, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L25:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $46, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L26:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $47, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L27:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $49, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2096:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <cuda.h>
#define N 1024 * 1024
#define CHECK_CUDA_ERR(x) { \
err = x; \
if (err != cudaSuccess) { \
printf("cuda error with %s in line %d\n",cudaGetErrorString(err),__LINE__); \
exit(1); \
} }
int main()
{
cudaError_t err;
cudaEvent_t start_event,stop_event;
CHECK_CUDA_ERR ( cudaEventCreate(&start_event) );
CHECK_CUDA_ERR ( cudaEventCreate(&stop_event) );
void * buf = malloc(sizeof(float) * N);
void * dBuf;
CHECK_CUDA_ERR ( cudaMalloc(&dBuf,sizeof(float) * N) );
CHECK_CUDA_ERR ( cudaEventRecord(start_event,0) ) ;
CHECK_CUDA_ERR ( cudaMemcpy(dBuf,buf,sizeof(float) * N, cudaMemcpyHostToDevice));
CHECK_CUDA_ERR ( cudaEventRecord(stop_event,0) );
CHECK_CUDA_ERR ( cudaDeviceSynchronize() );
float ms = 100.f;
CHECK_CUDA_ERR ( cudaEventElapsedTime(&ms,start_event,stop_event));
printf("%f m second cost\n",ms);
CHECK_CUDA_ERR ( cudaEventDestroy(start_event) );
CHECK_CUDA_ERR ( cudaEventDestroy(stop_event) );
free(buf);
CHECK_CUDA_ERR ( cudaFree(dBuf) );
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <hip/hip_runtime.h>
#define N 1024 * 1024
#define CHECK_CUDA_ERR(x) { \
err = x; \
if (err != hipSuccess) { \
printf("cuda error with %s in line %d\n",hipGetErrorString(err),__LINE__); \
exit(1); \
} }
int main()
{
hipError_t err;
hipEvent_t start_event,stop_event;
CHECK_CUDA_ERR ( hipEventCreate(&start_event) );
CHECK_CUDA_ERR ( hipEventCreate(&stop_event) );
void * buf = malloc(sizeof(float) * N);
void * dBuf;
CHECK_CUDA_ERR ( hipMalloc(&dBuf,sizeof(float) * N) );
CHECK_CUDA_ERR ( hipEventRecord(start_event,0) ) ;
CHECK_CUDA_ERR ( hipMemcpy(dBuf,buf,sizeof(float) * N, hipMemcpyHostToDevice));
CHECK_CUDA_ERR ( hipEventRecord(stop_event,0) );
CHECK_CUDA_ERR ( hipDeviceSynchronize() );
float ms = 100.f;
CHECK_CUDA_ERR ( hipEventElapsedTime(&ms,start_event,stop_event));
printf("%f m second cost\n",ms);
CHECK_CUDA_ERR ( hipEventDestroy(start_event) );
CHECK_CUDA_ERR ( hipEventDestroy(stop_event) );
free(buf);
CHECK_CUDA_ERR ( hipFree(dBuf) );
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <hip/hip_runtime.h>
#define N 1024 * 1024
#define CHECK_CUDA_ERR(x) { \
err = x; \
if (err != hipSuccess) { \
printf("cuda error with %s in line %d\n",hipGetErrorString(err),__LINE__); \
exit(1); \
} }
int main()
{
hipError_t err;
hipEvent_t start_event,stop_event;
CHECK_CUDA_ERR ( hipEventCreate(&start_event) );
CHECK_CUDA_ERR ( hipEventCreate(&stop_event) );
void * buf = malloc(sizeof(float) * N);
void * dBuf;
CHECK_CUDA_ERR ( hipMalloc(&dBuf,sizeof(float) * N) );
CHECK_CUDA_ERR ( hipEventRecord(start_event,0) ) ;
CHECK_CUDA_ERR ( hipMemcpy(dBuf,buf,sizeof(float) * N, hipMemcpyHostToDevice));
CHECK_CUDA_ERR ( hipEventRecord(stop_event,0) );
CHECK_CUDA_ERR ( hipDeviceSynchronize() );
float ms = 100.f;
CHECK_CUDA_ERR ( hipEventElapsedTime(&ms,start_event,stop_event));
printf("%f m second cost\n",ms);
CHECK_CUDA_ERR ( hipEventDestroy(start_event) );
CHECK_CUDA_ERR ( hipEventDestroy(stop_event) );
free(buf);
CHECK_CUDA_ERR ( hipFree(dBuf) );
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <hip/hip_runtime.h>
#define N 1024 * 1024
#define CHECK_CUDA_ERR(x) { \
err = x; \
if (err != hipSuccess) { \
printf("cuda error with %s in line %d\n",hipGetErrorString(err),__LINE__); \
exit(1); \
} }
int main()
{
hipError_t err;
hipEvent_t start_event,stop_event;
CHECK_CUDA_ERR ( hipEventCreate(&start_event) );
CHECK_CUDA_ERR ( hipEventCreate(&stop_event) );
void * buf = malloc(sizeof(float) * N);
void * dBuf;
CHECK_CUDA_ERR ( hipMalloc(&dBuf,sizeof(float) * N) );
CHECK_CUDA_ERR ( hipEventRecord(start_event,0) ) ;
CHECK_CUDA_ERR ( hipMemcpy(dBuf,buf,sizeof(float) * N, hipMemcpyHostToDevice));
CHECK_CUDA_ERR ( hipEventRecord(stop_event,0) );
CHECK_CUDA_ERR ( hipDeviceSynchronize() );
float ms = 100.f;
CHECK_CUDA_ERR ( hipEventElapsedTime(&ms,start_event,stop_event));
printf("%f m second cost\n",ms);
CHECK_CUDA_ERR ( hipEventDestroy(start_event) );
CHECK_CUDA_ERR ( hipEventDestroy(stop_event) );
free(buf);
CHECK_CUDA_ERR ( hipFree(dBuf) );
return 0;
} | .text
.file "elapsed.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
leaq 16(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB0_1
# %bb.3:
leaq 8(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB0_4
# %bb.5:
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
leaq 24(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
testl %eax, %eax
jne .LBB0_6
# %bb.7:
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB0_8
# %bb.9:
movq 24(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_10
# %bb.11:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB0_12
# %bb.13:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB0_14
# %bb.15:
movl $1120403456, 4(%rsp) # imm = 0x42C80000
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
testl %eax, %eax
jne .LBB0_16
# %bb.17:
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
callq hipEventDestroy
testl %eax, %eax
jne .LBB0_18
# %bb.19:
movq 8(%rsp), %rdi
callq hipEventDestroy
testl %eax, %eax
jne .LBB0_20
# %bb.21:
movq %rbx, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB0_22
# %bb.23:
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB0_1:
.cfi_def_cfa_offset 48
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl $23, %edx
jmp .LBB0_2
.LBB0_4:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl $24, %edx
jmp .LBB0_2
.LBB0_6:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl $32, %edx
jmp .LBB0_2
.LBB0_8:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl $34, %edx
jmp .LBB0_2
.LBB0_10:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl $35, %edx
jmp .LBB0_2
.LBB0_12:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl $36, %edx
jmp .LBB0_2
.LBB0_14:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl $37, %edx
jmp .LBB0_2
.LBB0_16:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl $40, %edx
jmp .LBB0_2
.LBB0_18:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl $46, %edx
jmp .LBB0_2
.LBB0_20:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl $47, %edx
jmp .LBB0_2
.LBB0_22:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl $49, %edx
.LBB0_2:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "cuda error with %s in line %d\n"
.size .L.str, 31
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%f m second cost\n"
.size .L.str.1, 18
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00173363_00000000-6_elapsed.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2073:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2073:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "cuda error with %s in line %d\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%f m second cost\n"
.text
.globl main
.type main, @function
main:
.LFB2070:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
testl %eax, %eax
jne .L17
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
testl %eax, %eax
jne .L18
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
leaq 32(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L19
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
testl %eax, %eax
jne .L20
movl $1, %ecx
movl $4194304, %edx
movq %rbx, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L21
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
testl %eax, %eax
jne .L22
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L23
movl $0x42c80000, 12(%rsp)
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
testl %eax, %eax
jne .L24
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
testl %eax, %eax
jne .L25
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
testl %eax, %eax
jne .L26
movq %rbx, %rdi
call free@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L27
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $23, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L18:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $24, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L19:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $32, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L20:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $34, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L21:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $35, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L22:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $36, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L23:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $37, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L24:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $40, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L25:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $46, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L26:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $47, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L27:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $49, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2096:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "elapsed.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
leaq 16(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB0_1
# %bb.3:
leaq 8(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB0_4
# %bb.5:
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
leaq 24(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
testl %eax, %eax
jne .LBB0_6
# %bb.7:
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB0_8
# %bb.9:
movq 24(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_10
# %bb.11:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB0_12
# %bb.13:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB0_14
# %bb.15:
movl $1120403456, 4(%rsp) # imm = 0x42C80000
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
testl %eax, %eax
jne .LBB0_16
# %bb.17:
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
callq hipEventDestroy
testl %eax, %eax
jne .LBB0_18
# %bb.19:
movq 8(%rsp), %rdi
callq hipEventDestroy
testl %eax, %eax
jne .LBB0_20
# %bb.21:
movq %rbx, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB0_22
# %bb.23:
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB0_1:
.cfi_def_cfa_offset 48
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl $23, %edx
jmp .LBB0_2
.LBB0_4:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl $24, %edx
jmp .LBB0_2
.LBB0_6:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl $32, %edx
jmp .LBB0_2
.LBB0_8:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl $34, %edx
jmp .LBB0_2
.LBB0_10:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl $35, %edx
jmp .LBB0_2
.LBB0_12:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl $36, %edx
jmp .LBB0_2
.LBB0_14:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl $37, %edx
jmp .LBB0_2
.LBB0_16:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl $40, %edx
jmp .LBB0_2
.LBB0_18:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl $46, %edx
jmp .LBB0_2
.LBB0_20:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl $47, %edx
jmp .LBB0_2
.LBB0_22:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl $49, %edx
.LBB0_2:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "cuda error with %s in line %d\n"
.size .L.str, 31
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%f m second cost\n"
.size .L.str.1, 18
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //#include "shallow.h"
#include <iostream>
#include <time.h>
#include <stdlib.h>
#define RELU(a) ((a > 0) ? a : 0)
#define KERNEL_SIZE(n_C) ((n_C * 2 > 8) ? 8 : n_C * 2)
struct layer_param {
int M; //Ilosc tablic podawanych na wejscie
int pad; //Grubosc warstwy zer na krawedziach (zero-padding)
int F; //Rozmiar 2D filtra (F x F)
int F_MP; //Rozmiar 2D filtra do max poolingu (F_MP x F_MP)
int stride; //Ilosc przeskakiwanych pikseli przy konwolucji na inkrementacje
int stride_MP; //To samo, tylko przy max poolingu
int n_Hprev; //Wysokosc tablicy wejsciowej podawanej na wejscie sieci
int n_Wprev; //Szerokosc tablicy wejsciowej podawanej na wejscie sieci
int n_Cprev; //Glebokosc tablicy wejsciowej, jednoczesnie musi to byc glebokosc filtra (F x F x C)
int n_H; //Wysokosc tablicy uzyskanej po konwolucji kernela z wejsciem
int n_W;
int n_C; //Ilosc filtrow, jednoczesnie glebokosc wyjscia warstwy
int n_Hout; //Wysokosc tablicy wyjsciowej warstwy
int n_Wout;
double alpha; //Predkosc uczenia
};
struct cache_data {
double** IN; //Tablica wejsciowa
double** Z; //Wynik splotu
double** A; //Wynik Aktywacji
double** OUT; //Poprzedni wynik po max poolingu, jednoczescie wyjscie warstwy sieci
double** kernel; //Filtr
double** dW; //Gradient kosztu wzgledem kerneli
double** dA; //Gradient kosztu wzgledem warstwy
double** dAprev; //Gradient kosztu wzgledem wyjscia warstwy n_l - 1
double** dZ; //Gradient kosztu wzgledem wyniku konwolucji
};
void set_random_IN(layer_param, double**&); //Ustawia losowe wejscie (do testowania)
void set_new_IN(double**&, double**&, layer_param l);
void show_results(layer_param, cache_data&); //Wyswietla zawartosc koncowych i posrednich wynikow w warstwie
void brief_inf(layer_param, double**); //Krotka informacja o wyjsciu sieci
void forw_prop(layer_param, cache_data&); //Najwazniejsza funkcja (konwolucja, aktywacja, maxpooling)
void simple_del(double**&, int); //Usuwanie pamieci
void update_param(layer_param&, layer_param&); //Ustawianie nowych parametrow warstwy
void prep_new_arrays(layer_param, cache_data&); //Tworzenie nowych tablic wynikowych
void prep_gradients(layer_param, cache_data&); //Tworzenie gradientow (narazie losowo, bez funkcji kosztu)
void show_gradients(layer_param, cache_data&);
void back_prop(layer_param, cache_data&);
int main() {
srand(time(NULL));
int number_of_layers = 2;
layer_param* l = new layer_param[number_of_layers];
cache_data* cache = new cache_data[number_of_layers];
int n_l = 0;
layer_param l_prev;
l[n_l].M = 1;
l[n_l].pad = 0;
l[n_l].F = 3;
l[n_l].F_MP = 2;
l[n_l].stride = 1;
l[n_l].stride_MP = 2;
l[n_l].alpha = 0.1;
int IN_size = 16; //Rzeczywisty rozmiar wejscia
int IN_depth = 1; //Rzeczywista glebokosc wejscia
l[n_l].n_Hprev = IN_size + 2 * l[n_l].pad;
l[n_l].n_Wprev = IN_size + 2 * l[n_l].pad;
l[n_l].n_Cprev = IN_depth;
l[n_l].n_H = int((l[n_l].n_Hprev - l[n_l].F) / l[n_l].stride) + 1;
l[n_l].n_W = int((l[n_l].n_Wprev - l[n_l].F) / l[n_l].stride) + 1;
l[n_l].n_C = 1;
l[n_l].n_Hout = int((l[n_l].n_H - l[n_l].F_MP) / l[n_l].stride_MP) + 1;
l[n_l].n_Wout = int((l[n_l].n_W - l[n_l].F_MP) / l[n_l].stride_MP) + 1;
for (n_l = 0; n_l < number_of_layers; n_l++) {
std::cout << "\n\n#### WARSTWA: " << n_l + 1 << "#### \n";
if (n_l == 0) set_random_IN(l[n_l], cache[n_l].IN);
else {
l_prev = l[n_l - 1];
update_param(l_prev, l[n_l]);
set_new_IN(cache[n_l].IN, cache[n_l - 1].OUT, l[n_l]);
}
prep_new_arrays(l[n_l], cache[n_l]);
forw_prop(l[n_l], cache[n_l]);
prep_gradients(l[n_l], cache[n_l]);
if (l[n_l].n_H < 25) show_results(l[n_l], cache[n_l]);
else brief_inf(l[n_l], cache[n_l].OUT);
//back_prop(l[n_l], cache[n_l]);
//show_gradients(l[n_l], cache[n_l]); //Funkcja wyswietla gradient
}
return 0;
}
void set_random_IN(layer_param l, double**& IN) {
IN = new double* [l.M];
for (int i = 0; i < l.M; i++) {
IN[i] = new double[l.n_Cprev * l.n_Hprev * l.n_Wprev];
}
for (int m = 0; m < l.M; m++) { //Dla kazdego badanego przypadku (np. pojedynczej mapy bajtowej- spektogram)
for (int h = 0; h < l.n_Hprev; h++) { //Przejdz po kazdym wierszu
for (int w = 0; w < l.n_Wprev; w++) { //Przejdz po kazdej kolumnie
for (int c = 0; c < l.n_Cprev; c++) { //Przejdz po kazdym kanale (np. dla wejscia w postaci zdjecia rgb - 3 kanaly)
if (h < l.pad || h > l.n_Hprev - l.pad - 1) IN[m][w + l.n_Wprev * (h + l.n_Hprev * c)] = 0; //Ustawianie zer dla zero paddingu
else if (w < l.pad || w > l.n_Wprev - l.pad - 1) IN[m][w + l.n_Wprev * (h + l.n_Hprev * c)] = 0;
else IN[m][w + l.n_Wprev * (h + l.n_Hprev * c)] = (rand() % 10 + 1)/10.; //W tablicy wejsciowej beda same wartosci int
}
}
}
}
}
void set_new_IN(double**& IN, double**& OUT, layer_param l) {
IN = new double* [l.M];
for (int i = 0; i < l.M; i++) {
IN[i] = new double[l.n_Cprev * l.n_Hprev * l.n_Wprev];
}
for (int m = 0; m < l.M; m++) {
for (int c = 0; c < l.n_Cprev; c++) {
for (int h = 0; h < l.n_Hprev; h++) {
for (int w = 0; w < l.n_Wprev; w++) {
IN[m][w + l.n_Wprev * (h + l.n_Hprev * c)] = OUT[m][w + l.n_Wprev * (h + l.n_Hprev * c)];
}
}
}
}
}
void update_param(layer_param& l_prev, layer_param& l) {
l.M = l_prev.M;
l.pad = l_prev.pad;
l.F = l_prev.F;
l.F_MP = l_prev.F_MP;
l.stride = l_prev.stride;
l.stride_MP = l_prev.stride_MP;
l.alpha = l_prev.alpha;
l.n_Hprev = l_prev.n_Hout;
l.n_Wprev = l_prev.n_Wout;
l.n_Cprev = l_prev.n_C;
l.n_H = int((l.n_Hprev - l.F) / l.stride) + 1;
l.n_W = int((l.n_Wprev - l.F) / l.stride) + 1;
l.n_C = KERNEL_SIZE(l_prev.n_C);
l.n_Hout = int((l.n_H - l.F_MP) / l.stride_MP) + 1;
l.n_Wout = int((l.n_W - l.F_MP) / l.stride_MP) + 1;
}
void prep_new_arrays(layer_param l, cache_data& cache) {
cache.Z = new double* [l.M];
cache.A = new double* [l.M];
cache.OUT = new double* [l.M];
cache.kernel = new double* [l.n_C];
for (int i = 0; i < l.M; i++) {
cache.Z[i] = new double[l.n_C * l.n_H * l.n_W];
cache.A[i] = new double[l.n_C * l.n_H * l.n_W];
cache.OUT[i] = new double[l.n_C * l.n_Hout * l.n_Wout];
}
for (int i = 0; i < l.n_C; i++) {
cache.kernel[i] = new double[l.n_Cprev * l.F * l.F];
}
for (int c = 0; c < l.n_C; c++) {
for (int h = 0; h < l.F; h++) {
for (int w = 0; w < l.F; w++) {
for (int d = 0; d < l.n_Cprev; d++) {
cache.kernel[c][w + l.F * (h + l.F * d)] = (rand()%10000 - 5000) * 0.0001; //Ustawianie losowych wag filtra
}
}
}
}
}
void prep_gradients(layer_param l, cache_data& cache) {
cache.dZ = new double* [l.M];
cache.dA = new double* [l.M];
cache.dAprev = new double* [l.M];
cache.dW = new double* [l.n_C];
for (int i = 0; i < l.M; i++) {
cache.dZ[i] = new double[l.n_C * l.n_H * l.n_W];
}
for (int i = 0; i < l.M; i++) {
cache.dA[i] = new double[l.n_C * l.n_Hout * l.n_Wout];
}
for (int i = 0; i < l.M; i++) {
cache.dAprev[i] = new double[l.n_Cprev * l.n_Hprev * l.n_Wprev];
}
for (int i = 0; i < l.n_C; i++) {
cache.dW[i] = new double[l.n_Cprev * l.F * l.F];
}
for (int m = 0; m < l.M; m++) {
for (int c = 0; c < l.n_C; c++) {
for (int h = 0; h < l.n_Hout; h++) {
for (int w = 0; w < l.n_Wout; w++) {
cache.dA[m][w + l.n_Wout * (h + l.n_Hout * c)] = (rand()%10000 - 5000) * 0.0001;
}
}
}
}
for (int m = 0; m < l.M; m++) {
for (int c = 0; c < l.n_Cprev; c++) {
for (int h = 0; h < l.n_Hprev; h++) {
for (int w = 0; w < l.n_Wprev; w++) {
cache.dAprev[m][w + l.n_Wprev * (h + l.n_Hprev * c)] = 0;
}
}
}
}
for (int c = 0; c < l.n_C; c++) {
for (int h = 0; h < l.F; h++) {
for (int w = 0; w < l.F; w++) {
for (int d = 0; d < l.n_Cprev; d++) {
cache.dW[c][w + l.F * (h + l.F * d)] = 0;
}
}
}
}
double maximum;
int vert_start, vert_end;
int horiz_start, horiz_end;
for (int m = 0; m < l.M; m++) { //Dla kazdego przypadku
for (int h = 0; h < l.n_Hout; h++) { //Dla kazdego wiersza wyjscia (wyniku max poolingu)
for (int w = 0; w < l.n_Wout; w++) { // Dla kazdej kolumny wyjscia
for (int c = 0; c < l.n_C; c++) { //Dla kazdego kanalu wyjscia
vert_start = h * l.stride_MP;
vert_end = vert_start + l.F_MP;
horiz_start = w * l.stride_MP;
horiz_end = horiz_start + l.F_MP;
maximum = 0;
for (int j = vert_start; j < vert_end; j++) { //Dla kazdego wiersza wycinka wyniku aktywacji
for (int k = horiz_start; k < horiz_end; k++) { //Dla kazdej kolumny wycinka wyniku aktywacji
if (cache.A[m][k + l.n_W * (j + l.n_H * c)] > maximum) maximum = cache.A[m][k + l.n_W * (j + l.n_H * c)];
}
}
for (int j = vert_start; j < vert_end; j++) {
for (int k = horiz_start; k < horiz_end; k++) {
if (cache.A[m][k + l.n_W * (j + l.n_H * c)] != maximum || maximum == 0) cache.dZ[m][k + l.n_W * (j + l.n_H * c)] = 0;
else cache.dZ[m][k + l.n_W * (j + l.n_H * c)] = cache.dA[m][w + l.n_Wout * (h + l.n_Hout * c)];
}
}
}
}
}
}
for (int m = 0; m < l.M; m++) {
for (int h = 0; h < l.n_H; h++) {
for (int w = 0; w < l.n_W; w++) {
for (int c = 0; c < l.n_C; c++) {
vert_start = h;
vert_end = vert_start + l.F;
horiz_start = w;
horiz_end = horiz_start + l.F;
for (int d = 0; d < l.n_Cprev; d++) {
for (int j = vert_start; j < vert_end; j++) {
for (int k = horiz_start; k < horiz_end; k++) {
if (cache.dZ[m][w + l.n_W * (h + l.n_H * c)] < 0) cache.dZ[m][w + l.n_W * (h + l.n_H * c)] = 0;
cache.dAprev[m][j + l.n_Wprev * (k + l.n_Hprev * d)] += cache.kernel[c][(k - horiz_start) + l.F * ((j - vert_start) + l.F * d)] *
cache.dZ[m][w + l.n_W * (h + l.n_H * c)];
cache.dW[c][(k - horiz_start) + l.F * ((j - vert_start) + l.F * d)] += cache.IN[m][j + l.n_Wprev * (k + l.n_Hprev * d)] *
cache.dZ[m][w + l.n_W * (h + l.n_H * c)];
}
}
}
}
}
}
}
}
void brief_inf(layer_param l, double** OUT) {
for (int m = 0; m < l.M; m++)
std::cout << "Wyjscie: " << m + 1 << " Kanaly: " << l.n_C << " (" << l.n_Hout << "x" << l.n_Wout << "x" << l.n_C << ")" << "\n" << std::fixed;
}
void forw_prop(layer_param l, cache_data& cache) {
int M = l.M;
int pad = l.pad;
int F = l.F;
int F_MP = l.F_MP;
int stride = l.stride;
int stride_MP = l.stride_MP;
int n_Hprev = l.n_Hprev;
int n_Wprev = l.n_Wprev;
int n_Cprev = l.n_Cprev;
int n_H = l.n_H;
int n_W = l.n_W;
int n_C = l.n_C;
int n_Hout = l.n_Hout;
int n_Wout = l.n_Wout;
int vert_start = 0;
int vert_end = 0;
int horiz_start = 0;
int horiz_end = 0;
for (int m = 0; m < M; m++) { //Dla kazdego przypadku
for (int h = 0; h < n_H; h++) { //Dla kazdego wiersza
for (int w = 0; w < n_W; w++) { //Dla kazdej kolumny
for (int c = 0; c < n_C; c++) { //Dla kazdego kanalu (kanalow bedzie tyle, ile chcemy kerneli)
vert_start = h * stride; //Poczatek wycinka w pionie
vert_end = vert_start + F; //Koniec wycinka w pionie
horiz_start = w * stride; //Poczatek wycika w poziomie
horiz_end = horiz_start + F; //Koniec wycinka w poziomie
cache.Z[m][w + n_W * (h + n_H * c)] = 0;
for (int d = 0; d < n_Cprev; d++) { //Dla kazdego kanalu w tablicy wejsciowej
for (int j = vert_start; j < vert_end; j++) { //Dla wybranych wierszy
for (int k = horiz_start; k < horiz_end; k++) { //Dla wybranych kolumn
cache.Z[m][w + n_W * (h + n_H * c)] += cache.kernel[c][(k - horiz_start) + F * ((j - vert_start) + F * d)] *
cache.IN[m][k + n_Wprev * (j + n_Hprev * d)];
//Pomnoz wartosc/piksel wycinka przez wage kernela i dodaj do wyniku konwolucji
}
}
}
cache.A[m][w + n_W * (h + n_H * c)] = RELU(cache.Z[m][w + n_W * (h + n_H * c)]); //Aktywowanie danej wartosci/neuronu
}
}
}
}
double maximum = 0;
for (int m = 0; m < M; m++) { //Dla kazdego przypadku
for (int h = 0; h < n_Hout; h++) { //Dla kazdego wiersza wyjscia (wyniku max poolingu)
for (int w = 0; w < n_Wout; w++) { // Dla kazdej kolumny wyjscia
for (int c = 0; c < n_C; c++) { //Dla kazdego kanalu wyjscia
if (n_Hout > 1) {
vert_start = h * stride_MP;
vert_end = vert_start + F_MP;
horiz_start = w * stride_MP;
horiz_end = horiz_start + F_MP;
maximum = 0;
for (int j = vert_start; j < vert_end; j++) { //Dla kazdego wiersza wycinka wyniku aktywacji
for (int k = horiz_start; k < horiz_end; k++) { //Dla kazdej kolumny wycinka wyniku aktywacji
if (cache.A[m][k + n_W * (j + n_H * c)] > maximum) maximum = cache.A[m][k + n_W * (j + n_H * c)]; //Wybierz maksimum z wycinka
}
}
cache.OUT[m][w + n_Wout * (h + n_Hout * c)] = maximum;
}
else
cache.OUT[m][w + n_Wout * (h + n_Hout * c)] = cache.A[m][0 + n_W * (0 + n_H * c)];
}
}
}
}
}
void show_gradients(layer_param l, cache_data& cache) {
for (int m = 0; m < l.M; m++) {
for (int c = 0; c < l.n_Cprev; c++) {
std::cout << "dAprev: " << m + 1 << " Kanal: " << c + 1 << " (" << l.n_Hprev << "x" << l.n_Wprev << "x" << l.n_Cprev << ")" << "\n";
for (int h = 0; h < l.n_Hprev; h++) {
for (int w = 0; w < l.n_Wprev; w++) {
std::cout << cache.dAprev[m][w + l.n_Wprev * (h + l.n_Hprev * c)] << " ";
}
std::cout << "\n";
}
}
std::cout << "\n\n";
}
std::cout << "#### dW #### \n\n";
for (int c = 0; c < l.n_C; c++) {
for (int d = 0; d < l.n_Cprev; d++) {
std::cout << "dW: " << c + 1 << " Kanal: " << d + 1 << " (" << l.F << "x" << l.F << "x" << l.n_Cprev << ")" << "\n" << std::fixed;
for (int h = 0; h < l.F; h++) {
for (int w = 0; w < l.F; w++) {
std::cout << cache.dW[c][w + l.F * (h + l.F * d)] << " ";
}
std::cout << "\n";
}
}
std::cout << "\n\n";
}
std::cout << "#### dZ #### \n\n";
for (int m = 0; m < l.M; m++) {
for (int c = 0; c < l.n_C; c++) {
std::cout << "dZ: " << m + 1 << " Kanal: " << c + 1 << " (" << l.n_H << "x" << l.n_W << "x" << l.n_C << ")" << "\n" << std::fixed;
for (int h = 0; h < l.n_H; h++) {
for (int w = 0; w < l.n_W; w++) {
std::cout << cache.dZ[m][w + l.n_W * (h + l.n_H * c)] << " ";
}
std::cout << "\n";
}
std::cout << "\n";
}
}
std::cout << "#### dA #### \n\n";
for (int m = 0; m < l.M; m++) {
for (int c = 0; c < l.n_C; c++) {
std::cout << "dA: " << m + 1 << " Kanal: " << c + 1 << " (" << l.n_Hout << "x" << l.n_Wout << "x" << l.n_C << ")" << "\n" << std::fixed;
for (int h = 0; h < l.n_Hout; h++) {
for (int w = 0; w < l.n_Wout; w++) {
std::cout << cache.dA[m][w + l.n_Wout * (h + l.n_Hout * c)] << " ";
}
std::cout << "\n";
}
std::cout << "\n";
}
}
}
void simple_del(double**& arr, int len) {
for (int i = 0; i < len; i++) {
delete[] arr[i];
}
delete[] arr;
}
void show_results(layer_param l, cache_data& cache)
{
std::cout.precision(4);
for (int m = 0; m < l.M; m++) {
for (int c = 0; c < l.n_Cprev; c++) {
std::cout << "Wejscie: " << m + 1 << " Kanal: " << c + 1 << " (" << l.n_Hprev << "x" << l.n_Wprev << "x" << l.n_Cprev << ")" << "\n";
for (int h = 0; h < l.n_Hprev; h++) {
for (int w = 0; w < l.n_Wprev; w++) {
std::cout << cache.IN[m][w + l.n_Wprev * (h + l.n_Hprev * c)] << " ";
}
std::cout << "\n";
}
}
std::cout << "\n\n";
}
std::cout << "#### FILTRY #### \n\n";
for (int c = 0; c < l.n_C; c++) {
for (int d = 0; d < l.n_Cprev; d++) {
std::cout << "Kernel: " << c + 1 << " Kanal: " << d + 1 << " (" << l.F << "x" << l.F << "x" << l.n_Cprev << ")" << "\n" << std::fixed;
for (int h = 0; h < l.F; h++) {
for (int w = 0; w < l.F; w++) {
std::cout << cache.kernel[c][w + l.F * (h + l.F * d)] << " ";
}
std::cout << "\n";
}
}
std::cout << "\n\n";
}
std::cout << "#### WYNIKI KONWOLUCJI #### \n\n";
for (int m = 0; m < l.M; m++) {
for (int c = 0; c < l.n_C; c++) {
std::cout << "Z: " << m + 1 << " Kanal: " << c + 1 << " (" << l.n_H << "x" << l.n_W << "x" << l.n_C << ")" << "\n" << std::fixed;
for (int h = 0; h < l.n_H; h++) {
for (int w = 0; w < l.n_W; w++) {
std::cout << cache.Z[m][w + l.n_W * (h + l.n_H * c)] << " ";
}
std::cout << "\n";
}
std::cout << "\n";
}
}
std::cout << "#### WYNIKI AKTYWACJI (RELU) #### \n\n";
for (int m = 0; m < l.M; m++) {
for (int c = 0; c < l.n_C; c++) {
std::cout << "A: " << m + 1 << " Kanal: " << c + 1 << " (" << l.n_H << "x" << l.n_W << "x" << l.n_C << ")" << "\n" << std::fixed;
for (int h = 0; h < l.n_H; h++) {
for (int w = 0; w < l.n_W; w++) {
std::cout << cache.A[m][w + l.n_W * (h + l.n_H * c)] << " ";
}
std::cout << "\n";
}
std::cout << "\n";
}
}
std::cout << "#### WYNIKI MAX POOLINGU #### \n\n";
for (int m = 0; m < l.M; m++) {
for (int c = 0; c < l.n_C; c++) {
std::cout << "Wyjscie: " << m + 1 << " Kanal: " << c + 1 << " (" << l.n_Hout << "x" << l.n_Wout << "x" << l.n_C << ")" << "\n" << std::fixed;
for (int h = 0; h < l.n_Hout; h++) {
for (int w = 0; w < l.n_Wout; w++) {
std::cout << cache.OUT[m][w + l.n_Wout * (h + l.n_Hout * c)] << " ";
}
std::cout << "\n";
}
std::cout << "\n";
}
}
}
void back_prop(layer_param l, cache_data& cache) {
std::cout << "#### FILTRY PO PO PROPAGACJI WSTECZNEJ #### \n\n";
for (int c = 0; c < l.n_C; c++) {
for (int d = 0; d < l.n_Cprev; d++) {
std::cout << "Wagi: " << c + 1 << " Kanal: " << d + 1 << " (" << l.F << "x" << l.F << "x" << l.n_Cprev << ")" << "\n" << std::fixed;
for (int h = 0; h < l.F; h++) {
for (int w = 0; w < l.F; w++) {
std::cout << cache.kernel[c][w + l.F * (h + l.F * d)] - l.alpha * cache.dW[c][w + l.F * (h + l.F * d)] << " ";
}
std::cout << "\n";
}
}
std::cout << "\n\n";
}
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //#include "shallow.h"
#include <iostream>
#include <time.h>
#include <stdlib.h>
#define RELU(a) ((a > 0) ? a : 0)
#define KERNEL_SIZE(n_C) ((n_C * 2 > 8) ? 8 : n_C * 2)
struct layer_param {
int M; //Ilosc tablic podawanych na wejscie
int pad; //Grubosc warstwy zer na krawedziach (zero-padding)
int F; //Rozmiar 2D filtra (F x F)
int F_MP; //Rozmiar 2D filtra do max poolingu (F_MP x F_MP)
int stride; //Ilosc przeskakiwanych pikseli przy konwolucji na inkrementacje
int stride_MP; //To samo, tylko przy max poolingu
int n_Hprev; //Wysokosc tablicy wejsciowej podawanej na wejscie sieci
int n_Wprev; //Szerokosc tablicy wejsciowej podawanej na wejscie sieci
int n_Cprev; //Glebokosc tablicy wejsciowej, jednoczesnie musi to byc glebokosc filtra (F x F x C)
int n_H; //Wysokosc tablicy uzyskanej po konwolucji kernela z wejsciem
int n_W;
int n_C; //Ilosc filtrow, jednoczesnie glebokosc wyjscia warstwy
int n_Hout; //Wysokosc tablicy wyjsciowej warstwy
int n_Wout;
double alpha; //Predkosc uczenia
};
struct cache_data {
double** IN; //Tablica wejsciowa
double** Z; //Wynik splotu
double** A; //Wynik Aktywacji
double** OUT; //Poprzedni wynik po max poolingu, jednoczescie wyjscie warstwy sieci
double** kernel; //Filtr
double** dW; //Gradient kosztu wzgledem kerneli
double** dA; //Gradient kosztu wzgledem warstwy
double** dAprev; //Gradient kosztu wzgledem wyjscia warstwy n_l - 1
double** dZ; //Gradient kosztu wzgledem wyniku konwolucji
};
void set_random_IN(layer_param, double**&); //Ustawia losowe wejscie (do testowania)
void set_new_IN(double**&, double**&, layer_param l);
void show_results(layer_param, cache_data&); //Wyswietla zawartosc koncowych i posrednich wynikow w warstwie
void brief_inf(layer_param, double**); //Krotka informacja o wyjsciu sieci
void forw_prop(layer_param, cache_data&); //Najwazniejsza funkcja (konwolucja, aktywacja, maxpooling)
void simple_del(double**&, int); //Usuwanie pamieci
void update_param(layer_param&, layer_param&); //Ustawianie nowych parametrow warstwy
void prep_new_arrays(layer_param, cache_data&); //Tworzenie nowych tablic wynikowych
void prep_gradients(layer_param, cache_data&); //Tworzenie gradientow (narazie losowo, bez funkcji kosztu)
void show_gradients(layer_param, cache_data&);
void back_prop(layer_param, cache_data&);
int main() {
srand(time(NULL));
int number_of_layers = 2;
layer_param* l = new layer_param[number_of_layers];
cache_data* cache = new cache_data[number_of_layers];
int n_l = 0;
layer_param l_prev;
l[n_l].M = 1;
l[n_l].pad = 0;
l[n_l].F = 3;
l[n_l].F_MP = 2;
l[n_l].stride = 1;
l[n_l].stride_MP = 2;
l[n_l].alpha = 0.1;
int IN_size = 16; //Rzeczywisty rozmiar wejscia
int IN_depth = 1; //Rzeczywista glebokosc wejscia
l[n_l].n_Hprev = IN_size + 2 * l[n_l].pad;
l[n_l].n_Wprev = IN_size + 2 * l[n_l].pad;
l[n_l].n_Cprev = IN_depth;
l[n_l].n_H = int((l[n_l].n_Hprev - l[n_l].F) / l[n_l].stride) + 1;
l[n_l].n_W = int((l[n_l].n_Wprev - l[n_l].F) / l[n_l].stride) + 1;
l[n_l].n_C = 1;
l[n_l].n_Hout = int((l[n_l].n_H - l[n_l].F_MP) / l[n_l].stride_MP) + 1;
l[n_l].n_Wout = int((l[n_l].n_W - l[n_l].F_MP) / l[n_l].stride_MP) + 1;
for (n_l = 0; n_l < number_of_layers; n_l++) {
std::cout << "\n\n#### WARSTWA: " << n_l + 1 << "#### \n";
if (n_l == 0) set_random_IN(l[n_l], cache[n_l].IN);
else {
l_prev = l[n_l - 1];
update_param(l_prev, l[n_l]);
set_new_IN(cache[n_l].IN, cache[n_l - 1].OUT, l[n_l]);
}
prep_new_arrays(l[n_l], cache[n_l]);
forw_prop(l[n_l], cache[n_l]);
prep_gradients(l[n_l], cache[n_l]);
if (l[n_l].n_H < 25) show_results(l[n_l], cache[n_l]);
else brief_inf(l[n_l], cache[n_l].OUT);
//back_prop(l[n_l], cache[n_l]);
//show_gradients(l[n_l], cache[n_l]); //Funkcja wyswietla gradient
}
return 0;
}
void set_random_IN(layer_param l, double**& IN) {
IN = new double* [l.M];
for (int i = 0; i < l.M; i++) {
IN[i] = new double[l.n_Cprev * l.n_Hprev * l.n_Wprev];
}
for (int m = 0; m < l.M; m++) { //Dla kazdego badanego przypadku (np. pojedynczej mapy bajtowej- spektogram)
for (int h = 0; h < l.n_Hprev; h++) { //Przejdz po kazdym wierszu
for (int w = 0; w < l.n_Wprev; w++) { //Przejdz po kazdej kolumnie
for (int c = 0; c < l.n_Cprev; c++) { //Przejdz po kazdym kanale (np. dla wejscia w postaci zdjecia rgb - 3 kanaly)
if (h < l.pad || h > l.n_Hprev - l.pad - 1) IN[m][w + l.n_Wprev * (h + l.n_Hprev * c)] = 0; //Ustawianie zer dla zero paddingu
else if (w < l.pad || w > l.n_Wprev - l.pad - 1) IN[m][w + l.n_Wprev * (h + l.n_Hprev * c)] = 0;
else IN[m][w + l.n_Wprev * (h + l.n_Hprev * c)] = (rand() % 10 + 1)/10.; //W tablicy wejsciowej beda same wartosci int
}
}
}
}
}
void set_new_IN(double**& IN, double**& OUT, layer_param l) {
IN = new double* [l.M];
for (int i = 0; i < l.M; i++) {
IN[i] = new double[l.n_Cprev * l.n_Hprev * l.n_Wprev];
}
for (int m = 0; m < l.M; m++) {
for (int c = 0; c < l.n_Cprev; c++) {
for (int h = 0; h < l.n_Hprev; h++) {
for (int w = 0; w < l.n_Wprev; w++) {
IN[m][w + l.n_Wprev * (h + l.n_Hprev * c)] = OUT[m][w + l.n_Wprev * (h + l.n_Hprev * c)];
}
}
}
}
}
void update_param(layer_param& l_prev, layer_param& l) {
l.M = l_prev.M;
l.pad = l_prev.pad;
l.F = l_prev.F;
l.F_MP = l_prev.F_MP;
l.stride = l_prev.stride;
l.stride_MP = l_prev.stride_MP;
l.alpha = l_prev.alpha;
l.n_Hprev = l_prev.n_Hout;
l.n_Wprev = l_prev.n_Wout;
l.n_Cprev = l_prev.n_C;
l.n_H = int((l.n_Hprev - l.F) / l.stride) + 1;
l.n_W = int((l.n_Wprev - l.F) / l.stride) + 1;
l.n_C = KERNEL_SIZE(l_prev.n_C);
l.n_Hout = int((l.n_H - l.F_MP) / l.stride_MP) + 1;
l.n_Wout = int((l.n_W - l.F_MP) / l.stride_MP) + 1;
}
void prep_new_arrays(layer_param l, cache_data& cache) {
cache.Z = new double* [l.M];
cache.A = new double* [l.M];
cache.OUT = new double* [l.M];
cache.kernel = new double* [l.n_C];
for (int i = 0; i < l.M; i++) {
cache.Z[i] = new double[l.n_C * l.n_H * l.n_W];
cache.A[i] = new double[l.n_C * l.n_H * l.n_W];
cache.OUT[i] = new double[l.n_C * l.n_Hout * l.n_Wout];
}
for (int i = 0; i < l.n_C; i++) {
cache.kernel[i] = new double[l.n_Cprev * l.F * l.F];
}
for (int c = 0; c < l.n_C; c++) {
for (int h = 0; h < l.F; h++) {
for (int w = 0; w < l.F; w++) {
for (int d = 0; d < l.n_Cprev; d++) {
cache.kernel[c][w + l.F * (h + l.F * d)] = (rand()%10000 - 5000) * 0.0001; //Ustawianie losowych wag filtra
}
}
}
}
}
void prep_gradients(layer_param l, cache_data& cache) {
cache.dZ = new double* [l.M];
cache.dA = new double* [l.M];
cache.dAprev = new double* [l.M];
cache.dW = new double* [l.n_C];
for (int i = 0; i < l.M; i++) {
cache.dZ[i] = new double[l.n_C * l.n_H * l.n_W];
}
for (int i = 0; i < l.M; i++) {
cache.dA[i] = new double[l.n_C * l.n_Hout * l.n_Wout];
}
for (int i = 0; i < l.M; i++) {
cache.dAprev[i] = new double[l.n_Cprev * l.n_Hprev * l.n_Wprev];
}
for (int i = 0; i < l.n_C; i++) {
cache.dW[i] = new double[l.n_Cprev * l.F * l.F];
}
for (int m = 0; m < l.M; m++) {
for (int c = 0; c < l.n_C; c++) {
for (int h = 0; h < l.n_Hout; h++) {
for (int w = 0; w < l.n_Wout; w++) {
cache.dA[m][w + l.n_Wout * (h + l.n_Hout * c)] = (rand()%10000 - 5000) * 0.0001;
}
}
}
}
for (int m = 0; m < l.M; m++) {
for (int c = 0; c < l.n_Cprev; c++) {
for (int h = 0; h < l.n_Hprev; h++) {
for (int w = 0; w < l.n_Wprev; w++) {
cache.dAprev[m][w + l.n_Wprev * (h + l.n_Hprev * c)] = 0;
}
}
}
}
for (int c = 0; c < l.n_C; c++) {
for (int h = 0; h < l.F; h++) {
for (int w = 0; w < l.F; w++) {
for (int d = 0; d < l.n_Cprev; d++) {
cache.dW[c][w + l.F * (h + l.F * d)] = 0;
}
}
}
}
double maximum;
int vert_start, vert_end;
int horiz_start, horiz_end;
for (int m = 0; m < l.M; m++) { //Dla kazdego przypadku
for (int h = 0; h < l.n_Hout; h++) { //Dla kazdego wiersza wyjscia (wyniku max poolingu)
for (int w = 0; w < l.n_Wout; w++) { // Dla kazdej kolumny wyjscia
for (int c = 0; c < l.n_C; c++) { //Dla kazdego kanalu wyjscia
vert_start = h * l.stride_MP;
vert_end = vert_start + l.F_MP;
horiz_start = w * l.stride_MP;
horiz_end = horiz_start + l.F_MP;
maximum = 0;
for (int j = vert_start; j < vert_end; j++) { //Dla kazdego wiersza wycinka wyniku aktywacji
for (int k = horiz_start; k < horiz_end; k++) { //Dla kazdej kolumny wycinka wyniku aktywacji
if (cache.A[m][k + l.n_W * (j + l.n_H * c)] > maximum) maximum = cache.A[m][k + l.n_W * (j + l.n_H * c)];
}
}
for (int j = vert_start; j < vert_end; j++) {
for (int k = horiz_start; k < horiz_end; k++) {
if (cache.A[m][k + l.n_W * (j + l.n_H * c)] != maximum || maximum == 0) cache.dZ[m][k + l.n_W * (j + l.n_H * c)] = 0;
else cache.dZ[m][k + l.n_W * (j + l.n_H * c)] = cache.dA[m][w + l.n_Wout * (h + l.n_Hout * c)];
}
}
}
}
}
}
for (int m = 0; m < l.M; m++) {
for (int h = 0; h < l.n_H; h++) {
for (int w = 0; w < l.n_W; w++) {
for (int c = 0; c < l.n_C; c++) {
vert_start = h;
vert_end = vert_start + l.F;
horiz_start = w;
horiz_end = horiz_start + l.F;
for (int d = 0; d < l.n_Cprev; d++) {
for (int j = vert_start; j < vert_end; j++) {
for (int k = horiz_start; k < horiz_end; k++) {
if (cache.dZ[m][w + l.n_W * (h + l.n_H * c)] < 0) cache.dZ[m][w + l.n_W * (h + l.n_H * c)] = 0;
cache.dAprev[m][j + l.n_Wprev * (k + l.n_Hprev * d)] += cache.kernel[c][(k - horiz_start) + l.F * ((j - vert_start) + l.F * d)] *
cache.dZ[m][w + l.n_W * (h + l.n_H * c)];
cache.dW[c][(k - horiz_start) + l.F * ((j - vert_start) + l.F * d)] += cache.IN[m][j + l.n_Wprev * (k + l.n_Hprev * d)] *
cache.dZ[m][w + l.n_W * (h + l.n_H * c)];
}
}
}
}
}
}
}
}
void brief_inf(layer_param l, double** OUT) {
for (int m = 0; m < l.M; m++)
std::cout << "Wyjscie: " << m + 1 << " Kanaly: " << l.n_C << " (" << l.n_Hout << "x" << l.n_Wout << "x" << l.n_C << ")" << "\n" << std::fixed;
}
void forw_prop(layer_param l, cache_data& cache) {
int M = l.M;
int pad = l.pad;
int F = l.F;
int F_MP = l.F_MP;
int stride = l.stride;
int stride_MP = l.stride_MP;
int n_Hprev = l.n_Hprev;
int n_Wprev = l.n_Wprev;
int n_Cprev = l.n_Cprev;
int n_H = l.n_H;
int n_W = l.n_W;
int n_C = l.n_C;
int n_Hout = l.n_Hout;
int n_Wout = l.n_Wout;
int vert_start = 0;
int vert_end = 0;
int horiz_start = 0;
int horiz_end = 0;
for (int m = 0; m < M; m++) { //Dla kazdego przypadku
for (int h = 0; h < n_H; h++) { //Dla kazdego wiersza
for (int w = 0; w < n_W; w++) { //Dla kazdej kolumny
for (int c = 0; c < n_C; c++) { //Dla kazdego kanalu (kanalow bedzie tyle, ile chcemy kerneli)
vert_start = h * stride; //Poczatek wycinka w pionie
vert_end = vert_start + F; //Koniec wycinka w pionie
horiz_start = w * stride; //Poczatek wycika w poziomie
horiz_end = horiz_start + F; //Koniec wycinka w poziomie
cache.Z[m][w + n_W * (h + n_H * c)] = 0;
for (int d = 0; d < n_Cprev; d++) { //Dla kazdego kanalu w tablicy wejsciowej
for (int j = vert_start; j < vert_end; j++) { //Dla wybranych wierszy
for (int k = horiz_start; k < horiz_end; k++) { //Dla wybranych kolumn
cache.Z[m][w + n_W * (h + n_H * c)] += cache.kernel[c][(k - horiz_start) + F * ((j - vert_start) + F * d)] *
cache.IN[m][k + n_Wprev * (j + n_Hprev * d)];
//Pomnoz wartosc/piksel wycinka przez wage kernela i dodaj do wyniku konwolucji
}
}
}
cache.A[m][w + n_W * (h + n_H * c)] = RELU(cache.Z[m][w + n_W * (h + n_H * c)]); //Aktywowanie danej wartosci/neuronu
}
}
}
}
double maximum = 0;
for (int m = 0; m < M; m++) { //Dla kazdego przypadku
for (int h = 0; h < n_Hout; h++) { //Dla kazdego wiersza wyjscia (wyniku max poolingu)
for (int w = 0; w < n_Wout; w++) { // Dla kazdej kolumny wyjscia
for (int c = 0; c < n_C; c++) { //Dla kazdego kanalu wyjscia
if (n_Hout > 1) {
vert_start = h * stride_MP;
vert_end = vert_start + F_MP;
horiz_start = w * stride_MP;
horiz_end = horiz_start + F_MP;
maximum = 0;
for (int j = vert_start; j < vert_end; j++) { //Dla kazdego wiersza wycinka wyniku aktywacji
for (int k = horiz_start; k < horiz_end; k++) { //Dla kazdej kolumny wycinka wyniku aktywacji
if (cache.A[m][k + n_W * (j + n_H * c)] > maximum) maximum = cache.A[m][k + n_W * (j + n_H * c)]; //Wybierz maksimum z wycinka
}
}
cache.OUT[m][w + n_Wout * (h + n_Hout * c)] = maximum;
}
else
cache.OUT[m][w + n_Wout * (h + n_Hout * c)] = cache.A[m][0 + n_W * (0 + n_H * c)];
}
}
}
}
}
void show_gradients(layer_param l, cache_data& cache) {
for (int m = 0; m < l.M; m++) {
for (int c = 0; c < l.n_Cprev; c++) {
std::cout << "dAprev: " << m + 1 << " Kanal: " << c + 1 << " (" << l.n_Hprev << "x" << l.n_Wprev << "x" << l.n_Cprev << ")" << "\n";
for (int h = 0; h < l.n_Hprev; h++) {
for (int w = 0; w < l.n_Wprev; w++) {
std::cout << cache.dAprev[m][w + l.n_Wprev * (h + l.n_Hprev * c)] << " ";
}
std::cout << "\n";
}
}
std::cout << "\n\n";
}
std::cout << "#### dW #### \n\n";
for (int c = 0; c < l.n_C; c++) {
for (int d = 0; d < l.n_Cprev; d++) {
std::cout << "dW: " << c + 1 << " Kanal: " << d + 1 << " (" << l.F << "x" << l.F << "x" << l.n_Cprev << ")" << "\n" << std::fixed;
for (int h = 0; h < l.F; h++) {
for (int w = 0; w < l.F; w++) {
std::cout << cache.dW[c][w + l.F * (h + l.F * d)] << " ";
}
std::cout << "\n";
}
}
std::cout << "\n\n";
}
std::cout << "#### dZ #### \n\n";
for (int m = 0; m < l.M; m++) {
for (int c = 0; c < l.n_C; c++) {
std::cout << "dZ: " << m + 1 << " Kanal: " << c + 1 << " (" << l.n_H << "x" << l.n_W << "x" << l.n_C << ")" << "\n" << std::fixed;
for (int h = 0; h < l.n_H; h++) {
for (int w = 0; w < l.n_W; w++) {
std::cout << cache.dZ[m][w + l.n_W * (h + l.n_H * c)] << " ";
}
std::cout << "\n";
}
std::cout << "\n";
}
}
std::cout << "#### dA #### \n\n";
for (int m = 0; m < l.M; m++) {
for (int c = 0; c < l.n_C; c++) {
std::cout << "dA: " << m + 1 << " Kanal: " << c + 1 << " (" << l.n_Hout << "x" << l.n_Wout << "x" << l.n_C << ")" << "\n" << std::fixed;
for (int h = 0; h < l.n_Hout; h++) {
for (int w = 0; w < l.n_Wout; w++) {
std::cout << cache.dA[m][w + l.n_Wout * (h + l.n_Hout * c)] << " ";
}
std::cout << "\n";
}
std::cout << "\n";
}
}
}
void simple_del(double**& arr, int len) {
for (int i = 0; i < len; i++) {
delete[] arr[i];
}
delete[] arr;
}
void show_results(layer_param l, cache_data& cache)
{
std::cout.precision(4);
for (int m = 0; m < l.M; m++) {
for (int c = 0; c < l.n_Cprev; c++) {
std::cout << "Wejscie: " << m + 1 << " Kanal: " << c + 1 << " (" << l.n_Hprev << "x" << l.n_Wprev << "x" << l.n_Cprev << ")" << "\n";
for (int h = 0; h < l.n_Hprev; h++) {
for (int w = 0; w < l.n_Wprev; w++) {
std::cout << cache.IN[m][w + l.n_Wprev * (h + l.n_Hprev * c)] << " ";
}
std::cout << "\n";
}
}
std::cout << "\n\n";
}
std::cout << "#### FILTRY #### \n\n";
for (int c = 0; c < l.n_C; c++) {
for (int d = 0; d < l.n_Cprev; d++) {
std::cout << "Kernel: " << c + 1 << " Kanal: " << d + 1 << " (" << l.F << "x" << l.F << "x" << l.n_Cprev << ")" << "\n" << std::fixed;
for (int h = 0; h < l.F; h++) {
for (int w = 0; w < l.F; w++) {
std::cout << cache.kernel[c][w + l.F * (h + l.F * d)] << " ";
}
std::cout << "\n";
}
}
std::cout << "\n\n";
}
std::cout << "#### WYNIKI KONWOLUCJI #### \n\n";
for (int m = 0; m < l.M; m++) {
for (int c = 0; c < l.n_C; c++) {
std::cout << "Z: " << m + 1 << " Kanal: " << c + 1 << " (" << l.n_H << "x" << l.n_W << "x" << l.n_C << ")" << "\n" << std::fixed;
for (int h = 0; h < l.n_H; h++) {
for (int w = 0; w < l.n_W; w++) {
std::cout << cache.Z[m][w + l.n_W * (h + l.n_H * c)] << " ";
}
std::cout << "\n";
}
std::cout << "\n";
}
}
std::cout << "#### WYNIKI AKTYWACJI (RELU) #### \n\n";
for (int m = 0; m < l.M; m++) {
for (int c = 0; c < l.n_C; c++) {
std::cout << "A: " << m + 1 << " Kanal: " << c + 1 << " (" << l.n_H << "x" << l.n_W << "x" << l.n_C << ")" << "\n" << std::fixed;
for (int h = 0; h < l.n_H; h++) {
for (int w = 0; w < l.n_W; w++) {
std::cout << cache.A[m][w + l.n_W * (h + l.n_H * c)] << " ";
}
std::cout << "\n";
}
std::cout << "\n";
}
}
std::cout << "#### WYNIKI MAX POOLINGU #### \n\n";
for (int m = 0; m < l.M; m++) {
for (int c = 0; c < l.n_C; c++) {
std::cout << "Wyjscie: " << m + 1 << " Kanal: " << c + 1 << " (" << l.n_Hout << "x" << l.n_Wout << "x" << l.n_C << ")" << "\n" << std::fixed;
for (int h = 0; h < l.n_Hout; h++) {
for (int w = 0; w < l.n_Wout; w++) {
std::cout << cache.OUT[m][w + l.n_Wout * (h + l.n_Hout * c)] << " ";
}
std::cout << "\n";
}
std::cout << "\n";
}
}
}
void back_prop(layer_param l, cache_data& cache) {
std::cout << "#### FILTRY PO PO PROPAGACJI WSTECZNEJ #### \n\n";
for (int c = 0; c < l.n_C; c++) {
for (int d = 0; d < l.n_Cprev; d++) {
std::cout << "Wagi: " << c + 1 << " Kanal: " << d + 1 << " (" << l.F << "x" << l.F << "x" << l.n_Cprev << ")" << "\n" << std::fixed;
for (int h = 0; h < l.F; h++) {
for (int w = 0; w < l.F; w++) {
std::cout << cache.kernel[c][w + l.F * (h + l.F * d)] - l.alpha * cache.dW[c][w + l.F * (h + l.F * d)] << " ";
}
std::cout << "\n";
}
}
std::cout << "\n\n";
}
} | //#include "shallow.h"
#include <hip/hip_runtime.h>
#include <iostream>
#include <time.h>
#include <stdlib.h>
#define RELU(a) ((a > 0) ? a : 0)
#define KERNEL_SIZE(n_C) ((n_C * 2 > 8) ? 8 : n_C * 2)
struct layer_param {
int M; //Ilosc tablic podawanych na wejscie
int pad; //Grubosc warstwy zer na krawedziach (zero-padding)
int F; //Rozmiar 2D filtra (F x F)
int F_MP; //Rozmiar 2D filtra do max poolingu (F_MP x F_MP)
int stride; //Ilosc przeskakiwanych pikseli przy konwolucji na inkrementacje
int stride_MP; //To samo, tylko przy max poolingu
int n_Hprev; //Wysokosc tablicy wejsciowej podawanej na wejscie sieci
int n_Wprev; //Szerokosc tablicy wejsciowej podawanej na wejscie sieci
int n_Cprev; //Glebokosc tablicy wejsciowej, jednoczesnie musi to byc glebokosc filtra (F x F x C)
int n_H; //Wysokosc tablicy uzyskanej po konwolucji kernela z wejsciem
int n_W;
int n_C; //Ilosc filtrow, jednoczesnie glebokosc wyjscia warstwy
int n_Hout; //Wysokosc tablicy wyjsciowej warstwy
int n_Wout;
double alpha; //Predkosc uczenia
};
struct cache_data {
double** IN; //Tablica wejsciowa
double** Z; //Wynik splotu
double** A; //Wynik Aktywacji
double** OUT; //Poprzedni wynik po max poolingu, jednoczescie wyjscie warstwy sieci
double** kernel; //Filtr
double** dW; //Gradient kosztu wzgledem kerneli
double** dA; //Gradient kosztu wzgledem warstwy
double** dAprev; //Gradient kosztu wzgledem wyjscia warstwy n_l - 1
double** dZ; //Gradient kosztu wzgledem wyniku konwolucji
};
void set_random_IN(layer_param, double**&); //Ustawia losowe wejscie (do testowania)
void set_new_IN(double**&, double**&, layer_param l);
void show_results(layer_param, cache_data&); //Wyswietla zawartosc koncowych i posrednich wynikow w warstwie
void brief_inf(layer_param, double**); //Krotka informacja o wyjsciu sieci
void forw_prop(layer_param, cache_data&); //Najwazniejsza funkcja (konwolucja, aktywacja, maxpooling)
void simple_del(double**&, int); //Usuwanie pamieci
void update_param(layer_param&, layer_param&); //Ustawianie nowych parametrow warstwy
void prep_new_arrays(layer_param, cache_data&); //Tworzenie nowych tablic wynikowych
void prep_gradients(layer_param, cache_data&); //Tworzenie gradientow (narazie losowo, bez funkcji kosztu)
void show_gradients(layer_param, cache_data&);
void back_prop(layer_param, cache_data&);
int main() {
srand(time(NULL));
int number_of_layers = 2;
layer_param* l = new layer_param[number_of_layers];
cache_data* cache = new cache_data[number_of_layers];
int n_l = 0;
layer_param l_prev;
l[n_l].M = 1;
l[n_l].pad = 0;
l[n_l].F = 3;
l[n_l].F_MP = 2;
l[n_l].stride = 1;
l[n_l].stride_MP = 2;
l[n_l].alpha = 0.1;
int IN_size = 16; //Rzeczywisty rozmiar wejscia
int IN_depth = 1; //Rzeczywista glebokosc wejscia
l[n_l].n_Hprev = IN_size + 2 * l[n_l].pad;
l[n_l].n_Wprev = IN_size + 2 * l[n_l].pad;
l[n_l].n_Cprev = IN_depth;
l[n_l].n_H = int((l[n_l].n_Hprev - l[n_l].F) / l[n_l].stride) + 1;
l[n_l].n_W = int((l[n_l].n_Wprev - l[n_l].F) / l[n_l].stride) + 1;
l[n_l].n_C = 1;
l[n_l].n_Hout = int((l[n_l].n_H - l[n_l].F_MP) / l[n_l].stride_MP) + 1;
l[n_l].n_Wout = int((l[n_l].n_W - l[n_l].F_MP) / l[n_l].stride_MP) + 1;
for (n_l = 0; n_l < number_of_layers; n_l++) {
std::cout << "\n\n#### WARSTWA: " << n_l + 1 << "#### \n";
if (n_l == 0) set_random_IN(l[n_l], cache[n_l].IN);
else {
l_prev = l[n_l - 1];
update_param(l_prev, l[n_l]);
set_new_IN(cache[n_l].IN, cache[n_l - 1].OUT, l[n_l]);
}
prep_new_arrays(l[n_l], cache[n_l]);
forw_prop(l[n_l], cache[n_l]);
prep_gradients(l[n_l], cache[n_l]);
if (l[n_l].n_H < 25) show_results(l[n_l], cache[n_l]);
else brief_inf(l[n_l], cache[n_l].OUT);
//back_prop(l[n_l], cache[n_l]);
//show_gradients(l[n_l], cache[n_l]); //Funkcja wyswietla gradient
}
return 0;
}
void set_random_IN(layer_param l, double**& IN) {
IN = new double* [l.M];
for (int i = 0; i < l.M; i++) {
IN[i] = new double[l.n_Cprev * l.n_Hprev * l.n_Wprev];
}
for (int m = 0; m < l.M; m++) { //Dla kazdego badanego przypadku (np. pojedynczej mapy bajtowej- spektogram)
for (int h = 0; h < l.n_Hprev; h++) { //Przejdz po kazdym wierszu
for (int w = 0; w < l.n_Wprev; w++) { //Przejdz po kazdej kolumnie
for (int c = 0; c < l.n_Cprev; c++) { //Przejdz po kazdym kanale (np. dla wejscia w postaci zdjecia rgb - 3 kanaly)
if (h < l.pad || h > l.n_Hprev - l.pad - 1) IN[m][w + l.n_Wprev * (h + l.n_Hprev * c)] = 0; //Ustawianie zer dla zero paddingu
else if (w < l.pad || w > l.n_Wprev - l.pad - 1) IN[m][w + l.n_Wprev * (h + l.n_Hprev * c)] = 0;
else IN[m][w + l.n_Wprev * (h + l.n_Hprev * c)] = (rand() % 10 + 1)/10.; //W tablicy wejsciowej beda same wartosci int
}
}
}
}
}
void set_new_IN(double**& IN, double**& OUT, layer_param l) {
IN = new double* [l.M];
for (int i = 0; i < l.M; i++) {
IN[i] = new double[l.n_Cprev * l.n_Hprev * l.n_Wprev];
}
for (int m = 0; m < l.M; m++) {
for (int c = 0; c < l.n_Cprev; c++) {
for (int h = 0; h < l.n_Hprev; h++) {
for (int w = 0; w < l.n_Wprev; w++) {
IN[m][w + l.n_Wprev * (h + l.n_Hprev * c)] = OUT[m][w + l.n_Wprev * (h + l.n_Hprev * c)];
}
}
}
}
}
void update_param(layer_param& l_prev, layer_param& l) {
l.M = l_prev.M;
l.pad = l_prev.pad;
l.F = l_prev.F;
l.F_MP = l_prev.F_MP;
l.stride = l_prev.stride;
l.stride_MP = l_prev.stride_MP;
l.alpha = l_prev.alpha;
l.n_Hprev = l_prev.n_Hout;
l.n_Wprev = l_prev.n_Wout;
l.n_Cprev = l_prev.n_C;
l.n_H = int((l.n_Hprev - l.F) / l.stride) + 1;
l.n_W = int((l.n_Wprev - l.F) / l.stride) + 1;
l.n_C = KERNEL_SIZE(l_prev.n_C);
l.n_Hout = int((l.n_H - l.F_MP) / l.stride_MP) + 1;
l.n_Wout = int((l.n_W - l.F_MP) / l.stride_MP) + 1;
}
void prep_new_arrays(layer_param l, cache_data& cache) {
cache.Z = new double* [l.M];
cache.A = new double* [l.M];
cache.OUT = new double* [l.M];
cache.kernel = new double* [l.n_C];
for (int i = 0; i < l.M; i++) {
cache.Z[i] = new double[l.n_C * l.n_H * l.n_W];
cache.A[i] = new double[l.n_C * l.n_H * l.n_W];
cache.OUT[i] = new double[l.n_C * l.n_Hout * l.n_Wout];
}
for (int i = 0; i < l.n_C; i++) {
cache.kernel[i] = new double[l.n_Cprev * l.F * l.F];
}
for (int c = 0; c < l.n_C; c++) {
for (int h = 0; h < l.F; h++) {
for (int w = 0; w < l.F; w++) {
for (int d = 0; d < l.n_Cprev; d++) {
cache.kernel[c][w + l.F * (h + l.F * d)] = (rand()%10000 - 5000) * 0.0001; //Ustawianie losowych wag filtra
}
}
}
}
}
void prep_gradients(layer_param l, cache_data& cache) {
cache.dZ = new double* [l.M];
cache.dA = new double* [l.M];
cache.dAprev = new double* [l.M];
cache.dW = new double* [l.n_C];
for (int i = 0; i < l.M; i++) {
cache.dZ[i] = new double[l.n_C * l.n_H * l.n_W];
}
for (int i = 0; i < l.M; i++) {
cache.dA[i] = new double[l.n_C * l.n_Hout * l.n_Wout];
}
for (int i = 0; i < l.M; i++) {
cache.dAprev[i] = new double[l.n_Cprev * l.n_Hprev * l.n_Wprev];
}
for (int i = 0; i < l.n_C; i++) {
cache.dW[i] = new double[l.n_Cprev * l.F * l.F];
}
for (int m = 0; m < l.M; m++) {
for (int c = 0; c < l.n_C; c++) {
for (int h = 0; h < l.n_Hout; h++) {
for (int w = 0; w < l.n_Wout; w++) {
cache.dA[m][w + l.n_Wout * (h + l.n_Hout * c)] = (rand()%10000 - 5000) * 0.0001;
}
}
}
}
for (int m = 0; m < l.M; m++) {
for (int c = 0; c < l.n_Cprev; c++) {
for (int h = 0; h < l.n_Hprev; h++) {
for (int w = 0; w < l.n_Wprev; w++) {
cache.dAprev[m][w + l.n_Wprev * (h + l.n_Hprev * c)] = 0;
}
}
}
}
for (int c = 0; c < l.n_C; c++) {
for (int h = 0; h < l.F; h++) {
for (int w = 0; w < l.F; w++) {
for (int d = 0; d < l.n_Cprev; d++) {
cache.dW[c][w + l.F * (h + l.F * d)] = 0;
}
}
}
}
double maximum;
int vert_start, vert_end;
int horiz_start, horiz_end;
for (int m = 0; m < l.M; m++) { //Dla kazdego przypadku
for (int h = 0; h < l.n_Hout; h++) { //Dla kazdego wiersza wyjscia (wyniku max poolingu)
for (int w = 0; w < l.n_Wout; w++) { // Dla kazdej kolumny wyjscia
for (int c = 0; c < l.n_C; c++) { //Dla kazdego kanalu wyjscia
vert_start = h * l.stride_MP;
vert_end = vert_start + l.F_MP;
horiz_start = w * l.stride_MP;
horiz_end = horiz_start + l.F_MP;
maximum = 0;
for (int j = vert_start; j < vert_end; j++) { //Dla kazdego wiersza wycinka wyniku aktywacji
for (int k = horiz_start; k < horiz_end; k++) { //Dla kazdej kolumny wycinka wyniku aktywacji
if (cache.A[m][k + l.n_W * (j + l.n_H * c)] > maximum) maximum = cache.A[m][k + l.n_W * (j + l.n_H * c)];
}
}
for (int j = vert_start; j < vert_end; j++) {
for (int k = horiz_start; k < horiz_end; k++) {
if (cache.A[m][k + l.n_W * (j + l.n_H * c)] != maximum || maximum == 0) cache.dZ[m][k + l.n_W * (j + l.n_H * c)] = 0;
else cache.dZ[m][k + l.n_W * (j + l.n_H * c)] = cache.dA[m][w + l.n_Wout * (h + l.n_Hout * c)];
}
}
}
}
}
}
for (int m = 0; m < l.M; m++) {
for (int h = 0; h < l.n_H; h++) {
for (int w = 0; w < l.n_W; w++) {
for (int c = 0; c < l.n_C; c++) {
vert_start = h;
vert_end = vert_start + l.F;
horiz_start = w;
horiz_end = horiz_start + l.F;
for (int d = 0; d < l.n_Cprev; d++) {
for (int j = vert_start; j < vert_end; j++) {
for (int k = horiz_start; k < horiz_end; k++) {
if (cache.dZ[m][w + l.n_W * (h + l.n_H * c)] < 0) cache.dZ[m][w + l.n_W * (h + l.n_H * c)] = 0;
cache.dAprev[m][j + l.n_Wprev * (k + l.n_Hprev * d)] += cache.kernel[c][(k - horiz_start) + l.F * ((j - vert_start) + l.F * d)] *
cache.dZ[m][w + l.n_W * (h + l.n_H * c)];
cache.dW[c][(k - horiz_start) + l.F * ((j - vert_start) + l.F * d)] += cache.IN[m][j + l.n_Wprev * (k + l.n_Hprev * d)] *
cache.dZ[m][w + l.n_W * (h + l.n_H * c)];
}
}
}
}
}
}
}
}
void brief_inf(layer_param l, double** OUT) {
for (int m = 0; m < l.M; m++)
std::cout << "Wyjscie: " << m + 1 << " Kanaly: " << l.n_C << " (" << l.n_Hout << "x" << l.n_Wout << "x" << l.n_C << ")" << "\n" << std::fixed;
}
void forw_prop(layer_param l, cache_data& cache) {
int M = l.M;
int pad = l.pad;
int F = l.F;
int F_MP = l.F_MP;
int stride = l.stride;
int stride_MP = l.stride_MP;
int n_Hprev = l.n_Hprev;
int n_Wprev = l.n_Wprev;
int n_Cprev = l.n_Cprev;
int n_H = l.n_H;
int n_W = l.n_W;
int n_C = l.n_C;
int n_Hout = l.n_Hout;
int n_Wout = l.n_Wout;
int vert_start = 0;
int vert_end = 0;
int horiz_start = 0;
int horiz_end = 0;
for (int m = 0; m < M; m++) { //Dla kazdego przypadku
for (int h = 0; h < n_H; h++) { //Dla kazdego wiersza
for (int w = 0; w < n_W; w++) { //Dla kazdej kolumny
for (int c = 0; c < n_C; c++) { //Dla kazdego kanalu (kanalow bedzie tyle, ile chcemy kerneli)
vert_start = h * stride; //Poczatek wycinka w pionie
vert_end = vert_start + F; //Koniec wycinka w pionie
horiz_start = w * stride; //Poczatek wycika w poziomie
horiz_end = horiz_start + F; //Koniec wycinka w poziomie
cache.Z[m][w + n_W * (h + n_H * c)] = 0;
for (int d = 0; d < n_Cprev; d++) { //Dla kazdego kanalu w tablicy wejsciowej
for (int j = vert_start; j < vert_end; j++) { //Dla wybranych wierszy
for (int k = horiz_start; k < horiz_end; k++) { //Dla wybranych kolumn
cache.Z[m][w + n_W * (h + n_H * c)] += cache.kernel[c][(k - horiz_start) + F * ((j - vert_start) + F * d)] *
cache.IN[m][k + n_Wprev * (j + n_Hprev * d)];
//Pomnoz wartosc/piksel wycinka przez wage kernela i dodaj do wyniku konwolucji
}
}
}
cache.A[m][w + n_W * (h + n_H * c)] = RELU(cache.Z[m][w + n_W * (h + n_H * c)]); //Aktywowanie danej wartosci/neuronu
}
}
}
}
double maximum = 0;
for (int m = 0; m < M; m++) { //Dla kazdego przypadku
for (int h = 0; h < n_Hout; h++) { //Dla kazdego wiersza wyjscia (wyniku max poolingu)
for (int w = 0; w < n_Wout; w++) { // Dla kazdej kolumny wyjscia
for (int c = 0; c < n_C; c++) { //Dla kazdego kanalu wyjscia
if (n_Hout > 1) {
vert_start = h * stride_MP;
vert_end = vert_start + F_MP;
horiz_start = w * stride_MP;
horiz_end = horiz_start + F_MP;
maximum = 0;
for (int j = vert_start; j < vert_end; j++) { //Dla kazdego wiersza wycinka wyniku aktywacji
for (int k = horiz_start; k < horiz_end; k++) { //Dla kazdej kolumny wycinka wyniku aktywacji
if (cache.A[m][k + n_W * (j + n_H * c)] > maximum) maximum = cache.A[m][k + n_W * (j + n_H * c)]; //Wybierz maksimum z wycinka
}
}
cache.OUT[m][w + n_Wout * (h + n_Hout * c)] = maximum;
}
else
cache.OUT[m][w + n_Wout * (h + n_Hout * c)] = cache.A[m][0 + n_W * (0 + n_H * c)];
}
}
}
}
}
void show_gradients(layer_param l, cache_data& cache) {
for (int m = 0; m < l.M; m++) {
for (int c = 0; c < l.n_Cprev; c++) {
std::cout << "dAprev: " << m + 1 << " Kanal: " << c + 1 << " (" << l.n_Hprev << "x" << l.n_Wprev << "x" << l.n_Cprev << ")" << "\n";
for (int h = 0; h < l.n_Hprev; h++) {
for (int w = 0; w < l.n_Wprev; w++) {
std::cout << cache.dAprev[m][w + l.n_Wprev * (h + l.n_Hprev * c)] << " ";
}
std::cout << "\n";
}
}
std::cout << "\n\n";
}
std::cout << "#### dW #### \n\n";
for (int c = 0; c < l.n_C; c++) {
for (int d = 0; d < l.n_Cprev; d++) {
std::cout << "dW: " << c + 1 << " Kanal: " << d + 1 << " (" << l.F << "x" << l.F << "x" << l.n_Cprev << ")" << "\n" << std::fixed;
for (int h = 0; h < l.F; h++) {
for (int w = 0; w < l.F; w++) {
std::cout << cache.dW[c][w + l.F * (h + l.F * d)] << " ";
}
std::cout << "\n";
}
}
std::cout << "\n\n";
}
std::cout << "#### dZ #### \n\n";
for (int m = 0; m < l.M; m++) {
for (int c = 0; c < l.n_C; c++) {
std::cout << "dZ: " << m + 1 << " Kanal: " << c + 1 << " (" << l.n_H << "x" << l.n_W << "x" << l.n_C << ")" << "\n" << std::fixed;
for (int h = 0; h < l.n_H; h++) {
for (int w = 0; w < l.n_W; w++) {
std::cout << cache.dZ[m][w + l.n_W * (h + l.n_H * c)] << " ";
}
std::cout << "\n";
}
std::cout << "\n";
}
}
std::cout << "#### dA #### \n\n";
for (int m = 0; m < l.M; m++) {
for (int c = 0; c < l.n_C; c++) {
std::cout << "dA: " << m + 1 << " Kanal: " << c + 1 << " (" << l.n_Hout << "x" << l.n_Wout << "x" << l.n_C << ")" << "\n" << std::fixed;
for (int h = 0; h < l.n_Hout; h++) {
for (int w = 0; w < l.n_Wout; w++) {
std::cout << cache.dA[m][w + l.n_Wout * (h + l.n_Hout * c)] << " ";
}
std::cout << "\n";
}
std::cout << "\n";
}
}
}
void simple_del(double**& arr, int len) {
for (int i = 0; i < len; i++) {
delete[] arr[i];
}
delete[] arr;
}
void show_results(layer_param l, cache_data& cache)
{
std::cout.precision(4);
for (int m = 0; m < l.M; m++) {
for (int c = 0; c < l.n_Cprev; c++) {
std::cout << "Wejscie: " << m + 1 << " Kanal: " << c + 1 << " (" << l.n_Hprev << "x" << l.n_Wprev << "x" << l.n_Cprev << ")" << "\n";
for (int h = 0; h < l.n_Hprev; h++) {
for (int w = 0; w < l.n_Wprev; w++) {
std::cout << cache.IN[m][w + l.n_Wprev * (h + l.n_Hprev * c)] << " ";
}
std::cout << "\n";
}
}
std::cout << "\n\n";
}
std::cout << "#### FILTRY #### \n\n";
for (int c = 0; c < l.n_C; c++) {
for (int d = 0; d < l.n_Cprev; d++) {
std::cout << "Kernel: " << c + 1 << " Kanal: " << d + 1 << " (" << l.F << "x" << l.F << "x" << l.n_Cprev << ")" << "\n" << std::fixed;
for (int h = 0; h < l.F; h++) {
for (int w = 0; w < l.F; w++) {
std::cout << cache.kernel[c][w + l.F * (h + l.F * d)] << " ";
}
std::cout << "\n";
}
}
std::cout << "\n\n";
}
std::cout << "#### WYNIKI KONWOLUCJI #### \n\n";
for (int m = 0; m < l.M; m++) {
for (int c = 0; c < l.n_C; c++) {
std::cout << "Z: " << m + 1 << " Kanal: " << c + 1 << " (" << l.n_H << "x" << l.n_W << "x" << l.n_C << ")" << "\n" << std::fixed;
for (int h = 0; h < l.n_H; h++) {
for (int w = 0; w < l.n_W; w++) {
std::cout << cache.Z[m][w + l.n_W * (h + l.n_H * c)] << " ";
}
std::cout << "\n";
}
std::cout << "\n";
}
}
std::cout << "#### WYNIKI AKTYWACJI (RELU) #### \n\n";
for (int m = 0; m < l.M; m++) {
for (int c = 0; c < l.n_C; c++) {
std::cout << "A: " << m + 1 << " Kanal: " << c + 1 << " (" << l.n_H << "x" << l.n_W << "x" << l.n_C << ")" << "\n" << std::fixed;
for (int h = 0; h < l.n_H; h++) {
for (int w = 0; w < l.n_W; w++) {
std::cout << cache.A[m][w + l.n_W * (h + l.n_H * c)] << " ";
}
std::cout << "\n";
}
std::cout << "\n";
}
}
std::cout << "#### WYNIKI MAX POOLINGU #### \n\n";
for (int m = 0; m < l.M; m++) {
for (int c = 0; c < l.n_C; c++) {
std::cout << "Wyjscie: " << m + 1 << " Kanal: " << c + 1 << " (" << l.n_Hout << "x" << l.n_Wout << "x" << l.n_C << ")" << "\n" << std::fixed;
for (int h = 0; h < l.n_Hout; h++) {
for (int w = 0; w < l.n_Wout; w++) {
std::cout << cache.OUT[m][w + l.n_Wout * (h + l.n_Hout * c)] << " ";
}
std::cout << "\n";
}
std::cout << "\n";
}
}
}
void back_prop(layer_param l, cache_data& cache) {
std::cout << "#### FILTRY PO PO PROPAGACJI WSTECZNEJ #### \n\n";
for (int c = 0; c < l.n_C; c++) {
for (int d = 0; d < l.n_Cprev; d++) {
std::cout << "Wagi: " << c + 1 << " Kanal: " << d + 1 << " (" << l.F << "x" << l.F << "x" << l.n_Cprev << ")" << "\n" << std::fixed;
for (int h = 0; h < l.F; h++) {
for (int w = 0; w < l.F; w++) {
std::cout << cache.kernel[c][w + l.F * (h + l.F * d)] - l.alpha * cache.dW[c][w + l.F * (h + l.F * d)] << " ";
}
std::cout << "\n";
}
}
std::cout << "\n\n";
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //#include "shallow.h"
#include <hip/hip_runtime.h>
#include <iostream>
#include <time.h>
#include <stdlib.h>
#define RELU(a) ((a > 0) ? a : 0)
#define KERNEL_SIZE(n_C) ((n_C * 2 > 8) ? 8 : n_C * 2)
struct layer_param {
int M; //Ilosc tablic podawanych na wejscie
int pad; //Grubosc warstwy zer na krawedziach (zero-padding)
int F; //Rozmiar 2D filtra (F x F)
int F_MP; //Rozmiar 2D filtra do max poolingu (F_MP x F_MP)
int stride; //Ilosc przeskakiwanych pikseli przy konwolucji na inkrementacje
int stride_MP; //To samo, tylko przy max poolingu
int n_Hprev; //Wysokosc tablicy wejsciowej podawanej na wejscie sieci
int n_Wprev; //Szerokosc tablicy wejsciowej podawanej na wejscie sieci
int n_Cprev; //Glebokosc tablicy wejsciowej, jednoczesnie musi to byc glebokosc filtra (F x F x C)
int n_H; //Wysokosc tablicy uzyskanej po konwolucji kernela z wejsciem
int n_W;
int n_C; //Ilosc filtrow, jednoczesnie glebokosc wyjscia warstwy
int n_Hout; //Wysokosc tablicy wyjsciowej warstwy
int n_Wout;
double alpha; //Predkosc uczenia
};
struct cache_data {
double** IN; //Tablica wejsciowa
double** Z; //Wynik splotu
double** A; //Wynik Aktywacji
double** OUT; //Poprzedni wynik po max poolingu, jednoczescie wyjscie warstwy sieci
double** kernel; //Filtr
double** dW; //Gradient kosztu wzgledem kerneli
double** dA; //Gradient kosztu wzgledem warstwy
double** dAprev; //Gradient kosztu wzgledem wyjscia warstwy n_l - 1
double** dZ; //Gradient kosztu wzgledem wyniku konwolucji
};
void set_random_IN(layer_param, double**&); //Ustawia losowe wejscie (do testowania)
void set_new_IN(double**&, double**&, layer_param l);
void show_results(layer_param, cache_data&); //Wyswietla zawartosc koncowych i posrednich wynikow w warstwie
void brief_inf(layer_param, double**); //Krotka informacja o wyjsciu sieci
void forw_prop(layer_param, cache_data&); //Najwazniejsza funkcja (konwolucja, aktywacja, maxpooling)
void simple_del(double**&, int); //Usuwanie pamieci
void update_param(layer_param&, layer_param&); //Ustawianie nowych parametrow warstwy
void prep_new_arrays(layer_param, cache_data&); //Tworzenie nowych tablic wynikowych
void prep_gradients(layer_param, cache_data&); //Tworzenie gradientow (narazie losowo, bez funkcji kosztu)
void show_gradients(layer_param, cache_data&);
void back_prop(layer_param, cache_data&);
int main() {
srand(time(NULL));
int number_of_layers = 2;
layer_param* l = new layer_param[number_of_layers];
cache_data* cache = new cache_data[number_of_layers];
int n_l = 0;
layer_param l_prev;
l[n_l].M = 1;
l[n_l].pad = 0;
l[n_l].F = 3;
l[n_l].F_MP = 2;
l[n_l].stride = 1;
l[n_l].stride_MP = 2;
l[n_l].alpha = 0.1;
int IN_size = 16; //Rzeczywisty rozmiar wejscia
int IN_depth = 1; //Rzeczywista glebokosc wejscia
l[n_l].n_Hprev = IN_size + 2 * l[n_l].pad;
l[n_l].n_Wprev = IN_size + 2 * l[n_l].pad;
l[n_l].n_Cprev = IN_depth;
l[n_l].n_H = int((l[n_l].n_Hprev - l[n_l].F) / l[n_l].stride) + 1;
l[n_l].n_W = int((l[n_l].n_Wprev - l[n_l].F) / l[n_l].stride) + 1;
l[n_l].n_C = 1;
l[n_l].n_Hout = int((l[n_l].n_H - l[n_l].F_MP) / l[n_l].stride_MP) + 1;
l[n_l].n_Wout = int((l[n_l].n_W - l[n_l].F_MP) / l[n_l].stride_MP) + 1;
for (n_l = 0; n_l < number_of_layers; n_l++) {
std::cout << "\n\n#### WARSTWA: " << n_l + 1 << "#### \n";
if (n_l == 0) set_random_IN(l[n_l], cache[n_l].IN);
else {
l_prev = l[n_l - 1];
update_param(l_prev, l[n_l]);
set_new_IN(cache[n_l].IN, cache[n_l - 1].OUT, l[n_l]);
}
prep_new_arrays(l[n_l], cache[n_l]);
forw_prop(l[n_l], cache[n_l]);
prep_gradients(l[n_l], cache[n_l]);
if (l[n_l].n_H < 25) show_results(l[n_l], cache[n_l]);
else brief_inf(l[n_l], cache[n_l].OUT);
//back_prop(l[n_l], cache[n_l]);
//show_gradients(l[n_l], cache[n_l]); //Funkcja wyswietla gradient
}
return 0;
}
void set_random_IN(layer_param l, double**& IN) {
IN = new double* [l.M];
for (int i = 0; i < l.M; i++) {
IN[i] = new double[l.n_Cprev * l.n_Hprev * l.n_Wprev];
}
for (int m = 0; m < l.M; m++) { //Dla kazdego badanego przypadku (np. pojedynczej mapy bajtowej- spektogram)
for (int h = 0; h < l.n_Hprev; h++) { //Przejdz po kazdym wierszu
for (int w = 0; w < l.n_Wprev; w++) { //Przejdz po kazdej kolumnie
for (int c = 0; c < l.n_Cprev; c++) { //Przejdz po kazdym kanale (np. dla wejscia w postaci zdjecia rgb - 3 kanaly)
if (h < l.pad || h > l.n_Hprev - l.pad - 1) IN[m][w + l.n_Wprev * (h + l.n_Hprev * c)] = 0; //Ustawianie zer dla zero paddingu
else if (w < l.pad || w > l.n_Wprev - l.pad - 1) IN[m][w + l.n_Wprev * (h + l.n_Hprev * c)] = 0;
else IN[m][w + l.n_Wprev * (h + l.n_Hprev * c)] = (rand() % 10 + 1)/10.; //W tablicy wejsciowej beda same wartosci int
}
}
}
}
}
void set_new_IN(double**& IN, double**& OUT, layer_param l) {
IN = new double* [l.M];
for (int i = 0; i < l.M; i++) {
IN[i] = new double[l.n_Cprev * l.n_Hprev * l.n_Wprev];
}
for (int m = 0; m < l.M; m++) {
for (int c = 0; c < l.n_Cprev; c++) {
for (int h = 0; h < l.n_Hprev; h++) {
for (int w = 0; w < l.n_Wprev; w++) {
IN[m][w + l.n_Wprev * (h + l.n_Hprev * c)] = OUT[m][w + l.n_Wprev * (h + l.n_Hprev * c)];
}
}
}
}
}
void update_param(layer_param& l_prev, layer_param& l) {
l.M = l_prev.M;
l.pad = l_prev.pad;
l.F = l_prev.F;
l.F_MP = l_prev.F_MP;
l.stride = l_prev.stride;
l.stride_MP = l_prev.stride_MP;
l.alpha = l_prev.alpha;
l.n_Hprev = l_prev.n_Hout;
l.n_Wprev = l_prev.n_Wout;
l.n_Cprev = l_prev.n_C;
l.n_H = int((l.n_Hprev - l.F) / l.stride) + 1;
l.n_W = int((l.n_Wprev - l.F) / l.stride) + 1;
l.n_C = KERNEL_SIZE(l_prev.n_C);
l.n_Hout = int((l.n_H - l.F_MP) / l.stride_MP) + 1;
l.n_Wout = int((l.n_W - l.F_MP) / l.stride_MP) + 1;
}
void prep_new_arrays(layer_param l, cache_data& cache) {
cache.Z = new double* [l.M];
cache.A = new double* [l.M];
cache.OUT = new double* [l.M];
cache.kernel = new double* [l.n_C];
for (int i = 0; i < l.M; i++) {
cache.Z[i] = new double[l.n_C * l.n_H * l.n_W];
cache.A[i] = new double[l.n_C * l.n_H * l.n_W];
cache.OUT[i] = new double[l.n_C * l.n_Hout * l.n_Wout];
}
for (int i = 0; i < l.n_C; i++) {
cache.kernel[i] = new double[l.n_Cprev * l.F * l.F];
}
for (int c = 0; c < l.n_C; c++) {
for (int h = 0; h < l.F; h++) {
for (int w = 0; w < l.F; w++) {
for (int d = 0; d < l.n_Cprev; d++) {
cache.kernel[c][w + l.F * (h + l.F * d)] = (rand()%10000 - 5000) * 0.0001; //Ustawianie losowych wag filtra
}
}
}
}
}
void prep_gradients(layer_param l, cache_data& cache) {
cache.dZ = new double* [l.M];
cache.dA = new double* [l.M];
cache.dAprev = new double* [l.M];
cache.dW = new double* [l.n_C];
for (int i = 0; i < l.M; i++) {
cache.dZ[i] = new double[l.n_C * l.n_H * l.n_W];
}
for (int i = 0; i < l.M; i++) {
cache.dA[i] = new double[l.n_C * l.n_Hout * l.n_Wout];
}
for (int i = 0; i < l.M; i++) {
cache.dAprev[i] = new double[l.n_Cprev * l.n_Hprev * l.n_Wprev];
}
for (int i = 0; i < l.n_C; i++) {
cache.dW[i] = new double[l.n_Cprev * l.F * l.F];
}
for (int m = 0; m < l.M; m++) {
for (int c = 0; c < l.n_C; c++) {
for (int h = 0; h < l.n_Hout; h++) {
for (int w = 0; w < l.n_Wout; w++) {
cache.dA[m][w + l.n_Wout * (h + l.n_Hout * c)] = (rand()%10000 - 5000) * 0.0001;
}
}
}
}
for (int m = 0; m < l.M; m++) {
for (int c = 0; c < l.n_Cprev; c++) {
for (int h = 0; h < l.n_Hprev; h++) {
for (int w = 0; w < l.n_Wprev; w++) {
cache.dAprev[m][w + l.n_Wprev * (h + l.n_Hprev * c)] = 0;
}
}
}
}
for (int c = 0; c < l.n_C; c++) {
for (int h = 0; h < l.F; h++) {
for (int w = 0; w < l.F; w++) {
for (int d = 0; d < l.n_Cprev; d++) {
cache.dW[c][w + l.F * (h + l.F * d)] = 0;
}
}
}
}
double maximum;
int vert_start, vert_end;
int horiz_start, horiz_end;
for (int m = 0; m < l.M; m++) { //Dla kazdego przypadku
for (int h = 0; h < l.n_Hout; h++) { //Dla kazdego wiersza wyjscia (wyniku max poolingu)
for (int w = 0; w < l.n_Wout; w++) { // Dla kazdej kolumny wyjscia
for (int c = 0; c < l.n_C; c++) { //Dla kazdego kanalu wyjscia
vert_start = h * l.stride_MP;
vert_end = vert_start + l.F_MP;
horiz_start = w * l.stride_MP;
horiz_end = horiz_start + l.F_MP;
maximum = 0;
for (int j = vert_start; j < vert_end; j++) { //Dla kazdego wiersza wycinka wyniku aktywacji
for (int k = horiz_start; k < horiz_end; k++) { //Dla kazdej kolumny wycinka wyniku aktywacji
if (cache.A[m][k + l.n_W * (j + l.n_H * c)] > maximum) maximum = cache.A[m][k + l.n_W * (j + l.n_H * c)];
}
}
for (int j = vert_start; j < vert_end; j++) {
for (int k = horiz_start; k < horiz_end; k++) {
if (cache.A[m][k + l.n_W * (j + l.n_H * c)] != maximum || maximum == 0) cache.dZ[m][k + l.n_W * (j + l.n_H * c)] = 0;
else cache.dZ[m][k + l.n_W * (j + l.n_H * c)] = cache.dA[m][w + l.n_Wout * (h + l.n_Hout * c)];
}
}
}
}
}
}
for (int m = 0; m < l.M; m++) {
for (int h = 0; h < l.n_H; h++) {
for (int w = 0; w < l.n_W; w++) {
for (int c = 0; c < l.n_C; c++) {
vert_start = h;
vert_end = vert_start + l.F;
horiz_start = w;
horiz_end = horiz_start + l.F;
for (int d = 0; d < l.n_Cprev; d++) {
for (int j = vert_start; j < vert_end; j++) {
for (int k = horiz_start; k < horiz_end; k++) {
if (cache.dZ[m][w + l.n_W * (h + l.n_H * c)] < 0) cache.dZ[m][w + l.n_W * (h + l.n_H * c)] = 0;
cache.dAprev[m][j + l.n_Wprev * (k + l.n_Hprev * d)] += cache.kernel[c][(k - horiz_start) + l.F * ((j - vert_start) + l.F * d)] *
cache.dZ[m][w + l.n_W * (h + l.n_H * c)];
cache.dW[c][(k - horiz_start) + l.F * ((j - vert_start) + l.F * d)] += cache.IN[m][j + l.n_Wprev * (k + l.n_Hprev * d)] *
cache.dZ[m][w + l.n_W * (h + l.n_H * c)];
}
}
}
}
}
}
}
}
void brief_inf(layer_param l, double** OUT) {
for (int m = 0; m < l.M; m++)
std::cout << "Wyjscie: " << m + 1 << " Kanaly: " << l.n_C << " (" << l.n_Hout << "x" << l.n_Wout << "x" << l.n_C << ")" << "\n" << std::fixed;
}
void forw_prop(layer_param l, cache_data& cache) {
int M = l.M;
int pad = l.pad;
int F = l.F;
int F_MP = l.F_MP;
int stride = l.stride;
int stride_MP = l.stride_MP;
int n_Hprev = l.n_Hprev;
int n_Wprev = l.n_Wprev;
int n_Cprev = l.n_Cprev;
int n_H = l.n_H;
int n_W = l.n_W;
int n_C = l.n_C;
int n_Hout = l.n_Hout;
int n_Wout = l.n_Wout;
int vert_start = 0;
int vert_end = 0;
int horiz_start = 0;
int horiz_end = 0;
for (int m = 0; m < M; m++) { //Dla kazdego przypadku
for (int h = 0; h < n_H; h++) { //Dla kazdego wiersza
for (int w = 0; w < n_W; w++) { //Dla kazdej kolumny
for (int c = 0; c < n_C; c++) { //Dla kazdego kanalu (kanalow bedzie tyle, ile chcemy kerneli)
vert_start = h * stride; //Poczatek wycinka w pionie
vert_end = vert_start + F; //Koniec wycinka w pionie
horiz_start = w * stride; //Poczatek wycika w poziomie
horiz_end = horiz_start + F; //Koniec wycinka w poziomie
cache.Z[m][w + n_W * (h + n_H * c)] = 0;
for (int d = 0; d < n_Cprev; d++) { //Dla kazdego kanalu w tablicy wejsciowej
for (int j = vert_start; j < vert_end; j++) { //Dla wybranych wierszy
for (int k = horiz_start; k < horiz_end; k++) { //Dla wybranych kolumn
cache.Z[m][w + n_W * (h + n_H * c)] += cache.kernel[c][(k - horiz_start) + F * ((j - vert_start) + F * d)] *
cache.IN[m][k + n_Wprev * (j + n_Hprev * d)];
//Pomnoz wartosc/piksel wycinka przez wage kernela i dodaj do wyniku konwolucji
}
}
}
cache.A[m][w + n_W * (h + n_H * c)] = RELU(cache.Z[m][w + n_W * (h + n_H * c)]); //Aktywowanie danej wartosci/neuronu
}
}
}
}
double maximum = 0;
for (int m = 0; m < M; m++) { //Dla kazdego przypadku
for (int h = 0; h < n_Hout; h++) { //Dla kazdego wiersza wyjscia (wyniku max poolingu)
for (int w = 0; w < n_Wout; w++) { // Dla kazdej kolumny wyjscia
for (int c = 0; c < n_C; c++) { //Dla kazdego kanalu wyjscia
if (n_Hout > 1) {
vert_start = h * stride_MP;
vert_end = vert_start + F_MP;
horiz_start = w * stride_MP;
horiz_end = horiz_start + F_MP;
maximum = 0;
for (int j = vert_start; j < vert_end; j++) { //Dla kazdego wiersza wycinka wyniku aktywacji
for (int k = horiz_start; k < horiz_end; k++) { //Dla kazdej kolumny wycinka wyniku aktywacji
if (cache.A[m][k + n_W * (j + n_H * c)] > maximum) maximum = cache.A[m][k + n_W * (j + n_H * c)]; //Wybierz maksimum z wycinka
}
}
cache.OUT[m][w + n_Wout * (h + n_Hout * c)] = maximum;
}
else
cache.OUT[m][w + n_Wout * (h + n_Hout * c)] = cache.A[m][0 + n_W * (0 + n_H * c)];
}
}
}
}
}
void show_gradients(layer_param l, cache_data& cache) {
for (int m = 0; m < l.M; m++) {
for (int c = 0; c < l.n_Cprev; c++) {
std::cout << "dAprev: " << m + 1 << " Kanal: " << c + 1 << " (" << l.n_Hprev << "x" << l.n_Wprev << "x" << l.n_Cprev << ")" << "\n";
for (int h = 0; h < l.n_Hprev; h++) {
for (int w = 0; w < l.n_Wprev; w++) {
std::cout << cache.dAprev[m][w + l.n_Wprev * (h + l.n_Hprev * c)] << " ";
}
std::cout << "\n";
}
}
std::cout << "\n\n";
}
std::cout << "#### dW #### \n\n";
for (int c = 0; c < l.n_C; c++) {
for (int d = 0; d < l.n_Cprev; d++) {
std::cout << "dW: " << c + 1 << " Kanal: " << d + 1 << " (" << l.F << "x" << l.F << "x" << l.n_Cprev << ")" << "\n" << std::fixed;
for (int h = 0; h < l.F; h++) {
for (int w = 0; w < l.F; w++) {
std::cout << cache.dW[c][w + l.F * (h + l.F * d)] << " ";
}
std::cout << "\n";
}
}
std::cout << "\n\n";
}
std::cout << "#### dZ #### \n\n";
for (int m = 0; m < l.M; m++) {
for (int c = 0; c < l.n_C; c++) {
std::cout << "dZ: " << m + 1 << " Kanal: " << c + 1 << " (" << l.n_H << "x" << l.n_W << "x" << l.n_C << ")" << "\n" << std::fixed;
for (int h = 0; h < l.n_H; h++) {
for (int w = 0; w < l.n_W; w++) {
std::cout << cache.dZ[m][w + l.n_W * (h + l.n_H * c)] << " ";
}
std::cout << "\n";
}
std::cout << "\n";
}
}
std::cout << "#### dA #### \n\n";
for (int m = 0; m < l.M; m++) {
for (int c = 0; c < l.n_C; c++) {
std::cout << "dA: " << m + 1 << " Kanal: " << c + 1 << " (" << l.n_Hout << "x" << l.n_Wout << "x" << l.n_C << ")" << "\n" << std::fixed;
for (int h = 0; h < l.n_Hout; h++) {
for (int w = 0; w < l.n_Wout; w++) {
std::cout << cache.dA[m][w + l.n_Wout * (h + l.n_Hout * c)] << " ";
}
std::cout << "\n";
}
std::cout << "\n";
}
}
}
void simple_del(double**& arr, int len) {
for (int i = 0; i < len; i++) {
delete[] arr[i];
}
delete[] arr;
}
void show_results(layer_param l, cache_data& cache)
{
std::cout.precision(4);
for (int m = 0; m < l.M; m++) {
for (int c = 0; c < l.n_Cprev; c++) {
std::cout << "Wejscie: " << m + 1 << " Kanal: " << c + 1 << " (" << l.n_Hprev << "x" << l.n_Wprev << "x" << l.n_Cprev << ")" << "\n";
for (int h = 0; h < l.n_Hprev; h++) {
for (int w = 0; w < l.n_Wprev; w++) {
std::cout << cache.IN[m][w + l.n_Wprev * (h + l.n_Hprev * c)] << " ";
}
std::cout << "\n";
}
}
std::cout << "\n\n";
}
std::cout << "#### FILTRY #### \n\n";
for (int c = 0; c < l.n_C; c++) {
for (int d = 0; d < l.n_Cprev; d++) {
std::cout << "Kernel: " << c + 1 << " Kanal: " << d + 1 << " (" << l.F << "x" << l.F << "x" << l.n_Cprev << ")" << "\n" << std::fixed;
for (int h = 0; h < l.F; h++) {
for (int w = 0; w < l.F; w++) {
std::cout << cache.kernel[c][w + l.F * (h + l.F * d)] << " ";
}
std::cout << "\n";
}
}
std::cout << "\n\n";
}
std::cout << "#### WYNIKI KONWOLUCJI #### \n\n";
for (int m = 0; m < l.M; m++) {
for (int c = 0; c < l.n_C; c++) {
std::cout << "Z: " << m + 1 << " Kanal: " << c + 1 << " (" << l.n_H << "x" << l.n_W << "x" << l.n_C << ")" << "\n" << std::fixed;
for (int h = 0; h < l.n_H; h++) {
for (int w = 0; w < l.n_W; w++) {
std::cout << cache.Z[m][w + l.n_W * (h + l.n_H * c)] << " ";
}
std::cout << "\n";
}
std::cout << "\n";
}
}
std::cout << "#### WYNIKI AKTYWACJI (RELU) #### \n\n";
for (int m = 0; m < l.M; m++) {
for (int c = 0; c < l.n_C; c++) {
std::cout << "A: " << m + 1 << " Kanal: " << c + 1 << " (" << l.n_H << "x" << l.n_W << "x" << l.n_C << ")" << "\n" << std::fixed;
for (int h = 0; h < l.n_H; h++) {
for (int w = 0; w < l.n_W; w++) {
std::cout << cache.A[m][w + l.n_W * (h + l.n_H * c)] << " ";
}
std::cout << "\n";
}
std::cout << "\n";
}
}
std::cout << "#### WYNIKI MAX POOLINGU #### \n\n";
for (int m = 0; m < l.M; m++) {
for (int c = 0; c < l.n_C; c++) {
std::cout << "Wyjscie: " << m + 1 << " Kanal: " << c + 1 << " (" << l.n_Hout << "x" << l.n_Wout << "x" << l.n_C << ")" << "\n" << std::fixed;
for (int h = 0; h < l.n_Hout; h++) {
for (int w = 0; w < l.n_Wout; w++) {
std::cout << cache.OUT[m][w + l.n_Wout * (h + l.n_Hout * c)] << " ";
}
std::cout << "\n";
}
std::cout << "\n";
}
}
}
void back_prop(layer_param l, cache_data& cache) {
std::cout << "#### FILTRY PO PO PROPAGACJI WSTECZNEJ #### \n\n";
for (int c = 0; c < l.n_C; c++) {
for (int d = 0; d < l.n_Cprev; d++) {
std::cout << "Wagi: " << c + 1 << " Kanal: " << d + 1 << " (" << l.F << "x" << l.F << "x" << l.n_Cprev << ")" << "\n" << std::fixed;
for (int h = 0; h < l.F; h++) {
for (int w = 0; w < l.F; w++) {
std::cout << cache.kernel[c][w + l.F * (h + l.F * d)] - l.alpha * cache.dW[c][w + l.F * (h + l.F * d)] << " ";
}
std::cout << "\n";
}
}
std::cout << "\n\n";
}
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#define MIN(x, y) (((x) < (y)) ? (x) : (y))
__global__ void
matmult_kernel1(int m, int n, int k, double *A, double *B, double *C){
// set C to zeros
for (int i=0;i<m;i++){
for (int p=0;p<n;p++){
C[i*n+p]=0; //C[i][p]
}
}
// do matmult with mkn loop order
for (int i=0;i<m;i++) {
for (int j=0;j<k;j++){
for (int p=0;p<n;p++) {
C[i*n+p] += A[i*k+j] * B[j*n+p];
}
}
}
}
__global__ void
matmult_kernel2(int m, int n, int k, double *A, double *B, double *C){
int j = blockIdx.x*blockDim.x+threadIdx.x; //looping through n
int i = blockIdx.y*blockDim.y+threadIdx.y; //looping through m
double tmp;
if((j<n)&&(i<m)){
for(int p=0; p<k; p++){
//read row of A and col of B
//row of A is A[mit*k+kit]
//col of B is B[kit*n+nit]
tmp += A[i*k+p] * B[p*n+j];
}
//C is C[mit*n+nit]
C[i*n+j] = tmp;
}
}
__global__ void
matmult_kernel3(int m, int n, int k, double *A, double *B, double *C){
//compute C(i,j) and C(i,j+1)
int j = 2*(blockIdx.x*blockDim.x+threadIdx.x); //looping through n (only half as many threads/blocks)
int i = blockIdx.y*blockDim.y+threadIdx.y; //looping through m
double tmp1 = 0.0;
double tmp2 = 0.0;
if((j<n)&&(i<m)){
//additional j to compute (here, either 1 or 0)
int j_add = MIN(1,n-1-j);
for(int p=0; p<k; p++){
//row of A and col of B
tmp1 += A[i*k+p] * B[p*n+j];
if(j_add == 1)
tmp2 += A[i*k+p] * B[p*n+j+1];
}
C[i*n+j] = tmp1;
if(j_add == 1)
C[i*n+j+1] = tmp2;
}
}
__global__ void
matmult_kernel4(int m, int n, int k, double *A, double *B, double *C, int s){
//compute C(i,j), C(i,j+1), ... C(i,j+s)
int j = s*(blockIdx.x*blockDim.x+threadIdx.x); //looping through n (only 1/s as many threads/blocks)
int i = blockIdx.y*blockDim.y+threadIdx.y; //looping through m
double tmp1 = 0.0;
double tmp2 = 0.0;
double tmp3 = 0.0;
double tmp4 = 0.0;
double tmp5 = 0.0;
double tmp6 = 0.0;
double tmp7 = 0.0;
double tmp8 = 0.0;
double tmp9 = 0.0;
double tmp10 = 0.0;
double tmp11 = 0.0;
double tmp12 = 0.0;
double tmp13 = 0.0;
double tmp14 = 0.0;
double tmp15 = 0.0;
double tmp16 = 0.0;
if((j<n)&&(i<m)){
//additional j to compute (here, from 0 to s-1)
int j_add = MIN(s-1,n-1-j);
for(int p=0; p<k; p++){
//row of A and col of B
tmp1 += A[i*k+p] * B[p*n+j+0];
if(j_add > 0)
tmp2 += A[i*k+p] * B[p*n+j+1];
if(j_add > 1)
tmp3 += A[i*k+p] * B[p*n+j+2];
if(j_add > 2)
tmp4 += A[i*k+p] * B[p*n+j+3];
if(j_add > 3)
tmp5 += A[i*k+p] * B[p*n+j+4];
if(j_add > 4)
tmp6 += A[i*k+p] * B[p*n+j+5];
if(j_add > 5)
tmp7 += A[i*k+p] * B[p*n+j+6];
if(j_add > 6)
tmp8 += A[i*k+p] * B[p*n+j+7];
if(j_add > 7)
tmp9 += A[i*k+p] * B[p*n+j+8];
if(j_add > 8)
tmp10 += A[i*k+p] * B[p*n+j+9];
if(j_add > 9)
tmp11 += A[i*k+p] * B[p*n+j+10];
if(j_add > 10)
tmp12 += A[i*k+p] * B[p*n+j+11];
if(j_add > 11)
tmp13 += A[i*k+p] * B[p*n+j+12];
if(j_add > 12)
tmp14 += A[i*k+p] * B[p*n+j+13];
if(j_add > 13)
tmp15 += A[i*k+p] * B[p*n+j+14];
if(j_add > 14)
tmp16 += A[i*k+p] * B[p*n+j+15];
}
C[i*n+j] = tmp1;
if(j_add > 0)
C[i*n+j+1] = tmp2;
if(j_add > 1)
C[i*n+j+2] = tmp3;
if(j_add > 2)
C[i*n+j+3] = tmp4;
if(j_add > 3)
C[i*n+j+4] = tmp5;
if(j_add > 4)
C[i*n+j+5] = tmp6;
if(j_add > 5)
C[i*n+j+6] = tmp7;
if(j_add > 6)
C[i*n+j+7] = tmp8;
if(j_add > 7)
C[i*n+j+8] = tmp9;
if(j_add > 8)
C[i*n+j+9] = tmp10;
if(j_add > 9)
C[i*n+j+10] = tmp11;
if(j_add > 10)
C[i*n+j+11] = tmp12;
if(j_add > 11)
C[i*n+j+12] = tmp13;
if(j_add > 12)
C[i*n+j+13] = tmp14;
if(j_add > 13)
C[i*n+j+14] = tmp15;
if(j_add > 14)
C[i*n+j+15] = tmp16;
}
}
/*
BEGIN GPU 5
##############################################################################
*/
#define BLOCK_SIZE 16
typedef struct {
int width;
int height;
int stride;
double* elements;
} Matrix;
// Get a matrix element
__device__ double GetElement(const Matrix A, int row, int col)
{
return A.elements[row * A.stride + col];
}
// Set a matrix element
__device__ void SetElement(Matrix A, int row, int col,
double value)
{
A.elements[row * A.stride + col] = value;
}
// Get the BLOCK_SIZExBLOCK_SIZE sub-matrix Asub of A that is
// located col sub-matrices to the right and row sub-matrices down
// from the upper-left corner of A
__device__ Matrix GetSubMatrix(Matrix A, int row, int col)
{
Matrix Asub;
Asub.width = BLOCK_SIZE;
Asub.height = BLOCK_SIZE;
Asub.stride = A.stride;
Asub.elements = &A.elements[A.stride * BLOCK_SIZE * row + BLOCK_SIZE * col];
return Asub;
}
// Matrix multiplication kernel called by MatMul()
__global__ void gpu5_kernel(const Matrix A, const Matrix B, Matrix C)
{
// Block row and column
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
// Each thread block computes one sub-matrix Csub of C
Matrix Csub = GetSubMatrix(C, blockRow, blockCol);
// Each thread computes one element of Csub
// by accumulating results into Cvalue
double Cvalue = 0;
// Thread row and column within Csub
int row = threadIdx.y;
int col = threadIdx.x;
// Loop over all the sub-matrices of A and B that are
// required to compute Csub
// Multiply each pair of sub-matrices together
// and accumulate the results
for (int m = 0; m < (A.width / BLOCK_SIZE); ++m) {
// Get sub-matrix Asub of A
Matrix Asub = GetSubMatrix(A, blockRow, m);
// Get sub-matrix Bsub of B
Matrix Bsub = GetSubMatrix(B, m, blockCol);
// Shared memory used to store Asub and Bsub respectively
__shared__ double As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ double Bs[BLOCK_SIZE][BLOCK_SIZE];
// Load Asub and Bsub from device memory to shared memory
// Each thread loads one element of each sub-matrix
As[row][col] = GetElement(Asub, row, col);
Bs[row][col] = GetElement(Bsub, row, col);
// Synchronize to make sure the sub-matrices are loaded
// before starting the computation
__syncthreads();
// Multiply Asub and Bsub together
for (int e = 0; e < BLOCK_SIZE; ++e)
Cvalue += As[row][e] * Bs[e][col];
// Synchronize to make sure that the preceding
// computation is done before loading two new
// sub-matrices of A and B in the next iteration
__syncthreads();
}
// Write Csub to device memory
// Each thread writes one element
SetElement(Csub, row, col, Cvalue);
} | .file "tmpxft_00152ae4_00000000-6_matmult_kernels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10GetElement6Matrixii
.type _Z10GetElement6Matrixii, @function
_Z10GetElement6Matrixii:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z10GetElement6Matrixii, .-_Z10GetElement6Matrixii
.globl _Z10SetElement6Matrixiid
.type _Z10SetElement6Matrixiid, @function
_Z10SetElement6Matrixiid:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z10SetElement6Matrixiid, .-_Z10SetElement6Matrixiid
.globl _Z12GetSubMatrix6Matrixii
.type _Z12GetSubMatrix6Matrixii, @function
_Z12GetSubMatrix6Matrixii:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z12GetSubMatrix6Matrixii, .-_Z12GetSubMatrix6Matrixii
.globl _Z42__device_stub__Z15matmult_kernel1iiiPdS_S_iiiPdS_S_
.type _Z42__device_stub__Z15matmult_kernel1iiiPdS_S_iiiPdS_S_, @function
_Z42__device_stub__Z15matmult_kernel1iiiPdS_S_iiiPdS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15matmult_kernel1iiiPdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z42__device_stub__Z15matmult_kernel1iiiPdS_S_iiiPdS_S_, .-_Z42__device_stub__Z15matmult_kernel1iiiPdS_S_iiiPdS_S_
.globl _Z15matmult_kernel1iiiPdS_S_
.type _Z15matmult_kernel1iiiPdS_S_, @function
_Z15matmult_kernel1iiiPdS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z15matmult_kernel1iiiPdS_S_iiiPdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z15matmult_kernel1iiiPdS_S_, .-_Z15matmult_kernel1iiiPdS_S_
.globl _Z42__device_stub__Z15matmult_kernel2iiiPdS_S_iiiPdS_S_
.type _Z42__device_stub__Z15matmult_kernel2iiiPdS_S_iiiPdS_S_, @function
_Z42__device_stub__Z15matmult_kernel2iiiPdS_S_iiiPdS_S_:
.LFB2086:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15matmult_kernel2iiiPdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z42__device_stub__Z15matmult_kernel2iiiPdS_S_iiiPdS_S_, .-_Z42__device_stub__Z15matmult_kernel2iiiPdS_S_iiiPdS_S_
.globl _Z15matmult_kernel2iiiPdS_S_
.type _Z15matmult_kernel2iiiPdS_S_, @function
_Z15matmult_kernel2iiiPdS_S_:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z15matmult_kernel2iiiPdS_S_iiiPdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z15matmult_kernel2iiiPdS_S_, .-_Z15matmult_kernel2iiiPdS_S_
.globl _Z42__device_stub__Z15matmult_kernel3iiiPdS_S_iiiPdS_S_
.type _Z42__device_stub__Z15matmult_kernel3iiiPdS_S_iiiPdS_S_, @function
_Z42__device_stub__Z15matmult_kernel3iiiPdS_S_iiiPdS_S_:
.LFB2088:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15matmult_kernel3iiiPdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z42__device_stub__Z15matmult_kernel3iiiPdS_S_iiiPdS_S_, .-_Z42__device_stub__Z15matmult_kernel3iiiPdS_S_iiiPdS_S_
.globl _Z15matmult_kernel3iiiPdS_S_
.type _Z15matmult_kernel3iiiPdS_S_, @function
_Z15matmult_kernel3iiiPdS_S_:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z15matmult_kernel3iiiPdS_S_iiiPdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z15matmult_kernel3iiiPdS_S_, .-_Z15matmult_kernel3iiiPdS_S_
.globl _Z43__device_stub__Z15matmult_kernel4iiiPdS_S_iiiiPdS_S_i
.type _Z43__device_stub__Z15matmult_kernel4iiiPdS_S_iiiiPdS_S_i, @function
_Z43__device_stub__Z15matmult_kernel4iiiPdS_S_iiiiPdS_S_i:
.LFB2090:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L37
.L33:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15matmult_kernel4iiiPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L33
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z43__device_stub__Z15matmult_kernel4iiiPdS_S_iiiiPdS_S_i, .-_Z43__device_stub__Z15matmult_kernel4iiiPdS_S_iiiiPdS_S_i
.globl _Z15matmult_kernel4iiiPdS_S_i
.type _Z15matmult_kernel4iiiPdS_S_i, @function
_Z15matmult_kernel4iiiPdS_S_i:
.LFB2091:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z43__device_stub__Z15matmult_kernel4iiiPdS_S_iiiiPdS_S_i
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z15matmult_kernel4iiiPdS_S_i, .-_Z15matmult_kernel4iiiPdS_S_i
.globl _Z40__device_stub__Z11gpu5_kernel6MatrixS_S_RK6MatrixS1_RS_
.type _Z40__device_stub__Z11gpu5_kernel6MatrixS_S_RK6MatrixS1_RS_, @function
_Z40__device_stub__Z11gpu5_kernel6MatrixS_S_RK6MatrixS1_RS_:
.LFB2092:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq %rdi, 64(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 80(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L45
.L41:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L46
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 120
pushq 8(%rsp)
.cfi_def_cfa_offset 128
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z11gpu5_kernel6MatrixS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L41
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2092:
.size _Z40__device_stub__Z11gpu5_kernel6MatrixS_S_RK6MatrixS1_RS_, .-_Z40__device_stub__Z11gpu5_kernel6MatrixS_S_RK6MatrixS1_RS_
.globl _Z11gpu5_kernel6MatrixS_S_
.type _Z11gpu5_kernel6MatrixS_S_, @function
_Z11gpu5_kernel6MatrixS_S_:
.LFB2093:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq 64(%rsp), %rdx
leaq 40(%rsp), %rsi
leaq 16(%rsp), %rdi
call _Z40__device_stub__Z11gpu5_kernel6MatrixS_S_RK6MatrixS1_RS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _Z11gpu5_kernel6MatrixS_S_, .-_Z11gpu5_kernel6MatrixS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11gpu5_kernel6MatrixS_S_"
.LC1:
.string "_Z15matmult_kernel4iiiPdS_S_i"
.LC2:
.string "_Z15matmult_kernel3iiiPdS_S_"
.LC3:
.string "_Z15matmult_kernel2iiiPdS_S_"
.LC4:
.string "_Z15matmult_kernel1iiiPdS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2095:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11gpu5_kernel6MatrixS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z15matmult_kernel4iiiPdS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z15matmult_kernel3iiiPdS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z15matmult_kernel2iiiPdS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z15matmult_kernel1iiiPdS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2095:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#define MIN(x, y) (((x) < (y)) ? (x) : (y))
__global__ void
matmult_kernel1(int m, int n, int k, double *A, double *B, double *C){
// set C to zeros
for (int i=0;i<m;i++){
for (int p=0;p<n;p++){
C[i*n+p]=0; //C[i][p]
}
}
// do matmult with mkn loop order
for (int i=0;i<m;i++) {
for (int j=0;j<k;j++){
for (int p=0;p<n;p++) {
C[i*n+p] += A[i*k+j] * B[j*n+p];
}
}
}
}
__global__ void
matmult_kernel2(int m, int n, int k, double *A, double *B, double *C){
int j = blockIdx.x*blockDim.x+threadIdx.x; //looping through n
int i = blockIdx.y*blockDim.y+threadIdx.y; //looping through m
double tmp;
if((j<n)&&(i<m)){
for(int p=0; p<k; p++){
//read row of A and col of B
//row of A is A[mit*k+kit]
//col of B is B[kit*n+nit]
tmp += A[i*k+p] * B[p*n+j];
}
//C is C[mit*n+nit]
C[i*n+j] = tmp;
}
}
__global__ void
matmult_kernel3(int m, int n, int k, double *A, double *B, double *C){
//compute C(i,j) and C(i,j+1)
int j = 2*(blockIdx.x*blockDim.x+threadIdx.x); //looping through n (only half as many threads/blocks)
int i = blockIdx.y*blockDim.y+threadIdx.y; //looping through m
double tmp1 = 0.0;
double tmp2 = 0.0;
if((j<n)&&(i<m)){
//additional j to compute (here, either 1 or 0)
int j_add = MIN(1,n-1-j);
for(int p=0; p<k; p++){
//row of A and col of B
tmp1 += A[i*k+p] * B[p*n+j];
if(j_add == 1)
tmp2 += A[i*k+p] * B[p*n+j+1];
}
C[i*n+j] = tmp1;
if(j_add == 1)
C[i*n+j+1] = tmp2;
}
}
__global__ void
matmult_kernel4(int m, int n, int k, double *A, double *B, double *C, int s){
//compute C(i,j), C(i,j+1), ... C(i,j+s)
int j = s*(blockIdx.x*blockDim.x+threadIdx.x); //looping through n (only 1/s as many threads/blocks)
int i = blockIdx.y*blockDim.y+threadIdx.y; //looping through m
double tmp1 = 0.0;
double tmp2 = 0.0;
double tmp3 = 0.0;
double tmp4 = 0.0;
double tmp5 = 0.0;
double tmp6 = 0.0;
double tmp7 = 0.0;
double tmp8 = 0.0;
double tmp9 = 0.0;
double tmp10 = 0.0;
double tmp11 = 0.0;
double tmp12 = 0.0;
double tmp13 = 0.0;
double tmp14 = 0.0;
double tmp15 = 0.0;
double tmp16 = 0.0;
if((j<n)&&(i<m)){
//additional j to compute (here, from 0 to s-1)
int j_add = MIN(s-1,n-1-j);
for(int p=0; p<k; p++){
//row of A and col of B
tmp1 += A[i*k+p] * B[p*n+j+0];
if(j_add > 0)
tmp2 += A[i*k+p] * B[p*n+j+1];
if(j_add > 1)
tmp3 += A[i*k+p] * B[p*n+j+2];
if(j_add > 2)
tmp4 += A[i*k+p] * B[p*n+j+3];
if(j_add > 3)
tmp5 += A[i*k+p] * B[p*n+j+4];
if(j_add > 4)
tmp6 += A[i*k+p] * B[p*n+j+5];
if(j_add > 5)
tmp7 += A[i*k+p] * B[p*n+j+6];
if(j_add > 6)
tmp8 += A[i*k+p] * B[p*n+j+7];
if(j_add > 7)
tmp9 += A[i*k+p] * B[p*n+j+8];
if(j_add > 8)
tmp10 += A[i*k+p] * B[p*n+j+9];
if(j_add > 9)
tmp11 += A[i*k+p] * B[p*n+j+10];
if(j_add > 10)
tmp12 += A[i*k+p] * B[p*n+j+11];
if(j_add > 11)
tmp13 += A[i*k+p] * B[p*n+j+12];
if(j_add > 12)
tmp14 += A[i*k+p] * B[p*n+j+13];
if(j_add > 13)
tmp15 += A[i*k+p] * B[p*n+j+14];
if(j_add > 14)
tmp16 += A[i*k+p] * B[p*n+j+15];
}
C[i*n+j] = tmp1;
if(j_add > 0)
C[i*n+j+1] = tmp2;
if(j_add > 1)
C[i*n+j+2] = tmp3;
if(j_add > 2)
C[i*n+j+3] = tmp4;
if(j_add > 3)
C[i*n+j+4] = tmp5;
if(j_add > 4)
C[i*n+j+5] = tmp6;
if(j_add > 5)
C[i*n+j+6] = tmp7;
if(j_add > 6)
C[i*n+j+7] = tmp8;
if(j_add > 7)
C[i*n+j+8] = tmp9;
if(j_add > 8)
C[i*n+j+9] = tmp10;
if(j_add > 9)
C[i*n+j+10] = tmp11;
if(j_add > 10)
C[i*n+j+11] = tmp12;
if(j_add > 11)
C[i*n+j+12] = tmp13;
if(j_add > 12)
C[i*n+j+13] = tmp14;
if(j_add > 13)
C[i*n+j+14] = tmp15;
if(j_add > 14)
C[i*n+j+15] = tmp16;
}
}
/*
BEGIN GPU 5
##############################################################################
*/
#define BLOCK_SIZE 16
typedef struct {
int width;
int height;
int stride;
double* elements;
} Matrix;
// Get a matrix element
__device__ double GetElement(const Matrix A, int row, int col)
{
return A.elements[row * A.stride + col];
}
// Set a matrix element
__device__ void SetElement(Matrix A, int row, int col,
double value)
{
A.elements[row * A.stride + col] = value;
}
// Get the BLOCK_SIZExBLOCK_SIZE sub-matrix Asub of A that is
// located col sub-matrices to the right and row sub-matrices down
// from the upper-left corner of A
__device__ Matrix GetSubMatrix(Matrix A, int row, int col)
{
Matrix Asub;
Asub.width = BLOCK_SIZE;
Asub.height = BLOCK_SIZE;
Asub.stride = A.stride;
Asub.elements = &A.elements[A.stride * BLOCK_SIZE * row + BLOCK_SIZE * col];
return Asub;
}
// Matrix multiplication kernel called by MatMul()
__global__ void gpu5_kernel(const Matrix A, const Matrix B, Matrix C)
{
// Block row and column
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
// Each thread block computes one sub-matrix Csub of C
Matrix Csub = GetSubMatrix(C, blockRow, blockCol);
// Each thread computes one element of Csub
// by accumulating results into Cvalue
double Cvalue = 0;
// Thread row and column within Csub
int row = threadIdx.y;
int col = threadIdx.x;
// Loop over all the sub-matrices of A and B that are
// required to compute Csub
// Multiply each pair of sub-matrices together
// and accumulate the results
for (int m = 0; m < (A.width / BLOCK_SIZE); ++m) {
// Get sub-matrix Asub of A
Matrix Asub = GetSubMatrix(A, blockRow, m);
// Get sub-matrix Bsub of B
Matrix Bsub = GetSubMatrix(B, m, blockCol);
// Shared memory used to store Asub and Bsub respectively
__shared__ double As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ double Bs[BLOCK_SIZE][BLOCK_SIZE];
// Load Asub and Bsub from device memory to shared memory
// Each thread loads one element of each sub-matrix
As[row][col] = GetElement(Asub, row, col);
Bs[row][col] = GetElement(Bsub, row, col);
// Synchronize to make sure the sub-matrices are loaded
// before starting the computation
__syncthreads();
// Multiply Asub and Bsub together
for (int e = 0; e < BLOCK_SIZE; ++e)
Cvalue += As[row][e] * Bs[e][col];
// Synchronize to make sure that the preceding
// computation is done before loading two new
// sub-matrices of A and B in the next iteration
__syncthreads();
}
// Write Csub to device memory
// Each thread writes one element
SetElement(Csub, row, col, Cvalue);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define MIN(x, y) (((x) < (y)) ? (x) : (y))
__global__ void
matmult_kernel1(int m, int n, int k, double *A, double *B, double *C){
// set C to zeros
for (int i=0;i<m;i++){
for (int p=0;p<n;p++){
C[i*n+p]=0; //C[i][p]
}
}
// do matmult with mkn loop order
for (int i=0;i<m;i++) {
for (int j=0;j<k;j++){
for (int p=0;p<n;p++) {
C[i*n+p] += A[i*k+j] * B[j*n+p];
}
}
}
}
__global__ void
matmult_kernel2(int m, int n, int k, double *A, double *B, double *C){
int j = blockIdx.x*blockDim.x+threadIdx.x; //looping through n
int i = blockIdx.y*blockDim.y+threadIdx.y; //looping through m
double tmp;
if((j<n)&&(i<m)){
for(int p=0; p<k; p++){
//read row of A and col of B
//row of A is A[mit*k+kit]
//col of B is B[kit*n+nit]
tmp += A[i*k+p] * B[p*n+j];
}
//C is C[mit*n+nit]
C[i*n+j] = tmp;
}
}
__global__ void
matmult_kernel3(int m, int n, int k, double *A, double *B, double *C){
//compute C(i,j) and C(i,j+1)
int j = 2*(blockIdx.x*blockDim.x+threadIdx.x); //looping through n (only half as many threads/blocks)
int i = blockIdx.y*blockDim.y+threadIdx.y; //looping through m
double tmp1 = 0.0;
double tmp2 = 0.0;
if((j<n)&&(i<m)){
//additional j to compute (here, either 1 or 0)
int j_add = MIN(1,n-1-j);
for(int p=0; p<k; p++){
//row of A and col of B
tmp1 += A[i*k+p] * B[p*n+j];
if(j_add == 1)
tmp2 += A[i*k+p] * B[p*n+j+1];
}
C[i*n+j] = tmp1;
if(j_add == 1)
C[i*n+j+1] = tmp2;
}
}
__global__ void
matmult_kernel4(int m, int n, int k, double *A, double *B, double *C, int s){
//compute C(i,j), C(i,j+1), ... C(i,j+s)
int j = s*(blockIdx.x*blockDim.x+threadIdx.x); //looping through n (only 1/s as many threads/blocks)
int i = blockIdx.y*blockDim.y+threadIdx.y; //looping through m
double tmp1 = 0.0;
double tmp2 = 0.0;
double tmp3 = 0.0;
double tmp4 = 0.0;
double tmp5 = 0.0;
double tmp6 = 0.0;
double tmp7 = 0.0;
double tmp8 = 0.0;
double tmp9 = 0.0;
double tmp10 = 0.0;
double tmp11 = 0.0;
double tmp12 = 0.0;
double tmp13 = 0.0;
double tmp14 = 0.0;
double tmp15 = 0.0;
double tmp16 = 0.0;
if((j<n)&&(i<m)){
//additional j to compute (here, from 0 to s-1)
int j_add = MIN(s-1,n-1-j);
for(int p=0; p<k; p++){
//row of A and col of B
tmp1 += A[i*k+p] * B[p*n+j+0];
if(j_add > 0)
tmp2 += A[i*k+p] * B[p*n+j+1];
if(j_add > 1)
tmp3 += A[i*k+p] * B[p*n+j+2];
if(j_add > 2)
tmp4 += A[i*k+p] * B[p*n+j+3];
if(j_add > 3)
tmp5 += A[i*k+p] * B[p*n+j+4];
if(j_add > 4)
tmp6 += A[i*k+p] * B[p*n+j+5];
if(j_add > 5)
tmp7 += A[i*k+p] * B[p*n+j+6];
if(j_add > 6)
tmp8 += A[i*k+p] * B[p*n+j+7];
if(j_add > 7)
tmp9 += A[i*k+p] * B[p*n+j+8];
if(j_add > 8)
tmp10 += A[i*k+p] * B[p*n+j+9];
if(j_add > 9)
tmp11 += A[i*k+p] * B[p*n+j+10];
if(j_add > 10)
tmp12 += A[i*k+p] * B[p*n+j+11];
if(j_add > 11)
tmp13 += A[i*k+p] * B[p*n+j+12];
if(j_add > 12)
tmp14 += A[i*k+p] * B[p*n+j+13];
if(j_add > 13)
tmp15 += A[i*k+p] * B[p*n+j+14];
if(j_add > 14)
tmp16 += A[i*k+p] * B[p*n+j+15];
}
C[i*n+j] = tmp1;
if(j_add > 0)
C[i*n+j+1] = tmp2;
if(j_add > 1)
C[i*n+j+2] = tmp3;
if(j_add > 2)
C[i*n+j+3] = tmp4;
if(j_add > 3)
C[i*n+j+4] = tmp5;
if(j_add > 4)
C[i*n+j+5] = tmp6;
if(j_add > 5)
C[i*n+j+6] = tmp7;
if(j_add > 6)
C[i*n+j+7] = tmp8;
if(j_add > 7)
C[i*n+j+8] = tmp9;
if(j_add > 8)
C[i*n+j+9] = tmp10;
if(j_add > 9)
C[i*n+j+10] = tmp11;
if(j_add > 10)
C[i*n+j+11] = tmp12;
if(j_add > 11)
C[i*n+j+12] = tmp13;
if(j_add > 12)
C[i*n+j+13] = tmp14;
if(j_add > 13)
C[i*n+j+14] = tmp15;
if(j_add > 14)
C[i*n+j+15] = tmp16;
}
}
/*
BEGIN GPU 5
##############################################################################
*/
#define BLOCK_SIZE 16
typedef struct {
int width;
int height;
int stride;
double* elements;
} Matrix;
// Get a matrix element
__device__ double GetElement(const Matrix A, int row, int col)
{
return A.elements[row * A.stride + col];
}
// Set a matrix element
__device__ void SetElement(Matrix A, int row, int col,
double value)
{
A.elements[row * A.stride + col] = value;
}
// Get the BLOCK_SIZExBLOCK_SIZE sub-matrix Asub of A that is
// located col sub-matrices to the right and row sub-matrices down
// from the upper-left corner of A
__device__ Matrix GetSubMatrix(Matrix A, int row, int col)
{
Matrix Asub;
Asub.width = BLOCK_SIZE;
Asub.height = BLOCK_SIZE;
Asub.stride = A.stride;
Asub.elements = &A.elements[A.stride * BLOCK_SIZE * row + BLOCK_SIZE * col];
return Asub;
}
// Matrix multiplication kernel called by MatMul()
__global__ void gpu5_kernel(const Matrix A, const Matrix B, Matrix C)
{
// Block row and column
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
// Each thread block computes one sub-matrix Csub of C
Matrix Csub = GetSubMatrix(C, blockRow, blockCol);
// Each thread computes one element of Csub
// by accumulating results into Cvalue
double Cvalue = 0;
// Thread row and column within Csub
int row = threadIdx.y;
int col = threadIdx.x;
// Loop over all the sub-matrices of A and B that are
// required to compute Csub
// Multiply each pair of sub-matrices together
// and accumulate the results
for (int m = 0; m < (A.width / BLOCK_SIZE); ++m) {
// Get sub-matrix Asub of A
Matrix Asub = GetSubMatrix(A, blockRow, m);
// Get sub-matrix Bsub of B
Matrix Bsub = GetSubMatrix(B, m, blockCol);
// Shared memory used to store Asub and Bsub respectively
__shared__ double As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ double Bs[BLOCK_SIZE][BLOCK_SIZE];
// Load Asub and Bsub from device memory to shared memory
// Each thread loads one element of each sub-matrix
As[row][col] = GetElement(Asub, row, col);
Bs[row][col] = GetElement(Bsub, row, col);
// Synchronize to make sure the sub-matrices are loaded
// before starting the computation
__syncthreads();
// Multiply Asub and Bsub together
for (int e = 0; e < BLOCK_SIZE; ++e)
Cvalue += As[row][e] * Bs[e][col];
// Synchronize to make sure that the preceding
// computation is done before loading two new
// sub-matrices of A and B in the next iteration
__syncthreads();
}
// Write Csub to device memory
// Each thread writes one element
SetElement(Csub, row, col, Cvalue);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define MIN(x, y) (((x) < (y)) ? (x) : (y))
__global__ void
matmult_kernel1(int m, int n, int k, double *A, double *B, double *C){
// set C to zeros
for (int i=0;i<m;i++){
for (int p=0;p<n;p++){
C[i*n+p]=0; //C[i][p]
}
}
// do matmult with mkn loop order
for (int i=0;i<m;i++) {
for (int j=0;j<k;j++){
for (int p=0;p<n;p++) {
C[i*n+p] += A[i*k+j] * B[j*n+p];
}
}
}
}
__global__ void
matmult_kernel2(int m, int n, int k, double *A, double *B, double *C){
int j = blockIdx.x*blockDim.x+threadIdx.x; //looping through n
int i = blockIdx.y*blockDim.y+threadIdx.y; //looping through m
double tmp;
if((j<n)&&(i<m)){
for(int p=0; p<k; p++){
//read row of A and col of B
//row of A is A[mit*k+kit]
//col of B is B[kit*n+nit]
tmp += A[i*k+p] * B[p*n+j];
}
//C is C[mit*n+nit]
C[i*n+j] = tmp;
}
}
__global__ void
matmult_kernel3(int m, int n, int k, double *A, double *B, double *C){
//compute C(i,j) and C(i,j+1)
int j = 2*(blockIdx.x*blockDim.x+threadIdx.x); //looping through n (only half as many threads/blocks)
int i = blockIdx.y*blockDim.y+threadIdx.y; //looping through m
double tmp1 = 0.0;
double tmp2 = 0.0;
if((j<n)&&(i<m)){
//additional j to compute (here, either 1 or 0)
int j_add = MIN(1,n-1-j);
for(int p=0; p<k; p++){
//row of A and col of B
tmp1 += A[i*k+p] * B[p*n+j];
if(j_add == 1)
tmp2 += A[i*k+p] * B[p*n+j+1];
}
C[i*n+j] = tmp1;
if(j_add == 1)
C[i*n+j+1] = tmp2;
}
}
__global__ void
matmult_kernel4(int m, int n, int k, double *A, double *B, double *C, int s){
//compute C(i,j), C(i,j+1), ... C(i,j+s)
int j = s*(blockIdx.x*blockDim.x+threadIdx.x); //looping through n (only 1/s as many threads/blocks)
int i = blockIdx.y*blockDim.y+threadIdx.y; //looping through m
double tmp1 = 0.0;
double tmp2 = 0.0;
double tmp3 = 0.0;
double tmp4 = 0.0;
double tmp5 = 0.0;
double tmp6 = 0.0;
double tmp7 = 0.0;
double tmp8 = 0.0;
double tmp9 = 0.0;
double tmp10 = 0.0;
double tmp11 = 0.0;
double tmp12 = 0.0;
double tmp13 = 0.0;
double tmp14 = 0.0;
double tmp15 = 0.0;
double tmp16 = 0.0;
if((j<n)&&(i<m)){
//additional j to compute (here, from 0 to s-1)
int j_add = MIN(s-1,n-1-j);
for(int p=0; p<k; p++){
//row of A and col of B
tmp1 += A[i*k+p] * B[p*n+j+0];
if(j_add > 0)
tmp2 += A[i*k+p] * B[p*n+j+1];
if(j_add > 1)
tmp3 += A[i*k+p] * B[p*n+j+2];
if(j_add > 2)
tmp4 += A[i*k+p] * B[p*n+j+3];
if(j_add > 3)
tmp5 += A[i*k+p] * B[p*n+j+4];
if(j_add > 4)
tmp6 += A[i*k+p] * B[p*n+j+5];
if(j_add > 5)
tmp7 += A[i*k+p] * B[p*n+j+6];
if(j_add > 6)
tmp8 += A[i*k+p] * B[p*n+j+7];
if(j_add > 7)
tmp9 += A[i*k+p] * B[p*n+j+8];
if(j_add > 8)
tmp10 += A[i*k+p] * B[p*n+j+9];
if(j_add > 9)
tmp11 += A[i*k+p] * B[p*n+j+10];
if(j_add > 10)
tmp12 += A[i*k+p] * B[p*n+j+11];
if(j_add > 11)
tmp13 += A[i*k+p] * B[p*n+j+12];
if(j_add > 12)
tmp14 += A[i*k+p] * B[p*n+j+13];
if(j_add > 13)
tmp15 += A[i*k+p] * B[p*n+j+14];
if(j_add > 14)
tmp16 += A[i*k+p] * B[p*n+j+15];
}
C[i*n+j] = tmp1;
if(j_add > 0)
C[i*n+j+1] = tmp2;
if(j_add > 1)
C[i*n+j+2] = tmp3;
if(j_add > 2)
C[i*n+j+3] = tmp4;
if(j_add > 3)
C[i*n+j+4] = tmp5;
if(j_add > 4)
C[i*n+j+5] = tmp6;
if(j_add > 5)
C[i*n+j+6] = tmp7;
if(j_add > 6)
C[i*n+j+7] = tmp8;
if(j_add > 7)
C[i*n+j+8] = tmp9;
if(j_add > 8)
C[i*n+j+9] = tmp10;
if(j_add > 9)
C[i*n+j+10] = tmp11;
if(j_add > 10)
C[i*n+j+11] = tmp12;
if(j_add > 11)
C[i*n+j+12] = tmp13;
if(j_add > 12)
C[i*n+j+13] = tmp14;
if(j_add > 13)
C[i*n+j+14] = tmp15;
if(j_add > 14)
C[i*n+j+15] = tmp16;
}
}
/*
BEGIN GPU 5
##############################################################################
*/
#define BLOCK_SIZE 16
typedef struct {
int width;
int height;
int stride;
double* elements;
} Matrix;
// Get a matrix element
__device__ double GetElement(const Matrix A, int row, int col)
{
return A.elements[row * A.stride + col];
}
// Set a matrix element
__device__ void SetElement(Matrix A, int row, int col,
double value)
{
A.elements[row * A.stride + col] = value;
}
// Get the BLOCK_SIZExBLOCK_SIZE sub-matrix Asub of A that is
// located col sub-matrices to the right and row sub-matrices down
// from the upper-left corner of A
__device__ Matrix GetSubMatrix(Matrix A, int row, int col)
{
Matrix Asub;
Asub.width = BLOCK_SIZE;
Asub.height = BLOCK_SIZE;
Asub.stride = A.stride;
Asub.elements = &A.elements[A.stride * BLOCK_SIZE * row + BLOCK_SIZE * col];
return Asub;
}
// Matrix multiplication kernel called by MatMul()
__global__ void gpu5_kernel(const Matrix A, const Matrix B, Matrix C)
{
// Block row and column
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
// Each thread block computes one sub-matrix Csub of C
Matrix Csub = GetSubMatrix(C, blockRow, blockCol);
// Each thread computes one element of Csub
// by accumulating results into Cvalue
double Cvalue = 0;
// Thread row and column within Csub
int row = threadIdx.y;
int col = threadIdx.x;
// Loop over all the sub-matrices of A and B that are
// required to compute Csub
// Multiply each pair of sub-matrices together
// and accumulate the results
for (int m = 0; m < (A.width / BLOCK_SIZE); ++m) {
// Get sub-matrix Asub of A
Matrix Asub = GetSubMatrix(A, blockRow, m);
// Get sub-matrix Bsub of B
Matrix Bsub = GetSubMatrix(B, m, blockCol);
// Shared memory used to store Asub and Bsub respectively
__shared__ double As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ double Bs[BLOCK_SIZE][BLOCK_SIZE];
// Load Asub and Bsub from device memory to shared memory
// Each thread loads one element of each sub-matrix
As[row][col] = GetElement(Asub, row, col);
Bs[row][col] = GetElement(Bsub, row, col);
// Synchronize to make sure the sub-matrices are loaded
// before starting the computation
__syncthreads();
// Multiply Asub and Bsub together
for (int e = 0; e < BLOCK_SIZE; ++e)
Cvalue += As[row][e] * Bs[e][col];
// Synchronize to make sure that the preceding
// computation is done before loading two new
// sub-matrices of A and B in the next iteration
__syncthreads();
}
// Write Csub to device memory
// Each thread writes one element
SetElement(Csub, row, col, Cvalue);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15matmult_kernel1iiiPdS_S_
.globl _Z15matmult_kernel1iiiPdS_S_
.p2align 8
.type _Z15matmult_kernel1iiiPdS_S_,@function
_Z15matmult_kernel1iiiPdS_S_:
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x0
s_load_b64 s[10:11], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s8, 1
s_cbranch_scc1 .LBB0_6
s_cmp_gt_i32 s9, 0
s_mov_b32 s5, 0
s_cselect_b32 s2, -1, 0
s_mov_b32 s4, s5
v_cndmask_b32_e64 v0, 0, 1, s2
s_mov_b32 s3, s5
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_2)
v_cmp_ne_u32_e64 s2, 1, v0
v_mov_b32_e32 v0, 0
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_add_i32 s3, s3, 1
s_add_i32 s4, s4, s9
s_cmp_eq_u32 s3, s8
s_cbranch_scc1 .LBB0_6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_2
s_lshl_b64 s[6:7], s[4:5], 3
s_mov_b32 s12, s9
s_add_u32 s6, s10, s6
s_addc_u32 s7, s11, s7
.LBB0_5:
v_mov_b32_e32 v2, v1
s_add_i32 s12, s12, -1
global_store_b64 v0, v[1:2], s[6:7]
s_add_u32 s6, s6, 8
s_addc_u32 s7, s7, 0
s_cmp_eq_u32 s12, 0
s_cbranch_scc0 .LBB0_5
s_branch .LBB0_2
.LBB0_6:
s_cmp_lt_i32 s8, 1
s_cbranch_scc1 .LBB0_15
s_clause 0x1
s_load_b32 s22, s[0:1], 0x8
s_load_b128 s[4:7], s[0:1], 0x10
s_mov_b32 s3, 0
s_mov_b32 s23, 0
s_mov_b32 s12, s3
s_waitcnt lgkmcnt(0)
s_cmp_gt_i32 s22, 0
s_cselect_b32 s0, -1, 0
s_cmp_gt_i32 s9, 0
v_cndmask_b32_e64 v0, 0, 1, s0
s_cselect_b32 s0, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v1, 0, 1, s0
v_cmp_ne_u32_e64 s0, 1, v0
v_mov_b32_e32 v0, 0
s_delay_alu instid0(VALU_DEP_3)
v_cmp_ne_u32_e64 s1, 1, v1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_9
.p2align 6
.LBB0_8:
s_add_i32 s23, s23, 1
s_add_i32 s12, s12, s9
s_cmp_eq_u32 s23, s8
s_cbranch_scc1 .LBB0_15
.LBB0_9:
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccnz .LBB0_8
s_mov_b32 s13, s3
s_mov_b32 s2, 0
s_lshl_b64 s[14:15], s[12:13], 3
s_mul_i32 s24, s23, s22
s_add_u32 s14, s10, s14
s_addc_u32 s15, s11, s15
s_mov_b32 s13, s2
s_branch .LBB0_12
.p2align 6
.LBB0_11:
s_add_i32 s13, s13, 1
s_add_i32 s2, s2, s9
s_cmp_eq_u32 s13, s22
s_cbranch_scc1 .LBB0_8
.LBB0_12:
s_and_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB0_11
s_lshl_b64 s[16:17], s[2:3], 3
s_mov_b32 s19, s3
s_add_u32 s16, s6, s16
s_addc_u32 s17, s7, s17
s_add_i32 s18, s13, s24
s_mov_b32 s25, s9
s_lshl_b64 s[20:21], s[18:19], 3
s_mov_b64 s[18:19], s[14:15]
s_add_u32 s20, s4, s20
s_addc_u32 s21, s5, s21
.p2align 6
.LBB0_14:
s_clause 0x2
global_load_b64 v[1:2], v0, s[20:21]
global_load_b64 v[3:4], v0, s[16:17]
global_load_b64 v[5:6], v0, s[18:19]
s_add_i32 s25, s25, -1
s_waitcnt vmcnt(0)
v_fma_f64 v[1:2], v[1:2], v[3:4], v[5:6]
global_store_b64 v0, v[1:2], s[18:19]
s_add_u32 s18, s18, 8
s_addc_u32 s19, s19, 0
s_add_u32 s16, s16, 8
s_addc_u32 s17, s17, 0
s_cmp_eq_u32 s25, 0
s_cbranch_scc0 .LBB0_14
s_branch .LBB0_11
.LBB0_15:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15matmult_kernel1iiiPdS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 26
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15matmult_kernel1iiiPdS_S_, .Lfunc_end0-_Z15matmult_kernel1iiiPdS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15matmult_kernel2iiiPdS_S_
.globl _Z15matmult_kernel2iiiPdS_S_
.p2align 8
.type _Z15matmult_kernel2iiiPdS_S_,@function
_Z15matmult_kernel2iiiPdS_S_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x0
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s2, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB1_6
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB1_4
s_load_b128 s[4:7], s[0:1], 0x10
v_mul_lo_u32 v2, v1, s2
v_mov_b32_e32 v6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB1_3:
v_ashrrev_i32_e32 v7, 31, v6
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s2, 0
v_lshlrev_b64 v[7:8], 3, v[6:7]
v_add_nc_u32_e32 v6, s3, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b64 v[9:10], v[4:5], off
global_load_b64 v[7:8], v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 8
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[9:10], v[7:8], v[2:3]
s_cbranch_scc0 .LBB1_3
s_branch .LBB1_5
.LBB1_4:
.LBB1_5:
s_load_b64 s[0:1], s[0:1], 0x20
v_mad_u64_u32 v[4:5], null, v1, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[0:1], 3, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB1_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15matmult_kernel2iiiPdS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z15matmult_kernel2iiiPdS_S_, .Lfunc_end1-_Z15matmult_kernel2iiiPdS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15matmult_kernel3iiiPdS_S_
.globl _Z15matmult_kernel3iiiPdS_S_
.p2align 8
.type _Z15matmult_kernel3iiiPdS_S_,@function
_Z15matmult_kernel3iiiPdS_S_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x0
v_and_b32_e32 v3, 0x3ff, v0
v_bfe_u32 v2, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_mul_i32 s14, s14, s5
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_add_lshl_u32 v1, s14, v3, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e32 vcc_lo, s3, v1
v_cmp_gt_i32_e64 s2, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB2_8
s_load_b32 s6, s[0:1], 0x8
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
v_xad_u32 v14, v1, -1, s3
s_delay_alu instid0(VALU_DEP_2)
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s6, 1
s_cbranch_scc1 .LBB2_6
s_load_b128 s[8:11], s[0:1], 0x10
v_mul_lo_u32 v4, v0, s6
v_ashrrev_i32_e32 v2, 31, v1
v_cmp_lt_i32_e32 vcc_lo, 0, v14
s_ashr_i32 s5, s3, 31
s_mov_b32 s4, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 3, v[1:2]
v_mov_b32_e32 v2, 0
v_ashrrev_i32_e32 v5, 31, v4
v_mov_b32_e32 v3, 0
s_lshl_b64 s[4:5], s[4:5], 3
v_lshlrev_b64 v[4:5], 3, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v8, s2, v6, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v9, s2, s11, v7, s2
v_add_co_u32 v6, s2, s8, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e64 v7, s2, s9, v5, s2
v_add_co_u32 v8, s2, v8, 8
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v9, s2, 0, v9, s2
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_set_inst_prefetch_distance 0x1
s_branch .LBB2_4
.p2align 6
.LBB2_3:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[10:11], v[12:13], v[2:3]
v_add_co_u32 v8, s2, v8, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v9, s2, s5, v9, s2
v_add_co_u32 v6, s2, v6, 8
v_add_co_ci_u32_e64 v7, s2, 0, v7, s2
s_add_i32 s6, s6, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s6, 0
s_cbranch_scc1 .LBB2_6
.LBB2_4:
global_load_b64 v[10:11], v[6:7], off
global_load_b64 v[12:13], v[8:9], off offset:-8
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB2_3
global_load_b64 v[15:16], v[8:9], off
s_waitcnt vmcnt(0)
v_fma_f64 v[4:5], v[10:11], v[15:16], v[4:5]
s_branch .LBB2_3
.LBB2_6:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x20
v_mad_u64_u32 v[6:7], null, v0, s3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[0:1], 3, v[6:7]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, 0, v14
global_store_b64 v[0:1], v[2:3], off
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB2_8
global_store_b64 v[0:1], v[4:5], off offset:8
.LBB2_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15matmult_kernel3iiiPdS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z15matmult_kernel3iiiPdS_S_, .Lfunc_end2-_Z15matmult_kernel3iiiPdS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15matmult_kernel4iiiPdS_S_i
.globl _Z15matmult_kernel4iiiPdS_S_i
.p2align 8
.type _Z15matmult_kernel4iiiPdS_S_i,@function
_Z15matmult_kernel4iiiPdS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s3, s[0:1], 0x28
v_and_b32_e32 v1, 0x3ff, v0
s_load_b64 s[16:17], s[0:1], 0x0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s4, v[1:2]
v_mad_u64_u32 v[15:16], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v12, v2, s3
v_cmp_gt_i32_e64 s2, s16, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s17, v12
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB3_64
s_load_b32 s24, s[0:1], 0x8
v_xad_u32 v0, v12, -1, s17
v_mov_b32_e32 v26, 0
s_add_i32 s2, s3, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v0
v_dual_mov_b32 v27, 0 :: v_dual_cndmask_b32 v42, s2, v0
v_dual_mov_b32 v0, v26 :: v_dual_mov_b32 v1, v27
v_dual_mov_b32 v2, v26 :: v_dual_mov_b32 v3, v27
v_dual_mov_b32 v4, v26 :: v_dual_mov_b32 v5, v27
v_dual_mov_b32 v6, v26 :: v_dual_mov_b32 v7, v27
v_dual_mov_b32 v8, v26 :: v_dual_mov_b32 v9, v27
v_dual_mov_b32 v10, v26 :: v_dual_mov_b32 v11, v27
v_dual_mov_b32 v13, v26 :: v_dual_mov_b32 v14, v27
v_dual_mov_b32 v16, v26 :: v_dual_mov_b32 v17, v27
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
v_dual_mov_b32 v20, v26 :: v_dual_mov_b32 v21, v27
v_dual_mov_b32 v22, v26 :: v_dual_mov_b32 v23, v27
v_dual_mov_b32 v24, v26 :: v_dual_mov_b32 v25, v27
v_dual_mov_b32 v29, v27 :: v_dual_mov_b32 v28, v26
v_dual_mov_b32 v31, v27 :: v_dual_mov_b32 v30, v26
v_dual_mov_b32 v33, v27 :: v_dual_mov_b32 v32, v26
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s24, 1
s_cbranch_scc1 .LBB3_34
s_load_b128 s[20:23], s[0:1], 0x10
v_mul_lo_u32 v0, v15, s24
v_ashrrev_i32_e32 v13, 31, v12
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
v_cmp_lt_i32_e32 vcc_lo, 0, v42
v_cmp_lt_i32_e64 s2, 1, v42
v_lshlrev_b64 v[2:3], 3, v[12:13]
v_cmp_lt_i32_e64 s3, 2, v42
v_ashrrev_i32_e32 v1, 31, v0
v_cmp_lt_i32_e64 s4, 3, v42
v_cmp_lt_i32_e64 s5, 4, v42
v_cmp_lt_i32_e64 s6, 5, v42
v_cmp_lt_i32_e64 s7, 6, v42
v_lshlrev_b64 v[0:1], 3, v[0:1]
v_cmp_lt_i32_e64 s8, 7, v42
v_cmp_lt_i32_e64 s9, 8, v42
v_cmp_lt_i32_e64 s10, 9, v42
v_cmp_lt_i32_e64 s11, 10, v42
v_cmp_lt_i32_e64 s12, 11, v42
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, s16, v2, s22
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v3, s16, s23, v3, s16
v_cmp_lt_i32_e64 s13, 12, v42
v_add_co_u32 v34, s16, v2, 0x78
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v35, s16, 0, v3, s16
v_add_co_u32 v36, s16, s20, v0
v_cmp_lt_i32_e64 s14, 13, v42
v_cmp_lt_i32_e64 s15, 14, v42
v_add_co_ci_u32_e64 v37, s16, s21, v1, s16
v_dual_mov_b32 v0, v26 :: v_dual_mov_b32 v1, v27
v_dual_mov_b32 v2, v26 :: v_dual_mov_b32 v3, v27
v_dual_mov_b32 v4, v26 :: v_dual_mov_b32 v5, v27
v_dual_mov_b32 v6, v26 :: v_dual_mov_b32 v7, v27
v_dual_mov_b32 v8, v26 :: v_dual_mov_b32 v9, v27
v_dual_mov_b32 v10, v26 :: v_dual_mov_b32 v11, v27
v_dual_mov_b32 v13, v26 :: v_dual_mov_b32 v14, v27
v_dual_mov_b32 v16, v26 :: v_dual_mov_b32 v17, v27
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
v_dual_mov_b32 v20, v26 :: v_dual_mov_b32 v21, v27
v_dual_mov_b32 v22, v26 :: v_dual_mov_b32 v23, v27
v_dual_mov_b32 v24, v26 :: v_dual_mov_b32 v25, v27
v_dual_mov_b32 v29, v27 :: v_dual_mov_b32 v28, v26
v_dual_mov_b32 v31, v27 :: v_dual_mov_b32 v30, v26
v_dual_mov_b32 v33, v27 :: v_dual_mov_b32 v32, v26
s_ashr_i32 s19, s17, 31
s_mov_b32 s18, s17
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[18:19], s[18:19], 3
s_branch .LBB3_4
.LBB3_3:
s_or_b32 exec_lo, exec_lo, s16
s_waitcnt vmcnt(0)
v_fma_f64 v[26:27], v[38:39], v[40:41], v[26:27]
v_add_co_u32 v34, s16, v34, s18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v35, s16, s19, v35, s16
v_add_co_u32 v36, s16, v36, 8
v_add_co_ci_u32_e64 v37, s16, 0, v37, s16
s_add_i32 s24, s24, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s24, 0
s_cbranch_scc1 .LBB3_34
.LBB3_4:
global_load_b64 v[38:39], v[36:37], off
global_load_b64 v[40:41], v[34:35], off offset:-120
s_and_saveexec_b32 s16, vcc_lo
s_cbranch_execz .LBB3_6
global_load_b64 v[43:44], v[34:35], off offset:-112
s_waitcnt vmcnt(0)
v_fma_f64 v[32:33], v[38:39], v[43:44], v[32:33]
.LBB3_6:
s_or_b32 exec_lo, exec_lo, s16
s_and_saveexec_b32 s16, s2
s_cbranch_execz .LBB3_8
global_load_b64 v[43:44], v[34:35], off offset:-104
s_waitcnt vmcnt(0)
v_fma_f64 v[30:31], v[38:39], v[43:44], v[30:31]
.LBB3_8:
s_or_b32 exec_lo, exec_lo, s16
s_and_saveexec_b32 s16, s3
s_cbranch_execz .LBB3_10
global_load_b64 v[43:44], v[34:35], off offset:-96
s_waitcnt vmcnt(0)
v_fma_f64 v[28:29], v[38:39], v[43:44], v[28:29]
.LBB3_10:
s_or_b32 exec_lo, exec_lo, s16
s_and_saveexec_b32 s16, s4
s_cbranch_execz .LBB3_12
global_load_b64 v[43:44], v[34:35], off offset:-88
s_waitcnt vmcnt(0)
v_fma_f64 v[24:25], v[38:39], v[43:44], v[24:25]
.LBB3_12:
s_or_b32 exec_lo, exec_lo, s16
s_and_saveexec_b32 s16, s5
s_cbranch_execz .LBB3_14
global_load_b64 v[43:44], v[34:35], off offset:-80
s_waitcnt vmcnt(0)
v_fma_f64 v[22:23], v[38:39], v[43:44], v[22:23]
.LBB3_14:
s_or_b32 exec_lo, exec_lo, s16
s_and_saveexec_b32 s16, s6
s_cbranch_execz .LBB3_16
global_load_b64 v[43:44], v[34:35], off offset:-72
s_waitcnt vmcnt(0)
v_fma_f64 v[20:21], v[38:39], v[43:44], v[20:21]
.LBB3_16:
s_or_b32 exec_lo, exec_lo, s16
s_and_saveexec_b32 s16, s7
s_cbranch_execz .LBB3_18
global_load_b64 v[43:44], v[34:35], off offset:-64
s_waitcnt vmcnt(0)
v_fma_f64 v[18:19], v[38:39], v[43:44], v[18:19]
.LBB3_18:
s_or_b32 exec_lo, exec_lo, s16
s_and_saveexec_b32 s16, s8
s_cbranch_execz .LBB3_20
global_load_b64 v[43:44], v[34:35], off offset:-56
s_waitcnt vmcnt(0)
v_fma_f64 v[16:17], v[38:39], v[43:44], v[16:17]
.LBB3_20:
s_or_b32 exec_lo, exec_lo, s16
s_and_saveexec_b32 s16, s9
s_cbranch_execz .LBB3_22
global_load_b64 v[43:44], v[34:35], off offset:-48
s_waitcnt vmcnt(0)
v_fma_f64 v[13:14], v[38:39], v[43:44], v[13:14]
.LBB3_22:
s_or_b32 exec_lo, exec_lo, s16
s_and_saveexec_b32 s16, s10
s_cbranch_execz .LBB3_24
global_load_b64 v[43:44], v[34:35], off offset:-40
s_waitcnt vmcnt(0)
v_fma_f64 v[10:11], v[38:39], v[43:44], v[10:11]
.LBB3_24:
s_or_b32 exec_lo, exec_lo, s16
s_and_saveexec_b32 s16, s11
s_cbranch_execz .LBB3_26
global_load_b64 v[43:44], v[34:35], off offset:-32
s_waitcnt vmcnt(0)
v_fma_f64 v[8:9], v[38:39], v[43:44], v[8:9]
.LBB3_26:
s_or_b32 exec_lo, exec_lo, s16
s_and_saveexec_b32 s16, s12
s_cbranch_execz .LBB3_28
global_load_b64 v[43:44], v[34:35], off offset:-24
s_waitcnt vmcnt(0)
v_fma_f64 v[6:7], v[38:39], v[43:44], v[6:7]
.LBB3_28:
s_or_b32 exec_lo, exec_lo, s16
s_and_saveexec_b32 s16, s13
s_cbranch_execz .LBB3_30
global_load_b64 v[43:44], v[34:35], off offset:-16
s_waitcnt vmcnt(0)
v_fma_f64 v[4:5], v[38:39], v[43:44], v[4:5]
.LBB3_30:
s_or_b32 exec_lo, exec_lo, s16
s_and_saveexec_b32 s16, s14
s_cbranch_execz .LBB3_32
global_load_b64 v[43:44], v[34:35], off offset:-8
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[38:39], v[43:44], v[2:3]
.LBB3_32:
s_or_b32 exec_lo, exec_lo, s16
s_and_saveexec_b32 s16, s15
s_cbranch_execz .LBB3_3
global_load_b64 v[43:44], v[34:35], off
s_waitcnt vmcnt(0)
v_fma_f64 v[0:1], v[38:39], v[43:44], v[0:1]
s_branch .LBB3_3
.LBB3_34:
s_load_b64 s[0:1], s[0:1], 0x20
v_mad_u64_u32 v[34:35], null, v15, s17, v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v35, 31, v34
v_lshlrev_b64 v[34:35], 3, v[34:35]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v34, vcc_lo, s0, v34
v_add_co_ci_u32_e32 v35, vcc_lo, s1, v35, vcc_lo
s_mov_b32 s0, exec_lo
global_store_b64 v[34:35], v[26:27], off
v_cmpx_lt_i32_e32 0, v42
s_cbranch_execz .LBB3_36
global_store_b64 v[34:35], v[32:33], off offset:8
.LBB3_36:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
v_cmpx_lt_i32_e32 1, v42
s_cbranch_execz .LBB3_38
global_store_b64 v[34:35], v[30:31], off offset:16
.LBB3_38:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
v_cmpx_lt_i32_e32 2, v42
s_cbranch_execz .LBB3_40
global_store_b64 v[34:35], v[28:29], off offset:24
.LBB3_40:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
v_cmpx_lt_i32_e32 3, v42
s_cbranch_execz .LBB3_42
global_store_b64 v[34:35], v[24:25], off offset:32
.LBB3_42:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
v_cmpx_lt_i32_e32 4, v42
s_cbranch_execz .LBB3_44
global_store_b64 v[34:35], v[22:23], off offset:40
.LBB3_44:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
v_cmpx_lt_i32_e32 5, v42
s_cbranch_execz .LBB3_46
global_store_b64 v[34:35], v[20:21], off offset:48
.LBB3_46:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
v_cmpx_lt_i32_e32 6, v42
s_cbranch_execz .LBB3_48
global_store_b64 v[34:35], v[18:19], off offset:56
.LBB3_48:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
v_cmpx_lt_i32_e32 7, v42
s_cbranch_execz .LBB3_50
global_store_b64 v[34:35], v[16:17], off offset:64
.LBB3_50:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
v_cmpx_lt_i32_e32 8, v42
s_cbranch_execz .LBB3_52
global_store_b64 v[34:35], v[13:14], off offset:72
.LBB3_52:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
v_cmpx_lt_i32_e32 9, v42
s_cbranch_execz .LBB3_54
global_store_b64 v[34:35], v[10:11], off offset:80
.LBB3_54:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
v_cmpx_lt_i32_e32 10, v42
s_cbranch_execz .LBB3_56
global_store_b64 v[34:35], v[8:9], off offset:88
.LBB3_56:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
v_cmpx_lt_i32_e32 11, v42
s_cbranch_execz .LBB3_58
global_store_b64 v[34:35], v[6:7], off offset:96
.LBB3_58:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
v_cmpx_lt_i32_e32 12, v42
s_cbranch_execz .LBB3_60
global_store_b64 v[34:35], v[4:5], off offset:104
.LBB3_60:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
v_cmpx_lt_i32_e32 13, v42
s_cbranch_execz .LBB3_62
global_store_b64 v[34:35], v[2:3], off offset:112
.LBB3_62:
s_or_b32 exec_lo, exec_lo, s0
v_cmp_lt_i32_e32 vcc_lo, 14, v42
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB3_64
global_store_b64 v[34:35], v[0:1], off offset:120
.LBB3_64:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15matmult_kernel4iiiPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 45
.amdhsa_next_free_sgpr 25
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z15matmult_kernel4iiiPdS_S_i, .Lfunc_end3-_Z15matmult_kernel4iiiPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11gpu5_kernel6MatrixS_S_
.globl _Z11gpu5_kernel6MatrixS_S_
.p2align 8
.type _Z11gpu5_kernel6MatrixS_S_,@function
_Z11gpu5_kernel6MatrixS_S_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x40
v_mov_b32_e32 v1, 0
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s5, 16
s_cbranch_scc1 .LBB4_5
s_clause 0x3
s_load_b32 s10, s[0:1], 0x8
s_load_b32 s4, s[0:1], 0x20
s_load_b64 s[6:7], s[0:1], 0x10
s_load_b64 s[8:9], s[0:1], 0x28
v_lshlrev_b32_e32 v11, 3, v0
v_lshlrev_b32_e32 v4, 7, v3
s_ashr_i32 s11, s5, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshr_b32 s11, s11, 28
s_add_i32 s5, s5, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_ashr_i32 s5, s5, 4
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[5:6], null, s10, v3, v[0:1]
v_mad_u64_u32 v[7:8], null, s4, v3, v[0:1]
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v6, 31, v5
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[9:10], 3, v[5:6]
v_add_nc_u32_e32 v5, v4, v11
v_add_nc_u32_e32 v6, 0x800, v11
v_lshlrev_b64 v[11:12], 3, v[7:8]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v10, vcc_lo
v_add_co_u32 v9, vcc_lo, s8, v11
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v10, vcc_lo, s9, v12, vcc_lo
v_add_nc_u32_e32 v11, v6, v4
s_mul_i32 s6, s10, s15
s_mov_b32 s7, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB4_2:
s_mul_i32 s8, s7, s4
s_add_i32 s9, s7, s6
s_add_i32 s10, s8, s14
s_lshl_b32 s8, s9, 4
s_lshl_b32 s10, s10, 4
s_ashr_i32 s9, s8, 31
s_ashr_i32 s11, s10, 31
s_lshl_b64 s[8:9], s[8:9], 3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_u32 v12, vcc_lo, v7, s8
v_add_co_ci_u32_e32 v13, vcc_lo, s9, v8, vcc_lo
s_lshl_b64 s[8:9], s[10:11], 3
v_add_co_u32 v14, vcc_lo, v9, s8
v_add_co_ci_u32_e32 v15, vcc_lo, s9, v10, vcc_lo
global_load_b64 v[16:17], v[12:13], off
global_load_b64 v[13:14], v[14:15], off
v_mov_b32_e32 v12, v6
s_mov_b32 s8, 0
s_waitcnt vmcnt(1)
ds_store_b64 v5, v[16:17]
s_waitcnt vmcnt(0)
ds_store_b64 v11, v[13:14]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB4_3:
v_add_nc_u32_e32 v15, s8, v4
s_add_i32 s8, s8, 8
ds_load_b64 v[13:14], v12
ds_load_b64 v[15:16], v15
v_add_nc_u32_e32 v12, 0x80, v12
s_cmpk_eq_i32 s8, 0x80
s_waitcnt lgkmcnt(0)
v_fma_f64 v[1:2], v[15:16], v[13:14], v[1:2]
s_cbranch_scc0 .LBB4_3
s_add_i32 s7, s7, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s7, s5
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB4_2
.LBB4_5:
s_set_inst_prefetch_distance 0x2
s_load_b32 s0, s[0:1], 0x38
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[4:5], null, s0, v3, v[0:1]
s_mul_i32 s0, s0, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s0, s0, s14
s_lshl_b32 s0, s0, 4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_ashr_i32 s1, s0, 31
v_ashrrev_i32_e32 v5, 31, v4
s_lshl_b64 s[0:1], s[0:1], 3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_add_u32 s0, s2, s0
s_addc_u32 s1, s3, s1
v_lshlrev_b64 v[3:4], 3, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_store_b64 v[3:4], v[1:2], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11gpu5_kernel6MatrixS_S_
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 72
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end4:
.size _Z11gpu5_kernel6MatrixS_S_, .Lfunc_end4-_Z11gpu5_kernel6MatrixS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15matmult_kernel1iiiPdS_S_
.private_segment_fixed_size: 0
.sgpr_count: 28
.sgpr_spill_count: 0
.symbol: _Z15matmult_kernel1iiiPdS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15matmult_kernel2iiiPdS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15matmult_kernel2iiiPdS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15matmult_kernel3iiiPdS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15matmult_kernel3iiiPdS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15matmult_kernel4iiiPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 27
.sgpr_spill_count: 0
.symbol: _Z15matmult_kernel4iiiPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 45
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 24
.value_kind: by_value
- .offset: 24
.size: 24
.value_kind: by_value
- .offset: 48
.size: 24
.value_kind: by_value
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 72
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11gpu5_kernel6MatrixS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11gpu5_kernel6MatrixS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define MIN(x, y) (((x) < (y)) ? (x) : (y))
__global__ void
matmult_kernel1(int m, int n, int k, double *A, double *B, double *C){
// set C to zeros
for (int i=0;i<m;i++){
for (int p=0;p<n;p++){
C[i*n+p]=0; //C[i][p]
}
}
// do matmult with mkn loop order
for (int i=0;i<m;i++) {
for (int j=0;j<k;j++){
for (int p=0;p<n;p++) {
C[i*n+p] += A[i*k+j] * B[j*n+p];
}
}
}
}
__global__ void
matmult_kernel2(int m, int n, int k, double *A, double *B, double *C){
int j = blockIdx.x*blockDim.x+threadIdx.x; //looping through n
int i = blockIdx.y*blockDim.y+threadIdx.y; //looping through m
double tmp;
if((j<n)&&(i<m)){
for(int p=0; p<k; p++){
//read row of A and col of B
//row of A is A[mit*k+kit]
//col of B is B[kit*n+nit]
tmp += A[i*k+p] * B[p*n+j];
}
//C is C[mit*n+nit]
C[i*n+j] = tmp;
}
}
__global__ void
matmult_kernel3(int m, int n, int k, double *A, double *B, double *C){
//compute C(i,j) and C(i,j+1)
int j = 2*(blockIdx.x*blockDim.x+threadIdx.x); //looping through n (only half as many threads/blocks)
int i = blockIdx.y*blockDim.y+threadIdx.y; //looping through m
double tmp1 = 0.0;
double tmp2 = 0.0;
if((j<n)&&(i<m)){
//additional j to compute (here, either 1 or 0)
int j_add = MIN(1,n-1-j);
for(int p=0; p<k; p++){
//row of A and col of B
tmp1 += A[i*k+p] * B[p*n+j];
if(j_add == 1)
tmp2 += A[i*k+p] * B[p*n+j+1];
}
C[i*n+j] = tmp1;
if(j_add == 1)
C[i*n+j+1] = tmp2;
}
}
__global__ void
matmult_kernel4(int m, int n, int k, double *A, double *B, double *C, int s){
//compute C(i,j), C(i,j+1), ... C(i,j+s)
int j = s*(blockIdx.x*blockDim.x+threadIdx.x); //looping through n (only 1/s as many threads/blocks)
int i = blockIdx.y*blockDim.y+threadIdx.y; //looping through m
double tmp1 = 0.0;
double tmp2 = 0.0;
double tmp3 = 0.0;
double tmp4 = 0.0;
double tmp5 = 0.0;
double tmp6 = 0.0;
double tmp7 = 0.0;
double tmp8 = 0.0;
double tmp9 = 0.0;
double tmp10 = 0.0;
double tmp11 = 0.0;
double tmp12 = 0.0;
double tmp13 = 0.0;
double tmp14 = 0.0;
double tmp15 = 0.0;
double tmp16 = 0.0;
if((j<n)&&(i<m)){
//additional j to compute (here, from 0 to s-1)
int j_add = MIN(s-1,n-1-j);
for(int p=0; p<k; p++){
//row of A and col of B
tmp1 += A[i*k+p] * B[p*n+j+0];
if(j_add > 0)
tmp2 += A[i*k+p] * B[p*n+j+1];
if(j_add > 1)
tmp3 += A[i*k+p] * B[p*n+j+2];
if(j_add > 2)
tmp4 += A[i*k+p] * B[p*n+j+3];
if(j_add > 3)
tmp5 += A[i*k+p] * B[p*n+j+4];
if(j_add > 4)
tmp6 += A[i*k+p] * B[p*n+j+5];
if(j_add > 5)
tmp7 += A[i*k+p] * B[p*n+j+6];
if(j_add > 6)
tmp8 += A[i*k+p] * B[p*n+j+7];
if(j_add > 7)
tmp9 += A[i*k+p] * B[p*n+j+8];
if(j_add > 8)
tmp10 += A[i*k+p] * B[p*n+j+9];
if(j_add > 9)
tmp11 += A[i*k+p] * B[p*n+j+10];
if(j_add > 10)
tmp12 += A[i*k+p] * B[p*n+j+11];
if(j_add > 11)
tmp13 += A[i*k+p] * B[p*n+j+12];
if(j_add > 12)
tmp14 += A[i*k+p] * B[p*n+j+13];
if(j_add > 13)
tmp15 += A[i*k+p] * B[p*n+j+14];
if(j_add > 14)
tmp16 += A[i*k+p] * B[p*n+j+15];
}
C[i*n+j] = tmp1;
if(j_add > 0)
C[i*n+j+1] = tmp2;
if(j_add > 1)
C[i*n+j+2] = tmp3;
if(j_add > 2)
C[i*n+j+3] = tmp4;
if(j_add > 3)
C[i*n+j+4] = tmp5;
if(j_add > 4)
C[i*n+j+5] = tmp6;
if(j_add > 5)
C[i*n+j+6] = tmp7;
if(j_add > 6)
C[i*n+j+7] = tmp8;
if(j_add > 7)
C[i*n+j+8] = tmp9;
if(j_add > 8)
C[i*n+j+9] = tmp10;
if(j_add > 9)
C[i*n+j+10] = tmp11;
if(j_add > 10)
C[i*n+j+11] = tmp12;
if(j_add > 11)
C[i*n+j+12] = tmp13;
if(j_add > 12)
C[i*n+j+13] = tmp14;
if(j_add > 13)
C[i*n+j+14] = tmp15;
if(j_add > 14)
C[i*n+j+15] = tmp16;
}
}
/*
BEGIN GPU 5
##############################################################################
*/
#define BLOCK_SIZE 16
typedef struct {
int width;
int height;
int stride;
double* elements;
} Matrix;
// Get a matrix element
__device__ double GetElement(const Matrix A, int row, int col)
{
return A.elements[row * A.stride + col];
}
// Set a matrix element
__device__ void SetElement(Matrix A, int row, int col,
double value)
{
A.elements[row * A.stride + col] = value;
}
// Get the BLOCK_SIZExBLOCK_SIZE sub-matrix Asub of A that is
// located col sub-matrices to the right and row sub-matrices down
// from the upper-left corner of A
__device__ Matrix GetSubMatrix(Matrix A, int row, int col)
{
Matrix Asub;
Asub.width = BLOCK_SIZE;
Asub.height = BLOCK_SIZE;
Asub.stride = A.stride;
Asub.elements = &A.elements[A.stride * BLOCK_SIZE * row + BLOCK_SIZE * col];
return Asub;
}
// Matrix multiplication kernel called by MatMul()
__global__ void gpu5_kernel(const Matrix A, const Matrix B, Matrix C)
{
// Block row and column
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
// Each thread block computes one sub-matrix Csub of C
Matrix Csub = GetSubMatrix(C, blockRow, blockCol);
// Each thread computes one element of Csub
// by accumulating results into Cvalue
double Cvalue = 0;
// Thread row and column within Csub
int row = threadIdx.y;
int col = threadIdx.x;
// Loop over all the sub-matrices of A and B that are
// required to compute Csub
// Multiply each pair of sub-matrices together
// and accumulate the results
for (int m = 0; m < (A.width / BLOCK_SIZE); ++m) {
// Get sub-matrix Asub of A
Matrix Asub = GetSubMatrix(A, blockRow, m);
// Get sub-matrix Bsub of B
Matrix Bsub = GetSubMatrix(B, m, blockCol);
// Shared memory used to store Asub and Bsub respectively
__shared__ double As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ double Bs[BLOCK_SIZE][BLOCK_SIZE];
// Load Asub and Bsub from device memory to shared memory
// Each thread loads one element of each sub-matrix
As[row][col] = GetElement(Asub, row, col);
Bs[row][col] = GetElement(Bsub, row, col);
// Synchronize to make sure the sub-matrices are loaded
// before starting the computation
__syncthreads();
// Multiply Asub and Bsub together
for (int e = 0; e < BLOCK_SIZE; ++e)
Cvalue += As[row][e] * Bs[e][col];
// Synchronize to make sure that the preceding
// computation is done before loading two new
// sub-matrices of A and B in the next iteration
__syncthreads();
}
// Write Csub to device memory
// Each thread writes one element
SetElement(Csub, row, col, Cvalue);
} | .text
.file "matmult_kernels.hip"
.globl _Z30__device_stub__matmult_kernel1iiiPdS_S_ # -- Begin function _Z30__device_stub__matmult_kernel1iiiPdS_S_
.p2align 4, 0x90
.type _Z30__device_stub__matmult_kernel1iiiPdS_S_,@function
_Z30__device_stub__matmult_kernel1iiiPdS_S_: # @_Z30__device_stub__matmult_kernel1iiiPdS_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 88(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15matmult_kernel1iiiPdS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z30__device_stub__matmult_kernel1iiiPdS_S_, .Lfunc_end0-_Z30__device_stub__matmult_kernel1iiiPdS_S_
.cfi_endproc
# -- End function
.globl _Z30__device_stub__matmult_kernel2iiiPdS_S_ # -- Begin function _Z30__device_stub__matmult_kernel2iiiPdS_S_
.p2align 4, 0x90
.type _Z30__device_stub__matmult_kernel2iiiPdS_S_,@function
_Z30__device_stub__matmult_kernel2iiiPdS_S_: # @_Z30__device_stub__matmult_kernel2iiiPdS_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 88(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15matmult_kernel2iiiPdS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z30__device_stub__matmult_kernel2iiiPdS_S_, .Lfunc_end1-_Z30__device_stub__matmult_kernel2iiiPdS_S_
.cfi_endproc
# -- End function
.globl _Z30__device_stub__matmult_kernel3iiiPdS_S_ # -- Begin function _Z30__device_stub__matmult_kernel3iiiPdS_S_
.p2align 4, 0x90
.type _Z30__device_stub__matmult_kernel3iiiPdS_S_,@function
_Z30__device_stub__matmult_kernel3iiiPdS_S_: # @_Z30__device_stub__matmult_kernel3iiiPdS_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 88(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15matmult_kernel3iiiPdS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size _Z30__device_stub__matmult_kernel3iiiPdS_S_, .Lfunc_end2-_Z30__device_stub__matmult_kernel3iiiPdS_S_
.cfi_endproc
# -- End function
.globl _Z30__device_stub__matmult_kernel4iiiPdS_S_i # -- Begin function _Z30__device_stub__matmult_kernel4iiiPdS_S_i
.p2align 4, 0x90
.type _Z30__device_stub__matmult_kernel4iiiPdS_S_i,@function
_Z30__device_stub__matmult_kernel4iiiPdS_S_i: # @_Z30__device_stub__matmult_kernel4iiiPdS_S_i
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 88(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15matmult_kernel4iiiPdS_S_i, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end3:
.size _Z30__device_stub__matmult_kernel4iiiPdS_S_i, .Lfunc_end3-_Z30__device_stub__matmult_kernel4iiiPdS_S_i
.cfi_endproc
# -- End function
.globl _Z26__device_stub__gpu5_kernel6MatrixS_S_ # -- Begin function _Z26__device_stub__gpu5_kernel6MatrixS_S_
.p2align 4, 0x90
.type _Z26__device_stub__gpu5_kernel6MatrixS_S_,@function
_Z26__device_stub__gpu5_kernel6MatrixS_S_: # @_Z26__device_stub__gpu5_kernel6MatrixS_S_
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
leaq 80(%rsp), %rax
movq %rax, 48(%rsp)
leaq 104(%rsp), %rax
movq %rax, 56(%rsp)
leaq 128(%rsp), %rax
movq %rax, 64(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z11gpu5_kernel6MatrixS_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end4:
.size _Z26__device_stub__gpu5_kernel6MatrixS_S_, .Lfunc_end4-_Z26__device_stub__gpu5_kernel6MatrixS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15matmult_kernel1iiiPdS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15matmult_kernel2iiiPdS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15matmult_kernel3iiiPdS_S_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15matmult_kernel4iiiPdS_S_i, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11gpu5_kernel6MatrixS_S_, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15matmult_kernel1iiiPdS_S_,@object # @_Z15matmult_kernel1iiiPdS_S_
.section .rodata,"a",@progbits
.globl _Z15matmult_kernel1iiiPdS_S_
.p2align 3, 0x0
_Z15matmult_kernel1iiiPdS_S_:
.quad _Z30__device_stub__matmult_kernel1iiiPdS_S_
.size _Z15matmult_kernel1iiiPdS_S_, 8
.type _Z15matmult_kernel2iiiPdS_S_,@object # @_Z15matmult_kernel2iiiPdS_S_
.globl _Z15matmult_kernel2iiiPdS_S_
.p2align 3, 0x0
_Z15matmult_kernel2iiiPdS_S_:
.quad _Z30__device_stub__matmult_kernel2iiiPdS_S_
.size _Z15matmult_kernel2iiiPdS_S_, 8
.type _Z15matmult_kernel3iiiPdS_S_,@object # @_Z15matmult_kernel3iiiPdS_S_
.globl _Z15matmult_kernel3iiiPdS_S_
.p2align 3, 0x0
_Z15matmult_kernel3iiiPdS_S_:
.quad _Z30__device_stub__matmult_kernel3iiiPdS_S_
.size _Z15matmult_kernel3iiiPdS_S_, 8
.type _Z15matmult_kernel4iiiPdS_S_i,@object # @_Z15matmult_kernel4iiiPdS_S_i
.globl _Z15matmult_kernel4iiiPdS_S_i
.p2align 3, 0x0
_Z15matmult_kernel4iiiPdS_S_i:
.quad _Z30__device_stub__matmult_kernel4iiiPdS_S_i
.size _Z15matmult_kernel4iiiPdS_S_i, 8
.type _Z11gpu5_kernel6MatrixS_S_,@object # @_Z11gpu5_kernel6MatrixS_S_
.globl _Z11gpu5_kernel6MatrixS_S_
.p2align 3, 0x0
_Z11gpu5_kernel6MatrixS_S_:
.quad _Z26__device_stub__gpu5_kernel6MatrixS_S_
.size _Z11gpu5_kernel6MatrixS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15matmult_kernel1iiiPdS_S_"
.size .L__unnamed_1, 29
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15matmult_kernel2iiiPdS_S_"
.size .L__unnamed_2, 29
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z15matmult_kernel3iiiPdS_S_"
.size .L__unnamed_3, 29
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z15matmult_kernel4iiiPdS_S_i"
.size .L__unnamed_4, 30
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z11gpu5_kernel6MatrixS_S_"
.size .L__unnamed_5, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__matmult_kernel1iiiPdS_S_
.addrsig_sym _Z30__device_stub__matmult_kernel2iiiPdS_S_
.addrsig_sym _Z30__device_stub__matmult_kernel3iiiPdS_S_
.addrsig_sym _Z30__device_stub__matmult_kernel4iiiPdS_S_i
.addrsig_sym _Z26__device_stub__gpu5_kernel6MatrixS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15matmult_kernel1iiiPdS_S_
.addrsig_sym _Z15matmult_kernel2iiiPdS_S_
.addrsig_sym _Z15matmult_kernel3iiiPdS_S_
.addrsig_sym _Z15matmult_kernel4iiiPdS_S_i
.addrsig_sym _Z11gpu5_kernel6MatrixS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00152ae4_00000000-6_matmult_kernels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10GetElement6Matrixii
.type _Z10GetElement6Matrixii, @function
_Z10GetElement6Matrixii:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z10GetElement6Matrixii, .-_Z10GetElement6Matrixii
.globl _Z10SetElement6Matrixiid
.type _Z10SetElement6Matrixiid, @function
_Z10SetElement6Matrixiid:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z10SetElement6Matrixiid, .-_Z10SetElement6Matrixiid
.globl _Z12GetSubMatrix6Matrixii
.type _Z12GetSubMatrix6Matrixii, @function
_Z12GetSubMatrix6Matrixii:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z12GetSubMatrix6Matrixii, .-_Z12GetSubMatrix6Matrixii
.globl _Z42__device_stub__Z15matmult_kernel1iiiPdS_S_iiiPdS_S_
.type _Z42__device_stub__Z15matmult_kernel1iiiPdS_S_iiiPdS_S_, @function
_Z42__device_stub__Z15matmult_kernel1iiiPdS_S_iiiPdS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15matmult_kernel1iiiPdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z42__device_stub__Z15matmult_kernel1iiiPdS_S_iiiPdS_S_, .-_Z42__device_stub__Z15matmult_kernel1iiiPdS_S_iiiPdS_S_
.globl _Z15matmult_kernel1iiiPdS_S_
.type _Z15matmult_kernel1iiiPdS_S_, @function
_Z15matmult_kernel1iiiPdS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z15matmult_kernel1iiiPdS_S_iiiPdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z15matmult_kernel1iiiPdS_S_, .-_Z15matmult_kernel1iiiPdS_S_
.globl _Z42__device_stub__Z15matmult_kernel2iiiPdS_S_iiiPdS_S_
.type _Z42__device_stub__Z15matmult_kernel2iiiPdS_S_iiiPdS_S_, @function
_Z42__device_stub__Z15matmult_kernel2iiiPdS_S_iiiPdS_S_:
.LFB2086:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15matmult_kernel2iiiPdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z42__device_stub__Z15matmult_kernel2iiiPdS_S_iiiPdS_S_, .-_Z42__device_stub__Z15matmult_kernel2iiiPdS_S_iiiPdS_S_
.globl _Z15matmult_kernel2iiiPdS_S_
.type _Z15matmult_kernel2iiiPdS_S_, @function
_Z15matmult_kernel2iiiPdS_S_:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z15matmult_kernel2iiiPdS_S_iiiPdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z15matmult_kernel2iiiPdS_S_, .-_Z15matmult_kernel2iiiPdS_S_
.globl _Z42__device_stub__Z15matmult_kernel3iiiPdS_S_iiiPdS_S_
.type _Z42__device_stub__Z15matmult_kernel3iiiPdS_S_iiiPdS_S_, @function
_Z42__device_stub__Z15matmult_kernel3iiiPdS_S_iiiPdS_S_:
.LFB2088:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15matmult_kernel3iiiPdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z42__device_stub__Z15matmult_kernel3iiiPdS_S_iiiPdS_S_, .-_Z42__device_stub__Z15matmult_kernel3iiiPdS_S_iiiPdS_S_
.globl _Z15matmult_kernel3iiiPdS_S_
.type _Z15matmult_kernel3iiiPdS_S_, @function
_Z15matmult_kernel3iiiPdS_S_:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z15matmult_kernel3iiiPdS_S_iiiPdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z15matmult_kernel3iiiPdS_S_, .-_Z15matmult_kernel3iiiPdS_S_
.globl _Z43__device_stub__Z15matmult_kernel4iiiPdS_S_iiiiPdS_S_i
.type _Z43__device_stub__Z15matmult_kernel4iiiPdS_S_iiiiPdS_S_i, @function
_Z43__device_stub__Z15matmult_kernel4iiiPdS_S_iiiiPdS_S_i:
.LFB2090:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L37
.L33:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15matmult_kernel4iiiPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L33
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z43__device_stub__Z15matmult_kernel4iiiPdS_S_iiiiPdS_S_i, .-_Z43__device_stub__Z15matmult_kernel4iiiPdS_S_iiiiPdS_S_i
.globl _Z15matmult_kernel4iiiPdS_S_i
.type _Z15matmult_kernel4iiiPdS_S_i, @function
_Z15matmult_kernel4iiiPdS_S_i:
.LFB2091:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z43__device_stub__Z15matmult_kernel4iiiPdS_S_iiiiPdS_S_i
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z15matmult_kernel4iiiPdS_S_i, .-_Z15matmult_kernel4iiiPdS_S_i
.globl _Z40__device_stub__Z11gpu5_kernel6MatrixS_S_RK6MatrixS1_RS_
.type _Z40__device_stub__Z11gpu5_kernel6MatrixS_S_RK6MatrixS1_RS_, @function
_Z40__device_stub__Z11gpu5_kernel6MatrixS_S_RK6MatrixS1_RS_:
.LFB2092:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq %rdi, 64(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 80(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L45
.L41:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L46
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 120
pushq 8(%rsp)
.cfi_def_cfa_offset 128
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z11gpu5_kernel6MatrixS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L41
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2092:
.size _Z40__device_stub__Z11gpu5_kernel6MatrixS_S_RK6MatrixS1_RS_, .-_Z40__device_stub__Z11gpu5_kernel6MatrixS_S_RK6MatrixS1_RS_
.globl _Z11gpu5_kernel6MatrixS_S_
.type _Z11gpu5_kernel6MatrixS_S_, @function
_Z11gpu5_kernel6MatrixS_S_:
.LFB2093:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq 64(%rsp), %rdx
leaq 40(%rsp), %rsi
leaq 16(%rsp), %rdi
call _Z40__device_stub__Z11gpu5_kernel6MatrixS_S_RK6MatrixS1_RS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _Z11gpu5_kernel6MatrixS_S_, .-_Z11gpu5_kernel6MatrixS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11gpu5_kernel6MatrixS_S_"
.LC1:
.string "_Z15matmult_kernel4iiiPdS_S_i"
.LC2:
.string "_Z15matmult_kernel3iiiPdS_S_"
.LC3:
.string "_Z15matmult_kernel2iiiPdS_S_"
.LC4:
.string "_Z15matmult_kernel1iiiPdS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2095:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11gpu5_kernel6MatrixS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z15matmult_kernel4iiiPdS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z15matmult_kernel3iiiPdS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z15matmult_kernel2iiiPdS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z15matmult_kernel1iiiPdS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2095:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matmult_kernels.hip"
.globl _Z30__device_stub__matmult_kernel1iiiPdS_S_ # -- Begin function _Z30__device_stub__matmult_kernel1iiiPdS_S_
.p2align 4, 0x90
.type _Z30__device_stub__matmult_kernel1iiiPdS_S_,@function
_Z30__device_stub__matmult_kernel1iiiPdS_S_: # @_Z30__device_stub__matmult_kernel1iiiPdS_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 88(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15matmult_kernel1iiiPdS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z30__device_stub__matmult_kernel1iiiPdS_S_, .Lfunc_end0-_Z30__device_stub__matmult_kernel1iiiPdS_S_
.cfi_endproc
# -- End function
.globl _Z30__device_stub__matmult_kernel2iiiPdS_S_ # -- Begin function _Z30__device_stub__matmult_kernel2iiiPdS_S_
.p2align 4, 0x90
.type _Z30__device_stub__matmult_kernel2iiiPdS_S_,@function
_Z30__device_stub__matmult_kernel2iiiPdS_S_: # @_Z30__device_stub__matmult_kernel2iiiPdS_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 88(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15matmult_kernel2iiiPdS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z30__device_stub__matmult_kernel2iiiPdS_S_, .Lfunc_end1-_Z30__device_stub__matmult_kernel2iiiPdS_S_
.cfi_endproc
# -- End function
.globl _Z30__device_stub__matmult_kernel3iiiPdS_S_ # -- Begin function _Z30__device_stub__matmult_kernel3iiiPdS_S_
.p2align 4, 0x90
.type _Z30__device_stub__matmult_kernel3iiiPdS_S_,@function
_Z30__device_stub__matmult_kernel3iiiPdS_S_: # @_Z30__device_stub__matmult_kernel3iiiPdS_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 88(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15matmult_kernel3iiiPdS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size _Z30__device_stub__matmult_kernel3iiiPdS_S_, .Lfunc_end2-_Z30__device_stub__matmult_kernel3iiiPdS_S_
.cfi_endproc
# -- End function
.globl _Z30__device_stub__matmult_kernel4iiiPdS_S_i # -- Begin function _Z30__device_stub__matmult_kernel4iiiPdS_S_i
.p2align 4, 0x90
.type _Z30__device_stub__matmult_kernel4iiiPdS_S_i,@function
_Z30__device_stub__matmult_kernel4iiiPdS_S_i: # @_Z30__device_stub__matmult_kernel4iiiPdS_S_i
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 88(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15matmult_kernel4iiiPdS_S_i, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end3:
.size _Z30__device_stub__matmult_kernel4iiiPdS_S_i, .Lfunc_end3-_Z30__device_stub__matmult_kernel4iiiPdS_S_i
.cfi_endproc
# -- End function
.globl _Z26__device_stub__gpu5_kernel6MatrixS_S_ # -- Begin function _Z26__device_stub__gpu5_kernel6MatrixS_S_
.p2align 4, 0x90
.type _Z26__device_stub__gpu5_kernel6MatrixS_S_,@function
_Z26__device_stub__gpu5_kernel6MatrixS_S_: # @_Z26__device_stub__gpu5_kernel6MatrixS_S_
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
leaq 80(%rsp), %rax
movq %rax, 48(%rsp)
leaq 104(%rsp), %rax
movq %rax, 56(%rsp)
leaq 128(%rsp), %rax
movq %rax, 64(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z11gpu5_kernel6MatrixS_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end4:
.size _Z26__device_stub__gpu5_kernel6MatrixS_S_, .Lfunc_end4-_Z26__device_stub__gpu5_kernel6MatrixS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15matmult_kernel1iiiPdS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15matmult_kernel2iiiPdS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15matmult_kernel3iiiPdS_S_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15matmult_kernel4iiiPdS_S_i, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11gpu5_kernel6MatrixS_S_, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15matmult_kernel1iiiPdS_S_,@object # @_Z15matmult_kernel1iiiPdS_S_
.section .rodata,"a",@progbits
.globl _Z15matmult_kernel1iiiPdS_S_
.p2align 3, 0x0
_Z15matmult_kernel1iiiPdS_S_:
.quad _Z30__device_stub__matmult_kernel1iiiPdS_S_
.size _Z15matmult_kernel1iiiPdS_S_, 8
.type _Z15matmult_kernel2iiiPdS_S_,@object # @_Z15matmult_kernel2iiiPdS_S_
.globl _Z15matmult_kernel2iiiPdS_S_
.p2align 3, 0x0
_Z15matmult_kernel2iiiPdS_S_:
.quad _Z30__device_stub__matmult_kernel2iiiPdS_S_
.size _Z15matmult_kernel2iiiPdS_S_, 8
.type _Z15matmult_kernel3iiiPdS_S_,@object # @_Z15matmult_kernel3iiiPdS_S_
.globl _Z15matmult_kernel3iiiPdS_S_
.p2align 3, 0x0
_Z15matmult_kernel3iiiPdS_S_:
.quad _Z30__device_stub__matmult_kernel3iiiPdS_S_
.size _Z15matmult_kernel3iiiPdS_S_, 8
.type _Z15matmult_kernel4iiiPdS_S_i,@object # @_Z15matmult_kernel4iiiPdS_S_i
.globl _Z15matmult_kernel4iiiPdS_S_i
.p2align 3, 0x0
_Z15matmult_kernel4iiiPdS_S_i:
.quad _Z30__device_stub__matmult_kernel4iiiPdS_S_i
.size _Z15matmult_kernel4iiiPdS_S_i, 8
.type _Z11gpu5_kernel6MatrixS_S_,@object # @_Z11gpu5_kernel6MatrixS_S_
.globl _Z11gpu5_kernel6MatrixS_S_
.p2align 3, 0x0
_Z11gpu5_kernel6MatrixS_S_:
.quad _Z26__device_stub__gpu5_kernel6MatrixS_S_
.size _Z11gpu5_kernel6MatrixS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15matmult_kernel1iiiPdS_S_"
.size .L__unnamed_1, 29
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15matmult_kernel2iiiPdS_S_"
.size .L__unnamed_2, 29
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z15matmult_kernel3iiiPdS_S_"
.size .L__unnamed_3, 29
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z15matmult_kernel4iiiPdS_S_i"
.size .L__unnamed_4, 30
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z11gpu5_kernel6MatrixS_S_"
.size .L__unnamed_5, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__matmult_kernel1iiiPdS_S_
.addrsig_sym _Z30__device_stub__matmult_kernel2iiiPdS_S_
.addrsig_sym _Z30__device_stub__matmult_kernel3iiiPdS_S_
.addrsig_sym _Z30__device_stub__matmult_kernel4iiiPdS_S_i
.addrsig_sym _Z26__device_stub__gpu5_kernel6MatrixS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15matmult_kernel1iiiPdS_S_
.addrsig_sym _Z15matmult_kernel2iiiPdS_S_
.addrsig_sym _Z15matmult_kernel3iiiPdS_S_
.addrsig_sym _Z15matmult_kernel4iiiPdS_S_i
.addrsig_sym _Z11gpu5_kernel6MatrixS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
__global__ void kernel(int *array){
int index_x = blockIdx.x * blockDim.x + threadIdx.x;
int index_y = blockIdx.y * blockDim.y + threadIdx.y;
int grid_width = gridDim.x * blockDim.x;
int index = index_y * grid_width + index_x;
int result = blockIdx.y * gridDim.x + blockIdx.x;
array[index] = result;
}
int main(){
int num_elements_x = 16;
int num_elements_y = 16;
int num_bytes = num_elements_x * num_elements_y * sizeof(int);
int *device_array = NULL;
int *host_array = 0;
host_array = (int *) malloc(num_bytes);
cudaMalloc((void **) &device_array, num_bytes);
dim3 block_size;
block_size.x = 4;
block_size.y = 4;
dim3 grid_size;
grid_size.x = num_elements_x / block_size.x;
grid_size.y = num_elements_y / block_size.y;
kernel<<<grid_size, block_size>>>(device_array);
cudaMemcpy(host_array, device_array, num_bytes, cudaMemcpyDeviceToHost);
int row, col;
for(row = 0; row <num_elements_y; ++row){
for(col = 0; col<num_elements_x; ++col)
printf("%2d ", host_array[row*num_elements_x + col]);
printf("\n");
}
free(host_array);
cudaFree(device_array);
return 0;
} | code for sm_80
Function : _Z6kernelPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000e280000002200 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000ea20000002100 */
/*0060*/ IMAD R0, R2, c[0x0][0x4], R7 ; /* 0x0000010002007a24 */
/* 0x001fe200078e0207 */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fc600000001ff */
/*0080*/ IMAD R0, R0, c[0x0][0xc], R5.reuse ; /* 0x0000030000007a24 */
/* 0x102fe400078e0205 */
/*0090*/ IMAD R5, R2, c[0x0][0xc], R5 ; /* 0x0000030002057a24 */
/* 0x000fe400078e0205 */
/*00a0*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x004fc800078e0203 */
/*00b0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0207 */
/*00c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
__global__ void kernel(int *array){
int index_x = blockIdx.x * blockDim.x + threadIdx.x;
int index_y = blockIdx.y * blockDim.y + threadIdx.y;
int grid_width = gridDim.x * blockDim.x;
int index = index_y * grid_width + index_x;
int result = blockIdx.y * gridDim.x + blockIdx.x;
array[index] = result;
}
int main(){
int num_elements_x = 16;
int num_elements_y = 16;
int num_bytes = num_elements_x * num_elements_y * sizeof(int);
int *device_array = NULL;
int *host_array = 0;
host_array = (int *) malloc(num_bytes);
cudaMalloc((void **) &device_array, num_bytes);
dim3 block_size;
block_size.x = 4;
block_size.y = 4;
dim3 grid_size;
grid_size.x = num_elements_x / block_size.x;
grid_size.y = num_elements_y / block_size.y;
kernel<<<grid_size, block_size>>>(device_array);
cudaMemcpy(host_array, device_array, num_bytes, cudaMemcpyDeviceToHost);
int row, col;
for(row = 0; row <num_elements_y; ++row){
for(col = 0; col<num_elements_x; ++col)
printf("%2d ", host_array[row*num_elements_x + col]);
printf("\n");
}
free(host_array);
cudaFree(device_array);
return 0;
} | .file "tmpxft_000ff563_00000000-6_two_d_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z6kernelPiPi
.type _Z25__device_stub__Z6kernelPiPi, @function
_Z25__device_stub__Z6kernelPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z25__device_stub__Z6kernelPiPi, .-_Z25__device_stub__Z6kernelPiPi
.globl _Z6kernelPi
.type _Z6kernelPi, @function
_Z6kernelPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z6kernelPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6kernelPi, .-_Z6kernelPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%2d "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
movl $1024, %edi
call malloc@PLT
movq %rax, %r15
leaq 8(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
movl $4, 28(%rsp)
movl $4, 32(%rsp)
movl $4, 16(%rsp)
movl $4, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L12:
movl $2, %ecx
movl $1024, %edx
movq 8(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
leaq 64(%r15), %rbp
leaq 1088(%r15), %r14
leaq .LC0(%rip), %r12
leaq .LC1(%rip), %r13
.L13:
leaq -64(%rbp), %rbx
.L14:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L14
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $64, %rbp
cmpq %r14, %rbp
jne .L13
movq %r15, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z25__device_stub__Z6kernelPiPi
jmp .L12
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z6kernelPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
__global__ void kernel(int *array){
int index_x = blockIdx.x * blockDim.x + threadIdx.x;
int index_y = blockIdx.y * blockDim.y + threadIdx.y;
int grid_width = gridDim.x * blockDim.x;
int index = index_y * grid_width + index_x;
int result = blockIdx.y * gridDim.x + blockIdx.x;
array[index] = result;
}
int main(){
int num_elements_x = 16;
int num_elements_y = 16;
int num_bytes = num_elements_x * num_elements_y * sizeof(int);
int *device_array = NULL;
int *host_array = 0;
host_array = (int *) malloc(num_bytes);
cudaMalloc((void **) &device_array, num_bytes);
dim3 block_size;
block_size.x = 4;
block_size.y = 4;
dim3 grid_size;
grid_size.x = num_elements_x / block_size.x;
grid_size.y = num_elements_y / block_size.y;
kernel<<<grid_size, block_size>>>(device_array);
cudaMemcpy(host_array, device_array, num_bytes, cudaMemcpyDeviceToHost);
int row, col;
for(row = 0; row <num_elements_y; ++row){
for(col = 0; col<num_elements_x; ++col)
printf("%2d ", host_array[row*num_elements_x + col]);
printf("\n");
}
free(host_array);
cudaFree(device_array);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void kernel(int *array){
int index_x = blockIdx.x * blockDim.x + threadIdx.x;
int index_y = blockIdx.y * blockDim.y + threadIdx.y;
int grid_width = gridDim.x * blockDim.x;
int index = index_y * grid_width + index_x;
int result = blockIdx.y * gridDim.x + blockIdx.x;
array[index] = result;
}
int main(){
int num_elements_x = 16;
int num_elements_y = 16;
int num_bytes = num_elements_x * num_elements_y * sizeof(int);
int *device_array = NULL;
int *host_array = 0;
host_array = (int *) malloc(num_bytes);
hipMalloc((void **) &device_array, num_bytes);
dim3 block_size;
block_size.x = 4;
block_size.y = 4;
dim3 grid_size;
grid_size.x = num_elements_x / block_size.x;
grid_size.y = num_elements_y / block_size.y;
kernel<<<grid_size, block_size>>>(device_array);
hipMemcpy(host_array, device_array, num_bytes, hipMemcpyDeviceToHost);
int row, col;
for(row = 0; row <num_elements_y; ++row){
for(col = 0; col<num_elements_x; ++col)
printf("%2d ", host_array[row*num_elements_x + col]);
printf("\n");
}
free(host_array);
hipFree(device_array);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void kernel(int *array){
int index_x = blockIdx.x * blockDim.x + threadIdx.x;
int index_y = blockIdx.y * blockDim.y + threadIdx.y;
int grid_width = gridDim.x * blockDim.x;
int index = index_y * grid_width + index_x;
int result = blockIdx.y * gridDim.x + blockIdx.x;
array[index] = result;
}
int main(){
int num_elements_x = 16;
int num_elements_y = 16;
int num_bytes = num_elements_x * num_elements_y * sizeof(int);
int *device_array = NULL;
int *host_array = 0;
host_array = (int *) malloc(num_bytes);
hipMalloc((void **) &device_array, num_bytes);
dim3 block_size;
block_size.x = 4;
block_size.y = 4;
dim3 grid_size;
grid_size.x = num_elements_x / block_size.x;
grid_size.y = num_elements_y / block_size.y;
kernel<<<grid_size, block_size>>>(device_array);
hipMemcpy(host_array, device_array, num_bytes, hipMemcpyDeviceToHost);
int row, col;
for(row = 0; row <num_elements_y; ++row){
for(col = 0; col<num_elements_x; ++col)
printf("%2d ", host_array[row*num_elements_x + col]);
printf("\n");
}
free(host_array);
hipFree(device_array);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPi
.globl _Z6kernelPi
.p2align 8
.type _Z6kernelPi,@function
_Z6kernelPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b32 s3, s[0:1], 0x8
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v2, s3, s[14:15]
v_mad_u64_u32 v[1:2], null, v3, s2, v[0:1]
s_mul_i32 s2, s3, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_add_i32 s2, s2, s14
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, s2
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPi, .Lfunc_end0-_Z6kernelPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void kernel(int *array){
int index_x = blockIdx.x * blockDim.x + threadIdx.x;
int index_y = blockIdx.y * blockDim.y + threadIdx.y;
int grid_width = gridDim.x * blockDim.x;
int index = index_y * grid_width + index_x;
int result = blockIdx.y * gridDim.x + blockIdx.x;
array[index] = result;
}
int main(){
int num_elements_x = 16;
int num_elements_y = 16;
int num_bytes = num_elements_x * num_elements_y * sizeof(int);
int *device_array = NULL;
int *host_array = 0;
host_array = (int *) malloc(num_bytes);
hipMalloc((void **) &device_array, num_bytes);
dim3 block_size;
block_size.x = 4;
block_size.y = 4;
dim3 grid_size;
grid_size.x = num_elements_x / block_size.x;
grid_size.y = num_elements_y / block_size.y;
kernel<<<grid_size, block_size>>>(device_array);
hipMemcpy(host_array, device_array, num_bytes, hipMemcpyDeviceToHost);
int row, col;
for(row = 0; row <num_elements_y; ++row){
for(col = 0; col<num_elements_x; ++col)
printf("%2d ", host_array[row*num_elements_x + col]);
printf("\n");
}
free(host_array);
hipFree(device_array);
return 0;
} | .text
.file "two_d_kernel.hip"
.globl _Z21__device_stub__kernelPi # -- Begin function _Z21__device_stub__kernelPi
.p2align 4, 0x90
.type _Z21__device_stub__kernelPi,@function
_Z21__device_stub__kernelPi: # @_Z21__device_stub__kernelPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z6kernelPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPi, .Lfunc_end0-_Z21__device_stub__kernelPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $88, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq $0, 8(%rsp)
movl $1024, %edi # imm = 0x400
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movabsq $17179869188, %rdi # imm = 0x400000004
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z6kernelPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq %rbx, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_3: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_3 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r12,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $16, %r12
jne .LBB1_4
# %bb.5: # in Loop: Header=BB1_3 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addq $64, %r14
cmpq $16, %r15
jne .LBB1_3
# %bb.6:
movq %rbx, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPi,@object # @_Z6kernelPi
.section .rodata,"a",@progbits
.globl _Z6kernelPi
.p2align 3, 0x0
_Z6kernelPi:
.quad _Z21__device_stub__kernelPi
.size _Z6kernelPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%2d "
.size .L.str, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPi"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6kernelPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000e280000002200 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000ea20000002100 */
/*0060*/ IMAD R0, R2, c[0x0][0x4], R7 ; /* 0x0000010002007a24 */
/* 0x001fe200078e0207 */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fc600000001ff */
/*0080*/ IMAD R0, R0, c[0x0][0xc], R5.reuse ; /* 0x0000030000007a24 */
/* 0x102fe400078e0205 */
/*0090*/ IMAD R5, R2, c[0x0][0xc], R5 ; /* 0x0000030002057a24 */
/* 0x000fe400078e0205 */
/*00a0*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x004fc800078e0203 */
/*00b0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0207 */
/*00c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPi
.globl _Z6kernelPi
.p2align 8
.type _Z6kernelPi,@function
_Z6kernelPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b32 s3, s[0:1], 0x8
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v2, s3, s[14:15]
v_mad_u64_u32 v[1:2], null, v3, s2, v[0:1]
s_mul_i32 s2, s3, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_add_i32 s2, s2, s14
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, s2
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPi, .Lfunc_end0-_Z6kernelPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ff563_00000000-6_two_d_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z6kernelPiPi
.type _Z25__device_stub__Z6kernelPiPi, @function
_Z25__device_stub__Z6kernelPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z25__device_stub__Z6kernelPiPi, .-_Z25__device_stub__Z6kernelPiPi
.globl _Z6kernelPi
.type _Z6kernelPi, @function
_Z6kernelPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z6kernelPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6kernelPi, .-_Z6kernelPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%2d "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
movl $1024, %edi
call malloc@PLT
movq %rax, %r15
leaq 8(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
movl $4, 28(%rsp)
movl $4, 32(%rsp)
movl $4, 16(%rsp)
movl $4, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L12:
movl $2, %ecx
movl $1024, %edx
movq 8(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
leaq 64(%r15), %rbp
leaq 1088(%r15), %r14
leaq .LC0(%rip), %r12
leaq .LC1(%rip), %r13
.L13:
leaq -64(%rbp), %rbx
.L14:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L14
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $64, %rbp
cmpq %r14, %rbp
jne .L13
movq %r15, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z25__device_stub__Z6kernelPiPi
jmp .L12
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z6kernelPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "two_d_kernel.hip"
.globl _Z21__device_stub__kernelPi # -- Begin function _Z21__device_stub__kernelPi
.p2align 4, 0x90
.type _Z21__device_stub__kernelPi,@function
_Z21__device_stub__kernelPi: # @_Z21__device_stub__kernelPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z6kernelPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPi, .Lfunc_end0-_Z21__device_stub__kernelPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $88, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq $0, 8(%rsp)
movl $1024, %edi # imm = 0x400
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movabsq $17179869188, %rdi # imm = 0x400000004
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z6kernelPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq %rbx, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_3: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_3 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r12,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $16, %r12
jne .LBB1_4
# %bb.5: # in Loop: Header=BB1_3 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addq $64, %r14
cmpq $16, %r15
jne .LBB1_3
# %bb.6:
movq %rbx, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPi,@object # @_Z6kernelPi
.section .rodata,"a",@progbits
.globl _Z6kernelPi
.p2align 3, 0x0
_Z6kernelPi:
.quad _Z21__device_stub__kernelPi
.size _Z6kernelPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%2d "
.size .L.str, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPi"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /****************************************************************************
*
* cuda-hello1.cu - Hello world with CUDA (with dummy device code)
*
* Written in 2017 by Moreno Marzolla <moreno.marzolla(at)unibo.it>
*
* To the extent possible under law, the author(s) have dedicated all
* copyright and related and neighboring rights to this software to the
* public domain worldwide. This software is distributed without any warranty.
*
* You should have received a copy of the CC0 Public Domain Dedication
* along with this software. If not, see
* <http://creativecommons.org/publicdomain/zero/1.0/>.
*
* ---------------------------------------------------------------------------
*
* Based on the example shown in the CUDA toolkit documentation
* http://docs.nvidia.com/cuda/cuda-c-programming-guide/
*
* Compile with:
* nvcc cuda-hello1.cu -o cuda-hello1
*
* Run with:
* ./cuda-hello1
*
****************************************************************************/
#include <stdio.h>
__global__ void mykernel( void ) { }
int main( void )
{
mykernel<<<1,1>>>( );
printf("Hello, world!\n");
return 0;
} | code for sm_80
Function : _Z8mykernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /****************************************************************************
*
* cuda-hello1.cu - Hello world with CUDA (with dummy device code)
*
* Written in 2017 by Moreno Marzolla <moreno.marzolla(at)unibo.it>
*
* To the extent possible under law, the author(s) have dedicated all
* copyright and related and neighboring rights to this software to the
* public domain worldwide. This software is distributed without any warranty.
*
* You should have received a copy of the CC0 Public Domain Dedication
* along with this software. If not, see
* <http://creativecommons.org/publicdomain/zero/1.0/>.
*
* ---------------------------------------------------------------------------
*
* Based on the example shown in the CUDA toolkit documentation
* http://docs.nvidia.com/cuda/cuda-c-programming-guide/
*
* Compile with:
* nvcc cuda-hello1.cu -o cuda-hello1
*
* Run with:
* ./cuda-hello1
*
****************************************************************************/
#include <stdio.h>
__global__ void mykernel( void ) { }
int main( void )
{
mykernel<<<1,1>>>( );
printf("Hello, world!\n");
return 0;
} | .file "tmpxft_0010205b_00000000-6_cuda-hello1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z8mykernelvv
.type _Z26__device_stub__Z8mykernelvv, @function
_Z26__device_stub__Z8mykernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z8mykernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z8mykernelvv, .-_Z26__device_stub__Z8mykernelvv
.globl _Z8mykernelv
.type _Z8mykernelv, @function
_Z8mykernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z8mykernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8mykernelv, .-_Z8mykernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello, world!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z26__device_stub__Z8mykernelvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z8mykernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z8mykernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /****************************************************************************
*
* cuda-hello1.cu - Hello world with CUDA (with dummy device code)
*
* Written in 2017 by Moreno Marzolla <moreno.marzolla(at)unibo.it>
*
* To the extent possible under law, the author(s) have dedicated all
* copyright and related and neighboring rights to this software to the
* public domain worldwide. This software is distributed without any warranty.
*
* You should have received a copy of the CC0 Public Domain Dedication
* along with this software. If not, see
* <http://creativecommons.org/publicdomain/zero/1.0/>.
*
* ---------------------------------------------------------------------------
*
* Based on the example shown in the CUDA toolkit documentation
* http://docs.nvidia.com/cuda/cuda-c-programming-guide/
*
* Compile with:
* nvcc cuda-hello1.cu -o cuda-hello1
*
* Run with:
* ./cuda-hello1
*
****************************************************************************/
#include <stdio.h>
__global__ void mykernel( void ) { }
int main( void )
{
mykernel<<<1,1>>>( );
printf("Hello, world!\n");
return 0;
} | /****************************************************************************
*
* cuda-hello1.cu - Hello world with CUDA (with dummy device code)
*
* Written in 2017 by Moreno Marzolla <moreno.marzolla(at)unibo.it>
*
* To the extent possible under law, the author(s) have dedicated all
* copyright and related and neighboring rights to this software to the
* public domain worldwide. This software is distributed without any warranty.
*
* You should have received a copy of the CC0 Public Domain Dedication
* along with this software. If not, see
* <http://creativecommons.org/publicdomain/zero/1.0/>.
*
* ---------------------------------------------------------------------------
*
* Based on the example shown in the CUDA toolkit documentation
* http://docs.nvidia.com/cuda/cuda-c-programming-guide/
*
* Compile with:
* nvcc cuda-hello1.cu -o cuda-hello1
*
* Run with:
* ./cuda-hello1
*
****************************************************************************/
#include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void mykernel( void ) { }
int main( void )
{
mykernel<<<1,1>>>( );
printf("Hello, world!\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /****************************************************************************
*
* cuda-hello1.cu - Hello world with CUDA (with dummy device code)
*
* Written in 2017 by Moreno Marzolla <moreno.marzolla(at)unibo.it>
*
* To the extent possible under law, the author(s) have dedicated all
* copyright and related and neighboring rights to this software to the
* public domain worldwide. This software is distributed without any warranty.
*
* You should have received a copy of the CC0 Public Domain Dedication
* along with this software. If not, see
* <http://creativecommons.org/publicdomain/zero/1.0/>.
*
* ---------------------------------------------------------------------------
*
* Based on the example shown in the CUDA toolkit documentation
* http://docs.nvidia.com/cuda/cuda-c-programming-guide/
*
* Compile with:
* nvcc cuda-hello1.cu -o cuda-hello1
*
* Run with:
* ./cuda-hello1
*
****************************************************************************/
#include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void mykernel( void ) { }
int main( void )
{
mykernel<<<1,1>>>( );
printf("Hello, world!\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8mykernelv
.globl _Z8mykernelv
.p2align 8
.type _Z8mykernelv,@function
_Z8mykernelv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8mykernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8mykernelv, .Lfunc_end0-_Z8mykernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8mykernelv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z8mykernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /****************************************************************************
*
* cuda-hello1.cu - Hello world with CUDA (with dummy device code)
*
* Written in 2017 by Moreno Marzolla <moreno.marzolla(at)unibo.it>
*
* To the extent possible under law, the author(s) have dedicated all
* copyright and related and neighboring rights to this software to the
* public domain worldwide. This software is distributed without any warranty.
*
* You should have received a copy of the CC0 Public Domain Dedication
* along with this software. If not, see
* <http://creativecommons.org/publicdomain/zero/1.0/>.
*
* ---------------------------------------------------------------------------
*
* Based on the example shown in the CUDA toolkit documentation
* http://docs.nvidia.com/cuda/cuda-c-programming-guide/
*
* Compile with:
* nvcc cuda-hello1.cu -o cuda-hello1
*
* Run with:
* ./cuda-hello1
*
****************************************************************************/
#include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void mykernel( void ) { }
int main( void )
{
mykernel<<<1,1>>>( );
printf("Hello, world!\n");
return 0;
} | .text
.file "cuda-hello1.hip"
.globl _Z23__device_stub__mykernelv # -- Begin function _Z23__device_stub__mykernelv
.p2align 4, 0x90
.type _Z23__device_stub__mykernelv,@function
_Z23__device_stub__mykernelv: # @_Z23__device_stub__mykernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8mykernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z23__device_stub__mykernelv, .Lfunc_end0-_Z23__device_stub__mykernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8mykernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8mykernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8mykernelv,@object # @_Z8mykernelv
.section .rodata,"a",@progbits
.globl _Z8mykernelv
.p2align 3, 0x0
_Z8mykernelv:
.quad _Z23__device_stub__mykernelv
.size _Z8mykernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8mykernelv"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello, world!"
.size .Lstr, 14
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__mykernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8mykernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8mykernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8mykernelv
.globl _Z8mykernelv
.p2align 8
.type _Z8mykernelv,@function
_Z8mykernelv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8mykernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8mykernelv, .Lfunc_end0-_Z8mykernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8mykernelv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z8mykernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010205b_00000000-6_cuda-hello1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z8mykernelvv
.type _Z26__device_stub__Z8mykernelvv, @function
_Z26__device_stub__Z8mykernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z8mykernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z8mykernelvv, .-_Z26__device_stub__Z8mykernelvv
.globl _Z8mykernelv
.type _Z8mykernelv, @function
_Z8mykernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z8mykernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8mykernelv, .-_Z8mykernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello, world!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z26__device_stub__Z8mykernelvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z8mykernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z8mykernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda-hello1.hip"
.globl _Z23__device_stub__mykernelv # -- Begin function _Z23__device_stub__mykernelv
.p2align 4, 0x90
.type _Z23__device_stub__mykernelv,@function
_Z23__device_stub__mykernelv: # @_Z23__device_stub__mykernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8mykernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z23__device_stub__mykernelv, .Lfunc_end0-_Z23__device_stub__mykernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8mykernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8mykernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8mykernelv,@object # @_Z8mykernelv
.section .rodata,"a",@progbits
.globl _Z8mykernelv
.p2align 3, 0x0
_Z8mykernelv:
.quad _Z23__device_stub__mykernelv
.size _Z8mykernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8mykernelv"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello, world!"
.size .Lstr, 14
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__mykernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8mykernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
*
* Authors: Steven Faulkner, Blaine Oakley, Felipe Gutierrez
*
* Final Project for CIS 4930, Implementation of K-means clustering
* optimized with shared memory and reduction methods.
*
* To compile nvcc kmeans.cu
* To run ./a.out "input.txt" "K" "iterations"
*
* @data file: is the specified input file
* @k: is the number of centroids tro be determined
* @iterations: total number of iterations to be performed
*
*/
#include<cuda_runtime.h>
#include <cstdlib>
#include <ctime>
#include <algorithm>
#include <fstream>
#include <iostream>
#include <sstream>
#include <vector>
#include <string>
void ErrorCheck( cudaError_t err, const char op[]){
/*
* @cudaError_t err: cuda api call catcher.
* * all cuda api's usually return
* cudaSuccess
* @const char op[]: error string will tell where api call
* failed
*
* Error Catch Function, will wrap all malloc, memset and
* memcopy calls
*
*/
if( err != cudaSuccess )
{
printf("CUDA Error: %s, %s ", op, cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
}
struct Point {
/*
*
* Struct for the imported data points
*
* Follows CADRe stanadards, moved cuadaMalloc and cudaFree
* to the constructors, destrucor. Just makes the code look
* a little cleaner
*
*
* @double x: x data point
* @double y: y data point
* @int size: size ofdata point
* @int bytes: # of bytes allocated for storage
*/
Point(long dataSize) : dataSize(dataSize), num_of_bytes(dataSize * sizeof(double)) {
ErrorCheck(cudaMalloc(&x, num_of_bytes),"Allocate x data\n");
ErrorCheck(cudaMalloc(&y, num_of_bytes), "Allocate y data\n");
ErrorCheck(cudaMemset(x, 0, num_of_bytes), "Set x data to '0'\n");
ErrorCheck(cudaMemset(y, 0, num_of_bytes), "Set y data to '0'\n");
}
Point(long dataSize, std::vector<double>& x_data, std::vector<double>& y_data) : dataSize(dataSize), num_of_bytes(dataSize * sizeof(double)) {
ErrorCheck(cudaMalloc(&x, num_of_bytes),"Allocate x array\n");
ErrorCheck(cudaMalloc(&y, num_of_bytes), "Allocate y array\n");;
ErrorCheck(cudaMemcpy(x, x_data.data(), num_of_bytes, cudaMemcpyHostToDevice),"Copy x array to device\n");
ErrorCheck(cudaMemcpy(y, y_data.data(), num_of_bytes, cudaMemcpyHostToDevice), "Copy y array to device\n");
}
~Point() {
ErrorCheck(cudaFree(x),"Freeing x \n");
ErrorCheck(cudaFree(y),"Freeing y \n");
}
double* x;
double* y;
long dataSize;
int num_of_bytes;
};
__device__ double
euclidean_distance(double x_1, double y_1, double x_2, double y_2) {
/*
*
* @double x_1, y_1, x_2, y_2: x and y coordinates from Point struct
*
*
* Standard Euclidean Distance function returns a straight line distance
* Point A to Point B.
*
* //If I Have Time\\
* We can exapnd this for higher dimensional data(add more x_n - x_m) or preprocess our data
* with PCA(prinicpal component analysis) to reduce to 2 dimensions
*
*/
return sqrt((x_1 - x_2) * (x_1 - x_2) + (y_1 - y_2) * (y_1 - y_2));
}
__global__ void
Assignment(double * data_x, double * data_y, int data_size, double * centroids_x, double * centroids_y, double * device_new_x, double * device_new_y, int k, int * device_counts) {
/*
*
* @double* data_x: array of x data points
* @double* data_y: array of y data points
* @int data_size: size of data array
* @centroid_x: array of x centroids
* @centroid_y: array of y centroids
* @device_new_x: updated array for x
* @device_new_y: updated array for y
* @int k: # of centroids
* @int* device_counts: int array, holds count
* for total points among all centodsi
*
* K-Means Algorithm : each x,y cluster is assigned to its closest centroid
* then each centroid is averaged over all the points
* assigned to it and then updated with this new value
*/
extern __shared__ double shared_mem[];
int reg = threadIdx.x;
int unique_index = blockIdx.x * blockDim.x + threadIdx.x;
//out of range
if (unique_index >= data_size) return;
//loading in centroids
if (reg < k) {
//1D array seperated by K values for each point
shared_mem[reg] = centroids_x[reg];
shared_mem[k + reg] = centroids_y[reg];
}
__syncthreads();
// load to registers
double x_value = data_x[unique_index];
double y_value = data_y[unique_index];
//none of our distance values will be large enough to use stl::infinity or FLT_MAX,
// arbitrary sentinal values will suffice for these two variables
double min_distance = 1000;
int best_cluster = -1;
//iterate over the all centroids keeping track of closest one for storage
for (int cluster = 0; cluster < k; ++cluster) {
double distance = euclidean_distance(x_value, y_value, shared_mem[cluster], shared_mem[k + cluster]);
if (distance < min_distance) {
min_distance = distance;
best_cluster = cluster;
}
}
__syncthreads();
// tree-reduction start
int x = reg;
int y = reg + blockDim.x;
int count = reg + blockDim.x + blockDim.x;
//check if thread is assigned to centroid, writing to local memory if true or 0 if false
for (int cluster = 0; cluster < k; ++cluster) {
shared_mem[x] = (best_cluster == cluster) ? x_value : 0;
shared_mem[y] = (best_cluster == cluster) ? y_value : 0;
shared_mem[count] = (best_cluster == cluster) ? 1 : 0;
__syncthreads();
// Reduction for local memory.
for (int stride = blockDim.x / 2; stride > 0; stride /= 2) {
if (reg < stride) {
shared_mem[x] += shared_mem[x + stride];
shared_mem[y] += shared_mem[y + stride];
shared_mem[count] += shared_mem[count + stride];
}
__syncthreads();
}
//push_back from shared mem to update array
if (reg == 0) {
int cluster_index = blockIdx.x * k + cluster;
device_new_x[cluster_index] = shared_mem[x];
device_new_y[cluster_index] = shared_mem[y];
device_counts[cluster_index] = shared_mem[count];
}
__syncthreads();
}
}
__global__ void
centroid_recompute(double * centroids_x, double * centroids_y, double * device_new_x, double * device_new_y, int k, int * device_counts) {
/*
*
*
* @double * centroids_x: array for x centroids
* @double * centroids_y: array for y centroids
* @double * new_sums_x: updated x array
* @double * new_sums_y: updated y array
* @int k: # of centroids
* @int * device_counts: int array,holds count
* for total points among all centodsi
*
*
*
* centroid Recompute: Recomputes the centroids from all
* points assigned to it.
*
*
*/
//local memory declaration
extern __shared__ double shared_mem[];
int reg = threadIdx.x;
int b_Dim = blockDim.x;
//load into local memory
shared_mem[reg] = device_new_x[reg];
shared_mem[b_Dim + reg] = device_new_y[reg];
__syncthreads();
//summination of every stride length block
for (int stride = blockDim.x / 2; stride >= k; stride /= 2) {
if (reg < stride) {
shared_mem[reg] += shared_mem[reg + stride];
shared_mem[b_Dim + reg] += shared_mem[b_Dim + reg + stride];
}
__syncthreads();
}
//recomputing centroid centers
if (reg < k) {
int count = max(1, device_counts[reg]);
centroids_x[reg] = device_new_x[reg] / count;
centroids_y[reg] = device_new_y[reg] / count;
device_new_y[reg] = 0;
device_new_x[reg] = 0;
device_counts[reg] = 0;
}
}
int main(int argc, const char * argv[]) {
if (argc < 4) {
std::cout << "Incorrect startup execution: <./a.out 'input.txt' 'K' 'iterations' " << std::endl;
std::exit(EXIT_FAILURE);
}
int k = std::atoi(argv[2]);
int number_of_iterations = std::atoi(argv[3]);
std::vector<double> x_data;
std::vector<double> y_data;
std::ifstream stream_in(argv[1]);
std::string line;
if(stream_in){
while (std::getline(stream_in, line)) {
std::istringstream line_stream(line);
double x, y;
line_stream >> x >> y;
x_data.push_back(x);
y_data.push_back(y);
}
}
else{
std::cout << "Error Opening File" << std::endl;
return(EXIT_FAILURE);
}
// dinput data up to 1,000,000 points
long number_of_elements = x_data.size();
// centroids are initalized to first k points of array
// in order to chose 'randomly' we shuffle the array
// input array after we initilize the devize point array
// and before we initilize the centroid array
Point device_data(number_of_elements, x_data, y_data);
std::srand(std::time(0));
random_shuffle(x_data.begin(),x_data.end());
random_shuffle(y_data.begin(),y_data.end());
Point device_centroids(k, x_data, y_data);
int threads = 1024;
int blocks = (number_of_elements + threads - 1) / threads;
std::cout << "\nProcessing " << number_of_elements << " points\n" << std::endl;
int kmeans_shared_memory = 3 * threads * sizeof(double);
int centroid_reduction_memory = 2 * k * blocks * sizeof(double);
Point device_sum(k * blocks);
int * device_count;
ErrorCheck(cudaMalloc(&device_count, k * blocks * sizeof(int)), "Allocate size for device_count\n");
ErrorCheck(cudaMemset(device_count, 0, k * blocks * sizeof(int)),"Set device_count to '0' \n");
// cuda api time start
cudaEvent_t start,stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start,0);
// start iteration loop, assigning and updating centroid on each iteration
for (size_t iteration = 0; iteration < number_of_iterations; ++iteration) {
Assignment<<<blocks, threads, kmeans_shared_memory>>>(device_data.x,device_data.y, device_data.dataSize, device_centroids.x, device_centroids.y, device_sum.x, device_sum.y, k,
device_count);
cudaDeviceSynchronize();
centroid_recompute<<<1, k * blocks, centroid_reduction_memory>>>(device_centroids.x, device_centroids.y, device_sum.x, device_sum.y, k, device_count);
cudaDeviceSynchronize();
}
// cuda api time stop
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
float elapsedTime;
cudaEventElapsedTime(&elapsedTime,start,stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
std::string unit = "";
unit = (elapsedTime > 999) ? "seconds" : "milliseconds";
elapsedTime = (elapsedTime > 999 ) ? elapsedTime/1000 : elapsedTime;
std::cout << "Elapsed time of kernal calls: " << elapsedTime << " " << unit << "\n" << std::endl;
ErrorCheck(cudaFree(device_count),"Freeing Device Memory");
std::vector<double> centroid_x(k, 0);
std::vector<double> centroid_y(k, 0);
ErrorCheck(cudaMemcpy(centroid_x.data(), device_centroids.x, device_centroids.num_of_bytes, cudaMemcpyDeviceToHost), "Moving Array back to host\n");
ErrorCheck(cudaMemcpy(centroid_y.data(), device_centroids.y, device_centroids.num_of_bytes, cudaMemcpyDeviceToHost), "Moving Array back to host\n");
std::cout << "centroids:" << std::endl;
for (size_t cluster = 0; cluster < k; ++cluster) {
std::cout << centroid_x[cluster] << " " << centroid_y[cluster] << std::endl;
}
std::cout << "\n" << std::endl;
return(EXIT_SUCCESS);
} | /*
*
* Authors: Steven Faulkner, Blaine Oakley, Felipe Gutierrez
*
* Final Project for CIS 4930, Implementation of K-means clustering
* optimized with shared memory and reduction methods.
*
* To compile nvcc kmeans.cu
* To run ./a.out "input.txt" "K" "iterations"
*
* @data file: is the specified input file
* @k: is the number of centroids tro be determined
* @iterations: total number of iterations to be performed
*
*/
#include<hip/hip_runtime.h>
#include <cstdlib>
#include <ctime>
#include <algorithm>
#include <fstream>
#include <iostream>
#include <sstream>
#include <vector>
#include <string>
void ErrorCheck( hipError_t err, const char op[]){
/*
* @cudaError_t err: cuda api call catcher.
* * all cuda api's usually return
* cudaSuccess
* @const char op[]: error string will tell where api call
* failed
*
* Error Catch Function, will wrap all malloc, memset and
* memcopy calls
*
*/
if( err != hipSuccess )
{
printf("CUDA Error: %s, %s ", op, hipGetErrorString(err));
exit(EXIT_FAILURE);
}
}
struct Point {
/*
*
* Struct for the imported data points
*
* Follows CADRe stanadards, moved cuadaMalloc and cudaFree
* to the constructors, destrucor. Just makes the code look
* a little cleaner
*
*
* @double x: x data point
* @double y: y data point
* @int size: size ofdata point
* @int bytes: # of bytes allocated for storage
*/
Point(long dataSize) : dataSize(dataSize), num_of_bytes(dataSize * sizeof(double)) {
ErrorCheck(hipMalloc(&x, num_of_bytes),"Allocate x data\n");
ErrorCheck(hipMalloc(&y, num_of_bytes), "Allocate y data\n");
ErrorCheck(hipMemset(x, 0, num_of_bytes), "Set x data to '0'\n");
ErrorCheck(hipMemset(y, 0, num_of_bytes), "Set y data to '0'\n");
}
Point(long dataSize, std::vector<double>& x_data, std::vector<double>& y_data) : dataSize(dataSize), num_of_bytes(dataSize * sizeof(double)) {
ErrorCheck(hipMalloc(&x, num_of_bytes),"Allocate x array\n");
ErrorCheck(hipMalloc(&y, num_of_bytes), "Allocate y array\n");;
ErrorCheck(hipMemcpy(x, x_data.data(), num_of_bytes, hipMemcpyHostToDevice),"Copy x array to device\n");
ErrorCheck(hipMemcpy(y, y_data.data(), num_of_bytes, hipMemcpyHostToDevice), "Copy y array to device\n");
}
~Point() {
ErrorCheck(hipFree(x),"Freeing x \n");
ErrorCheck(hipFree(y),"Freeing y \n");
}
double* x;
double* y;
long dataSize;
int num_of_bytes;
};
__device__ double
euclidean_distance(double x_1, double y_1, double x_2, double y_2) {
/*
*
* @double x_1, y_1, x_2, y_2: x and y coordinates from Point struct
*
*
* Standard Euclidean Distance function returns a straight line distance
* Point A to Point B.
*
* //If I Have Time\\
* We can exapnd this for higher dimensional data(add more x_n - x_m) or preprocess our data
* with PCA(prinicpal component analysis) to reduce to 2 dimensions
*
*/
return sqrt((x_1 - x_2) * (x_1 - x_2) + (y_1 - y_2) * (y_1 - y_2));
}
__global__ void
Assignment(double * data_x, double * data_y, int data_size, double * centroids_x, double * centroids_y, double * device_new_x, double * device_new_y, int k, int * device_counts) {
/*
*
* @double* data_x: array of x data points
* @double* data_y: array of y data points
* @int data_size: size of data array
* @centroid_x: array of x centroids
* @centroid_y: array of y centroids
* @device_new_x: updated array for x
* @device_new_y: updated array for y
* @int k: # of centroids
* @int* device_counts: int array, holds count
* for total points among all centodsi
*
* K-Means Algorithm : each x,y cluster is assigned to its closest centroid
* then each centroid is averaged over all the points
* assigned to it and then updated with this new value
*/
extern __shared__ double shared_mem[];
int reg = threadIdx.x;
int unique_index = blockIdx.x * blockDim.x + threadIdx.x;
//out of range
if (unique_index >= data_size) return;
//loading in centroids
if (reg < k) {
//1D array seperated by K values for each point
shared_mem[reg] = centroids_x[reg];
shared_mem[k + reg] = centroids_y[reg];
}
__syncthreads();
// load to registers
double x_value = data_x[unique_index];
double y_value = data_y[unique_index];
//none of our distance values will be large enough to use stl::infinity or FLT_MAX,
// arbitrary sentinal values will suffice for these two variables
double min_distance = 1000;
int best_cluster = -1;
//iterate over the all centroids keeping track of closest one for storage
for (int cluster = 0; cluster < k; ++cluster) {
double distance = euclidean_distance(x_value, y_value, shared_mem[cluster], shared_mem[k + cluster]);
if (distance < min_distance) {
min_distance = distance;
best_cluster = cluster;
}
}
__syncthreads();
// tree-reduction start
int x = reg;
int y = reg + blockDim.x;
int count = reg + blockDim.x + blockDim.x;
//check if thread is assigned to centroid, writing to local memory if true or 0 if false
for (int cluster = 0; cluster < k; ++cluster) {
shared_mem[x] = (best_cluster == cluster) ? x_value : 0;
shared_mem[y] = (best_cluster == cluster) ? y_value : 0;
shared_mem[count] = (best_cluster == cluster) ? 1 : 0;
__syncthreads();
// Reduction for local memory.
for (int stride = blockDim.x / 2; stride > 0; stride /= 2) {
if (reg < stride) {
shared_mem[x] += shared_mem[x + stride];
shared_mem[y] += shared_mem[y + stride];
shared_mem[count] += shared_mem[count + stride];
}
__syncthreads();
}
//push_back from shared mem to update array
if (reg == 0) {
int cluster_index = blockIdx.x * k + cluster;
device_new_x[cluster_index] = shared_mem[x];
device_new_y[cluster_index] = shared_mem[y];
device_counts[cluster_index] = shared_mem[count];
}
__syncthreads();
}
}
__global__ void
centroid_recompute(double * centroids_x, double * centroids_y, double * device_new_x, double * device_new_y, int k, int * device_counts) {
/*
*
*
* @double * centroids_x: array for x centroids
* @double * centroids_y: array for y centroids
* @double * new_sums_x: updated x array
* @double * new_sums_y: updated y array
* @int k: # of centroids
* @int * device_counts: int array,holds count
* for total points among all centodsi
*
*
*
* centroid Recompute: Recomputes the centroids from all
* points assigned to it.
*
*
*/
//local memory declaration
extern __shared__ double shared_mem[];
int reg = threadIdx.x;
int b_Dim = blockDim.x;
//load into local memory
shared_mem[reg] = device_new_x[reg];
shared_mem[b_Dim + reg] = device_new_y[reg];
__syncthreads();
//summination of every stride length block
for (int stride = blockDim.x / 2; stride >= k; stride /= 2) {
if (reg < stride) {
shared_mem[reg] += shared_mem[reg + stride];
shared_mem[b_Dim + reg] += shared_mem[b_Dim + reg + stride];
}
__syncthreads();
}
//recomputing centroid centers
if (reg < k) {
int count = max(1, device_counts[reg]);
centroids_x[reg] = device_new_x[reg] / count;
centroids_y[reg] = device_new_y[reg] / count;
device_new_y[reg] = 0;
device_new_x[reg] = 0;
device_counts[reg] = 0;
}
}
int main(int argc, const char * argv[]) {
if (argc < 4) {
std::cout << "Incorrect startup execution: <./a.out 'input.txt' 'K' 'iterations' " << std::endl;
std::exit(EXIT_FAILURE);
}
int k = std::atoi(argv[2]);
int number_of_iterations = std::atoi(argv[3]);
std::vector<double> x_data;
std::vector<double> y_data;
std::ifstream stream_in(argv[1]);
std::string line;
if(stream_in){
while (std::getline(stream_in, line)) {
std::istringstream line_stream(line);
double x, y;
line_stream >> x >> y;
x_data.push_back(x);
y_data.push_back(y);
}
}
else{
std::cout << "Error Opening File" << std::endl;
return(EXIT_FAILURE);
}
// dinput data up to 1,000,000 points
long number_of_elements = x_data.size();
// centroids are initalized to first k points of array
// in order to chose 'randomly' we shuffle the array
// input array after we initilize the devize point array
// and before we initilize the centroid array
Point device_data(number_of_elements, x_data, y_data);
std::srand(std::time(0));
random_shuffle(x_data.begin(),x_data.end());
random_shuffle(y_data.begin(),y_data.end());
Point device_centroids(k, x_data, y_data);
int threads = 1024;
int blocks = (number_of_elements + threads - 1) / threads;
std::cout << "\nProcessing " << number_of_elements << " points\n" << std::endl;
int kmeans_shared_memory = 3 * threads * sizeof(double);
int centroid_reduction_memory = 2 * k * blocks * sizeof(double);
Point device_sum(k * blocks);
int * device_count;
ErrorCheck(hipMalloc(&device_count, k * blocks * sizeof(int)), "Allocate size for device_count\n");
ErrorCheck(hipMemset(device_count, 0, k * blocks * sizeof(int)),"Set device_count to '0' \n");
// cuda api time start
hipEvent_t start,stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start,0);
// start iteration loop, assigning and updating centroid on each iteration
for (size_t iteration = 0; iteration < number_of_iterations; ++iteration) {
Assignment<<<blocks, threads, kmeans_shared_memory>>>(device_data.x,device_data.y, device_data.dataSize, device_centroids.x, device_centroids.y, device_sum.x, device_sum.y, k,
device_count);
hipDeviceSynchronize();
centroid_recompute<<<1, k * blocks, centroid_reduction_memory>>>(device_centroids.x, device_centroids.y, device_sum.x, device_sum.y, k, device_count);
hipDeviceSynchronize();
}
// cuda api time stop
hipEventRecord(stop,0);
hipEventSynchronize(stop);
float elapsedTime;
hipEventElapsedTime(&elapsedTime,start,stop);
hipEventDestroy(start);
hipEventDestroy(stop);
std::string unit = "";
unit = (elapsedTime > 999) ? "seconds" : "milliseconds";
elapsedTime = (elapsedTime > 999 ) ? elapsedTime/1000 : elapsedTime;
std::cout << "Elapsed time of kernal calls: " << elapsedTime << " " << unit << "\n" << std::endl;
ErrorCheck(hipFree(device_count),"Freeing Device Memory");
std::vector<double> centroid_x(k, 0);
std::vector<double> centroid_y(k, 0);
ErrorCheck(hipMemcpy(centroid_x.data(), device_centroids.x, device_centroids.num_of_bytes, hipMemcpyDeviceToHost), "Moving Array back to host\n");
ErrorCheck(hipMemcpy(centroid_y.data(), device_centroids.y, device_centroids.num_of_bytes, hipMemcpyDeviceToHost), "Moving Array back to host\n");
std::cout << "centroids:" << std::endl;
for (size_t cluster = 0; cluster < k; ++cluster) {
std::cout << centroid_x[cluster] << " " << centroid_y[cluster] << std::endl;
}
std::cout << "\n" << std::endl;
return(EXIT_SUCCESS);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
*
* Authors: Steven Faulkner, Blaine Oakley, Felipe Gutierrez
*
* Final Project for CIS 4930, Implementation of K-means clustering
* optimized with shared memory and reduction methods.
*
* To compile nvcc kmeans.cu
* To run ./a.out "input.txt" "K" "iterations"
*
* @data file: is the specified input file
* @k: is the number of centroids tro be determined
* @iterations: total number of iterations to be performed
*
*/
#include<hip/hip_runtime.h>
#include <cstdlib>
#include <ctime>
#include <algorithm>
#include <fstream>
#include <iostream>
#include <sstream>
#include <vector>
#include <string>
void ErrorCheck( hipError_t err, const char op[]){
/*
* @cudaError_t err: cuda api call catcher.
* * all cuda api's usually return
* cudaSuccess
* @const char op[]: error string will tell where api call
* failed
*
* Error Catch Function, will wrap all malloc, memset and
* memcopy calls
*
*/
if( err != hipSuccess )
{
printf("CUDA Error: %s, %s ", op, hipGetErrorString(err));
exit(EXIT_FAILURE);
}
}
struct Point {
/*
*
* Struct for the imported data points
*
* Follows CADRe stanadards, moved cuadaMalloc and cudaFree
* to the constructors, destrucor. Just makes the code look
* a little cleaner
*
*
* @double x: x data point
* @double y: y data point
* @int size: size ofdata point
* @int bytes: # of bytes allocated for storage
*/
Point(long dataSize) : dataSize(dataSize), num_of_bytes(dataSize * sizeof(double)) {
ErrorCheck(hipMalloc(&x, num_of_bytes),"Allocate x data\n");
ErrorCheck(hipMalloc(&y, num_of_bytes), "Allocate y data\n");
ErrorCheck(hipMemset(x, 0, num_of_bytes), "Set x data to '0'\n");
ErrorCheck(hipMemset(y, 0, num_of_bytes), "Set y data to '0'\n");
}
Point(long dataSize, std::vector<double>& x_data, std::vector<double>& y_data) : dataSize(dataSize), num_of_bytes(dataSize * sizeof(double)) {
ErrorCheck(hipMalloc(&x, num_of_bytes),"Allocate x array\n");
ErrorCheck(hipMalloc(&y, num_of_bytes), "Allocate y array\n");;
ErrorCheck(hipMemcpy(x, x_data.data(), num_of_bytes, hipMemcpyHostToDevice),"Copy x array to device\n");
ErrorCheck(hipMemcpy(y, y_data.data(), num_of_bytes, hipMemcpyHostToDevice), "Copy y array to device\n");
}
~Point() {
ErrorCheck(hipFree(x),"Freeing x \n");
ErrorCheck(hipFree(y),"Freeing y \n");
}
double* x;
double* y;
long dataSize;
int num_of_bytes;
};
__device__ double
euclidean_distance(double x_1, double y_1, double x_2, double y_2) {
/*
*
* @double x_1, y_1, x_2, y_2: x and y coordinates from Point struct
*
*
* Standard Euclidean Distance function returns a straight line distance
* Point A to Point B.
*
* //If I Have Time\\
* We can exapnd this for higher dimensional data(add more x_n - x_m) or preprocess our data
* with PCA(prinicpal component analysis) to reduce to 2 dimensions
*
*/
return sqrt((x_1 - x_2) * (x_1 - x_2) + (y_1 - y_2) * (y_1 - y_2));
}
__global__ void
Assignment(double * data_x, double * data_y, int data_size, double * centroids_x, double * centroids_y, double * device_new_x, double * device_new_y, int k, int * device_counts) {
/*
*
* @double* data_x: array of x data points
* @double* data_y: array of y data points
* @int data_size: size of data array
* @centroid_x: array of x centroids
* @centroid_y: array of y centroids
* @device_new_x: updated array for x
* @device_new_y: updated array for y
* @int k: # of centroids
* @int* device_counts: int array, holds count
* for total points among all centodsi
*
* K-Means Algorithm : each x,y cluster is assigned to its closest centroid
* then each centroid is averaged over all the points
* assigned to it and then updated with this new value
*/
extern __shared__ double shared_mem[];
int reg = threadIdx.x;
int unique_index = blockIdx.x * blockDim.x + threadIdx.x;
//out of range
if (unique_index >= data_size) return;
//loading in centroids
if (reg < k) {
//1D array seperated by K values for each point
shared_mem[reg] = centroids_x[reg];
shared_mem[k + reg] = centroids_y[reg];
}
__syncthreads();
// load to registers
double x_value = data_x[unique_index];
double y_value = data_y[unique_index];
//none of our distance values will be large enough to use stl::infinity or FLT_MAX,
// arbitrary sentinal values will suffice for these two variables
double min_distance = 1000;
int best_cluster = -1;
//iterate over the all centroids keeping track of closest one for storage
for (int cluster = 0; cluster < k; ++cluster) {
double distance = euclidean_distance(x_value, y_value, shared_mem[cluster], shared_mem[k + cluster]);
if (distance < min_distance) {
min_distance = distance;
best_cluster = cluster;
}
}
__syncthreads();
// tree-reduction start
int x = reg;
int y = reg + blockDim.x;
int count = reg + blockDim.x + blockDim.x;
//check if thread is assigned to centroid, writing to local memory if true or 0 if false
for (int cluster = 0; cluster < k; ++cluster) {
shared_mem[x] = (best_cluster == cluster) ? x_value : 0;
shared_mem[y] = (best_cluster == cluster) ? y_value : 0;
shared_mem[count] = (best_cluster == cluster) ? 1 : 0;
__syncthreads();
// Reduction for local memory.
for (int stride = blockDim.x / 2; stride > 0; stride /= 2) {
if (reg < stride) {
shared_mem[x] += shared_mem[x + stride];
shared_mem[y] += shared_mem[y + stride];
shared_mem[count] += shared_mem[count + stride];
}
__syncthreads();
}
//push_back from shared mem to update array
if (reg == 0) {
int cluster_index = blockIdx.x * k + cluster;
device_new_x[cluster_index] = shared_mem[x];
device_new_y[cluster_index] = shared_mem[y];
device_counts[cluster_index] = shared_mem[count];
}
__syncthreads();
}
}
__global__ void
centroid_recompute(double * centroids_x, double * centroids_y, double * device_new_x, double * device_new_y, int k, int * device_counts) {
/*
*
*
* @double * centroids_x: array for x centroids
* @double * centroids_y: array for y centroids
* @double * new_sums_x: updated x array
* @double * new_sums_y: updated y array
* @int k: # of centroids
* @int * device_counts: int array,holds count
* for total points among all centodsi
*
*
*
* centroid Recompute: Recomputes the centroids from all
* points assigned to it.
*
*
*/
//local memory declaration
extern __shared__ double shared_mem[];
int reg = threadIdx.x;
int b_Dim = blockDim.x;
//load into local memory
shared_mem[reg] = device_new_x[reg];
shared_mem[b_Dim + reg] = device_new_y[reg];
__syncthreads();
//summination of every stride length block
for (int stride = blockDim.x / 2; stride >= k; stride /= 2) {
if (reg < stride) {
shared_mem[reg] += shared_mem[reg + stride];
shared_mem[b_Dim + reg] += shared_mem[b_Dim + reg + stride];
}
__syncthreads();
}
//recomputing centroid centers
if (reg < k) {
int count = max(1, device_counts[reg]);
centroids_x[reg] = device_new_x[reg] / count;
centroids_y[reg] = device_new_y[reg] / count;
device_new_y[reg] = 0;
device_new_x[reg] = 0;
device_counts[reg] = 0;
}
}
int main(int argc, const char * argv[]) {
if (argc < 4) {
std::cout << "Incorrect startup execution: <./a.out 'input.txt' 'K' 'iterations' " << std::endl;
std::exit(EXIT_FAILURE);
}
int k = std::atoi(argv[2]);
int number_of_iterations = std::atoi(argv[3]);
std::vector<double> x_data;
std::vector<double> y_data;
std::ifstream stream_in(argv[1]);
std::string line;
if(stream_in){
while (std::getline(stream_in, line)) {
std::istringstream line_stream(line);
double x, y;
line_stream >> x >> y;
x_data.push_back(x);
y_data.push_back(y);
}
}
else{
std::cout << "Error Opening File" << std::endl;
return(EXIT_FAILURE);
}
// dinput data up to 1,000,000 points
long number_of_elements = x_data.size();
// centroids are initalized to first k points of array
// in order to chose 'randomly' we shuffle the array
// input array after we initilize the devize point array
// and before we initilize the centroid array
Point device_data(number_of_elements, x_data, y_data);
std::srand(std::time(0));
random_shuffle(x_data.begin(),x_data.end());
random_shuffle(y_data.begin(),y_data.end());
Point device_centroids(k, x_data, y_data);
int threads = 1024;
int blocks = (number_of_elements + threads - 1) / threads;
std::cout << "\nProcessing " << number_of_elements << " points\n" << std::endl;
int kmeans_shared_memory = 3 * threads * sizeof(double);
int centroid_reduction_memory = 2 * k * blocks * sizeof(double);
Point device_sum(k * blocks);
int * device_count;
ErrorCheck(hipMalloc(&device_count, k * blocks * sizeof(int)), "Allocate size for device_count\n");
ErrorCheck(hipMemset(device_count, 0, k * blocks * sizeof(int)),"Set device_count to '0' \n");
// cuda api time start
hipEvent_t start,stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start,0);
// start iteration loop, assigning and updating centroid on each iteration
for (size_t iteration = 0; iteration < number_of_iterations; ++iteration) {
Assignment<<<blocks, threads, kmeans_shared_memory>>>(device_data.x,device_data.y, device_data.dataSize, device_centroids.x, device_centroids.y, device_sum.x, device_sum.y, k,
device_count);
hipDeviceSynchronize();
centroid_recompute<<<1, k * blocks, centroid_reduction_memory>>>(device_centroids.x, device_centroids.y, device_sum.x, device_sum.y, k, device_count);
hipDeviceSynchronize();
}
// cuda api time stop
hipEventRecord(stop,0);
hipEventSynchronize(stop);
float elapsedTime;
hipEventElapsedTime(&elapsedTime,start,stop);
hipEventDestroy(start);
hipEventDestroy(stop);
std::string unit = "";
unit = (elapsedTime > 999) ? "seconds" : "milliseconds";
elapsedTime = (elapsedTime > 999 ) ? elapsedTime/1000 : elapsedTime;
std::cout << "Elapsed time of kernal calls: " << elapsedTime << " " << unit << "\n" << std::endl;
ErrorCheck(hipFree(device_count),"Freeing Device Memory");
std::vector<double> centroid_x(k, 0);
std::vector<double> centroid_y(k, 0);
ErrorCheck(hipMemcpy(centroid_x.data(), device_centroids.x, device_centroids.num_of_bytes, hipMemcpyDeviceToHost), "Moving Array back to host\n");
ErrorCheck(hipMemcpy(centroid_y.data(), device_centroids.y, device_centroids.num_of_bytes, hipMemcpyDeviceToHost), "Moving Array back to host\n");
std::cout << "centroids:" << std::endl;
for (size_t cluster = 0; cluster < k; ++cluster) {
std::cout << centroid_x[cluster] << " " << centroid_y[cluster] << std::endl;
}
std::cout << "\n" << std::endl;
return(EXIT_SUCCESS);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10AssignmentPdS_iS_S_S_S_iPi
.globl _Z10AssignmentPdS_iS_S_S_S_iPi
.p2align 8
.type _Z10AssignmentPdS_iS_S_S_S_iPi,@function
_Z10AssignmentPdS_iS_S_S_S_iPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x54
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s2, 0xffff
s_mov_b32 s2, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_16
s_load_b32 s9, s[0:1], 0x38
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s9, v0
s_cbranch_execz .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x18
v_lshlrev_b32_e32 v6, 3, v0
v_add_nc_u32_e32 v7, s9, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[2:3], v6, s[4:5]
global_load_b64 v[4:5], v6, s[6:7]
v_add_nc_u32_e32 v6, 0, v6
v_lshl_add_u32 v7, v7, 3, 0
s_waitcnt vmcnt(1)
ds_store_b64 v6, v[2:3]
s_waitcnt vmcnt(0)
ds_store_b64 v7, v[4:5]
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cmp_lt_i32 s9, 1
v_lshlrev_b64 v[1:2], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v2, vcc_lo
global_load_b64 v[1:2], v[3:4], off
global_load_b64 v[3:4], v[5:6], off
s_cbranch_scc1 .LBB0_6
v_mov_b32_e32 v5, 0
v_dual_mov_b32 v6, 0x408f4000 :: v_dual_mov_b32 v7, -1
s_lshl_b32 s2, s9, 3
s_mov_b32 s3, 0
s_mov_b32 s4, 0
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s5, s4, s2
v_mov_b32_e32 v8, s4
v_mov_b32_e32 v10, s5
s_add_i32 s4, s4, 8
ds_load_b64 v[8:9], v8
ds_load_b64 v[10:11], v10
s_waitcnt vmcnt(1) lgkmcnt(1)
v_add_f64 v[8:9], v[1:2], -v[8:9]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f64 v[10:11], v[3:4], -v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[10:11], v[10:11], v[10:11]
v_fma_f64 v[8:9], v[8:9], v[8:9], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[8:9]
v_cndmask_b32_e64 v10, 0, 1, vcc_lo
v_lshlrev_b32_e32 v10, 8, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[8:9], v[8:9], v10
v_rsq_f64_e32 v[10:11], v[8:9]
s_waitcnt_depctr 0xfff
v_mul_f64 v[12:13], v[8:9], v[10:11]
v_mul_f64 v[10:11], v[10:11], 0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], -v[10:11], v[12:13], 0.5
v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], -v[12:13], v[12:13], v[8:9]
v_fma_f64 v[12:13], v[14:15], v[10:11], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], -v[12:13], v[12:13], v[8:9]
v_fma_f64 v[10:11], v[14:15], v[10:11], v[12:13]
v_cndmask_b32_e64 v12, 0, 0xffffff80, vcc_lo
v_cmp_class_f64_e64 vcc_lo, v[8:9], 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[10:11], v[10:11], v12
v_dual_cndmask_b32 v9, v11, v9 :: v_dual_cndmask_b32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_cmp_lt_f64_e32 vcc_lo, v[8:9], v[5:6]
v_cndmask_b32_e32 v5, v5, v8, vcc_lo
v_cndmask_b32_e64 v7, v7, s3, vcc_lo
v_cndmask_b32_e32 v6, v6, v9, vcc_lo
s_add_i32 s3, s3, 1
s_cmp_eq_u32 s9, s3
s_cbranch_scc0 .LBB0_5
s_branch .LBB0_7
.LBB0_6:
v_mov_b32_e32 v7, -1
.LBB0_7:
s_cmp_lt_i32 s9, 1
s_waitcnt vmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_16
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x28
s_load_b64 s[2:3], s[0:1], 0x40
v_add_nc_u32_e32 v5, s8, v0
v_lshl_add_u32 v8, v0, 3, 0
v_cmp_eq_u32_e64 s0, 0, v0
s_cmp_gt_u32 s8, 1
s_delay_alu instid0(VALU_DEP_3)
v_dual_mov_b32 v11, 0 :: v_dual_add_nc_u32 v6, s8, v5
v_lshl_add_u32 v9, v5, 3, 0
s_cselect_b32 s1, -1, 0
s_mov_b32 s10, 0
s_mul_i32 s15, s15, s9
v_lshl_add_u32 v10, v6, 3, 0
s_branch .LBB0_10
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s11
s_add_i32 s10, s10, 1
s_waitcnt_vscnt null, 0x0
s_cmp_lg_u32 s10, s9
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_16
.LBB0_10:
v_cmp_eq_u32_e32 vcc_lo, s10, v7
s_mov_b32 s11, s8
v_dual_mov_b32 v14, 0 :: v_dual_cndmask_b32 v13, 0, v2
v_dual_cndmask_b32 v12, 0, v1 :: v_dual_cndmask_b32 v17, 0, v4
v_cndmask_b32_e32 v16, 0, v3, vcc_lo
v_cndmask_b32_e64 v15, 0, 0x3ff00000, vcc_lo
s_and_not1_b32 vcc_lo, exec_lo, s1
ds_store_b64 v8, v[12:13]
ds_store_b64 v9, v[16:17]
ds_store_b64 v10, v[14:15]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_vccz .LBB0_14
.LBB0_11:
s_and_saveexec_b32 s11, s0
s_cbranch_execz .LBB0_9
ds_load_b64 v[12:13], v10
s_add_i32 s12, s10, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s13, s12, 31
s_lshl_b64 s[16:17], s[12:13], 3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_add_u32 s18, s4, s16
s_addc_u32 s19, s5, s17
s_add_u32 s16, s6, s16
s_addc_u32 s17, s7, s17
s_lshl_b64 s[12:13], s[12:13], 2
s_add_u32 s12, s2, s12
s_addc_u32 s13, s3, s13
s_waitcnt lgkmcnt(0)
v_cvt_i32_f64_e32 v16, v[12:13]
ds_load_b64 v[12:13], v8
ds_load_b64 v[14:15], v9
s_waitcnt lgkmcnt(1)
global_store_b64 v11, v[12:13], s[18:19]
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_store_b64 v11, v[14:15], s[16:17]
global_store_b32 v11, v16, s[12:13]
s_branch .LBB0_9
.p2align 6
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s13
s_cmp_lt_u32 s11, 4
s_mov_b32 s11, s12
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_11
.LBB0_14:
s_lshr_b32 s12, s11, 1
s_mov_b32 s13, exec_lo
v_cmpx_gt_u32_e64 s12, v0
s_cbranch_execz .LBB0_13
v_add_nc_u32_e32 v12, s12, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v12, v12, 3, 0
ds_load_b64 v[12:13], v12
ds_load_b64 v[14:15], v8
s_waitcnt lgkmcnt(0)
v_add_f64 v[12:13], v[12:13], v[14:15]
v_add_nc_u32_e32 v14, s12, v5
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v14, v14, 3, 0
ds_store_b64 v8, v[12:13]
ds_load_b64 v[12:13], v14
ds_load_b64 v[14:15], v9
s_waitcnt lgkmcnt(0)
v_add_f64 v[12:13], v[12:13], v[14:15]
v_add_nc_u32_e32 v14, s12, v6
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v14, v14, 3, 0
ds_store_b64 v9, v[12:13]
ds_load_b64 v[12:13], v14
ds_load_b64 v[14:15], v10
s_waitcnt lgkmcnt(0)
v_add_f64 v[12:13], v[12:13], v[14:15]
ds_store_b64 v10, v[12:13]
s_branch .LBB0_13
.LBB0_16:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10AssignmentPdS_iS_S_S_S_iPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 328
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10AssignmentPdS_iS_S_S_S_iPi, .Lfunc_end0-_Z10AssignmentPdS_iS_S_S_S_iPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z18centroid_recomputePdS_S_S_iPi
.globl _Z18centroid_recomputePdS_S_S_iPi
.p2align 8
.type _Z18centroid_recomputePdS_S_S_iPi,@function
_Z18centroid_recomputePdS_S_S_iPi:
s_load_b128 s[4:7], s[0:1], 0x10
v_lshlrev_b32_e32 v1, 3, v0
s_clause 0x1
s_load_b32 s2, s[0:1], 0x20
s_load_b32 s3, s[0:1], 0x3c
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[5:6], v1, s[4:5]
global_load_b64 v[7:8], v1, s[6:7]
v_add_nc_u32_e32 v3, 0, v1
s_and_b32 s8, s3, 0xffff
s_bfe_u32 s3, s3, 0xf0001
v_add_nc_u32_e32 v2, s8, v0
s_cmp_lt_i32 s3, s2
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v4, v2, 3, 0
s_waitcnt vmcnt(1)
ds_store_b64 v3, v[5:6]
s_waitcnt vmcnt(0)
ds_store_b64 v4, v[7:8]
s_waitcnt lgkmcnt(0)
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_2
.p2align 6
.LBB1_1:
s_or_b32 exec_lo, exec_lo, s8
s_lshr_b32 s3, s3, 1
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s3, s2
.LBB1_2:
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_5
s_mov_b32 s8, exec_lo
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB1_1
v_add_nc_u32_e32 v5, s3, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v5, v5, 3, 0
ds_load_b64 v[5:6], v5
ds_load_b64 v[7:8], v3
s_waitcnt lgkmcnt(0)
v_add_f64 v[5:6], v[5:6], v[7:8]
v_add_nc_u32_e32 v7, s3, v2
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v7, v7, 3, 0
ds_store_b64 v3, v[5:6]
ds_load_b64 v[5:6], v7
ds_load_b64 v[7:8], v4
s_waitcnt lgkmcnt(0)
v_add_f64 v[5:6], v[5:6], v[7:8]
ds_store_b64 v4, v[5:6]
s_branch .LBB1_1
.LBB1_5:
s_set_inst_prefetch_distance 0x2
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_7
s_load_b64 s[8:9], s[0:1], 0x28
v_lshlrev_b32_e32 v16, 2, v0
v_add_co_u32 v2, s2, s4, v1
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, null, s5, 0, s2
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v17, 3, v0
v_add_co_u32 v0, s4, s6, v1
global_load_b64 v[4:5], v[2:3], off
v_add_co_ci_u32_e64 v1, null, s7, 0, s4
s_waitcnt lgkmcnt(0)
global_load_b32 v6, v16, s[8:9]
s_waitcnt vmcnt(0)
v_max_i32_e32 v6, 1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_i32_e32 v[6:7], v6
v_div_scale_f64 v[8:9], null, v[6:7], v[6:7], v[4:5]
v_div_scale_f64 v[14:15], vcc_lo, v[4:5], v[6:7], v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[10:11], v[8:9]
s_waitcnt_depctr 0xfff
v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[12:13], v[14:15], v[10:11]
v_fma_f64 v[8:9], -v[8:9], v[12:13], v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[12:13]
v_div_fixup_f64 v[4:5], v[8:9], v[6:7], v[4:5]
global_store_b64 v17, v[4:5], s[0:1]
global_load_b64 v[4:5], v[0:1], off
s_mov_b32 s0, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
s_mov_b32 s1, s0
s_waitcnt vmcnt(0)
v_div_scale_f64 v[8:9], null, v[6:7], v[6:7], v[4:5]
v_div_scale_f64 v[14:15], vcc_lo, v[4:5], v[6:7], v[4:5]
v_rcp_f64_e32 v[10:11], v[8:9]
s_waitcnt_depctr 0xfff
v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
v_mul_f64 v[12:13], v[14:15], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], -v[8:9], v[12:13], v[14:15]
v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[12:13]
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f64 v[4:5], v[8:9], v[6:7], v[4:5]
v_dual_mov_b32 v7, s1 :: v_dual_mov_b32 v6, s0
v_mov_b32_e32 v8, 0
global_store_b64 v17, v[4:5], s[2:3]
global_store_b64 v[0:1], v[6:7], off
global_store_b64 v[2:3], v[6:7], off
global_store_b32 v16, v8, s[8:9]
.LBB1_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18centroid_recomputePdS_S_S_iPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 10
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z18centroid_recomputePdS_S_S_iPi, .Lfunc_end1-_Z18centroid_recomputePdS_S_S_iPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .offset: 72
.size: 4
.value_kind: hidden_block_count_x
- .offset: 76
.size: 4
.value_kind: hidden_block_count_y
- .offset: 80
.size: 4
.value_kind: hidden_block_count_z
- .offset: 84
.size: 2
.value_kind: hidden_group_size_x
- .offset: 86
.size: 2
.value_kind: hidden_group_size_y
- .offset: 88
.size: 2
.value_kind: hidden_group_size_z
- .offset: 90
.size: 2
.value_kind: hidden_remainder_x
- .offset: 92
.size: 2
.value_kind: hidden_remainder_y
- .offset: 94
.size: 2
.value_kind: hidden_remainder_z
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 136
.size: 2
.value_kind: hidden_grid_dims
- .offset: 192
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 328
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10AssignmentPdS_iS_S_S_S_iPi
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z10AssignmentPdS_iS_S_S_S_iPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
- .offset: 168
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18centroid_recomputePdS_S_S_iPi
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: _Z18centroid_recomputePdS_S_S_iPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void callOperationSharedStatic(int *a, int *b, int x, int *res, int n)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
if (tid >= n)
{
return;
}
__shared__ int s_a[size], s_b[size], s_res[size];
__shared__ int s_x;
s_x = x;
s_a[tid] = a[tid];
s_b[tid] = b[tid];
s_res[tid] = ((s_a[tid] * s_x) + s_b[tid]);
res[tid] = s_res[tid];
} | code for sm_80
Function : _Z25callOperationSharedStaticPiS_iS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee2000c1e1900 */
/*00c0*/ MOV R8, c[0x0][0x170] ; /* 0x00005c0000087a02 */
/* 0x000fe20000000f00 */
/*00d0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x178] ; /* 0x00005e0000067625 */
/* 0x000fc800078e0207 */
/*00e0*/ STS [0x14], R8 ; /* 0x00001408ff007388 */
/* 0x000fe80000000800 */
/*00f0*/ STS [R0.X4], R3 ; /* 0x0000000300007388 */
/* 0x004fe20000004800 */
/*0100*/ IMAD R9, R3, c[0x0][0x170], R4 ; /* 0x00005c0003097a24 */
/* 0x008fca00078e0204 */
/*0110*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void callOperationSharedStatic(int *a, int *b, int x, int *res, int n)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
if (tid >= n)
{
return;
}
__shared__ int s_a[size], s_b[size], s_res[size];
__shared__ int s_x;
s_x = x;
s_a[tid] = a[tid];
s_b[tid] = b[tid];
s_res[tid] = ((s_a[tid] * s_x) + s_b[tid]);
res[tid] = s_res[tid];
} | .file "tmpxft_0016f500_00000000-6_callOperationSharedStatic.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z25callOperationSharedStaticPiS_iS_iPiS_iS_i
.type _Z51__device_stub__Z25callOperationSharedStaticPiS_iS_iPiS_iS_i, @function
_Z51__device_stub__Z25callOperationSharedStaticPiS_iS_iPiS_iS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, (%rsp)
movl %r8d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z25callOperationSharedStaticPiS_iS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z51__device_stub__Z25callOperationSharedStaticPiS_iS_iPiS_iS_i, .-_Z51__device_stub__Z25callOperationSharedStaticPiS_iS_iPiS_iS_i
.globl _Z25callOperationSharedStaticPiS_iS_i
.type _Z25callOperationSharedStaticPiS_iS_i, @function
_Z25callOperationSharedStaticPiS_iS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z25callOperationSharedStaticPiS_iS_iPiS_iS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z25callOperationSharedStaticPiS_iS_i, .-_Z25callOperationSharedStaticPiS_iS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z25callOperationSharedStaticPiS_iS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z25callOperationSharedStaticPiS_iS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void callOperationSharedStatic(int *a, int *b, int x, int *res, int n)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
if (tid >= n)
{
return;
}
__shared__ int s_a[size], s_b[size], s_res[size];
__shared__ int s_x;
s_x = x;
s_a[tid] = a[tid];
s_b[tid] = b[tid];
s_res[tid] = ((s_a[tid] * s_x) + s_b[tid]);
res[tid] = s_res[tid];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void callOperationSharedStatic(int *a, int *b, int x, int *res, int n)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
if (tid >= n)
{
return;
}
__shared__ int s_a[size], s_b[size], s_res[size];
__shared__ int s_x;
s_x = x;
s_a[tid] = a[tid];
s_b[tid] = b[tid];
s_res[tid] = ((s_a[tid] * s_x) + s_b[tid]);
res[tid] = s_res[tid];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void callOperationSharedStatic(int *a, int *b, int x, int *res, int n)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
if (tid >= n)
{
return;
}
__shared__ int s_a[size], s_b[size], s_res[size];
__shared__ int s_x;
s_x = x;
s_a[tid] = a[tid];
s_b[tid] = b[tid];
s_res[tid] = ((s_a[tid] * s_x) + s_b[tid]);
res[tid] = s_res[tid];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25callOperationSharedStaticPiS_iS_i
.globl _Z25callOperationSharedStaticPiS_iS_i
.p2align 8
.type _Z25callOperationSharedStaticPiS_iS_i,@function
_Z25callOperationSharedStaticPiS_iS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s2, s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v6, v[2:3], off
global_load_b32 v2, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v6, s2, v[2:3]
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25callOperationSharedStaticPiS_iS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z25callOperationSharedStaticPiS_iS_i, .Lfunc_end0-_Z25callOperationSharedStaticPiS_iS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25callOperationSharedStaticPiS_iS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z25callOperationSharedStaticPiS_iS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void callOperationSharedStatic(int *a, int *b, int x, int *res, int n)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
if (tid >= n)
{
return;
}
__shared__ int s_a[size], s_b[size], s_res[size];
__shared__ int s_x;
s_x = x;
s_a[tid] = a[tid];
s_b[tid] = b[tid];
s_res[tid] = ((s_a[tid] * s_x) + s_b[tid]);
res[tid] = s_res[tid];
} | .text
.file "callOperationSharedStatic.hip"
.globl _Z40__device_stub__callOperationSharedStaticPiS_iS_i # -- Begin function _Z40__device_stub__callOperationSharedStaticPiS_iS_i
.p2align 4, 0x90
.type _Z40__device_stub__callOperationSharedStaticPiS_iS_i,@function
_Z40__device_stub__callOperationSharedStaticPiS_iS_i: # @_Z40__device_stub__callOperationSharedStaticPiS_iS_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 56(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z25callOperationSharedStaticPiS_iS_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z40__device_stub__callOperationSharedStaticPiS_iS_i, .Lfunc_end0-_Z40__device_stub__callOperationSharedStaticPiS_iS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25callOperationSharedStaticPiS_iS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z25callOperationSharedStaticPiS_iS_i,@object # @_Z25callOperationSharedStaticPiS_iS_i
.section .rodata,"a",@progbits
.globl _Z25callOperationSharedStaticPiS_iS_i
.p2align 3, 0x0
_Z25callOperationSharedStaticPiS_iS_i:
.quad _Z40__device_stub__callOperationSharedStaticPiS_iS_i
.size _Z25callOperationSharedStaticPiS_iS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z25callOperationSharedStaticPiS_iS_i"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__callOperationSharedStaticPiS_iS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z25callOperationSharedStaticPiS_iS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z25callOperationSharedStaticPiS_iS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee2000c1e1900 */
/*00c0*/ MOV R8, c[0x0][0x170] ; /* 0x00005c0000087a02 */
/* 0x000fe20000000f00 */
/*00d0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x178] ; /* 0x00005e0000067625 */
/* 0x000fc800078e0207 */
/*00e0*/ STS [0x14], R8 ; /* 0x00001408ff007388 */
/* 0x000fe80000000800 */
/*00f0*/ STS [R0.X4], R3 ; /* 0x0000000300007388 */
/* 0x004fe20000004800 */
/*0100*/ IMAD R9, R3, c[0x0][0x170], R4 ; /* 0x00005c0003097a24 */
/* 0x008fca00078e0204 */
/*0110*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25callOperationSharedStaticPiS_iS_i
.globl _Z25callOperationSharedStaticPiS_iS_i
.p2align 8
.type _Z25callOperationSharedStaticPiS_iS_i,@function
_Z25callOperationSharedStaticPiS_iS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s2, s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v6, v[2:3], off
global_load_b32 v2, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v6, s2, v[2:3]
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25callOperationSharedStaticPiS_iS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z25callOperationSharedStaticPiS_iS_i, .Lfunc_end0-_Z25callOperationSharedStaticPiS_iS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25callOperationSharedStaticPiS_iS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z25callOperationSharedStaticPiS_iS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016f500_00000000-6_callOperationSharedStatic.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z25callOperationSharedStaticPiS_iS_iPiS_iS_i
.type _Z51__device_stub__Z25callOperationSharedStaticPiS_iS_iPiS_iS_i, @function
_Z51__device_stub__Z25callOperationSharedStaticPiS_iS_iPiS_iS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, (%rsp)
movl %r8d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z25callOperationSharedStaticPiS_iS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z51__device_stub__Z25callOperationSharedStaticPiS_iS_iPiS_iS_i, .-_Z51__device_stub__Z25callOperationSharedStaticPiS_iS_iPiS_iS_i
.globl _Z25callOperationSharedStaticPiS_iS_i
.type _Z25callOperationSharedStaticPiS_iS_i, @function
_Z25callOperationSharedStaticPiS_iS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z25callOperationSharedStaticPiS_iS_iPiS_iS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z25callOperationSharedStaticPiS_iS_i, .-_Z25callOperationSharedStaticPiS_iS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z25callOperationSharedStaticPiS_iS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z25callOperationSharedStaticPiS_iS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "callOperationSharedStatic.hip"
.globl _Z40__device_stub__callOperationSharedStaticPiS_iS_i # -- Begin function _Z40__device_stub__callOperationSharedStaticPiS_iS_i
.p2align 4, 0x90
.type _Z40__device_stub__callOperationSharedStaticPiS_iS_i,@function
_Z40__device_stub__callOperationSharedStaticPiS_iS_i: # @_Z40__device_stub__callOperationSharedStaticPiS_iS_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 56(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z25callOperationSharedStaticPiS_iS_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z40__device_stub__callOperationSharedStaticPiS_iS_i, .Lfunc_end0-_Z40__device_stub__callOperationSharedStaticPiS_iS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25callOperationSharedStaticPiS_iS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z25callOperationSharedStaticPiS_iS_i,@object # @_Z25callOperationSharedStaticPiS_iS_i
.section .rodata,"a",@progbits
.globl _Z25callOperationSharedStaticPiS_iS_i
.p2align 3, 0x0
_Z25callOperationSharedStaticPiS_iS_i:
.quad _Z40__device_stub__callOperationSharedStaticPiS_iS_i
.size _Z25callOperationSharedStaticPiS_iS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z25callOperationSharedStaticPiS_iS_i"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__callOperationSharedStaticPiS_iS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z25callOperationSharedStaticPiS_iS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
extern "C"
__global__ void add32(float* A, float *B, int size) {
int block = blockIdx.x + blockIdx.y * gridDim.x + gridDim.x * gridDim.y * blockIdx.z;
int index = block * (blockDim.x * blockDim.y * blockDim.z) + (threadIdx.z * (blockDim.x * blockDim.y)) + (threadIdx.y * blockDim.x) + threadIdx.x;
if(index >= size) return;
A[index] = A[index] + B[index];
} | code for sm_80
Function : add32
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Z ; /* 0x0000000000007919 */
/* 0x000e280000002700 */
/*0020*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002600 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e680000002500 */
/*0040*/ S2R R7, SR_TID.Z ; /* 0x0000000000077919 */
/* 0x000ea80000002300 */
/*0050*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000ee80000002200 */
/*0060*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000f220000002100 */
/*0070*/ IMAD R0, R0, c[0x0][0x10], R5 ; /* 0x0000040000007a24 */
/* 0x001fc800078e0205 */
/*0080*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x002fc800078e0203 */
/*0090*/ IMAD R0, R0, c[0x0][0x8], R7 ; /* 0x0000020000007a24 */
/* 0x004fc800078e0207 */
/*00a0*/ IMAD R0, R0, c[0x0][0x4], R9 ; /* 0x0000010000007a24 */
/* 0x008fc800078e0209 */
/*00b0*/ IMAD R0, R0, c[0x0][0x0], R11 ; /* 0x0000000000007a24 */
/* 0x010fca00078e020b */
/*00c0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*00f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0100*/ IMAD.WIDE R4, R0, R3, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0203 */
/*0110*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fe400078e0203 */
/*0120*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0130*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea4000c1e1900 */
/*0140*/ FADD R7, R4, R7 ; /* 0x0000000704077221 */
/* 0x004fca0000000000 */
/*0150*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
extern "C"
__global__ void add32(float* A, float *B, int size) {
int block = blockIdx.x + blockIdx.y * gridDim.x + gridDim.x * gridDim.y * blockIdx.z;
int index = block * (blockDim.x * blockDim.y * blockDim.z) + (threadIdx.z * (blockDim.x * blockDim.y)) + (threadIdx.y * blockDim.x) + threadIdx.x;
if(index >= size) return;
A[index] = A[index] + B[index];
} | .file "tmpxft_001263e2_00000000-6_add32.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z5add32PfS_iPfS_i
.type _Z27__device_stub__Z5add32PfS_iPfS_i, @function
_Z27__device_stub__Z5add32PfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq add32(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z5add32PfS_iPfS_i, .-_Z27__device_stub__Z5add32PfS_iPfS_i
.globl add32
.type add32, @function
add32:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z5add32PfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size add32, .-add32
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "add32"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq add32(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
extern "C"
__global__ void add32(float* A, float *B, int size) {
int block = blockIdx.x + blockIdx.y * gridDim.x + gridDim.x * gridDim.y * blockIdx.z;
int index = block * (blockDim.x * blockDim.y * blockDim.z) + (threadIdx.z * (blockDim.x * blockDim.y)) + (threadIdx.y * blockDim.x) + threadIdx.x;
if(index >= size) return;
A[index] = A[index] + B[index];
} | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C"
__global__ void add32(float* A, float *B, int size) {
int block = blockIdx.x + blockIdx.y * gridDim.x + gridDim.x * gridDim.y * blockIdx.z;
int index = block * (blockDim.x * blockDim.y * blockDim.z) + (threadIdx.z * (blockDim.x * blockDim.y)) + (threadIdx.y * blockDim.x) + threadIdx.x;
if(index >= size) return;
A[index] = A[index] + B[index];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C"
__global__ void add32(float* A, float *B, int size) {
int block = blockIdx.x + blockIdx.y * gridDim.x + gridDim.x * gridDim.y * blockIdx.z;
int index = block * (blockDim.x * blockDim.y * blockDim.z) + (threadIdx.z * (blockDim.x * blockDim.y)) + (threadIdx.y * blockDim.x) + threadIdx.x;
if(index >= size) return;
A[index] = A[index] + B[index];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected add32
.globl add32
.p2align 8
.type add32,@function
add32:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b64 s[4:5], s[0:1], 0x24
v_bfe_u32 v1, v0, 20, 10
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, s14
s_mul_i32 s2, s3, s2
s_and_b32 s3, s5, 0xffff
s_add_i32 s2, s2, s13
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s2, s3, v[1:2]
v_bfe_u32 v1, v0, 10, 10
s_load_b32 s2, s[0:1], 0x10
s_lshr_b32 s3, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, v2, s3, v[1:2]
v_and_b32_e32 v2, 0x3ff, v0
s_and_b32 s3, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, v3, s3, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v4, v[2:3], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v4, v0
global_store_b32 v[2:3], v0, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel add32
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size add32, .Lfunc_end0-add32
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: add32
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: add32.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C"
__global__ void add32(float* A, float *B, int size) {
int block = blockIdx.x + blockIdx.y * gridDim.x + gridDim.x * gridDim.y * blockIdx.z;
int index = block * (blockDim.x * blockDim.y * blockDim.z) + (threadIdx.z * (blockDim.x * blockDim.y)) + (threadIdx.y * blockDim.x) + threadIdx.x;
if(index >= size) return;
A[index] = A[index] + B[index];
} | .text
.file "add32.hip"
.globl __device_stub__add32 # -- Begin function __device_stub__add32
.p2align 4, 0x90
.type __device_stub__add32,@function
__device_stub__add32: # @__device_stub__add32
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $add32, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size __device_stub__add32, .Lfunc_end0-__device_stub__add32
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $add32, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type add32,@object # @add32
.section .rodata,"a",@progbits
.globl add32
.p2align 3, 0x0
add32:
.quad __device_stub__add32
.size add32, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "add32"
.size .L__unnamed_1, 6
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__add32
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym add32
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : add32
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Z ; /* 0x0000000000007919 */
/* 0x000e280000002700 */
/*0020*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002600 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e680000002500 */
/*0040*/ S2R R7, SR_TID.Z ; /* 0x0000000000077919 */
/* 0x000ea80000002300 */
/*0050*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000ee80000002200 */
/*0060*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000f220000002100 */
/*0070*/ IMAD R0, R0, c[0x0][0x10], R5 ; /* 0x0000040000007a24 */
/* 0x001fc800078e0205 */
/*0080*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x002fc800078e0203 */
/*0090*/ IMAD R0, R0, c[0x0][0x8], R7 ; /* 0x0000020000007a24 */
/* 0x004fc800078e0207 */
/*00a0*/ IMAD R0, R0, c[0x0][0x4], R9 ; /* 0x0000010000007a24 */
/* 0x008fc800078e0209 */
/*00b0*/ IMAD R0, R0, c[0x0][0x0], R11 ; /* 0x0000000000007a24 */
/* 0x010fca00078e020b */
/*00c0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*00f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0100*/ IMAD.WIDE R4, R0, R3, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0203 */
/*0110*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fe400078e0203 */
/*0120*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0130*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea4000c1e1900 */
/*0140*/ FADD R7, R4, R7 ; /* 0x0000000704077221 */
/* 0x004fca0000000000 */
/*0150*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected add32
.globl add32
.p2align 8
.type add32,@function
add32:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b64 s[4:5], s[0:1], 0x24
v_bfe_u32 v1, v0, 20, 10
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, s14
s_mul_i32 s2, s3, s2
s_and_b32 s3, s5, 0xffff
s_add_i32 s2, s2, s13
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s2, s3, v[1:2]
v_bfe_u32 v1, v0, 10, 10
s_load_b32 s2, s[0:1], 0x10
s_lshr_b32 s3, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, v2, s3, v[1:2]
v_and_b32_e32 v2, 0x3ff, v0
s_and_b32 s3, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, v3, s3, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v4, v[2:3], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v4, v0
global_store_b32 v[2:3], v0, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel add32
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size add32, .Lfunc_end0-add32
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: add32
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: add32.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001263e2_00000000-6_add32.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z5add32PfS_iPfS_i
.type _Z27__device_stub__Z5add32PfS_iPfS_i, @function
_Z27__device_stub__Z5add32PfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq add32(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z5add32PfS_iPfS_i, .-_Z27__device_stub__Z5add32PfS_iPfS_i
.globl add32
.type add32, @function
add32:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z5add32PfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size add32, .-add32
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "add32"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq add32(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "add32.hip"
.globl __device_stub__add32 # -- Begin function __device_stub__add32
.p2align 4, 0x90
.type __device_stub__add32,@function
__device_stub__add32: # @__device_stub__add32
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $add32, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size __device_stub__add32, .Lfunc_end0-__device_stub__add32
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $add32, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type add32,@object # @add32
.section .rodata,"a",@progbits
.globl add32
.p2align 3, 0x0
add32:
.quad __device_stub__add32
.size add32, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "add32"
.size .L__unnamed_1, 6
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__add32
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym add32
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <sys/time.h>
#include <cuda.h>
long long getCurrentTime()
{
struct timeval te;
gettimeofday(&te, NULL); // get current time
long long microseconds = te.tv_sec*1000000LL + te.tv_usec;
return microseconds;
}
#define CUDA_ERROR_CHECK
#define CudaSafeCall( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
inline void __cudaSafeCall( cudaError err, const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
if ( cudaSuccess != err ) {
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
#endif
return;
}
__global__ void assign(int *A, int streamId)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x;
i < 1024 * 1024;
i += blockDim.x * gridDim.x) {
A[i] += 1024*1024*streamId + i;
}
}
int main()
{
cudaStream_t streams[4];
int *A[4], *dA[4];
int N = 1024*1024;
// Initialization
for (int i = 0; i < 4; i++) {
CudaSafeCall(cudaStreamCreate(&streams[i]));
CudaSafeCall(cudaMallocHost((void**)&A[i], sizeof(int) * N));
CudaSafeCall(cudaMalloc(&dA[i], N * sizeof(int)));
}
// Asynchronous H2D copies
for (int i = 0; i < 4; i++) {
CudaSafeCall(cudaMemcpyAsync(dA[i], A[i], N * sizeof(int),
cudaMemcpyHostToDevice, streams[i]));
}
// Asynchronous kernel launches
for (int i = 0; i < 4; i++) {
assign<<<1, 1024, 0, streams[i]>>>(dA[i], i);
}
// Asynchronous D2H copies
for (int i = 0; i < 4; i++) {
CudaSafeCall(cudaMemcpyAsync(A[i], dA[i], N * sizeof(int),
cudaMemcpyDeviceToHost, streams[i]));
}
// Synchronization
for (int i = 0; i < 4; i++) {
CudaSafeCall(cudaStreamSynchronize(streams[i]));
}
// Verification
int error = 0;
for (int i = 0; i < 4; i++) {
for (int j = 0; j < N; j++) {
if (A[i][j] != i * N + j) {
error++;
}
}
}
if (!error) {
printf("VERIFILED\n");
} else {
printf("NOT VERIFIED");
}
return 0;
} | code for sm_80
Function : _Z6assignPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R0, 0xfffff, PT ; /* 0x000fffff0000780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ MOV R5, 0x100000 ; /* 0x0010000000057802 */
/* 0x000fe40000000f00 */
/*00b0*/ MOV R7, c[0x0][0x0] ; /* 0x0000000000077a02 */
/* 0x000fc60000000f00 */
/*00c0*/ IMAD R5, R5, c[0x0][0x168], R0.reuse ; /* 0x00005a0005057a24 */
/* 0x100fe400078e0200 */
/*00d0*/ IMAD R0, R7, c[0x0][0xc], R0 ; /* 0x0000030007007a24 */
/* 0x000fca00078e0200 */
/*00e0*/ ISETP.GE.AND P0, PT, R0, 0x100000, PT ; /* 0x001000000000780c */
/* 0x000fe40003f06270 */
/*00f0*/ IADD3 R5, R4, R5, RZ ; /* 0x0000000504057210 */
/* 0x004fca0007ffe0ff */
/*0100*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001ec000c101904 */
/*0110*/ @!P0 BRA 0x70 ; /* 0xffffff5000008947 */
/* 0x000fea000383ffff */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <sys/time.h>
#include <cuda.h>
long long getCurrentTime()
{
struct timeval te;
gettimeofday(&te, NULL); // get current time
long long microseconds = te.tv_sec*1000000LL + te.tv_usec;
return microseconds;
}
#define CUDA_ERROR_CHECK
#define CudaSafeCall( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
inline void __cudaSafeCall( cudaError err, const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
if ( cudaSuccess != err ) {
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
#endif
return;
}
__global__ void assign(int *A, int streamId)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x;
i < 1024 * 1024;
i += blockDim.x * gridDim.x) {
A[i] += 1024*1024*streamId + i;
}
}
int main()
{
cudaStream_t streams[4];
int *A[4], *dA[4];
int N = 1024*1024;
// Initialization
for (int i = 0; i < 4; i++) {
CudaSafeCall(cudaStreamCreate(&streams[i]));
CudaSafeCall(cudaMallocHost((void**)&A[i], sizeof(int) * N));
CudaSafeCall(cudaMalloc(&dA[i], N * sizeof(int)));
}
// Asynchronous H2D copies
for (int i = 0; i < 4; i++) {
CudaSafeCall(cudaMemcpyAsync(dA[i], A[i], N * sizeof(int),
cudaMemcpyHostToDevice, streams[i]));
}
// Asynchronous kernel launches
for (int i = 0; i < 4; i++) {
assign<<<1, 1024, 0, streams[i]>>>(dA[i], i);
}
// Asynchronous D2H copies
for (int i = 0; i < 4; i++) {
CudaSafeCall(cudaMemcpyAsync(A[i], dA[i], N * sizeof(int),
cudaMemcpyDeviceToHost, streams[i]));
}
// Synchronization
for (int i = 0; i < 4; i++) {
CudaSafeCall(cudaStreamSynchronize(streams[i]));
}
// Verification
int error = 0;
for (int i = 0; i < 4; i++) {
for (int j = 0; j < N; j++) {
if (A[i][j] != i * N + j) {
error++;
}
}
}
if (!error) {
printf("VERIFILED\n");
} else {
printf("NOT VERIFIED");
}
return 0;
} | .file "tmpxft_00098435_00000000-6_streams.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14getCurrentTimev
.type _Z14getCurrentTimev, @function
_Z14getCurrentTimev:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
imulq $1000000, (%rsp), %rax
addq 8(%rsp), %rax
movq 24(%rsp), %rdx
subq %fs:40, %rdx
jne .L6
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z14getCurrentTimev, .-_Z14getCurrentTimev
.globl _Z26__device_stub__Z6assignPiiPii
.type _Z26__device_stub__Z6assignPiiPii, @function
_Z26__device_stub__Z6assignPiiPii:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6assignPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z26__device_stub__Z6assignPiiPii, .-_Z26__device_stub__Z6assignPiiPii
.globl _Z6assignPii
.type _Z6assignPii, @function
_Z6assignPii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6assignPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z6assignPii, .-_Z6assignPii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/ryuji0123/cuda-tutorial/master/waseda2018/examples/streams/streams.cu"
.align 8
.LC1:
.string "cudaSafeCall() failed at %s:%i : %s\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "VERIFILED\n"
.LC3:
.string "NOT VERIFIED"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $152, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl $0, %r12d
leaq 96(%rsp), %r13
.L19:
leaq 32(%rsp), %rbp
leaq (%r12,%rbp), %rdi
call cudaStreamCreate@PLT
testl %eax, %eax
jne .L42
leaq 64(%rsp), %rbx
leaq (%r12,%rbx), %rdi
movl $4194304, %esi
call cudaMallocHost@PLT
testl %eax, %eax
jne .L43
leaq 0(%r13,%r12), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L44
addq $8, %r12
cmpq $32, %r12
jne .L19
movl $0, %r12d
.L21:
movq 64(%rsp,%r12), %rsi
movq 96(%rsp,%r12), %rdi
movq 32(%rsp,%r12), %r8
movl $1, %ecx
movl $4194304, %edx
call cudaMemcpyAsync@PLT
testl %eax, %eax
jne .L45
addq $8, %r12
cmpq $32, %r12
jne .L21
movl $0, %r12d
jmp .L23
.L42:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $45, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L43:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $46, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L44:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $47, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L45:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $52, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L22:
addq $1, %r12
cmpq $4, %r12
je .L46
.L23:
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movq 32(%rsp,%r12,8), %r9
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L22
movq 96(%rsp,%r12,8), %rdi
movl %r12d, %esi
call _Z26__device_stub__Z6assignPiiPii
jmp .L22
.L46:
movl $0, %r12d
.L25:
movq 96(%rsp,%r12), %rsi
movq 64(%rsp,%r12), %rdi
movq 32(%rsp,%r12), %r8
movl $2, %ecx
movl $4194304, %edx
call cudaMemcpyAsync@PLT
testl %eax, %eax
jne .L47
addq $8, %r12
cmpq $32, %r12
jne .L25
leaq 32(%rbp), %r12
.L27:
movq 0(%rbp), %rdi
call cudaStreamSynchronize@PLT
testl %eax, %eax
jne .L48
addq $8, %rbp
cmpq %r12, %rbp
jne .L27
movl $0, %esi
jmp .L28
.L47:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $63, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L48:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $69, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L29:
addq $1, %rdx
cmpq $1048576, %rdx
je .L49
.L30:
leal (%rax,%rdx), %ecx
cmpl %ecx, (%rdi,%rdx,4)
je .L29
addl $1, %esi
jmp .L29
.L49:
addq $8, %rbx
addl $1048576, %eax
cmpl $4194304, %eax
je .L31
.L28:
movq (%rbx), %rdi
movl $0, %edx
jmp .L30
.L31:
testl %esi, %esi
jne .L32
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L33:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L50
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L33
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z6assignPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z6assignPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <sys/time.h>
#include <cuda.h>
long long getCurrentTime()
{
struct timeval te;
gettimeofday(&te, NULL); // get current time
long long microseconds = te.tv_sec*1000000LL + te.tv_usec;
return microseconds;
}
#define CUDA_ERROR_CHECK
#define CudaSafeCall( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
inline void __cudaSafeCall( cudaError err, const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
if ( cudaSuccess != err ) {
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
#endif
return;
}
__global__ void assign(int *A, int streamId)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x;
i < 1024 * 1024;
i += blockDim.x * gridDim.x) {
A[i] += 1024*1024*streamId + i;
}
}
int main()
{
cudaStream_t streams[4];
int *A[4], *dA[4];
int N = 1024*1024;
// Initialization
for (int i = 0; i < 4; i++) {
CudaSafeCall(cudaStreamCreate(&streams[i]));
CudaSafeCall(cudaMallocHost((void**)&A[i], sizeof(int) * N));
CudaSafeCall(cudaMalloc(&dA[i], N * sizeof(int)));
}
// Asynchronous H2D copies
for (int i = 0; i < 4; i++) {
CudaSafeCall(cudaMemcpyAsync(dA[i], A[i], N * sizeof(int),
cudaMemcpyHostToDevice, streams[i]));
}
// Asynchronous kernel launches
for (int i = 0; i < 4; i++) {
assign<<<1, 1024, 0, streams[i]>>>(dA[i], i);
}
// Asynchronous D2H copies
for (int i = 0; i < 4; i++) {
CudaSafeCall(cudaMemcpyAsync(A[i], dA[i], N * sizeof(int),
cudaMemcpyDeviceToHost, streams[i]));
}
// Synchronization
for (int i = 0; i < 4; i++) {
CudaSafeCall(cudaStreamSynchronize(streams[i]));
}
// Verification
int error = 0;
for (int i = 0; i < 4; i++) {
for (int j = 0; j < N; j++) {
if (A[i][j] != i * N + j) {
error++;
}
}
}
if (!error) {
printf("VERIFILED\n");
} else {
printf("NOT VERIFIED");
}
return 0;
} | #include <stdio.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
long long getCurrentTime()
{
struct timeval te;
gettimeofday(&te, NULL); // get current time
long long microseconds = te.tv_sec*1000000LL + te.tv_usec;
return microseconds;
}
#define CUDA_ERROR_CHECK
#define CudaSafeCall( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
inline void __cudaSafeCall( hipError_t err, const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
if ( hipSuccess != err ) {
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
#endif
return;
}
__global__ void assign(int *A, int streamId)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x;
i < 1024 * 1024;
i += blockDim.x * gridDim.x) {
A[i] += 1024*1024*streamId + i;
}
}
int main()
{
hipStream_t streams[4];
int *A[4], *dA[4];
int N = 1024*1024;
// Initialization
for (int i = 0; i < 4; i++) {
CudaSafeCall(hipStreamCreate(&streams[i]));
CudaSafeCall(hipHostMalloc((void**)&A[i], sizeof(int) * N, hipHostMallocDefault));
CudaSafeCall(hipMalloc(&dA[i], N * sizeof(int)));
}
// Asynchronous H2D copies
for (int i = 0; i < 4; i++) {
CudaSafeCall(hipMemcpyAsync(dA[i], A[i], N * sizeof(int),
hipMemcpyHostToDevice, streams[i]));
}
// Asynchronous kernel launches
for (int i = 0; i < 4; i++) {
assign<<<1, 1024, 0, streams[i]>>>(dA[i], i);
}
// Asynchronous D2H copies
for (int i = 0; i < 4; i++) {
CudaSafeCall(hipMemcpyAsync(A[i], dA[i], N * sizeof(int),
hipMemcpyDeviceToHost, streams[i]));
}
// Synchronization
for (int i = 0; i < 4; i++) {
CudaSafeCall(hipStreamSynchronize(streams[i]));
}
// Verification
int error = 0;
for (int i = 0; i < 4; i++) {
for (int j = 0; j < N; j++) {
if (A[i][j] != i * N + j) {
error++;
}
}
}
if (!error) {
printf("VERIFILED\n");
} else {
printf("NOT VERIFIED");
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
long long getCurrentTime()
{
struct timeval te;
gettimeofday(&te, NULL); // get current time
long long microseconds = te.tv_sec*1000000LL + te.tv_usec;
return microseconds;
}
#define CUDA_ERROR_CHECK
#define CudaSafeCall( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
inline void __cudaSafeCall( hipError_t err, const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
if ( hipSuccess != err ) {
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
#endif
return;
}
__global__ void assign(int *A, int streamId)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x;
i < 1024 * 1024;
i += blockDim.x * gridDim.x) {
A[i] += 1024*1024*streamId + i;
}
}
int main()
{
hipStream_t streams[4];
int *A[4], *dA[4];
int N = 1024*1024;
// Initialization
for (int i = 0; i < 4; i++) {
CudaSafeCall(hipStreamCreate(&streams[i]));
CudaSafeCall(hipHostMalloc((void**)&A[i], sizeof(int) * N, hipHostMallocDefault));
CudaSafeCall(hipMalloc(&dA[i], N * sizeof(int)));
}
// Asynchronous H2D copies
for (int i = 0; i < 4; i++) {
CudaSafeCall(hipMemcpyAsync(dA[i], A[i], N * sizeof(int),
hipMemcpyHostToDevice, streams[i]));
}
// Asynchronous kernel launches
for (int i = 0; i < 4; i++) {
assign<<<1, 1024, 0, streams[i]>>>(dA[i], i);
}
// Asynchronous D2H copies
for (int i = 0; i < 4; i++) {
CudaSafeCall(hipMemcpyAsync(A[i], dA[i], N * sizeof(int),
hipMemcpyDeviceToHost, streams[i]));
}
// Synchronization
for (int i = 0; i < 4; i++) {
CudaSafeCall(hipStreamSynchronize(streams[i]));
}
// Verification
int error = 0;
for (int i = 0; i < 4; i++) {
for (int j = 0; j < N; j++) {
if (A[i][j] != i * N + j) {
error++;
}
}
}
if (!error) {
printf("VERIFILED\n");
} else {
printf("NOT VERIFIED");
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6assignPii
.globl _Z6assignPii
.p2align 8
.type _Z6assignPii,@function
_Z6assignPii:
s_load_b32 s4, s[0:1], 0x1c
s_add_u32 s2, s0, 16
s_addc_u32 s3, s1, 0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_cmpx_gt_i32_e32 0x100000, v1
s_cbranch_execz .LBB0_3
s_load_b32 s5, s[0:1], 0x8
s_load_b32 s3, s[2:3], 0x0
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_lshl_b32 s2, s5, 20
s_mul_i32 s3, s3, s4
s_mov_b32 s4, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_add3_u32 v0, s2, v1, v0
v_add_nc_u32_e32 v1, s3, v1
global_store_b32 v[2:3], v0, off
v_cmp_lt_i32_e32 vcc_lo, 0xfffff, v1
s_or_b32 s4, vcc_lo, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6assignPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6assignPii, .Lfunc_end0-_Z6assignPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6assignPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6assignPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
long long getCurrentTime()
{
struct timeval te;
gettimeofday(&te, NULL); // get current time
long long microseconds = te.tv_sec*1000000LL + te.tv_usec;
return microseconds;
}
#define CUDA_ERROR_CHECK
#define CudaSafeCall( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
inline void __cudaSafeCall( hipError_t err, const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
if ( hipSuccess != err ) {
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
#endif
return;
}
__global__ void assign(int *A, int streamId)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x;
i < 1024 * 1024;
i += blockDim.x * gridDim.x) {
A[i] += 1024*1024*streamId + i;
}
}
int main()
{
hipStream_t streams[4];
int *A[4], *dA[4];
int N = 1024*1024;
// Initialization
for (int i = 0; i < 4; i++) {
CudaSafeCall(hipStreamCreate(&streams[i]));
CudaSafeCall(hipHostMalloc((void**)&A[i], sizeof(int) * N, hipHostMallocDefault));
CudaSafeCall(hipMalloc(&dA[i], N * sizeof(int)));
}
// Asynchronous H2D copies
for (int i = 0; i < 4; i++) {
CudaSafeCall(hipMemcpyAsync(dA[i], A[i], N * sizeof(int),
hipMemcpyHostToDevice, streams[i]));
}
// Asynchronous kernel launches
for (int i = 0; i < 4; i++) {
assign<<<1, 1024, 0, streams[i]>>>(dA[i], i);
}
// Asynchronous D2H copies
for (int i = 0; i < 4; i++) {
CudaSafeCall(hipMemcpyAsync(A[i], dA[i], N * sizeof(int),
hipMemcpyDeviceToHost, streams[i]));
}
// Synchronization
for (int i = 0; i < 4; i++) {
CudaSafeCall(hipStreamSynchronize(streams[i]));
}
// Verification
int error = 0;
for (int i = 0; i < 4; i++) {
for (int j = 0; j < N; j++) {
if (A[i][j] != i * N + j) {
error++;
}
}
}
if (!error) {
printf("VERIFILED\n");
} else {
printf("NOT VERIFIED");
}
return 0;
} | .text
.file "streams.hip"
.globl _Z14getCurrentTimev # -- Begin function _Z14getCurrentTimev
.p2align 4, 0x90
.type _Z14getCurrentTimev,@function
_Z14getCurrentTimev: # @_Z14getCurrentTimev
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
imulq $1000000, 8(%rsp), %rax # imm = 0xF4240
addq 16(%rsp), %rax
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z14getCurrentTimev, .Lfunc_end0-_Z14getCurrentTimev
.cfi_endproc
# -- End function
.globl _Z21__device_stub__assignPii # -- Begin function _Z21__device_stub__assignPii
.p2align 4, 0x90
.type _Z21__device_stub__assignPii,@function
_Z21__device_stub__assignPii: # @_Z21__device_stub__assignPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6assignPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z21__device_stub__assignPii, .Lfunc_end1-_Z21__device_stub__assignPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
leaq (%rsp,%rbx), %rdi
addq $80, %rdi
callq hipStreamCreate
testl %eax, %eax
jne .LBB2_2
# %bb.8: # %_Z14__cudaSafeCall10hipError_tPKci.exit
# in Loop: Header=BB2_1 Depth=1
leaq (%rsp,%rbx), %rdi
addq $144, %rdi
movl $4194304, %esi # imm = 0x400000
xorl %edx, %edx
callq hipHostMalloc
testl %eax, %eax
jne .LBB2_9
# %bb.10: # %_Z14__cudaSafeCall10hipError_tPKci.exit52
# in Loop: Header=BB2_1 Depth=1
leaq (%rsp,%rbx), %rdi
addq $112, %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
testl %eax, %eax
jne .LBB2_11
# %bb.4: # in Loop: Header=BB2_1 Depth=1
addq $8, %rbx
cmpq $32, %rbx
jne .LBB2_1
# %bb.5: # %_Z14__cudaSafeCall10hipError_tPKci.exit56.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_6: # %_Z14__cudaSafeCall10hipError_tPKci.exit56
# =>This Inner Loop Header: Depth=1
movq 112(%rsp,%rbx,8), %rdi
movq 144(%rsp,%rbx,8), %rsi
movq 80(%rsp,%rbx,8), %r8
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpyAsync
testl %eax, %eax
jne .LBB2_7
# %bb.12: # in Loop: Header=BB2_6 Depth=1
incq %rbx
cmpq $4, %rbx
jne .LBB2_6
# %bb.13: # %.preheader67
movabsq $4294967297, %rbx # imm = 0x100000001
xorl %r12d, %r12d
leaq 1023(%rbx), %r14
leaq 16(%rsp), %r13
leaq 8(%rsp), %rbp
leaq 64(%rsp), %r15
jmp .LBB2_14
.p2align 4, 0x90
.LBB2_16: # in Loop: Header=BB2_14 Depth=1
incq %r12
cmpq $4, %r12
je .LBB2_17
.LBB2_14: # =>This Inner Loop Header: Depth=1
movq 80(%rsp,%r12,8), %r9
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_16
# %bb.15: # in Loop: Header=BB2_14 Depth=1
movq 112(%rsp,%r12,8), %rax
movq %rax, 56(%rsp)
movl %r12d, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movl $_Z6assignPii, %edi
movq %r15, %r9
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_16
.LBB2_17: # %_Z14__cudaSafeCall10hipError_tPKci.exit58.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_18: # %_Z14__cudaSafeCall10hipError_tPKci.exit58
# =>This Inner Loop Header: Depth=1
movq 144(%rsp,%rbx,8), %rdi
movq 112(%rsp,%rbx,8), %rsi
movq 80(%rsp,%rbx,8), %r8
movl $4194304, %edx # imm = 0x400000
movl $2, %ecx
callq hipMemcpyAsync
testl %eax, %eax
jne .LBB2_23
# %bb.19: # in Loop: Header=BB2_18 Depth=1
incq %rbx
cmpq $4, %rbx
jne .LBB2_18
# %bb.20: # %_Z14__cudaSafeCall10hipError_tPKci.exit60.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_21: # %_Z14__cudaSafeCall10hipError_tPKci.exit60
# =>This Inner Loop Header: Depth=1
movq 80(%rsp,%rbx,8), %rdi
callq hipStreamSynchronize
testl %eax, %eax
jne .LBB2_22
# %bb.24: # in Loop: Header=BB2_21 Depth=1
incq %rbx
cmpq $4, %rbx
jne .LBB2_21
# %bb.25: # %.preheader.preheader
xorl %eax, %eax
xorl %edx, %edx
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_26: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_27 Depth 2
movq 144(%rsp,%rdx,8), %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB2_27: # Parent Loop BB2_26 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rsi,%rdi,4), %r8d
leaq (%rax,%rdi), %r9
xorl %r10d, %r10d
cmpq %r8, %r9
setne %r10b
addl %r10d, %ecx
incq %rdi
cmpq $1048576, %rdi # imm = 0x100000
jne .LBB2_27
# %bb.28: # in Loop: Header=BB2_26 Depth=1
incq %rdx
addq $1048576, %rax # imm = 0x100000
cmpq $4, %rdx
jne .LBB2_26
# %bb.29:
testl %ecx, %ecx
je .LBB2_30
# %bb.31:
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
jmp .LBB2_32
.LBB2_30:
movl $.Lstr, %edi
callq puts@PLT
.LBB2_32:
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_11:
.cfi_def_cfa_offset 240
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $47, %ecx
jmp .LBB2_3
.LBB2_9:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $46, %ecx
jmp .LBB2_3
.LBB2_2:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $45, %ecx
jmp .LBB2_3
.LBB2_7:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $53, %ecx
jmp .LBB2_3
.LBB2_23:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $64, %ecx
jmp .LBB2_3
.LBB2_22:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $69, %ecx
.LBB2_3:
movq %rax, %r8
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6assignPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6assignPii,@object # @_Z6assignPii
.section .rodata,"a",@progbits
.globl _Z6assignPii
.p2align 3, 0x0
_Z6assignPii:
.quad _Z21__device_stub__assignPii
.size _Z6assignPii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/ryuji0123/cuda-tutorial/master/waseda2018/examples/streams/streams.hip"
.size .L.str, 128
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "NOT VERIFIED"
.size .L.str.2, 13
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "cudaSafeCall() failed at %s:%i : %s\n"
.size .L.str.3, 37
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6assignPii"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "VERIFILED"
.size .Lstr, 10
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__assignPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6assignPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6assignPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R0, 0xfffff, PT ; /* 0x000fffff0000780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ MOV R5, 0x100000 ; /* 0x0010000000057802 */
/* 0x000fe40000000f00 */
/*00b0*/ MOV R7, c[0x0][0x0] ; /* 0x0000000000077a02 */
/* 0x000fc60000000f00 */
/*00c0*/ IMAD R5, R5, c[0x0][0x168], R0.reuse ; /* 0x00005a0005057a24 */
/* 0x100fe400078e0200 */
/*00d0*/ IMAD R0, R7, c[0x0][0xc], R0 ; /* 0x0000030007007a24 */
/* 0x000fca00078e0200 */
/*00e0*/ ISETP.GE.AND P0, PT, R0, 0x100000, PT ; /* 0x001000000000780c */
/* 0x000fe40003f06270 */
/*00f0*/ IADD3 R5, R4, R5, RZ ; /* 0x0000000504057210 */
/* 0x004fca0007ffe0ff */
/*0100*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001ec000c101904 */
/*0110*/ @!P0 BRA 0x70 ; /* 0xffffff5000008947 */
/* 0x000fea000383ffff */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6assignPii
.globl _Z6assignPii
.p2align 8
.type _Z6assignPii,@function
_Z6assignPii:
s_load_b32 s4, s[0:1], 0x1c
s_add_u32 s2, s0, 16
s_addc_u32 s3, s1, 0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_cmpx_gt_i32_e32 0x100000, v1
s_cbranch_execz .LBB0_3
s_load_b32 s5, s[0:1], 0x8
s_load_b32 s3, s[2:3], 0x0
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_lshl_b32 s2, s5, 20
s_mul_i32 s3, s3, s4
s_mov_b32 s4, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_add3_u32 v0, s2, v1, v0
v_add_nc_u32_e32 v1, s3, v1
global_store_b32 v[2:3], v0, off
v_cmp_lt_i32_e32 vcc_lo, 0xfffff, v1
s_or_b32 s4, vcc_lo, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6assignPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6assignPii, .Lfunc_end0-_Z6assignPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6assignPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6assignPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00098435_00000000-6_streams.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14getCurrentTimev
.type _Z14getCurrentTimev, @function
_Z14getCurrentTimev:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
imulq $1000000, (%rsp), %rax
addq 8(%rsp), %rax
movq 24(%rsp), %rdx
subq %fs:40, %rdx
jne .L6
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z14getCurrentTimev, .-_Z14getCurrentTimev
.globl _Z26__device_stub__Z6assignPiiPii
.type _Z26__device_stub__Z6assignPiiPii, @function
_Z26__device_stub__Z6assignPiiPii:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6assignPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z26__device_stub__Z6assignPiiPii, .-_Z26__device_stub__Z6assignPiiPii
.globl _Z6assignPii
.type _Z6assignPii, @function
_Z6assignPii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6assignPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z6assignPii, .-_Z6assignPii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/ryuji0123/cuda-tutorial/master/waseda2018/examples/streams/streams.cu"
.align 8
.LC1:
.string "cudaSafeCall() failed at %s:%i : %s\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "VERIFILED\n"
.LC3:
.string "NOT VERIFIED"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $152, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl $0, %r12d
leaq 96(%rsp), %r13
.L19:
leaq 32(%rsp), %rbp
leaq (%r12,%rbp), %rdi
call cudaStreamCreate@PLT
testl %eax, %eax
jne .L42
leaq 64(%rsp), %rbx
leaq (%r12,%rbx), %rdi
movl $4194304, %esi
call cudaMallocHost@PLT
testl %eax, %eax
jne .L43
leaq 0(%r13,%r12), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L44
addq $8, %r12
cmpq $32, %r12
jne .L19
movl $0, %r12d
.L21:
movq 64(%rsp,%r12), %rsi
movq 96(%rsp,%r12), %rdi
movq 32(%rsp,%r12), %r8
movl $1, %ecx
movl $4194304, %edx
call cudaMemcpyAsync@PLT
testl %eax, %eax
jne .L45
addq $8, %r12
cmpq $32, %r12
jne .L21
movl $0, %r12d
jmp .L23
.L42:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $45, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L43:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $46, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L44:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $47, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L45:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $52, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L22:
addq $1, %r12
cmpq $4, %r12
je .L46
.L23:
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movq 32(%rsp,%r12,8), %r9
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L22
movq 96(%rsp,%r12,8), %rdi
movl %r12d, %esi
call _Z26__device_stub__Z6assignPiiPii
jmp .L22
.L46:
movl $0, %r12d
.L25:
movq 96(%rsp,%r12), %rsi
movq 64(%rsp,%r12), %rdi
movq 32(%rsp,%r12), %r8
movl $2, %ecx
movl $4194304, %edx
call cudaMemcpyAsync@PLT
testl %eax, %eax
jne .L47
addq $8, %r12
cmpq $32, %r12
jne .L25
leaq 32(%rbp), %r12
.L27:
movq 0(%rbp), %rdi
call cudaStreamSynchronize@PLT
testl %eax, %eax
jne .L48
addq $8, %rbp
cmpq %r12, %rbp
jne .L27
movl $0, %esi
jmp .L28
.L47:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $63, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L48:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $69, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L29:
addq $1, %rdx
cmpq $1048576, %rdx
je .L49
.L30:
leal (%rax,%rdx), %ecx
cmpl %ecx, (%rdi,%rdx,4)
je .L29
addl $1, %esi
jmp .L29
.L49:
addq $8, %rbx
addl $1048576, %eax
cmpl $4194304, %eax
je .L31
.L28:
movq (%rbx), %rdi
movl $0, %edx
jmp .L30
.L31:
testl %esi, %esi
jne .L32
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L33:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L50
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L33
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z6assignPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z6assignPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "streams.hip"
.globl _Z14getCurrentTimev # -- Begin function _Z14getCurrentTimev
.p2align 4, 0x90
.type _Z14getCurrentTimev,@function
_Z14getCurrentTimev: # @_Z14getCurrentTimev
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
imulq $1000000, 8(%rsp), %rax # imm = 0xF4240
addq 16(%rsp), %rax
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z14getCurrentTimev, .Lfunc_end0-_Z14getCurrentTimev
.cfi_endproc
# -- End function
.globl _Z21__device_stub__assignPii # -- Begin function _Z21__device_stub__assignPii
.p2align 4, 0x90
.type _Z21__device_stub__assignPii,@function
_Z21__device_stub__assignPii: # @_Z21__device_stub__assignPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6assignPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z21__device_stub__assignPii, .Lfunc_end1-_Z21__device_stub__assignPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
leaq (%rsp,%rbx), %rdi
addq $80, %rdi
callq hipStreamCreate
testl %eax, %eax
jne .LBB2_2
# %bb.8: # %_Z14__cudaSafeCall10hipError_tPKci.exit
# in Loop: Header=BB2_1 Depth=1
leaq (%rsp,%rbx), %rdi
addq $144, %rdi
movl $4194304, %esi # imm = 0x400000
xorl %edx, %edx
callq hipHostMalloc
testl %eax, %eax
jne .LBB2_9
# %bb.10: # %_Z14__cudaSafeCall10hipError_tPKci.exit52
# in Loop: Header=BB2_1 Depth=1
leaq (%rsp,%rbx), %rdi
addq $112, %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
testl %eax, %eax
jne .LBB2_11
# %bb.4: # in Loop: Header=BB2_1 Depth=1
addq $8, %rbx
cmpq $32, %rbx
jne .LBB2_1
# %bb.5: # %_Z14__cudaSafeCall10hipError_tPKci.exit56.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_6: # %_Z14__cudaSafeCall10hipError_tPKci.exit56
# =>This Inner Loop Header: Depth=1
movq 112(%rsp,%rbx,8), %rdi
movq 144(%rsp,%rbx,8), %rsi
movq 80(%rsp,%rbx,8), %r8
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpyAsync
testl %eax, %eax
jne .LBB2_7
# %bb.12: # in Loop: Header=BB2_6 Depth=1
incq %rbx
cmpq $4, %rbx
jne .LBB2_6
# %bb.13: # %.preheader67
movabsq $4294967297, %rbx # imm = 0x100000001
xorl %r12d, %r12d
leaq 1023(%rbx), %r14
leaq 16(%rsp), %r13
leaq 8(%rsp), %rbp
leaq 64(%rsp), %r15
jmp .LBB2_14
.p2align 4, 0x90
.LBB2_16: # in Loop: Header=BB2_14 Depth=1
incq %r12
cmpq $4, %r12
je .LBB2_17
.LBB2_14: # =>This Inner Loop Header: Depth=1
movq 80(%rsp,%r12,8), %r9
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_16
# %bb.15: # in Loop: Header=BB2_14 Depth=1
movq 112(%rsp,%r12,8), %rax
movq %rax, 56(%rsp)
movl %r12d, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movl $_Z6assignPii, %edi
movq %r15, %r9
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_16
.LBB2_17: # %_Z14__cudaSafeCall10hipError_tPKci.exit58.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_18: # %_Z14__cudaSafeCall10hipError_tPKci.exit58
# =>This Inner Loop Header: Depth=1
movq 144(%rsp,%rbx,8), %rdi
movq 112(%rsp,%rbx,8), %rsi
movq 80(%rsp,%rbx,8), %r8
movl $4194304, %edx # imm = 0x400000
movl $2, %ecx
callq hipMemcpyAsync
testl %eax, %eax
jne .LBB2_23
# %bb.19: # in Loop: Header=BB2_18 Depth=1
incq %rbx
cmpq $4, %rbx
jne .LBB2_18
# %bb.20: # %_Z14__cudaSafeCall10hipError_tPKci.exit60.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_21: # %_Z14__cudaSafeCall10hipError_tPKci.exit60
# =>This Inner Loop Header: Depth=1
movq 80(%rsp,%rbx,8), %rdi
callq hipStreamSynchronize
testl %eax, %eax
jne .LBB2_22
# %bb.24: # in Loop: Header=BB2_21 Depth=1
incq %rbx
cmpq $4, %rbx
jne .LBB2_21
# %bb.25: # %.preheader.preheader
xorl %eax, %eax
xorl %edx, %edx
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_26: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_27 Depth 2
movq 144(%rsp,%rdx,8), %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB2_27: # Parent Loop BB2_26 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rsi,%rdi,4), %r8d
leaq (%rax,%rdi), %r9
xorl %r10d, %r10d
cmpq %r8, %r9
setne %r10b
addl %r10d, %ecx
incq %rdi
cmpq $1048576, %rdi # imm = 0x100000
jne .LBB2_27
# %bb.28: # in Loop: Header=BB2_26 Depth=1
incq %rdx
addq $1048576, %rax # imm = 0x100000
cmpq $4, %rdx
jne .LBB2_26
# %bb.29:
testl %ecx, %ecx
je .LBB2_30
# %bb.31:
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
jmp .LBB2_32
.LBB2_30:
movl $.Lstr, %edi
callq puts@PLT
.LBB2_32:
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_11:
.cfi_def_cfa_offset 240
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $47, %ecx
jmp .LBB2_3
.LBB2_9:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $46, %ecx
jmp .LBB2_3
.LBB2_2:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $45, %ecx
jmp .LBB2_3
.LBB2_7:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $53, %ecx
jmp .LBB2_3
.LBB2_23:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $64, %ecx
jmp .LBB2_3
.LBB2_22:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $69, %ecx
.LBB2_3:
movq %rax, %r8
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6assignPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6assignPii,@object # @_Z6assignPii
.section .rodata,"a",@progbits
.globl _Z6assignPii
.p2align 3, 0x0
_Z6assignPii:
.quad _Z21__device_stub__assignPii
.size _Z6assignPii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/ryuji0123/cuda-tutorial/master/waseda2018/examples/streams/streams.hip"
.size .L.str, 128
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "NOT VERIFIED"
.size .L.str.2, 13
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "cudaSafeCall() failed at %s:%i : %s\n"
.size .L.str.3, 37
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6assignPii"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "VERIFILED"
.size .Lstr, 10
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__assignPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6assignPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#define BLOCK_SIZE 1024
#ifndef THREADS
# define THREADS 1024
#endif
__global__ void total(float * input, float * output, unsigned int len) {
__shared__ float sum[2*BLOCK_SIZE];
unsigned int i = threadIdx.x;
unsigned int j = blockIdx.x * (blockDim.x * 2) + threadIdx.x;
float localSum = (i < len) ? input[j] : 0;
if (j + blockDim.x < len) localSum += input[j + blockDim.x];
sum[i] = localSum;
__syncthreads();
for (unsigned int step = blockDim.x / 2; step >= 1; step >>= 1) {
if (i < step) sum[i] = localSum = localSum + sum[i + step];
__syncthreads();
}
if(i == 0) output[blockIdx.x] = sum[0];
} | code for sm_80
Function : _Z5totalPfS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0020*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*0040*/ USHF.L.U32 UR5, UR4, 0x1, URZ ; /* 0x0000000104057899 */
/* 0x000fe2000800063f */
/*0050*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e620000002500 */
/*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0070*/ ISETP.GE.U32.AND P1, PT, R7, c[0x0][0x170], PT ; /* 0x00005c0007007a0c */
/* 0x001fc60003f26070 */
/*0080*/ IMAD R2, R6, UR5, R7 ; /* 0x0000000506027c24 */
/* 0x002fca000f8e0207 */
/*0090*/ IADD3 R4, R2, c[0x0][0x0], RZ ; /* 0x0000000002047a10 */
/* 0x000fc80007ffe0ff */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fe20003f06070 */
/*00b0*/ @!P1 IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff039424 */
/* 0x000fc800078e00ff */
/*00c0*/ @!P1 IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002029625 */
/* 0x000fca00078e0003 */
/*00d0*/ @!P1 LDG.E R0, [R2.64] ; /* 0x0000000602009981 */
/* 0x000ea6000c1e1900 */
/*00e0*/ @!P0 MOV R5, 0x4 ; /* 0x0000000400058802 */
/* 0x000fca0000000f00 */
/*00f0*/ @!P0 IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004048625 */
/* 0x000fcc00078e0005 */
/*0100*/ @!P0 LDG.E R5, [R4.64] ; /* 0x0000000604058981 */
/* 0x000ea2000c1e1900 */
/*0110*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011604 */
/*0120*/ ISETP.NE.AND P2, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe4000bf45270 */
/*0130*/ ISETP.NE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f25270 */
/*0140*/ @!P0 FADD R0, R0, R5 ; /* 0x0000000500008221 */
/* 0x004fca0000000000 */
/*0150*/ STS [R7.X4], R0 ; /* 0x0000000007007388 */
/* 0x0001e80000004800 */
/*0160*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0170*/ @!P2 BRA 0x230 ; /* 0x000000b00000a947 */
/* 0x000fea0003800000 */
/*0180*/ SHF.L.U32 R2, R7, 0x2, RZ ; /* 0x0000000207027819 */
/* 0x001fe200000006ff */
/*0190*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fca000f8e00ff */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R7, R3, PT ; /* 0x000000030700720c */
/* 0x000fda0003f06070 */
/*01b0*/ @!P0 LEA R4, R3, R2, 0x2 ; /* 0x0000000203048211 */
/* 0x000fe400078e10ff */
/*01c0*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc60000011603 */
/*01d0*/ @!P0 LDS R5, [R4] ; /* 0x0000000004058984 */
/* 0x000e240000000800 */
/*01e0*/ @!P0 FADD R0, R0, R5 ; /* 0x0000000500008221 */
/* 0x001fca0000000000 */
/*01f0*/ @!P0 STS [R7.X4], R0 ; /* 0x0000000007008388 */
/* 0x0001e80000004800 */
/*0200*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0210*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*0220*/ @P0 BRA 0x1a0 ; /* 0xffffff7000000947 */
/* 0x001fea000383ffff */
/*0230*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x001fea0003800000 */
/*0240*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*0250*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0260*/ IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fca00078e0003 */
/*0270*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*0280*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0290*/ BRA 0x290; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define BLOCK_SIZE 1024
#ifndef THREADS
# define THREADS 1024
#endif
__global__ void total(float * input, float * output, unsigned int len) {
__shared__ float sum[2*BLOCK_SIZE];
unsigned int i = threadIdx.x;
unsigned int j = blockIdx.x * (blockDim.x * 2) + threadIdx.x;
float localSum = (i < len) ? input[j] : 0;
if (j + blockDim.x < len) localSum += input[j + blockDim.x];
sum[i] = localSum;
__syncthreads();
for (unsigned int step = blockDim.x / 2; step >= 1; step >>= 1) {
if (i < step) sum[i] = localSum = localSum + sum[i + step];
__syncthreads();
}
if(i == 0) output[blockIdx.x] = sum[0];
} | .file "tmpxft_00015a86_00000000-6_total.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z5totalPfS_jPfS_j
.type _Z27__device_stub__Z5totalPfS_jPfS_j, @function
_Z27__device_stub__Z5totalPfS_jPfS_j:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5totalPfS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z5totalPfS_jPfS_j, .-_Z27__device_stub__Z5totalPfS_jPfS_j
.globl _Z5totalPfS_j
.type _Z5totalPfS_j, @function
_Z5totalPfS_j:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z5totalPfS_jPfS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z5totalPfS_j, .-_Z5totalPfS_j
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5totalPfS_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5totalPfS_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define BLOCK_SIZE 1024
#ifndef THREADS
# define THREADS 1024
#endif
__global__ void total(float * input, float * output, unsigned int len) {
__shared__ float sum[2*BLOCK_SIZE];
unsigned int i = threadIdx.x;
unsigned int j = blockIdx.x * (blockDim.x * 2) + threadIdx.x;
float localSum = (i < len) ? input[j] : 0;
if (j + blockDim.x < len) localSum += input[j + blockDim.x];
sum[i] = localSum;
__syncthreads();
for (unsigned int step = blockDim.x / 2; step >= 1; step >>= 1) {
if (i < step) sum[i] = localSum = localSum + sum[i + step];
__syncthreads();
}
if(i == 0) output[blockIdx.x] = sum[0];
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define BLOCK_SIZE 1024
#ifndef THREADS
# define THREADS 1024
#endif
__global__ void total(float * input, float * output, unsigned int len) {
__shared__ float sum[2*BLOCK_SIZE];
unsigned int i = threadIdx.x;
unsigned int j = blockIdx.x * (blockDim.x * 2) + threadIdx.x;
float localSum = (i < len) ? input[j] : 0;
if (j + blockDim.x < len) localSum += input[j + blockDim.x];
sum[i] = localSum;
__syncthreads();
for (unsigned int step = blockDim.x / 2; step >= 1; step >>= 1) {
if (i < step) sum[i] = localSum = localSum + sum[i + step];
__syncthreads();
}
if(i == 0) output[blockIdx.x] = sum[0];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define BLOCK_SIZE 1024
#ifndef THREADS
# define THREADS 1024
#endif
__global__ void total(float * input, float * output, unsigned int len) {
__shared__ float sum[2*BLOCK_SIZE];
unsigned int i = threadIdx.x;
unsigned int j = blockIdx.x * (blockDim.x * 2) + threadIdx.x;
float localSum = (i < len) ? input[j] : 0;
if (j + blockDim.x < len) localSum += input[j + blockDim.x];
sum[i] = localSum;
__syncthreads();
for (unsigned int step = blockDim.x / 2; step >= 1; step >>= 1) {
if (i < step) sum[i] = localSum = localSum + sum[i + step];
__syncthreads();
}
if(i == 0) output[blockIdx.x] = sum[0];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5totalPfS_j
.globl _Z5totalPfS_j
.p2align 8
.type _Z5totalPfS_j,@function
_Z5totalPfS_j:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s6, s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x0
v_mov_b32_e32 v3, 0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s7, s15, s3
v_lshl_add_u32 v1, s7, 1, v0
s_mov_b32 s7, exec_lo
v_cmpx_gt_u32_e64 s6, v0
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v3, v[2:3], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s7
v_add_nc_u32_e32 v1, s3, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u32_e32 vcc_lo, s6, v1
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz .LBB0_4
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, v3, v1
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s6
v_lshlrev_b32_e32 v1, 2, v0
s_cmp_lt_u32 s3, 2
s_waitcnt vmcnt(0)
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s3, 4
s_mov_b32 s3, s4
.LBB0_6:
buffer_gl0_inv
s_cbranch_scc1 .LBB0_9
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_5
v_add_lshl_u32 v2, s4, v0, 2
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v3, v3, v2
ds_store_b32 v1, v3
s_branch .LBB0_5
.LBB0_9:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_11
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5totalPfS_j
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5totalPfS_j, .Lfunc_end0-_Z5totalPfS_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5totalPfS_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5totalPfS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define BLOCK_SIZE 1024
#ifndef THREADS
# define THREADS 1024
#endif
__global__ void total(float * input, float * output, unsigned int len) {
__shared__ float sum[2*BLOCK_SIZE];
unsigned int i = threadIdx.x;
unsigned int j = blockIdx.x * (blockDim.x * 2) + threadIdx.x;
float localSum = (i < len) ? input[j] : 0;
if (j + blockDim.x < len) localSum += input[j + blockDim.x];
sum[i] = localSum;
__syncthreads();
for (unsigned int step = blockDim.x / 2; step >= 1; step >>= 1) {
if (i < step) sum[i] = localSum = localSum + sum[i + step];
__syncthreads();
}
if(i == 0) output[blockIdx.x] = sum[0];
} | .text
.file "total.hip"
.globl _Z20__device_stub__totalPfS_j # -- Begin function _Z20__device_stub__totalPfS_j
.p2align 4, 0x90
.type _Z20__device_stub__totalPfS_j,@function
_Z20__device_stub__totalPfS_j: # @_Z20__device_stub__totalPfS_j
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5totalPfS_j, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z20__device_stub__totalPfS_j, .Lfunc_end0-_Z20__device_stub__totalPfS_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5totalPfS_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5totalPfS_j,@object # @_Z5totalPfS_j
.section .rodata,"a",@progbits
.globl _Z5totalPfS_j
.p2align 3, 0x0
_Z5totalPfS_j:
.quad _Z20__device_stub__totalPfS_j
.size _Z5totalPfS_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5totalPfS_j"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__totalPfS_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5totalPfS_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5totalPfS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0020*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*0040*/ USHF.L.U32 UR5, UR4, 0x1, URZ ; /* 0x0000000104057899 */
/* 0x000fe2000800063f */
/*0050*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e620000002500 */
/*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0070*/ ISETP.GE.U32.AND P1, PT, R7, c[0x0][0x170], PT ; /* 0x00005c0007007a0c */
/* 0x001fc60003f26070 */
/*0080*/ IMAD R2, R6, UR5, R7 ; /* 0x0000000506027c24 */
/* 0x002fca000f8e0207 */
/*0090*/ IADD3 R4, R2, c[0x0][0x0], RZ ; /* 0x0000000002047a10 */
/* 0x000fc80007ffe0ff */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fe20003f06070 */
/*00b0*/ @!P1 IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff039424 */
/* 0x000fc800078e00ff */
/*00c0*/ @!P1 IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002029625 */
/* 0x000fca00078e0003 */
/*00d0*/ @!P1 LDG.E R0, [R2.64] ; /* 0x0000000602009981 */
/* 0x000ea6000c1e1900 */
/*00e0*/ @!P0 MOV R5, 0x4 ; /* 0x0000000400058802 */
/* 0x000fca0000000f00 */
/*00f0*/ @!P0 IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004048625 */
/* 0x000fcc00078e0005 */
/*0100*/ @!P0 LDG.E R5, [R4.64] ; /* 0x0000000604058981 */
/* 0x000ea2000c1e1900 */
/*0110*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011604 */
/*0120*/ ISETP.NE.AND P2, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe4000bf45270 */
/*0130*/ ISETP.NE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f25270 */
/*0140*/ @!P0 FADD R0, R0, R5 ; /* 0x0000000500008221 */
/* 0x004fca0000000000 */
/*0150*/ STS [R7.X4], R0 ; /* 0x0000000007007388 */
/* 0x0001e80000004800 */
/*0160*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0170*/ @!P2 BRA 0x230 ; /* 0x000000b00000a947 */
/* 0x000fea0003800000 */
/*0180*/ SHF.L.U32 R2, R7, 0x2, RZ ; /* 0x0000000207027819 */
/* 0x001fe200000006ff */
/*0190*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fca000f8e00ff */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R7, R3, PT ; /* 0x000000030700720c */
/* 0x000fda0003f06070 */
/*01b0*/ @!P0 LEA R4, R3, R2, 0x2 ; /* 0x0000000203048211 */
/* 0x000fe400078e10ff */
/*01c0*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc60000011603 */
/*01d0*/ @!P0 LDS R5, [R4] ; /* 0x0000000004058984 */
/* 0x000e240000000800 */
/*01e0*/ @!P0 FADD R0, R0, R5 ; /* 0x0000000500008221 */
/* 0x001fca0000000000 */
/*01f0*/ @!P0 STS [R7.X4], R0 ; /* 0x0000000007008388 */
/* 0x0001e80000004800 */
/*0200*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0210*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*0220*/ @P0 BRA 0x1a0 ; /* 0xffffff7000000947 */
/* 0x001fea000383ffff */
/*0230*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x001fea0003800000 */
/*0240*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*0250*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0260*/ IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fca00078e0003 */
/*0270*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*0280*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0290*/ BRA 0x290; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5totalPfS_j
.globl _Z5totalPfS_j
.p2align 8
.type _Z5totalPfS_j,@function
_Z5totalPfS_j:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s6, s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x0
v_mov_b32_e32 v3, 0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s7, s15, s3
v_lshl_add_u32 v1, s7, 1, v0
s_mov_b32 s7, exec_lo
v_cmpx_gt_u32_e64 s6, v0
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v3, v[2:3], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s7
v_add_nc_u32_e32 v1, s3, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u32_e32 vcc_lo, s6, v1
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz .LBB0_4
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, v3, v1
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s6
v_lshlrev_b32_e32 v1, 2, v0
s_cmp_lt_u32 s3, 2
s_waitcnt vmcnt(0)
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s3, 4
s_mov_b32 s3, s4
.LBB0_6:
buffer_gl0_inv
s_cbranch_scc1 .LBB0_9
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_5
v_add_lshl_u32 v2, s4, v0, 2
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v3, v3, v2
ds_store_b32 v1, v3
s_branch .LBB0_5
.LBB0_9:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_11
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5totalPfS_j
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5totalPfS_j, .Lfunc_end0-_Z5totalPfS_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5totalPfS_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5totalPfS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00015a86_00000000-6_total.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z5totalPfS_jPfS_j
.type _Z27__device_stub__Z5totalPfS_jPfS_j, @function
_Z27__device_stub__Z5totalPfS_jPfS_j:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5totalPfS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z5totalPfS_jPfS_j, .-_Z27__device_stub__Z5totalPfS_jPfS_j
.globl _Z5totalPfS_j
.type _Z5totalPfS_j, @function
_Z5totalPfS_j:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z5totalPfS_jPfS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z5totalPfS_j, .-_Z5totalPfS_j
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5totalPfS_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5totalPfS_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "total.hip"
.globl _Z20__device_stub__totalPfS_j # -- Begin function _Z20__device_stub__totalPfS_j
.p2align 4, 0x90
.type _Z20__device_stub__totalPfS_j,@function
_Z20__device_stub__totalPfS_j: # @_Z20__device_stub__totalPfS_j
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5totalPfS_j, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z20__device_stub__totalPfS_j, .Lfunc_end0-_Z20__device_stub__totalPfS_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5totalPfS_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5totalPfS_j,@object # @_Z5totalPfS_j
.section .rodata,"a",@progbits
.globl _Z5totalPfS_j
.p2align 3, 0x0
_Z5totalPfS_j:
.quad _Z20__device_stub__totalPfS_j
.size _Z5totalPfS_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5totalPfS_j"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__totalPfS_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5totalPfS_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "stdio.h"
int main(){
// define total data elements
int nElem = 1024;
// define grid and block structure
dim3 block(1024);
dim3 grid((nElem+block.x-1)/block.x);
printf("grid.x: %d block.x %d \n", grid.x, block.x);
// reset block
block.x = 512;
grid.x = (nElem+block.x-1)/block.x;
printf("grid.x: %d block.x %d \n", grid.x, block.x);
// reset block
block.x = 256;
grid.x = (nElem+block.x-1)/block.x;
printf("grid.x: %d block.x %d \n", grid.x, block.x);
// reset block
block.x = 128;
grid.x = (nElem+block.x-1)/block.x;
printf("grid.x: %d block.x %d \n", grid.x, block.x);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "stdio.h"
int main(){
// define total data elements
int nElem = 1024;
// define grid and block structure
dim3 block(1024);
dim3 grid((nElem+block.x-1)/block.x);
printf("grid.x: %d block.x %d \n", grid.x, block.x);
// reset block
block.x = 512;
grid.x = (nElem+block.x-1)/block.x;
printf("grid.x: %d block.x %d \n", grid.x, block.x);
// reset block
block.x = 256;
grid.x = (nElem+block.x-1)/block.x;
printf("grid.x: %d block.x %d \n", grid.x, block.x);
// reset block
block.x = 128;
grid.x = (nElem+block.x-1)/block.x;
printf("grid.x: %d block.x %d \n", grid.x, block.x);
} | .file "tmpxft_000dcbb9_00000000-6_defineGridBlock.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "grid.x: %d block.x %d \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl $1024, %ecx
movl $1, %edx
leaq .LC0(%rip), %rbx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $512, %ecx
movl $2, %edx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $256, %ecx
movl $4, %edx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $128, %ecx
movl $8, %edx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "stdio.h"
int main(){
// define total data elements
int nElem = 1024;
// define grid and block structure
dim3 block(1024);
dim3 grid((nElem+block.x-1)/block.x);
printf("grid.x: %d block.x %d \n", grid.x, block.x);
// reset block
block.x = 512;
grid.x = (nElem+block.x-1)/block.x;
printf("grid.x: %d block.x %d \n", grid.x, block.x);
// reset block
block.x = 256;
grid.x = (nElem+block.x-1)/block.x;
printf("grid.x: %d block.x %d \n", grid.x, block.x);
// reset block
block.x = 128;
grid.x = (nElem+block.x-1)/block.x;
printf("grid.x: %d block.x %d \n", grid.x, block.x);
} | #include "hip/hip_runtime.h"
#include "stdio.h"
int main(){
// define total data elements
int nElem = 1024;
// define grid and block structure
dim3 block(1024);
dim3 grid((nElem+block.x-1)/block.x);
printf("grid.x: %d block.x %d \n", grid.x, block.x);
// reset block
block.x = 512;
grid.x = (nElem+block.x-1)/block.x;
printf("grid.x: %d block.x %d \n", grid.x, block.x);
// reset block
block.x = 256;
grid.x = (nElem+block.x-1)/block.x;
printf("grid.x: %d block.x %d \n", grid.x, block.x);
// reset block
block.x = 128;
grid.x = (nElem+block.x-1)/block.x;
printf("grid.x: %d block.x %d \n", grid.x, block.x);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include "stdio.h"
int main(){
// define total data elements
int nElem = 1024;
// define grid and block structure
dim3 block(1024);
dim3 grid((nElem+block.x-1)/block.x);
printf("grid.x: %d block.x %d \n", grid.x, block.x);
// reset block
block.x = 512;
grid.x = (nElem+block.x-1)/block.x;
printf("grid.x: %d block.x %d \n", grid.x, block.x);
// reset block
block.x = 256;
grid.x = (nElem+block.x-1)/block.x;
printf("grid.x: %d block.x %d \n", grid.x, block.x);
// reset block
block.x = 128;
grid.x = (nElem+block.x-1)/block.x;
printf("grid.x: %d block.x %d \n", grid.x, block.x);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include "stdio.h"
int main(){
// define total data elements
int nElem = 1024;
// define grid and block structure
dim3 block(1024);
dim3 grid((nElem+block.x-1)/block.x);
printf("grid.x: %d block.x %d \n", grid.x, block.x);
// reset block
block.x = 512;
grid.x = (nElem+block.x-1)/block.x;
printf("grid.x: %d block.x %d \n", grid.x, block.x);
// reset block
block.x = 256;
grid.x = (nElem+block.x-1)/block.x;
printf("grid.x: %d block.x %d \n", grid.x, block.x);
// reset block
block.x = 128;
grid.x = (nElem+block.x-1)/block.x;
printf("grid.x: %d block.x %d \n", grid.x, block.x);
} | .text
.file "defineGridBlock.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.L.str, %edi
movl $1, %esi
movl $1024, %edx # imm = 0x400
xorl %eax, %eax
callq printf
movl $.L.str, %edi
movl $2, %esi
movl $512, %edx # imm = 0x200
xorl %eax, %eax
callq printf
movl $.L.str, %edi
movl $4, %esi
movl $256, %edx # imm = 0x100
xorl %eax, %eax
callq printf
movl $.L.str, %edi
movl $8, %esi
movl $128, %edx
xorl %eax, %eax
callq printf
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "grid.x: %d block.x %d \n"
.size .L.str, 26
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000dcbb9_00000000-6_defineGridBlock.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "grid.x: %d block.x %d \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl $1024, %ecx
movl $1, %edx
leaq .LC0(%rip), %rbx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $512, %ecx
movl $2, %edx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $256, %ecx
movl $4, %edx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $128, %ecx
movl $8, %edx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "defineGridBlock.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.L.str, %edi
movl $1, %esi
movl $1024, %edx # imm = 0x400
xorl %eax, %eax
callq printf
movl $.L.str, %edi
movl $2, %esi
movl $512, %edx # imm = 0x200
xorl %eax, %eax
callq printf
movl $.L.str, %edi
movl $4, %esi
movl $256, %edx # imm = 0x100
xorl %eax, %eax
callq printf
movl $.L.str, %edi
movl $8, %esi
movl $128, %edx
xorl %eax, %eax
callq printf
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "grid.x: %d block.x %d \n"
.size .L.str, 26
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | # include <iostream>
// # include "book.h"
__global__ void kernel ( void )
{
}
__global__ void add( int a, int b, int *c )
{
*c = a + b;
}
int main(int argc, char const *argv[])
{
// kernel<<<1, 1>>>();
// printf( "Hello, World!\n");
// int c;
// int *dev_c;
// int N = 1;
// cudaMalloc( (void**)&dev_c, N * sizeof(int) );
// add<<<1, N>>>( 2, 7 , dev_c);
// cudaMemcpy ( &c, dev_c, N * sizeof(int),
// cudaMemcpyDeviceToHost );
// printf("2 + 7 = %d\n", c);
// cudaFree( dev_c);
/* Below are the codes for detecting CUDA capable devices and
* output some useful information of the deives for references
* by Wu Zheshu, May 18, 2018
*/
int cudaDeviceCount;
cudaGetDeviceCount( &cudaDeviceCount );
printf("\nDetected %d CUDA device(s) on this computer\n", cudaDeviceCount);
cudaDeviceProp prop; // cudaDeviceProp is a built-in struct
// list all the detected devices
for (int i=0; i < cudaDeviceCount; i++)
{
cudaGetDeviceProperties( &prop, i );
printf(" --- General Information for Device %d ---\n", i );
printf("\tDevice name:\t\t %s\n", prop.name );
printf("\tCompute capability:\t %d.%d\n", prop.major, prop.minor );
printf("\tClock rate:\t\t %d\n", prop.clockRate );
printf(" --- Memory Information for device %d ---\n", i );
printf("\tTotal global mem:\t %f\n", prop.totalGlobalMem );
//[Caution] Here the type of totalGlobalMem is "size_t", might
// output some erroneous number if the type is not set correctly
printf("\tTotal constant Mem:\t %ld\n", prop.totalConstMem );
//[Caution] Here the type of totalConstMem is "size_t"
printf(" --- MP Information for device %d ---\n", i );
printf("\tMultiprocessor count:\t %d\n", prop.multiProcessorCount );
printf("\tShared mem per mp:\t %ld\n", prop.sharedMemPerBlock );
printf("\tRegisters per mp:\t %d\n", prop.regsPerBlock );
printf("\tThreads in warp:\t %d\n", prop.warpSize );
printf("\tMax threads per block:\t %d\n", prop.maxThreadsPerBlock );
printf("\tMax thread dimensions:\t (%d, %d, %d)\n",
prop.maxThreadsDim[0], prop.maxThreadsDim[1],
prop.maxThreadsDim[2] );
printf("\tMax grid dimensions:\t (%f, %d, %d)\n",
prop.maxGridSize[0], prop.maxGridSize[1],
prop.maxGridSize[2] );
printf("\n" );
}
return 0;
} | code for sm_80
Function : _Z3addiiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fe40000000f00 */
/*0050*/ IADD3 R5, R5, c[0x0][0x160], RZ ; /* 0x0000580005057a10 */
/* 0x000fca0007ffe0ff */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z6kernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | # include <iostream>
// # include "book.h"
__global__ void kernel ( void )
{
}
__global__ void add( int a, int b, int *c )
{
*c = a + b;
}
int main(int argc, char const *argv[])
{
// kernel<<<1, 1>>>();
// printf( "Hello, World!\n");
// int c;
// int *dev_c;
// int N = 1;
// cudaMalloc( (void**)&dev_c, N * sizeof(int) );
// add<<<1, N>>>( 2, 7 , dev_c);
// cudaMemcpy ( &c, dev_c, N * sizeof(int),
// cudaMemcpyDeviceToHost );
// printf("2 + 7 = %d\n", c);
// cudaFree( dev_c);
/* Below are the codes for detecting CUDA capable devices and
* output some useful information of the deives for references
* by Wu Zheshu, May 18, 2018
*/
int cudaDeviceCount;
cudaGetDeviceCount( &cudaDeviceCount );
printf("\nDetected %d CUDA device(s) on this computer\n", cudaDeviceCount);
cudaDeviceProp prop; // cudaDeviceProp is a built-in struct
// list all the detected devices
for (int i=0; i < cudaDeviceCount; i++)
{
cudaGetDeviceProperties( &prop, i );
printf(" --- General Information for Device %d ---\n", i );
printf("\tDevice name:\t\t %s\n", prop.name );
printf("\tCompute capability:\t %d.%d\n", prop.major, prop.minor );
printf("\tClock rate:\t\t %d\n", prop.clockRate );
printf(" --- Memory Information for device %d ---\n", i );
printf("\tTotal global mem:\t %f\n", prop.totalGlobalMem );
//[Caution] Here the type of totalGlobalMem is "size_t", might
// output some erroneous number if the type is not set correctly
printf("\tTotal constant Mem:\t %ld\n", prop.totalConstMem );
//[Caution] Here the type of totalConstMem is "size_t"
printf(" --- MP Information for device %d ---\n", i );
printf("\tMultiprocessor count:\t %d\n", prop.multiProcessorCount );
printf("\tShared mem per mp:\t %ld\n", prop.sharedMemPerBlock );
printf("\tRegisters per mp:\t %d\n", prop.regsPerBlock );
printf("\tThreads in warp:\t %d\n", prop.warpSize );
printf("\tMax threads per block:\t %d\n", prop.maxThreadsPerBlock );
printf("\tMax thread dimensions:\t (%d, %d, %d)\n",
prop.maxThreadsDim[0], prop.maxThreadsDim[1],
prop.maxThreadsDim[2] );
printf("\tMax grid dimensions:\t (%f, %d, %d)\n",
prop.maxGridSize[0], prop.maxGridSize[1],
prop.maxGridSize[2] );
printf("\n" );
}
return 0;
} | .file "tmpxft_00118ae7_00000000-6_cudaTest.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "\nDetected %d CUDA device(s) on this computer\n"
.align 8
.LC1:
.string " --- General Information for Device %d ---\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "\tDevice name:\t\t %s\n"
.LC3:
.string "\tCompute capability:\t %d.%d\n"
.LC4:
.string "\tClock rate:\t\t %d\n"
.section .rodata.str1.8
.align 8
.LC5:
.string " --- Memory Information for device %d ---\n"
.section .rodata.str1.1
.LC6:
.string "\tTotal global mem:\t %f\n"
.LC7:
.string "\tTotal constant Mem:\t %ld\n"
.section .rodata.str1.8
.align 8
.LC8:
.string " --- MP Information for device %d ---\n"
.section .rodata.str1.1
.LC9:
.string "\tMultiprocessor count:\t %d\n"
.LC10:
.string "\tShared mem per mp:\t %ld\n"
.LC11:
.string "\tRegisters per mp:\t %d\n"
.LC12:
.string "\tThreads in warp:\t %d\n"
.LC13:
.string "\tMax threads per block:\t %d\n"
.section .rodata.str1.8
.align 8
.LC14:
.string "\tMax thread dimensions:\t (%d, %d, %d)\n"
.align 8
.LC15:
.string "\tMax grid dimensions:\t (%f, %d, %d)\n"
.section .rodata.str1.1
.LC16:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1064, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 12(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 12(%rsp)
jle .L4
movl $0, %ebx
leaq .LC1(%rip), %r15
leaq .LC2(%rip), %r14
leaq .LC3(%rip), %r13
leaq .LC4(%rip), %r12
.L5:
leaq 16(%rsp), %rbp
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
movl %ebx, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 380(%rsp), %ecx
movl 376(%rsp), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 364(%rsp), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 304(%rsp), %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 368(%rsp), %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 404(%rsp), %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 312(%rsp), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 320(%rsp), %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 324(%rsp), %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 348(%rsp), %r8d
movl 344(%rsp), %ecx
movl 340(%rsp), %edx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 360(%rsp), %r8d
movl 356(%rsp), %ecx
movl 352(%rsp), %edx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jg .L5
.L4:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L9
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.globl _Z24__device_stub__Z6kernelvv
.type _Z24__device_stub__Z6kernelvv, @function
_Z24__device_stub__Z6kernelvv:
.LFB3694:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L14
.L10:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z6kernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L10
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z24__device_stub__Z6kernelvv, .-_Z24__device_stub__Z6kernelvv
.globl _Z6kernelv
.type _Z6kernelv, @function
_Z6kernelv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z6kernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z6kernelv, .-_Z6kernelv
.globl _Z24__device_stub__Z3addiiPiiiPi
.type _Z24__device_stub__Z3addiiPiiiPi, @function
_Z24__device_stub__Z3addiiPiiiPi:
.LFB3696:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L22
.L18:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L23
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3addiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L18
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z24__device_stub__Z3addiiPiiiPi, .-_Z24__device_stub__Z3addiiPiiiPi
.globl _Z3addiiPi
.type _Z3addiiPi, @function
_Z3addiiPi:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3addiiPiiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z3addiiPi, .-_Z3addiiPi
.section .rodata.str1.1
.LC17:
.string "_Z3addiiPi"
.LC18:
.string "_Z6kernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiiPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelv(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | # include <iostream>
// # include "book.h"
__global__ void kernel ( void )
{
}
__global__ void add( int a, int b, int *c )
{
*c = a + b;
}
int main(int argc, char const *argv[])
{
// kernel<<<1, 1>>>();
// printf( "Hello, World!\n");
// int c;
// int *dev_c;
// int N = 1;
// cudaMalloc( (void**)&dev_c, N * sizeof(int) );
// add<<<1, N>>>( 2, 7 , dev_c);
// cudaMemcpy ( &c, dev_c, N * sizeof(int),
// cudaMemcpyDeviceToHost );
// printf("2 + 7 = %d\n", c);
// cudaFree( dev_c);
/* Below are the codes for detecting CUDA capable devices and
* output some useful information of the deives for references
* by Wu Zheshu, May 18, 2018
*/
int cudaDeviceCount;
cudaGetDeviceCount( &cudaDeviceCount );
printf("\nDetected %d CUDA device(s) on this computer\n", cudaDeviceCount);
cudaDeviceProp prop; // cudaDeviceProp is a built-in struct
// list all the detected devices
for (int i=0; i < cudaDeviceCount; i++)
{
cudaGetDeviceProperties( &prop, i );
printf(" --- General Information for Device %d ---\n", i );
printf("\tDevice name:\t\t %s\n", prop.name );
printf("\tCompute capability:\t %d.%d\n", prop.major, prop.minor );
printf("\tClock rate:\t\t %d\n", prop.clockRate );
printf(" --- Memory Information for device %d ---\n", i );
printf("\tTotal global mem:\t %f\n", prop.totalGlobalMem );
//[Caution] Here the type of totalGlobalMem is "size_t", might
// output some erroneous number if the type is not set correctly
printf("\tTotal constant Mem:\t %ld\n", prop.totalConstMem );
//[Caution] Here the type of totalConstMem is "size_t"
printf(" --- MP Information for device %d ---\n", i );
printf("\tMultiprocessor count:\t %d\n", prop.multiProcessorCount );
printf("\tShared mem per mp:\t %ld\n", prop.sharedMemPerBlock );
printf("\tRegisters per mp:\t %d\n", prop.regsPerBlock );
printf("\tThreads in warp:\t %d\n", prop.warpSize );
printf("\tMax threads per block:\t %d\n", prop.maxThreadsPerBlock );
printf("\tMax thread dimensions:\t (%d, %d, %d)\n",
prop.maxThreadsDim[0], prop.maxThreadsDim[1],
prop.maxThreadsDim[2] );
printf("\tMax grid dimensions:\t (%f, %d, %d)\n",
prop.maxGridSize[0], prop.maxGridSize[1],
prop.maxGridSize[2] );
printf("\n" );
}
return 0;
} | #include <hip/hip_runtime.h>
# include <iostream>
// # include "book.h"
__global__ void kernel ( void )
{
}
__global__ void add( int a, int b, int *c )
{
*c = a + b;
}
int main(int argc, char const *argv[])
{
// kernel<<<1, 1>>>();
// printf( "Hello, World!\n");
// int c;
// int *dev_c;
// int N = 1;
// cudaMalloc( (void**)&dev_c, N * sizeof(int) );
// add<<<1, N>>>( 2, 7 , dev_c);
// cudaMemcpy ( &c, dev_c, N * sizeof(int),
// cudaMemcpyDeviceToHost );
// printf("2 + 7 = %d\n", c);
// cudaFree( dev_c);
/* Below are the codes for detecting CUDA capable devices and
* output some useful information of the deives for references
* by Wu Zheshu, May 18, 2018
*/
int cudaDeviceCount;
hipGetDeviceCount( &cudaDeviceCount );
printf("\nDetected %d CUDA device(s) on this computer\n", cudaDeviceCount);
hipDeviceProp_t prop; // cudaDeviceProp is a built-in struct
// list all the detected devices
for (int i=0; i < cudaDeviceCount; i++)
{
hipGetDeviceProperties( &prop, i );
printf(" --- General Information for Device %d ---\n", i );
printf("\tDevice name:\t\t %s\n", prop.name );
printf("\tCompute capability:\t %d.%d\n", prop.major, prop.minor );
printf("\tClock rate:\t\t %d\n", prop.clockRate );
printf(" --- Memory Information for device %d ---\n", i );
printf("\tTotal global mem:\t %f\n", prop.totalGlobalMem );
//[Caution] Here the type of totalGlobalMem is "size_t", might
// output some erroneous number if the type is not set correctly
printf("\tTotal constant Mem:\t %ld\n", prop.totalConstMem );
//[Caution] Here the type of totalConstMem is "size_t"
printf(" --- MP Information for device %d ---\n", i );
printf("\tMultiprocessor count:\t %d\n", prop.multiProcessorCount );
printf("\tShared mem per mp:\t %ld\n", prop.sharedMemPerBlock );
printf("\tRegisters per mp:\t %d\n", prop.regsPerBlock );
printf("\tThreads in warp:\t %d\n", prop.warpSize );
printf("\tMax threads per block:\t %d\n", prop.maxThreadsPerBlock );
printf("\tMax thread dimensions:\t (%d, %d, %d)\n",
prop.maxThreadsDim[0], prop.maxThreadsDim[1],
prop.maxThreadsDim[2] );
printf("\tMax grid dimensions:\t (%f, %d, %d)\n",
prop.maxGridSize[0], prop.maxGridSize[1],
prop.maxGridSize[2] );
printf("\n" );
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
# include <iostream>
// # include "book.h"
__global__ void kernel ( void )
{
}
__global__ void add( int a, int b, int *c )
{
*c = a + b;
}
int main(int argc, char const *argv[])
{
// kernel<<<1, 1>>>();
// printf( "Hello, World!\n");
// int c;
// int *dev_c;
// int N = 1;
// cudaMalloc( (void**)&dev_c, N * sizeof(int) );
// add<<<1, N>>>( 2, 7 , dev_c);
// cudaMemcpy ( &c, dev_c, N * sizeof(int),
// cudaMemcpyDeviceToHost );
// printf("2 + 7 = %d\n", c);
// cudaFree( dev_c);
/* Below are the codes for detecting CUDA capable devices and
* output some useful information of the deives for references
* by Wu Zheshu, May 18, 2018
*/
int cudaDeviceCount;
hipGetDeviceCount( &cudaDeviceCount );
printf("\nDetected %d CUDA device(s) on this computer\n", cudaDeviceCount);
hipDeviceProp_t prop; // cudaDeviceProp is a built-in struct
// list all the detected devices
for (int i=0; i < cudaDeviceCount; i++)
{
hipGetDeviceProperties( &prop, i );
printf(" --- General Information for Device %d ---\n", i );
printf("\tDevice name:\t\t %s\n", prop.name );
printf("\tCompute capability:\t %d.%d\n", prop.major, prop.minor );
printf("\tClock rate:\t\t %d\n", prop.clockRate );
printf(" --- Memory Information for device %d ---\n", i );
printf("\tTotal global mem:\t %f\n", prop.totalGlobalMem );
//[Caution] Here the type of totalGlobalMem is "size_t", might
// output some erroneous number if the type is not set correctly
printf("\tTotal constant Mem:\t %ld\n", prop.totalConstMem );
//[Caution] Here the type of totalConstMem is "size_t"
printf(" --- MP Information for device %d ---\n", i );
printf("\tMultiprocessor count:\t %d\n", prop.multiProcessorCount );
printf("\tShared mem per mp:\t %ld\n", prop.sharedMemPerBlock );
printf("\tRegisters per mp:\t %d\n", prop.regsPerBlock );
printf("\tThreads in warp:\t %d\n", prop.warpSize );
printf("\tMax threads per block:\t %d\n", prop.maxThreadsPerBlock );
printf("\tMax thread dimensions:\t (%d, %d, %d)\n",
prop.maxThreadsDim[0], prop.maxThreadsDim[1],
prop.maxThreadsDim[2] );
printf("\tMax grid dimensions:\t (%f, %d, %d)\n",
prop.maxGridSize[0], prop.maxGridSize[1],
prop.maxGridSize[2] );
printf("\n" );
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelv
.globl _Z6kernelv
.p2align 8
.type _Z6kernelv,@function
_Z6kernelv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelv, .Lfunc_end0-_Z6kernelv
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3addiiPi
.globl _Z3addiiPi
.p2align 8
.type _Z3addiiPi,@function
_Z3addiiPi:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z3addiiPi, .Lfunc_end1-_Z3addiiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z6kernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiiPi
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z3addiiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
# include <iostream>
// # include "book.h"
__global__ void kernel ( void )
{
}
__global__ void add( int a, int b, int *c )
{
*c = a + b;
}
int main(int argc, char const *argv[])
{
// kernel<<<1, 1>>>();
// printf( "Hello, World!\n");
// int c;
// int *dev_c;
// int N = 1;
// cudaMalloc( (void**)&dev_c, N * sizeof(int) );
// add<<<1, N>>>( 2, 7 , dev_c);
// cudaMemcpy ( &c, dev_c, N * sizeof(int),
// cudaMemcpyDeviceToHost );
// printf("2 + 7 = %d\n", c);
// cudaFree( dev_c);
/* Below are the codes for detecting CUDA capable devices and
* output some useful information of the deives for references
* by Wu Zheshu, May 18, 2018
*/
int cudaDeviceCount;
hipGetDeviceCount( &cudaDeviceCount );
printf("\nDetected %d CUDA device(s) on this computer\n", cudaDeviceCount);
hipDeviceProp_t prop; // cudaDeviceProp is a built-in struct
// list all the detected devices
for (int i=0; i < cudaDeviceCount; i++)
{
hipGetDeviceProperties( &prop, i );
printf(" --- General Information for Device %d ---\n", i );
printf("\tDevice name:\t\t %s\n", prop.name );
printf("\tCompute capability:\t %d.%d\n", prop.major, prop.minor );
printf("\tClock rate:\t\t %d\n", prop.clockRate );
printf(" --- Memory Information for device %d ---\n", i );
printf("\tTotal global mem:\t %f\n", prop.totalGlobalMem );
//[Caution] Here the type of totalGlobalMem is "size_t", might
// output some erroneous number if the type is not set correctly
printf("\tTotal constant Mem:\t %ld\n", prop.totalConstMem );
//[Caution] Here the type of totalConstMem is "size_t"
printf(" --- MP Information for device %d ---\n", i );
printf("\tMultiprocessor count:\t %d\n", prop.multiProcessorCount );
printf("\tShared mem per mp:\t %ld\n", prop.sharedMemPerBlock );
printf("\tRegisters per mp:\t %d\n", prop.regsPerBlock );
printf("\tThreads in warp:\t %d\n", prop.warpSize );
printf("\tMax threads per block:\t %d\n", prop.maxThreadsPerBlock );
printf("\tMax thread dimensions:\t (%d, %d, %d)\n",
prop.maxThreadsDim[0], prop.maxThreadsDim[1],
prop.maxThreadsDim[2] );
printf("\tMax grid dimensions:\t (%f, %d, %d)\n",
prop.maxGridSize[0], prop.maxGridSize[1],
prop.maxGridSize[2] );
printf("\n" );
}
return 0;
} | .text
.file "cudaTest.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__kernelv # -- Begin function _Z21__device_stub__kernelv
.p2align 4, 0x90
.type _Z21__device_stub__kernelv,@function
_Z21__device_stub__kernelv: # @_Z21__device_stub__kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelv, .Lfunc_end0-_Z21__device_stub__kernelv
.cfi_endproc
# -- End function
.globl _Z18__device_stub__addiiPi # -- Begin function _Z18__device_stub__addiiPi
.p2align 4, 0x90
.type _Z18__device_stub__addiiPi,@function
_Z18__device_stub__addiiPi: # @_Z18__device_stub__addiiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3addiiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z18__device_stub__addiiPi, .Lfunc_end1-_Z18__device_stub__addiiPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
movl 4(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
cmpl $0, 4(%rsp)
jle .LBB2_3
# %bb.1: # %.lr.ph
leaq 8(%rsp), %rbx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_2: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.1, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl 368(%rsp), %esi
movl 372(%rsp), %edx
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl 356(%rsp), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl $.L.str.5, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movq 296(%rsp), %rsi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movq 360(%rsp), %rsi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl $.L.str.8, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movl 396(%rsp), %esi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movq 304(%rsp), %rsi
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movl 312(%rsp), %esi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movl 316(%rsp), %esi
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
movl 328(%rsp), %esi
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
movl 332(%rsp), %esi
movl 336(%rsp), %edx
movl 340(%rsp), %ecx
movl $.L.str.14, %edi
xorl %eax, %eax
callq printf
movl 344(%rsp), %esi
movl 348(%rsp), %edx
movl 352(%rsp), %ecx
movl $.L.str.15, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
incl %ebp
cmpl 4(%rsp), %ebp
jl .LBB2_2
.LBB2_3: # %._crit_edge
xorl %eax, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiiPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelv,@object # @_Z6kernelv
.section .rodata,"a",@progbits
.globl _Z6kernelv
.p2align 3, 0x0
_Z6kernelv:
.quad _Z21__device_stub__kernelv
.size _Z6kernelv, 8
.type _Z3addiiPi,@object # @_Z3addiiPi
.globl _Z3addiiPi
.p2align 3, 0x0
_Z3addiiPi:
.quad _Z18__device_stub__addiiPi
.size _Z3addiiPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nDetected %d CUDA device(s) on this computer\n"
.size .L.str, 46
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " --- General Information for Device %d ---\n"
.size .L.str.1, 44
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\tDevice name:\t\t %s\n"
.size .L.str.2, 20
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\tCompute capability:\t %d.%d\n"
.size .L.str.3, 29
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\tClock rate:\t\t %d\n"
.size .L.str.4, 19
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " --- Memory Information for device %d ---\n"
.size .L.str.5, 43
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\tTotal global mem:\t %f\n"
.size .L.str.6, 24
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "\tTotal constant Mem:\t %ld\n"
.size .L.str.7, 27
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz " --- MP Information for device %d ---\n"
.size .L.str.8, 39
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "\tMultiprocessor count:\t %d\n"
.size .L.str.9, 28
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "\tShared mem per mp:\t %ld\n"
.size .L.str.10, 26
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "\tRegisters per mp:\t %d\n"
.size .L.str.11, 24
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "\tThreads in warp:\t %d\n"
.size .L.str.12, 23
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "\tMax threads per block:\t %d\n"
.size .L.str.13, 29
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "\tMax thread dimensions:\t (%d, %d, %d)\n"
.size .L.str.14, 39
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "\tMax grid dimensions:\t (%f, %d, %d)\n"
.size .L.str.15, 37
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelv"
.size .L__unnamed_1, 11
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z3addiiPi"
.size .L__unnamed_2, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelv
.addrsig_sym _Z18__device_stub__addiiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelv
.addrsig_sym _Z3addiiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addiiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fe40000000f00 */
/*0050*/ IADD3 R5, R5, c[0x0][0x160], RZ ; /* 0x0000580005057a10 */
/* 0x000fca0007ffe0ff */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z6kernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelv
.globl _Z6kernelv
.p2align 8
.type _Z6kernelv,@function
_Z6kernelv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelv, .Lfunc_end0-_Z6kernelv
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3addiiPi
.globl _Z3addiiPi
.p2align 8
.type _Z3addiiPi,@function
_Z3addiiPi:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z3addiiPi, .Lfunc_end1-_Z3addiiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z6kernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiiPi
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z3addiiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00118ae7_00000000-6_cudaTest.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "\nDetected %d CUDA device(s) on this computer\n"
.align 8
.LC1:
.string " --- General Information for Device %d ---\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "\tDevice name:\t\t %s\n"
.LC3:
.string "\tCompute capability:\t %d.%d\n"
.LC4:
.string "\tClock rate:\t\t %d\n"
.section .rodata.str1.8
.align 8
.LC5:
.string " --- Memory Information for device %d ---\n"
.section .rodata.str1.1
.LC6:
.string "\tTotal global mem:\t %f\n"
.LC7:
.string "\tTotal constant Mem:\t %ld\n"
.section .rodata.str1.8
.align 8
.LC8:
.string " --- MP Information for device %d ---\n"
.section .rodata.str1.1
.LC9:
.string "\tMultiprocessor count:\t %d\n"
.LC10:
.string "\tShared mem per mp:\t %ld\n"
.LC11:
.string "\tRegisters per mp:\t %d\n"
.LC12:
.string "\tThreads in warp:\t %d\n"
.LC13:
.string "\tMax threads per block:\t %d\n"
.section .rodata.str1.8
.align 8
.LC14:
.string "\tMax thread dimensions:\t (%d, %d, %d)\n"
.align 8
.LC15:
.string "\tMax grid dimensions:\t (%f, %d, %d)\n"
.section .rodata.str1.1
.LC16:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1064, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 12(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 12(%rsp)
jle .L4
movl $0, %ebx
leaq .LC1(%rip), %r15
leaq .LC2(%rip), %r14
leaq .LC3(%rip), %r13
leaq .LC4(%rip), %r12
.L5:
leaq 16(%rsp), %rbp
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
movl %ebx, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 380(%rsp), %ecx
movl 376(%rsp), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 364(%rsp), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 304(%rsp), %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 368(%rsp), %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 404(%rsp), %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 312(%rsp), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 320(%rsp), %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 324(%rsp), %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 348(%rsp), %r8d
movl 344(%rsp), %ecx
movl 340(%rsp), %edx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 360(%rsp), %r8d
movl 356(%rsp), %ecx
movl 352(%rsp), %edx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jg .L5
.L4:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L9
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.globl _Z24__device_stub__Z6kernelvv
.type _Z24__device_stub__Z6kernelvv, @function
_Z24__device_stub__Z6kernelvv:
.LFB3694:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L14
.L10:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z6kernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L10
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z24__device_stub__Z6kernelvv, .-_Z24__device_stub__Z6kernelvv
.globl _Z6kernelv
.type _Z6kernelv, @function
_Z6kernelv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z6kernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z6kernelv, .-_Z6kernelv
.globl _Z24__device_stub__Z3addiiPiiiPi
.type _Z24__device_stub__Z3addiiPiiiPi, @function
_Z24__device_stub__Z3addiiPiiiPi:
.LFB3696:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L22
.L18:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L23
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3addiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L18
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z24__device_stub__Z3addiiPiiiPi, .-_Z24__device_stub__Z3addiiPiiiPi
.globl _Z3addiiPi
.type _Z3addiiPi, @function
_Z3addiiPi:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3addiiPiiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z3addiiPi, .-_Z3addiiPi
.section .rodata.str1.1
.LC17:
.string "_Z3addiiPi"
.LC18:
.string "_Z6kernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiiPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelv(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cudaTest.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__kernelv # -- Begin function _Z21__device_stub__kernelv
.p2align 4, 0x90
.type _Z21__device_stub__kernelv,@function
_Z21__device_stub__kernelv: # @_Z21__device_stub__kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelv, .Lfunc_end0-_Z21__device_stub__kernelv
.cfi_endproc
# -- End function
.globl _Z18__device_stub__addiiPi # -- Begin function _Z18__device_stub__addiiPi
.p2align 4, 0x90
.type _Z18__device_stub__addiiPi,@function
_Z18__device_stub__addiiPi: # @_Z18__device_stub__addiiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3addiiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z18__device_stub__addiiPi, .Lfunc_end1-_Z18__device_stub__addiiPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
movl 4(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
cmpl $0, 4(%rsp)
jle .LBB2_3
# %bb.1: # %.lr.ph
leaq 8(%rsp), %rbx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_2: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.1, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl 368(%rsp), %esi
movl 372(%rsp), %edx
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl 356(%rsp), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl $.L.str.5, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movq 296(%rsp), %rsi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movq 360(%rsp), %rsi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl $.L.str.8, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movl 396(%rsp), %esi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movq 304(%rsp), %rsi
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movl 312(%rsp), %esi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movl 316(%rsp), %esi
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
movl 328(%rsp), %esi
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
movl 332(%rsp), %esi
movl 336(%rsp), %edx
movl 340(%rsp), %ecx
movl $.L.str.14, %edi
xorl %eax, %eax
callq printf
movl 344(%rsp), %esi
movl 348(%rsp), %edx
movl 352(%rsp), %ecx
movl $.L.str.15, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
incl %ebp
cmpl 4(%rsp), %ebp
jl .LBB2_2
.LBB2_3: # %._crit_edge
xorl %eax, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiiPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelv,@object # @_Z6kernelv
.section .rodata,"a",@progbits
.globl _Z6kernelv
.p2align 3, 0x0
_Z6kernelv:
.quad _Z21__device_stub__kernelv
.size _Z6kernelv, 8
.type _Z3addiiPi,@object # @_Z3addiiPi
.globl _Z3addiiPi
.p2align 3, 0x0
_Z3addiiPi:
.quad _Z18__device_stub__addiiPi
.size _Z3addiiPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nDetected %d CUDA device(s) on this computer\n"
.size .L.str, 46
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " --- General Information for Device %d ---\n"
.size .L.str.1, 44
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\tDevice name:\t\t %s\n"
.size .L.str.2, 20
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\tCompute capability:\t %d.%d\n"
.size .L.str.3, 29
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\tClock rate:\t\t %d\n"
.size .L.str.4, 19
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " --- Memory Information for device %d ---\n"
.size .L.str.5, 43
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\tTotal global mem:\t %f\n"
.size .L.str.6, 24
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "\tTotal constant Mem:\t %ld\n"
.size .L.str.7, 27
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz " --- MP Information for device %d ---\n"
.size .L.str.8, 39
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "\tMultiprocessor count:\t %d\n"
.size .L.str.9, 28
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "\tShared mem per mp:\t %ld\n"
.size .L.str.10, 26
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "\tRegisters per mp:\t %d\n"
.size .L.str.11, 24
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "\tThreads in warp:\t %d\n"
.size .L.str.12, 23
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "\tMax threads per block:\t %d\n"
.size .L.str.13, 29
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "\tMax thread dimensions:\t (%d, %d, %d)\n"
.size .L.str.14, 39
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "\tMax grid dimensions:\t (%f, %d, %d)\n"
.size .L.str.15, 37
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelv"
.size .L__unnamed_1, 11
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z3addiiPi"
.size .L__unnamed_2, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelv
.addrsig_sym _Z18__device_stub__addiiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelv
.addrsig_sym _Z3addiiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <stdlib.h>
#include <stdio.h>
#include <math.h>
/* Define the matrix size */
#define NX 200
#define NY 100
/* Size of a block */
#define BLOCKSIZE 256
__global__ void kernadd (float* mout, float* min1, float *min2, int nx, int ny)
{
int i, j, index;
index = blockDim.x*blockIdx.x+threadIdx.x;
j = index/nx;
i = index - j*nx;
if ((i < nx) && (j < ny))
mout[index] = min1[index] + min2[index];
}
/*******************************************************/
/* We initialize the vectors with random values */
/*******************************************************/
void Init(float* mat, int nx, int ny) {
int i, j;
for (i = 0; i < nx; i++) { /* 2D loop */
for (j = 0; j < ny; j++) {
mat[i+j*nx] = drand48 (); /* position of cell (i,j) */
}
}
}
/*******************************************************/
/* MAIN PROGRAM */
/*******************************************************/
int main () {
int i=0, error=0, nx=NX, ny=NY;
float diff;
int size = nx * ny * sizeof(float);
/* Matrix allocation */
float *mat_in1 = (float*) malloc(size);
float *mat_in2 = (float*) malloc(size);
float *mat_out = (float*) malloc(size);
/* Matrix allocation on device */
float *mat_out_gpu, *mat_in1_gpu, *mat_in2_gpu;
/* TO DO : do the allocation below, using cudaMalloc()*/
cudaMalloc (&mat_in1_gpu, size);
cudaMalloc (&mat_in2_gpu, size);
cudaMalloc (&mat_out_gpu, size);
/* Matrix initialization */
Init(mat_in1, nx, ny);
Init(mat_in2, nx, ny);
/* TO DO : write below the instructions to copy it to the device */
cudaMemcpy(mat_in1_gpu, mat_in1, size, cudaMemcpyHostToDevice);
cudaMemcpy(mat_in2_gpu, mat_in2, size, cudaMemcpyHostToDevice);
cudaMemcpy(mat_out_gpu, mat_out, size, cudaMemcpyHostToDevice);
/* TO DO : complete the number of blocks below */
int numBlocks = (nx * ny + BLOCKSIZE-1) / BLOCKSIZE;
/* TO DO : kernel invocation */
kernadd<<<numBlocks, BLOCKSIZE>>>(mat_out_gpu, mat_in1_gpu, mat_in2_gpu, nx, ny);
cudaDeviceSynchronize();
/* We now transfer back the matrix from the device to the host */
/* TO DO : write cudaMemcpy() instruction below */
cudaMemcpy(mat_out, mat_out_gpu, size, cudaMemcpyDeviceToHost);
/* free memory */
cudaFree(mat_out_gpu);
cudaFree(mat_in1_gpu);
cudaFree(mat_in2_gpu);
/* We now check that the result is correct */
for (i=0; i< nx*ny; i++) { /* No need for a 2D loop, actually ! */
diff = mat_out[i] - (mat_in1[i]+mat_in2[i]);
if (fabs(diff) > 0.0000001f) {
error = 1;
}
}
if (error) {
printf("FAILED\n");
}
else {
printf("PASSED\n");
}
free (mat_in1);
free (mat_in2);
free (mat_out);
} | code for sm_80
Function : _Z7kernaddPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R7, c[0x0][0x178] ; /* 0x00005e0000077a13 */
/* 0x000fe20000000000 */
/*0020*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e260000002500 */
/*0030*/ I2F.RP R0, R7 ; /* 0x0000000700007306 */
/* 0x000e620000209400 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e2e0000002100 */
/*0050*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x002e620000001000 */
/*0060*/ IMAD R6, R6, c[0x0][0x0], R5 ; /* 0x0000000006067a24 */
/* 0x001fe200078e0205 */
/*0070*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x002fc80007ffe0ff */
/*0080*/ IABS R0, R6 ; /* 0x0000000600007213 */
/* 0x000fe40000000000 */
/*0090*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00a0*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*00b0*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x002fc800078e0a03 */
/*00c0*/ IMAD R5, R4, R7, RZ ; /* 0x0000000704057224 */
/* 0x000fca00078e02ff */
/*00d0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*00e0*/ IMAD.HI.U32 R3, R3, R0, RZ ; /* 0x0000000003037227 */
/* 0x000fc800078e00ff */
/*00f0*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a03 */
/*0100*/ IMAD R0, R7, R4, R0 ; /* 0x0000000407007224 */
/* 0x000fca00078e0200 */
/*0110*/ ISETP.GT.U32.AND P2, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f44070 */
/*0120*/ @!P2 IADD3 R0, R0, -R7.reuse, RZ ; /* 0x800000070000a210 */
/* 0x080fe40007ffe0ff */
/*0130*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*0140*/ ISETP.GE.U32.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x000fe40003f06070 */
/*0150*/ LOP3.LUT R0, R6, c[0x0][0x178], RZ, 0x3c, !PT ; /* 0x00005e0006007a12 */
/* 0x000fe400078e3cff */
/*0160*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe40003f45270 */
/*0170*/ ISETP.GE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fce0003f26270 */
/*0180*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fcc0007ffe0ff */
/*0190*/ @!P1 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff039224 */
/* 0x000fe200078e0a03 */
/*01a0*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff03aa12 */
/* 0x000fc800078e33ff */
/*01b0*/ IADD3 R5, -R3, RZ, RZ ; /* 0x000000ff03057210 */
/* 0x000fca0007ffe1ff */
/*01c0*/ IMAD R0, R5, c[0x0][0x178], R6 ; /* 0x00005e0005007a24 */
/* 0x000fca00078e0206 */
/*01d0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc80003f06270 */
/*01e0*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x17c], P0 ; /* 0x00005f0003007a0c */
/* 0x000fda0000706670 */
/*01f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0200*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0210*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0220*/ IMAD.WIDE R4, R6, R7, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x000fc800078e0207 */
/*0230*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x0c0fe400078e0207 */
/*0240*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0250*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0260*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0207 */
/*0270*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*0280*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0290*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02a0*/ BRA 0x2a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <stdlib.h>
#include <stdio.h>
#include <math.h>
/* Define the matrix size */
#define NX 200
#define NY 100
/* Size of a block */
#define BLOCKSIZE 256
__global__ void kernadd (float* mout, float* min1, float *min2, int nx, int ny)
{
int i, j, index;
index = blockDim.x*blockIdx.x+threadIdx.x;
j = index/nx;
i = index - j*nx;
if ((i < nx) && (j < ny))
mout[index] = min1[index] + min2[index];
}
/*******************************************************/
/* We initialize the vectors with random values */
/*******************************************************/
void Init(float* mat, int nx, int ny) {
int i, j;
for (i = 0; i < nx; i++) { /* 2D loop */
for (j = 0; j < ny; j++) {
mat[i+j*nx] = drand48 (); /* position of cell (i,j) */
}
}
}
/*******************************************************/
/* MAIN PROGRAM */
/*******************************************************/
int main () {
int i=0, error=0, nx=NX, ny=NY;
float diff;
int size = nx * ny * sizeof(float);
/* Matrix allocation */
float *mat_in1 = (float*) malloc(size);
float *mat_in2 = (float*) malloc(size);
float *mat_out = (float*) malloc(size);
/* Matrix allocation on device */
float *mat_out_gpu, *mat_in1_gpu, *mat_in2_gpu;
/* TO DO : do the allocation below, using cudaMalloc()*/
cudaMalloc (&mat_in1_gpu, size);
cudaMalloc (&mat_in2_gpu, size);
cudaMalloc (&mat_out_gpu, size);
/* Matrix initialization */
Init(mat_in1, nx, ny);
Init(mat_in2, nx, ny);
/* TO DO : write below the instructions to copy it to the device */
cudaMemcpy(mat_in1_gpu, mat_in1, size, cudaMemcpyHostToDevice);
cudaMemcpy(mat_in2_gpu, mat_in2, size, cudaMemcpyHostToDevice);
cudaMemcpy(mat_out_gpu, mat_out, size, cudaMemcpyHostToDevice);
/* TO DO : complete the number of blocks below */
int numBlocks = (nx * ny + BLOCKSIZE-1) / BLOCKSIZE;
/* TO DO : kernel invocation */
kernadd<<<numBlocks, BLOCKSIZE>>>(mat_out_gpu, mat_in1_gpu, mat_in2_gpu, nx, ny);
cudaDeviceSynchronize();
/* We now transfer back the matrix from the device to the host */
/* TO DO : write cudaMemcpy() instruction below */
cudaMemcpy(mat_out, mat_out_gpu, size, cudaMemcpyDeviceToHost);
/* free memory */
cudaFree(mat_out_gpu);
cudaFree(mat_in1_gpu);
cudaFree(mat_in2_gpu);
/* We now check that the result is correct */
for (i=0; i< nx*ny; i++) { /* No need for a 2D loop, actually ! */
diff = mat_out[i] - (mat_in1[i]+mat_in2[i]);
if (fabs(diff) > 0.0000001f) {
error = 1;
}
}
if (error) {
printf("FAILED\n");
}
else {
printf("PASSED\n");
}
free (mat_in1);
free (mat_in2);
free (mat_out);
} | .file "tmpxft_0003d2e8_00000000-6_addongpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4InitPfii
.type _Z4InitPfii, @function
_Z4InitPfii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 8(%rsp)
testl %esi, %esi
jle .L3
movl %edx, %r12d
movslq %esi, %r15
leaq 0(,%r15,4), %r13
movl $0, %r14d
jmp .L5
.L6:
call drand48@PLT
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 0(%rbp)
addl $1, %ebx
addq %r13, %rbp
cmpl %ebx, %r12d
jne .L6
.L8:
addq $1, %r14
cmpq %r15, %r14
je .L3
.L5:
movq 8(%rsp), %rax
leaq (%rax,%r14,4), %rbp
movl $0, %ebx
testl %r12d, %r12d
jg .L6
jmp .L8
.L3:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z4InitPfii, .-_Z4InitPfii
.globl _Z32__device_stub__Z7kernaddPfS_S_iiPfS_S_ii
.type _Z32__device_stub__Z7kernaddPfS_S_iiPfS_S_ii, @function
_Z32__device_stub__Z7kernaddPfS_S_iiPfS_S_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7kernaddPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z32__device_stub__Z7kernaddPfS_S_iiPfS_S_ii, .-_Z32__device_stub__Z7kernaddPfS_S_iiPfS_S_ii
.globl _Z7kernaddPfS_S_ii
.type _Z7kernaddPfS_S_ii, @function
_Z7kernaddPfS_S_ii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z7kernaddPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7kernaddPfS_S_ii, .-_Z7kernaddPfS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "FAILED\n"
.LC3:
.string "PASSED\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $80000, %edi
call malloc@PLT
movq %rax, %r12
movl $80000, %edi
call malloc@PLT
movq %rax, %rbp
movl $80000, %edi
call malloc@PLT
movq %rax, %rbx
leaq 16(%rsp), %rdi
movl $80000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $80000, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $80000, %esi
call cudaMalloc@PLT
movl $100, %edx
movl $200, %esi
movq %r12, %rdi
call _Z4InitPfii
movl $100, %edx
movl $200, %esi
movq %rbp, %rdi
call _Z4InitPfii
movl $1, %ecx
movl $80000, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $80000, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $80000, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $79, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L21:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $80000, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
movl $0, %edx
movss .LC0(%rip), %xmm2
movl $1, %ecx
.L23:
movss (%r12,%rax), %xmm1
addss 0(%rbp,%rax), %xmm1
movss (%rbx,%rax), %xmm0
subss %xmm1, %xmm0
andps %xmm2, %xmm0
ucomiss .LC1(%rip), %xmm0
cmova %ecx, %edx
addq $4, %rax
cmpq $80000, %rax
jne .L23
testl %edx, %edx
je .L24
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L25:
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L31
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
movl $100, %r8d
movl $200, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z7kernaddPfS_S_iiPfS_S_ii
jmp .L21
.L24:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L25
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z7kernaddPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kernaddPfS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC0:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 869711765
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <stdlib.h>
#include <stdio.h>
#include <math.h>
/* Define the matrix size */
#define NX 200
#define NY 100
/* Size of a block */
#define BLOCKSIZE 256
__global__ void kernadd (float* mout, float* min1, float *min2, int nx, int ny)
{
int i, j, index;
index = blockDim.x*blockIdx.x+threadIdx.x;
j = index/nx;
i = index - j*nx;
if ((i < nx) && (j < ny))
mout[index] = min1[index] + min2[index];
}
/*******************************************************/
/* We initialize the vectors with random values */
/*******************************************************/
void Init(float* mat, int nx, int ny) {
int i, j;
for (i = 0; i < nx; i++) { /* 2D loop */
for (j = 0; j < ny; j++) {
mat[i+j*nx] = drand48 (); /* position of cell (i,j) */
}
}
}
/*******************************************************/
/* MAIN PROGRAM */
/*******************************************************/
int main () {
int i=0, error=0, nx=NX, ny=NY;
float diff;
int size = nx * ny * sizeof(float);
/* Matrix allocation */
float *mat_in1 = (float*) malloc(size);
float *mat_in2 = (float*) malloc(size);
float *mat_out = (float*) malloc(size);
/* Matrix allocation on device */
float *mat_out_gpu, *mat_in1_gpu, *mat_in2_gpu;
/* TO DO : do the allocation below, using cudaMalloc()*/
cudaMalloc (&mat_in1_gpu, size);
cudaMalloc (&mat_in2_gpu, size);
cudaMalloc (&mat_out_gpu, size);
/* Matrix initialization */
Init(mat_in1, nx, ny);
Init(mat_in2, nx, ny);
/* TO DO : write below the instructions to copy it to the device */
cudaMemcpy(mat_in1_gpu, mat_in1, size, cudaMemcpyHostToDevice);
cudaMemcpy(mat_in2_gpu, mat_in2, size, cudaMemcpyHostToDevice);
cudaMemcpy(mat_out_gpu, mat_out, size, cudaMemcpyHostToDevice);
/* TO DO : complete the number of blocks below */
int numBlocks = (nx * ny + BLOCKSIZE-1) / BLOCKSIZE;
/* TO DO : kernel invocation */
kernadd<<<numBlocks, BLOCKSIZE>>>(mat_out_gpu, mat_in1_gpu, mat_in2_gpu, nx, ny);
cudaDeviceSynchronize();
/* We now transfer back the matrix from the device to the host */
/* TO DO : write cudaMemcpy() instruction below */
cudaMemcpy(mat_out, mat_out_gpu, size, cudaMemcpyDeviceToHost);
/* free memory */
cudaFree(mat_out_gpu);
cudaFree(mat_in1_gpu);
cudaFree(mat_in2_gpu);
/* We now check that the result is correct */
for (i=0; i< nx*ny; i++) { /* No need for a 2D loop, actually ! */
diff = mat_out[i] - (mat_in1[i]+mat_in2[i]);
if (fabs(diff) > 0.0000001f) {
error = 1;
}
}
if (error) {
printf("FAILED\n");
}
else {
printf("PASSED\n");
}
free (mat_in1);
free (mat_in2);
free (mat_out);
} | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <math.h>
/* Define the matrix size */
#define NX 200
#define NY 100
/* Size of a block */
#define BLOCKSIZE 256
__global__ void kernadd (float* mout, float* min1, float *min2, int nx, int ny)
{
int i, j, index;
index = blockDim.x*blockIdx.x+threadIdx.x;
j = index/nx;
i = index - j*nx;
if ((i < nx) && (j < ny))
mout[index] = min1[index] + min2[index];
}
/*******************************************************/
/* We initialize the vectors with random values */
/*******************************************************/
void Init(float* mat, int nx, int ny) {
int i, j;
for (i = 0; i < nx; i++) { /* 2D loop */
for (j = 0; j < ny; j++) {
mat[i+j*nx] = drand48 (); /* position of cell (i,j) */
}
}
}
/*******************************************************/
/* MAIN PROGRAM */
/*******************************************************/
int main () {
int i=0, error=0, nx=NX, ny=NY;
float diff;
int size = nx * ny * sizeof(float);
/* Matrix allocation */
float *mat_in1 = (float*) malloc(size);
float *mat_in2 = (float*) malloc(size);
float *mat_out = (float*) malloc(size);
/* Matrix allocation on device */
float *mat_out_gpu, *mat_in1_gpu, *mat_in2_gpu;
/* TO DO : do the allocation below, using cudaMalloc()*/
hipMalloc (&mat_in1_gpu, size);
hipMalloc (&mat_in2_gpu, size);
hipMalloc (&mat_out_gpu, size);
/* Matrix initialization */
Init(mat_in1, nx, ny);
Init(mat_in2, nx, ny);
/* TO DO : write below the instructions to copy it to the device */
hipMemcpy(mat_in1_gpu, mat_in1, size, hipMemcpyHostToDevice);
hipMemcpy(mat_in2_gpu, mat_in2, size, hipMemcpyHostToDevice);
hipMemcpy(mat_out_gpu, mat_out, size, hipMemcpyHostToDevice);
/* TO DO : complete the number of blocks below */
int numBlocks = (nx * ny + BLOCKSIZE-1) / BLOCKSIZE;
/* TO DO : kernel invocation */
kernadd<<<numBlocks, BLOCKSIZE>>>(mat_out_gpu, mat_in1_gpu, mat_in2_gpu, nx, ny);
hipDeviceSynchronize();
/* We now transfer back the matrix from the device to the host */
/* TO DO : write cudaMemcpy() instruction below */
hipMemcpy(mat_out, mat_out_gpu, size, hipMemcpyDeviceToHost);
/* free memory */
hipFree(mat_out_gpu);
hipFree(mat_in1_gpu);
hipFree(mat_in2_gpu);
/* We now check that the result is correct */
for (i=0; i< nx*ny; i++) { /* No need for a 2D loop, actually ! */
diff = mat_out[i] - (mat_in1[i]+mat_in2[i]);
if (fabs(diff) > 0.0000001f) {
error = 1;
}
}
if (error) {
printf("FAILED\n");
}
else {
printf("PASSED\n");
}
free (mat_in1);
free (mat_in2);
free (mat_out);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <math.h>
/* Define the matrix size */
#define NX 200
#define NY 100
/* Size of a block */
#define BLOCKSIZE 256
__global__ void kernadd (float* mout, float* min1, float *min2, int nx, int ny)
{
int i, j, index;
index = blockDim.x*blockIdx.x+threadIdx.x;
j = index/nx;
i = index - j*nx;
if ((i < nx) && (j < ny))
mout[index] = min1[index] + min2[index];
}
/*******************************************************/
/* We initialize the vectors with random values */
/*******************************************************/
void Init(float* mat, int nx, int ny) {
int i, j;
for (i = 0; i < nx; i++) { /* 2D loop */
for (j = 0; j < ny; j++) {
mat[i+j*nx] = drand48 (); /* position of cell (i,j) */
}
}
}
/*******************************************************/
/* MAIN PROGRAM */
/*******************************************************/
int main () {
int i=0, error=0, nx=NX, ny=NY;
float diff;
int size = nx * ny * sizeof(float);
/* Matrix allocation */
float *mat_in1 = (float*) malloc(size);
float *mat_in2 = (float*) malloc(size);
float *mat_out = (float*) malloc(size);
/* Matrix allocation on device */
float *mat_out_gpu, *mat_in1_gpu, *mat_in2_gpu;
/* TO DO : do the allocation below, using cudaMalloc()*/
hipMalloc (&mat_in1_gpu, size);
hipMalloc (&mat_in2_gpu, size);
hipMalloc (&mat_out_gpu, size);
/* Matrix initialization */
Init(mat_in1, nx, ny);
Init(mat_in2, nx, ny);
/* TO DO : write below the instructions to copy it to the device */
hipMemcpy(mat_in1_gpu, mat_in1, size, hipMemcpyHostToDevice);
hipMemcpy(mat_in2_gpu, mat_in2, size, hipMemcpyHostToDevice);
hipMemcpy(mat_out_gpu, mat_out, size, hipMemcpyHostToDevice);
/* TO DO : complete the number of blocks below */
int numBlocks = (nx * ny + BLOCKSIZE-1) / BLOCKSIZE;
/* TO DO : kernel invocation */
kernadd<<<numBlocks, BLOCKSIZE>>>(mat_out_gpu, mat_in1_gpu, mat_in2_gpu, nx, ny);
hipDeviceSynchronize();
/* We now transfer back the matrix from the device to the host */
/* TO DO : write cudaMemcpy() instruction below */
hipMemcpy(mat_out, mat_out_gpu, size, hipMemcpyDeviceToHost);
/* free memory */
hipFree(mat_out_gpu);
hipFree(mat_in1_gpu);
hipFree(mat_in2_gpu);
/* We now check that the result is correct */
for (i=0; i< nx*ny; i++) { /* No need for a 2D loop, actually ! */
diff = mat_out[i] - (mat_in1[i]+mat_in2[i]);
if (fabs(diff) > 0.0000001f) {
error = 1;
}
}
if (error) {
printf("FAILED\n");
}
else {
printf("PASSED\n");
}
free (mat_in1);
free (mat_in2);
free (mat_out);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7kernaddPfS_S_ii
.globl _Z7kernaddPfS_S_ii
.p2align 8
.type _Z7kernaddPfS_S_ii,@function
_Z7kernaddPfS_S_ii:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b32 s4, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_ashr_i32 s5, s2, 31
s_and_b32 s4, s4, 0xffff
s_add_i32 s6, s2, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s6, s6, s5
v_cvt_f32_u32_e32 v1, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_sub_i32 s4, 0, s6
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v0, s4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_mul_hi_u32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v2
v_xor_b32_e32 v4, v4, v2
v_xor_b32_e32 v2, s5, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v3, v0
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v0, s6
v_sub_nc_u32_e32 v3, v4, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s6, v3
v_cmp_le_u32_e32 vcc_lo, s6, v3
v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s6, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_xor_b32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v2
v_mul_lo_u32 v2, v0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v1, v2
v_cmp_gt_i32_e32 vcc_lo, s2, v2
v_cmp_gt_i32_e64 s2, s3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7kernaddPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7kernaddPfS_S_ii, .Lfunc_end0-_Z7kernaddPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7kernaddPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7kernaddPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <math.h>
/* Define the matrix size */
#define NX 200
#define NY 100
/* Size of a block */
#define BLOCKSIZE 256
__global__ void kernadd (float* mout, float* min1, float *min2, int nx, int ny)
{
int i, j, index;
index = blockDim.x*blockIdx.x+threadIdx.x;
j = index/nx;
i = index - j*nx;
if ((i < nx) && (j < ny))
mout[index] = min1[index] + min2[index];
}
/*******************************************************/
/* We initialize the vectors with random values */
/*******************************************************/
void Init(float* mat, int nx, int ny) {
int i, j;
for (i = 0; i < nx; i++) { /* 2D loop */
for (j = 0; j < ny; j++) {
mat[i+j*nx] = drand48 (); /* position of cell (i,j) */
}
}
}
/*******************************************************/
/* MAIN PROGRAM */
/*******************************************************/
int main () {
int i=0, error=0, nx=NX, ny=NY;
float diff;
int size = nx * ny * sizeof(float);
/* Matrix allocation */
float *mat_in1 = (float*) malloc(size);
float *mat_in2 = (float*) malloc(size);
float *mat_out = (float*) malloc(size);
/* Matrix allocation on device */
float *mat_out_gpu, *mat_in1_gpu, *mat_in2_gpu;
/* TO DO : do the allocation below, using cudaMalloc()*/
hipMalloc (&mat_in1_gpu, size);
hipMalloc (&mat_in2_gpu, size);
hipMalloc (&mat_out_gpu, size);
/* Matrix initialization */
Init(mat_in1, nx, ny);
Init(mat_in2, nx, ny);
/* TO DO : write below the instructions to copy it to the device */
hipMemcpy(mat_in1_gpu, mat_in1, size, hipMemcpyHostToDevice);
hipMemcpy(mat_in2_gpu, mat_in2, size, hipMemcpyHostToDevice);
hipMemcpy(mat_out_gpu, mat_out, size, hipMemcpyHostToDevice);
/* TO DO : complete the number of blocks below */
int numBlocks = (nx * ny + BLOCKSIZE-1) / BLOCKSIZE;
/* TO DO : kernel invocation */
kernadd<<<numBlocks, BLOCKSIZE>>>(mat_out_gpu, mat_in1_gpu, mat_in2_gpu, nx, ny);
hipDeviceSynchronize();
/* We now transfer back the matrix from the device to the host */
/* TO DO : write cudaMemcpy() instruction below */
hipMemcpy(mat_out, mat_out_gpu, size, hipMemcpyDeviceToHost);
/* free memory */
hipFree(mat_out_gpu);
hipFree(mat_in1_gpu);
hipFree(mat_in2_gpu);
/* We now check that the result is correct */
for (i=0; i< nx*ny; i++) { /* No need for a 2D loop, actually ! */
diff = mat_out[i] - (mat_in1[i]+mat_in2[i]);
if (fabs(diff) > 0.0000001f) {
error = 1;
}
}
if (error) {
printf("FAILED\n");
}
else {
printf("PASSED\n");
}
free (mat_in1);
free (mat_in2);
free (mat_out);
} | .text
.file "addongpu.hip"
.globl _Z22__device_stub__kernaddPfS_S_ii # -- Begin function _Z22__device_stub__kernaddPfS_S_ii
.p2align 4, 0x90
.type _Z22__device_stub__kernaddPfS_S_ii,@function
_Z22__device_stub__kernaddPfS_S_ii: # @_Z22__device_stub__kernaddPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7kernaddPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__kernaddPfS_S_ii, .Lfunc_end0-_Z22__device_stub__kernaddPfS_S_ii
.cfi_endproc
# -- End function
.globl _Z4InitPfii # -- Begin function _Z4InitPfii
.p2align 4, 0x90
.type _Z4InitPfii,@function
_Z4InitPfii: # @_Z4InitPfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, 12(%rsp) # 4-byte Spill
testl %esi, %esi
jle .LBB1_6
# %bb.1: # %.preheader.lr.ph
movq %rdi, %rbx
movl %esi, %r15d
movl 12(%rsp), %eax # 4-byte Reload
movq %rax, 16(%rsp) # 8-byte Spill
leaq (,%r15,4), %r13
xorl %ebp, %ebp
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %rbp
addq $4, %rbx
cmpq %r15, %rbp
je .LBB1_6
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
cmpl $0, 12(%rsp) # 4-byte Folded Reload
jle .LBB1_5
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB1_2 Depth=1
movq 16(%rsp), %r12 # 8-byte Reload
movq %rbx, %r14
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
callq drand48
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r14)
addq %r13, %r14
decq %r12
jne .LBB1_4
jmp .LBB1_5
.LBB1_6: # %._crit_edge13
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z4InitPfii, .Lfunc_end1-_Z4InitPfii
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI2_1:
.long 0x33d6bf95 # float 1.00000001E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $80000, %edi # imm = 0x13880
callq malloc
movq %rax, %rbx
movl $80000, %edi # imm = 0x13880
callq malloc
movq %rax, %r14
movl $80000, %edi # imm = 0x13880
callq malloc
movq %rax, %r15
leaq 24(%rsp), %rdi
movl $80000, %esi # imm = 0x13880
callq hipMalloc
leaq 16(%rsp), %rdi
movl $80000, %esi # imm = 0x13880
callq hipMalloc
leaq 8(%rsp), %rdi
movl $80000, %esi # imm = 0x13880
callq hipMalloc
xorl %r12d, %r12d
movq %rbx, %r13
.p2align 4, 0x90
.LBB2_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_2: # %.lr.ph.i
# Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
callq drand48
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r13,%rbp)
addq $800, %rbp # imm = 0x320
cmpq $80000, %rbp # imm = 0x13880
jne .LBB2_2
# %bb.3: # %._crit_edge.i
# in Loop: Header=BB2_1 Depth=1
incq %r12
addq $4, %r13
cmpq $200, %r12
jne .LBB2_1
# %bb.4: # %.preheader.i47.preheader
xorl %r12d, %r12d
movq %r14, %r13
.p2align 4, 0x90
.LBB2_5: # %.preheader.i47
# =>This Loop Header: Depth=1
# Child Loop BB2_6 Depth 2
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_6: # %.lr.ph.i49
# Parent Loop BB2_5 Depth=1
# => This Inner Loop Header: Depth=2
callq drand48
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r13,%rbp)
addq $800, %rbp # imm = 0x320
cmpq $80000, %rbp # imm = 0x13880
jne .LBB2_6
# %bb.7: # %._crit_edge.i53
# in Loop: Header=BB2_5 Depth=1
incq %r12
addq $4, %r13
cmpq $200, %r12
jne .LBB2_5
# %bb.8: # %_Z4InitPfii.exit56
movq 24(%rsp), %rdi
movl $1, %ebp
movl $80000, %edx # imm = 0x13880
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $80000, %edx # imm = 0x13880
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $80000, %edx # imm = 0x13880
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967375, %rdi # imm = 0x10000004F
leaq 177(%rdi), %rdx
xorl %r12d, %r12d
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_10
# %bb.9:
movq 8(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $200, 36(%rsp)
movl $100, 32(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z7kernaddPfS_S_ii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_10:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movl $80000, %edx # imm = 0x13880
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movaps .LCPI2_0(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN]
movss .LCPI2_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_11: # =>This Inner Loop Header: Depth=1
movss (%r15,%rax,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss (%rbx,%rax,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
addss (%r14,%rax,4), %xmm3
subss %xmm3, %xmm2
andps %xmm0, %xmm2
ucomiss %xmm1, %xmm2
cmoval %ebp, %r12d
incq %rax
cmpq $20000, %rax # imm = 0x4E20
jne .LBB2_11
# %bb.12:
testl %r12d, %r12d
movl $.Lstr, %eax
movl $.Lstr.1, %edi
cmoveq %rax, %rdi
callq puts@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kernaddPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7kernaddPfS_S_ii,@object # @_Z7kernaddPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z7kernaddPfS_S_ii
.p2align 3, 0x0
_Z7kernaddPfS_S_ii:
.quad _Z22__device_stub__kernaddPfS_S_ii
.size _Z7kernaddPfS_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7kernaddPfS_S_ii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "PASSED"
.size .Lstr, 7
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "FAILED"
.size .Lstr.1, 7
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__kernaddPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7kernaddPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7kernaddPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R7, c[0x0][0x178] ; /* 0x00005e0000077a13 */
/* 0x000fe20000000000 */
/*0020*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e260000002500 */
/*0030*/ I2F.RP R0, R7 ; /* 0x0000000700007306 */
/* 0x000e620000209400 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e2e0000002100 */
/*0050*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x002e620000001000 */
/*0060*/ IMAD R6, R6, c[0x0][0x0], R5 ; /* 0x0000000006067a24 */
/* 0x001fe200078e0205 */
/*0070*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x002fc80007ffe0ff */
/*0080*/ IABS R0, R6 ; /* 0x0000000600007213 */
/* 0x000fe40000000000 */
/*0090*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00a0*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*00b0*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x002fc800078e0a03 */
/*00c0*/ IMAD R5, R4, R7, RZ ; /* 0x0000000704057224 */
/* 0x000fca00078e02ff */
/*00d0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*00e0*/ IMAD.HI.U32 R3, R3, R0, RZ ; /* 0x0000000003037227 */
/* 0x000fc800078e00ff */
/*00f0*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a03 */
/*0100*/ IMAD R0, R7, R4, R0 ; /* 0x0000000407007224 */
/* 0x000fca00078e0200 */
/*0110*/ ISETP.GT.U32.AND P2, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f44070 */
/*0120*/ @!P2 IADD3 R0, R0, -R7.reuse, RZ ; /* 0x800000070000a210 */
/* 0x080fe40007ffe0ff */
/*0130*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*0140*/ ISETP.GE.U32.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x000fe40003f06070 */
/*0150*/ LOP3.LUT R0, R6, c[0x0][0x178], RZ, 0x3c, !PT ; /* 0x00005e0006007a12 */
/* 0x000fe400078e3cff */
/*0160*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe40003f45270 */
/*0170*/ ISETP.GE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fce0003f26270 */
/*0180*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fcc0007ffe0ff */
/*0190*/ @!P1 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff039224 */
/* 0x000fe200078e0a03 */
/*01a0*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff03aa12 */
/* 0x000fc800078e33ff */
/*01b0*/ IADD3 R5, -R3, RZ, RZ ; /* 0x000000ff03057210 */
/* 0x000fca0007ffe1ff */
/*01c0*/ IMAD R0, R5, c[0x0][0x178], R6 ; /* 0x00005e0005007a24 */
/* 0x000fca00078e0206 */
/*01d0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc80003f06270 */
/*01e0*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x17c], P0 ; /* 0x00005f0003007a0c */
/* 0x000fda0000706670 */
/*01f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0200*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0210*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0220*/ IMAD.WIDE R4, R6, R7, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x000fc800078e0207 */
/*0230*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x0c0fe400078e0207 */
/*0240*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0250*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0260*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0207 */
/*0270*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*0280*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0290*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02a0*/ BRA 0x2a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7kernaddPfS_S_ii
.globl _Z7kernaddPfS_S_ii
.p2align 8
.type _Z7kernaddPfS_S_ii,@function
_Z7kernaddPfS_S_ii:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b32 s4, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_ashr_i32 s5, s2, 31
s_and_b32 s4, s4, 0xffff
s_add_i32 s6, s2, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s6, s6, s5
v_cvt_f32_u32_e32 v1, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_sub_i32 s4, 0, s6
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v0, s4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_mul_hi_u32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v2
v_xor_b32_e32 v4, v4, v2
v_xor_b32_e32 v2, s5, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v3, v0
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v0, s6
v_sub_nc_u32_e32 v3, v4, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s6, v3
v_cmp_le_u32_e32 vcc_lo, s6, v3
v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s6, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_xor_b32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v2
v_mul_lo_u32 v2, v0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v1, v2
v_cmp_gt_i32_e32 vcc_lo, s2, v2
v_cmp_gt_i32_e64 s2, s3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7kernaddPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7kernaddPfS_S_ii, .Lfunc_end0-_Z7kernaddPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7kernaddPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7kernaddPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003d2e8_00000000-6_addongpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4InitPfii
.type _Z4InitPfii, @function
_Z4InitPfii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 8(%rsp)
testl %esi, %esi
jle .L3
movl %edx, %r12d
movslq %esi, %r15
leaq 0(,%r15,4), %r13
movl $0, %r14d
jmp .L5
.L6:
call drand48@PLT
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 0(%rbp)
addl $1, %ebx
addq %r13, %rbp
cmpl %ebx, %r12d
jne .L6
.L8:
addq $1, %r14
cmpq %r15, %r14
je .L3
.L5:
movq 8(%rsp), %rax
leaq (%rax,%r14,4), %rbp
movl $0, %ebx
testl %r12d, %r12d
jg .L6
jmp .L8
.L3:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z4InitPfii, .-_Z4InitPfii
.globl _Z32__device_stub__Z7kernaddPfS_S_iiPfS_S_ii
.type _Z32__device_stub__Z7kernaddPfS_S_iiPfS_S_ii, @function
_Z32__device_stub__Z7kernaddPfS_S_iiPfS_S_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7kernaddPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z32__device_stub__Z7kernaddPfS_S_iiPfS_S_ii, .-_Z32__device_stub__Z7kernaddPfS_S_iiPfS_S_ii
.globl _Z7kernaddPfS_S_ii
.type _Z7kernaddPfS_S_ii, @function
_Z7kernaddPfS_S_ii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z7kernaddPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7kernaddPfS_S_ii, .-_Z7kernaddPfS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "FAILED\n"
.LC3:
.string "PASSED\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $80000, %edi
call malloc@PLT
movq %rax, %r12
movl $80000, %edi
call malloc@PLT
movq %rax, %rbp
movl $80000, %edi
call malloc@PLT
movq %rax, %rbx
leaq 16(%rsp), %rdi
movl $80000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $80000, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $80000, %esi
call cudaMalloc@PLT
movl $100, %edx
movl $200, %esi
movq %r12, %rdi
call _Z4InitPfii
movl $100, %edx
movl $200, %esi
movq %rbp, %rdi
call _Z4InitPfii
movl $1, %ecx
movl $80000, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $80000, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $80000, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $79, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L21:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $80000, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
movl $0, %edx
movss .LC0(%rip), %xmm2
movl $1, %ecx
.L23:
movss (%r12,%rax), %xmm1
addss 0(%rbp,%rax), %xmm1
movss (%rbx,%rax), %xmm0
subss %xmm1, %xmm0
andps %xmm2, %xmm0
ucomiss .LC1(%rip), %xmm0
cmova %ecx, %edx
addq $4, %rax
cmpq $80000, %rax
jne .L23
testl %edx, %edx
je .L24
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L25:
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L31
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
movl $100, %r8d
movl $200, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z7kernaddPfS_S_iiPfS_S_ii
jmp .L21
.L24:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L25
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z7kernaddPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kernaddPfS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC0:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 869711765
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "addongpu.hip"
.globl _Z22__device_stub__kernaddPfS_S_ii # -- Begin function _Z22__device_stub__kernaddPfS_S_ii
.p2align 4, 0x90
.type _Z22__device_stub__kernaddPfS_S_ii,@function
_Z22__device_stub__kernaddPfS_S_ii: # @_Z22__device_stub__kernaddPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7kernaddPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__kernaddPfS_S_ii, .Lfunc_end0-_Z22__device_stub__kernaddPfS_S_ii
.cfi_endproc
# -- End function
.globl _Z4InitPfii # -- Begin function _Z4InitPfii
.p2align 4, 0x90
.type _Z4InitPfii,@function
_Z4InitPfii: # @_Z4InitPfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, 12(%rsp) # 4-byte Spill
testl %esi, %esi
jle .LBB1_6
# %bb.1: # %.preheader.lr.ph
movq %rdi, %rbx
movl %esi, %r15d
movl 12(%rsp), %eax # 4-byte Reload
movq %rax, 16(%rsp) # 8-byte Spill
leaq (,%r15,4), %r13
xorl %ebp, %ebp
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %rbp
addq $4, %rbx
cmpq %r15, %rbp
je .LBB1_6
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
cmpl $0, 12(%rsp) # 4-byte Folded Reload
jle .LBB1_5
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB1_2 Depth=1
movq 16(%rsp), %r12 # 8-byte Reload
movq %rbx, %r14
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
callq drand48
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r14)
addq %r13, %r14
decq %r12
jne .LBB1_4
jmp .LBB1_5
.LBB1_6: # %._crit_edge13
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z4InitPfii, .Lfunc_end1-_Z4InitPfii
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI2_1:
.long 0x33d6bf95 # float 1.00000001E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $80000, %edi # imm = 0x13880
callq malloc
movq %rax, %rbx
movl $80000, %edi # imm = 0x13880
callq malloc
movq %rax, %r14
movl $80000, %edi # imm = 0x13880
callq malloc
movq %rax, %r15
leaq 24(%rsp), %rdi
movl $80000, %esi # imm = 0x13880
callq hipMalloc
leaq 16(%rsp), %rdi
movl $80000, %esi # imm = 0x13880
callq hipMalloc
leaq 8(%rsp), %rdi
movl $80000, %esi # imm = 0x13880
callq hipMalloc
xorl %r12d, %r12d
movq %rbx, %r13
.p2align 4, 0x90
.LBB2_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_2: # %.lr.ph.i
# Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
callq drand48
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r13,%rbp)
addq $800, %rbp # imm = 0x320
cmpq $80000, %rbp # imm = 0x13880
jne .LBB2_2
# %bb.3: # %._crit_edge.i
# in Loop: Header=BB2_1 Depth=1
incq %r12
addq $4, %r13
cmpq $200, %r12
jne .LBB2_1
# %bb.4: # %.preheader.i47.preheader
xorl %r12d, %r12d
movq %r14, %r13
.p2align 4, 0x90
.LBB2_5: # %.preheader.i47
# =>This Loop Header: Depth=1
# Child Loop BB2_6 Depth 2
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_6: # %.lr.ph.i49
# Parent Loop BB2_5 Depth=1
# => This Inner Loop Header: Depth=2
callq drand48
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r13,%rbp)
addq $800, %rbp # imm = 0x320
cmpq $80000, %rbp # imm = 0x13880
jne .LBB2_6
# %bb.7: # %._crit_edge.i53
# in Loop: Header=BB2_5 Depth=1
incq %r12
addq $4, %r13
cmpq $200, %r12
jne .LBB2_5
# %bb.8: # %_Z4InitPfii.exit56
movq 24(%rsp), %rdi
movl $1, %ebp
movl $80000, %edx # imm = 0x13880
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $80000, %edx # imm = 0x13880
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $80000, %edx # imm = 0x13880
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967375, %rdi # imm = 0x10000004F
leaq 177(%rdi), %rdx
xorl %r12d, %r12d
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_10
# %bb.9:
movq 8(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $200, 36(%rsp)
movl $100, 32(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z7kernaddPfS_S_ii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_10:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movl $80000, %edx # imm = 0x13880
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movaps .LCPI2_0(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN]
movss .LCPI2_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_11: # =>This Inner Loop Header: Depth=1
movss (%r15,%rax,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss (%rbx,%rax,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
addss (%r14,%rax,4), %xmm3
subss %xmm3, %xmm2
andps %xmm0, %xmm2
ucomiss %xmm1, %xmm2
cmoval %ebp, %r12d
incq %rax
cmpq $20000, %rax # imm = 0x4E20
jne .LBB2_11
# %bb.12:
testl %r12d, %r12d
movl $.Lstr, %eax
movl $.Lstr.1, %edi
cmoveq %rax, %rdi
callq puts@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kernaddPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7kernaddPfS_S_ii,@object # @_Z7kernaddPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z7kernaddPfS_S_ii
.p2align 3, 0x0
_Z7kernaddPfS_S_ii:
.quad _Z22__device_stub__kernaddPfS_S_ii
.size _Z7kernaddPfS_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7kernaddPfS_S_ii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "PASSED"
.size .Lstr, 7
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "FAILED"
.size .Lstr.1, 7
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__kernaddPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7kernaddPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void cudaSAnchorBackPropagateSSD_NegSamples_kernel(const float* inputCls, float* diffOutputsCls, const float* confSamples, const int* keySamples, const int nbSamples, const int nbPositive, const unsigned int nbAnchors, const unsigned int outputsHeight, const unsigned int outputsWidth, const unsigned int batchSize)
{
const int index = (threadIdx.x & 0x1f) + blockIdx.x*blockDim.x;
if(index < nbSamples)
{
const int indexSamples = keySamples[index];
const float error = inputCls[indexSamples];
//diffOutputsCls[indexSamples] = -inputCls[index] / (nbPositive * batchSize);
//printf("error[%d]: %f\n", indexSamples, error);
diffOutputsCls[indexSamples] = -error / (nbPositive * batchSize);
}
} | code for sm_80
Function : _Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0030*/ LOP3.LUT R0, R0, 0x1f, RZ, 0xc0, !PT ; /* 0x0000001f00007812 */
/* 0x001fca00078ec0ff */
/*0040*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x002fca00078e0200 */
/*0050*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fda0003f06270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0090*/ IMAD.WIDE R2, R0, R5, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x000fca00078e0205 */
/*00a0*/ LDG.E R0, [R2.64] ; /* 0x0000000602007981 */
/* 0x000ea2000c1e1900 */
/*00b0*/ ULDC UR4, c[0x0][0x194] ; /* 0x0000650000047ab9 */
/* 0x000fe40000000800 */
/*00c0*/ ULDC UR5, c[0x0][0x184] ; /* 0x0000610000057ab9 */
/* 0x000fe40000000800 */
/*00d0*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fd2000f8e023f */
/*00e0*/ I2F.U32 R7, UR4 ; /* 0x0000000400077d06 */
/* 0x000e220008201000 */
/*00f0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x004fcc00078e0205 */
/*0100*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1900 */
/*0110*/ MUFU.RCP R6, R7 ; /* 0x0000000700067308 */
/* 0x001e220000001000 */
/*0120*/ BSSY B0, 0x1e0 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0130*/ FFMA R9, -R7, R6, 1 ; /* 0x3f80000007097423 */
/* 0x001fc80000000106 */
/*0140*/ FFMA R9, R6, R9, R6 ; /* 0x0000000906097223 */
/* 0x000fe40000000006 */
/*0150*/ FCHK P0, -R4, R7 ; /* 0x0000000704007302 */
/* 0x004e240000000100 */
/*0160*/ FFMA R2, -R4, R9, RZ ; /* 0x0000000904027223 */
/* 0x000fc800000001ff */
/*0170*/ FFMA R3, -R7, R2, -R4 ; /* 0x0000000207037223 */
/* 0x000fc80000000904 */
/*0180*/ FFMA R9, R9, R3, R2 ; /* 0x0000000309097223 */
/* 0x000fe20000000002 */
/*0190*/ @!P0 BRA 0x1d0 ; /* 0x0000003000008947 */
/* 0x001fea0003800000 */
/*01a0*/ FADD R5, -R4, -RZ ; /* 0x800000ff04057221 */
/* 0x000fe20000000100 */
/*01b0*/ MOV R2, 0x1d0 ; /* 0x000001d000027802 */
/* 0x000fe40000000f00 */
/*01c0*/ CALL.REL.NOINC 0x220 ; /* 0x0000005000007944 */
/* 0x000fea0003c00000 */
/*01d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*01f0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0203 */
/*0200*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101906 */
/*0210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0220*/ SHF.R.U32.HI R4, RZ, 0x17, R7 ; /* 0x00000017ff047819 */
/* 0x000fe20000011607 */
/*0230*/ BSSY B1, 0x870 ; /* 0x0000063000017945 */
/* 0x000fe20003800000 */
/*0240*/ SHF.R.U32.HI R3, RZ, 0x17, R5 ; /* 0x00000017ff037819 */
/* 0x000fe20000011605 */
/*0250*/ IMAD.MOV.U32 R6, RZ, RZ, R7 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0007 */
/*0260*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fe400078ec0ff */
/*0270*/ LOP3.LUT R3, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff03037812 */
/* 0x000fe400078ec0ff */
/*0280*/ IADD3 R10, R4, -0x1, RZ ; /* 0xffffffff040a7810 */
/* 0x000fe40007ffe0ff */
/*0290*/ IADD3 R9, R3, -0x1, RZ ; /* 0xffffffff03097810 */
/* 0x000fc40007ffe0ff */
/*02a0*/ ISETP.GT.U32.AND P0, PT, R10, 0xfd, PT ; /* 0x000000fd0a00780c */
/* 0x000fc80003f04070 */
/*02b0*/ ISETP.GT.U32.OR P0, PT, R9, 0xfd, P0 ; /* 0x000000fd0900780c */
/* 0x000fda0000704470 */
/*02c0*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff088224 */
/* 0x000fe200078e00ff */
/*02d0*/ @!P0 BRA 0x450 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*02e0*/ FSETP.GTU.FTZ.AND P0, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fe40003f1c200 */
/*02f0*/ FSETP.GTU.FTZ.AND P1, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fc80003f3c200 */
/*0300*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0310*/ @P0 BRA 0x850 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0320*/ LOP3.LUT P0, RZ, R6, 0x7fffffff, R5, 0xc8, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fda000780c805 */
/*0330*/ @!P0 BRA 0x830 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0340*/ FSETP.NEU.FTZ.AND P2, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fe40003f5d200 */
/*0350*/ FSETP.NEU.FTZ.AND P1, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fe40003f3d200 */
/*0360*/ FSETP.NEU.FTZ.AND P0, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fd60003f1d200 */
/*0370*/ @!P1 BRA !P2, 0x830 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0380*/ LOP3.LUT P2, RZ, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05ff7812 */
/* 0x000fc8000784c0ff */
/*0390*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*03a0*/ @P1 BRA 0x810 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*03b0*/ LOP3.LUT P1, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fc8000782c0ff */
/*03c0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*03d0*/ @P0 BRA 0x7e0 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*03e0*/ ISETP.GE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f06270 */
/*03f0*/ ISETP.GE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fd60003f26270 */
/*0400*/ @P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff080224 */
/* 0x000fe400078e00ff */
/*0410*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, -0x40 ; /* 0xffffffc0ff088424 */
/* 0x000fe400078e00ff */
/*0420*/ @!P0 FFMA R5, R5, 1.84467440737095516160e+19, RZ ; /* 0x5f80000005058823 */
/* 0x000fe400000000ff */
/*0430*/ @!P1 FFMA R6, R7, 1.84467440737095516160e+19, RZ ; /* 0x5f80000007069823 */
/* 0x000fe200000000ff */
/*0440*/ @!P1 IADD3 R8, R8, 0x40, RZ ; /* 0x0000004008089810 */
/* 0x000fe40007ffe0ff */
/*0450*/ LEA R7, R4, 0xc0800000, 0x17 ; /* 0xc080000004077811 */
/* 0x000fe200078eb8ff */
/*0460*/ BSSY B2, 0x7d0 ; /* 0x0000036000027945 */
/* 0x000fe80003800000 */
/*0470*/ IMAD.IADD R7, R6, 0x1, -R7 ; /* 0x0000000106077824 */
/* 0x000fe200078e0a07 */
/*0480*/ IADD3 R6, R3, -0x7f, RZ ; /* 0xffffff8103067810 */
/* 0x000fc60007ffe0ff */
/*0490*/ MUFU.RCP R9, R7 ; /* 0x0000000700097308 */
/* 0x000e220000001000 */
/*04a0*/ FADD.FTZ R10, -R7, -RZ ; /* 0x800000ff070a7221 */
/* 0x000fe40000010100 */
/*04b0*/ IMAD R5, R6, -0x800000, R5 ; /* 0xff80000006057824 */
/* 0x000fe400078e0205 */
/*04c0*/ FFMA R12, R9, R10, 1 ; /* 0x3f800000090c7423 */
/* 0x001fc8000000000a */
/*04d0*/ FFMA R14, R9, R12, R9 ; /* 0x0000000c090e7223 */
/* 0x000fc80000000009 */
/*04e0*/ FFMA R3, R5, R14, RZ ; /* 0x0000000e05037223 */
/* 0x000fc800000000ff */
/*04f0*/ FFMA R12, R10, R3, R5 ; /* 0x000000030a0c7223 */
/* 0x000fc80000000005 */
/*0500*/ FFMA R9, R14, R12, R3 ; /* 0x0000000c0e097223 */
/* 0x000fc80000000003 */
/*0510*/ FFMA R10, R10, R9, R5 ; /* 0x000000090a0a7223 */
/* 0x000fe20000000005 */
/*0520*/ IADD3 R5, R6, 0x7f, -R4 ; /* 0x0000007f06057810 */
/* 0x000fc60007ffe804 */
/*0530*/ FFMA R3, R14, R10, R9 ; /* 0x0000000a0e037223 */
/* 0x000fe40000000009 */
/*0540*/ IMAD.IADD R5, R5, 0x1, R8 ; /* 0x0000000105057824 */
/* 0x000fc600078e0208 */
/*0550*/ SHF.R.U32.HI R4, RZ, 0x17, R3 ; /* 0x00000017ff047819 */
/* 0x000fc80000011603 */
/*0560*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fca00078ec0ff */
/*0570*/ IMAD.IADD R8, R4, 0x1, R5 ; /* 0x0000000104087824 */
/* 0x000fca00078e0205 */
/*0580*/ IADD3 R4, R8, -0x1, RZ ; /* 0xffffffff08047810 */
/* 0x000fc80007ffe0ff */
/*0590*/ ISETP.GE.U32.AND P0, PT, R4, 0xfe, PT ; /* 0x000000fe0400780c */
/* 0x000fda0003f06070 */
/*05a0*/ @!P0 BRA 0x7b0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*05b0*/ ISETP.GT.AND P0, PT, R8, 0xfe, PT ; /* 0x000000fe0800780c */
/* 0x000fda0003f04270 */
/*05c0*/ @P0 BRA 0x780 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*05d0*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fda0003f06270 */
/*05e0*/ @P0 BRA 0x7c0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*05f0*/ ISETP.GE.AND P0, PT, R8, -0x18, PT ; /* 0xffffffe80800780c */
/* 0x000fe40003f06270 */
/*0600*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*0610*/ @!P0 BRA 0x7c0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0620*/ FFMA.RZ R4, R14, R10.reuse, R9.reuse ; /* 0x0000000a0e047223 */
/* 0x180fe2000000c009 */
/*0630*/ IADD3 R7, R8, 0x20, RZ ; /* 0x0000002008077810 */
/* 0x000fe20007ffe0ff */
/*0640*/ FFMA.RM R5, R14, R10.reuse, R9.reuse ; /* 0x0000000a0e057223 */
/* 0x180fe20000004009 */
/*0650*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f45270 */
/*0660*/ LOP3.LUT R6, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04067812 */
/* 0x000fe200078ec0ff */
/*0670*/ FFMA.RP R4, R14, R10, R9 ; /* 0x0000000a0e047223 */
/* 0x000fe20000008009 */
/*0680*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f25270 */
/*0690*/ IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0a08 */
/*06a0*/ LOP3.LUT R6, R6, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000006067812 */
/* 0x000fe400078efcff */
/*06b0*/ FSETP.NEU.FTZ.AND P0, PT, R4, R5, PT ; /* 0x000000050400720b */
/* 0x000fc40003f1d000 */
/*06c0*/ SHF.L.U32 R7, R6, R7, RZ ; /* 0x0000000706077219 */
/* 0x000fe400000006ff */
/*06d0*/ SEL R5, R8, RZ, P2 ; /* 0x000000ff08057207 */
/* 0x000fe40001000000 */
/*06e0*/ ISETP.NE.AND P1, PT, R7, RZ, P1 ; /* 0x000000ff0700720c */
/* 0x000fe40000f25270 */
/*06f0*/ SHF.R.U32.HI R5, RZ, R5, R6 ; /* 0x00000005ff057219 */
/* 0x000fe40000011606 */
/*0700*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0710*/ SHF.R.U32.HI R7, RZ, 0x1, R5 ; /* 0x00000001ff077819 */
/* 0x000fc40000011605 */
/*0720*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*0730*/ LOP3.LUT R4, R4, 0x1, R7, 0xf8, !PT ; /* 0x0000000104047812 */
/* 0x000fc800078ef807 */
/*0740*/ LOP3.LUT R4, R4, R5, RZ, 0xc0, !PT ; /* 0x0000000504047212 */
/* 0x000fca00078ec0ff */
/*0750*/ IMAD.IADD R4, R7, 0x1, R4 ; /* 0x0000000107047824 */
/* 0x000fca00078e0204 */
/*0760*/ LOP3.LUT R3, R4, R3, RZ, 0xfc, !PT ; /* 0x0000000304037212 */
/* 0x000fe200078efcff */
/*0770*/ BRA 0x7c0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0780*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*0790*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*07a0*/ BRA 0x7c0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*07b0*/ IMAD R3, R5, 0x800000, R3 ; /* 0x0080000005037824 */
/* 0x000fe400078e0203 */
/*07c0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*07d0*/ BRA 0x860 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*07e0*/ LOP3.LUT R3, R6, 0x80000000, R5, 0x48, !PT ; /* 0x8000000006037812 */
/* 0x000fc800078e4805 */
/*07f0*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0800*/ BRA 0x860 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0810*/ LOP3.LUT R3, R6, 0x80000000, R5, 0x48, !PT ; /* 0x8000000006037812 */
/* 0x000fe200078e4805 */
/*0820*/ BRA 0x860 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0830*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*0840*/ BRA 0x860 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0850*/ FADD.FTZ R3, R5, R7 ; /* 0x0000000705037221 */
/* 0x000fe40000010000 */
/*0860*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0870*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x001fe400078e0003 */
/*0880*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0890*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff76002007950 */
/* 0x000fea0003c3ffff */
/*08a0*/ BRA 0x8a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void cudaSAnchorBackPropagateSSD_NegSamples_kernel(const float* inputCls, float* diffOutputsCls, const float* confSamples, const int* keySamples, const int nbSamples, const int nbPositive, const unsigned int nbAnchors, const unsigned int outputsHeight, const unsigned int outputsWidth, const unsigned int batchSize)
{
const int index = (threadIdx.x & 0x1f) + blockIdx.x*blockDim.x;
if(index < nbSamples)
{
const int indexSamples = keySamples[index];
const float error = inputCls[indexSamples];
//diffOutputsCls[indexSamples] = -inputCls[index] / (nbPositive * batchSize);
//printf("error[%d]: %f\n", indexSamples, error);
diffOutputsCls[indexSamples] = -error / (nbPositive * batchSize);
}
} | .file "tmpxft_0019613a_00000000-6_cudaSAnchorBackPropagateSSD_NegSamples_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z80__device_stub__Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjjPKfPfS0_PKiiijjjj
.type _Z80__device_stub__Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjjPKfPfS0_PKiiijjjj, @function
_Z80__device_stub__Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjjPKfPfS0_PKiiijjjj:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z80__device_stub__Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjjPKfPfS0_PKiiijjjj, .-_Z80__device_stub__Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjjPKfPfS0_PKiiijjjj
.globl _Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj
.type _Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj, @function
_Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z80__device_stub__Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjjPKfPfS0_PKiiijjjj
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj, .-_Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void cudaSAnchorBackPropagateSSD_NegSamples_kernel(const float* inputCls, float* diffOutputsCls, const float* confSamples, const int* keySamples, const int nbSamples, const int nbPositive, const unsigned int nbAnchors, const unsigned int outputsHeight, const unsigned int outputsWidth, const unsigned int batchSize)
{
const int index = (threadIdx.x & 0x1f) + blockIdx.x*blockDim.x;
if(index < nbSamples)
{
const int indexSamples = keySamples[index];
const float error = inputCls[indexSamples];
//diffOutputsCls[indexSamples] = -inputCls[index] / (nbPositive * batchSize);
//printf("error[%d]: %f\n", indexSamples, error);
diffOutputsCls[indexSamples] = -error / (nbPositive * batchSize);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cudaSAnchorBackPropagateSSD_NegSamples_kernel(const float* inputCls, float* diffOutputsCls, const float* confSamples, const int* keySamples, const int nbSamples, const int nbPositive, const unsigned int nbAnchors, const unsigned int outputsHeight, const unsigned int outputsWidth, const unsigned int batchSize)
{
const int index = (threadIdx.x & 0x1f) + blockIdx.x*blockDim.x;
if(index < nbSamples)
{
const int indexSamples = keySamples[index];
const float error = inputCls[indexSamples];
//diffOutputsCls[indexSamples] = -inputCls[index] / (nbPositive * batchSize);
//printf("error[%d]: %f\n", indexSamples, error);
diffOutputsCls[indexSamples] = -error / (nbPositive * batchSize);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cudaSAnchorBackPropagateSSD_NegSamples_kernel(const float* inputCls, float* diffOutputsCls, const float* confSamples, const int* keySamples, const int nbSamples, const int nbPositive, const unsigned int nbAnchors, const unsigned int outputsHeight, const unsigned int outputsWidth, const unsigned int batchSize)
{
const int index = (threadIdx.x & 0x1f) + blockIdx.x*blockDim.x;
if(index < nbSamples)
{
const int indexSamples = keySamples[index];
const float error = inputCls[indexSamples];
//diffOutputsCls[indexSamples] = -inputCls[index] / (nbPositive * batchSize);
//printf("error[%d]: %f\n", indexSamples, error);
diffOutputsCls[indexSamples] = -error / (nbPositive * batchSize);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj
.globl _Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj
.p2align 8
.type _Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj,@function
_Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x44
s_load_b32 s3, s[0:1], 0x20
v_and_b32_e32 v2, 31, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s15, s2, v[2:3]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s0, s[0:1], 0x34
s_waitcnt lgkmcnt(0)
s_mul_i32 s0, s0, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v3, s0
s_waitcnt vmcnt(0)
v_div_scale_f32 v4, null, v3, v3, -v2
v_div_scale_f32 v7, vcc_lo, -v2, v3, -v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
v_fmac_f32_e32 v5, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, v7, v5
v_fma_f32 v8, -v4, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v8, v5
v_fma_f32 v4, -v4, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fmas_f32 v4, v4, v5, v6
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
v_div_fixup_f32 v2, v4, v3, -v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj, .Lfunc_end0-_Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cudaSAnchorBackPropagateSSD_NegSamples_kernel(const float* inputCls, float* diffOutputsCls, const float* confSamples, const int* keySamples, const int nbSamples, const int nbPositive, const unsigned int nbAnchors, const unsigned int outputsHeight, const unsigned int outputsWidth, const unsigned int batchSize)
{
const int index = (threadIdx.x & 0x1f) + blockIdx.x*blockDim.x;
if(index < nbSamples)
{
const int indexSamples = keySamples[index];
const float error = inputCls[indexSamples];
//diffOutputsCls[indexSamples] = -inputCls[index] / (nbPositive * batchSize);
//printf("error[%d]: %f\n", indexSamples, error);
diffOutputsCls[indexSamples] = -error / (nbPositive * batchSize);
}
} | .text
.file "cudaSAnchorBackPropagateSSD_NegSamples_kernel.hip"
.globl _Z60__device_stub__cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj # -- Begin function _Z60__device_stub__cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj
.p2align 4, 0x90
.type _Z60__device_stub__cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj,@function
_Z60__device_stub__cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj: # @_Z60__device_stub__cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z60__device_stub__cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj, .Lfunc_end0-_Z60__device_stub__cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj,@object # @_Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj
.section .rodata,"a",@progbits
.globl _Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj
.p2align 3, 0x0
_Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj:
.quad _Z60__device_stub__cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj
.size _Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj"
.size .L__unnamed_1, 67
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z60__device_stub__cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0030*/ LOP3.LUT R0, R0, 0x1f, RZ, 0xc0, !PT ; /* 0x0000001f00007812 */
/* 0x001fca00078ec0ff */
/*0040*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x002fca00078e0200 */
/*0050*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fda0003f06270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0090*/ IMAD.WIDE R2, R0, R5, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x000fca00078e0205 */
/*00a0*/ LDG.E R0, [R2.64] ; /* 0x0000000602007981 */
/* 0x000ea2000c1e1900 */
/*00b0*/ ULDC UR4, c[0x0][0x194] ; /* 0x0000650000047ab9 */
/* 0x000fe40000000800 */
/*00c0*/ ULDC UR5, c[0x0][0x184] ; /* 0x0000610000057ab9 */
/* 0x000fe40000000800 */
/*00d0*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fd2000f8e023f */
/*00e0*/ I2F.U32 R7, UR4 ; /* 0x0000000400077d06 */
/* 0x000e220008201000 */
/*00f0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x004fcc00078e0205 */
/*0100*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1900 */
/*0110*/ MUFU.RCP R6, R7 ; /* 0x0000000700067308 */
/* 0x001e220000001000 */
/*0120*/ BSSY B0, 0x1e0 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0130*/ FFMA R9, -R7, R6, 1 ; /* 0x3f80000007097423 */
/* 0x001fc80000000106 */
/*0140*/ FFMA R9, R6, R9, R6 ; /* 0x0000000906097223 */
/* 0x000fe40000000006 */
/*0150*/ FCHK P0, -R4, R7 ; /* 0x0000000704007302 */
/* 0x004e240000000100 */
/*0160*/ FFMA R2, -R4, R9, RZ ; /* 0x0000000904027223 */
/* 0x000fc800000001ff */
/*0170*/ FFMA R3, -R7, R2, -R4 ; /* 0x0000000207037223 */
/* 0x000fc80000000904 */
/*0180*/ FFMA R9, R9, R3, R2 ; /* 0x0000000309097223 */
/* 0x000fe20000000002 */
/*0190*/ @!P0 BRA 0x1d0 ; /* 0x0000003000008947 */
/* 0x001fea0003800000 */
/*01a0*/ FADD R5, -R4, -RZ ; /* 0x800000ff04057221 */
/* 0x000fe20000000100 */
/*01b0*/ MOV R2, 0x1d0 ; /* 0x000001d000027802 */
/* 0x000fe40000000f00 */
/*01c0*/ CALL.REL.NOINC 0x220 ; /* 0x0000005000007944 */
/* 0x000fea0003c00000 */
/*01d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*01f0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0203 */
/*0200*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101906 */
/*0210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0220*/ SHF.R.U32.HI R4, RZ, 0x17, R7 ; /* 0x00000017ff047819 */
/* 0x000fe20000011607 */
/*0230*/ BSSY B1, 0x870 ; /* 0x0000063000017945 */
/* 0x000fe20003800000 */
/*0240*/ SHF.R.U32.HI R3, RZ, 0x17, R5 ; /* 0x00000017ff037819 */
/* 0x000fe20000011605 */
/*0250*/ IMAD.MOV.U32 R6, RZ, RZ, R7 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0007 */
/*0260*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fe400078ec0ff */
/*0270*/ LOP3.LUT R3, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff03037812 */
/* 0x000fe400078ec0ff */
/*0280*/ IADD3 R10, R4, -0x1, RZ ; /* 0xffffffff040a7810 */
/* 0x000fe40007ffe0ff */
/*0290*/ IADD3 R9, R3, -0x1, RZ ; /* 0xffffffff03097810 */
/* 0x000fc40007ffe0ff */
/*02a0*/ ISETP.GT.U32.AND P0, PT, R10, 0xfd, PT ; /* 0x000000fd0a00780c */
/* 0x000fc80003f04070 */
/*02b0*/ ISETP.GT.U32.OR P0, PT, R9, 0xfd, P0 ; /* 0x000000fd0900780c */
/* 0x000fda0000704470 */
/*02c0*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff088224 */
/* 0x000fe200078e00ff */
/*02d0*/ @!P0 BRA 0x450 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*02e0*/ FSETP.GTU.FTZ.AND P0, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fe40003f1c200 */
/*02f0*/ FSETP.GTU.FTZ.AND P1, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fc80003f3c200 */
/*0300*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0310*/ @P0 BRA 0x850 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0320*/ LOP3.LUT P0, RZ, R6, 0x7fffffff, R5, 0xc8, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fda000780c805 */
/*0330*/ @!P0 BRA 0x830 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0340*/ FSETP.NEU.FTZ.AND P2, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fe40003f5d200 */
/*0350*/ FSETP.NEU.FTZ.AND P1, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fe40003f3d200 */
/*0360*/ FSETP.NEU.FTZ.AND P0, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fd60003f1d200 */
/*0370*/ @!P1 BRA !P2, 0x830 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0380*/ LOP3.LUT P2, RZ, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05ff7812 */
/* 0x000fc8000784c0ff */
/*0390*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*03a0*/ @P1 BRA 0x810 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*03b0*/ LOP3.LUT P1, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fc8000782c0ff */
/*03c0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*03d0*/ @P0 BRA 0x7e0 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*03e0*/ ISETP.GE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f06270 */
/*03f0*/ ISETP.GE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fd60003f26270 */
/*0400*/ @P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff080224 */
/* 0x000fe400078e00ff */
/*0410*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, -0x40 ; /* 0xffffffc0ff088424 */
/* 0x000fe400078e00ff */
/*0420*/ @!P0 FFMA R5, R5, 1.84467440737095516160e+19, RZ ; /* 0x5f80000005058823 */
/* 0x000fe400000000ff */
/*0430*/ @!P1 FFMA R6, R7, 1.84467440737095516160e+19, RZ ; /* 0x5f80000007069823 */
/* 0x000fe200000000ff */
/*0440*/ @!P1 IADD3 R8, R8, 0x40, RZ ; /* 0x0000004008089810 */
/* 0x000fe40007ffe0ff */
/*0450*/ LEA R7, R4, 0xc0800000, 0x17 ; /* 0xc080000004077811 */
/* 0x000fe200078eb8ff */
/*0460*/ BSSY B2, 0x7d0 ; /* 0x0000036000027945 */
/* 0x000fe80003800000 */
/*0470*/ IMAD.IADD R7, R6, 0x1, -R7 ; /* 0x0000000106077824 */
/* 0x000fe200078e0a07 */
/*0480*/ IADD3 R6, R3, -0x7f, RZ ; /* 0xffffff8103067810 */
/* 0x000fc60007ffe0ff */
/*0490*/ MUFU.RCP R9, R7 ; /* 0x0000000700097308 */
/* 0x000e220000001000 */
/*04a0*/ FADD.FTZ R10, -R7, -RZ ; /* 0x800000ff070a7221 */
/* 0x000fe40000010100 */
/*04b0*/ IMAD R5, R6, -0x800000, R5 ; /* 0xff80000006057824 */
/* 0x000fe400078e0205 */
/*04c0*/ FFMA R12, R9, R10, 1 ; /* 0x3f800000090c7423 */
/* 0x001fc8000000000a */
/*04d0*/ FFMA R14, R9, R12, R9 ; /* 0x0000000c090e7223 */
/* 0x000fc80000000009 */
/*04e0*/ FFMA R3, R5, R14, RZ ; /* 0x0000000e05037223 */
/* 0x000fc800000000ff */
/*04f0*/ FFMA R12, R10, R3, R5 ; /* 0x000000030a0c7223 */
/* 0x000fc80000000005 */
/*0500*/ FFMA R9, R14, R12, R3 ; /* 0x0000000c0e097223 */
/* 0x000fc80000000003 */
/*0510*/ FFMA R10, R10, R9, R5 ; /* 0x000000090a0a7223 */
/* 0x000fe20000000005 */
/*0520*/ IADD3 R5, R6, 0x7f, -R4 ; /* 0x0000007f06057810 */
/* 0x000fc60007ffe804 */
/*0530*/ FFMA R3, R14, R10, R9 ; /* 0x0000000a0e037223 */
/* 0x000fe40000000009 */
/*0540*/ IMAD.IADD R5, R5, 0x1, R8 ; /* 0x0000000105057824 */
/* 0x000fc600078e0208 */
/*0550*/ SHF.R.U32.HI R4, RZ, 0x17, R3 ; /* 0x00000017ff047819 */
/* 0x000fc80000011603 */
/*0560*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fca00078ec0ff */
/*0570*/ IMAD.IADD R8, R4, 0x1, R5 ; /* 0x0000000104087824 */
/* 0x000fca00078e0205 */
/*0580*/ IADD3 R4, R8, -0x1, RZ ; /* 0xffffffff08047810 */
/* 0x000fc80007ffe0ff */
/*0590*/ ISETP.GE.U32.AND P0, PT, R4, 0xfe, PT ; /* 0x000000fe0400780c */
/* 0x000fda0003f06070 */
/*05a0*/ @!P0 BRA 0x7b0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*05b0*/ ISETP.GT.AND P0, PT, R8, 0xfe, PT ; /* 0x000000fe0800780c */
/* 0x000fda0003f04270 */
/*05c0*/ @P0 BRA 0x780 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*05d0*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fda0003f06270 */
/*05e0*/ @P0 BRA 0x7c0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*05f0*/ ISETP.GE.AND P0, PT, R8, -0x18, PT ; /* 0xffffffe80800780c */
/* 0x000fe40003f06270 */
/*0600*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*0610*/ @!P0 BRA 0x7c0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0620*/ FFMA.RZ R4, R14, R10.reuse, R9.reuse ; /* 0x0000000a0e047223 */
/* 0x180fe2000000c009 */
/*0630*/ IADD3 R7, R8, 0x20, RZ ; /* 0x0000002008077810 */
/* 0x000fe20007ffe0ff */
/*0640*/ FFMA.RM R5, R14, R10.reuse, R9.reuse ; /* 0x0000000a0e057223 */
/* 0x180fe20000004009 */
/*0650*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f45270 */
/*0660*/ LOP3.LUT R6, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04067812 */
/* 0x000fe200078ec0ff */
/*0670*/ FFMA.RP R4, R14, R10, R9 ; /* 0x0000000a0e047223 */
/* 0x000fe20000008009 */
/*0680*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f25270 */
/*0690*/ IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0a08 */
/*06a0*/ LOP3.LUT R6, R6, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000006067812 */
/* 0x000fe400078efcff */
/*06b0*/ FSETP.NEU.FTZ.AND P0, PT, R4, R5, PT ; /* 0x000000050400720b */
/* 0x000fc40003f1d000 */
/*06c0*/ SHF.L.U32 R7, R6, R7, RZ ; /* 0x0000000706077219 */
/* 0x000fe400000006ff */
/*06d0*/ SEL R5, R8, RZ, P2 ; /* 0x000000ff08057207 */
/* 0x000fe40001000000 */
/*06e0*/ ISETP.NE.AND P1, PT, R7, RZ, P1 ; /* 0x000000ff0700720c */
/* 0x000fe40000f25270 */
/*06f0*/ SHF.R.U32.HI R5, RZ, R5, R6 ; /* 0x00000005ff057219 */
/* 0x000fe40000011606 */
/*0700*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0710*/ SHF.R.U32.HI R7, RZ, 0x1, R5 ; /* 0x00000001ff077819 */
/* 0x000fc40000011605 */
/*0720*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*0730*/ LOP3.LUT R4, R4, 0x1, R7, 0xf8, !PT ; /* 0x0000000104047812 */
/* 0x000fc800078ef807 */
/*0740*/ LOP3.LUT R4, R4, R5, RZ, 0xc0, !PT ; /* 0x0000000504047212 */
/* 0x000fca00078ec0ff */
/*0750*/ IMAD.IADD R4, R7, 0x1, R4 ; /* 0x0000000107047824 */
/* 0x000fca00078e0204 */
/*0760*/ LOP3.LUT R3, R4, R3, RZ, 0xfc, !PT ; /* 0x0000000304037212 */
/* 0x000fe200078efcff */
/*0770*/ BRA 0x7c0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0780*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*0790*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*07a0*/ BRA 0x7c0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*07b0*/ IMAD R3, R5, 0x800000, R3 ; /* 0x0080000005037824 */
/* 0x000fe400078e0203 */
/*07c0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*07d0*/ BRA 0x860 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*07e0*/ LOP3.LUT R3, R6, 0x80000000, R5, 0x48, !PT ; /* 0x8000000006037812 */
/* 0x000fc800078e4805 */
/*07f0*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0800*/ BRA 0x860 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0810*/ LOP3.LUT R3, R6, 0x80000000, R5, 0x48, !PT ; /* 0x8000000006037812 */
/* 0x000fe200078e4805 */
/*0820*/ BRA 0x860 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0830*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*0840*/ BRA 0x860 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0850*/ FADD.FTZ R3, R5, R7 ; /* 0x0000000705037221 */
/* 0x000fe40000010000 */
/*0860*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0870*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x001fe400078e0003 */
/*0880*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0890*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff76002007950 */
/* 0x000fea0003c3ffff */
/*08a0*/ BRA 0x8a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj
.globl _Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj
.p2align 8
.type _Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj,@function
_Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x44
s_load_b32 s3, s[0:1], 0x20
v_and_b32_e32 v2, 31, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s15, s2, v[2:3]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s0, s[0:1], 0x34
s_waitcnt lgkmcnt(0)
s_mul_i32 s0, s0, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v3, s0
s_waitcnt vmcnt(0)
v_div_scale_f32 v4, null, v3, v3, -v2
v_div_scale_f32 v7, vcc_lo, -v2, v3, -v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
v_fmac_f32_e32 v5, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, v7, v5
v_fma_f32 v8, -v4, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v8, v5
v_fma_f32 v4, -v4, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fmas_f32 v4, v4, v5, v6
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
v_div_fixup_f32 v2, v4, v3, -v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj, .Lfunc_end0-_Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0019613a_00000000-6_cudaSAnchorBackPropagateSSD_NegSamples_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z80__device_stub__Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjjPKfPfS0_PKiiijjjj
.type _Z80__device_stub__Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjjPKfPfS0_PKiiijjjj, @function
_Z80__device_stub__Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjjPKfPfS0_PKiiijjjj:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z80__device_stub__Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjjPKfPfS0_PKiiijjjj, .-_Z80__device_stub__Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjjPKfPfS0_PKiiijjjj
.globl _Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj
.type _Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj, @function
_Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z80__device_stub__Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjjPKfPfS0_PKiiijjjj
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj, .-_Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cudaSAnchorBackPropagateSSD_NegSamples_kernel.hip"
.globl _Z60__device_stub__cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj # -- Begin function _Z60__device_stub__cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj
.p2align 4, 0x90
.type _Z60__device_stub__cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj,@function
_Z60__device_stub__cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj: # @_Z60__device_stub__cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z60__device_stub__cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj, .Lfunc_end0-_Z60__device_stub__cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj,@object # @_Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj
.section .rodata,"a",@progbits
.globl _Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj
.p2align 3, 0x0
_Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj:
.quad _Z60__device_stub__cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj
.size _Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj"
.size .L__unnamed_1, 67
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z60__device_stub__cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z45cudaSAnchorBackPropagateSSD_NegSamples_kernelPKfPfS0_PKiiijjjj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /* Cuda Program for finding cos(0), cos(1*2*pi/N), ... , cos((N-1)*2*pi/N) */
// nvcc CUDA_example_01.cu -use_fast_math -o CUDA_example_01.out
/* --------------------------- header secton ----------------------------*/
#include<stdio.h>
#include<cuda.h>
#define PRINT_RESULT 1
#define COS_THREAD_CNT 512
#define N 1000000
#define TWO_PI 6.283185
/* --------------------------- target code ------------------------------*/
struct cosParams {
float *arg;
float *res;
int n;
};
// CUDA kernel:
__global__ void cos_main(struct cosParams params)
{
// Computes:
// res[threadIdx.x + 0*COS_THREAD_CNT] = cos(threadIdx.x + 0*COS_THREAD_CNT)
// res[threadIdx.x + 1*COS_THREAD_CNT] = cos(threadIdx.x + 1*COS_THREAD_CNT)
// res[threadIdx.x + 2*COS_THREAD_CNT] = cos(threadIdx.x + 2*COS_THREAD_CNT)
// ...etc...
//
// if COS_THREAD_CNT = 1, this computes all of the cosines in one go,
// otherwise, it spreads it out across threads...
//
// Choice of either:
//
// __cosf:
// Calculate the fast approximate cosine of the input argument x, measured in radians.
//
// cosf:
// Calculate the cosine of the input argument x (measured in radians).
int i;
for (i=threadIdx.x; i<params.n; i+=COS_THREAD_CNT){
// params.res[i] = __cosf(params.arg[i]);
params.res[i] = cosf(params.arg[i]);
}
return;
}
/* --------------------------- host code ------------------------------*/
int main (int argc, char *argv[])
{
printf("\nBeginning CUDA example code on the CPU...\n");
printf("Getting some info about CUDA devices on your system...\n");
int i, devCount;
cudaGetDeviceCount(&devCount);
if (devCount == 1){
printf("There is %d CUDA device on your system.\n", devCount);
} else {
printf("There are %d CUDA devices on your system.\n", devCount);
}
// Iterate through devices
for (i=0; i<devCount; i++)
{
// Get device properties
printf("\nCUDA Device #%d\n", i);
cudaDeviceProp devProp;
cudaGetDeviceProperties(&devProp, i);
printf("Name: %s\n", devProp.name);
}
printf("\n");
// Begin cosine code:
cudaError_t cudaStat;
float* gpu_res = 0;
float* gpu_arg = 0;
printf("Allocating memory on the CPU... (n=%d)\n",(int)N);
// Allocate the vector 1,...,N:
float *arg = (float *) malloc(N*sizeof(float));
// Allocate vector of length N to store the result:
float *res = (float *) malloc(N*sizeof(float));
int print_every = (int)((double)N/10.0);
struct cosParams funcParams;
// Populate arg with 1,...,N
for(i=0; i<N; i++){
arg[i] = (float)i*(float)TWO_PI/(float)N;
}
printf("Allocating memory on the GPU... (n=%d)\n",(int)N);
// Key function:
// cudaError_t cudaMalloc(void ** devPtr, size_t size);
// Allocate N floats on the GPU for the argument 0,1,...,N-1, and make gpu_arg a pointer to that memory:
// NOTE: sizeof(gpu_arg[0]) is equivalent to sizeof(float) here
cudaStat = cudaMalloc((void **)&gpu_arg, N*sizeof(gpu_arg[0]));
if (cudaStat){
printf(" value = %d : Memory Allocation on GPU Device failed\n", cudaStat);
} else {
printf("done. Allocating more memory on the GPU...\n");
}
// Allocate N floats on the GPU to store the result, and make gpu_res a pointer to that memory:
// NOTE: sizeof(gpu_res[0]) is equivalent to sizeof(float) here
cudaStat = cudaMalloc((void **)&gpu_res, N*sizeof(gpu_res[0]));
if (cudaStat){
printf(" value = %d : Memory Allocation on GPU Device failed\n", (int)cudaStat);
} else {
printf("done again. Copying stuff from host (CPU) to device (GPU)...\n");
}
// Key function:
// cudaError_t cudaMemcpy(void * dst, const void * src, size_t count, enum cudaMemcpyKind kind);
// Copy the vector 0,1,...,N-1 from arg (on the host) to gpu_arg (on the device)
// NOTE: sizeof(arg[0]) is equivalent to sizeof(float) here
cudaStat = cudaMemcpy(gpu_arg, arg, N*sizeof(arg[0]), cudaMemcpyHostToDevice);
if (cudaStat){
printf(" Memory Copy from Host to Device failed.\n");
} else {
printf("successful.\n");
}
// Set up the parameters for the GPU kernel:
funcParams.res = gpu_res;
funcParams.arg = gpu_arg;
funcParams.n = N;
printf("Launching kernel on GPU...\n");
// Launch the GPU kernel...
// Key code:
// KernelFunction<<<dimGrid, dimBlock>>>(args);
cos_main<<<1,COS_THREAD_CNT>>>(funcParams);
printf("GPU computations finished. Copying result back to CPU...\n");
// Copy the vector cos(0),cos(1),...,cos(N-1) from gpu_res (on the device) to res (on the host)
cudaStat = cudaMemcpy(res, gpu_res, N*sizeof(gpu_res[0]), cudaMemcpyDeviceToHost);
if (cudaStat){
printf(" Memory Copy from Device to Host failed.\n");
} else {
printf("Copy back successful. Printing result...\n");
}
if (PRINT_RESULT){
// Print the result?
for(i=0; i < N; i++ ){
if (i%print_every == 0 ){
printf("cos(%f) = %f\n", arg[i], res[i] );
}
}
}
printf("Freeing memory...\n");
free(arg);
free(res);
cudaFree(gpu_arg);
cudaFree(gpu_res);
printf("\n\nFinished. :)\n\n");
return 0;
} | code for sm_80
Function : _Z8cos_main9cosParams
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0050*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fc800078e00ff */
/*0060*/ IMAD.WIDE R6, R0, R7, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fca00078e0207 */
/*0070*/ LDG.E R3, [R6.64] ; /* 0x0000000606037981 */
/* 0x001ea2000c1e1900 */
/*0080*/ BSSY B0, 0x7f0 ; /* 0x0000076000007945 */
/* 0x000fe20003800000 */
/*0090*/ FMUL R4, R3.reuse, 0.63661974668502807617 ; /* 0x3f22f98303047820 */
/* 0x044fe20000400000 */
/*00a0*/ FSETP.GE.AND P0, PT, |R3|, 105615, PT ; /* 0x47ce47800300780b */
/* 0x000fca0003f06200 */
/*00b0*/ F2I.NTZ R4, R4 ; /* 0x0000000400047305 */
/* 0x000e300000203100 */
/*00c0*/ I2F R8, R4 ; /* 0x0000000400087306 */
/* 0x001e240000201400 */
/*00d0*/ FFMA R5, R8, -1.5707962512969970703, R3 ; /* 0xbfc90fda08057823 */
/* 0x001fc80000000003 */
/*00e0*/ FFMA R9, R8, -7.5497894158615963534e-08, R5 ; /* 0xb3a2216808097823 */
/* 0x000fe20000000005 */
/*00f0*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x000fc60000011400 */
/*0100*/ FFMA R17, R8, -5.3903029534742383927e-15, R9 ; /* 0xa7c234c508117823 */
/* 0x000fe20000000009 */
/*0110*/ @!P0 BRA 0x7e0 ; /* 0x000006c000008947 */
/* 0x000fea0003800000 */
/*0120*/ FSETP.NEU.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fda0003f0d200 */
/*0130*/ @!P0 BRA 0x7c0 ; /* 0x0000068000008947 */
/* 0x000fea0003800000 */
/*0140*/ SHF.R.U32.HI R4, RZ, 0x17, R3 ; /* 0x00000017ff047819 */
/* 0x000fe20000011603 */
/*0150*/ IMAD.SHL.U32 R7, R3, 0x100, RZ ; /* 0x0000010003077824 */
/* 0x000fe200078e00ff */
/*0160*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0170*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e00ff */
/*0180*/ LOP3.LUT R6, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04067812 */
/* 0x000fe200078ec0ff */
/*0190*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*01a0*/ LOP3.LUT R17, R7, 0x80000000, RZ, 0xfc, !PT ; /* 0x8000000007117812 */
/* 0x000fe200078efcff */
/*01b0*/ IMAD.MOV.U32 R19, RZ, RZ, RZ ; /* 0x000000ffff137224 */
/* 0x000fe200078e00ff */
/*01c0*/ IADD3 R11, R6, -0x80, RZ ; /* 0xffffff80060b7810 */
/* 0x000fe20007ffe0ff */
/*01d0*/ ULDC.64 UR8, c[0x4][0x0] ; /* 0x0100000000087ab9 */
/* 0x000fc60000000a00 */
/*01e0*/ SHF.R.U32.HI R18, RZ, 0x5, R11 ; /* 0x00000005ff127819 */
/* 0x000fe4000001160b */
/*01f0*/ IMAD.U32 R8, RZ, RZ, UR8 ; /* 0x00000008ff087e24 */
/* 0x000fe4000f8e00ff */
/*0200*/ IMAD.U32 R9, RZ, RZ, UR9 ; /* 0x00000009ff097e24 */
/* 0x000fca000f8e00ff */
/*0210*/ LDG.E.CONSTANT R6, [R8.64] ; /* 0x0000000608067981 */
/* 0x000ea2000c1e9900 */
/*0220*/ IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a7810 */
/* 0x000fe20007ffe0ff */
/*0230*/ UIADD3 UR8, UP0, UR8, 0x4, URZ ; /* 0x0000000408087890 */
/* 0x000fe2000ff1e03f */
/*0240*/ ISETP.EQ.AND P0, PT, R19.reuse, RZ, PT ; /* 0x000000ff1300720c */
/* 0x040fe40003f02270 */
/*0250*/ ISETP.EQ.AND P5, PT, R19.reuse, 0x4, PT ; /* 0x000000041300780c */
/* 0x040fe20003fa2270 */
/*0260*/ UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; /* 0x000000093f097290 */
/* 0x000fe200087fe43f */
/*0270*/ ISETP.EQ.AND P4, PT, R19.reuse, 0x8, PT ; /* 0x000000081300780c */
/* 0x040fe40003f82270 */
/*0280*/ ISETP.EQ.AND P3, PT, R19.reuse, 0xc, PT ; /* 0x0000000c1300780c */
/* 0x040fe40003f62270 */
/*0290*/ ISETP.EQ.AND P2, PT, R19, 0x10, PT ; /* 0x000000101300780c */
/* 0x000fc40003f42270 */
/*02a0*/ ISETP.EQ.AND P1, PT, R19.reuse, 0x14, PT ; /* 0x000000141300780c */
/* 0x040fe40003f22270 */
/*02b0*/ IADD3 R19, R19, 0x4, RZ ; /* 0x0000000413137810 */
/* 0x000fe20007ffe0ff */
/*02c0*/ IMAD.WIDE.U32 R6, R6, R17, RZ ; /* 0x0000001106067225 */
/* 0x004fca00078e00ff */
/*02d0*/ IADD3 R6, P6, R6, R4, RZ ; /* 0x0000000406067210 */
/* 0x000fc80007fde0ff */
/*02e0*/ IADD3.X R4, R7, UR4, RZ, P6, !PT ; /* 0x0000000407047c10 */
/* 0x000fe2000b7fe4ff */
/*02f0*/ @P0 IMAD.MOV.U32 R2, RZ, RZ, R6.reuse ; /* 0x000000ffff020224 */
/* 0x100fe200078e0006 */
/*0300*/ ISETP.NE.AND P6, PT, R10, 0x6, PT ; /* 0x000000060a00780c */
/* 0x000fe20003fc5270 */
/*0310*/ @P5 IMAD.MOV.U32 R12, RZ, RZ, R6.reuse ; /* 0x000000ffff0c5224 */
/* 0x100fe400078e0006 */
/*0320*/ @P4 IMAD.MOV.U32 R13, RZ, RZ, R6.reuse ; /* 0x000000ffff0d4224 */
/* 0x100fe400078e0006 */
/*0330*/ @P3 IMAD.MOV.U32 R14, RZ, RZ, R6.reuse ; /* 0x000000ffff0e3224 */
/* 0x100fe400078e0006 */
/*0340*/ @P2 IMAD.MOV.U32 R15, RZ, RZ, R6.reuse ; /* 0x000000ffff0f2224 */
/* 0x100fe400078e0006 */
/*0350*/ @P1 IMAD.MOV.U32 R16, RZ, RZ, R6 ; /* 0x000000ffff101224 */
/* 0x000fc800078e0006 */
/*0360*/ @P6 BRA 0x1f0 ; /* 0xfffffe8000006947 */
/* 0x000fea000383ffff */
/*0370*/ IADD3 R6, -R18, 0x6, RZ ; /* 0x0000000612067810 */
/* 0x000fe20007ffe1ff */
/*0380*/ BSSY B1, 0x6b0 ; /* 0x0000032000017945 */
/* 0x000fe80003800000 */
/*0390*/ IMAD.SHL.U32 R6, R6, 0x4, RZ ; /* 0x0000000406067824 */
/* 0x000fca00078e00ff */
/*03a0*/ ISETP.EQ.AND P0, PT, R6.reuse, RZ, PT ; /* 0x000000ff0600720c */
/* 0x040fe40003f02270 */
/*03b0*/ ISETP.EQ.AND P3, PT, R6.reuse, 0x4, PT ; /* 0x000000040600780c */
/* 0x040fe40003f62270 */
/*03c0*/ ISETP.EQ.AND P4, PT, R6.reuse, 0x8, PT ; /* 0x000000080600780c */
/* 0x040fe40003f82270 */
/*03d0*/ ISETP.EQ.AND P2, PT, R6.reuse, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x040fe40003f42270 */
/*03e0*/ ISETP.EQ.AND P1, PT, R6, 0x10, PT ; /* 0x000000100600780c */
/* 0x000fca0003f22270 */
/*03f0*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, R2.reuse ; /* 0x000000ffff070224 */
/* 0x100fe200078e0002 */
/*0400*/ ISETP.EQ.AND P0, PT, R6.reuse, 0x14, PT ; /* 0x000000140600780c */
/* 0x040fe20003f02270 */
/*0410*/ @P3 IMAD.MOV.U32 R8, RZ, RZ, R2 ; /* 0x000000ffff083224 */
/* 0x000fe400078e0002 */
/*0420*/ @P3 IMAD.MOV.U32 R7, RZ, RZ, R12.reuse ; /* 0x000000ffff073224 */
/* 0x100fe200078e000c */
/*0430*/ ISETP.EQ.AND P3, PT, R6.reuse, 0x18, PT ; /* 0x000000180600780c */
/* 0x040fe20003f62270 */
/*0440*/ @P4 IMAD.MOV.U32 R8, RZ, RZ, R12 ; /* 0x000000ffff084224 */
/* 0x000fe400078e000c */
/*0450*/ @P4 IMAD.MOV.U32 R7, RZ, RZ, R13.reuse ; /* 0x000000ffff074224 */
/* 0x100fe200078e000d */
/*0460*/ ISETP.EQ.AND P4, PT, R6, 0x1c, PT ; /* 0x0000001c0600780c */
/* 0x000fe20003f82270 */
/*0470*/ @P2 IMAD.MOV.U32 R8, RZ, RZ, R13 ; /* 0x000000ffff082224 */
/* 0x000fc400078e000d */
/*0480*/ @P2 IMAD.MOV.U32 R7, RZ, RZ, R14.reuse ; /* 0x000000ffff072224 */
/* 0x100fe400078e000e */
/*0490*/ @P1 IMAD.MOV.U32 R8, RZ, RZ, R14 ; /* 0x000000ffff081224 */
/* 0x000fe400078e000e */
/*04a0*/ @P1 IMAD.MOV.U32 R7, RZ, RZ, R15.reuse ; /* 0x000000ffff071224 */
/* 0x100fe200078e000f */
/*04b0*/ LOP3.LUT P1, R11, R11, 0x1f, RZ, 0xc0, !PT ; /* 0x0000001f0b0b7812 */
/* 0x000fe2000782c0ff */
/*04c0*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, R16 ; /* 0x000000ffff070224 */
/* 0x000fe400078e0010 */
/*04d0*/ @P3 IMAD.MOV.U32 R7, RZ, RZ, R4 ; /* 0x000000ffff073224 */
/* 0x000fe400078e0004 */
/*04e0*/ @P0 IMAD.MOV.U32 R8, RZ, RZ, R15 ; /* 0x000000ffff080224 */
/* 0x000fc400078e000f */
/*04f0*/ @P3 IMAD.MOV.U32 R8, RZ, RZ, R16 ; /* 0x000000ffff083224 */
/* 0x000fe400078e0010 */
/*0500*/ @P4 IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff084224 */
/* 0x000fe400078e0004 */
/*0510*/ IMAD.MOV.U32 R6, RZ, RZ, R7 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0007 */
/*0520*/ @!P1 BRA 0x6a0 ; /* 0x0000017000009947 */
/* 0x000fea0003800000 */
/*0530*/ IADD3 R7, -R18, 0x4, RZ ; /* 0x0000000412077810 */
/* 0x000fe40007ffe1ff */
/*0540*/ SHF.L.U32 R9, R6, R11, RZ ; /* 0x0000000b06097219 */
/* 0x000fc600000006ff */
/*0550*/ IMAD.SHL.U32 R7, R7, 0x4, RZ ; /* 0x0000000407077824 */
/* 0x000fca00078e00ff */
/*0560*/ ISETP.EQ.AND P0, PT, R7.reuse, RZ, PT ; /* 0x000000ff0700720c */
/* 0x040fe40003f02270 */
/*0570*/ ISETP.EQ.AND P1, PT, R7.reuse, 0x4, PT ; /* 0x000000040700780c */
/* 0x040fe40003f22270 */
/*0580*/ ISETP.EQ.AND P2, PT, R7.reuse, 0x8, PT ; /* 0x000000080700780c */
/* 0x040fe40003f42270 */
/*0590*/ ISETP.EQ.AND P3, PT, R7, 0xc, PT ; /* 0x0000000c0700780c */
/* 0x000fce0003f62270 */
/*05a0*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, R2 ; /* 0x000000ffff0a0224 */
/* 0x000fe200078e0002 */
/*05b0*/ ISETP.EQ.AND P0, PT, R7.reuse, 0x10, PT ; /* 0x000000100700780c */
/* 0x040fe20003f02270 */
/*05c0*/ @P1 IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a1224 */
/* 0x000fe200078e000c */
/*05d0*/ ISETP.EQ.AND P1, PT, R7.reuse, 0x14, PT ; /* 0x000000140700780c */
/* 0x040fe20003f22270 */
/*05e0*/ @P2 IMAD.MOV.U32 R10, RZ, RZ, R13 ; /* 0x000000ffff0a2224 */
/* 0x000fe200078e000d */
/*05f0*/ ISETP.EQ.AND P2, PT, R7, 0x18, PT ; /* 0x000000180700780c */
/* 0x000fe20003f42270 */
/*0600*/ @P3 IMAD.MOV.U32 R10, RZ, RZ, R14 ; /* 0x000000ffff0a3224 */
/* 0x000fe200078e000e */
/*0610*/ IADD3 R7, -R11, 0x20, RZ ; /* 0x000000200b077810 */
/* 0x000fc80007ffe1ff */
/*0620*/ SHF.R.U32.HI R6, RZ, R7, R8 ; /* 0x00000007ff067219 */
/* 0x000fc60000011608 */
/*0630*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, R15 ; /* 0x000000ffff0a0224 */
/* 0x000fe400078e000f */
/*0640*/ @P1 IMAD.MOV.U32 R10, RZ, RZ, R16 ; /* 0x000000ffff0a1224 */
/* 0x000fe400078e0010 */
/*0650*/ @P2 IMAD.MOV.U32 R10, RZ, RZ, R4 ; /* 0x000000ffff0a2224 */
/* 0x000fe200078e0004 */
/*0660*/ SHF.L.U32 R4, R8, R11, RZ ; /* 0x0000000b08047219 */
/* 0x000fe200000006ff */
/*0670*/ IMAD.IADD R6, R6, 0x1, R9 ; /* 0x0000000106067824 */
/* 0x000fc600078e0209 */
/*0680*/ SHF.R.U32.HI R7, RZ, R7, R10 ; /* 0x00000007ff077219 */
/* 0x000fca000001160a */
/*0690*/ IMAD.IADD R8, R7, 0x1, R4 ; /* 0x0000000107087824 */
/* 0x000fe400078e0204 */
/*06a0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*06b0*/ SHF.L.U32.HI R11, R8.reuse, 0x2, R6 ; /* 0x00000002080b7819 */
/* 0x040fe20000010606 */
/*06c0*/ IMAD.SHL.U32 R10, R8, 0x4, RZ ; /* 0x00000004080a7824 */
/* 0x000fe200078e00ff */
/*06d0*/ LOP3.LUT P1, R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fe4000782c0ff */
/*06e0*/ SHF.R.U32.HI R7, RZ, 0x1f, R11 ; /* 0x0000001fff077819 */
/* 0x000fc8000001160b */
/*06f0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f05270 */
/*0700*/ LEA.HI R4, R6, R7, RZ, 0x2 ; /* 0x0000000706047211 */
/* 0x000fd600078f10ff */
/*0710*/ @P0 LOP3.LUT R11, RZ, R11, RZ, 0x33, !PT ; /* 0x0000000bff0b0212 */
/* 0x000fe400078e33ff */
/*0720*/ @P0 LOP3.LUT R10, RZ, R10, RZ, 0x33, !PT ; /* 0x0000000aff0a0212 */
/* 0x000fe400078e33ff */
/*0730*/ @P0 LOP3.LUT R3, R3, 0x80000000, RZ, 0x3c, !PT ; /* 0x8000000003030812 */
/* 0x000fe400078e3cff */
/*0740*/ I2F.F64.S64 R8, R10 ; /* 0x0000000a00087312 */
/* 0x000e240000301c00 */
/*0750*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003f05270 */
/*0760*/ IMAD.MOV R3, RZ, RZ, -R4 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a04 */
/*0770*/ @P1 IMAD.MOV.U32 R4, RZ, RZ, R3 ; /* 0x000000ffff041224 */
/* 0x000fe200078e0003 */
/*0780*/ DMUL R8, R8, c[0x2][0x0] ; /* 0x0080000008087a28 */
/* 0x001e140000000000 */
/*0790*/ F2F.F32.F64 R8, R8 ; /* 0x0000000800087310 */
/* 0x001e240000301000 */
/*07a0*/ FSEL R17, R8, -R8, !P0 ; /* 0x8000000808117208 */
/* 0x001fe20004000000 */
/*07b0*/ BRA 0x7e0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*07c0*/ FMUL R17, RZ, R3 ; /* 0x00000003ff117220 */
/* 0x000fe40000400000 */
/*07d0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe400078e00ff */
/*07e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*07f0*/ IADD3 R8, R4, 0x1, RZ ; /* 0x0000000104087810 */
/* 0x000fe20007ffe0ff */
/*0800*/ IMAD.MOV.U32 R4, RZ, RZ, 0x3c0885e4 ; /* 0x3c0885e4ff047424 */
/* 0x000fe400078e00ff */
/*0810*/ FMUL R9, R17, R17 ; /* 0x0000001111097220 */
/* 0x000fe20000400000 */
/*0820*/ LOP3.LUT P1, RZ, R8.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000108ff7812 */
/* 0x040fe2000782c0ff */
/*0830*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3e2aaaa8 ; /* 0x3e2aaaa8ff077424 */
/* 0x000fe200078e00ff */
/*0840*/ LOP3.LUT P0, RZ, R8, 0x2, RZ, 0xc0, !PT ; /* 0x0000000208ff7812 */
/* 0x000fe2000780c0ff */
/*0850*/ IMAD.MOV.U32 R3, RZ, RZ, -0x46b2bead ; /* 0xb94d4153ff037424 */
/* 0x000fe200078e00ff */
/*0860*/ FSEL R4, R4, 0.041666727513074874878, !P1 ; /* 0x3d2aaabb04047808 */
/* 0x000fc40004800000 */
/*0870*/ FSEL R17, R17, 1, !P1 ; /* 0x3f80000011117808 */
/* 0x000fca0004800000 */
/*0880*/ FFMA R8, R17, R9, RZ ; /* 0x0000000911087223 */
/* 0x000fe400000000ff */
/*0890*/ @P1 IMAD.MOV.U32 R6, RZ, RZ, 0x37cbac00 ; /* 0x37cbac00ff061424 */
/* 0x000fc800078e00ff */
/*08a0*/ @P1 FFMA R3, R9, R6, -0.0013887860113754868507 ; /* 0xbab607ed09031423 */
/* 0x000fe20000000006 */
/*08b0*/ FSEL R6, -R7, -0.4999999701976776123, !P1 ; /* 0xbeffffff07067808 */
/* 0x000fc60004800100 */
/*08c0*/ FFMA R3, R9, R3, R4 ; /* 0x0000000309037223 */
/* 0x000fe20000000004 */
/*08d0*/ LEA R4, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000047a11 */
/* 0x000fc600078210ff */
/*08e0*/ FFMA R3, R9, R3, R6 ; /* 0x0000000309037223 */
/* 0x000fe20000000006 */
/*08f0*/ LEA.HI.X R5, R0.reuse, c[0x0][0x16c], R5, 0x2, P1 ; /* 0x00005b0000057a11 */
/* 0x040fe400008f1405 */
/*0900*/ IADD3 R0, R0, 0x200, RZ ; /* 0x0000020000007810 */
/* 0x000fe20007ffe0ff */
/*0910*/ FFMA R3, R3, R8, R17 ; /* 0x0000000803037223 */
/* 0x000fc80000000011 */
/*0920*/ @P0 FFMA R3, R3, -1, RZ ; /* 0xbf80000003030823 */
/* 0x000fe200000000ff */
/*0930*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fc80003f06270 */
/*0940*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0001f2000c101906 */
/*0950*/ @!P0 BRA 0x50 ; /* 0xfffff6f000008947 */
/* 0x000fea000383ffff */
/*0960*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0970*/ BRA 0x970; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* Cuda Program for finding cos(0), cos(1*2*pi/N), ... , cos((N-1)*2*pi/N) */
// nvcc CUDA_example_01.cu -use_fast_math -o CUDA_example_01.out
/* --------------------------- header secton ----------------------------*/
#include<stdio.h>
#include<cuda.h>
#define PRINT_RESULT 1
#define COS_THREAD_CNT 512
#define N 1000000
#define TWO_PI 6.283185
/* --------------------------- target code ------------------------------*/
struct cosParams {
float *arg;
float *res;
int n;
};
// CUDA kernel:
__global__ void cos_main(struct cosParams params)
{
// Computes:
// res[threadIdx.x + 0*COS_THREAD_CNT] = cos(threadIdx.x + 0*COS_THREAD_CNT)
// res[threadIdx.x + 1*COS_THREAD_CNT] = cos(threadIdx.x + 1*COS_THREAD_CNT)
// res[threadIdx.x + 2*COS_THREAD_CNT] = cos(threadIdx.x + 2*COS_THREAD_CNT)
// ...etc...
//
// if COS_THREAD_CNT = 1, this computes all of the cosines in one go,
// otherwise, it spreads it out across threads...
//
// Choice of either:
//
// __cosf:
// Calculate the fast approximate cosine of the input argument x, measured in radians.
//
// cosf:
// Calculate the cosine of the input argument x (measured in radians).
int i;
for (i=threadIdx.x; i<params.n; i+=COS_THREAD_CNT){
// params.res[i] = __cosf(params.arg[i]);
params.res[i] = cosf(params.arg[i]);
}
return;
}
/* --------------------------- host code ------------------------------*/
int main (int argc, char *argv[])
{
printf("\nBeginning CUDA example code on the CPU...\n");
printf("Getting some info about CUDA devices on your system...\n");
int i, devCount;
cudaGetDeviceCount(&devCount);
if (devCount == 1){
printf("There is %d CUDA device on your system.\n", devCount);
} else {
printf("There are %d CUDA devices on your system.\n", devCount);
}
// Iterate through devices
for (i=0; i<devCount; i++)
{
// Get device properties
printf("\nCUDA Device #%d\n", i);
cudaDeviceProp devProp;
cudaGetDeviceProperties(&devProp, i);
printf("Name: %s\n", devProp.name);
}
printf("\n");
// Begin cosine code:
cudaError_t cudaStat;
float* gpu_res = 0;
float* gpu_arg = 0;
printf("Allocating memory on the CPU... (n=%d)\n",(int)N);
// Allocate the vector 1,...,N:
float *arg = (float *) malloc(N*sizeof(float));
// Allocate vector of length N to store the result:
float *res = (float *) malloc(N*sizeof(float));
int print_every = (int)((double)N/10.0);
struct cosParams funcParams;
// Populate arg with 1,...,N
for(i=0; i<N; i++){
arg[i] = (float)i*(float)TWO_PI/(float)N;
}
printf("Allocating memory on the GPU... (n=%d)\n",(int)N);
// Key function:
// cudaError_t cudaMalloc(void ** devPtr, size_t size);
// Allocate N floats on the GPU for the argument 0,1,...,N-1, and make gpu_arg a pointer to that memory:
// NOTE: sizeof(gpu_arg[0]) is equivalent to sizeof(float) here
cudaStat = cudaMalloc((void **)&gpu_arg, N*sizeof(gpu_arg[0]));
if (cudaStat){
printf(" value = %d : Memory Allocation on GPU Device failed\n", cudaStat);
} else {
printf("done. Allocating more memory on the GPU...\n");
}
// Allocate N floats on the GPU to store the result, and make gpu_res a pointer to that memory:
// NOTE: sizeof(gpu_res[0]) is equivalent to sizeof(float) here
cudaStat = cudaMalloc((void **)&gpu_res, N*sizeof(gpu_res[0]));
if (cudaStat){
printf(" value = %d : Memory Allocation on GPU Device failed\n", (int)cudaStat);
} else {
printf("done again. Copying stuff from host (CPU) to device (GPU)...\n");
}
// Key function:
// cudaError_t cudaMemcpy(void * dst, const void * src, size_t count, enum cudaMemcpyKind kind);
// Copy the vector 0,1,...,N-1 from arg (on the host) to gpu_arg (on the device)
// NOTE: sizeof(arg[0]) is equivalent to sizeof(float) here
cudaStat = cudaMemcpy(gpu_arg, arg, N*sizeof(arg[0]), cudaMemcpyHostToDevice);
if (cudaStat){
printf(" Memory Copy from Host to Device failed.\n");
} else {
printf("successful.\n");
}
// Set up the parameters for the GPU kernel:
funcParams.res = gpu_res;
funcParams.arg = gpu_arg;
funcParams.n = N;
printf("Launching kernel on GPU...\n");
// Launch the GPU kernel...
// Key code:
// KernelFunction<<<dimGrid, dimBlock>>>(args);
cos_main<<<1,COS_THREAD_CNT>>>(funcParams);
printf("GPU computations finished. Copying result back to CPU...\n");
// Copy the vector cos(0),cos(1),...,cos(N-1) from gpu_res (on the device) to res (on the host)
cudaStat = cudaMemcpy(res, gpu_res, N*sizeof(gpu_res[0]), cudaMemcpyDeviceToHost);
if (cudaStat){
printf(" Memory Copy from Device to Host failed.\n");
} else {
printf("Copy back successful. Printing result...\n");
}
if (PRINT_RESULT){
// Print the result?
for(i=0; i < N; i++ ){
if (i%print_every == 0 ){
printf("cos(%f) = %f\n", arg[i], res[i] );
}
}
}
printf("Freeing memory...\n");
free(arg);
free(res);
cudaFree(gpu_arg);
cudaFree(gpu_res);
printf("\n\nFinished. :)\n\n");
return 0;
} | .file "tmpxft_000d8b16_00000000-6_CUDA_example_01.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z8cos_main9cosParamsR9cosParams
.type _Z35__device_stub__Z8cos_main9cosParamsR9cosParams, @function
_Z35__device_stub__Z8cos_main9cosParamsR9cosParams:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq %rdi, 64(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z8cos_main9cosParams(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z8cos_main9cosParamsR9cosParams, .-_Z35__device_stub__Z8cos_main9cosParamsR9cosParams
.globl _Z8cos_main9cosParams
.type _Z8cos_main9cosParams, @function
_Z8cos_main9cosParams:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq 16(%rsp), %rdi
call _Z35__device_stub__Z8cos_main9cosParamsR9cosParams
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8cos_main9cosParams, .-_Z8cos_main9cosParams
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "\nBeginning CUDA example code on the CPU...\n"
.align 8
.LC1:
.string "Getting some info about CUDA devices on your system...\n"
.align 8
.LC2:
.string "There is %d CUDA device on your system.\n"
.align 8
.LC3:
.string "There are %d CUDA devices on your system.\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "\nCUDA Device #%d\n"
.LC5:
.string "Name: %s\n"
.LC6:
.string "\n"
.section .rodata.str1.8
.align 8
.LC7:
.string "Allocating memory on the CPU... (n=%d)\n"
.align 8
.LC10:
.string "Allocating memory on the GPU... (n=%d)\n"
.align 8
.LC11:
.string " value = %d : Memory Allocation on GPU Device failed\n"
.align 8
.LC12:
.string "done. Allocating more memory on the GPU...\n"
.align 8
.LC13:
.string "done again. Copying stuff from host (CPU) to device (GPU)...\n"
.align 8
.LC14:
.string " Memory Copy from Host to Device failed.\n"
.section .rodata.str1.1
.LC15:
.string "successful.\n"
.LC16:
.string "Launching kernel on GPU...\n"
.section .rodata.str1.8
.align 8
.LC17:
.string "GPU computations finished. Copying result back to CPU...\n"
.align 8
.LC18:
.string " Memory Copy from Device to Host failed.\n"
.align 8
.LC19:
.string "Copy back successful. Printing result...\n"
.section .rodata.str1.1
.LC20:
.string "cos(%f) = %f\n"
.LC21:
.string "Freeing memory...\n"
.LC22:
.string "\n\nFinished. :)\n\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $1128, %rsp
.cfi_def_cfa_offset 1168
movq %fs:40, %rax
movq %rax, 1112(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 4(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 4(%rsp), %edx
cmpl $1, %edx
je .L35
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L15:
movl $0, %ebx
leaq .LC4(%rip), %r13
leaq 80(%rsp), %rbp
leaq .LC5(%rip), %r12
cmpl $0, 4(%rsp)
jle .L14
.L13:
movl %ebx, %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %rbp, %rdx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 4(%rsp)
jg .L13
.L14:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movl $1000000, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4000000, %edi
call malloc@PLT
movq %rax, %rbp
movl $4000000, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %eax
movss .LC8(%rip), %xmm2
movss .LC9(%rip), %xmm1
.L16:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss %xmm2, %xmm0
divss %xmm1, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $1000000, %rax
jne .L16
movl $1000000, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 16(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
testl %eax, %eax
je .L17
movl %eax, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L18:
leaq 8(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
testl %eax, %eax
je .L19
movl %eax, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L20:
movl $1, %ecx
movl $4000000, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
je .L21
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L22:
movq 8(%rsp), %rbx
movq 16(%rsp), %r13
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $512, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L23:
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $4000000, %edx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
je .L24
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L26:
movl $0, %ebx
leaq .LC20(%rip), %r13
jmp .L25
.L35:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L15
.L17:
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L18
.L19:
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L20
.L21:
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L22
.L36:
movq %r13, 48(%rsp)
movq %rbx, 56(%rsp)
movl $1000000, 64(%rsp)
leaq 48(%rsp), %rdi
call _Z35__device_stub__Z8cos_main9cosParamsR9cosParams
jmp .L23
.L24:
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L26
.L27:
addq $1, %rbx
cmpq $1000000, %rbx
je .L37
.L25:
movslq %ebx, %rax
imulq $351843721, %rax, %rax
sarq $45, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
imull $100000, %eax, %eax
cmpl %ebx, %eax
jne .L27
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
pxor %xmm1, %xmm1
cvtss2sd (%r12,%rbx,4), %xmm1
movq %r13, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
jmp .L27
.L37:
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 1112(%rsp), %rax
subq %fs:40, %rax
jne .L38
movl $0, %eax
addq $1128, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC23:
.string "_Z8cos_main9cosParams"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC23(%rip), %rdx
movq %rdx, %rcx
leaq _Z8cos_main9cosParams(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC8:
.long 1086918618
.align 4
.LC9:
.long 1232348160
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* Cuda Program for finding cos(0), cos(1*2*pi/N), ... , cos((N-1)*2*pi/N) */
// nvcc CUDA_example_01.cu -use_fast_math -o CUDA_example_01.out
/* --------------------------- header secton ----------------------------*/
#include<stdio.h>
#include<cuda.h>
#define PRINT_RESULT 1
#define COS_THREAD_CNT 512
#define N 1000000
#define TWO_PI 6.283185
/* --------------------------- target code ------------------------------*/
struct cosParams {
float *arg;
float *res;
int n;
};
// CUDA kernel:
__global__ void cos_main(struct cosParams params)
{
// Computes:
// res[threadIdx.x + 0*COS_THREAD_CNT] = cos(threadIdx.x + 0*COS_THREAD_CNT)
// res[threadIdx.x + 1*COS_THREAD_CNT] = cos(threadIdx.x + 1*COS_THREAD_CNT)
// res[threadIdx.x + 2*COS_THREAD_CNT] = cos(threadIdx.x + 2*COS_THREAD_CNT)
// ...etc...
//
// if COS_THREAD_CNT = 1, this computes all of the cosines in one go,
// otherwise, it spreads it out across threads...
//
// Choice of either:
//
// __cosf:
// Calculate the fast approximate cosine of the input argument x, measured in radians.
//
// cosf:
// Calculate the cosine of the input argument x (measured in radians).
int i;
for (i=threadIdx.x; i<params.n; i+=COS_THREAD_CNT){
// params.res[i] = __cosf(params.arg[i]);
params.res[i] = cosf(params.arg[i]);
}
return;
}
/* --------------------------- host code ------------------------------*/
int main (int argc, char *argv[])
{
printf("\nBeginning CUDA example code on the CPU...\n");
printf("Getting some info about CUDA devices on your system...\n");
int i, devCount;
cudaGetDeviceCount(&devCount);
if (devCount == 1){
printf("There is %d CUDA device on your system.\n", devCount);
} else {
printf("There are %d CUDA devices on your system.\n", devCount);
}
// Iterate through devices
for (i=0; i<devCount; i++)
{
// Get device properties
printf("\nCUDA Device #%d\n", i);
cudaDeviceProp devProp;
cudaGetDeviceProperties(&devProp, i);
printf("Name: %s\n", devProp.name);
}
printf("\n");
// Begin cosine code:
cudaError_t cudaStat;
float* gpu_res = 0;
float* gpu_arg = 0;
printf("Allocating memory on the CPU... (n=%d)\n",(int)N);
// Allocate the vector 1,...,N:
float *arg = (float *) malloc(N*sizeof(float));
// Allocate vector of length N to store the result:
float *res = (float *) malloc(N*sizeof(float));
int print_every = (int)((double)N/10.0);
struct cosParams funcParams;
// Populate arg with 1,...,N
for(i=0; i<N; i++){
arg[i] = (float)i*(float)TWO_PI/(float)N;
}
printf("Allocating memory on the GPU... (n=%d)\n",(int)N);
// Key function:
// cudaError_t cudaMalloc(void ** devPtr, size_t size);
// Allocate N floats on the GPU for the argument 0,1,...,N-1, and make gpu_arg a pointer to that memory:
// NOTE: sizeof(gpu_arg[0]) is equivalent to sizeof(float) here
cudaStat = cudaMalloc((void **)&gpu_arg, N*sizeof(gpu_arg[0]));
if (cudaStat){
printf(" value = %d : Memory Allocation on GPU Device failed\n", cudaStat);
} else {
printf("done. Allocating more memory on the GPU...\n");
}
// Allocate N floats on the GPU to store the result, and make gpu_res a pointer to that memory:
// NOTE: sizeof(gpu_res[0]) is equivalent to sizeof(float) here
cudaStat = cudaMalloc((void **)&gpu_res, N*sizeof(gpu_res[0]));
if (cudaStat){
printf(" value = %d : Memory Allocation on GPU Device failed\n", (int)cudaStat);
} else {
printf("done again. Copying stuff from host (CPU) to device (GPU)...\n");
}
// Key function:
// cudaError_t cudaMemcpy(void * dst, const void * src, size_t count, enum cudaMemcpyKind kind);
// Copy the vector 0,1,...,N-1 from arg (on the host) to gpu_arg (on the device)
// NOTE: sizeof(arg[0]) is equivalent to sizeof(float) here
cudaStat = cudaMemcpy(gpu_arg, arg, N*sizeof(arg[0]), cudaMemcpyHostToDevice);
if (cudaStat){
printf(" Memory Copy from Host to Device failed.\n");
} else {
printf("successful.\n");
}
// Set up the parameters for the GPU kernel:
funcParams.res = gpu_res;
funcParams.arg = gpu_arg;
funcParams.n = N;
printf("Launching kernel on GPU...\n");
// Launch the GPU kernel...
// Key code:
// KernelFunction<<<dimGrid, dimBlock>>>(args);
cos_main<<<1,COS_THREAD_CNT>>>(funcParams);
printf("GPU computations finished. Copying result back to CPU...\n");
// Copy the vector cos(0),cos(1),...,cos(N-1) from gpu_res (on the device) to res (on the host)
cudaStat = cudaMemcpy(res, gpu_res, N*sizeof(gpu_res[0]), cudaMemcpyDeviceToHost);
if (cudaStat){
printf(" Memory Copy from Device to Host failed.\n");
} else {
printf("Copy back successful. Printing result...\n");
}
if (PRINT_RESULT){
// Print the result?
for(i=0; i < N; i++ ){
if (i%print_every == 0 ){
printf("cos(%f) = %f\n", arg[i], res[i] );
}
}
}
printf("Freeing memory...\n");
free(arg);
free(res);
cudaFree(gpu_arg);
cudaFree(gpu_res);
printf("\n\nFinished. :)\n\n");
return 0;
} | /* Cuda Program for finding cos(0), cos(1*2*pi/N), ... , cos((N-1)*2*pi/N) */
// nvcc CUDA_example_01.cu -use_fast_math -o CUDA_example_01.out
/* --------------------------- header secton ----------------------------*/
#include<stdio.h>
#include<hip/hip_runtime.h>
#define PRINT_RESULT 1
#define COS_THREAD_CNT 512
#define N 1000000
#define TWO_PI 6.283185
/* --------------------------- target code ------------------------------*/
struct cosParams {
float *arg;
float *res;
int n;
};
// CUDA kernel:
__global__ void cos_main(struct cosParams params)
{
// Computes:
// res[threadIdx.x + 0*COS_THREAD_CNT] = cos(threadIdx.x + 0*COS_THREAD_CNT)
// res[threadIdx.x + 1*COS_THREAD_CNT] = cos(threadIdx.x + 1*COS_THREAD_CNT)
// res[threadIdx.x + 2*COS_THREAD_CNT] = cos(threadIdx.x + 2*COS_THREAD_CNT)
// ...etc...
//
// if COS_THREAD_CNT = 1, this computes all of the cosines in one go,
// otherwise, it spreads it out across threads...
//
// Choice of either:
//
// __cosf:
// Calculate the fast approximate cosine of the input argument x, measured in radians.
//
// cosf:
// Calculate the cosine of the input argument x (measured in radians).
int i;
for (i=threadIdx.x; i<params.n; i+=COS_THREAD_CNT){
// params.res[i] = __cosf(params.arg[i]);
params.res[i] = cosf(params.arg[i]);
}
return;
}
/* --------------------------- host code ------------------------------*/
int main (int argc, char *argv[])
{
printf("\nBeginning CUDA example code on the CPU...\n");
printf("Getting some info about CUDA devices on your system...\n");
int i, devCount;
hipGetDeviceCount(&devCount);
if (devCount == 1){
printf("There is %d CUDA device on your system.\n", devCount);
} else {
printf("There are %d CUDA devices on your system.\n", devCount);
}
// Iterate through devices
for (i=0; i<devCount; i++)
{
// Get device properties
printf("\nCUDA Device #%d\n", i);
hipDeviceProp_t devProp;
hipGetDeviceProperties(&devProp, i);
printf("Name: %s\n", devProp.name);
}
printf("\n");
// Begin cosine code:
hipError_t cudaStat;
float* gpu_res = 0;
float* gpu_arg = 0;
printf("Allocating memory on the CPU... (n=%d)\n",(int)N);
// Allocate the vector 1,...,N:
float *arg = (float *) malloc(N*sizeof(float));
// Allocate vector of length N to store the result:
float *res = (float *) malloc(N*sizeof(float));
int print_every = (int)((double)N/10.0);
struct cosParams funcParams;
// Populate arg with 1,...,N
for(i=0; i<N; i++){
arg[i] = (float)i*(float)TWO_PI/(float)N;
}
printf("Allocating memory on the GPU... (n=%d)\n",(int)N);
// Key function:
// cudaError_t cudaMalloc(void ** devPtr, size_t size);
// Allocate N floats on the GPU for the argument 0,1,...,N-1, and make gpu_arg a pointer to that memory:
// NOTE: sizeof(gpu_arg[0]) is equivalent to sizeof(float) here
cudaStat = hipMalloc((void **)&gpu_arg, N*sizeof(gpu_arg[0]));
if (cudaStat){
printf(" value = %d : Memory Allocation on GPU Device failed\n", cudaStat);
} else {
printf("done. Allocating more memory on the GPU...\n");
}
// Allocate N floats on the GPU to store the result, and make gpu_res a pointer to that memory:
// NOTE: sizeof(gpu_res[0]) is equivalent to sizeof(float) here
cudaStat = hipMalloc((void **)&gpu_res, N*sizeof(gpu_res[0]));
if (cudaStat){
printf(" value = %d : Memory Allocation on GPU Device failed\n", (int)cudaStat);
} else {
printf("done again. Copying stuff from host (CPU) to device (GPU)...\n");
}
// Key function:
// cudaError_t cudaMemcpy(void * dst, const void * src, size_t count, enum cudaMemcpyKind kind);
// Copy the vector 0,1,...,N-1 from arg (on the host) to gpu_arg (on the device)
// NOTE: sizeof(arg[0]) is equivalent to sizeof(float) here
cudaStat = hipMemcpy(gpu_arg, arg, N*sizeof(arg[0]), hipMemcpyHostToDevice);
if (cudaStat){
printf(" Memory Copy from Host to Device failed.\n");
} else {
printf("successful.\n");
}
// Set up the parameters for the GPU kernel:
funcParams.res = gpu_res;
funcParams.arg = gpu_arg;
funcParams.n = N;
printf("Launching kernel on GPU...\n");
// Launch the GPU kernel...
// Key code:
// KernelFunction<<<dimGrid, dimBlock>>>(args);
cos_main<<<1,COS_THREAD_CNT>>>(funcParams);
printf("GPU computations finished. Copying result back to CPU...\n");
// Copy the vector cos(0),cos(1),...,cos(N-1) from gpu_res (on the device) to res (on the host)
cudaStat = hipMemcpy(res, gpu_res, N*sizeof(gpu_res[0]), hipMemcpyDeviceToHost);
if (cudaStat){
printf(" Memory Copy from Device to Host failed.\n");
} else {
printf("Copy back successful. Printing result...\n");
}
if (PRINT_RESULT){
// Print the result?
for(i=0; i < N; i++ ){
if (i%print_every == 0 ){
printf("cos(%f) = %f\n", arg[i], res[i] );
}
}
}
printf("Freeing memory...\n");
free(arg);
free(res);
hipFree(gpu_arg);
hipFree(gpu_res);
printf("\n\nFinished. :)\n\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /* Cuda Program for finding cos(0), cos(1*2*pi/N), ... , cos((N-1)*2*pi/N) */
// nvcc CUDA_example_01.cu -use_fast_math -o CUDA_example_01.out
/* --------------------------- header secton ----------------------------*/
#include<stdio.h>
#include<hip/hip_runtime.h>
#define PRINT_RESULT 1
#define COS_THREAD_CNT 512
#define N 1000000
#define TWO_PI 6.283185
/* --------------------------- target code ------------------------------*/
struct cosParams {
float *arg;
float *res;
int n;
};
// CUDA kernel:
__global__ void cos_main(struct cosParams params)
{
// Computes:
// res[threadIdx.x + 0*COS_THREAD_CNT] = cos(threadIdx.x + 0*COS_THREAD_CNT)
// res[threadIdx.x + 1*COS_THREAD_CNT] = cos(threadIdx.x + 1*COS_THREAD_CNT)
// res[threadIdx.x + 2*COS_THREAD_CNT] = cos(threadIdx.x + 2*COS_THREAD_CNT)
// ...etc...
//
// if COS_THREAD_CNT = 1, this computes all of the cosines in one go,
// otherwise, it spreads it out across threads...
//
// Choice of either:
//
// __cosf:
// Calculate the fast approximate cosine of the input argument x, measured in radians.
//
// cosf:
// Calculate the cosine of the input argument x (measured in radians).
int i;
for (i=threadIdx.x; i<params.n; i+=COS_THREAD_CNT){
// params.res[i] = __cosf(params.arg[i]);
params.res[i] = cosf(params.arg[i]);
}
return;
}
/* --------------------------- host code ------------------------------*/
int main (int argc, char *argv[])
{
printf("\nBeginning CUDA example code on the CPU...\n");
printf("Getting some info about CUDA devices on your system...\n");
int i, devCount;
hipGetDeviceCount(&devCount);
if (devCount == 1){
printf("There is %d CUDA device on your system.\n", devCount);
} else {
printf("There are %d CUDA devices on your system.\n", devCount);
}
// Iterate through devices
for (i=0; i<devCount; i++)
{
// Get device properties
printf("\nCUDA Device #%d\n", i);
hipDeviceProp_t devProp;
hipGetDeviceProperties(&devProp, i);
printf("Name: %s\n", devProp.name);
}
printf("\n");
// Begin cosine code:
hipError_t cudaStat;
float* gpu_res = 0;
float* gpu_arg = 0;
printf("Allocating memory on the CPU... (n=%d)\n",(int)N);
// Allocate the vector 1,...,N:
float *arg = (float *) malloc(N*sizeof(float));
// Allocate vector of length N to store the result:
float *res = (float *) malloc(N*sizeof(float));
int print_every = (int)((double)N/10.0);
struct cosParams funcParams;
// Populate arg with 1,...,N
for(i=0; i<N; i++){
arg[i] = (float)i*(float)TWO_PI/(float)N;
}
printf("Allocating memory on the GPU... (n=%d)\n",(int)N);
// Key function:
// cudaError_t cudaMalloc(void ** devPtr, size_t size);
// Allocate N floats on the GPU for the argument 0,1,...,N-1, and make gpu_arg a pointer to that memory:
// NOTE: sizeof(gpu_arg[0]) is equivalent to sizeof(float) here
cudaStat = hipMalloc((void **)&gpu_arg, N*sizeof(gpu_arg[0]));
if (cudaStat){
printf(" value = %d : Memory Allocation on GPU Device failed\n", cudaStat);
} else {
printf("done. Allocating more memory on the GPU...\n");
}
// Allocate N floats on the GPU to store the result, and make gpu_res a pointer to that memory:
// NOTE: sizeof(gpu_res[0]) is equivalent to sizeof(float) here
cudaStat = hipMalloc((void **)&gpu_res, N*sizeof(gpu_res[0]));
if (cudaStat){
printf(" value = %d : Memory Allocation on GPU Device failed\n", (int)cudaStat);
} else {
printf("done again. Copying stuff from host (CPU) to device (GPU)...\n");
}
// Key function:
// cudaError_t cudaMemcpy(void * dst, const void * src, size_t count, enum cudaMemcpyKind kind);
// Copy the vector 0,1,...,N-1 from arg (on the host) to gpu_arg (on the device)
// NOTE: sizeof(arg[0]) is equivalent to sizeof(float) here
cudaStat = hipMemcpy(gpu_arg, arg, N*sizeof(arg[0]), hipMemcpyHostToDevice);
if (cudaStat){
printf(" Memory Copy from Host to Device failed.\n");
} else {
printf("successful.\n");
}
// Set up the parameters for the GPU kernel:
funcParams.res = gpu_res;
funcParams.arg = gpu_arg;
funcParams.n = N;
printf("Launching kernel on GPU...\n");
// Launch the GPU kernel...
// Key code:
// KernelFunction<<<dimGrid, dimBlock>>>(args);
cos_main<<<1,COS_THREAD_CNT>>>(funcParams);
printf("GPU computations finished. Copying result back to CPU...\n");
// Copy the vector cos(0),cos(1),...,cos(N-1) from gpu_res (on the device) to res (on the host)
cudaStat = hipMemcpy(res, gpu_res, N*sizeof(gpu_res[0]), hipMemcpyDeviceToHost);
if (cudaStat){
printf(" Memory Copy from Device to Host failed.\n");
} else {
printf("Copy back successful. Printing result...\n");
}
if (PRINT_RESULT){
// Print the result?
for(i=0; i < N; i++ ){
if (i%print_every == 0 ){
printf("cos(%f) = %f\n", arg[i], res[i] );
}
}
}
printf("Freeing memory...\n");
free(arg);
free(res);
hipFree(gpu_arg);
hipFree(gpu_res);
printf("\n\nFinished. :)\n\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8cos_main9cosParams
.globl _Z8cos_main9cosParams
.p2align 8
.type _Z8cos_main9cosParams,@function
_Z8cos_main9cosParams:
s_load_b32 s2, s[0:1], 0x10
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s2, v0
s_cbranch_execz .LBB0_7
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v3, 2, v0
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v1, s0, s4, v3
v_add_co_ci_u32_e64 v2, null, s5, 0, s0
v_add_co_u32 v3, s0, s6, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, null, s7, 0, s0
s_mov_b32 s4, 0x7fffff
s_mov_b32 s5, 0xb94c1982
s_mov_b32 s6, 0x37d75334
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_dual_mul_f32 v8, v6, v6 :: v_dual_and_b32 v11, 1, v7
v_add_nc_u32_e32 v0, 0x200, v0
v_lshlrev_b32_e32 v7, 30, v7
v_fmaak_f32 v9, s5, v8, 0x3c0881c4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_u32_e32 vcc_lo, 0, v11
v_and_b32_e32 v7, 0x80000000, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v9, v8, v9, 0xbe2aaa9d
v_dual_fmaak_f32 v10, s6, v8, 0xbab64f3b :: v_dual_mul_f32 v9, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmaak_f32 v10, v8, v10, 0x3d2aabf7
v_fmac_f32_e32 v6, v6, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v10, v8, v10, 0xbf000004
v_fma_f32 v8, v8, v10, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v6, -v6, v8, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v5, 0x1f8
v_xor_b32_e32 v6, v7, v6
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e32 v5, 0x7fc00000, v6, vcc_lo
v_add_co_u32 v1, vcc_lo, v1, 0x800
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s2, v0
global_store_b32 v[3:4], v5, off
v_add_co_u32 v3, s0, v3, 0x800
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v4, s0, 0, v4, s0
s_or_b32 s3, vcc_lo, s3
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execz .LBB0_7
.LBB0_3:
global_load_b32 v5, v[1:2], off
s_mov_b32 s1, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_ngt_f32_e64 0x48000000, |v5|
s_xor_b32 s7, exec_lo, s1
s_cbranch_execz .LBB0_5
v_dual_mov_b32 v8, 0 :: v_dual_and_b32 v13, 0x7fffffff, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_and_or_b32 v16, v13, s4, 0x800000
v_lshrrev_b32_e32 v13, 23, v13
v_mad_u64_u32 v[6:7], null, v16, 0xfe5163ab, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v14, 0xffffff88, v13
v_cmp_lt_u32_e32 vcc_lo, 63, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[9:10], null, v16, 0x3c439041, v[7:8]
v_cndmask_b32_e64 v15, 0, 0xffffffc0, vcc_lo
v_mov_b32_e32 v7, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v15, v15, v14
v_mad_u64_u32 v[10:11], null, v16, 0xdb629599, v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_u32_e64 s0, 31, v15
v_cndmask_b32_e64 v17, 0, 0xffffffe0, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mov_b32 v7, v11 :: v_dual_cndmask_b32 v6, v10, v6
v_add_nc_u32_e32 v17, v17, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[11:12], null, v16, 0xf534ddc0, v[7:8]
v_cmp_lt_u32_e64 s1, 31, v17
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mov_b32_e32 v7, v12
v_cndmask_b32_e32 v9, v11, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[12:13], null, v16, 0xfc2757d1, v[7:8]
v_cndmask_b32_e64 v6, v9, v6, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v7, v13
v_mad_u64_u32 v[13:14], null, v16, 0x4e441529, v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v7, v14
v_mad_u64_u32 v[14:15], null, v16, 0xa2f9836e, v[7:8]
v_cndmask_b32_e64 v7, 0, 0xffffffe0, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v8, v13, v11 :: v_dual_add_nc_u32 v7, v7, v17
v_dual_cndmask_b32 v14, v14, v12 :: v_dual_cndmask_b32 v13, v15, v13
v_cndmask_b32_e32 v12, v12, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_u32_e32 vcc_lo, 0, v7
v_cndmask_b32_e64 v11, v14, v8, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v13, v13, v14, s0
v_cndmask_b32_e64 v8, v8, v12, s0
v_sub_nc_u32_e32 v14, 32, v7
v_cndmask_b32_e64 v12, v12, v9, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v13, v13, v11, s1
v_cndmask_b32_e64 v11, v11, v8, s1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v8, v8, v12, s1
v_cndmask_b32_e64 v6, v12, v6, s1
v_alignbit_b32 v15, v13, v11, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_alignbit_b32 v10, v11, v8, v14
v_cndmask_b32_e32 v7, v15, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v13, v8, v6, v14
v_cndmask_b32_e32 v9, v10, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_bfe_u32 v10, v7, 29, 1
v_cndmask_b32_e32 v8, v13, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v11, v7, v9, 30
v_sub_nc_u32_e32 v12, 0, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_alignbit_b32 v9, v9, v8, 30
v_alignbit_b32 v6, v8, v6, 30
v_xor_b32_e32 v11, v11, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v8, v9, v12
v_xor_b32_e32 v6, v6, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_clz_i32_u32_e32 v13, v11
v_min_u32_e32 v13, 32, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v9, 31, v13
v_lshlrev_b32_e32 v15, 23, v13
v_alignbit_b32 v11, v11, v8, v9
v_alignbit_b32 v6, v8, v6, v9
v_lshrrev_b32_e32 v9, 29, v7
v_lshrrev_b32_e32 v7, 30, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v8, v11, v6, 9
v_lshlrev_b32_e32 v9, 31, v9
v_lshrrev_b32_e32 v11, 9, v11
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v7, v10, v7
v_clz_i32_u32_e32 v12, v8
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v14, 0.5, v9
v_min_u32_e32 v12, 32, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v14, v14, v15
v_sub_nc_u32_e32 v16, 31, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v6, v8, v6, v16
v_or_b32_e32 v8, v11, v14
v_add_lshl_u32 v11, v12, v13, 23
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshrrev_b32_e32 v6, 9, v6
v_mul_f32_e32 v12, 0x3fc90fda, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v6, v6, v11
v_fma_f32 v11, v8, 0x3fc90fda, -v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v6, 0x33000000, v6
v_fmac_f32_e32 v11, 0x33a22168, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v6, v6, v9
v_fmac_f32_e32 v11, 0x3fc90fda, v6
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v6, v12, v11
.LBB0_5:
s_and_not1_saveexec_b32 s0, s7
s_cbranch_execz .LBB0_2
v_mul_f32_e64 v6, 0x3f22f983, |v5|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v7, v6
v_fma_f32 v6, v7, 0xbfc90fda, |v5|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, 0xb3a22168, v7
v_fmac_f32_e32 v6, 0xa7c234c4, v7
v_cvt_i32_f32_e32 v7, v7
s_branch .LBB0_2
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8cos_main9cosParams
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8cos_main9cosParams, .Lfunc_end0-_Z8cos_main9cosParams
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 24
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8cos_main9cosParams
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z8cos_main9cosParams.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* Cuda Program for finding cos(0), cos(1*2*pi/N), ... , cos((N-1)*2*pi/N) */
// nvcc CUDA_example_01.cu -use_fast_math -o CUDA_example_01.out
/* --------------------------- header secton ----------------------------*/
#include<stdio.h>
#include<hip/hip_runtime.h>
#define PRINT_RESULT 1
#define COS_THREAD_CNT 512
#define N 1000000
#define TWO_PI 6.283185
/* --------------------------- target code ------------------------------*/
struct cosParams {
float *arg;
float *res;
int n;
};
// CUDA kernel:
__global__ void cos_main(struct cosParams params)
{
// Computes:
// res[threadIdx.x + 0*COS_THREAD_CNT] = cos(threadIdx.x + 0*COS_THREAD_CNT)
// res[threadIdx.x + 1*COS_THREAD_CNT] = cos(threadIdx.x + 1*COS_THREAD_CNT)
// res[threadIdx.x + 2*COS_THREAD_CNT] = cos(threadIdx.x + 2*COS_THREAD_CNT)
// ...etc...
//
// if COS_THREAD_CNT = 1, this computes all of the cosines in one go,
// otherwise, it spreads it out across threads...
//
// Choice of either:
//
// __cosf:
// Calculate the fast approximate cosine of the input argument x, measured in radians.
//
// cosf:
// Calculate the cosine of the input argument x (measured in radians).
int i;
for (i=threadIdx.x; i<params.n; i+=COS_THREAD_CNT){
// params.res[i] = __cosf(params.arg[i]);
params.res[i] = cosf(params.arg[i]);
}
return;
}
/* --------------------------- host code ------------------------------*/
int main (int argc, char *argv[])
{
printf("\nBeginning CUDA example code on the CPU...\n");
printf("Getting some info about CUDA devices on your system...\n");
int i, devCount;
hipGetDeviceCount(&devCount);
if (devCount == 1){
printf("There is %d CUDA device on your system.\n", devCount);
} else {
printf("There are %d CUDA devices on your system.\n", devCount);
}
// Iterate through devices
for (i=0; i<devCount; i++)
{
// Get device properties
printf("\nCUDA Device #%d\n", i);
hipDeviceProp_t devProp;
hipGetDeviceProperties(&devProp, i);
printf("Name: %s\n", devProp.name);
}
printf("\n");
// Begin cosine code:
hipError_t cudaStat;
float* gpu_res = 0;
float* gpu_arg = 0;
printf("Allocating memory on the CPU... (n=%d)\n",(int)N);
// Allocate the vector 1,...,N:
float *arg = (float *) malloc(N*sizeof(float));
// Allocate vector of length N to store the result:
float *res = (float *) malloc(N*sizeof(float));
int print_every = (int)((double)N/10.0);
struct cosParams funcParams;
// Populate arg with 1,...,N
for(i=0; i<N; i++){
arg[i] = (float)i*(float)TWO_PI/(float)N;
}
printf("Allocating memory on the GPU... (n=%d)\n",(int)N);
// Key function:
// cudaError_t cudaMalloc(void ** devPtr, size_t size);
// Allocate N floats on the GPU for the argument 0,1,...,N-1, and make gpu_arg a pointer to that memory:
// NOTE: sizeof(gpu_arg[0]) is equivalent to sizeof(float) here
cudaStat = hipMalloc((void **)&gpu_arg, N*sizeof(gpu_arg[0]));
if (cudaStat){
printf(" value = %d : Memory Allocation on GPU Device failed\n", cudaStat);
} else {
printf("done. Allocating more memory on the GPU...\n");
}
// Allocate N floats on the GPU to store the result, and make gpu_res a pointer to that memory:
// NOTE: sizeof(gpu_res[0]) is equivalent to sizeof(float) here
cudaStat = hipMalloc((void **)&gpu_res, N*sizeof(gpu_res[0]));
if (cudaStat){
printf(" value = %d : Memory Allocation on GPU Device failed\n", (int)cudaStat);
} else {
printf("done again. Copying stuff from host (CPU) to device (GPU)...\n");
}
// Key function:
// cudaError_t cudaMemcpy(void * dst, const void * src, size_t count, enum cudaMemcpyKind kind);
// Copy the vector 0,1,...,N-1 from arg (on the host) to gpu_arg (on the device)
// NOTE: sizeof(arg[0]) is equivalent to sizeof(float) here
cudaStat = hipMemcpy(gpu_arg, arg, N*sizeof(arg[0]), hipMemcpyHostToDevice);
if (cudaStat){
printf(" Memory Copy from Host to Device failed.\n");
} else {
printf("successful.\n");
}
// Set up the parameters for the GPU kernel:
funcParams.res = gpu_res;
funcParams.arg = gpu_arg;
funcParams.n = N;
printf("Launching kernel on GPU...\n");
// Launch the GPU kernel...
// Key code:
// KernelFunction<<<dimGrid, dimBlock>>>(args);
cos_main<<<1,COS_THREAD_CNT>>>(funcParams);
printf("GPU computations finished. Copying result back to CPU...\n");
// Copy the vector cos(0),cos(1),...,cos(N-1) from gpu_res (on the device) to res (on the host)
cudaStat = hipMemcpy(res, gpu_res, N*sizeof(gpu_res[0]), hipMemcpyDeviceToHost);
if (cudaStat){
printf(" Memory Copy from Device to Host failed.\n");
} else {
printf("Copy back successful. Printing result...\n");
}
if (PRINT_RESULT){
// Print the result?
for(i=0; i < N; i++ ){
if (i%print_every == 0 ){
printf("cos(%f) = %f\n", arg[i], res[i] );
}
}
}
printf("Freeing memory...\n");
free(arg);
free(res);
hipFree(gpu_arg);
hipFree(gpu_res);
printf("\n\nFinished. :)\n\n");
return 0;
} | .text
.file "CUDA_example_01.hip"
.globl _Z23__device_stub__cos_main9cosParams # -- Begin function _Z23__device_stub__cos_main9cosParams
.p2align 4, 0x90
.type _Z23__device_stub__cos_main9cosParams,@function
_Z23__device_stub__cos_main9cosParams: # @_Z23__device_stub__cos_main9cosParams
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movq %rsp, %r9
movl $_Z8cos_main9cosParams, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z23__device_stub__cos_main9cosParams, .Lfunc_end0-_Z23__device_stub__cos_main9cosParams
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x40c90fda # float 6.283185
.LCPI1_1:
.long 0x49742400 # float 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1560, %rsp # imm = 0x618
.cfi_def_cfa_offset 1616
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.Lstr, %edi
callq puts@PLT
movl $.Lstr.1, %edi
callq puts@PLT
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
movl 12(%rsp), %esi
cmpl $1, %esi
jne .LBB1_2
# %bb.1:
movl $.L.str.2, %edi
movl $1, %esi
jmp .LBB1_3
.LBB1_2:
movl $.L.str.3, %edi
.LBB1_3:
xorl %eax, %eax
callq printf
cmpl $0, 12(%rsp)
jle .LBB1_6
# %bb.4: # %.lr.ph.preheader
leaq 88(%rsp), %rbx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_5: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.4, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.5, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
incl %ebp
cmpl 12(%rsp), %ebp
jl .LBB1_5
.LBB1_6: # %._crit_edge
movl $10, %edi
callq putchar@PLT
movq $0, 24(%rsp)
movq $0, 16(%rsp)
xorl %r15d, %r15d
movl $.L.str.7, %edi
movl $1000000, %esi # imm = 0xF4240
xorl %eax, %eax
callq printf
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %rbx
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %r14
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
xorps %xmm2, %xmm2
cvtsi2ss %r15d, %xmm2
mulss %xmm0, %xmm2
divss %xmm1, %xmm2
movss %xmm2, (%rbx,%r15,4)
incq %r15
cmpq $1000000, %r15 # imm = 0xF4240
jne .LBB1_7
# %bb.8:
movl $.L.str.8, %edi
movl $1000000, %esi # imm = 0xF4240
xorl %eax, %eax
callq printf
leaq 16(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
testl %eax, %eax
je .LBB1_10
# %bb.9:
movl $.L.str.9, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
jmp .LBB1_11
.LBB1_10:
movl $.Lstr.2, %edi
callq puts@PLT
.LBB1_11:
leaq 24(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
testl %eax, %eax
je .LBB1_13
# %bb.12:
movl $.L.str.9, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
jmp .LBB1_14
.LBB1_13:
movl $.Lstr.3, %edi
callq puts@PLT
.LBB1_14:
movq 16(%rsp), %rdi
movl $4000000, %edx # imm = 0x3D0900
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
movl $.Lstr.4, %eax
movl $.Lstr.5, %edi
cmoveq %rax, %rdi
callq puts@PLT
movq 24(%rsp), %r12
movq 16(%rsp), %r13
movl $.Lstr.6, %edi
callq puts@PLT
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 511(%rdi), %rdx
xorl %r15d, %r15d
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_16
# %bb.15:
movq %r13, 88(%rsp)
movq %r12, 96(%rsp)
movl $1000000, 104(%rsp) # imm = 0xF4240
leaq 88(%rsp), %rax
movq %rax, 32(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z8cos_main9cosParams, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_16:
movl $.Lstr.7, %edi
callq puts@PLT
movq 24(%rsp), %rsi
movl $4000000, %edx # imm = 0x3D0900
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
movl $.Lstr.8, %eax
movl $.Lstr.9, %edi
cmoveq %rax, %rdi
callq puts@PLT
xorl %r12d, %r12d
jmp .LBB1_17
.p2align 4, 0x90
.LBB1_19: # in Loop: Header=BB1_17 Depth=1
incq %r12
decl %r15d
cmpq $1000000, %r12 # imm = 0xF4240
je .LBB1_20
.LBB1_17: # =>This Inner Loop Header: Depth=1
movl %r12d, %eax
shrl $5, %eax
imulq $175921861, %rax, %rax # imm = 0xA7C5AC5
shrq $39, %rax
imull $100000, %eax, %eax # imm = 0x186A0
addl %r15d, %eax
jne .LBB1_19
# %bb.18: # in Loop: Header=BB1_17 Depth=1
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss (%r14,%r12,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movl $.L.str.18, %edi
movb $2, %al
callq printf
jmp .LBB1_19
.LBB1_20:
movl $.Lstr.10, %edi
callq puts@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movl $.Lstr.11, %edi
callq puts@PLT
xorl %eax, %eax
addq $1560, %rsp # imm = 0x618
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8cos_main9cosParams, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8cos_main9cosParams,@object # @_Z8cos_main9cosParams
.section .rodata,"a",@progbits
.globl _Z8cos_main9cosParams
.p2align 3, 0x0
_Z8cos_main9cosParams:
.quad _Z23__device_stub__cos_main9cosParams
.size _Z8cos_main9cosParams, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "There is %d CUDA device on your system.\n"
.size .L.str.2, 41
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "There are %d CUDA devices on your system.\n"
.size .L.str.3, 43
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\nCUDA Device #%d\n"
.size .L.str.4, 18
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Name: %s\n"
.size .L.str.5, 11
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Allocating memory on the CPU... (n=%d)\n"
.size .L.str.7, 40
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Allocating memory on the GPU... (n=%d)\n"
.size .L.str.8, 40
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz " value = %d : Memory Allocation on GPU Device failed\n"
.size .L.str.9, 54
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "cos(%f) = %f\n"
.size .L.str.18, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8cos_main9cosParams"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nBeginning CUDA example code on the CPU..."
.size .Lstr, 43
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Getting some info about CUDA devices on your system..."
.size .Lstr.1, 55
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "done. Allocating more memory on the GPU..."
.size .Lstr.2, 43
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "done again. Copying stuff from host (CPU) to device (GPU)..."
.size .Lstr.3, 61
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "successful."
.size .Lstr.4, 12
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz " Memory Copy from Host to Device failed."
.size .Lstr.5, 41
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "Launching kernel on GPU..."
.size .Lstr.6, 27
.type .Lstr.7,@object # @str.7
.Lstr.7:
.asciz "GPU computations finished. Copying result back to CPU..."
.size .Lstr.7, 57
.type .Lstr.8,@object # @str.8
.Lstr.8:
.asciz "Copy back successful. Printing result..."
.size .Lstr.8, 41
.type .Lstr.9,@object # @str.9
.Lstr.9:
.asciz " Memory Copy from Device to Host failed."
.size .Lstr.9, 41
.type .Lstr.10,@object # @str.10
.Lstr.10:
.asciz "Freeing memory..."
.size .Lstr.10, 18
.type .Lstr.11,@object # @str.11
.Lstr.11:
.asciz "\n\nFinished. :)\n"
.size .Lstr.11, 16
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__cos_main9cosParams
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8cos_main9cosParams
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8cos_main9cosParams
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0050*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fc800078e00ff */
/*0060*/ IMAD.WIDE R6, R0, R7, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fca00078e0207 */
/*0070*/ LDG.E R3, [R6.64] ; /* 0x0000000606037981 */
/* 0x001ea2000c1e1900 */
/*0080*/ BSSY B0, 0x7f0 ; /* 0x0000076000007945 */
/* 0x000fe20003800000 */
/*0090*/ FMUL R4, R3.reuse, 0.63661974668502807617 ; /* 0x3f22f98303047820 */
/* 0x044fe20000400000 */
/*00a0*/ FSETP.GE.AND P0, PT, |R3|, 105615, PT ; /* 0x47ce47800300780b */
/* 0x000fca0003f06200 */
/*00b0*/ F2I.NTZ R4, R4 ; /* 0x0000000400047305 */
/* 0x000e300000203100 */
/*00c0*/ I2F R8, R4 ; /* 0x0000000400087306 */
/* 0x001e240000201400 */
/*00d0*/ FFMA R5, R8, -1.5707962512969970703, R3 ; /* 0xbfc90fda08057823 */
/* 0x001fc80000000003 */
/*00e0*/ FFMA R9, R8, -7.5497894158615963534e-08, R5 ; /* 0xb3a2216808097823 */
/* 0x000fe20000000005 */
/*00f0*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x000fc60000011400 */
/*0100*/ FFMA R17, R8, -5.3903029534742383927e-15, R9 ; /* 0xa7c234c508117823 */
/* 0x000fe20000000009 */
/*0110*/ @!P0 BRA 0x7e0 ; /* 0x000006c000008947 */
/* 0x000fea0003800000 */
/*0120*/ FSETP.NEU.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fda0003f0d200 */
/*0130*/ @!P0 BRA 0x7c0 ; /* 0x0000068000008947 */
/* 0x000fea0003800000 */
/*0140*/ SHF.R.U32.HI R4, RZ, 0x17, R3 ; /* 0x00000017ff047819 */
/* 0x000fe20000011603 */
/*0150*/ IMAD.SHL.U32 R7, R3, 0x100, RZ ; /* 0x0000010003077824 */
/* 0x000fe200078e00ff */
/*0160*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0170*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e00ff */
/*0180*/ LOP3.LUT R6, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04067812 */
/* 0x000fe200078ec0ff */
/*0190*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*01a0*/ LOP3.LUT R17, R7, 0x80000000, RZ, 0xfc, !PT ; /* 0x8000000007117812 */
/* 0x000fe200078efcff */
/*01b0*/ IMAD.MOV.U32 R19, RZ, RZ, RZ ; /* 0x000000ffff137224 */
/* 0x000fe200078e00ff */
/*01c0*/ IADD3 R11, R6, -0x80, RZ ; /* 0xffffff80060b7810 */
/* 0x000fe20007ffe0ff */
/*01d0*/ ULDC.64 UR8, c[0x4][0x0] ; /* 0x0100000000087ab9 */
/* 0x000fc60000000a00 */
/*01e0*/ SHF.R.U32.HI R18, RZ, 0x5, R11 ; /* 0x00000005ff127819 */
/* 0x000fe4000001160b */
/*01f0*/ IMAD.U32 R8, RZ, RZ, UR8 ; /* 0x00000008ff087e24 */
/* 0x000fe4000f8e00ff */
/*0200*/ IMAD.U32 R9, RZ, RZ, UR9 ; /* 0x00000009ff097e24 */
/* 0x000fca000f8e00ff */
/*0210*/ LDG.E.CONSTANT R6, [R8.64] ; /* 0x0000000608067981 */
/* 0x000ea2000c1e9900 */
/*0220*/ IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a7810 */
/* 0x000fe20007ffe0ff */
/*0230*/ UIADD3 UR8, UP0, UR8, 0x4, URZ ; /* 0x0000000408087890 */
/* 0x000fe2000ff1e03f */
/*0240*/ ISETP.EQ.AND P0, PT, R19.reuse, RZ, PT ; /* 0x000000ff1300720c */
/* 0x040fe40003f02270 */
/*0250*/ ISETP.EQ.AND P5, PT, R19.reuse, 0x4, PT ; /* 0x000000041300780c */
/* 0x040fe20003fa2270 */
/*0260*/ UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; /* 0x000000093f097290 */
/* 0x000fe200087fe43f */
/*0270*/ ISETP.EQ.AND P4, PT, R19.reuse, 0x8, PT ; /* 0x000000081300780c */
/* 0x040fe40003f82270 */
/*0280*/ ISETP.EQ.AND P3, PT, R19.reuse, 0xc, PT ; /* 0x0000000c1300780c */
/* 0x040fe40003f62270 */
/*0290*/ ISETP.EQ.AND P2, PT, R19, 0x10, PT ; /* 0x000000101300780c */
/* 0x000fc40003f42270 */
/*02a0*/ ISETP.EQ.AND P1, PT, R19.reuse, 0x14, PT ; /* 0x000000141300780c */
/* 0x040fe40003f22270 */
/*02b0*/ IADD3 R19, R19, 0x4, RZ ; /* 0x0000000413137810 */
/* 0x000fe20007ffe0ff */
/*02c0*/ IMAD.WIDE.U32 R6, R6, R17, RZ ; /* 0x0000001106067225 */
/* 0x004fca00078e00ff */
/*02d0*/ IADD3 R6, P6, R6, R4, RZ ; /* 0x0000000406067210 */
/* 0x000fc80007fde0ff */
/*02e0*/ IADD3.X R4, R7, UR4, RZ, P6, !PT ; /* 0x0000000407047c10 */
/* 0x000fe2000b7fe4ff */
/*02f0*/ @P0 IMAD.MOV.U32 R2, RZ, RZ, R6.reuse ; /* 0x000000ffff020224 */
/* 0x100fe200078e0006 */
/*0300*/ ISETP.NE.AND P6, PT, R10, 0x6, PT ; /* 0x000000060a00780c */
/* 0x000fe20003fc5270 */
/*0310*/ @P5 IMAD.MOV.U32 R12, RZ, RZ, R6.reuse ; /* 0x000000ffff0c5224 */
/* 0x100fe400078e0006 */
/*0320*/ @P4 IMAD.MOV.U32 R13, RZ, RZ, R6.reuse ; /* 0x000000ffff0d4224 */
/* 0x100fe400078e0006 */
/*0330*/ @P3 IMAD.MOV.U32 R14, RZ, RZ, R6.reuse ; /* 0x000000ffff0e3224 */
/* 0x100fe400078e0006 */
/*0340*/ @P2 IMAD.MOV.U32 R15, RZ, RZ, R6.reuse ; /* 0x000000ffff0f2224 */
/* 0x100fe400078e0006 */
/*0350*/ @P1 IMAD.MOV.U32 R16, RZ, RZ, R6 ; /* 0x000000ffff101224 */
/* 0x000fc800078e0006 */
/*0360*/ @P6 BRA 0x1f0 ; /* 0xfffffe8000006947 */
/* 0x000fea000383ffff */
/*0370*/ IADD3 R6, -R18, 0x6, RZ ; /* 0x0000000612067810 */
/* 0x000fe20007ffe1ff */
/*0380*/ BSSY B1, 0x6b0 ; /* 0x0000032000017945 */
/* 0x000fe80003800000 */
/*0390*/ IMAD.SHL.U32 R6, R6, 0x4, RZ ; /* 0x0000000406067824 */
/* 0x000fca00078e00ff */
/*03a0*/ ISETP.EQ.AND P0, PT, R6.reuse, RZ, PT ; /* 0x000000ff0600720c */
/* 0x040fe40003f02270 */
/*03b0*/ ISETP.EQ.AND P3, PT, R6.reuse, 0x4, PT ; /* 0x000000040600780c */
/* 0x040fe40003f62270 */
/*03c0*/ ISETP.EQ.AND P4, PT, R6.reuse, 0x8, PT ; /* 0x000000080600780c */
/* 0x040fe40003f82270 */
/*03d0*/ ISETP.EQ.AND P2, PT, R6.reuse, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x040fe40003f42270 */
/*03e0*/ ISETP.EQ.AND P1, PT, R6, 0x10, PT ; /* 0x000000100600780c */
/* 0x000fca0003f22270 */
/*03f0*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, R2.reuse ; /* 0x000000ffff070224 */
/* 0x100fe200078e0002 */
/*0400*/ ISETP.EQ.AND P0, PT, R6.reuse, 0x14, PT ; /* 0x000000140600780c */
/* 0x040fe20003f02270 */
/*0410*/ @P3 IMAD.MOV.U32 R8, RZ, RZ, R2 ; /* 0x000000ffff083224 */
/* 0x000fe400078e0002 */
/*0420*/ @P3 IMAD.MOV.U32 R7, RZ, RZ, R12.reuse ; /* 0x000000ffff073224 */
/* 0x100fe200078e000c */
/*0430*/ ISETP.EQ.AND P3, PT, R6.reuse, 0x18, PT ; /* 0x000000180600780c */
/* 0x040fe20003f62270 */
/*0440*/ @P4 IMAD.MOV.U32 R8, RZ, RZ, R12 ; /* 0x000000ffff084224 */
/* 0x000fe400078e000c */
/*0450*/ @P4 IMAD.MOV.U32 R7, RZ, RZ, R13.reuse ; /* 0x000000ffff074224 */
/* 0x100fe200078e000d */
/*0460*/ ISETP.EQ.AND P4, PT, R6, 0x1c, PT ; /* 0x0000001c0600780c */
/* 0x000fe20003f82270 */
/*0470*/ @P2 IMAD.MOV.U32 R8, RZ, RZ, R13 ; /* 0x000000ffff082224 */
/* 0x000fc400078e000d */
/*0480*/ @P2 IMAD.MOV.U32 R7, RZ, RZ, R14.reuse ; /* 0x000000ffff072224 */
/* 0x100fe400078e000e */
/*0490*/ @P1 IMAD.MOV.U32 R8, RZ, RZ, R14 ; /* 0x000000ffff081224 */
/* 0x000fe400078e000e */
/*04a0*/ @P1 IMAD.MOV.U32 R7, RZ, RZ, R15.reuse ; /* 0x000000ffff071224 */
/* 0x100fe200078e000f */
/*04b0*/ LOP3.LUT P1, R11, R11, 0x1f, RZ, 0xc0, !PT ; /* 0x0000001f0b0b7812 */
/* 0x000fe2000782c0ff */
/*04c0*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, R16 ; /* 0x000000ffff070224 */
/* 0x000fe400078e0010 */
/*04d0*/ @P3 IMAD.MOV.U32 R7, RZ, RZ, R4 ; /* 0x000000ffff073224 */
/* 0x000fe400078e0004 */
/*04e0*/ @P0 IMAD.MOV.U32 R8, RZ, RZ, R15 ; /* 0x000000ffff080224 */
/* 0x000fc400078e000f */
/*04f0*/ @P3 IMAD.MOV.U32 R8, RZ, RZ, R16 ; /* 0x000000ffff083224 */
/* 0x000fe400078e0010 */
/*0500*/ @P4 IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff084224 */
/* 0x000fe400078e0004 */
/*0510*/ IMAD.MOV.U32 R6, RZ, RZ, R7 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0007 */
/*0520*/ @!P1 BRA 0x6a0 ; /* 0x0000017000009947 */
/* 0x000fea0003800000 */
/*0530*/ IADD3 R7, -R18, 0x4, RZ ; /* 0x0000000412077810 */
/* 0x000fe40007ffe1ff */
/*0540*/ SHF.L.U32 R9, R6, R11, RZ ; /* 0x0000000b06097219 */
/* 0x000fc600000006ff */
/*0550*/ IMAD.SHL.U32 R7, R7, 0x4, RZ ; /* 0x0000000407077824 */
/* 0x000fca00078e00ff */
/*0560*/ ISETP.EQ.AND P0, PT, R7.reuse, RZ, PT ; /* 0x000000ff0700720c */
/* 0x040fe40003f02270 */
/*0570*/ ISETP.EQ.AND P1, PT, R7.reuse, 0x4, PT ; /* 0x000000040700780c */
/* 0x040fe40003f22270 */
/*0580*/ ISETP.EQ.AND P2, PT, R7.reuse, 0x8, PT ; /* 0x000000080700780c */
/* 0x040fe40003f42270 */
/*0590*/ ISETP.EQ.AND P3, PT, R7, 0xc, PT ; /* 0x0000000c0700780c */
/* 0x000fce0003f62270 */
/*05a0*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, R2 ; /* 0x000000ffff0a0224 */
/* 0x000fe200078e0002 */
/*05b0*/ ISETP.EQ.AND P0, PT, R7.reuse, 0x10, PT ; /* 0x000000100700780c */
/* 0x040fe20003f02270 */
/*05c0*/ @P1 IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a1224 */
/* 0x000fe200078e000c */
/*05d0*/ ISETP.EQ.AND P1, PT, R7.reuse, 0x14, PT ; /* 0x000000140700780c */
/* 0x040fe20003f22270 */
/*05e0*/ @P2 IMAD.MOV.U32 R10, RZ, RZ, R13 ; /* 0x000000ffff0a2224 */
/* 0x000fe200078e000d */
/*05f0*/ ISETP.EQ.AND P2, PT, R7, 0x18, PT ; /* 0x000000180700780c */
/* 0x000fe20003f42270 */
/*0600*/ @P3 IMAD.MOV.U32 R10, RZ, RZ, R14 ; /* 0x000000ffff0a3224 */
/* 0x000fe200078e000e */
/*0610*/ IADD3 R7, -R11, 0x20, RZ ; /* 0x000000200b077810 */
/* 0x000fc80007ffe1ff */
/*0620*/ SHF.R.U32.HI R6, RZ, R7, R8 ; /* 0x00000007ff067219 */
/* 0x000fc60000011608 */
/*0630*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, R15 ; /* 0x000000ffff0a0224 */
/* 0x000fe400078e000f */
/*0640*/ @P1 IMAD.MOV.U32 R10, RZ, RZ, R16 ; /* 0x000000ffff0a1224 */
/* 0x000fe400078e0010 */
/*0650*/ @P2 IMAD.MOV.U32 R10, RZ, RZ, R4 ; /* 0x000000ffff0a2224 */
/* 0x000fe200078e0004 */
/*0660*/ SHF.L.U32 R4, R8, R11, RZ ; /* 0x0000000b08047219 */
/* 0x000fe200000006ff */
/*0670*/ IMAD.IADD R6, R6, 0x1, R9 ; /* 0x0000000106067824 */
/* 0x000fc600078e0209 */
/*0680*/ SHF.R.U32.HI R7, RZ, R7, R10 ; /* 0x00000007ff077219 */
/* 0x000fca000001160a */
/*0690*/ IMAD.IADD R8, R7, 0x1, R4 ; /* 0x0000000107087824 */
/* 0x000fe400078e0204 */
/*06a0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*06b0*/ SHF.L.U32.HI R11, R8.reuse, 0x2, R6 ; /* 0x00000002080b7819 */
/* 0x040fe20000010606 */
/*06c0*/ IMAD.SHL.U32 R10, R8, 0x4, RZ ; /* 0x00000004080a7824 */
/* 0x000fe200078e00ff */
/*06d0*/ LOP3.LUT P1, R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fe4000782c0ff */
/*06e0*/ SHF.R.U32.HI R7, RZ, 0x1f, R11 ; /* 0x0000001fff077819 */
/* 0x000fc8000001160b */
/*06f0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f05270 */
/*0700*/ LEA.HI R4, R6, R7, RZ, 0x2 ; /* 0x0000000706047211 */
/* 0x000fd600078f10ff */
/*0710*/ @P0 LOP3.LUT R11, RZ, R11, RZ, 0x33, !PT ; /* 0x0000000bff0b0212 */
/* 0x000fe400078e33ff */
/*0720*/ @P0 LOP3.LUT R10, RZ, R10, RZ, 0x33, !PT ; /* 0x0000000aff0a0212 */
/* 0x000fe400078e33ff */
/*0730*/ @P0 LOP3.LUT R3, R3, 0x80000000, RZ, 0x3c, !PT ; /* 0x8000000003030812 */
/* 0x000fe400078e3cff */
/*0740*/ I2F.F64.S64 R8, R10 ; /* 0x0000000a00087312 */
/* 0x000e240000301c00 */
/*0750*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003f05270 */
/*0760*/ IMAD.MOV R3, RZ, RZ, -R4 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a04 */
/*0770*/ @P1 IMAD.MOV.U32 R4, RZ, RZ, R3 ; /* 0x000000ffff041224 */
/* 0x000fe200078e0003 */
/*0780*/ DMUL R8, R8, c[0x2][0x0] ; /* 0x0080000008087a28 */
/* 0x001e140000000000 */
/*0790*/ F2F.F32.F64 R8, R8 ; /* 0x0000000800087310 */
/* 0x001e240000301000 */
/*07a0*/ FSEL R17, R8, -R8, !P0 ; /* 0x8000000808117208 */
/* 0x001fe20004000000 */
/*07b0*/ BRA 0x7e0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*07c0*/ FMUL R17, RZ, R3 ; /* 0x00000003ff117220 */
/* 0x000fe40000400000 */
/*07d0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe400078e00ff */
/*07e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*07f0*/ IADD3 R8, R4, 0x1, RZ ; /* 0x0000000104087810 */
/* 0x000fe20007ffe0ff */
/*0800*/ IMAD.MOV.U32 R4, RZ, RZ, 0x3c0885e4 ; /* 0x3c0885e4ff047424 */
/* 0x000fe400078e00ff */
/*0810*/ FMUL R9, R17, R17 ; /* 0x0000001111097220 */
/* 0x000fe20000400000 */
/*0820*/ LOP3.LUT P1, RZ, R8.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000108ff7812 */
/* 0x040fe2000782c0ff */
/*0830*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3e2aaaa8 ; /* 0x3e2aaaa8ff077424 */
/* 0x000fe200078e00ff */
/*0840*/ LOP3.LUT P0, RZ, R8, 0x2, RZ, 0xc0, !PT ; /* 0x0000000208ff7812 */
/* 0x000fe2000780c0ff */
/*0850*/ IMAD.MOV.U32 R3, RZ, RZ, -0x46b2bead ; /* 0xb94d4153ff037424 */
/* 0x000fe200078e00ff */
/*0860*/ FSEL R4, R4, 0.041666727513074874878, !P1 ; /* 0x3d2aaabb04047808 */
/* 0x000fc40004800000 */
/*0870*/ FSEL R17, R17, 1, !P1 ; /* 0x3f80000011117808 */
/* 0x000fca0004800000 */
/*0880*/ FFMA R8, R17, R9, RZ ; /* 0x0000000911087223 */
/* 0x000fe400000000ff */
/*0890*/ @P1 IMAD.MOV.U32 R6, RZ, RZ, 0x37cbac00 ; /* 0x37cbac00ff061424 */
/* 0x000fc800078e00ff */
/*08a0*/ @P1 FFMA R3, R9, R6, -0.0013887860113754868507 ; /* 0xbab607ed09031423 */
/* 0x000fe20000000006 */
/*08b0*/ FSEL R6, -R7, -0.4999999701976776123, !P1 ; /* 0xbeffffff07067808 */
/* 0x000fc60004800100 */
/*08c0*/ FFMA R3, R9, R3, R4 ; /* 0x0000000309037223 */
/* 0x000fe20000000004 */
/*08d0*/ LEA R4, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000047a11 */
/* 0x000fc600078210ff */
/*08e0*/ FFMA R3, R9, R3, R6 ; /* 0x0000000309037223 */
/* 0x000fe20000000006 */
/*08f0*/ LEA.HI.X R5, R0.reuse, c[0x0][0x16c], R5, 0x2, P1 ; /* 0x00005b0000057a11 */
/* 0x040fe400008f1405 */
/*0900*/ IADD3 R0, R0, 0x200, RZ ; /* 0x0000020000007810 */
/* 0x000fe20007ffe0ff */
/*0910*/ FFMA R3, R3, R8, R17 ; /* 0x0000000803037223 */
/* 0x000fc80000000011 */
/*0920*/ @P0 FFMA R3, R3, -1, RZ ; /* 0xbf80000003030823 */
/* 0x000fe200000000ff */
/*0930*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fc80003f06270 */
/*0940*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0001f2000c101906 */
/*0950*/ @!P0 BRA 0x50 ; /* 0xfffff6f000008947 */
/* 0x000fea000383ffff */
/*0960*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0970*/ BRA 0x970; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8cos_main9cosParams
.globl _Z8cos_main9cosParams
.p2align 8
.type _Z8cos_main9cosParams,@function
_Z8cos_main9cosParams:
s_load_b32 s2, s[0:1], 0x10
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s2, v0
s_cbranch_execz .LBB0_7
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v3, 2, v0
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v1, s0, s4, v3
v_add_co_ci_u32_e64 v2, null, s5, 0, s0
v_add_co_u32 v3, s0, s6, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, null, s7, 0, s0
s_mov_b32 s4, 0x7fffff
s_mov_b32 s5, 0xb94c1982
s_mov_b32 s6, 0x37d75334
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_dual_mul_f32 v8, v6, v6 :: v_dual_and_b32 v11, 1, v7
v_add_nc_u32_e32 v0, 0x200, v0
v_lshlrev_b32_e32 v7, 30, v7
v_fmaak_f32 v9, s5, v8, 0x3c0881c4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_u32_e32 vcc_lo, 0, v11
v_and_b32_e32 v7, 0x80000000, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v9, v8, v9, 0xbe2aaa9d
v_dual_fmaak_f32 v10, s6, v8, 0xbab64f3b :: v_dual_mul_f32 v9, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmaak_f32 v10, v8, v10, 0x3d2aabf7
v_fmac_f32_e32 v6, v6, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v10, v8, v10, 0xbf000004
v_fma_f32 v8, v8, v10, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v6, -v6, v8, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v5, 0x1f8
v_xor_b32_e32 v6, v7, v6
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e32 v5, 0x7fc00000, v6, vcc_lo
v_add_co_u32 v1, vcc_lo, v1, 0x800
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s2, v0
global_store_b32 v[3:4], v5, off
v_add_co_u32 v3, s0, v3, 0x800
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v4, s0, 0, v4, s0
s_or_b32 s3, vcc_lo, s3
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execz .LBB0_7
.LBB0_3:
global_load_b32 v5, v[1:2], off
s_mov_b32 s1, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_ngt_f32_e64 0x48000000, |v5|
s_xor_b32 s7, exec_lo, s1
s_cbranch_execz .LBB0_5
v_dual_mov_b32 v8, 0 :: v_dual_and_b32 v13, 0x7fffffff, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_and_or_b32 v16, v13, s4, 0x800000
v_lshrrev_b32_e32 v13, 23, v13
v_mad_u64_u32 v[6:7], null, v16, 0xfe5163ab, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v14, 0xffffff88, v13
v_cmp_lt_u32_e32 vcc_lo, 63, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[9:10], null, v16, 0x3c439041, v[7:8]
v_cndmask_b32_e64 v15, 0, 0xffffffc0, vcc_lo
v_mov_b32_e32 v7, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v15, v15, v14
v_mad_u64_u32 v[10:11], null, v16, 0xdb629599, v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_u32_e64 s0, 31, v15
v_cndmask_b32_e64 v17, 0, 0xffffffe0, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mov_b32 v7, v11 :: v_dual_cndmask_b32 v6, v10, v6
v_add_nc_u32_e32 v17, v17, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[11:12], null, v16, 0xf534ddc0, v[7:8]
v_cmp_lt_u32_e64 s1, 31, v17
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mov_b32_e32 v7, v12
v_cndmask_b32_e32 v9, v11, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[12:13], null, v16, 0xfc2757d1, v[7:8]
v_cndmask_b32_e64 v6, v9, v6, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v7, v13
v_mad_u64_u32 v[13:14], null, v16, 0x4e441529, v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v7, v14
v_mad_u64_u32 v[14:15], null, v16, 0xa2f9836e, v[7:8]
v_cndmask_b32_e64 v7, 0, 0xffffffe0, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v8, v13, v11 :: v_dual_add_nc_u32 v7, v7, v17
v_dual_cndmask_b32 v14, v14, v12 :: v_dual_cndmask_b32 v13, v15, v13
v_cndmask_b32_e32 v12, v12, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_u32_e32 vcc_lo, 0, v7
v_cndmask_b32_e64 v11, v14, v8, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v13, v13, v14, s0
v_cndmask_b32_e64 v8, v8, v12, s0
v_sub_nc_u32_e32 v14, 32, v7
v_cndmask_b32_e64 v12, v12, v9, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v13, v13, v11, s1
v_cndmask_b32_e64 v11, v11, v8, s1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v8, v8, v12, s1
v_cndmask_b32_e64 v6, v12, v6, s1
v_alignbit_b32 v15, v13, v11, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_alignbit_b32 v10, v11, v8, v14
v_cndmask_b32_e32 v7, v15, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v13, v8, v6, v14
v_cndmask_b32_e32 v9, v10, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_bfe_u32 v10, v7, 29, 1
v_cndmask_b32_e32 v8, v13, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v11, v7, v9, 30
v_sub_nc_u32_e32 v12, 0, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_alignbit_b32 v9, v9, v8, 30
v_alignbit_b32 v6, v8, v6, 30
v_xor_b32_e32 v11, v11, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v8, v9, v12
v_xor_b32_e32 v6, v6, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_clz_i32_u32_e32 v13, v11
v_min_u32_e32 v13, 32, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v9, 31, v13
v_lshlrev_b32_e32 v15, 23, v13
v_alignbit_b32 v11, v11, v8, v9
v_alignbit_b32 v6, v8, v6, v9
v_lshrrev_b32_e32 v9, 29, v7
v_lshrrev_b32_e32 v7, 30, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v8, v11, v6, 9
v_lshlrev_b32_e32 v9, 31, v9
v_lshrrev_b32_e32 v11, 9, v11
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v7, v10, v7
v_clz_i32_u32_e32 v12, v8
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v14, 0.5, v9
v_min_u32_e32 v12, 32, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v14, v14, v15
v_sub_nc_u32_e32 v16, 31, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v6, v8, v6, v16
v_or_b32_e32 v8, v11, v14
v_add_lshl_u32 v11, v12, v13, 23
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshrrev_b32_e32 v6, 9, v6
v_mul_f32_e32 v12, 0x3fc90fda, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v6, v6, v11
v_fma_f32 v11, v8, 0x3fc90fda, -v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v6, 0x33000000, v6
v_fmac_f32_e32 v11, 0x33a22168, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v6, v6, v9
v_fmac_f32_e32 v11, 0x3fc90fda, v6
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v6, v12, v11
.LBB0_5:
s_and_not1_saveexec_b32 s0, s7
s_cbranch_execz .LBB0_2
v_mul_f32_e64 v6, 0x3f22f983, |v5|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v7, v6
v_fma_f32 v6, v7, 0xbfc90fda, |v5|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, 0xb3a22168, v7
v_fmac_f32_e32 v6, 0xa7c234c4, v7
v_cvt_i32_f32_e32 v7, v7
s_branch .LBB0_2
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8cos_main9cosParams
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8cos_main9cosParams, .Lfunc_end0-_Z8cos_main9cosParams
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 24
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8cos_main9cosParams
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z8cos_main9cosParams.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d8b16_00000000-6_CUDA_example_01.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z8cos_main9cosParamsR9cosParams
.type _Z35__device_stub__Z8cos_main9cosParamsR9cosParams, @function
_Z35__device_stub__Z8cos_main9cosParamsR9cosParams:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq %rdi, 64(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z8cos_main9cosParams(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z8cos_main9cosParamsR9cosParams, .-_Z35__device_stub__Z8cos_main9cosParamsR9cosParams
.globl _Z8cos_main9cosParams
.type _Z8cos_main9cosParams, @function
_Z8cos_main9cosParams:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq 16(%rsp), %rdi
call _Z35__device_stub__Z8cos_main9cosParamsR9cosParams
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8cos_main9cosParams, .-_Z8cos_main9cosParams
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "\nBeginning CUDA example code on the CPU...\n"
.align 8
.LC1:
.string "Getting some info about CUDA devices on your system...\n"
.align 8
.LC2:
.string "There is %d CUDA device on your system.\n"
.align 8
.LC3:
.string "There are %d CUDA devices on your system.\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "\nCUDA Device #%d\n"
.LC5:
.string "Name: %s\n"
.LC6:
.string "\n"
.section .rodata.str1.8
.align 8
.LC7:
.string "Allocating memory on the CPU... (n=%d)\n"
.align 8
.LC10:
.string "Allocating memory on the GPU... (n=%d)\n"
.align 8
.LC11:
.string " value = %d : Memory Allocation on GPU Device failed\n"
.align 8
.LC12:
.string "done. Allocating more memory on the GPU...\n"
.align 8
.LC13:
.string "done again. Copying stuff from host (CPU) to device (GPU)...\n"
.align 8
.LC14:
.string " Memory Copy from Host to Device failed.\n"
.section .rodata.str1.1
.LC15:
.string "successful.\n"
.LC16:
.string "Launching kernel on GPU...\n"
.section .rodata.str1.8
.align 8
.LC17:
.string "GPU computations finished. Copying result back to CPU...\n"
.align 8
.LC18:
.string " Memory Copy from Device to Host failed.\n"
.align 8
.LC19:
.string "Copy back successful. Printing result...\n"
.section .rodata.str1.1
.LC20:
.string "cos(%f) = %f\n"
.LC21:
.string "Freeing memory...\n"
.LC22:
.string "\n\nFinished. :)\n\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $1128, %rsp
.cfi_def_cfa_offset 1168
movq %fs:40, %rax
movq %rax, 1112(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 4(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 4(%rsp), %edx
cmpl $1, %edx
je .L35
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L15:
movl $0, %ebx
leaq .LC4(%rip), %r13
leaq 80(%rsp), %rbp
leaq .LC5(%rip), %r12
cmpl $0, 4(%rsp)
jle .L14
.L13:
movl %ebx, %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %rbp, %rdx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 4(%rsp)
jg .L13
.L14:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movl $1000000, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4000000, %edi
call malloc@PLT
movq %rax, %rbp
movl $4000000, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %eax
movss .LC8(%rip), %xmm2
movss .LC9(%rip), %xmm1
.L16:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss %xmm2, %xmm0
divss %xmm1, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $1000000, %rax
jne .L16
movl $1000000, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 16(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
testl %eax, %eax
je .L17
movl %eax, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L18:
leaq 8(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
testl %eax, %eax
je .L19
movl %eax, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L20:
movl $1, %ecx
movl $4000000, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
je .L21
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L22:
movq 8(%rsp), %rbx
movq 16(%rsp), %r13
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $512, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L23:
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $4000000, %edx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
je .L24
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L26:
movl $0, %ebx
leaq .LC20(%rip), %r13
jmp .L25
.L35:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L15
.L17:
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L18
.L19:
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L20
.L21:
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L22
.L36:
movq %r13, 48(%rsp)
movq %rbx, 56(%rsp)
movl $1000000, 64(%rsp)
leaq 48(%rsp), %rdi
call _Z35__device_stub__Z8cos_main9cosParamsR9cosParams
jmp .L23
.L24:
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L26
.L27:
addq $1, %rbx
cmpq $1000000, %rbx
je .L37
.L25:
movslq %ebx, %rax
imulq $351843721, %rax, %rax
sarq $45, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
imull $100000, %eax, %eax
cmpl %ebx, %eax
jne .L27
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
pxor %xmm1, %xmm1
cvtss2sd (%r12,%rbx,4), %xmm1
movq %r13, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
jmp .L27
.L37:
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 1112(%rsp), %rax
subq %fs:40, %rax
jne .L38
movl $0, %eax
addq $1128, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC23:
.string "_Z8cos_main9cosParams"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC23(%rip), %rdx
movq %rdx, %rcx
leaq _Z8cos_main9cosParams(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC8:
.long 1086918618
.align 4
.LC9:
.long 1232348160
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "CUDA_example_01.hip"
.globl _Z23__device_stub__cos_main9cosParams # -- Begin function _Z23__device_stub__cos_main9cosParams
.p2align 4, 0x90
.type _Z23__device_stub__cos_main9cosParams,@function
_Z23__device_stub__cos_main9cosParams: # @_Z23__device_stub__cos_main9cosParams
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movq %rsp, %r9
movl $_Z8cos_main9cosParams, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z23__device_stub__cos_main9cosParams, .Lfunc_end0-_Z23__device_stub__cos_main9cosParams
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x40c90fda # float 6.283185
.LCPI1_1:
.long 0x49742400 # float 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1560, %rsp # imm = 0x618
.cfi_def_cfa_offset 1616
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.Lstr, %edi
callq puts@PLT
movl $.Lstr.1, %edi
callq puts@PLT
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
movl 12(%rsp), %esi
cmpl $1, %esi
jne .LBB1_2
# %bb.1:
movl $.L.str.2, %edi
movl $1, %esi
jmp .LBB1_3
.LBB1_2:
movl $.L.str.3, %edi
.LBB1_3:
xorl %eax, %eax
callq printf
cmpl $0, 12(%rsp)
jle .LBB1_6
# %bb.4: # %.lr.ph.preheader
leaq 88(%rsp), %rbx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_5: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.4, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.5, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
incl %ebp
cmpl 12(%rsp), %ebp
jl .LBB1_5
.LBB1_6: # %._crit_edge
movl $10, %edi
callq putchar@PLT
movq $0, 24(%rsp)
movq $0, 16(%rsp)
xorl %r15d, %r15d
movl $.L.str.7, %edi
movl $1000000, %esi # imm = 0xF4240
xorl %eax, %eax
callq printf
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %rbx
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %r14
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
xorps %xmm2, %xmm2
cvtsi2ss %r15d, %xmm2
mulss %xmm0, %xmm2
divss %xmm1, %xmm2
movss %xmm2, (%rbx,%r15,4)
incq %r15
cmpq $1000000, %r15 # imm = 0xF4240
jne .LBB1_7
# %bb.8:
movl $.L.str.8, %edi
movl $1000000, %esi # imm = 0xF4240
xorl %eax, %eax
callq printf
leaq 16(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
testl %eax, %eax
je .LBB1_10
# %bb.9:
movl $.L.str.9, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
jmp .LBB1_11
.LBB1_10:
movl $.Lstr.2, %edi
callq puts@PLT
.LBB1_11:
leaq 24(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
testl %eax, %eax
je .LBB1_13
# %bb.12:
movl $.L.str.9, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
jmp .LBB1_14
.LBB1_13:
movl $.Lstr.3, %edi
callq puts@PLT
.LBB1_14:
movq 16(%rsp), %rdi
movl $4000000, %edx # imm = 0x3D0900
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
movl $.Lstr.4, %eax
movl $.Lstr.5, %edi
cmoveq %rax, %rdi
callq puts@PLT
movq 24(%rsp), %r12
movq 16(%rsp), %r13
movl $.Lstr.6, %edi
callq puts@PLT
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 511(%rdi), %rdx
xorl %r15d, %r15d
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_16
# %bb.15:
movq %r13, 88(%rsp)
movq %r12, 96(%rsp)
movl $1000000, 104(%rsp) # imm = 0xF4240
leaq 88(%rsp), %rax
movq %rax, 32(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z8cos_main9cosParams, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_16:
movl $.Lstr.7, %edi
callq puts@PLT
movq 24(%rsp), %rsi
movl $4000000, %edx # imm = 0x3D0900
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
movl $.Lstr.8, %eax
movl $.Lstr.9, %edi
cmoveq %rax, %rdi
callq puts@PLT
xorl %r12d, %r12d
jmp .LBB1_17
.p2align 4, 0x90
.LBB1_19: # in Loop: Header=BB1_17 Depth=1
incq %r12
decl %r15d
cmpq $1000000, %r12 # imm = 0xF4240
je .LBB1_20
.LBB1_17: # =>This Inner Loop Header: Depth=1
movl %r12d, %eax
shrl $5, %eax
imulq $175921861, %rax, %rax # imm = 0xA7C5AC5
shrq $39, %rax
imull $100000, %eax, %eax # imm = 0x186A0
addl %r15d, %eax
jne .LBB1_19
# %bb.18: # in Loop: Header=BB1_17 Depth=1
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss (%r14,%r12,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movl $.L.str.18, %edi
movb $2, %al
callq printf
jmp .LBB1_19
.LBB1_20:
movl $.Lstr.10, %edi
callq puts@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movl $.Lstr.11, %edi
callq puts@PLT
xorl %eax, %eax
addq $1560, %rsp # imm = 0x618
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8cos_main9cosParams, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8cos_main9cosParams,@object # @_Z8cos_main9cosParams
.section .rodata,"a",@progbits
.globl _Z8cos_main9cosParams
.p2align 3, 0x0
_Z8cos_main9cosParams:
.quad _Z23__device_stub__cos_main9cosParams
.size _Z8cos_main9cosParams, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "There is %d CUDA device on your system.\n"
.size .L.str.2, 41
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "There are %d CUDA devices on your system.\n"
.size .L.str.3, 43
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\nCUDA Device #%d\n"
.size .L.str.4, 18
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Name: %s\n"
.size .L.str.5, 11
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Allocating memory on the CPU... (n=%d)\n"
.size .L.str.7, 40
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Allocating memory on the GPU... (n=%d)\n"
.size .L.str.8, 40
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz " value = %d : Memory Allocation on GPU Device failed\n"
.size .L.str.9, 54
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "cos(%f) = %f\n"
.size .L.str.18, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8cos_main9cosParams"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nBeginning CUDA example code on the CPU..."
.size .Lstr, 43
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Getting some info about CUDA devices on your system..."
.size .Lstr.1, 55
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "done. Allocating more memory on the GPU..."
.size .Lstr.2, 43
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "done again. Copying stuff from host (CPU) to device (GPU)..."
.size .Lstr.3, 61
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "successful."
.size .Lstr.4, 12
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz " Memory Copy from Host to Device failed."
.size .Lstr.5, 41
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "Launching kernel on GPU..."
.size .Lstr.6, 27
.type .Lstr.7,@object # @str.7
.Lstr.7:
.asciz "GPU computations finished. Copying result back to CPU..."
.size .Lstr.7, 57
.type .Lstr.8,@object # @str.8
.Lstr.8:
.asciz "Copy back successful. Printing result..."
.size .Lstr.8, 41
.type .Lstr.9,@object # @str.9
.Lstr.9:
.asciz " Memory Copy from Device to Host failed."
.size .Lstr.9, 41
.type .Lstr.10,@object # @str.10
.Lstr.10:
.asciz "Freeing memory..."
.size .Lstr.10, 18
.type .Lstr.11,@object # @str.11
.Lstr.11:
.asciz "\n\nFinished. :)\n"
.size .Lstr.11, 16
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__cos_main9cosParams
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8cos_main9cosParams
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.