system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00178ddc_00000000-6_hello-cuda.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8distance6float2S_
.type _Z8distance6float2S_, @function
_Z8distance6float2S_:
.LFB3669:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z8distance6float2S_, .-_Z8distance6float2S_
.globl _Z14init_host_dataP6float2i
.type _Z14init_host_dataP6float2i, @function
_Z14init_host_dataP6float2i:
.LFB3670:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L10
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
leal -1(%rsi), %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd .LC0(%rip), %xmm0
mulsd .LC1(%rip), %xmm0
movsd %xmm0, 8(%rsp)
movslq %esi, %r12
movl $0, %ebx
.L7:
pxor %xmm0, %xmm0
cvtsi2ssl %ebx, %xmm0
cvtss2sd %xmm0, %xmm0
divsd 8(%rsp), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 0(%rbp,%rbx,8)
call sinf@PLT
movss %xmm0, 4(%rbp,%rbx,8)
addq $1, %rbx
cmpq %r12, %rbx
jne .L7
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE3670:
.size _Z14init_host_dataP6float2i, .-_Z14init_host_dataP6float2i
.globl _Z44__device_stub__Z15distance_kernelP6float2PfiP6float2Pfi
.type _Z44__device_stub__Z15distance_kernelP6float2PfiP6float2Pfi, @function
_Z44__device_stub__Z15distance_kernelP6float2PfiP6float2Pfi:
.LFB3696:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15distance_kernelP6float2Pfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z44__device_stub__Z15distance_kernelP6float2PfiP6float2Pfi, .-_Z44__device_stub__Z15distance_kernelP6float2PfiP6float2Pfi
.globl _Z15distance_kernelP6float2Pfi
.type _Z15distance_kernelP6float2Pfi, @function
_Z15distance_kernelP6float2Pfi:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z15distance_kernelP6float2PfiP6float2Pfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z15distance_kernelP6float2Pfi, .-_Z15distance_kernelP6float2Pfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string ":<"
.LC3:
.string ","
.LC4:
.string ">, dist:"
.text
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movq $0, 8(%rsp)
movl $32768, %edi
call malloc@PLT
movq %rax, %r13
movl $16384, %edi
call malloc@PLT
movq %rax, %r14
leaq 8(%rsp), %rdi
movl $32768, %esi
call cudaMalloc@PLT
movq %rsp, %rdi
movl $16384, %esi
call cudaMalloc@PLT
movl $4096, %esi
movq %r13, %rdi
call _Z14init_host_dataP6float2i
movl $1, %ecx
movl $32768, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $128, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L22:
movl $2, %ecx
movl $16384, %edx
movq (%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movl $0, %ebx
leaq _ZSt4cout(%rip), %r15
jmp .L27
.L31:
movl $4096, %edx
movq (%rsp), %rsi
movq 8(%rsp), %rdi
call _Z44__device_stub__Z15distance_kernelP6float2PfiP6float2Pfi
jmp .L22
.L34:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L32
call _ZSt16__throw_bad_castv@PLT
.L32:
call __stack_chk_fail@PLT
.L35:
movzbl 67(%r12), %esi
.L26:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %rbx
cmpq $4096, %rbx
je .L33
.L27:
movl %ebx, %esi
movq %r15, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $2, %edx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,8), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $1, %edx
leaq .LC3(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%r13), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $8, %edx
leaq .LC4(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r14,%rbx,4), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L34
cmpb $0, 56(%r12)
jne .L35
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L26
.L33:
movq %r13, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L36
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "_Z15distance_kernelP6float2Pfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z15distance_kernelP6float2Pfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 1413754136
.long 1074340347
.align 8
.LC1:
.long 0
.long 1079574528
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hello-cuda.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z30__device_stub__distance_kernelP15HIP_vector_typeIfLj2EEPfi # -- Begin function _Z30__device_stub__distance_kernelP15HIP_vector_typeIfLj2EEPfi
.p2align 4, 0x90
.type _Z30__device_stub__distance_kernelP15HIP_vector_typeIfLj2EEPfi,@function
_Z30__device_stub__distance_kernelP15HIP_vector_typeIfLj2EEPfi: # @_Z30__device_stub__distance_kernelP15HIP_vector_typeIfLj2EEPfi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15distance_kernelP15HIP_vector_typeIfLj2EEPfi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z30__device_stub__distance_kernelP15HIP_vector_typeIfLj2EEPfi, .Lfunc_end0-_Z30__device_stub__distance_kernelP15HIP_vector_typeIfLj2EEPfi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z14init_host_dataP15HIP_vector_typeIfLj2EEi
.LCPI1_0:
.quad 0x400921fb54442d18 # double 3.1415926535897931
.LCPI1_1:
.quad 0x4059000000000000 # double 100
.text
.globl _Z14init_host_dataP15HIP_vector_typeIfLj2EEi
.p2align 4, 0x90
.type _Z14init_host_dataP15HIP_vector_typeIfLj2EEi,@function
_Z14init_host_dataP15HIP_vector_typeIfLj2EEi: # @_Z14init_host_dataP15HIP_vector_typeIfLj2EEi
.cfi_startproc
# %bb.0:
# kill: def $esi killed $esi def $rsi
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
leal -1(%rsi), %eax
cvtsi2sd %eax, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
mulsd .LCPI1_1(%rip), %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %r15d, %xmm0
cvtss2sd %xmm0, %xmm0
divsd 8(%rsp), %xmm0 # 8-byte Folded Reload
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx,%r15,8)
callq sinf
movss %xmm0, 4(%rbx,%r15,8)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z14init_host_dataP15HIP_vector_typeIfLj2EEi, .Lfunc_end1-_Z14init_host_dataP15HIP_vector_typeIfLj2EEi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x4133a152310fa5e6 # double 1286482.1916450202
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq $0, 16(%rsp)
movq $0, 8(%rsp)
movl $32768, %edi # imm = 0x8000
callq malloc
movq %rax, %rbx
movl $16384, %edi # imm = 0x4000
callq malloc
movq %rax, %r14
leaq 8(%rsp), %rdi
movl $32768, %esi # imm = 0x8000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $16384, %esi # imm = 0x4000
callq hipMalloc
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %r15d, %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LCPI2_0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx,%r15,8)
callq sinf
movss %xmm0, 4(%rbx,%r15,8)
incq %r15
cmpq $4096, %r15 # imm = 0x1000
jne .LBB2_1
# %bb.2: # %_Z14init_host_dataP15HIP_vector_typeIfLj2EEi.exit
movq 8(%rsp), %rdi
movl $32768, %edx # imm = 0x8000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967328, %rdx # imm = 0x100000020
leaq 96(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $4096, 28(%rsp) # imm = 0x1000
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15distance_kernelP15HIP_vector_typeIfLj2EEPfi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq 16(%rsp), %rsi
movl $16384, %edx # imm = 0x4000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %r15d, %r15d
jmp .LBB2_5
.p2align 4, 0x90
.LBB2_8: # in Loop: Header=BB2_5 Depth=1
movq %r12, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB2_9: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB2_5 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r15
cmpq $4096, %r15 # imm = 0x1000
je .LBB2_10
.LBB2_5: # =>This Inner Loop Header: Depth=1
movl $_ZSt4cout, %edi
movl %r15d, %esi
callq _ZNSolsEi
movq %rax, %r12
movl $.L.str, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%rbx,%r15,8), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r12, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r12
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 12(%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r12, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r12
movl $.L.str.2, %esi
movl $8, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r12, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB2_11
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB2_5 Depth=1
cmpb $0, 56(%r12)
je .LBB2_8
# %bb.7: # in Loop: Header=BB2_5 Depth=1
movzbl 67(%r12), %ecx
jmp .LBB2_9
.LBB2_10:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_11:
.cfi_def_cfa_offset 176
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15distance_kernelP15HIP_vector_typeIfLj2EEPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15distance_kernelP15HIP_vector_typeIfLj2EEPfi,@object # @_Z15distance_kernelP15HIP_vector_typeIfLj2EEPfi
.section .rodata,"a",@progbits
.globl _Z15distance_kernelP15HIP_vector_typeIfLj2EEPfi
.p2align 3, 0x0
_Z15distance_kernelP15HIP_vector_typeIfLj2EEPfi:
.quad _Z30__device_stub__distance_kernelP15HIP_vector_typeIfLj2EEPfi
.size _Z15distance_kernelP15HIP_vector_typeIfLj2EEPfi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz ":<"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz ","
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz ">, dist:"
.size .L.str.2, 9
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15distance_kernelP15HIP_vector_typeIfLj2EEPfi"
.size .L__unnamed_1, 48
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__distance_kernelP15HIP_vector_typeIfLj2EEPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15distance_kernelP15HIP_vector_typeIfLj2EEPfi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /**
* Programma che simula il comportamento del gpdt per
* la risoluzione di un kernel di una serie di
* valori di dimensione variabile utilizzando la
* tecnologia cuda.
* compilare con:
* nvcc -o simil_gpdt_si_cuda simil_gpdt_si_cuda.cu
* lanciare con:
* ./simil_gpdt_si_cuda [numero vettori] [numero componenti] [numero di righe da calcolare] [tipo di kernel] [grado(int)/sigma(float)]
**/
#include <iostream>
#include <ctime>
#include <cstdlib>
#include <cstdio>
#include <math.h>
#include <cuda.h>
using namespace std;
/**
* Funzione che riempie i vettori con numeri
* casuali compresi tra 0 e 99.
**/
void riempi_vettori(float *vettori, int Nr_vet_elem, int Nr_vet_comp)
{
for (int i = 0; i < Nr_vet_elem; i++)
for(int j = 0; j < Nr_vet_comp; j++)
vettori[i * Nr_vet_comp + j] = i * 2 + j; //j % 4; //
}
/**
* Funzione che crea dei vettori contenente i valori significativi su cui
* calcolare la norma 2 al quadrato.
**/
void crea_vettori_termini_noti(int *vettori, int Nr_vet_elem, int Nr_vet_comp)
{
for (int i = 0; i < Nr_vet_elem; i++)
for(int j = 0; j < Nr_vet_comp; j++)
vettori[i * Nr_vet_comp + j] = (j+1)*3;
}
/**
* Funzione che crea un vettore contenente il numero di valori significative.
**/
void crea_vettori_posizioni(int *vettore, int Nr_vet_elem, int numero_val)
{
for (int i = 0; i < Nr_vet_elem; i++)
vettore[i] = numero_val;
}
/**
* kernel per il calcolo delle norme al quadrato dei vettori.
**/
__global__ void Kernel_norme(float *Vd, float *Nd, int *Vp, int *Vnp, int N, int C, int nr_max_val)
{
long int x = threadIdx.x + blockIdx.x * blockDim.x;
int pos;
if(x < N)
{
float norma = 0;
int Nr_val = Vnp[x];
for(int i = 0; i < Nr_val; i++)
{
pos = Vp[x * nr_max_val + i];
norma = norma + (Vd[x * C + pos] * Vd[x * C + pos]);
}
Nd[x] = norma;
}
}
/**
* Kernel per il calcolo del del guassiano, basato sul metodo utilizzato nel gpdt,
* modificato per l'utilizzo con la tecnologia CUDA.
**/
__global__ void Kernel_gaus(float *Vd, float *Ris, float *Nd, int N, int C, int dim_indici, int *ind, float sigma, int *Vp, int *Vnp, int nr_max_val)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int j;
int pos;
int tmp_ind;
float gaus;
for ( ; x < N ; x+=blockDim.x * gridDim.x)
{
for( ; y < dim_indici; y+=blockDim.y * gridDim.y)
{
tmp_ind = ind[y];
gaus = 0.0;
int Nr_val = Vnp[x];
for(j = 0; j < Nr_val; j++)
{
pos = Vp[x * nr_max_val + j];
gaus = gaus + (Vd[x * C + pos] * Vd[tmp_ind * C + pos]);
}
gaus = - 2.0*gaus +Nd[x] + Nd[tmp_ind];
gaus = (exp(-gaus*sigma));
//Ris[x * dim_indici + y] = gaus;
Ris[y * N + x] = gaus;
}
}
}
/**
* Kernel per il calcolo del kernel lineare
* modificato per l'utilizzo con la tecnologia CUDA.
**/
__global__ void Kernel_lineare(float *Vd, float *Ris, int N, int C, int dim_indici, int *ind, int *Vp, int *Vnp, int nr_max_val)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int j;
int pos;
int tmp_ind;
float lin;
for ( ; x < N ; x+=blockDim.x * gridDim.x)
{
for( ; y < dim_indici; y+=blockDim.y * gridDim.y)
{
tmp_ind = ind[y];
lin = 0.0;
int Nr_val = Vnp[x];
for(j = 0; j < Nr_val; j++)
{
pos = Vp[x * nr_max_val + j];
lin = lin + (Vd[x * C + pos] * Vd[tmp_ind * C + pos]);
}
//Ris[x * dim_indici + y] = lin;
Ris[y * N + x ] = lin;
}
}
}
/**
* Kernel per il calcolo del kernel lineare
* modificato per l'utilizzo con la tecnologia CUDA.
**/
__global__ void Kernel_polimoniale(float *Vd, float *Ris, int N, int C, int dim_indici, int *ind, int *Vp, int *Vnp, int nr_max_val, int s)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int j;
int pos;
int tmp_ind;
float pol;
float tmp;
for ( ; x < N ; x+=blockDim.x * gridDim.x)
{
for( ; y < dim_indici; y+=blockDim.y * gridDim.y)
{
tmp_ind = ind[y];
tmp = 1.0;
pol = 0.0;
int Nr_val = Vnp[x];
for(j = 0; j < Nr_val; j++)
{
pos = Vp[x * nr_max_val + j];
pol = pol + (Vd[x * C + pos] * Vd[tmp_ind * C + pos]);
}
pol = pol + 1;
for(j = 0; j < s; j++)
{
tmp = tmp * pol;
}
//Ris[x * dim_indici + y] = tmp;
Ris[y * N + x ] = tmp;
}
}
}
int main(int argc, char** argv)
{
/**
* Variabile contenente la percentuale dei valori significativi
* all'interno dei vettori.
**/
float perc_val_noti= 1.0 - 0.82;
/**
* Matrice contenente i vettori da cui calcolare la differeza
* per calcolarne le norme.
* Il numero di vettori e la dimensione degli stessi viene definita
* dall'utente.
**/
float *vettori;
/**
* Matrice contenente le posizioni all'interno del vettore contenente
* le posizioni dei valori significativi.
**/
int *vettore_posizioni;
/**
* Vettore contenente il numero di valori non nulli nel vettore.
**/
int *vett_numero_posizioni;
/**
* vettore contenente le norme 2 al quadreato dei vettori.
**/
float *vett_norme;
/**
* Matrice contenente i risultati.
**/
float *risultati;
/**
*
**/
int *indici;
/**
* Tempo impiegato per il calcolo
**/
float elapsedTime;
cudaEvent_t start, stop;
//nr di vettori e di elementi.
int Nr_vet_elem = atoi(argv[1]);
int Nr_vet_comp = atoi(argv[2]);
//Numero di righe da calcolare.
int Nr_righe = atoi(argv[3]);
/**
* Numero per la selezione del kernel.
* 1 = kernel lineare.
* 2 = kernel polimoniale.
* 3 = kernel gaussiano.
**/
int sel_kernel = atoi(argv[4]);
/**
* Sigma della funzione gaussiana.
**/
//float sigma = atoi(argv[5]);
//sigma = (1.0/(2.0*sigma*sigma));
//Copia per il device.
float *Vd;
int *Vp;
int *Vnp;
float *Nd;
float *Ris;
int *ind;
//Variabili per il controllo della memoria disponibile.
size_t free_byte;
size_t total_byte;
/**
* Variabile contenente il numero dei valori significativi.
**/
int numero_val_significativi = Nr_vet_comp * perc_val_noti;
//Spazio necessario per l'allocazione dei vettori.
int tot_vett_size = Nr_vet_elem * Nr_vet_comp * sizeof(float);
//Spazio necessario per l'allocazione della Matrice dei risultati.
int norme_size = Nr_vet_elem * sizeof(float);
//Spazio necessario per l'allocazione della Matrice delle posizioni.
int vett_pos_size = Nr_vet_elem * numero_val_significativi * sizeof(int);
//Spazio necessario per l'allocazione del vettore con il numero dei valori significativi.
int vett_nrpos_size = Nr_vet_elem * sizeof(int);
//Spazio necessario per l'allocazione di una colonna.
int col_size = Nr_vet_elem * sizeof(float);
//Allocazione.
vettori = (float*)malloc(tot_vett_size);
vett_norme = (float*)malloc(norme_size);
vettore_posizioni = (int*)malloc(vett_pos_size);
vett_numero_posizioni = (int*)malloc(vett_nrpos_size);
//Allocazione nel device.
cudaMalloc((void **)&Vd, tot_vett_size);
cudaMalloc((void **)&Nd, norme_size);
cudaMalloc((void **)&Vp, vett_pos_size);
cudaMalloc((void **)&Vnp, vett_nrpos_size);
srand(time(0));
//Riempimento dei vettori.
riempi_vettori(vettori, Nr_vet_elem, Nr_vet_comp);
//Riempimento dei vettori delle posizioni.
crea_vettori_termini_noti(vettore_posizioni, Nr_vet_elem, numero_val_significativi);
//Riempimento del vettore contenente il numero dei valori significativi.
crea_vettori_posizioni(vett_numero_posizioni, Nr_vet_elem, numero_val_significativi);
//trasferimento dei vettori nel device.
cudaMemcpy(Vd, vettori, tot_vett_size, cudaMemcpyHostToDevice);
//trasferimento dei vettori delle posizioni nel device.
cudaMemcpy(Vp, vettore_posizioni, vett_pos_size, cudaMemcpyHostToDevice);
//trasferimento del vettore conentente il numero di valori all'interno di ogni singolo vettore.
cudaMemcpy(Vnp, vett_numero_posizioni, vett_nrpos_size, cudaMemcpyHostToDevice);
cudaMemGetInfo( &free_byte, &total_byte );
int col_ospitabili_mem = (free_byte*0.7)/col_size;
int contatore = 0;
/**
* Valori impostati per ottimizzare il funzionamento del device.
* Questi valori sono basati sull'utilizzo di una Nvidia 230m.
**/
int dimXX =4;
int dimYY =128;
/**
* Numero di colonne ospitabili calcolabili dal kernel contemporaneamente.
* Purtroppo a causa del fatto che il kernel CUDA fallisca in automatico
* se impiega più di 5 secondi per il calcolo, è necessario inserire un
* limitatore per il calcolo.
* Questo valore è basato sull'utilizzo di una Nvidia 230m.
**/
int col_ospitabili = 200;
if (col_ospitabili > Nr_righe)
{
col_ospitabili = Nr_righe;
}
if (col_ospitabili > col_ospitabili_mem)
{
col_ospitabili = col_ospitabili_mem;
}
int numero_cicli = Nr_righe/col_ospitabili;
cout<<"Numero cicli necessari: "<<numero_cicli<<endl;
int risultati_size = Nr_righe * Nr_vet_elem * sizeof(float);
int indici_size = col_ospitabili * sizeof(int);
int risultati_part_size = col_ospitabili * Nr_vet_elem * sizeof(float);
risultati = (float*)malloc(risultati_size);
indici = (int*)malloc(indici_size);
int numSMs;
cudaDeviceGetAttribute(&numSMs, cudaDevAttrMultiProcessorCount, 0);
cudaMalloc((void **)&Ris, risultati_part_size);
cudaMalloc((void **)&ind, indici_size);
dim3 blockGridRows;
blockGridRows.x=Nr_vet_elem/dimXX + (Nr_vet_elem%dimXX== 0?0:1);;
blockGridRows.y=col_ospitabili/dimYY + (col_ospitabili%dimYY== 0?0:1);
dim3 threadBlockRows;
threadBlockRows.x=dimXX;
threadBlockRows.y=dimYY;
cout<<"Memoria allocata, griglie definite:"<<endl;
cout<<"blockGridRows.x: "<<blockGridRows.x<<endl;
cout<<"blockGridRows.y: "<<blockGridRows.y<<endl;
cout<<"threadBlockRows.x: "<<threadBlockRows.x<<endl;
cout<<"threadBlockRows.y: "<<threadBlockRows.y<<endl;
int cicle_dim = col_ospitabili * Nr_vet_elem * sizeof(float);
dim3 blockGridRowsn(Nr_vet_elem, 1);
int resto;
cudaEventCreate(&start);
cudaEventRecord(start,0);
switch(sel_kernel){
case(1):{
//cout<<"Kernel Lineare\n";
for(int i = 0; i < numero_cicli; i++)
{
for (int kk = 0; kk < col_ospitabili; kk++)
{
indici[kk] = contatore + kk;
}
cudaMemcpy(ind, indici, indici_size, cudaMemcpyHostToDevice);
//__global__ void Kernel_lineare(float *Vd, float *Ris, int N, int C, int dim_indici, int *ind, int *Vp, int *Vnp, int nr_max_val)
Kernel_lineare<<< blockGridRows, threadBlockRows>>>(Vd, Ris, Nr_vet_elem, Nr_vet_comp, col_ospitabili, ind, Vp, Vnp, numero_val_significativi);
cudaMemcpy(risultati+(i*col_ospitabili*Nr_vet_elem), Ris, cicle_dim, cudaMemcpyDeviceToHost);
contatore = contatore + col_ospitabili;
}
resto = Nr_righe - contatore;
if (resto > 0)
{
for (int kk = 0; kk < resto; kk++)
{
indici[kk] = contatore + kk;
}
cudaMemcpy(ind, indici, indici_size, cudaMemcpyHostToDevice);
Kernel_lineare<<< blockGridRows, threadBlockRows>>>(Vd, Ris, Nr_vet_elem, Nr_vet_comp, resto, ind, Vp, Vnp, numero_val_significativi);
cudaMemcpy(risultati+(numero_cicli)*(col_ospitabili*Nr_vet_elem), Ris, resto * Nr_vet_elem * sizeof(float), cudaMemcpyDeviceToHost);
}
break;
}
case(2):{
//cout<<"Kernel Polimoniale\n";
/**
* Grado del kernel.
**/
int grado = atoi(argv[5]);
for(int i = 0; i < numero_cicli; i++)
{
for (int kk = 0; kk < col_ospitabili; kk++)
{
indici[kk] = contatore + kk;
}
cudaMemcpy(ind, indici, indici_size, cudaMemcpyHostToDevice);
//__global__ void Kernel_polimoniale(float *Vd, float *Ris, int N, int C, int dim_indici, int *ind, int *Vp, int *Vnp, int nr_max_val, int s)
Kernel_polimoniale<<< blockGridRows, threadBlockRows>>>(Vd, Ris, Nr_vet_elem, Nr_vet_comp, col_ospitabili, ind, Vp, Vnp, numero_val_significativi,grado);
cudaMemcpy(risultati+(i*col_ospitabili*Nr_vet_elem), Ris, cicle_dim, cudaMemcpyDeviceToHost);
contatore = contatore + col_ospitabili;
}
resto = Nr_righe - contatore;
if (resto > 0)
{
for (int kk = 0; kk < resto; kk++)
{
indici[kk] = contatore + kk;
}
cudaMemcpy(ind, indici, indici_size, cudaMemcpyHostToDevice);
Kernel_polimoniale<<< blockGridRows, threadBlockRows>>>(Vd, Ris, Nr_vet_elem, Nr_vet_comp, resto, ind, Vp, Vnp, numero_val_significativi,grado);
cudaMemcpy(risultati+(numero_cicli)*(col_ospitabili*Nr_vet_elem), Ris, resto * Nr_vet_elem * sizeof(float), cudaMemcpyDeviceToHost);
}
break;
}
case(3):{
//cout<<"Kernel gaussiano\n";
/**
* Sigma della funzione gaussiana.
**/
float sigma = atof(argv[5]);
sigma = (1.0/(2.0*sigma*sigma));
//calcolo norme.
Kernel_norme<<< blockGridRowsn, 256 >>>(Vd, Nd, Vp, Vnp, Nr_vet_elem, Nr_vet_comp, numero_val_significativi);
//calcolo kernel
for(int i = 0; i < numero_cicli; i++)
{
for (int kk = 0; kk < col_ospitabili; kk++)
{
indici[kk] = contatore + kk;
}
cudaMemcpy(ind, indici, indici_size, cudaMemcpyHostToDevice);
//Kernel_gaus(float *Vd, float *Ris, float *Nd, int N, int C, int dim_indici, int *ind, float sigma, float *Vp, float *Vnp)
Kernel_gaus<<< blockGridRows, threadBlockRows>>>(Vd, Ris, Nd, Nr_vet_elem, Nr_vet_comp, col_ospitabili, ind, sigma, Vp, Vnp, numero_val_significativi);
cudaMemcpy(risultati+(i*col_ospitabili*Nr_vet_elem), Ris, cicle_dim, cudaMemcpyDeviceToHost);
contatore = contatore + col_ospitabili;
}
resto = Nr_righe - contatore;
if (resto > 0)
{
for (int kk = 0; kk < resto; kk++)
{
indici[kk] = contatore + kk;
}
cudaMemcpy(ind, indici, indici_size, cudaMemcpyHostToDevice);
Kernel_gaus<<< blockGridRows, threadBlockRows>>>(Vd, Ris, Nd, Nr_vet_elem, Nr_vet_comp, resto, ind, sigma, Vp, Vnp, numero_val_significativi);
cudaMemcpy(risultati+(numero_cicli)*(col_ospitabili*Nr_vet_elem), Ris, resto * Nr_vet_elem * sizeof(float), cudaMemcpyDeviceToHost);
}
break;
}
default:
{
cout<<"Scelta non valida.\n";
cout<<"4° argomento non esistente.\n";
cout<<"1 = kernel lineare\t2 = kernel polimoniale\t 3 = kernel gaussiano\n";
break;
}
}
cudaEventCreate(&stop);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start,stop);
cout<<"Tempo totale:\t"<<elapsedTime/1000<<" secondi\n";
/*for (int i = 0; i < Nr_vet_elem*Nr_righe; i++)
{
cout<<risultati[i]<<endl;
}*/
free(vettori);
free(vett_norme);
free(vettore_posizioni);
free(vett_numero_posizioni);
free(indici);
free(risultati);
cudaFree(Vd);
cudaFree(Vp);
cudaFree(Vnp);
cudaFree(Nd);
cudaFree(ind);
cudaFree(Ris);
return 0;
} | .file "tmpxft_0019b7bc_00000000-6_simil_gpdt_si_cuda.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3675:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14riempi_vettoriPfii
.type _Z14riempi_vettoriPfii, @function
_Z14riempi_vettoriPfii:
.LFB3669:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L3
leal (%rdx,%rsi,2), %r10d
movl %edx, %esi
movl $0, %r9d
movl $0, %r8d
jmp .L5
.L7:
movslq %r9d, %rax
leaq (%rdi,%rax,4), %rcx
movl %r8d, %eax
.L6:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rcx)
addl $1, %eax
addq $4, %rcx
cmpl %esi, %eax
jne .L6
.L8:
addl $2, %r8d
addl %edx, %r9d
addl $2, %esi
cmpl %r10d, %esi
je .L3
.L5:
testl %edx, %edx
jg .L7
jmp .L8
.L3:
ret
.cfi_endproc
.LFE3669:
.size _Z14riempi_vettoriPfii, .-_Z14riempi_vettoriPfii
.globl _Z25crea_vettori_termini_notiPiii
.type _Z25crea_vettori_termini_notiPiii, @function
_Z25crea_vettori_termini_notiPiii:
.LFB3670:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L10
leal 3(%rdx,%rdx,2), %r8d
movl $0, %r10d
movl $0, %r9d
jmp .L12
.L14:
movslq %r10d, %rax
leaq (%rdi,%rax,4), %rcx
movl $3, %eax
.L13:
movl %eax, (%rcx)
addl $3, %eax
addq $4, %rcx
cmpl %r8d, %eax
jne .L13
.L15:
addl $1, %r9d
addl %edx, %r10d
cmpl %r9d, %esi
je .L10
.L12:
testl %edx, %edx
jg .L14
jmp .L15
.L10:
ret
.cfi_endproc
.LFE3670:
.size _Z25crea_vettori_termini_notiPiii, .-_Z25crea_vettori_termini_notiPiii
.globl _Z22crea_vettori_posizioniPiii
.type _Z22crea_vettori_posizioniPiii, @function
_Z22crea_vettori_posizioniPiii:
.LFB3671:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L17
movq %rdi, %rax
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rcx
.L19:
movl %edx, (%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L19
.L17:
ret
.cfi_endproc
.LFE3671:
.size _Z22crea_vettori_posizioniPiii, .-_Z22crea_vettori_posizioniPiii
.globl _Z42__device_stub__Z12Kernel_normePfS_PiS0_iiiPfS_PiS0_iii
.type _Z42__device_stub__Z12Kernel_normePfS_PiS0_iiiPfS_PiS0_iii, @function
_Z42__device_stub__Z12Kernel_normePfS_PiS0_iiiPfS_PiS0_iii:
.LFB3697:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12Kernel_normePfS_PiS0_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z42__device_stub__Z12Kernel_normePfS_PiS0_iiiPfS_PiS0_iii, .-_Z42__device_stub__Z12Kernel_normePfS_PiS0_iiiPfS_PiS0_iii
.globl _Z12Kernel_normePfS_PiS0_iii
.type _Z12Kernel_normePfS_PiS0_iii, @function
_Z12Kernel_normePfS_PiS0_iii:
.LFB3698:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z42__device_stub__Z12Kernel_normePfS_PiS0_iiiPfS_PiS0_iii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z12Kernel_normePfS_PiS0_iii, .-_Z12Kernel_normePfS_PiS0_iii
.globl _Z48__device_stub__Z11Kernel_gausPfS_S_iiiPifS0_S0_iPfS_S_iiiPifS0_S0_i
.type _Z48__device_stub__Z11Kernel_gausPfS_S_iiiPifS0_S0_iPfS_S_iiiPifS0_S0_i, @function
_Z48__device_stub__Z11Kernel_gausPfS_S_iiiPifS0_S0_iPfS_S_iiiPifS0_S0_i:
.LFB3699:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movl %ecx, 36(%rsp)
movl %r8d, 32(%rsp)
movl %r9d, 28(%rsp)
movss %xmm0, 24(%rsp)
movq 240(%rsp), %rax
movq %rax, 16(%rsp)
movq 248(%rsp), %rax
movq %rax, 8(%rsp)
movq 256(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 28(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 24(%rsp), %rax
movq %rax, 184(%rsp)
leaq 8(%rsp), %rax
movq %rax, 192(%rsp)
movq %rsp, %rax
movq %rax, 200(%rsp)
leaq 264(%rsp), %rax
movq %rax, 208(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z11Kernel_gausPfS_S_iiiPifS0_S0_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3699:
.size _Z48__device_stub__Z11Kernel_gausPfS_S_iiiPifS0_S0_iPfS_S_iiiPifS0_S0_i, .-_Z48__device_stub__Z11Kernel_gausPfS_S_iiiPifS0_S0_iPfS_S_iiiPifS0_S0_i
.globl _Z11Kernel_gausPfS_S_iiiPifS0_S0_i
.type _Z11Kernel_gausPfS_S_iiiPifS0_S0_i, @function
_Z11Kernel_gausPfS_S_iiiPifS0_S0_i:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z48__device_stub__Z11Kernel_gausPfS_S_iiiPifS0_S0_iPfS_S_iiiPifS0_S0_i
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _Z11Kernel_gausPfS_S_iiiPifS0_S0_i, .-_Z11Kernel_gausPfS_S_iiiPifS0_S0_i
.globl _Z48__device_stub__Z14Kernel_linearePfS_iiiPiS0_S0_iPfS_iiiPiS0_S0_i
.type _Z48__device_stub__Z14Kernel_linearePfS_iiiPiS0_S0_iPfS_iiiPiS0_S0_i, @function
_Z48__device_stub__Z14Kernel_linearePfS_iiiPiS0_S0_iPfS_iiiPiS0_S0_i:
.LFB3701:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movl %edx, 44(%rsp)
movl %ecx, 40(%rsp)
movl %r8d, 36(%rsp)
movq %r9, 24(%rsp)
movq 224(%rsp), %rax
movq %rax, 16(%rsp)
movq 232(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 44(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 36(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
leaq 240(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z14Kernel_linearePfS_iiiPiS0_S0_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3701:
.size _Z48__device_stub__Z14Kernel_linearePfS_iiiPiS0_S0_iPfS_iiiPiS0_S0_i, .-_Z48__device_stub__Z14Kernel_linearePfS_iiiPiS0_S0_iPfS_iiiPiS0_S0_i
.globl _Z14Kernel_linearePfS_iiiPiS0_S0_i
.type _Z14Kernel_linearePfS_iiiPiS0_S0_i, @function
_Z14Kernel_linearePfS_iiiPiS0_S0_i:
.LFB3702:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z48__device_stub__Z14Kernel_linearePfS_iiiPiS0_S0_iPfS_iiiPiS0_S0_i
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3702:
.size _Z14Kernel_linearePfS_iiiPiS0_S0_i, .-_Z14Kernel_linearePfS_iiiPiS0_S0_i
.globl _Z53__device_stub__Z18Kernel_polimonialePfS_iiiPiS0_S0_iiPfS_iiiPiS0_S0_ii
.type _Z53__device_stub__Z18Kernel_polimonialePfS_iiiPiS0_S0_iiPfS_iiiPiS0_S0_ii, @function
_Z53__device_stub__Z18Kernel_polimonialePfS_iiiPiS0_S0_iiPfS_iiiPiS0_S0_ii:
.LFB3703:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movl %edx, 44(%rsp)
movl %ecx, 40(%rsp)
movl %r8d, 36(%rsp)
movq %r9, 24(%rsp)
movq 240(%rsp), %rax
movq %rax, 16(%rsp)
movq 248(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 44(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 36(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
leaq 264(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L49
.L45:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L50
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z18Kernel_polimonialePfS_iiiPiS0_S0_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L45
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3703:
.size _Z53__device_stub__Z18Kernel_polimonialePfS_iiiPiS0_S0_iiPfS_iiiPiS0_S0_ii, .-_Z53__device_stub__Z18Kernel_polimonialePfS_iiiPiS0_S0_iiPfS_iiiPiS0_S0_ii
.globl _Z18Kernel_polimonialePfS_iiiPiS0_S0_ii
.type _Z18Kernel_polimonialePfS_iiiPiS0_S0_ii, @function
_Z18Kernel_polimonialePfS_iiiPiS0_S0_ii:
.LFB3704:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z53__device_stub__Z18Kernel_polimonialePfS_iiiPiS0_S0_iiPfS_iiiPiS0_S0_ii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3704:
.size _Z18Kernel_polimonialePfS_iiiPiS0_S0_ii, .-_Z18Kernel_polimonialePfS_iiiPiS0_S0_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Numero cicli necessari: "
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Memoria allocata, griglie definite:"
.section .rodata.str1.1
.LC4:
.string "blockGridRows.x: "
.LC5:
.string "blockGridRows.y: "
.LC6:
.string "threadBlockRows.x: "
.LC7:
.string "threadBlockRows.y: "
.LC9:
.string "Scelta non valida.\n"
.LC10:
.string "4\302\260 argomento non esistente.\n"
.section .rodata.str1.8
.align 8
.LC11:
.string "1 = kernel lineare\t2 = kernel polimoniale\t 3 = kernel gaussiano\n"
.section .rodata.str1.1
.LC12:
.string "Tempo totale:\t"
.LC14:
.string " secondi\n"
.text
.globl main
.type main, @function
main:
.LFB3672:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $264, %rsp
.cfi_def_cfa_offset 320
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
movl %eax, 32(%rsp)
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movq %rax, 96(%rsp)
movl %eax, 80(%rsp)
movq 24(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 72(%rsp)
movl %eax, 4(%rsp)
movq 32(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 88(%rsp)
movq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2ssl %ebx, %xmm0
mulss .LC0(%rip), %xmm0
cvttss2sil %xmm0, %ebx
leal 0(,%r15,4), %r14d
movl %eax, %r12d
imull %r15d, %r12d
sall $2, %r12d
movslq %r12d, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, 40(%rsp)
movslq %r14d, %r13
movl %ebx, 36(%rsp)
imull %r15d, %ebx
sall $2, %ebx
movslq %ebx, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, 48(%rsp)
movq %r13, %rdi
call malloc@PLT
movq %rax, 56(%rsp)
leaq 128(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 152(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 136(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 144(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl 80(%rsp), %edx
movl 32(%rsp), %esi
movq 40(%rsp), %rdi
call _Z14riempi_vettoriPfii
movl 36(%rsp), %edx
movl 32(%rsp), %esi
movq 48(%rsp), %rdi
call _Z25crea_vettori_termini_notiPiii
movl 36(%rsp), %edx
movl 32(%rsp), %esi
movq 56(%rsp), %rdi
call _Z22crea_vettori_posizioniPiii
movl $1, %ecx
movq %r12, %rdx
movq 40(%rsp), %rsi
movq 128(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 48(%rsp), %rsi
movq 136(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq 56(%rsp), %rsi
movq 144(%rsp), %rdi
call cudaMemcpy@PLT
leaq 184(%rsp), %rsi
leaq 176(%rsp), %rdi
call cudaMemGetInfo@PLT
movq 176(%rsp), %rax
testq %rax, %rax
js .L54
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
.L55:
mulsd .LC1(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdl %r14d, %xmm1
divsd %xmm1, %xmm0
cvttsd2sil %xmm0, %ebx
movl $200, %eax
movq 72(%rsp), %r12
cmpl %eax, %r12d
cmovle %r12d, %eax
cmpl %eax, %ebx
cmovg %eax, %ebx
movl 4(%rsp), %eax
cltd
idivl %ebx
movl %eax, 4(%rsp)
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 4(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl %ebx, %ecx
imull %r15d, %ecx
movl %ecx, 84(%rsp)
movslq %ecx, %r14
movl %r12d, %edi
imull %r15d, %edi
sall $2, %edi
movslq %edi, %rdi
call malloc@PLT
movq %rax, 64(%rsp)
leal 0(,%rbx,4), %eax
movslq %eax, %rdi
movq %rdi, 8(%rsp)
call malloc@PLT
movq %rax, %r12
leaq 116(%rsp), %rdi
movl $0, %edx
movl $16, %esi
call cudaDeviceGetAttribute@PLT
movl 84(%rsp), %ecx
leal 0(,%rcx,4), %eax
movslq %eax, %rcx
movq %rcx, 24(%rsp)
leaq 160(%rsp), %rdi
movq %rcx, %rsi
call cudaMalloc@PLT
leaq 168(%rsp), %rdi
movq 8(%rsp), %rsi
call cudaMalloc@PLT
movl $1, 204(%rsp)
testb $3, %r15b
setne %dl
movzbl %dl, %edx
leal 3(%r15), %eax
testl %r15d, %r15d
cmovns %r15d, %eax
sarl $2, %eax
leal (%rdx,%rax), %ecx
movl %ecx, 16(%rsp)
testb $127, %bl
setne %dl
movzbl %dl, %edx
leal 127(%rbx), %eax
testl %ebx, %ebx
cmovns %ebx, %eax
sarl $7, %eax
leal (%rdx,%rax), %edi
movl %edi, 20(%rsp)
movl $1, 216(%rsp)
leaq .LC3(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC4(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 16(%rsp), %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC5(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 20(%rsp), %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC6(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $4, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC7(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $128, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl %r15d, 220(%rsp)
movl $1, 224(%rsp)
movl $1, 228(%rsp)
leaq 120(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 120(%rsp), %rdi
call cudaEventRecord@PLT
movq 88(%rsp), %rcx
cmpl $2, %ecx
je .L56
cmpl $3, %ecx
je .L57
cmpl $1, %ecx
jne .L58
cmpl $0, 4(%rsp)
jle .L86
leaq 0(,%r14,4), %rcx
movq 64(%rsp), %r14
movl %ebx, %ebp
movl $0, %r13d
movq %r15, 88(%rsp)
movq %rcx, %r15
jmp .L60
.L54:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
jmp .L55
.L62:
movl $2, %ecx
movq 24(%rsp), %rdx
movq 160(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
addl $1, %r13d
addl %ebx, %ebp
addq %r15, %r14
cmpl %r13d, 4(%rsp)
je .L105
.L60:
movl %ebp, %eax
subl %ebx, %eax
movq %r12, %rdx
testl %ebx, %ebx
jle .L64
.L61:
movl %eax, (%rdx)
addl $1, %eax
addq $4, %rdx
cmpl %eax, %ebp
jne .L61
.L64:
movl $1, %ecx
movq 8(%rsp), %rdx
movq %r12, %rsi
movq 168(%rsp), %rdi
call cudaMemcpy@PLT
movl 16(%rsp), %eax
movl %eax, 196(%rsp)
movl 20(%rsp), %eax
movl %eax, 200(%rsp)
movl $4, 208(%rsp)
movl $128, 212(%rsp)
movl 216(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 208(%rsp), %rdx
movq 196(%rsp), %rdi
movl 204(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L62
subq $8, %rsp
.cfi_def_cfa_offset 328
movl 44(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 336
pushq 160(%rsp)
.cfi_def_cfa_offset 344
pushq 160(%rsp)
.cfi_def_cfa_offset 352
movq 200(%rsp), %r9
movl %ebx, %r8d
movl 112(%rsp), %ecx
movl 64(%rsp), %edx
movq 192(%rsp), %rsi
movq 160(%rsp), %rdi
call _Z48__device_stub__Z14Kernel_linearePfS_iiiPiS0_S0_iPfS_iiiPiS0_S0_i
addq $32, %rsp
.cfi_def_cfa_offset 320
jmp .L62
.L105:
movq 88(%rsp), %r15
movl 4(%rsp), %eax
imull %eax, %ebx
.L59:
movq 72(%rsp), %rcx
movl %ecx, %ebp
subl %ebx, %ebp
testl %ebp, %ebp
jle .L65
movq %r12, %rax
movl %ecx, %edx
.L66:
movl %ebx, (%rax)
addl $1, %ebx
addq $4, %rax
cmpl %ebx, %edx
jne .L66
movl $1, %ecx
movq 8(%rsp), %rdx
movq %r12, %rsi
movq 168(%rsp), %rdi
call cudaMemcpy@PLT
movl 16(%rsp), %eax
movl %eax, 196(%rsp)
movl 20(%rsp), %eax
movl %eax, 200(%rsp)
movl $4, 208(%rsp)
movl $128, 212(%rsp)
movl 216(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 208(%rsp), %rdx
movq 196(%rsp), %rdi
movl 204(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L106
.L67:
imull %r15d, %ebp
movslq %ebp, %rdx
salq $2, %rdx
movl 84(%rsp), %eax
movl 4(%rsp), %ecx
imull %ecx, %eax
cltq
movq 64(%rsp), %rcx
leaq (%rcx,%rax,4), %rdi
movl $2, %ecx
movq 160(%rsp), %rsi
call cudaMemcpy@PLT
jmp .L65
.L86:
movl $0, %ebx
jmp .L59
.L106:
subq $8, %rsp
.cfi_def_cfa_offset 328
movl 44(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 336
pushq 160(%rsp)
.cfi_def_cfa_offset 344
pushq 160(%rsp)
.cfi_def_cfa_offset 352
movq 200(%rsp), %r9
movl %ebp, %r8d
movl 112(%rsp), %ecx
movl 64(%rsp), %edx
movq 192(%rsp), %rsi
movq 160(%rsp), %rdi
call _Z48__device_stub__Z14Kernel_linearePfS_iiiPiS0_S0_iPfS_iiiPiS0_S0_i
addq $32, %rsp
.cfi_def_cfa_offset 320
jmp .L67
.L56:
movq 40(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 104(%rsp)
movl %eax, 88(%rsp)
cmpl $0, 4(%rsp)
jle .L87
leaq 0(,%r14,4), %rax
movq 64(%rsp), %r14
movl %ebx, %ebp
movl $0, %r13d
movq %r15, 96(%rsp)
movq %rax, %r15
jmp .L69
.L71:
movl $2, %ecx
movq 24(%rsp), %rdx
movq 160(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
addl $1, %r13d
addl %ebx, %ebp
addq %r15, %r14
cmpl %r13d, 4(%rsp)
je .L107
.L69:
movl %ebp, %eax
subl %ebx, %eax
movq %r12, %rdx
testl %ebx, %ebx
jle .L73
.L70:
movl %eax, (%rdx)
addl $1, %eax
addq $4, %rdx
cmpl %ebp, %eax
jne .L70
.L73:
movl $1, %ecx
movq 8(%rsp), %rdx
movq %r12, %rsi
movq 168(%rsp), %rdi
call cudaMemcpy@PLT
movl 16(%rsp), %eax
movl %eax, 196(%rsp)
movl 20(%rsp), %eax
movl %eax, 200(%rsp)
movl $4, 208(%rsp)
movl $128, 212(%rsp)
movl 216(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 208(%rsp), %rdx
movq 196(%rsp), %rdi
movl 204(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L71
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 328
movl 44(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 336
pushq 160(%rsp)
.cfi_def_cfa_offset 344
pushq 160(%rsp)
.cfi_def_cfa_offset 352
movq 200(%rsp), %r9
movl %ebx, %r8d
movl 112(%rsp), %ecx
movl 64(%rsp), %edx
movq 192(%rsp), %rsi
movq 160(%rsp), %rdi
call _Z53__device_stub__Z18Kernel_polimonialePfS_iiiPiS0_S0_iiPfS_iiiPiS0_S0_ii
addq $32, %rsp
.cfi_def_cfa_offset 320
jmp .L71
.L107:
movq 96(%rsp), %r15
movl 4(%rsp), %eax
imull %eax, %ebx
.L68:
movq 72(%rsp), %rcx
movl %ecx, %ebp
subl %ebx, %ebp
testl %ebp, %ebp
jle .L65
movq %r12, %rax
movl %ecx, %edx
.L74:
movl %ebx, (%rax)
addl $1, %ebx
addq $4, %rax
cmpl %edx, %ebx
jne .L74
movl $1, %ecx
movq 8(%rsp), %rdx
movq %r12, %rsi
movq 168(%rsp), %rdi
call cudaMemcpy@PLT
movl 16(%rsp), %eax
movl %eax, 196(%rsp)
movl 20(%rsp), %eax
movl %eax, 200(%rsp)
movl $4, 208(%rsp)
movl $128, 212(%rsp)
movl 216(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 208(%rsp), %rdx
movq 196(%rsp), %rdi
movl 204(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L108
.L75:
imull %r15d, %ebp
movslq %ebp, %rdx
salq $2, %rdx
movl 84(%rsp), %eax
movl 4(%rsp), %ecx
imull %ecx, %eax
cltq
movq 64(%rsp), %rcx
leaq (%rcx,%rax,4), %rdi
movl $2, %ecx
movq 160(%rsp), %rsi
call cudaMemcpy@PLT
jmp .L65
.L87:
movl $0, %ebx
jmp .L68
.L108:
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 328
movl 44(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 336
pushq 160(%rsp)
.cfi_def_cfa_offset 344
pushq 160(%rsp)
.cfi_def_cfa_offset 352
movq 200(%rsp), %r9
movl %ebp, %r8d
movl 112(%rsp), %ecx
movl 64(%rsp), %edx
movq 192(%rsp), %rsi
movq 160(%rsp), %rdi
call _Z53__device_stub__Z18Kernel_polimonialePfS_iiiPiS0_S0_iiPfS_iiiPiS0_S0_ii
addq $32, %rsp
.cfi_def_cfa_offset 320
jmp .L75
.L57:
movq 40(%rbp), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm0
movapd %xmm0, %xmm1
addsd %xmm0, %xmm1
mulsd %xmm0, %xmm1
movsd .LC8(%rip), %xmm0
divsd %xmm1, %xmm0
pxor %xmm2, %xmm2
cvtsd2ss %xmm0, %xmm2
movss %xmm2, 88(%rsp)
movl $256, 232(%rsp)
movl $1, 236(%rsp)
movl $1, 240(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 232(%rsp), %rdx
movl $1, %ecx
movq 220(%rsp), %rdi
movl 228(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L109
.L76:
cmpl $0, 4(%rsp)
jle .L88
leaq 0(,%r14,4), %rax
movq 64(%rsp), %r14
movl %ebx, %ebp
movl $0, %r13d
movq %r15, 104(%rsp)
movq %rax, %r15
jmp .L78
.L109:
subq $8, %rsp
.cfi_def_cfa_offset 328
movl 44(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 336
movl 112(%rsp), %r9d
movl %r15d, %r8d
movq 160(%rsp), %rcx
movq 152(%rsp), %rdx
movq 168(%rsp), %rsi
movq 144(%rsp), %rdi
call _Z42__device_stub__Z12Kernel_normePfS_PiS0_iiiPfS_PiS0_iii
addq $16, %rsp
.cfi_def_cfa_offset 320
jmp .L76
.L80:
movl $2, %ecx
movq 24(%rsp), %rdx
movq 160(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
addl $1, %r13d
addl %ebx, %ebp
addq %r15, %r14
cmpl %r13d, 4(%rsp)
je .L110
.L78:
movl %ebp, %eax
subl %ebx, %eax
movq %r12, %rdx
testl %ebx, %ebx
jle .L82
.L79:
movl %eax, (%rdx)
addl $1, %eax
addq $4, %rdx
cmpl %ebp, %eax
jne .L79
.L82:
movl $1, %ecx
movq 8(%rsp), %rdx
movq %r12, %rsi
movq 168(%rsp), %rdi
call cudaMemcpy@PLT
movl 16(%rsp), %eax
movl %eax, 196(%rsp)
movl 20(%rsp), %eax
movl %eax, 200(%rsp)
movl $4, 208(%rsp)
movl $128, 212(%rsp)
movl 216(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 208(%rsp), %rdx
movq 196(%rsp), %rdi
movl 204(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L80
movl 36(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 328
pushq 152(%rsp)
.cfi_def_cfa_offset 336
pushq 152(%rsp)
.cfi_def_cfa_offset 344
pushq 192(%rsp)
.cfi_def_cfa_offset 352
movss 120(%rsp), %xmm0
movl %ebx, %r9d
movl 112(%rsp), %r8d
movl 64(%rsp), %ecx
movq 184(%rsp), %rdx
movq 192(%rsp), %rsi
movq 160(%rsp), %rdi
call _Z48__device_stub__Z11Kernel_gausPfS_S_iiiPifS0_S0_iPfS_S_iiiPifS0_S0_i
addq $32, %rsp
.cfi_def_cfa_offset 320
jmp .L80
.L110:
movq 104(%rsp), %r15
movl 4(%rsp), %eax
imull %eax, %ebx
.L77:
movq 72(%rsp), %rax
movl %eax, %ebp
subl %ebx, %ebp
testl %ebp, %ebp
jle .L65
movq %r12, %rdx
.L83:
movl %ebx, (%rdx)
addl $1, %ebx
addq $4, %rdx
cmpl %eax, %ebx
jne .L83
movl $1, %ecx
movq 8(%rsp), %rdx
movq %r12, %rsi
movq 168(%rsp), %rdi
call cudaMemcpy@PLT
movl 16(%rsp), %eax
movl %eax, 196(%rsp)
movl 20(%rsp), %eax
movl %eax, 200(%rsp)
movl $4, 208(%rsp)
movl $128, 212(%rsp)
movl 216(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 208(%rsp), %rdx
movq 196(%rsp), %rdi
movl 204(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L111
.L84:
imull %r15d, %ebp
movslq %ebp, %rdx
salq $2, %rdx
movl 84(%rsp), %eax
movl 4(%rsp), %ecx
imull %ecx, %eax
cltq
movq 64(%rsp), %rcx
leaq (%rcx,%rax,4), %rdi
movl $2, %ecx
movq 160(%rsp), %rsi
call cudaMemcpy@PLT
jmp .L65
.L88:
movl $0, %ebx
jmp .L77
.L111:
movl 36(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 328
pushq 152(%rsp)
.cfi_def_cfa_offset 336
pushq 152(%rsp)
.cfi_def_cfa_offset 344
pushq 192(%rsp)
.cfi_def_cfa_offset 352
movss 120(%rsp), %xmm0
movl %ebp, %r9d
movl 128(%rsp), %r8d
movl 64(%rsp), %ecx
movq 184(%rsp), %rdx
movq 192(%rsp), %rsi
movq 160(%rsp), %rdi
call _Z48__device_stub__Z11Kernel_gausPfS_S_iiiPifS0_S0_iPfS_S_iiiPifS0_S0_i
addq $32, %rsp
.cfi_def_cfa_offset 320
jmp .L84
.L58:
leaq .LC9(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC10(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC11(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.L65:
leaq 232(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 232(%rsp), %rdi
call cudaEventRecord@PLT
movq 232(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 112(%rsp), %rdi
movq 232(%rsp), %rdx
movq 120(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC12(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movss 112(%rsp), %xmm0
divss .LC13(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC14(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 40(%rsp), %rdi
call free@PLT
movq 48(%rsp), %rdi
call free@PLT
movq 56(%rsp), %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 64(%rsp), %rdi
call free@PLT
movq 128(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rdi
call cudaFree@PLT
movq 144(%rsp), %rdi
call cudaFree@PLT
movq 152(%rsp), %rdi
call cudaFree@PLT
movq 168(%rsp), %rdi
call cudaFree@PLT
movq 160(%rsp), %rdi
call cudaFree@PLT
movq 248(%rsp), %rax
subq %fs:40, %rax
jne .L112
movl $0, %eax
addq $264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L112:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3672:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC15:
.string "_Z18Kernel_polimonialePfS_iiiPiS0_S0_ii"
.align 8
.LC16:
.string "_Z14Kernel_linearePfS_iiiPiS0_S0_i"
.align 8
.LC17:
.string "_Z11Kernel_gausPfS_S_iiiPifS0_S0_i"
.section .rodata.str1.1
.LC18:
.string "_Z12Kernel_normePfS_PiS0_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3706:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z18Kernel_polimonialePfS_iiiPiS0_S0_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z14Kernel_linearePfS_iiiPiS0_S0_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _Z11Kernel_gausPfS_S_iiiPifS0_S0_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z12Kernel_normePfS_PiS0_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3706:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1043878380
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 1717986918
.long 1072064102
.align 8
.LC8:
.long 0
.long 1072693248
.section .rodata.cst4
.align 4
.LC13:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
* Programma che simula il comportamento del gpdt per
* la risoluzione di un kernel di una serie di
* valori di dimensione variabile utilizzando la
* tecnologia cuda.
* compilare con:
* nvcc -o simil_gpdt_si_cuda simil_gpdt_si_cuda.cu
* lanciare con:
* ./simil_gpdt_si_cuda [numero vettori] [numero componenti] [numero di righe da calcolare] [tipo di kernel] [grado(int)/sigma(float)]
**/
#include <iostream>
#include <ctime>
#include <cstdlib>
#include <cstdio>
#include <math.h>
#include <cuda.h>
using namespace std;
/**
* Funzione che riempie i vettori con numeri
* casuali compresi tra 0 e 99.
**/
void riempi_vettori(float *vettori, int Nr_vet_elem, int Nr_vet_comp)
{
for (int i = 0; i < Nr_vet_elem; i++)
for(int j = 0; j < Nr_vet_comp; j++)
vettori[i * Nr_vet_comp + j] = i * 2 + j; //j % 4; //
}
/**
* Funzione che crea dei vettori contenente i valori significativi su cui
* calcolare la norma 2 al quadrato.
**/
void crea_vettori_termini_noti(int *vettori, int Nr_vet_elem, int Nr_vet_comp)
{
for (int i = 0; i < Nr_vet_elem; i++)
for(int j = 0; j < Nr_vet_comp; j++)
vettori[i * Nr_vet_comp + j] = (j+1)*3;
}
/**
* Funzione che crea un vettore contenente il numero di valori significative.
**/
void crea_vettori_posizioni(int *vettore, int Nr_vet_elem, int numero_val)
{
for (int i = 0; i < Nr_vet_elem; i++)
vettore[i] = numero_val;
}
/**
* kernel per il calcolo delle norme al quadrato dei vettori.
**/
__global__ void Kernel_norme(float *Vd, float *Nd, int *Vp, int *Vnp, int N, int C, int nr_max_val)
{
long int x = threadIdx.x + blockIdx.x * blockDim.x;
int pos;
if(x < N)
{
float norma = 0;
int Nr_val = Vnp[x];
for(int i = 0; i < Nr_val; i++)
{
pos = Vp[x * nr_max_val + i];
norma = norma + (Vd[x * C + pos] * Vd[x * C + pos]);
}
Nd[x] = norma;
}
}
/**
* Kernel per il calcolo del del guassiano, basato sul metodo utilizzato nel gpdt,
* modificato per l'utilizzo con la tecnologia CUDA.
**/
__global__ void Kernel_gaus(float *Vd, float *Ris, float *Nd, int N, int C, int dim_indici, int *ind, float sigma, int *Vp, int *Vnp, int nr_max_val)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int j;
int pos;
int tmp_ind;
float gaus;
for ( ; x < N ; x+=blockDim.x * gridDim.x)
{
for( ; y < dim_indici; y+=blockDim.y * gridDim.y)
{
tmp_ind = ind[y];
gaus = 0.0;
int Nr_val = Vnp[x];
for(j = 0; j < Nr_val; j++)
{
pos = Vp[x * nr_max_val + j];
gaus = gaus + (Vd[x * C + pos] * Vd[tmp_ind * C + pos]);
}
gaus = - 2.0*gaus +Nd[x] + Nd[tmp_ind];
gaus = (exp(-gaus*sigma));
//Ris[x * dim_indici + y] = gaus;
Ris[y * N + x] = gaus;
}
}
}
/**
* Kernel per il calcolo del kernel lineare
* modificato per l'utilizzo con la tecnologia CUDA.
**/
__global__ void Kernel_lineare(float *Vd, float *Ris, int N, int C, int dim_indici, int *ind, int *Vp, int *Vnp, int nr_max_val)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int j;
int pos;
int tmp_ind;
float lin;
for ( ; x < N ; x+=blockDim.x * gridDim.x)
{
for( ; y < dim_indici; y+=blockDim.y * gridDim.y)
{
tmp_ind = ind[y];
lin = 0.0;
int Nr_val = Vnp[x];
for(j = 0; j < Nr_val; j++)
{
pos = Vp[x * nr_max_val + j];
lin = lin + (Vd[x * C + pos] * Vd[tmp_ind * C + pos]);
}
//Ris[x * dim_indici + y] = lin;
Ris[y * N + x ] = lin;
}
}
}
/**
* Kernel per il calcolo del kernel lineare
* modificato per l'utilizzo con la tecnologia CUDA.
**/
__global__ void Kernel_polimoniale(float *Vd, float *Ris, int N, int C, int dim_indici, int *ind, int *Vp, int *Vnp, int nr_max_val, int s)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int j;
int pos;
int tmp_ind;
float pol;
float tmp;
for ( ; x < N ; x+=blockDim.x * gridDim.x)
{
for( ; y < dim_indici; y+=blockDim.y * gridDim.y)
{
tmp_ind = ind[y];
tmp = 1.0;
pol = 0.0;
int Nr_val = Vnp[x];
for(j = 0; j < Nr_val; j++)
{
pos = Vp[x * nr_max_val + j];
pol = pol + (Vd[x * C + pos] * Vd[tmp_ind * C + pos]);
}
pol = pol + 1;
for(j = 0; j < s; j++)
{
tmp = tmp * pol;
}
//Ris[x * dim_indici + y] = tmp;
Ris[y * N + x ] = tmp;
}
}
}
int main(int argc, char** argv)
{
/**
* Variabile contenente la percentuale dei valori significativi
* all'interno dei vettori.
**/
float perc_val_noti= 1.0 - 0.82;
/**
* Matrice contenente i vettori da cui calcolare la differeza
* per calcolarne le norme.
* Il numero di vettori e la dimensione degli stessi viene definita
* dall'utente.
**/
float *vettori;
/**
* Matrice contenente le posizioni all'interno del vettore contenente
* le posizioni dei valori significativi.
**/
int *vettore_posizioni;
/**
* Vettore contenente il numero di valori non nulli nel vettore.
**/
int *vett_numero_posizioni;
/**
* vettore contenente le norme 2 al quadreato dei vettori.
**/
float *vett_norme;
/**
* Matrice contenente i risultati.
**/
float *risultati;
/**
*
**/
int *indici;
/**
* Tempo impiegato per il calcolo
**/
float elapsedTime;
cudaEvent_t start, stop;
//nr di vettori e di elementi.
int Nr_vet_elem = atoi(argv[1]);
int Nr_vet_comp = atoi(argv[2]);
//Numero di righe da calcolare.
int Nr_righe = atoi(argv[3]);
/**
* Numero per la selezione del kernel.
* 1 = kernel lineare.
* 2 = kernel polimoniale.
* 3 = kernel gaussiano.
**/
int sel_kernel = atoi(argv[4]);
/**
* Sigma della funzione gaussiana.
**/
//float sigma = atoi(argv[5]);
//sigma = (1.0/(2.0*sigma*sigma));
//Copia per il device.
float *Vd;
int *Vp;
int *Vnp;
float *Nd;
float *Ris;
int *ind;
//Variabili per il controllo della memoria disponibile.
size_t free_byte;
size_t total_byte;
/**
* Variabile contenente il numero dei valori significativi.
**/
int numero_val_significativi = Nr_vet_comp * perc_val_noti;
//Spazio necessario per l'allocazione dei vettori.
int tot_vett_size = Nr_vet_elem * Nr_vet_comp * sizeof(float);
//Spazio necessario per l'allocazione della Matrice dei risultati.
int norme_size = Nr_vet_elem * sizeof(float);
//Spazio necessario per l'allocazione della Matrice delle posizioni.
int vett_pos_size = Nr_vet_elem * numero_val_significativi * sizeof(int);
//Spazio necessario per l'allocazione del vettore con il numero dei valori significativi.
int vett_nrpos_size = Nr_vet_elem * sizeof(int);
//Spazio necessario per l'allocazione di una colonna.
int col_size = Nr_vet_elem * sizeof(float);
//Allocazione.
vettori = (float*)malloc(tot_vett_size);
vett_norme = (float*)malloc(norme_size);
vettore_posizioni = (int*)malloc(vett_pos_size);
vett_numero_posizioni = (int*)malloc(vett_nrpos_size);
//Allocazione nel device.
cudaMalloc((void **)&Vd, tot_vett_size);
cudaMalloc((void **)&Nd, norme_size);
cudaMalloc((void **)&Vp, vett_pos_size);
cudaMalloc((void **)&Vnp, vett_nrpos_size);
srand(time(0));
//Riempimento dei vettori.
riempi_vettori(vettori, Nr_vet_elem, Nr_vet_comp);
//Riempimento dei vettori delle posizioni.
crea_vettori_termini_noti(vettore_posizioni, Nr_vet_elem, numero_val_significativi);
//Riempimento del vettore contenente il numero dei valori significativi.
crea_vettori_posizioni(vett_numero_posizioni, Nr_vet_elem, numero_val_significativi);
//trasferimento dei vettori nel device.
cudaMemcpy(Vd, vettori, tot_vett_size, cudaMemcpyHostToDevice);
//trasferimento dei vettori delle posizioni nel device.
cudaMemcpy(Vp, vettore_posizioni, vett_pos_size, cudaMemcpyHostToDevice);
//trasferimento del vettore conentente il numero di valori all'interno di ogni singolo vettore.
cudaMemcpy(Vnp, vett_numero_posizioni, vett_nrpos_size, cudaMemcpyHostToDevice);
cudaMemGetInfo( &free_byte, &total_byte );
int col_ospitabili_mem = (free_byte*0.7)/col_size;
int contatore = 0;
/**
* Valori impostati per ottimizzare il funzionamento del device.
* Questi valori sono basati sull'utilizzo di una Nvidia 230m.
**/
int dimXX =4;
int dimYY =128;
/**
* Numero di colonne ospitabili calcolabili dal kernel contemporaneamente.
* Purtroppo a causa del fatto che il kernel CUDA fallisca in automatico
* se impiega più di 5 secondi per il calcolo, è necessario inserire un
* limitatore per il calcolo.
* Questo valore è basato sull'utilizzo di una Nvidia 230m.
**/
int col_ospitabili = 200;
if (col_ospitabili > Nr_righe)
{
col_ospitabili = Nr_righe;
}
if (col_ospitabili > col_ospitabili_mem)
{
col_ospitabili = col_ospitabili_mem;
}
int numero_cicli = Nr_righe/col_ospitabili;
cout<<"Numero cicli necessari: "<<numero_cicli<<endl;
int risultati_size = Nr_righe * Nr_vet_elem * sizeof(float);
int indici_size = col_ospitabili * sizeof(int);
int risultati_part_size = col_ospitabili * Nr_vet_elem * sizeof(float);
risultati = (float*)malloc(risultati_size);
indici = (int*)malloc(indici_size);
int numSMs;
cudaDeviceGetAttribute(&numSMs, cudaDevAttrMultiProcessorCount, 0);
cudaMalloc((void **)&Ris, risultati_part_size);
cudaMalloc((void **)&ind, indici_size);
dim3 blockGridRows;
blockGridRows.x=Nr_vet_elem/dimXX + (Nr_vet_elem%dimXX== 0?0:1);;
blockGridRows.y=col_ospitabili/dimYY + (col_ospitabili%dimYY== 0?0:1);
dim3 threadBlockRows;
threadBlockRows.x=dimXX;
threadBlockRows.y=dimYY;
cout<<"Memoria allocata, griglie definite:"<<endl;
cout<<"blockGridRows.x: "<<blockGridRows.x<<endl;
cout<<"blockGridRows.y: "<<blockGridRows.y<<endl;
cout<<"threadBlockRows.x: "<<threadBlockRows.x<<endl;
cout<<"threadBlockRows.y: "<<threadBlockRows.y<<endl;
int cicle_dim = col_ospitabili * Nr_vet_elem * sizeof(float);
dim3 blockGridRowsn(Nr_vet_elem, 1);
int resto;
cudaEventCreate(&start);
cudaEventRecord(start,0);
switch(sel_kernel){
case(1):{
//cout<<"Kernel Lineare\n";
for(int i = 0; i < numero_cicli; i++)
{
for (int kk = 0; kk < col_ospitabili; kk++)
{
indici[kk] = contatore + kk;
}
cudaMemcpy(ind, indici, indici_size, cudaMemcpyHostToDevice);
//__global__ void Kernel_lineare(float *Vd, float *Ris, int N, int C, int dim_indici, int *ind, int *Vp, int *Vnp, int nr_max_val)
Kernel_lineare<<< blockGridRows, threadBlockRows>>>(Vd, Ris, Nr_vet_elem, Nr_vet_comp, col_ospitabili, ind, Vp, Vnp, numero_val_significativi);
cudaMemcpy(risultati+(i*col_ospitabili*Nr_vet_elem), Ris, cicle_dim, cudaMemcpyDeviceToHost);
contatore = contatore + col_ospitabili;
}
resto = Nr_righe - contatore;
if (resto > 0)
{
for (int kk = 0; kk < resto; kk++)
{
indici[kk] = contatore + kk;
}
cudaMemcpy(ind, indici, indici_size, cudaMemcpyHostToDevice);
Kernel_lineare<<< blockGridRows, threadBlockRows>>>(Vd, Ris, Nr_vet_elem, Nr_vet_comp, resto, ind, Vp, Vnp, numero_val_significativi);
cudaMemcpy(risultati+(numero_cicli)*(col_ospitabili*Nr_vet_elem), Ris, resto * Nr_vet_elem * sizeof(float), cudaMemcpyDeviceToHost);
}
break;
}
case(2):{
//cout<<"Kernel Polimoniale\n";
/**
* Grado del kernel.
**/
int grado = atoi(argv[5]);
for(int i = 0; i < numero_cicli; i++)
{
for (int kk = 0; kk < col_ospitabili; kk++)
{
indici[kk] = contatore + kk;
}
cudaMemcpy(ind, indici, indici_size, cudaMemcpyHostToDevice);
//__global__ void Kernel_polimoniale(float *Vd, float *Ris, int N, int C, int dim_indici, int *ind, int *Vp, int *Vnp, int nr_max_val, int s)
Kernel_polimoniale<<< blockGridRows, threadBlockRows>>>(Vd, Ris, Nr_vet_elem, Nr_vet_comp, col_ospitabili, ind, Vp, Vnp, numero_val_significativi,grado);
cudaMemcpy(risultati+(i*col_ospitabili*Nr_vet_elem), Ris, cicle_dim, cudaMemcpyDeviceToHost);
contatore = contatore + col_ospitabili;
}
resto = Nr_righe - contatore;
if (resto > 0)
{
for (int kk = 0; kk < resto; kk++)
{
indici[kk] = contatore + kk;
}
cudaMemcpy(ind, indici, indici_size, cudaMemcpyHostToDevice);
Kernel_polimoniale<<< blockGridRows, threadBlockRows>>>(Vd, Ris, Nr_vet_elem, Nr_vet_comp, resto, ind, Vp, Vnp, numero_val_significativi,grado);
cudaMemcpy(risultati+(numero_cicli)*(col_ospitabili*Nr_vet_elem), Ris, resto * Nr_vet_elem * sizeof(float), cudaMemcpyDeviceToHost);
}
break;
}
case(3):{
//cout<<"Kernel gaussiano\n";
/**
* Sigma della funzione gaussiana.
**/
float sigma = atof(argv[5]);
sigma = (1.0/(2.0*sigma*sigma));
//calcolo norme.
Kernel_norme<<< blockGridRowsn, 256 >>>(Vd, Nd, Vp, Vnp, Nr_vet_elem, Nr_vet_comp, numero_val_significativi);
//calcolo kernel
for(int i = 0; i < numero_cicli; i++)
{
for (int kk = 0; kk < col_ospitabili; kk++)
{
indici[kk] = contatore + kk;
}
cudaMemcpy(ind, indici, indici_size, cudaMemcpyHostToDevice);
//Kernel_gaus(float *Vd, float *Ris, float *Nd, int N, int C, int dim_indici, int *ind, float sigma, float *Vp, float *Vnp)
Kernel_gaus<<< blockGridRows, threadBlockRows>>>(Vd, Ris, Nd, Nr_vet_elem, Nr_vet_comp, col_ospitabili, ind, sigma, Vp, Vnp, numero_val_significativi);
cudaMemcpy(risultati+(i*col_ospitabili*Nr_vet_elem), Ris, cicle_dim, cudaMemcpyDeviceToHost);
contatore = contatore + col_ospitabili;
}
resto = Nr_righe - contatore;
if (resto > 0)
{
for (int kk = 0; kk < resto; kk++)
{
indici[kk] = contatore + kk;
}
cudaMemcpy(ind, indici, indici_size, cudaMemcpyHostToDevice);
Kernel_gaus<<< blockGridRows, threadBlockRows>>>(Vd, Ris, Nd, Nr_vet_elem, Nr_vet_comp, resto, ind, sigma, Vp, Vnp, numero_val_significativi);
cudaMemcpy(risultati+(numero_cicli)*(col_ospitabili*Nr_vet_elem), Ris, resto * Nr_vet_elem * sizeof(float), cudaMemcpyDeviceToHost);
}
break;
}
default:
{
cout<<"Scelta non valida.\n";
cout<<"4° argomento non esistente.\n";
cout<<"1 = kernel lineare\t2 = kernel polimoniale\t 3 = kernel gaussiano\n";
break;
}
}
cudaEventCreate(&stop);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start,stop);
cout<<"Tempo totale:\t"<<elapsedTime/1000<<" secondi\n";
/*for (int i = 0; i < Nr_vet_elem*Nr_righe; i++)
{
cout<<risultati[i]<<endl;
}*/
free(vettori);
free(vett_norme);
free(vettore_posizioni);
free(vett_numero_posizioni);
free(indici);
free(risultati);
cudaFree(Vd);
cudaFree(Vp);
cudaFree(Vnp);
cudaFree(Nd);
cudaFree(ind);
cudaFree(Ris);
return 0;
} | /**
* Programma che simula il comportamento del gpdt per
* la risoluzione di un kernel di una serie di
* valori di dimensione variabile utilizzando la
* tecnologia cuda.
* compilare con:
* nvcc -o simil_gpdt_si_cuda simil_gpdt_si_cuda.cu
* lanciare con:
* ./simil_gpdt_si_cuda [numero vettori] [numero componenti] [numero di righe da calcolare] [tipo di kernel] [grado(int)/sigma(float)]
**/
#include <iostream>
#include <ctime>
#include <cstdlib>
#include <cstdio>
#include <math.h>
#include <hip/hip_runtime.h>
using namespace std;
/**
* Funzione che riempie i vettori con numeri
* casuali compresi tra 0 e 99.
**/
void riempi_vettori(float *vettori, int Nr_vet_elem, int Nr_vet_comp)
{
for (int i = 0; i < Nr_vet_elem; i++)
for(int j = 0; j < Nr_vet_comp; j++)
vettori[i * Nr_vet_comp + j] = i * 2 + j; //j % 4; //
}
/**
* Funzione che crea dei vettori contenente i valori significativi su cui
* calcolare la norma 2 al quadrato.
**/
void crea_vettori_termini_noti(int *vettori, int Nr_vet_elem, int Nr_vet_comp)
{
for (int i = 0; i < Nr_vet_elem; i++)
for(int j = 0; j < Nr_vet_comp; j++)
vettori[i * Nr_vet_comp + j] = (j+1)*3;
}
/**
* Funzione che crea un vettore contenente il numero di valori significative.
**/
void crea_vettori_posizioni(int *vettore, int Nr_vet_elem, int numero_val)
{
for (int i = 0; i < Nr_vet_elem; i++)
vettore[i] = numero_val;
}
/**
* kernel per il calcolo delle norme al quadrato dei vettori.
**/
__global__ void Kernel_norme(float *Vd, float *Nd, int *Vp, int *Vnp, int N, int C, int nr_max_val)
{
long int x = threadIdx.x + blockIdx.x * blockDim.x;
int pos;
if(x < N)
{
float norma = 0;
int Nr_val = Vnp[x];
for(int i = 0; i < Nr_val; i++)
{
pos = Vp[x * nr_max_val + i];
norma = norma + (Vd[x * C + pos] * Vd[x * C + pos]);
}
Nd[x] = norma;
}
}
/**
* Kernel per il calcolo del del guassiano, basato sul metodo utilizzato nel gpdt,
* modificato per l'utilizzo con la tecnologia CUDA.
**/
__global__ void Kernel_gaus(float *Vd, float *Ris, float *Nd, int N, int C, int dim_indici, int *ind, float sigma, int *Vp, int *Vnp, int nr_max_val)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int j;
int pos;
int tmp_ind;
float gaus;
for ( ; x < N ; x+=blockDim.x * gridDim.x)
{
for( ; y < dim_indici; y+=blockDim.y * gridDim.y)
{
tmp_ind = ind[y];
gaus = 0.0;
int Nr_val = Vnp[x];
for(j = 0; j < Nr_val; j++)
{
pos = Vp[x * nr_max_val + j];
gaus = gaus + (Vd[x * C + pos] * Vd[tmp_ind * C + pos]);
}
gaus = - 2.0*gaus +Nd[x] + Nd[tmp_ind];
gaus = (exp(-gaus*sigma));
//Ris[x * dim_indici + y] = gaus;
Ris[y * N + x] = gaus;
}
}
}
/**
* Kernel per il calcolo del kernel lineare
* modificato per l'utilizzo con la tecnologia CUDA.
**/
__global__ void Kernel_lineare(float *Vd, float *Ris, int N, int C, int dim_indici, int *ind, int *Vp, int *Vnp, int nr_max_val)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int j;
int pos;
int tmp_ind;
float lin;
for ( ; x < N ; x+=blockDim.x * gridDim.x)
{
for( ; y < dim_indici; y+=blockDim.y * gridDim.y)
{
tmp_ind = ind[y];
lin = 0.0;
int Nr_val = Vnp[x];
for(j = 0; j < Nr_val; j++)
{
pos = Vp[x * nr_max_val + j];
lin = lin + (Vd[x * C + pos] * Vd[tmp_ind * C + pos]);
}
//Ris[x * dim_indici + y] = lin;
Ris[y * N + x ] = lin;
}
}
}
/**
* Kernel per il calcolo del kernel lineare
* modificato per l'utilizzo con la tecnologia CUDA.
**/
__global__ void Kernel_polimoniale(float *Vd, float *Ris, int N, int C, int dim_indici, int *ind, int *Vp, int *Vnp, int nr_max_val, int s)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int j;
int pos;
int tmp_ind;
float pol;
float tmp;
for ( ; x < N ; x+=blockDim.x * gridDim.x)
{
for( ; y < dim_indici; y+=blockDim.y * gridDim.y)
{
tmp_ind = ind[y];
tmp = 1.0;
pol = 0.0;
int Nr_val = Vnp[x];
for(j = 0; j < Nr_val; j++)
{
pos = Vp[x * nr_max_val + j];
pol = pol + (Vd[x * C + pos] * Vd[tmp_ind * C + pos]);
}
pol = pol + 1;
for(j = 0; j < s; j++)
{
tmp = tmp * pol;
}
//Ris[x * dim_indici + y] = tmp;
Ris[y * N + x ] = tmp;
}
}
}
int main(int argc, char** argv)
{
/**
* Variabile contenente la percentuale dei valori significativi
* all'interno dei vettori.
**/
float perc_val_noti= 1.0 - 0.82;
/**
* Matrice contenente i vettori da cui calcolare la differeza
* per calcolarne le norme.
* Il numero di vettori e la dimensione degli stessi viene definita
* dall'utente.
**/
float *vettori;
/**
* Matrice contenente le posizioni all'interno del vettore contenente
* le posizioni dei valori significativi.
**/
int *vettore_posizioni;
/**
* Vettore contenente il numero di valori non nulli nel vettore.
**/
int *vett_numero_posizioni;
/**
* vettore contenente le norme 2 al quadreato dei vettori.
**/
float *vett_norme;
/**
* Matrice contenente i risultati.
**/
float *risultati;
/**
*
**/
int *indici;
/**
* Tempo impiegato per il calcolo
**/
float elapsedTime;
hipEvent_t start, stop;
//nr di vettori e di elementi.
int Nr_vet_elem = atoi(argv[1]);
int Nr_vet_comp = atoi(argv[2]);
//Numero di righe da calcolare.
int Nr_righe = atoi(argv[3]);
/**
* Numero per la selezione del kernel.
* 1 = kernel lineare.
* 2 = kernel polimoniale.
* 3 = kernel gaussiano.
**/
int sel_kernel = atoi(argv[4]);
/**
* Sigma della funzione gaussiana.
**/
//float sigma = atoi(argv[5]);
//sigma = (1.0/(2.0*sigma*sigma));
//Copia per il device.
float *Vd;
int *Vp;
int *Vnp;
float *Nd;
float *Ris;
int *ind;
//Variabili per il controllo della memoria disponibile.
size_t free_byte;
size_t total_byte;
/**
* Variabile contenente il numero dei valori significativi.
**/
int numero_val_significativi = Nr_vet_comp * perc_val_noti;
//Spazio necessario per l'allocazione dei vettori.
int tot_vett_size = Nr_vet_elem * Nr_vet_comp * sizeof(float);
//Spazio necessario per l'allocazione della Matrice dei risultati.
int norme_size = Nr_vet_elem * sizeof(float);
//Spazio necessario per l'allocazione della Matrice delle posizioni.
int vett_pos_size = Nr_vet_elem * numero_val_significativi * sizeof(int);
//Spazio necessario per l'allocazione del vettore con il numero dei valori significativi.
int vett_nrpos_size = Nr_vet_elem * sizeof(int);
//Spazio necessario per l'allocazione di una colonna.
int col_size = Nr_vet_elem * sizeof(float);
//Allocazione.
vettori = (float*)malloc(tot_vett_size);
vett_norme = (float*)malloc(norme_size);
vettore_posizioni = (int*)malloc(vett_pos_size);
vett_numero_posizioni = (int*)malloc(vett_nrpos_size);
//Allocazione nel device.
hipMalloc((void **)&Vd, tot_vett_size);
hipMalloc((void **)&Nd, norme_size);
hipMalloc((void **)&Vp, vett_pos_size);
hipMalloc((void **)&Vnp, vett_nrpos_size);
srand(time(0));
//Riempimento dei vettori.
riempi_vettori(vettori, Nr_vet_elem, Nr_vet_comp);
//Riempimento dei vettori delle posizioni.
crea_vettori_termini_noti(vettore_posizioni, Nr_vet_elem, numero_val_significativi);
//Riempimento del vettore contenente il numero dei valori significativi.
crea_vettori_posizioni(vett_numero_posizioni, Nr_vet_elem, numero_val_significativi);
//trasferimento dei vettori nel device.
hipMemcpy(Vd, vettori, tot_vett_size, hipMemcpyHostToDevice);
//trasferimento dei vettori delle posizioni nel device.
hipMemcpy(Vp, vettore_posizioni, vett_pos_size, hipMemcpyHostToDevice);
//trasferimento del vettore conentente il numero di valori all'interno di ogni singolo vettore.
hipMemcpy(Vnp, vett_numero_posizioni, vett_nrpos_size, hipMemcpyHostToDevice);
hipMemGetInfo( &free_byte, &total_byte );
int col_ospitabili_mem = (free_byte*0.7)/col_size;
int contatore = 0;
/**
* Valori impostati per ottimizzare il funzionamento del device.
* Questi valori sono basati sull'utilizzo di una Nvidia 230m.
**/
int dimXX =4;
int dimYY =128;
/**
* Numero di colonne ospitabili calcolabili dal kernel contemporaneamente.
* Purtroppo a causa del fatto che il kernel CUDA fallisca in automatico
* se impiega più di 5 secondi per il calcolo, è necessario inserire un
* limitatore per il calcolo.
* Questo valore è basato sull'utilizzo di una Nvidia 230m.
**/
int col_ospitabili = 200;
if (col_ospitabili > Nr_righe)
{
col_ospitabili = Nr_righe;
}
if (col_ospitabili > col_ospitabili_mem)
{
col_ospitabili = col_ospitabili_mem;
}
int numero_cicli = Nr_righe/col_ospitabili;
cout<<"Numero cicli necessari: "<<numero_cicli<<endl;
int risultati_size = Nr_righe * Nr_vet_elem * sizeof(float);
int indici_size = col_ospitabili * sizeof(int);
int risultati_part_size = col_ospitabili * Nr_vet_elem * sizeof(float);
risultati = (float*)malloc(risultati_size);
indici = (int*)malloc(indici_size);
int numSMs;
hipDeviceGetAttribute(&numSMs, hipDeviceAttributeMultiprocessorCount, 0);
hipMalloc((void **)&Ris, risultati_part_size);
hipMalloc((void **)&ind, indici_size);
dim3 blockGridRows;
blockGridRows.x=Nr_vet_elem/dimXX + (Nr_vet_elem%dimXX== 0?0:1);;
blockGridRows.y=col_ospitabili/dimYY + (col_ospitabili%dimYY== 0?0:1);
dim3 threadBlockRows;
threadBlockRows.x=dimXX;
threadBlockRows.y=dimYY;
cout<<"Memoria allocata, griglie definite:"<<endl;
cout<<"blockGridRows.x: "<<blockGridRows.x<<endl;
cout<<"blockGridRows.y: "<<blockGridRows.y<<endl;
cout<<"threadBlockRows.x: "<<threadBlockRows.x<<endl;
cout<<"threadBlockRows.y: "<<threadBlockRows.y<<endl;
int cicle_dim = col_ospitabili * Nr_vet_elem * sizeof(float);
dim3 blockGridRowsn(Nr_vet_elem, 1);
int resto;
hipEventCreate(&start);
hipEventRecord(start,0);
switch(sel_kernel){
case(1):{
//cout<<"Kernel Lineare\n";
for(int i = 0; i < numero_cicli; i++)
{
for (int kk = 0; kk < col_ospitabili; kk++)
{
indici[kk] = contatore + kk;
}
hipMemcpy(ind, indici, indici_size, hipMemcpyHostToDevice);
//__global__ void Kernel_lineare(float *Vd, float *Ris, int N, int C, int dim_indici, int *ind, int *Vp, int *Vnp, int nr_max_val)
Kernel_lineare<<< blockGridRows, threadBlockRows>>>(Vd, Ris, Nr_vet_elem, Nr_vet_comp, col_ospitabili, ind, Vp, Vnp, numero_val_significativi);
hipMemcpy(risultati+(i*col_ospitabili*Nr_vet_elem), Ris, cicle_dim, hipMemcpyDeviceToHost);
contatore = contatore + col_ospitabili;
}
resto = Nr_righe - contatore;
if (resto > 0)
{
for (int kk = 0; kk < resto; kk++)
{
indici[kk] = contatore + kk;
}
hipMemcpy(ind, indici, indici_size, hipMemcpyHostToDevice);
Kernel_lineare<<< blockGridRows, threadBlockRows>>>(Vd, Ris, Nr_vet_elem, Nr_vet_comp, resto, ind, Vp, Vnp, numero_val_significativi);
hipMemcpy(risultati+(numero_cicli)*(col_ospitabili*Nr_vet_elem), Ris, resto * Nr_vet_elem * sizeof(float), hipMemcpyDeviceToHost);
}
break;
}
case(2):{
//cout<<"Kernel Polimoniale\n";
/**
* Grado del kernel.
**/
int grado = atoi(argv[5]);
for(int i = 0; i < numero_cicli; i++)
{
for (int kk = 0; kk < col_ospitabili; kk++)
{
indici[kk] = contatore + kk;
}
hipMemcpy(ind, indici, indici_size, hipMemcpyHostToDevice);
//__global__ void Kernel_polimoniale(float *Vd, float *Ris, int N, int C, int dim_indici, int *ind, int *Vp, int *Vnp, int nr_max_val, int s)
Kernel_polimoniale<<< blockGridRows, threadBlockRows>>>(Vd, Ris, Nr_vet_elem, Nr_vet_comp, col_ospitabili, ind, Vp, Vnp, numero_val_significativi,grado);
hipMemcpy(risultati+(i*col_ospitabili*Nr_vet_elem), Ris, cicle_dim, hipMemcpyDeviceToHost);
contatore = contatore + col_ospitabili;
}
resto = Nr_righe - contatore;
if (resto > 0)
{
for (int kk = 0; kk < resto; kk++)
{
indici[kk] = contatore + kk;
}
hipMemcpy(ind, indici, indici_size, hipMemcpyHostToDevice);
Kernel_polimoniale<<< blockGridRows, threadBlockRows>>>(Vd, Ris, Nr_vet_elem, Nr_vet_comp, resto, ind, Vp, Vnp, numero_val_significativi,grado);
hipMemcpy(risultati+(numero_cicli)*(col_ospitabili*Nr_vet_elem), Ris, resto * Nr_vet_elem * sizeof(float), hipMemcpyDeviceToHost);
}
break;
}
case(3):{
//cout<<"Kernel gaussiano\n";
/**
* Sigma della funzione gaussiana.
**/
float sigma = atof(argv[5]);
sigma = (1.0/(2.0*sigma*sigma));
//calcolo norme.
Kernel_norme<<< blockGridRowsn, 256 >>>(Vd, Nd, Vp, Vnp, Nr_vet_elem, Nr_vet_comp, numero_val_significativi);
//calcolo kernel
for(int i = 0; i < numero_cicli; i++)
{
for (int kk = 0; kk < col_ospitabili; kk++)
{
indici[kk] = contatore + kk;
}
hipMemcpy(ind, indici, indici_size, hipMemcpyHostToDevice);
//Kernel_gaus(float *Vd, float *Ris, float *Nd, int N, int C, int dim_indici, int *ind, float sigma, float *Vp, float *Vnp)
Kernel_gaus<<< blockGridRows, threadBlockRows>>>(Vd, Ris, Nd, Nr_vet_elem, Nr_vet_comp, col_ospitabili, ind, sigma, Vp, Vnp, numero_val_significativi);
hipMemcpy(risultati+(i*col_ospitabili*Nr_vet_elem), Ris, cicle_dim, hipMemcpyDeviceToHost);
contatore = contatore + col_ospitabili;
}
resto = Nr_righe - contatore;
if (resto > 0)
{
for (int kk = 0; kk < resto; kk++)
{
indici[kk] = contatore + kk;
}
hipMemcpy(ind, indici, indici_size, hipMemcpyHostToDevice);
Kernel_gaus<<< blockGridRows, threadBlockRows>>>(Vd, Ris, Nd, Nr_vet_elem, Nr_vet_comp, resto, ind, sigma, Vp, Vnp, numero_val_significativi);
hipMemcpy(risultati+(numero_cicli)*(col_ospitabili*Nr_vet_elem), Ris, resto * Nr_vet_elem * sizeof(float), hipMemcpyDeviceToHost);
}
break;
}
default:
{
cout<<"Scelta non valida.\n";
cout<<"4° argomento non esistente.\n";
cout<<"1 = kernel lineare\t2 = kernel polimoniale\t 3 = kernel gaussiano\n";
break;
}
}
hipEventCreate(&stop);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start,stop);
cout<<"Tempo totale:\t"<<elapsedTime/1000<<" secondi\n";
/*for (int i = 0; i < Nr_vet_elem*Nr_righe; i++)
{
cout<<risultati[i]<<endl;
}*/
free(vettori);
free(vett_norme);
free(vettore_posizioni);
free(vett_numero_posizioni);
free(indici);
free(risultati);
hipFree(Vd);
hipFree(Vp);
hipFree(Vnp);
hipFree(Nd);
hipFree(ind);
hipFree(Ris);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /**
* Programma che simula il comportamento del gpdt per
* la risoluzione di un kernel di una serie di
* valori di dimensione variabile utilizzando la
* tecnologia cuda.
* compilare con:
* nvcc -o simil_gpdt_si_cuda simil_gpdt_si_cuda.cu
* lanciare con:
* ./simil_gpdt_si_cuda [numero vettori] [numero componenti] [numero di righe da calcolare] [tipo di kernel] [grado(int)/sigma(float)]
**/
#include <iostream>
#include <ctime>
#include <cstdlib>
#include <cstdio>
#include <math.h>
#include <hip/hip_runtime.h>
using namespace std;
/**
* Funzione che riempie i vettori con numeri
* casuali compresi tra 0 e 99.
**/
void riempi_vettori(float *vettori, int Nr_vet_elem, int Nr_vet_comp)
{
for (int i = 0; i < Nr_vet_elem; i++)
for(int j = 0; j < Nr_vet_comp; j++)
vettori[i * Nr_vet_comp + j] = i * 2 + j; //j % 4; //
}
/**
* Funzione che crea dei vettori contenente i valori significativi su cui
* calcolare la norma 2 al quadrato.
**/
void crea_vettori_termini_noti(int *vettori, int Nr_vet_elem, int Nr_vet_comp)
{
for (int i = 0; i < Nr_vet_elem; i++)
for(int j = 0; j < Nr_vet_comp; j++)
vettori[i * Nr_vet_comp + j] = (j+1)*3;
}
/**
* Funzione che crea un vettore contenente il numero di valori significative.
**/
void crea_vettori_posizioni(int *vettore, int Nr_vet_elem, int numero_val)
{
for (int i = 0; i < Nr_vet_elem; i++)
vettore[i] = numero_val;
}
/**
* kernel per il calcolo delle norme al quadrato dei vettori.
**/
__global__ void Kernel_norme(float *Vd, float *Nd, int *Vp, int *Vnp, int N, int C, int nr_max_val)
{
long int x = threadIdx.x + blockIdx.x * blockDim.x;
int pos;
if(x < N)
{
float norma = 0;
int Nr_val = Vnp[x];
for(int i = 0; i < Nr_val; i++)
{
pos = Vp[x * nr_max_val + i];
norma = norma + (Vd[x * C + pos] * Vd[x * C + pos]);
}
Nd[x] = norma;
}
}
/**
* Kernel per il calcolo del del guassiano, basato sul metodo utilizzato nel gpdt,
* modificato per l'utilizzo con la tecnologia CUDA.
**/
__global__ void Kernel_gaus(float *Vd, float *Ris, float *Nd, int N, int C, int dim_indici, int *ind, float sigma, int *Vp, int *Vnp, int nr_max_val)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int j;
int pos;
int tmp_ind;
float gaus;
for ( ; x < N ; x+=blockDim.x * gridDim.x)
{
for( ; y < dim_indici; y+=blockDim.y * gridDim.y)
{
tmp_ind = ind[y];
gaus = 0.0;
int Nr_val = Vnp[x];
for(j = 0; j < Nr_val; j++)
{
pos = Vp[x * nr_max_val + j];
gaus = gaus + (Vd[x * C + pos] * Vd[tmp_ind * C + pos]);
}
gaus = - 2.0*gaus +Nd[x] + Nd[tmp_ind];
gaus = (exp(-gaus*sigma));
//Ris[x * dim_indici + y] = gaus;
Ris[y * N + x] = gaus;
}
}
}
/**
* Kernel per il calcolo del kernel lineare
* modificato per l'utilizzo con la tecnologia CUDA.
**/
__global__ void Kernel_lineare(float *Vd, float *Ris, int N, int C, int dim_indici, int *ind, int *Vp, int *Vnp, int nr_max_val)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int j;
int pos;
int tmp_ind;
float lin;
for ( ; x < N ; x+=blockDim.x * gridDim.x)
{
for( ; y < dim_indici; y+=blockDim.y * gridDim.y)
{
tmp_ind = ind[y];
lin = 0.0;
int Nr_val = Vnp[x];
for(j = 0; j < Nr_val; j++)
{
pos = Vp[x * nr_max_val + j];
lin = lin + (Vd[x * C + pos] * Vd[tmp_ind * C + pos]);
}
//Ris[x * dim_indici + y] = lin;
Ris[y * N + x ] = lin;
}
}
}
/**
* Kernel per il calcolo del kernel lineare
* modificato per l'utilizzo con la tecnologia CUDA.
**/
__global__ void Kernel_polimoniale(float *Vd, float *Ris, int N, int C, int dim_indici, int *ind, int *Vp, int *Vnp, int nr_max_val, int s)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int j;
int pos;
int tmp_ind;
float pol;
float tmp;
for ( ; x < N ; x+=blockDim.x * gridDim.x)
{
for( ; y < dim_indici; y+=blockDim.y * gridDim.y)
{
tmp_ind = ind[y];
tmp = 1.0;
pol = 0.0;
int Nr_val = Vnp[x];
for(j = 0; j < Nr_val; j++)
{
pos = Vp[x * nr_max_val + j];
pol = pol + (Vd[x * C + pos] * Vd[tmp_ind * C + pos]);
}
pol = pol + 1;
for(j = 0; j < s; j++)
{
tmp = tmp * pol;
}
//Ris[x * dim_indici + y] = tmp;
Ris[y * N + x ] = tmp;
}
}
}
int main(int argc, char** argv)
{
/**
* Variabile contenente la percentuale dei valori significativi
* all'interno dei vettori.
**/
float perc_val_noti= 1.0 - 0.82;
/**
* Matrice contenente i vettori da cui calcolare la differeza
* per calcolarne le norme.
* Il numero di vettori e la dimensione degli stessi viene definita
* dall'utente.
**/
float *vettori;
/**
* Matrice contenente le posizioni all'interno del vettore contenente
* le posizioni dei valori significativi.
**/
int *vettore_posizioni;
/**
* Vettore contenente il numero di valori non nulli nel vettore.
**/
int *vett_numero_posizioni;
/**
* vettore contenente le norme 2 al quadreato dei vettori.
**/
float *vett_norme;
/**
* Matrice contenente i risultati.
**/
float *risultati;
/**
*
**/
int *indici;
/**
* Tempo impiegato per il calcolo
**/
float elapsedTime;
hipEvent_t start, stop;
//nr di vettori e di elementi.
int Nr_vet_elem = atoi(argv[1]);
int Nr_vet_comp = atoi(argv[2]);
//Numero di righe da calcolare.
int Nr_righe = atoi(argv[3]);
/**
* Numero per la selezione del kernel.
* 1 = kernel lineare.
* 2 = kernel polimoniale.
* 3 = kernel gaussiano.
**/
int sel_kernel = atoi(argv[4]);
/**
* Sigma della funzione gaussiana.
**/
//float sigma = atoi(argv[5]);
//sigma = (1.0/(2.0*sigma*sigma));
//Copia per il device.
float *Vd;
int *Vp;
int *Vnp;
float *Nd;
float *Ris;
int *ind;
//Variabili per il controllo della memoria disponibile.
size_t free_byte;
size_t total_byte;
/**
* Variabile contenente il numero dei valori significativi.
**/
int numero_val_significativi = Nr_vet_comp * perc_val_noti;
//Spazio necessario per l'allocazione dei vettori.
int tot_vett_size = Nr_vet_elem * Nr_vet_comp * sizeof(float);
//Spazio necessario per l'allocazione della Matrice dei risultati.
int norme_size = Nr_vet_elem * sizeof(float);
//Spazio necessario per l'allocazione della Matrice delle posizioni.
int vett_pos_size = Nr_vet_elem * numero_val_significativi * sizeof(int);
//Spazio necessario per l'allocazione del vettore con il numero dei valori significativi.
int vett_nrpos_size = Nr_vet_elem * sizeof(int);
//Spazio necessario per l'allocazione di una colonna.
int col_size = Nr_vet_elem * sizeof(float);
//Allocazione.
vettori = (float*)malloc(tot_vett_size);
vett_norme = (float*)malloc(norme_size);
vettore_posizioni = (int*)malloc(vett_pos_size);
vett_numero_posizioni = (int*)malloc(vett_nrpos_size);
//Allocazione nel device.
hipMalloc((void **)&Vd, tot_vett_size);
hipMalloc((void **)&Nd, norme_size);
hipMalloc((void **)&Vp, vett_pos_size);
hipMalloc((void **)&Vnp, vett_nrpos_size);
srand(time(0));
//Riempimento dei vettori.
riempi_vettori(vettori, Nr_vet_elem, Nr_vet_comp);
//Riempimento dei vettori delle posizioni.
crea_vettori_termini_noti(vettore_posizioni, Nr_vet_elem, numero_val_significativi);
//Riempimento del vettore contenente il numero dei valori significativi.
crea_vettori_posizioni(vett_numero_posizioni, Nr_vet_elem, numero_val_significativi);
//trasferimento dei vettori nel device.
hipMemcpy(Vd, vettori, tot_vett_size, hipMemcpyHostToDevice);
//trasferimento dei vettori delle posizioni nel device.
hipMemcpy(Vp, vettore_posizioni, vett_pos_size, hipMemcpyHostToDevice);
//trasferimento del vettore conentente il numero di valori all'interno di ogni singolo vettore.
hipMemcpy(Vnp, vett_numero_posizioni, vett_nrpos_size, hipMemcpyHostToDevice);
hipMemGetInfo( &free_byte, &total_byte );
int col_ospitabili_mem = (free_byte*0.7)/col_size;
int contatore = 0;
/**
* Valori impostati per ottimizzare il funzionamento del device.
* Questi valori sono basati sull'utilizzo di una Nvidia 230m.
**/
int dimXX =4;
int dimYY =128;
/**
* Numero di colonne ospitabili calcolabili dal kernel contemporaneamente.
* Purtroppo a causa del fatto che il kernel CUDA fallisca in automatico
* se impiega più di 5 secondi per il calcolo, è necessario inserire un
* limitatore per il calcolo.
* Questo valore è basato sull'utilizzo di una Nvidia 230m.
**/
int col_ospitabili = 200;
if (col_ospitabili > Nr_righe)
{
col_ospitabili = Nr_righe;
}
if (col_ospitabili > col_ospitabili_mem)
{
col_ospitabili = col_ospitabili_mem;
}
int numero_cicli = Nr_righe/col_ospitabili;
cout<<"Numero cicli necessari: "<<numero_cicli<<endl;
int risultati_size = Nr_righe * Nr_vet_elem * sizeof(float);
int indici_size = col_ospitabili * sizeof(int);
int risultati_part_size = col_ospitabili * Nr_vet_elem * sizeof(float);
risultati = (float*)malloc(risultati_size);
indici = (int*)malloc(indici_size);
int numSMs;
hipDeviceGetAttribute(&numSMs, hipDeviceAttributeMultiprocessorCount, 0);
hipMalloc((void **)&Ris, risultati_part_size);
hipMalloc((void **)&ind, indici_size);
dim3 blockGridRows;
blockGridRows.x=Nr_vet_elem/dimXX + (Nr_vet_elem%dimXX== 0?0:1);;
blockGridRows.y=col_ospitabili/dimYY + (col_ospitabili%dimYY== 0?0:1);
dim3 threadBlockRows;
threadBlockRows.x=dimXX;
threadBlockRows.y=dimYY;
cout<<"Memoria allocata, griglie definite:"<<endl;
cout<<"blockGridRows.x: "<<blockGridRows.x<<endl;
cout<<"blockGridRows.y: "<<blockGridRows.y<<endl;
cout<<"threadBlockRows.x: "<<threadBlockRows.x<<endl;
cout<<"threadBlockRows.y: "<<threadBlockRows.y<<endl;
int cicle_dim = col_ospitabili * Nr_vet_elem * sizeof(float);
dim3 blockGridRowsn(Nr_vet_elem, 1);
int resto;
hipEventCreate(&start);
hipEventRecord(start,0);
switch(sel_kernel){
case(1):{
//cout<<"Kernel Lineare\n";
for(int i = 0; i < numero_cicli; i++)
{
for (int kk = 0; kk < col_ospitabili; kk++)
{
indici[kk] = contatore + kk;
}
hipMemcpy(ind, indici, indici_size, hipMemcpyHostToDevice);
//__global__ void Kernel_lineare(float *Vd, float *Ris, int N, int C, int dim_indici, int *ind, int *Vp, int *Vnp, int nr_max_val)
Kernel_lineare<<< blockGridRows, threadBlockRows>>>(Vd, Ris, Nr_vet_elem, Nr_vet_comp, col_ospitabili, ind, Vp, Vnp, numero_val_significativi);
hipMemcpy(risultati+(i*col_ospitabili*Nr_vet_elem), Ris, cicle_dim, hipMemcpyDeviceToHost);
contatore = contatore + col_ospitabili;
}
resto = Nr_righe - contatore;
if (resto > 0)
{
for (int kk = 0; kk < resto; kk++)
{
indici[kk] = contatore + kk;
}
hipMemcpy(ind, indici, indici_size, hipMemcpyHostToDevice);
Kernel_lineare<<< blockGridRows, threadBlockRows>>>(Vd, Ris, Nr_vet_elem, Nr_vet_comp, resto, ind, Vp, Vnp, numero_val_significativi);
hipMemcpy(risultati+(numero_cicli)*(col_ospitabili*Nr_vet_elem), Ris, resto * Nr_vet_elem * sizeof(float), hipMemcpyDeviceToHost);
}
break;
}
case(2):{
//cout<<"Kernel Polimoniale\n";
/**
* Grado del kernel.
**/
int grado = atoi(argv[5]);
for(int i = 0; i < numero_cicli; i++)
{
for (int kk = 0; kk < col_ospitabili; kk++)
{
indici[kk] = contatore + kk;
}
hipMemcpy(ind, indici, indici_size, hipMemcpyHostToDevice);
//__global__ void Kernel_polimoniale(float *Vd, float *Ris, int N, int C, int dim_indici, int *ind, int *Vp, int *Vnp, int nr_max_val, int s)
Kernel_polimoniale<<< blockGridRows, threadBlockRows>>>(Vd, Ris, Nr_vet_elem, Nr_vet_comp, col_ospitabili, ind, Vp, Vnp, numero_val_significativi,grado);
hipMemcpy(risultati+(i*col_ospitabili*Nr_vet_elem), Ris, cicle_dim, hipMemcpyDeviceToHost);
contatore = contatore + col_ospitabili;
}
resto = Nr_righe - contatore;
if (resto > 0)
{
for (int kk = 0; kk < resto; kk++)
{
indici[kk] = contatore + kk;
}
hipMemcpy(ind, indici, indici_size, hipMemcpyHostToDevice);
Kernel_polimoniale<<< blockGridRows, threadBlockRows>>>(Vd, Ris, Nr_vet_elem, Nr_vet_comp, resto, ind, Vp, Vnp, numero_val_significativi,grado);
hipMemcpy(risultati+(numero_cicli)*(col_ospitabili*Nr_vet_elem), Ris, resto * Nr_vet_elem * sizeof(float), hipMemcpyDeviceToHost);
}
break;
}
case(3):{
//cout<<"Kernel gaussiano\n";
/**
* Sigma della funzione gaussiana.
**/
float sigma = atof(argv[5]);
sigma = (1.0/(2.0*sigma*sigma));
//calcolo norme.
Kernel_norme<<< blockGridRowsn, 256 >>>(Vd, Nd, Vp, Vnp, Nr_vet_elem, Nr_vet_comp, numero_val_significativi);
//calcolo kernel
for(int i = 0; i < numero_cicli; i++)
{
for (int kk = 0; kk < col_ospitabili; kk++)
{
indici[kk] = contatore + kk;
}
hipMemcpy(ind, indici, indici_size, hipMemcpyHostToDevice);
//Kernel_gaus(float *Vd, float *Ris, float *Nd, int N, int C, int dim_indici, int *ind, float sigma, float *Vp, float *Vnp)
Kernel_gaus<<< blockGridRows, threadBlockRows>>>(Vd, Ris, Nd, Nr_vet_elem, Nr_vet_comp, col_ospitabili, ind, sigma, Vp, Vnp, numero_val_significativi);
hipMemcpy(risultati+(i*col_ospitabili*Nr_vet_elem), Ris, cicle_dim, hipMemcpyDeviceToHost);
contatore = contatore + col_ospitabili;
}
resto = Nr_righe - contatore;
if (resto > 0)
{
for (int kk = 0; kk < resto; kk++)
{
indici[kk] = contatore + kk;
}
hipMemcpy(ind, indici, indici_size, hipMemcpyHostToDevice);
Kernel_gaus<<< blockGridRows, threadBlockRows>>>(Vd, Ris, Nd, Nr_vet_elem, Nr_vet_comp, resto, ind, sigma, Vp, Vnp, numero_val_significativi);
hipMemcpy(risultati+(numero_cicli)*(col_ospitabili*Nr_vet_elem), Ris, resto * Nr_vet_elem * sizeof(float), hipMemcpyDeviceToHost);
}
break;
}
default:
{
cout<<"Scelta non valida.\n";
cout<<"4° argomento non esistente.\n";
cout<<"1 = kernel lineare\t2 = kernel polimoniale\t 3 = kernel gaussiano\n";
break;
}
}
hipEventCreate(&stop);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start,stop);
cout<<"Tempo totale:\t"<<elapsedTime/1000<<" secondi\n";
/*for (int i = 0; i < Nr_vet_elem*Nr_righe; i++)
{
cout<<risultati[i]<<endl;
}*/
free(vettori);
free(vett_norme);
free(vettore_posizioni);
free(vett_numero_posizioni);
free(indici);
free(risultati);
hipFree(Vd);
hipFree(Vp);
hipFree(Vnp);
hipFree(Nd);
hipFree(ind);
hipFree(Ris);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12Kernel_normePfS_PiS0_iii
.globl _Z12Kernel_normePfS_PiS0_iii
.p2align 8
.type _Z12Kernel_normePfS_PiS0_iii,@function
_Z12Kernel_normePfS_PiS0_iii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x3c
s_load_b32 s2, s[0:1], 0x20
v_mov_b32_e32 v5, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
v_mov_b32_e32 v2, v5
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_6
s_load_b64 s[2:3], s[0:1], 0x18
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_mov_b32 s4, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_mov_b32 s3, exec_lo
global_load_b32 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e32 0, v0
s_cbranch_execz .LBB0_5
s_clause 0x2
s_load_b64 s[6:7], s[0:1], 0x24
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b64 s[10:11], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, s7, 0
v_mad_u64_u32 v[5:6], null, v1, s6, 0
s_ashr_i32 s2, s7, 31
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[7:8], null, v1, s2, v[4:5]
s_ashr_i32 s2, s6, 31
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[8:9], null, v1, s2, v[6:7]
v_mov_b32_e32 v4, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v6, v8
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v3, vcc_lo, s8, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
v_add_co_u32 v6, vcc_lo, s10, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v7, vcc_lo
.p2align 6
.LBB0_3:
global_load_b32 v8, v[3:4], off
v_add_nc_u32_e32 v0, -1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s2, 0, v0
s_or_b32 s4, s2, s4
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v9, 31, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_add_co_u32 v8, vcc_lo, v6, v8
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v9, vcc_lo, v7, v9, vcc_lo
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
global_load_b32 v8, v[8:9], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v5, v8, v8
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s4
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v5, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12Kernel_normePfS_PiS0_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12Kernel_normePfS_PiS0_iii, .Lfunc_end0-_Z12Kernel_normePfS_PiS0_iii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11Kernel_gausPfS_S_iiiPifS0_S0_i
.globl _Z11Kernel_gausPfS_S_iiiPifS0_S0_i
.p2align 8
.type _Z11Kernel_gausPfS_S_iiiPifS0_S0_i,@function
_Z11Kernel_gausPfS_S_iiiPifS0_S0_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x5c
s_load_b32 s18, s[0:1], 0x18
v_and_b32_e32 v3, 0x3ff, v0
s_add_u32 s2, s0, 0x50
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s19, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s14, s19, v[3:4]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s18, v1
s_cbranch_execz .LBB1_11
s_load_b32 s22, s[2:3], 0xc
s_load_b32 s23, s[0:1], 0x48
s_load_b64 s[20:21], s[2:3], 0x0
s_clause 0x5
s_load_b128 s[4:7], s[0:1], 0x38
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b64 s[12:13], s[0:1], 0x1c
s_load_b64 s[16:17], s[0:1], 0x28
s_load_b32 s14, s[0:1], 0x30
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s0, s22, 16
v_mul_lo_u32 v5, s23, v1
s_delay_alu instid0(VALU_DEP_2)
v_mad_u64_u32 v[3:4], null, s15, s0, v[0:1]
s_mul_i32 s15, s20, s19
s_mul_i32 s19, s21, s0
s_mul_i32 s20, s15, s23
s_mov_b32 s21, 0
s_branch .LBB1_4
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s23
.LBB1_3:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
s_or_b32 exec_lo, exec_lo, s22
v_add_nc_u32_e32 v1, s15, v1
v_add_nc_u32_e32 v5, s20, v5
v_cmp_le_i32_e32 vcc_lo, s18, v1
s_or_b32 s21, vcc_lo, s21
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s21
s_cbranch_execz .LBB1_11
.LBB1_4:
s_mov_b32 s22, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s13, v3
s_cbranch_execz .LBB1_3
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s23, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[8:9], 2, v[1:2]
v_mul_lo_u32 v2, v1, s12
v_add_co_u32 v6, vcc_lo, s6, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v9, vcc_lo
v_add_co_u32 v8, s0, s2, v8
v_add_co_ci_u32_e64 v9, s0, s3, v9, s0
global_load_b32 v0, v[6:7], off
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, 0, v0
s_branch .LBB1_7
.LBB1_6:
s_or_b32 exec_lo, exec_lo, s24
global_load_b32 v12, v[8:9], off
s_waitcnt vmcnt(1)
v_ashrrev_i32_e32 v11, 31, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], 2, v[10:11]
v_add_co_u32 v10, s0, s2, v10
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v11, s0, s3, v11, s0
global_load_b32 v14, v[10:11], off
v_cvt_f64_f32_e32 v[10:11], v4
s_waitcnt vmcnt(1)
v_cvt_f64_f32_e32 v[12:13], v12
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[14:15], v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], v[10:11], -2.0, v[12:13]
v_add_f64 v[10:11], v[10:11], v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_f64_e64 v4, -v[10:11]
v_mul_f32_e32 v4, s14, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v10, 0x3fb8aa3b, v4
v_fma_f32 v11, v4, 0x3fb8aa3b, -v10
v_rndne_f32_e32 v12, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v11, 0x32a5705f, v4
v_sub_f32_e32 v10, v10, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v10, v10, v11
v_exp_f32_e32 v13, v10
v_mad_u64_u32 v[10:11], null, v3, s18, v[1:2]
v_add_nc_u32_e32 v3, s19, v3
v_cvt_i32_f32_e32 v11, v12
v_cmp_ngt_f32_e64 s0, 0xc2ce8ed0, v4
v_cmp_nlt_f32_e64 s1, 0x42b17218, v4
s_waitcnt_depctr 0xfff
v_ldexp_f32 v12, v13, v11
v_ashrrev_i32_e32 v11, 31, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v12, 0, v12, s0
v_lshlrev_b64 v[10:11], 2, v[10:11]
v_cmp_le_i32_e64 s0, s13, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v4, 0x7f800000, v12, s1
v_add_co_u32 v10, s1, s10, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e64 v11, s1, s11, v11, s1
s_or_b32 s23, s0, s23
global_store_b32 v[10:11], v4, off
s_and_not1_b32 exec_lo, exec_lo, s23
s_cbranch_execz .LBB1_2
.LBB1_7:
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[10:11], 2, v[3:4]
v_mov_b32_e32 v4, 0
v_add_co_u32 v10, s0, s16, v10
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v11, s0, s17, v11, s0
global_load_b32 v10, v[10:11], off
s_and_saveexec_b32 s24, vcc_lo
s_cbranch_execz .LBB1_6
s_waitcnt vmcnt(0)
v_mul_lo_u32 v13, v10, s12
v_mov_b32_e32 v12, v7
v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v11, v6
v_mov_b32_e32 v14, v0
s_mov_b32 s25, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB1_9:
global_load_b32 v16, v[11:12], off
v_add_nc_u32_e32 v14, -1, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s1, 0, v14
s_or_b32 s25, s1, s25
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v15, v16, v2
v_add_nc_u32_e32 v17, v16, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v16, 31, v15
v_ashrrev_i32_e32 v18, 31, v17
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[15:16], 2, v[15:16]
v_lshlrev_b64 v[17:18], 2, v[17:18]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v15, s0, s8, v15
v_add_co_ci_u32_e64 v16, s0, s9, v16, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v17, s0, s8, v17
v_add_co_ci_u32_e64 v18, s0, s9, v18, s0
v_add_co_u32 v11, s0, v11, 4
s_clause 0x1
global_load_b32 v15, v[15:16], off
global_load_b32 v16, v[17:18], off
v_add_co_ci_u32_e64 v12, s0, 0, v12, s0
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v4, v15, v16
s_and_not1_b32 exec_lo, exec_lo, s25
s_cbranch_execnz .LBB1_9
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s25
s_branch .LBB1_6
.LBB1_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11Kernel_gausPfS_S_iiiPifS0_S0_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 336
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 19
.amdhsa_next_free_sgpr 26
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z11Kernel_gausPfS_S_iiiPifS0_S0_i, .Lfunc_end1-_Z11Kernel_gausPfS_S_iiiPifS0_S0_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z14Kernel_linearePfS_iiiPiS0_S0_i
.globl _Z14Kernel_linearePfS_iiiPiS0_S0_i
.p2align 8
.type _Z14Kernel_linearePfS_iiiPiS0_S0_i,@function
_Z14Kernel_linearePfS_iiiPiS0_S0_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x4c
s_load_b32 s16, s[0:1], 0x10
v_and_b32_e32 v3, 0x3ff, v0
s_add_u32 s2, s0, 64
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s17, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s14, s17, v[3:4]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s16, v1
s_cbranch_execz .LBB2_11
s_load_b32 s14, s[2:3], 0xc
s_load_b32 s20, s[0:1], 0x38
s_load_b64 s[18:19], s[2:3], 0x0
s_clause 0x3
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x14
s_load_b128 s[8:11], s[0:1], 0x20
s_load_b64 s[12:13], s[0:1], 0x30
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s0, s14, 16
v_mul_lo_u32 v5, s20, v1
s_delay_alu instid0(VALU_DEP_2)
v_mad_u64_u32 v[3:4], null, s15, s0, v[0:1]
s_mul_i32 s14, s18, s17
s_mul_i32 s15, s19, s0
s_mul_i32 s17, s14, s20
s_mov_b32 s18, 0
s_branch .LBB2_4
.LBB2_2:
s_or_b32 exec_lo, exec_lo, s20
.LBB2_3:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
s_or_b32 exec_lo, exec_lo, s19
v_add_nc_u32_e32 v1, s14, v1
v_add_nc_u32_e32 v5, s17, v5
v_cmp_le_i32_e32 vcc_lo, s16, v1
s_or_b32 s18, vcc_lo, s18
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s18
s_cbranch_execz .LBB2_11
.LBB2_4:
s_mov_b32 s19, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v3
s_cbranch_execz .LBB2_3
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s20, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[1:2]
v_mul_lo_u32 v2, v1, s2
v_add_co_u32 v6, vcc_lo, s12, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, s13, v7, vcc_lo
global_load_b32 v0, v[6:7], off
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[6:7], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s10, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v7, vcc_lo
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, 0, v0
s_branch .LBB2_7
.LBB2_6:
s_or_b32 exec_lo, exec_lo, s21
v_mad_u64_u32 v[8:9], null, v3, s16, v[1:2]
v_add_nc_u32_e32 v3, s15, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_le_i32_e64 s0, s3, v3
v_ashrrev_i32_e32 v9, 31, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
s_or_b32 s20, s0, s20
v_lshlrev_b64 v[8:9], 2, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v8, s1, s6, v8
v_add_co_ci_u32_e64 v9, s1, s7, v9, s1
global_store_b32 v[8:9], v4, off
s_and_not1_b32 exec_lo, exec_lo, s20
s_cbranch_execz .LBB2_2
.LBB2_7:
v_mov_b32_e32 v4, 0
s_and_saveexec_b32 s21, vcc_lo
s_cbranch_execz .LBB2_6
v_ashrrev_i32_e32 v4, 31, v3
s_mov_b32 s22, 0
v_mov_b32_e32 v11, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[3:4]
v_add_co_u32 v8, s0, s8, v8
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v9, s0, s9, v9, s0
global_load_b32 v4, v[8:9], off
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(0)
v_mul_lo_u32 v10, v4, s2
v_mov_b32_e32 v4, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB2_9:
global_load_b32 v13, v[8:9], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v12, v13, v2
v_add_nc_u32_e32 v14, v13, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v13, 31, v12
v_ashrrev_i32_e32 v15, 31, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[12:13], 2, v[12:13]
v_lshlrev_b64 v[14:15], 2, v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v12, s0, s4, v12
v_add_co_ci_u32_e64 v13, s0, s5, v13, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v14, s0, s4, v14
v_add_co_ci_u32_e64 v15, s0, s5, v15, s0
v_add_co_u32 v8, s0, v8, 4
s_clause 0x1
global_load_b32 v12, v[12:13], off
global_load_b32 v13, v[14:15], off
v_add_nc_u32_e32 v11, -1, v11
v_add_co_ci_u32_e64 v9, s0, 0, v9, s0
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v4, v12, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s1, 0, v11
s_or_b32 s22, s1, s22
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s22
s_cbranch_execnz .LBB2_9
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s22
s_branch .LBB2_6
.LBB2_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14Kernel_linearePfS_iiiPiS0_S0_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 23
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z14Kernel_linearePfS_iiiPiS0_S0_i, .Lfunc_end2-_Z14Kernel_linearePfS_iiiPiS0_S0_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z18Kernel_polimonialePfS_iiiPiS0_S0_ii
.globl _Z18Kernel_polimonialePfS_iiiPiS0_S0_ii
.p2align 8
.type _Z18Kernel_polimonialePfS_iiiPiS0_S0_ii,@function
_Z18Kernel_polimonialePfS_iiiPiS0_S0_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x4c
s_load_b32 s12, s[0:1], 0x10
v_and_b32_e32 v3, 0x3ff, v0
s_add_u32 s2, s0, 64
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s20, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s14, s20, v[3:4]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB3_15
s_load_b32 s13, s[2:3], 0xc
s_load_b256 s[4:11], s[0:1], 0x20
s_load_b64 s[22:23], s[2:3], 0x0
s_clause 0x1
s_load_b128 s[16:19], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x14
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s0, s13, 16
v_mul_lo_u32 v5, s10, v1
s_delay_alu instid0(VALU_DEP_2)
v_mad_u64_u32 v[3:4], null, s15, s0, v[0:1]
s_cmp_gt_i32 s11, 0
s_mul_i32 s15, s22, s20
s_mov_b32 s13, 0
s_cselect_b32 s14, -1, 0
s_mul_i32 s20, s23, s0
s_mul_i32 s10, s15, s10
s_branch .LBB3_4
.LBB3_2:
s_or_b32 exec_lo, exec_lo, s22
.LBB3_3:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
s_or_b32 exec_lo, exec_lo, s21
v_add_nc_u32_e32 v1, s15, v1
v_add_nc_u32_e32 v5, s10, v5
v_cmp_le_i32_e32 vcc_lo, s12, v1
s_or_b32 s13, vcc_lo, s13
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execz .LBB3_15
.LBB3_4:
s_mov_b32 s21, exec_lo
v_cmpx_gt_i32_e64 s3, v3
s_cbranch_execz .LBB3_3
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s22, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[1:2]
v_mul_lo_u32 v2, v1, s2
v_add_co_u32 v6, vcc_lo, s8, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
global_load_b32 v0, v[6:7], off
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[6:7], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e64 s0, 0, v0
s_branch .LBB3_8
.LBB3_6:
v_mov_b32_e32 v4, 1.0
.LBB3_7:
v_mad_u64_u32 v[8:9], null, v3, s12, v[1:2]
v_add_nc_u32_e32 v3, s20, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_le_i32_e32 vcc_lo, s3, v3
v_ashrrev_i32_e32 v9, 31, v8
s_or_b32 s22, vcc_lo, s22
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_add_co_u32 v8, s1, s18, v8
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v9, s1, s19, v9, s1
global_store_b32 v[8:9], v4, off
s_and_not1_b32 exec_lo, exec_lo, s22
s_cbranch_execz .LBB3_2
.LBB3_8:
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_2)
s_and_saveexec_b32 s23, s0
s_cbranch_execz .LBB3_12
v_ashrrev_i32_e32 v4, 31, v3
s_mov_b32 s24, 0
v_mov_b32_e32 v11, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[3:4]
v_add_co_u32 v8, vcc_lo, s4, v8
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
global_load_b32 v4, v[8:9], off
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(0)
v_mul_lo_u32 v10, v4, s2
v_mov_b32_e32 v4, 0
.p2align 6
.LBB3_10:
global_load_b32 v13, v[8:9], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v12, v13, v2
v_add_nc_u32_e32 v14, v13, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v13, 31, v12
v_ashrrev_i32_e32 v15, 31, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[12:13], 2, v[12:13]
v_lshlrev_b64 v[14:15], 2, v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v12, vcc_lo, s16, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s17, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v14, vcc_lo, s16, v14
v_add_co_ci_u32_e32 v15, vcc_lo, s17, v15, vcc_lo
v_add_co_u32 v8, vcc_lo, v8, 4
s_clause 0x1
global_load_b32 v12, v[12:13], off
global_load_b32 v13, v[14:15], off
v_add_nc_u32_e32 v11, -1, v11
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v4, v12, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s1, 0, v11
s_or_b32 s24, s1, s24
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s24
s_cbranch_execnz .LBB3_10
s_or_b32 exec_lo, exec_lo, s24
.LBB3_12:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s23
s_and_not1_b32 vcc_lo, exec_lo, s14
s_cbranch_vccnz .LBB3_6
v_add_f32_e32 v8, 1.0, v4
v_mov_b32_e32 v4, 1.0
s_mov_b32 s1, s11
.LBB3_14:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mul_f32_e32 v4, v8, v4
s_add_i32 s1, s1, -1
s_cmp_lg_u32 s1, 0
s_cbranch_scc1 .LBB3_14
s_branch .LBB3_7
.LBB3_15:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18Kernel_polimonialePfS_iiiPiS0_S0_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 25
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z18Kernel_polimonialePfS_iiiPiS0_S0_ii, .Lfunc_end3-_Z18Kernel_polimonialePfS_iiiPiS0_S0_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12Kernel_normePfS_PiS0_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12Kernel_normePfS_PiS0_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .offset: 72
.size: 4
.value_kind: by_value
- .offset: 80
.size: 4
.value_kind: hidden_block_count_x
- .offset: 84
.size: 4
.value_kind: hidden_block_count_y
- .offset: 88
.size: 4
.value_kind: hidden_block_count_z
- .offset: 92
.size: 2
.value_kind: hidden_group_size_x
- .offset: 94
.size: 2
.value_kind: hidden_group_size_y
- .offset: 96
.size: 2
.value_kind: hidden_group_size_z
- .offset: 98
.size: 2
.value_kind: hidden_remainder_x
- .offset: 100
.size: 2
.value_kind: hidden_remainder_y
- .offset: 102
.size: 2
.value_kind: hidden_remainder_z
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 136
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 144
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 336
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11Kernel_gausPfS_S_iiiPifS0_S0_i
.private_segment_fixed_size: 0
.sgpr_count: 28
.sgpr_spill_count: 0
.symbol: _Z11Kernel_gausPfS_S_iiiPifS0_S0_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 19
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14Kernel_linearePfS_iiiPiS0_S0_i
.private_segment_fixed_size: 0
.sgpr_count: 25
.sgpr_spill_count: 0
.symbol: _Z14Kernel_linearePfS_iiiPiS0_S0_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 60
.size: 4
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18Kernel_polimonialePfS_iiiPiS0_S0_ii
.private_segment_fixed_size: 0
.sgpr_count: 27
.sgpr_spill_count: 0
.symbol: _Z18Kernel_polimonialePfS_iiiPiS0_S0_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void computeMoment(int8_t *readArr, int8_t *writeArr, float *weightArr, int n, int tileSize){
int row_init = blockIdx.x*(blockDim.x*tileSize) + threadIdx.x*tileSize;
int col_init = blockIdx.y*(blockDim.y*tileSize) + threadIdx.y*tileSize;
// Assign each thread a tileSizeXtileSize tile
for(int ii=0; ii<tileSize; ++ii){
for (int jj=0; jj<tileSize; ++jj){
int row = row_init + ii;
int col = col_init + jj;
// If coordinates are between boundaries
// update the write array accordingly
if(row < n && col < n){
float influence = 0.0f;
for (int i=-2; i<3; i++)
{
for (int j=-2; j<3; j++)
{
//add extra n so that modulo behaves like mathematics modulo
//that is return only positive values
int y = (row+i+n)%n;
int x = (col+j+n)%n;
influence += weightArr[i*5 + j]*readArr[y*n + x];
}
}
writeArr[row*n + col] = readArr[row*n + col];
if (influence<-diff) writeArr[row*n + col] = -1;
else if (influence>diff) writeArr[row*n + col] = 1;
__syncthreads();
}
}
}
} | .file "tmpxft_00056dc1_00000000-6_computeMoment.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z13computeMomentPaS_PfiiPaS_Pfii
.type _Z39__device_stub__Z13computeMomentPaS_PfiiPaS_Pfii, @function
_Z39__device_stub__Z13computeMomentPaS_PfiiPaS_Pfii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13computeMomentPaS_Pfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z13computeMomentPaS_PfiiPaS_Pfii, .-_Z39__device_stub__Z13computeMomentPaS_PfiiPaS_Pfii
.globl _Z13computeMomentPaS_Pfii
.type _Z13computeMomentPaS_Pfii, @function
_Z13computeMomentPaS_Pfii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z13computeMomentPaS_PfiiPaS_Pfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13computeMomentPaS_Pfii, .-_Z13computeMomentPaS_Pfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13computeMomentPaS_Pfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13computeMomentPaS_Pfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void computeMoment(int8_t *readArr, int8_t *writeArr, float *weightArr, int n, int tileSize){
int row_init = blockIdx.x*(blockDim.x*tileSize) + threadIdx.x*tileSize;
int col_init = blockIdx.y*(blockDim.y*tileSize) + threadIdx.y*tileSize;
// Assign each thread a tileSizeXtileSize tile
for(int ii=0; ii<tileSize; ++ii){
for (int jj=0; jj<tileSize; ++jj){
int row = row_init + ii;
int col = col_init + jj;
// If coordinates are between boundaries
// update the write array accordingly
if(row < n && col < n){
float influence = 0.0f;
for (int i=-2; i<3; i++)
{
for (int j=-2; j<3; j++)
{
//add extra n so that modulo behaves like mathematics modulo
//that is return only positive values
int y = (row+i+n)%n;
int x = (col+j+n)%n;
influence += weightArr[i*5 + j]*readArr[y*n + x];
}
}
writeArr[row*n + col] = readArr[row*n + col];
if (influence<-diff) writeArr[row*n + col] = -1;
else if (influence>diff) writeArr[row*n + col] = 1;
__syncthreads();
}
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void computeMoment(int8_t *readArr, int8_t *writeArr, float *weightArr, int n, int tileSize){
int row_init = blockIdx.x*(blockDim.x*tileSize) + threadIdx.x*tileSize;
int col_init = blockIdx.y*(blockDim.y*tileSize) + threadIdx.y*tileSize;
// Assign each thread a tileSizeXtileSize tile
for(int ii=0; ii<tileSize; ++ii){
for (int jj=0; jj<tileSize; ++jj){
int row = row_init + ii;
int col = col_init + jj;
// If coordinates are between boundaries
// update the write array accordingly
if(row < n && col < n){
float influence = 0.0f;
for (int i=-2; i<3; i++)
{
for (int j=-2; j<3; j++)
{
//add extra n so that modulo behaves like mathematics modulo
//that is return only positive values
int y = (row+i+n)%n;
int x = (col+j+n)%n;
influence += weightArr[i*5 + j]*readArr[y*n + x];
}
}
writeArr[row*n + col] = readArr[row*n + col];
if (influence<-diff) writeArr[row*n + col] = -1;
else if (influence>diff) writeArr[row*n + col] = 1;
__syncthreads();
}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void computeMoment(int8_t *readArr, int8_t *writeArr, float *weightArr, int n, int tileSize){
int row_init = blockIdx.x*(blockDim.x*tileSize) + threadIdx.x*tileSize;
int col_init = blockIdx.y*(blockDim.y*tileSize) + threadIdx.y*tileSize;
// Assign each thread a tileSizeXtileSize tile
for(int ii=0; ii<tileSize; ++ii){
for (int jj=0; jj<tileSize; ++jj){
int row = row_init + ii;
int col = col_init + jj;
// If coordinates are between boundaries
// update the write array accordingly
if(row < n && col < n){
float influence = 0.0f;
for (int i=-2; i<3; i++)
{
for (int j=-2; j<3; j++)
{
//add extra n so that modulo behaves like mathematics modulo
//that is return only positive values
int y = (row+i+n)%n;
int x = (col+j+n)%n;
influence += weightArr[i*5 + j]*readArr[y*n + x];
}
}
writeArr[row*n + col] = readArr[row*n + col];
if (influence<-diff) writeArr[row*n + col] = -1;
else if (influence>diff) writeArr[row*n + col] = 1;
__syncthreads();
}
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13computeMomentPaS_Pfii
.globl _Z13computeMomentPaS_Pfii
.p2align 8
.type _Z13computeMomentPaS_Pfii,@function
_Z13computeMomentPaS_Pfii:
s_load_b32 s12, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s12, 1
s_cbranch_scc1 .LBB0_15
s_clause 0x1
s_load_b32 s13, s[0:1], 0x18
s_load_b32 s8, s[0:1], 0x2c
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
v_mov_b32_e32 v6, 0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s2, s13, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s13, s2
s_xor_b32 s16, s3, s2
s_lshr_b32 s2, s8, 16
v_cvt_f32_u32_e32 v4, s16
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_and_b32 s0, s8, 0xffff
v_rcp_iflag_f32_e32 v1, v4
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v2, s12
s_waitcnt_depctr 0xfff
v_mad_u64_u32 v[3:4], null, s14, s0, v[0:1]
v_mul_f32_e32 v0, 0x4f7ffffe, v1
v_add3_u32 v4, s13, v2, -2
v_cvt_u32_f32_e32 v5, v0
s_delay_alu instid0(VALU_DEP_4)
v_mul_lo_u32 v3, v3, s12
s_branch .LBB0_3
.LBB0_2:
s_add_i32 s1, s1, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s1, s12
s_cbranch_scc1 .LBB0_15
.LBB0_3:
s_sub_i32 s0, 0, s16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_dual_mov_b32 v10, v4 :: v_dual_add_nc_u32 v1, s1, v3
v_mul_lo_u32 v0, s0, v5
s_mov_b32 s14, 0
v_mul_lo_u32 v7, v1, s13
v_cmp_gt_i32_e32 vcc_lo, s13, v1
v_add_nc_u32_e32 v8, s13, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v5, v0
v_add_nc_u32_e32 v9, v5, v0
s_branch .LBB0_6
.LBB0_4:
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s15
v_add_nc_u32_e32 v10, 1, v10
s_add_i32 s14, s14, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s14, s12
s_cbranch_scc1 .LBB0_2
.LBB0_6:
v_add_nc_u32_e32 v0, s14, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s0, s13, v0
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s15, s0
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v11, 0
s_mov_b32 s17, -2
s_waitcnt lgkmcnt(0)
s_mov_b64 s[8:9], s[2:3]
.LBB0_8:
v_add_nc_u32_e32 v1, s17, v8
s_movk_i32 s10, 0xffd0
s_mov_b32 s11, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v12, 31, v1
v_add_nc_u32_e32 v1, v1, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v1, v1, v12
v_mul_hi_u32 v13, v1, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v13, v13, s16
v_sub_nc_u32_e32 v1, v1, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v13, s16, v1
v_cmp_le_u32_e64 s0, s16, v1
v_cndmask_b32_e64 v1, v1, v13, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v13, s16, v1
v_cmp_le_u32_e64 s0, s16, v1
v_cndmask_b32_e64 v1, v1, v13, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v1, v1, v12
v_sub_nc_u32_e32 v1, v1, v12
v_mov_b32_e32 v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_mul_lo_u32 v1, v1, s13
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_9:
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
s_add_u32 s18, s8, s10
s_addc_u32 s19, s9, s11
s_add_u32 s10, s10, 4
s_addc_u32 s11, s11, 0
v_add_nc_u32_e32 v14, v12, v13
s_cmpk_eq_i32 s10, 0xffe4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v14, v14, v13
v_mul_hi_u32 v15, v14, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v15, v15, s16
v_sub_nc_u32_e32 v14, v14, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v15, s16, v14
v_cmp_le_u32_e64 s0, s16, v14
v_cndmask_b32_e64 v14, v14, v15, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v15, s16, v14
v_cmp_le_u32_e64 s0, s16, v14
v_cndmask_b32_e64 v14, v14, v15, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v14, v14, v13
v_sub_nc_u32_e32 v13, v14, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v13, v1, v13
v_ashrrev_i32_e32 v14, 31, v13
v_add_co_u32 v13, s0, s4, v13
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v14, s0, s5, v14, s0
global_load_i8 v13, v[13:14], off
global_load_b32 v14, v6, s[18:19]
s_waitcnt vmcnt(1)
v_cvt_f32_i32_e32 v13, v13
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_dual_fmac_f32 v11, v14, v13 :: v_dual_add_nc_u32 v12, 1, v12
s_cbranch_scc0 .LBB0_9
s_set_inst_prefetch_distance 0x2
s_add_i32 s17, s17, 1
s_add_u32 s8, s8, 20
s_addc_u32 s9, s9, 0
s_cmp_eq_u32 s17, 3
s_cbranch_scc0 .LBB0_8
v_add_nc_u32_e32 v12, v0, v7
v_cmp_gt_f32_e64 s8, 0xb58637bd, v11
s_mov_b32 s9, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
v_add_co_u32 v0, s0, s4, v12
v_add_co_ci_u32_e64 v1, s0, s5, v13, s0
global_load_u8 v14, v[0:1], off
v_add_co_u32 v0, s0, s6, v12
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, s0, s7, v13, s0
v_mov_b32_e32 v12, 0xff
s_waitcnt vmcnt(0)
global_store_b8 v[0:1], v14, off
v_cmpx_ngt_f32_e32 0xb58637bd, v11
v_cmp_lt_f32_e64 s0, 0x358637bd, v11
v_mov_b32_e32 v12, 1
s_and_not1_b32 s8, s8, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, exec_lo
s_or_b32 s8, s8, s0
s_or_b32 exec_lo, exec_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s8
s_cbranch_execz .LBB0_4
global_store_b8 v[0:1], v12, off
s_branch .LBB0_4
.LBB0_15:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13computeMomentPaS_Pfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13computeMomentPaS_Pfii, .Lfunc_end0-_Z13computeMomentPaS_Pfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13computeMomentPaS_Pfii
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z13computeMomentPaS_Pfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void computeMoment(int8_t *readArr, int8_t *writeArr, float *weightArr, int n, int tileSize){
int row_init = blockIdx.x*(blockDim.x*tileSize) + threadIdx.x*tileSize;
int col_init = blockIdx.y*(blockDim.y*tileSize) + threadIdx.y*tileSize;
// Assign each thread a tileSizeXtileSize tile
for(int ii=0; ii<tileSize; ++ii){
for (int jj=0; jj<tileSize; ++jj){
int row = row_init + ii;
int col = col_init + jj;
// If coordinates are between boundaries
// update the write array accordingly
if(row < n && col < n){
float influence = 0.0f;
for (int i=-2; i<3; i++)
{
for (int j=-2; j<3; j++)
{
//add extra n so that modulo behaves like mathematics modulo
//that is return only positive values
int y = (row+i+n)%n;
int x = (col+j+n)%n;
influence += weightArr[i*5 + j]*readArr[y*n + x];
}
}
writeArr[row*n + col] = readArr[row*n + col];
if (influence<-diff) writeArr[row*n + col] = -1;
else if (influence>diff) writeArr[row*n + col] = 1;
__syncthreads();
}
}
}
} | .text
.file "computeMoment.hip"
.globl _Z28__device_stub__computeMomentPaS_Pfii # -- Begin function _Z28__device_stub__computeMomentPaS_Pfii
.p2align 4, 0x90
.type _Z28__device_stub__computeMomentPaS_Pfii,@function
_Z28__device_stub__computeMomentPaS_Pfii: # @_Z28__device_stub__computeMomentPaS_Pfii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13computeMomentPaS_Pfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__computeMomentPaS_Pfii, .Lfunc_end0-_Z28__device_stub__computeMomentPaS_Pfii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13computeMomentPaS_Pfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13computeMomentPaS_Pfii,@object # @_Z13computeMomentPaS_Pfii
.section .rodata,"a",@progbits
.globl _Z13computeMomentPaS_Pfii
.p2align 3, 0x0
_Z13computeMomentPaS_Pfii:
.quad _Z28__device_stub__computeMomentPaS_Pfii
.size _Z13computeMomentPaS_Pfii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13computeMomentPaS_Pfii"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__computeMomentPaS_Pfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13computeMomentPaS_Pfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00056dc1_00000000-6_computeMoment.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z13computeMomentPaS_PfiiPaS_Pfii
.type _Z39__device_stub__Z13computeMomentPaS_PfiiPaS_Pfii, @function
_Z39__device_stub__Z13computeMomentPaS_PfiiPaS_Pfii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13computeMomentPaS_Pfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z13computeMomentPaS_PfiiPaS_Pfii, .-_Z39__device_stub__Z13computeMomentPaS_PfiiPaS_Pfii
.globl _Z13computeMomentPaS_Pfii
.type _Z13computeMomentPaS_Pfii, @function
_Z13computeMomentPaS_Pfii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z13computeMomentPaS_PfiiPaS_Pfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13computeMomentPaS_Pfii, .-_Z13computeMomentPaS_Pfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13computeMomentPaS_Pfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13computeMomentPaS_Pfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "computeMoment.hip"
.globl _Z28__device_stub__computeMomentPaS_Pfii # -- Begin function _Z28__device_stub__computeMomentPaS_Pfii
.p2align 4, 0x90
.type _Z28__device_stub__computeMomentPaS_Pfii,@function
_Z28__device_stub__computeMomentPaS_Pfii: # @_Z28__device_stub__computeMomentPaS_Pfii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13computeMomentPaS_Pfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__computeMomentPaS_Pfii, .Lfunc_end0-_Z28__device_stub__computeMomentPaS_Pfii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13computeMomentPaS_Pfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13computeMomentPaS_Pfii,@object # @_Z13computeMomentPaS_Pfii
.section .rodata,"a",@progbits
.globl _Z13computeMomentPaS_Pfii
.p2align 3, 0x0
_Z13computeMomentPaS_Pfii:
.quad _Z28__device_stub__computeMomentPaS_Pfii
.size _Z13computeMomentPaS_Pfii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13computeMomentPaS_Pfii"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__computeMomentPaS_Pfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13computeMomentPaS_Pfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<iostream>
using namespace std;
__global__ void matrixAdd(int **a,int **b,int **c){
int j = blockIdx.x*blockDim.x+threadIdx.x;
int i = blockIdx.y*blockDim.y+threadIdx.y;
c[i][j] = a[i][j]+b[i][j];
}
int main(){
int N=16;
int A[N][N],B[N][N],C[N][N];
for(int i=0;i<N;i++){
for(int j=0;j<N;j++){
A[i][j]=1;
B[i][j]=1;
C[i][j]=0;
}
}
int **a,**b,**c;
cudaMalloc((void**)&a,N*N*sizeof(int));
cudaMalloc((void**)&b,N*N*sizeof(int));
cudaMalloc((void**)&c,N*N*sizeof(int));
cudaMemcpy(a, A, (N*N)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(b, B, (N*N)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(c, C, (N*N)*sizeof(int), cudaMemcpyHostToDevice);
dim3 blocksPerGrid(N/16,N/16,1);
dim3 threadsPerBlock(16,16,1);
matrixAdd<<<blocksPerGrid,threadsPerBlock>>>(a,b,c);
cudaMemcpy(C, c, (N*N)*sizeof(int), cudaMemcpyDeviceToHost);
for(int i=0;i<N;i++){
for(int j=0;j<N;j++){
cout<<C[i][j]<<" ";
}
cout<<endl;
}
} | code for sm_80
Function : _Z9matrixAddPPiS0_S0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R10, SR_CTAID.Y ; /* 0x00000000000a7919 */
/* 0x000e220000002600 */
/*0020*/ HFMA2.MMA R11, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff0b7435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002200 */
/*0050*/ IMAD R10, R10, c[0x0][0x4], R3 ; /* 0x000001000a0a7a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R10, R11, c[0x0][0x160] ; /* 0x000058000a027625 */
/* 0x000fc800078e020b */
/*0070*/ IMAD.WIDE R6, R10.reuse, R11.reuse, c[0x0][0x168] ; /* 0x00005a000a067625 */
/* 0x0c0fe400078e020b */
/*0080*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*0090*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1b00 */
/*00a0*/ IMAD.WIDE R10, R10, R11, c[0x0][0x170] ; /* 0x00005c000a0a7625 */
/* 0x000fc600078e020b */
/*00b0*/ S2R R13, SR_CTAID.X ; /* 0x00000000000d7919 */
/* 0x000e280000002500 */
/*00c0*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*00d0*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000f22000c1e1b00 */
/*00e0*/ IMAD R13, R13, c[0x0][0x0], R0 ; /* 0x000000000d0d7a24 */
/* 0x001fc800078e0200 */
/*00f0*/ IMAD.WIDE R4, R13, 0x4, R2 ; /* 0x000000040d047825 */
/* 0x004fc800078e0202 */
/*0100*/ IMAD.WIDE R8, R13.reuse, 0x4, R6 ; /* 0x000000040d087825 */
/* 0x048fe400078e0206 */
/*0110*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0120*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*0130*/ IMAD.WIDE R2, R13, 0x4, R10 ; /* 0x000000040d027825 */
/* 0x010fe200078e020a */
/*0140*/ IADD3 R7, R4, R9, RZ ; /* 0x0000000904077210 */
/* 0x004fca0007ffe0ff */
/*0150*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<iostream>
using namespace std;
__global__ void matrixAdd(int **a,int **b,int **c){
int j = blockIdx.x*blockDim.x+threadIdx.x;
int i = blockIdx.y*blockDim.y+threadIdx.y;
c[i][j] = a[i][j]+b[i][j];
}
int main(){
int N=16;
int A[N][N],B[N][N],C[N][N];
for(int i=0;i<N;i++){
for(int j=0;j<N;j++){
A[i][j]=1;
B[i][j]=1;
C[i][j]=0;
}
}
int **a,**b,**c;
cudaMalloc((void**)&a,N*N*sizeof(int));
cudaMalloc((void**)&b,N*N*sizeof(int));
cudaMalloc((void**)&c,N*N*sizeof(int));
cudaMemcpy(a, A, (N*N)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(b, B, (N*N)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(c, C, (N*N)*sizeof(int), cudaMemcpyHostToDevice);
dim3 blocksPerGrid(N/16,N/16,1);
dim3 threadsPerBlock(16,16,1);
matrixAdd<<<blocksPerGrid,threadsPerBlock>>>(a,b,c);
cudaMemcpy(C, c, (N*N)*sizeof(int), cudaMemcpyDeviceToHost);
for(int i=0;i<N;i++){
for(int j=0;j<N;j++){
cout<<C[i][j]<<" ";
}
cout<<endl;
}
} | .file "tmpxft_000b86ac_00000000-6_test.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z9matrixAddPPiS0_S0_PPiS0_S0_
.type _Z35__device_stub__Z9matrixAddPPiS0_S0_PPiS0_S0_, @function
_Z35__device_stub__Z9matrixAddPPiS0_S0_PPiS0_S0_:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9matrixAddPPiS0_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z35__device_stub__Z9matrixAddPPiS0_S0_PPiS0_S0_, .-_Z35__device_stub__Z9matrixAddPPiS0_S0_PPiS0_S0_
.globl _Z9matrixAddPPiS0_S0_
.type _Z9matrixAddPPiS0_S0_, @function
_Z9matrixAddPPiS0_S0_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z9matrixAddPPiS0_S0_PPiS0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z9matrixAddPPiS0_S0_, .-_Z9matrixAddPPiS0_S0_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $72, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
movq %rsp, %rax
.L12:
cmpq %rax, %rsp
je .L13
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L12
.L13:
subq $1024, %rsp
orq $0, 1016(%rsp)
movq %rsp, %r12
movq %rsp, %rax
.L15:
cmpq %rax, %rsp
je .L16
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L15
.L16:
subq $1024, %rsp
orq $0, 1016(%rsp)
movq %rsp, %rbx
movq %rsp, %rax
.L18:
cmpq %rax, %rsp
je .L19
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L18
.L19:
subq $1024, %rsp
orq $0, 1016(%rsp)
movq %rsp, %r14
movl $64, %edx
.L21:
leaq -64(%rdx), %rax
.L22:
movl $1, (%r12,%rax)
movl $1, (%rbx,%rax)
movl $0, (%r14,%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L22
addq $64, %rdx
cmpq $1088, %rdx
jne .L21
leaq -104(%rbp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq -96(%rbp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq -88(%rbp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $1024, %edx
movq %r12, %rsi
movq -104(%rbp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $1024, %edx
movq %rbx, %rsi
movq -96(%rbp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $1024, %edx
movq %r14, %rsi
movq -88(%rbp), %rdi
call cudaMemcpy@PLT
movl $1, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl $16, -68(%rbp)
movl $16, -64(%rbp)
movl $1, -60(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L24:
movl $2, %ecx
movl $1024, %edx
movq -88(%rbp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
leaq 64(%r14), %r12
addq $1088, %r14
leaq _ZSt4cout(%rip), %r13
leaq .LC0(%rip), %r15
jmp .L25
.L36:
movq -88(%rbp), %rdx
movq -96(%rbp), %rsi
movq -104(%rbp), %rdi
call _Z35__device_stub__Z9matrixAddPPiS0_S0_PPiS0_S0_
jmp .L24
.L38:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L37
call _ZSt16__throw_bad_castv@PLT
.L37:
call __stack_chk_fail@PLT
.L29:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
.L30:
movsbl %sil, %esi
movq %r13, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $64, %r12
cmpq %r14, %r12
je .L31
.L25:
leaq -64(%r12), %rbx
.L26:
movl (%rbx), %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r15, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L26
movq 0(%r13), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %rbx
testq %rbx, %rbx
je .L38
cmpb $0, 56(%rbx)
je .L29
movzbl 67(%rbx), %esi
jmp .L30
.L31:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L39
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L39:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z9matrixAddPPiS0_S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9matrixAddPPiS0_S0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<iostream>
using namespace std;
__global__ void matrixAdd(int **a,int **b,int **c){
int j = blockIdx.x*blockDim.x+threadIdx.x;
int i = blockIdx.y*blockDim.y+threadIdx.y;
c[i][j] = a[i][j]+b[i][j];
}
int main(){
int N=16;
int A[N][N],B[N][N],C[N][N];
for(int i=0;i<N;i++){
for(int j=0;j<N;j++){
A[i][j]=1;
B[i][j]=1;
C[i][j]=0;
}
}
int **a,**b,**c;
cudaMalloc((void**)&a,N*N*sizeof(int));
cudaMalloc((void**)&b,N*N*sizeof(int));
cudaMalloc((void**)&c,N*N*sizeof(int));
cudaMemcpy(a, A, (N*N)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(b, B, (N*N)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(c, C, (N*N)*sizeof(int), cudaMemcpyHostToDevice);
dim3 blocksPerGrid(N/16,N/16,1);
dim3 threadsPerBlock(16,16,1);
matrixAdd<<<blocksPerGrid,threadsPerBlock>>>(a,b,c);
cudaMemcpy(C, c, (N*N)*sizeof(int), cudaMemcpyDeviceToHost);
for(int i=0;i<N;i++){
for(int j=0;j<N;j++){
cout<<C[i][j]<<" ";
}
cout<<endl;
}
} | #include <hip/hip_runtime.h>
#include<iostream>
using namespace std;
__global__ void matrixAdd(int **a,int **b,int **c){
int j = blockIdx.x*blockDim.x+threadIdx.x;
int i = blockIdx.y*blockDim.y+threadIdx.y;
c[i][j] = a[i][j]+b[i][j];
}
int main(){
int N=16;
int A[N][N],B[N][N],C[N][N];
for(int i=0;i<N;i++){
for(int j=0;j<N;j++){
A[i][j]=1;
B[i][j]=1;
C[i][j]=0;
}
}
int **a,**b,**c;
hipMalloc((void**)&a,N*N*sizeof(int));
hipMalloc((void**)&b,N*N*sizeof(int));
hipMalloc((void**)&c,N*N*sizeof(int));
hipMemcpy(a, A, (N*N)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(b, B, (N*N)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(c, C, (N*N)*sizeof(int), hipMemcpyHostToDevice);
dim3 blocksPerGrid(N/16,N/16,1);
dim3 threadsPerBlock(16,16,1);
matrixAdd<<<blocksPerGrid,threadsPerBlock>>>(a,b,c);
hipMemcpy(C, c, (N*N)*sizeof(int), hipMemcpyDeviceToHost);
for(int i=0;i<N;i++){
for(int j=0;j<N;j++){
cout<<C[i][j]<<" ";
}
cout<<endl;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<iostream>
using namespace std;
__global__ void matrixAdd(int **a,int **b,int **c){
int j = blockIdx.x*blockDim.x+threadIdx.x;
int i = blockIdx.y*blockDim.y+threadIdx.y;
c[i][j] = a[i][j]+b[i][j];
}
int main(){
int N=16;
int A[N][N],B[N][N],C[N][N];
for(int i=0;i<N;i++){
for(int j=0;j<N;j++){
A[i][j]=1;
B[i][j]=1;
C[i][j]=0;
}
}
int **a,**b,**c;
hipMalloc((void**)&a,N*N*sizeof(int));
hipMalloc((void**)&b,N*N*sizeof(int));
hipMalloc((void**)&c,N*N*sizeof(int));
hipMemcpy(a, A, (N*N)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(b, B, (N*N)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(c, C, (N*N)*sizeof(int), hipMemcpyHostToDevice);
dim3 blocksPerGrid(N/16,N/16,1);
dim3 threadsPerBlock(16,16,1);
matrixAdd<<<blocksPerGrid,threadsPerBlock>>>(a,b,c);
hipMemcpy(C, c, (N*N)*sizeof(int), hipMemcpyDeviceToHost);
for(int i=0;i<N;i++){
for(int j=0;j<N;j++){
cout<<C[i][j]<<" ";
}
cout<<endl;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9matrixAddPPiS0_S0_
.globl _Z9matrixAddPPiS0_S0_
.p2align 8
.type _Z9matrixAddPPiS0_S0_,@function
_Z9matrixAddPPiS0_S0_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[1:2], 3, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v2, vcc_lo
v_mad_u64_u32 v[7:8], null, s14, s2, v[0:1]
global_load_b64 v[3:4], v[3:4], off
global_load_b64 v[5:6], v[5:6], off
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_waitcnt vmcnt(1)
v_add_co_u32 v3, vcc_lo, v3, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, v4, v8, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v5, vcc_lo, v5, v7
v_add_co_ci_u32_e32 v6, vcc_lo, v6, v8, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
flat_load_b32 v2, v[3:4]
flat_load_b32 v3, v[5:6]
global_load_b64 v[0:1], v[0:1], off
s_waitcnt vmcnt(1) lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v0, vcc_lo, v0, v7
v_add_co_ci_u32_e32 v1, vcc_lo, v1, v8, vcc_lo
flat_store_b32 v[0:1], v2
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9matrixAddPPiS0_S0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9matrixAddPPiS0_S0_, .Lfunc_end0-_Z9matrixAddPPiS0_S0_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9matrixAddPPiS0_S0_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9matrixAddPPiS0_S0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<iostream>
using namespace std;
__global__ void matrixAdd(int **a,int **b,int **c){
int j = blockIdx.x*blockDim.x+threadIdx.x;
int i = blockIdx.y*blockDim.y+threadIdx.y;
c[i][j] = a[i][j]+b[i][j];
}
int main(){
int N=16;
int A[N][N],B[N][N],C[N][N];
for(int i=0;i<N;i++){
for(int j=0;j<N;j++){
A[i][j]=1;
B[i][j]=1;
C[i][j]=0;
}
}
int **a,**b,**c;
hipMalloc((void**)&a,N*N*sizeof(int));
hipMalloc((void**)&b,N*N*sizeof(int));
hipMalloc((void**)&c,N*N*sizeof(int));
hipMemcpy(a, A, (N*N)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(b, B, (N*N)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(c, C, (N*N)*sizeof(int), hipMemcpyHostToDevice);
dim3 blocksPerGrid(N/16,N/16,1);
dim3 threadsPerBlock(16,16,1);
matrixAdd<<<blocksPerGrid,threadsPerBlock>>>(a,b,c);
hipMemcpy(C, c, (N*N)*sizeof(int), hipMemcpyDeviceToHost);
for(int i=0;i<N;i++){
for(int j=0;j<N;j++){
cout<<C[i][j]<<" ";
}
cout<<endl;
}
} | .text
.file "test.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__matrixAddPPiS0_S0_ # -- Begin function _Z24__device_stub__matrixAddPPiS0_S0_
.p2align 4, 0x90
.type _Z24__device_stub__matrixAddPPiS0_S0_,@function
_Z24__device_stub__matrixAddPPiS0_S0_: # @_Z24__device_stub__matrixAddPPiS0_S0_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9matrixAddPPiS0_S0_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__matrixAddPPiS0_S0_, .Lfunc_end0-_Z24__device_stub__matrixAddPPiS0_S0_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $3200, %rsp # imm = 0xC80
.cfi_def_cfa_offset 3232
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 128(%rsp), %rdi
xorl %ebx, %ebx
movl $1024, %edx # imm = 0x400
xorl %esi, %esi
callq memset@PLT
leaq 1152(%rsp), %rax
leaq 2176(%rsp), %rcx
.p2align 4, 0x90
.LBB1_1: # %.preheader54
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movl $1, (%rcx,%rdx,4)
movl $1, (%rax,%rdx,4)
incq %rdx
cmpq $16, %rdx
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %rbx
addq $64, %rax
addq $64, %rcx
cmpq $16, %rbx
jne .LBB1_1
# %bb.4:
leaq 16(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
leaq 8(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movq %rsp, %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movq 16(%rsp), %rdi
leaq 2176(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 1152(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
leaq 128(%rsp), %rbx
movl $1024, %edx # imm = 0x400
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9matrixAddPPiS0_S0_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq (%rsp), %rsi
movl $1024, %edx # imm = 0x400
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r15d, %r15d
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_12: # in Loop: Header=BB1_7 Depth=1
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_13: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB1_7 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r15
addq $64, %rbx
cmpq $16, %r15
je .LBB1_14
.LBB1_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_8: # Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%r14,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r14
cmpq $16, %r14
jne .LBB1_8
# %bb.9: # in Loop: Header=BB1_7 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB1_15
# %bb.10: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_7 Depth=1
cmpb $0, 56(%r14)
je .LBB1_12
# %bb.11: # in Loop: Header=BB1_7 Depth=1
movzbl 67(%r14), %eax
jmp .LBB1_13
.LBB1_14:
xorl %eax, %eax
addq $3200, %rsp # imm = 0xC80
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_15:
.cfi_def_cfa_offset 3232
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9matrixAddPPiS0_S0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9matrixAddPPiS0_S0_,@object # @_Z9matrixAddPPiS0_S0_
.section .rodata,"a",@progbits
.globl _Z9matrixAddPPiS0_S0_
.p2align 3, 0x0
_Z9matrixAddPPiS0_S0_:
.quad _Z24__device_stub__matrixAddPPiS0_S0_
.size _Z9matrixAddPPiS0_S0_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9matrixAddPPiS0_S0_"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__matrixAddPPiS0_S0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9matrixAddPPiS0_S0_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9matrixAddPPiS0_S0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R10, SR_CTAID.Y ; /* 0x00000000000a7919 */
/* 0x000e220000002600 */
/*0020*/ HFMA2.MMA R11, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff0b7435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002200 */
/*0050*/ IMAD R10, R10, c[0x0][0x4], R3 ; /* 0x000001000a0a7a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R10, R11, c[0x0][0x160] ; /* 0x000058000a027625 */
/* 0x000fc800078e020b */
/*0070*/ IMAD.WIDE R6, R10.reuse, R11.reuse, c[0x0][0x168] ; /* 0x00005a000a067625 */
/* 0x0c0fe400078e020b */
/*0080*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*0090*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1b00 */
/*00a0*/ IMAD.WIDE R10, R10, R11, c[0x0][0x170] ; /* 0x00005c000a0a7625 */
/* 0x000fc600078e020b */
/*00b0*/ S2R R13, SR_CTAID.X ; /* 0x00000000000d7919 */
/* 0x000e280000002500 */
/*00c0*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*00d0*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000f22000c1e1b00 */
/*00e0*/ IMAD R13, R13, c[0x0][0x0], R0 ; /* 0x000000000d0d7a24 */
/* 0x001fc800078e0200 */
/*00f0*/ IMAD.WIDE R4, R13, 0x4, R2 ; /* 0x000000040d047825 */
/* 0x004fc800078e0202 */
/*0100*/ IMAD.WIDE R8, R13.reuse, 0x4, R6 ; /* 0x000000040d087825 */
/* 0x048fe400078e0206 */
/*0110*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0120*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*0130*/ IMAD.WIDE R2, R13, 0x4, R10 ; /* 0x000000040d027825 */
/* 0x010fe200078e020a */
/*0140*/ IADD3 R7, R4, R9, RZ ; /* 0x0000000904077210 */
/* 0x004fca0007ffe0ff */
/*0150*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9matrixAddPPiS0_S0_
.globl _Z9matrixAddPPiS0_S0_
.p2align 8
.type _Z9matrixAddPPiS0_S0_,@function
_Z9matrixAddPPiS0_S0_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[1:2], 3, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v2, vcc_lo
v_mad_u64_u32 v[7:8], null, s14, s2, v[0:1]
global_load_b64 v[3:4], v[3:4], off
global_load_b64 v[5:6], v[5:6], off
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_waitcnt vmcnt(1)
v_add_co_u32 v3, vcc_lo, v3, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, v4, v8, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v5, vcc_lo, v5, v7
v_add_co_ci_u32_e32 v6, vcc_lo, v6, v8, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
flat_load_b32 v2, v[3:4]
flat_load_b32 v3, v[5:6]
global_load_b64 v[0:1], v[0:1], off
s_waitcnt vmcnt(1) lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v0, vcc_lo, v0, v7
v_add_co_ci_u32_e32 v1, vcc_lo, v1, v8, vcc_lo
flat_store_b32 v[0:1], v2
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9matrixAddPPiS0_S0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9matrixAddPPiS0_S0_, .Lfunc_end0-_Z9matrixAddPPiS0_S0_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9matrixAddPPiS0_S0_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9matrixAddPPiS0_S0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b86ac_00000000-6_test.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z9matrixAddPPiS0_S0_PPiS0_S0_
.type _Z35__device_stub__Z9matrixAddPPiS0_S0_PPiS0_S0_, @function
_Z35__device_stub__Z9matrixAddPPiS0_S0_PPiS0_S0_:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9matrixAddPPiS0_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z35__device_stub__Z9matrixAddPPiS0_S0_PPiS0_S0_, .-_Z35__device_stub__Z9matrixAddPPiS0_S0_PPiS0_S0_
.globl _Z9matrixAddPPiS0_S0_
.type _Z9matrixAddPPiS0_S0_, @function
_Z9matrixAddPPiS0_S0_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z9matrixAddPPiS0_S0_PPiS0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z9matrixAddPPiS0_S0_, .-_Z9matrixAddPPiS0_S0_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $72, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
movq %rsp, %rax
.L12:
cmpq %rax, %rsp
je .L13
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L12
.L13:
subq $1024, %rsp
orq $0, 1016(%rsp)
movq %rsp, %r12
movq %rsp, %rax
.L15:
cmpq %rax, %rsp
je .L16
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L15
.L16:
subq $1024, %rsp
orq $0, 1016(%rsp)
movq %rsp, %rbx
movq %rsp, %rax
.L18:
cmpq %rax, %rsp
je .L19
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L18
.L19:
subq $1024, %rsp
orq $0, 1016(%rsp)
movq %rsp, %r14
movl $64, %edx
.L21:
leaq -64(%rdx), %rax
.L22:
movl $1, (%r12,%rax)
movl $1, (%rbx,%rax)
movl $0, (%r14,%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L22
addq $64, %rdx
cmpq $1088, %rdx
jne .L21
leaq -104(%rbp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq -96(%rbp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq -88(%rbp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $1024, %edx
movq %r12, %rsi
movq -104(%rbp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $1024, %edx
movq %rbx, %rsi
movq -96(%rbp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $1024, %edx
movq %r14, %rsi
movq -88(%rbp), %rdi
call cudaMemcpy@PLT
movl $1, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl $16, -68(%rbp)
movl $16, -64(%rbp)
movl $1, -60(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L24:
movl $2, %ecx
movl $1024, %edx
movq -88(%rbp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
leaq 64(%r14), %r12
addq $1088, %r14
leaq _ZSt4cout(%rip), %r13
leaq .LC0(%rip), %r15
jmp .L25
.L36:
movq -88(%rbp), %rdx
movq -96(%rbp), %rsi
movq -104(%rbp), %rdi
call _Z35__device_stub__Z9matrixAddPPiS0_S0_PPiS0_S0_
jmp .L24
.L38:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L37
call _ZSt16__throw_bad_castv@PLT
.L37:
call __stack_chk_fail@PLT
.L29:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
.L30:
movsbl %sil, %esi
movq %r13, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $64, %r12
cmpq %r14, %r12
je .L31
.L25:
leaq -64(%r12), %rbx
.L26:
movl (%rbx), %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r15, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L26
movq 0(%r13), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %rbx
testq %rbx, %rbx
je .L38
cmpb $0, 56(%rbx)
je .L29
movzbl 67(%rbx), %esi
jmp .L30
.L31:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L39
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L39:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z9matrixAddPPiS0_S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9matrixAddPPiS0_S0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__matrixAddPPiS0_S0_ # -- Begin function _Z24__device_stub__matrixAddPPiS0_S0_
.p2align 4, 0x90
.type _Z24__device_stub__matrixAddPPiS0_S0_,@function
_Z24__device_stub__matrixAddPPiS0_S0_: # @_Z24__device_stub__matrixAddPPiS0_S0_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9matrixAddPPiS0_S0_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__matrixAddPPiS0_S0_, .Lfunc_end0-_Z24__device_stub__matrixAddPPiS0_S0_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $3200, %rsp # imm = 0xC80
.cfi_def_cfa_offset 3232
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 128(%rsp), %rdi
xorl %ebx, %ebx
movl $1024, %edx # imm = 0x400
xorl %esi, %esi
callq memset@PLT
leaq 1152(%rsp), %rax
leaq 2176(%rsp), %rcx
.p2align 4, 0x90
.LBB1_1: # %.preheader54
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movl $1, (%rcx,%rdx,4)
movl $1, (%rax,%rdx,4)
incq %rdx
cmpq $16, %rdx
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %rbx
addq $64, %rax
addq $64, %rcx
cmpq $16, %rbx
jne .LBB1_1
# %bb.4:
leaq 16(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
leaq 8(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movq %rsp, %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movq 16(%rsp), %rdi
leaq 2176(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 1152(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
leaq 128(%rsp), %rbx
movl $1024, %edx # imm = 0x400
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9matrixAddPPiS0_S0_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq (%rsp), %rsi
movl $1024, %edx # imm = 0x400
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r15d, %r15d
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_12: # in Loop: Header=BB1_7 Depth=1
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_13: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB1_7 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r15
addq $64, %rbx
cmpq $16, %r15
je .LBB1_14
.LBB1_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_8: # Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%r14,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r14
cmpq $16, %r14
jne .LBB1_8
# %bb.9: # in Loop: Header=BB1_7 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB1_15
# %bb.10: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_7 Depth=1
cmpb $0, 56(%r14)
je .LBB1_12
# %bb.11: # in Loop: Header=BB1_7 Depth=1
movzbl 67(%r14), %eax
jmp .LBB1_13
.LBB1_14:
xorl %eax, %eax
addq $3200, %rsp # imm = 0xC80
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_15:
.cfi_def_cfa_offset 3232
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9matrixAddPPiS0_S0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9matrixAddPPiS0_S0_,@object # @_Z9matrixAddPPiS0_S0_
.section .rodata,"a",@progbits
.globl _Z9matrixAddPPiS0_S0_
.p2align 3, 0x0
_Z9matrixAddPPiS0_S0_:
.quad _Z24__device_stub__matrixAddPPiS0_S0_
.size _Z9matrixAddPPiS0_S0_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9matrixAddPPiS0_S0_"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__matrixAddPPiS0_S0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9matrixAddPPiS0_S0_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
using namespace std;
__global__ void square(float *d_out, float *d_in){
int idx = blockDim.x*blockIdx.x + threadIdx.x;
float f = d_in[idx];
d_out[idx] = f*f;
}
int main(){
const int ARRAY_SIZE = 10000;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
float h_in[ARRAY_SIZE];
for(int i=0; i < ARRAY_SIZE; i++){
h_in[i] = float(i);
}
float h_out[ARRAY_SIZE];
float *d_in;
float *d_out;
cudaMalloc((void**) &d_in, ARRAY_BYTES);
cudaMalloc((void**) &d_out, ARRAY_BYTES);
cudaMemcpy(d_in, h_in, ARRAY_BYTES, cudaMemcpyHostToDevice);
int NUM_THREADS = 512;
int NUM_BLOCKS = ARRAY_SIZE / NUM_THREADS + 1;
square<<<NUM_BLOCKS, NUM_THREADS>>>(d_out, d_in);
cudaMemcpy(h_out, d_out, ARRAY_BYTES, cudaMemcpyDeviceToHost);
for(int i=0; i< ARRAY_SIZE; i++){
cout << h_out[i];
if(i%10!=9) cout << "\t";
else cout << endl;
}
} | code for sm_80
Function : _Z6squarePfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fcc00078e0205 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0205 */
/*0090*/ FMUL R7, R2, R2 ; /* 0x0000000202077220 */
/* 0x004fca0000400000 */
/*00a0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
using namespace std;
__global__ void square(float *d_out, float *d_in){
int idx = blockDim.x*blockIdx.x + threadIdx.x;
float f = d_in[idx];
d_out[idx] = f*f;
}
int main(){
const int ARRAY_SIZE = 10000;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
float h_in[ARRAY_SIZE];
for(int i=0; i < ARRAY_SIZE; i++){
h_in[i] = float(i);
}
float h_out[ARRAY_SIZE];
float *d_in;
float *d_out;
cudaMalloc((void**) &d_in, ARRAY_BYTES);
cudaMalloc((void**) &d_out, ARRAY_BYTES);
cudaMemcpy(d_in, h_in, ARRAY_BYTES, cudaMemcpyHostToDevice);
int NUM_THREADS = 512;
int NUM_BLOCKS = ARRAY_SIZE / NUM_THREADS + 1;
square<<<NUM_BLOCKS, NUM_THREADS>>>(d_out, d_in);
cudaMemcpy(h_out, d_out, ARRAY_BYTES, cudaMemcpyDeviceToHost);
for(int i=0; i< ARRAY_SIZE; i++){
cout << h_out[i];
if(i%10!=9) cout << "\t";
else cout << endl;
}
} | .file "tmpxft_001b33b0_00000000-6_square.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z6squarePfS_PfS_
.type _Z27__device_stub__Z6squarePfS_PfS_, @function
_Z27__device_stub__Z6squarePfS_PfS_:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6squarePfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z27__device_stub__Z6squarePfS_PfS_, .-_Z27__device_stub__Z6squarePfS_PfS_
.globl _Z6squarePfS_
.type _Z6squarePfS_, @function
_Z6squarePfS_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6squarePfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z6squarePfS_, .-_Z6squarePfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\t"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
leaq -77824(%rsp), %r11
.cfi_def_cfa 11, 77872
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $2240, %rsp
.cfi_def_cfa_offset 80112
movq %fs:40, %rax
movq %rax, 80056(%rsp)
xorl %eax, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 48(%rsp,%rax,4)
addq $1, %rax
cmpq $10000, %rax
jne .L12
leaq 8(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $40000, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $20, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L13:
leaq 40048(%rsp), %rdi
movl $2, %ecx
movl $40000, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %ebx
leaq 40048(%rsp), %r12
leaq _ZSt4cout(%rip), %rbp
leaq .LC0(%rip), %r13
jmp .L20
.L25:
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z27__device_stub__Z6squarePfS_PfS_
jmp .L13
.L14:
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r14
testq %r14, %r14
je .L26
cmpb $0, 56(%r14)
je .L18
movzbl 67(%r14), %esi
.L19:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.L15:
addq $1, %rbx
cmpq $10000, %rbx
je .L27
.L20:
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movslq %ebx, %rax
imulq $1717986919, %rax, %rax
sarq $34, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,4), %eax
addl %eax, %eax
movl %ebx, %edx
subl %eax, %edx
cmpl $9, %edx
je .L14
movl $1, %edx
movq %r13, %rsi
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L15
.L26:
movq 80056(%rsp), %rax
subq %fs:40, %rax
jne .L28
call _ZSt16__throw_bad_castv@PLT
.L28:
call __stack_chk_fail@PLT
.L18:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L19
.L27:
movq 80056(%rsp), %rax
subq %fs:40, %rax
jne .L29
movl $0, %eax
addq $80064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z6squarePfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6squarePfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
using namespace std;
__global__ void square(float *d_out, float *d_in){
int idx = blockDim.x*blockIdx.x + threadIdx.x;
float f = d_in[idx];
d_out[idx] = f*f;
}
int main(){
const int ARRAY_SIZE = 10000;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
float h_in[ARRAY_SIZE];
for(int i=0; i < ARRAY_SIZE; i++){
h_in[i] = float(i);
}
float h_out[ARRAY_SIZE];
float *d_in;
float *d_out;
cudaMalloc((void**) &d_in, ARRAY_BYTES);
cudaMalloc((void**) &d_out, ARRAY_BYTES);
cudaMemcpy(d_in, h_in, ARRAY_BYTES, cudaMemcpyHostToDevice);
int NUM_THREADS = 512;
int NUM_BLOCKS = ARRAY_SIZE / NUM_THREADS + 1;
square<<<NUM_BLOCKS, NUM_THREADS>>>(d_out, d_in);
cudaMemcpy(h_out, d_out, ARRAY_BYTES, cudaMemcpyDeviceToHost);
for(int i=0; i< ARRAY_SIZE; i++){
cout << h_out[i];
if(i%10!=9) cout << "\t";
else cout << endl;
}
} | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
__global__ void square(float *d_out, float *d_in){
int idx = blockDim.x*blockIdx.x + threadIdx.x;
float f = d_in[idx];
d_out[idx] = f*f;
}
int main(){
const int ARRAY_SIZE = 10000;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
float h_in[ARRAY_SIZE];
for(int i=0; i < ARRAY_SIZE; i++){
h_in[i] = float(i);
}
float h_out[ARRAY_SIZE];
float *d_in;
float *d_out;
hipMalloc((void**) &d_in, ARRAY_BYTES);
hipMalloc((void**) &d_out, ARRAY_BYTES);
hipMemcpy(d_in, h_in, ARRAY_BYTES, hipMemcpyHostToDevice);
int NUM_THREADS = 512;
int NUM_BLOCKS = ARRAY_SIZE / NUM_THREADS + 1;
square<<<NUM_BLOCKS, NUM_THREADS>>>(d_out, d_in);
hipMemcpy(h_out, d_out, ARRAY_BYTES, hipMemcpyDeviceToHost);
for(int i=0; i< ARRAY_SIZE; i++){
cout << h_out[i];
if(i%10!=9) cout << "\t";
else cout << endl;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
__global__ void square(float *d_out, float *d_in){
int idx = blockDim.x*blockIdx.x + threadIdx.x;
float f = d_in[idx];
d_out[idx] = f*f;
}
int main(){
const int ARRAY_SIZE = 10000;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
float h_in[ARRAY_SIZE];
for(int i=0; i < ARRAY_SIZE; i++){
h_in[i] = float(i);
}
float h_out[ARRAY_SIZE];
float *d_in;
float *d_out;
hipMalloc((void**) &d_in, ARRAY_BYTES);
hipMalloc((void**) &d_out, ARRAY_BYTES);
hipMemcpy(d_in, h_in, ARRAY_BYTES, hipMemcpyHostToDevice);
int NUM_THREADS = 512;
int NUM_BLOCKS = ARRAY_SIZE / NUM_THREADS + 1;
square<<<NUM_BLOCKS, NUM_THREADS>>>(d_out, d_in);
hipMemcpy(h_out, d_out, ARRAY_BYTES, hipMemcpyDeviceToHost);
for(int i=0; i< ARRAY_SIZE; i++){
cout << h_out[i];
if(i%10!=9) cout << "\t";
else cout << endl;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6squarePfS_
.globl _Z6squarePfS_
.p2align 8
.type _Z6squarePfS_,@function
_Z6squarePfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6squarePfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6squarePfS_, .Lfunc_end0-_Z6squarePfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6squarePfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6squarePfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
__global__ void square(float *d_out, float *d_in){
int idx = blockDim.x*blockIdx.x + threadIdx.x;
float f = d_in[idx];
d_out[idx] = f*f;
}
int main(){
const int ARRAY_SIZE = 10000;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
float h_in[ARRAY_SIZE];
for(int i=0; i < ARRAY_SIZE; i++){
h_in[i] = float(i);
}
float h_out[ARRAY_SIZE];
float *d_in;
float *d_out;
hipMalloc((void**) &d_in, ARRAY_BYTES);
hipMalloc((void**) &d_out, ARRAY_BYTES);
hipMemcpy(d_in, h_in, ARRAY_BYTES, hipMemcpyHostToDevice);
int NUM_THREADS = 512;
int NUM_BLOCKS = ARRAY_SIZE / NUM_THREADS + 1;
square<<<NUM_BLOCKS, NUM_THREADS>>>(d_out, d_in);
hipMemcpy(h_out, d_out, ARRAY_BYTES, hipMemcpyDeviceToHost);
for(int i=0; i< ARRAY_SIZE; i++){
cout << h_out[i];
if(i%10!=9) cout << "\t";
else cout << endl;
}
} | .text
.file "square.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__squarePfS_ # -- Begin function _Z21__device_stub__squarePfS_
.p2align 4, 0x90
.type _Z21__device_stub__squarePfS_,@function
_Z21__device_stub__squarePfS_: # @_Z21__device_stub__squarePfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6squarePfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__squarePfS_, .Lfunc_end0-_Z21__device_stub__squarePfS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $80088, %rsp # imm = 0x138D8
.cfi_def_cfa_offset 80128
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, 40080(%rsp,%rax,4)
incq %rax
cmpq $10000, %rax # imm = 0x2710
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
movq %rsp, %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
movq 8(%rsp), %rdi
leaq 40080(%rsp), %rsi
movl $40000, %edx # imm = 0x9C40
movl $1, %ecx
callq hipMemcpy
movabsq $4294967316, %rdi # imm = 0x100000014
leaq 492(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6squarePfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
leaq 80(%rsp), %rdi
movl $40000, %edx # imm = 0x9C40
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
movabsq $-3689348814741910323, %r15 # imm = 0xCCCCCCCCCCCCCCCD
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_6: # in Loop: Header=BB1_5 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB1_12: # in Loop: Header=BB1_5 Depth=1
incq %rbx
cmpq $10000, %rbx # imm = 0x2710
je .LBB1_13
.LBB1_5: # =>This Inner Loop Header: Depth=1
movq %rbx, %rax
mulq %r15
shrq $3, %rdx
leal (%rdx,%rdx,4), %eax
leal 9(,%rax,2), %ebp
movss 80(%rsp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
cmpl %ebx, %ebp
jne .LBB1_6
# %bb.7: # in Loop: Header=BB1_5 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB1_14
# %bb.8: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_5 Depth=1
cmpb $0, 56(%r14)
je .LBB1_10
# %bb.9: # in Loop: Header=BB1_5 Depth=1
movzbl 67(%r14), %eax
jmp .LBB1_11
.LBB1_10: # in Loop: Header=BB1_5 Depth=1
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_11: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB1_5 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
jmp .LBB1_12
.LBB1_13:
xorl %eax, %eax
addq $80088, %rsp # imm = 0x138D8
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_14:
.cfi_def_cfa_offset 80128
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6squarePfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6squarePfS_,@object # @_Z6squarePfS_
.section .rodata,"a",@progbits
.globl _Z6squarePfS_
.p2align 3, 0x0
_Z6squarePfS_:
.quad _Z21__device_stub__squarePfS_
.size _Z6squarePfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\t"
.size .L.str, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6squarePfS_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__squarePfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6squarePfS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6squarePfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fcc00078e0205 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0205 */
/*0090*/ FMUL R7, R2, R2 ; /* 0x0000000202077220 */
/* 0x004fca0000400000 */
/*00a0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6squarePfS_
.globl _Z6squarePfS_
.p2align 8
.type _Z6squarePfS_,@function
_Z6squarePfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6squarePfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6squarePfS_, .Lfunc_end0-_Z6squarePfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6squarePfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6squarePfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b33b0_00000000-6_square.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z6squarePfS_PfS_
.type _Z27__device_stub__Z6squarePfS_PfS_, @function
_Z27__device_stub__Z6squarePfS_PfS_:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6squarePfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z27__device_stub__Z6squarePfS_PfS_, .-_Z27__device_stub__Z6squarePfS_PfS_
.globl _Z6squarePfS_
.type _Z6squarePfS_, @function
_Z6squarePfS_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6squarePfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z6squarePfS_, .-_Z6squarePfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\t"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
leaq -77824(%rsp), %r11
.cfi_def_cfa 11, 77872
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $2240, %rsp
.cfi_def_cfa_offset 80112
movq %fs:40, %rax
movq %rax, 80056(%rsp)
xorl %eax, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 48(%rsp,%rax,4)
addq $1, %rax
cmpq $10000, %rax
jne .L12
leaq 8(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $40000, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $20, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L13:
leaq 40048(%rsp), %rdi
movl $2, %ecx
movl $40000, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %ebx
leaq 40048(%rsp), %r12
leaq _ZSt4cout(%rip), %rbp
leaq .LC0(%rip), %r13
jmp .L20
.L25:
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z27__device_stub__Z6squarePfS_PfS_
jmp .L13
.L14:
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r14
testq %r14, %r14
je .L26
cmpb $0, 56(%r14)
je .L18
movzbl 67(%r14), %esi
.L19:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.L15:
addq $1, %rbx
cmpq $10000, %rbx
je .L27
.L20:
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movslq %ebx, %rax
imulq $1717986919, %rax, %rax
sarq $34, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,4), %eax
addl %eax, %eax
movl %ebx, %edx
subl %eax, %edx
cmpl $9, %edx
je .L14
movl $1, %edx
movq %r13, %rsi
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L15
.L26:
movq 80056(%rsp), %rax
subq %fs:40, %rax
jne .L28
call _ZSt16__throw_bad_castv@PLT
.L28:
call __stack_chk_fail@PLT
.L18:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L19
.L27:
movq 80056(%rsp), %rax
subq %fs:40, %rax
jne .L29
movl $0, %eax
addq $80064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z6squarePfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6squarePfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "square.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__squarePfS_ # -- Begin function _Z21__device_stub__squarePfS_
.p2align 4, 0x90
.type _Z21__device_stub__squarePfS_,@function
_Z21__device_stub__squarePfS_: # @_Z21__device_stub__squarePfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6squarePfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__squarePfS_, .Lfunc_end0-_Z21__device_stub__squarePfS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $80088, %rsp # imm = 0x138D8
.cfi_def_cfa_offset 80128
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, 40080(%rsp,%rax,4)
incq %rax
cmpq $10000, %rax # imm = 0x2710
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
movq %rsp, %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
movq 8(%rsp), %rdi
leaq 40080(%rsp), %rsi
movl $40000, %edx # imm = 0x9C40
movl $1, %ecx
callq hipMemcpy
movabsq $4294967316, %rdi # imm = 0x100000014
leaq 492(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6squarePfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
leaq 80(%rsp), %rdi
movl $40000, %edx # imm = 0x9C40
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
movabsq $-3689348814741910323, %r15 # imm = 0xCCCCCCCCCCCCCCCD
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_6: # in Loop: Header=BB1_5 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB1_12: # in Loop: Header=BB1_5 Depth=1
incq %rbx
cmpq $10000, %rbx # imm = 0x2710
je .LBB1_13
.LBB1_5: # =>This Inner Loop Header: Depth=1
movq %rbx, %rax
mulq %r15
shrq $3, %rdx
leal (%rdx,%rdx,4), %eax
leal 9(,%rax,2), %ebp
movss 80(%rsp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
cmpl %ebx, %ebp
jne .LBB1_6
# %bb.7: # in Loop: Header=BB1_5 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB1_14
# %bb.8: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_5 Depth=1
cmpb $0, 56(%r14)
je .LBB1_10
# %bb.9: # in Loop: Header=BB1_5 Depth=1
movzbl 67(%r14), %eax
jmp .LBB1_11
.LBB1_10: # in Loop: Header=BB1_5 Depth=1
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_11: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB1_5 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
jmp .LBB1_12
.LBB1_13:
xorl %eax, %eax
addq $80088, %rsp # imm = 0x138D8
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_14:
.cfi_def_cfa_offset 80128
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6squarePfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6squarePfS_,@object # @_Z6squarePfS_
.section .rodata,"a",@progbits
.globl _Z6squarePfS_
.p2align 3, 0x0
_Z6squarePfS_:
.quad _Z21__device_stub__squarePfS_
.size _Z6squarePfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\t"
.size .L.str, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6squarePfS_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__squarePfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6squarePfS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a9159_00000000-6_reordered.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA error : %s, %s\n"
.text
.globl _Z11check_errorPKc
.type _Z11check_errorPKc, @function
_Z11check_errorPKc:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movq %rbx, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z11check_errorPKc, .-_Z11check_errorPKc
.globl _Z41__device_stub__Z5sw4_aPdS_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_i
.type _Z41__device_stub__Z5sw4_aPdS_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_i, @function
_Z41__device_stub__Z5sw4_aPdS_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsi, 16(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
movq %rdx, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
movq %rcx, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
movq %r8, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
movq %r9, 48(%rsp)
leaq 48(%rsp), %rax
movq %rax, 184(%rsp)
movq 256(%rsp), %rax
movq %rax, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 192(%rsp)
movq 264(%rsp), %rax
movq %rax, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, 200(%rsp)
movq 272(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 208(%rsp)
leaq 280(%rsp), %rax
movq %rax, 216(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 264
pushq 88(%rsp)
.cfi_def_cfa_offset 272
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z5sw4_aPdS_S_S_S_S_S_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z41__device_stub__Z5sw4_aPdS_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_i, .-_Z41__device_stub__Z5sw4_aPdS_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_i
.globl _Z5sw4_aPdS_S_S_S_S_S_S_S_i
.type _Z5sw4_aPdS_S_S_S_S_S_S_S_i, @function
_Z5sw4_aPdS_S_S_S_S_S_S_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z41__device_stub__Z5sw4_aPdS_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_i
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z5sw4_aPdS_S_S_S_S_S_S_S_i, .-_Z5sw4_aPdS_S_S_S_S_S_S_S_i
.globl _Z41__device_stub__Z5sw4_bPdS_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_i
.type _Z41__device_stub__Z5sw4_bPdS_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_i, @function
_Z41__device_stub__Z5sw4_bPdS_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsi, 16(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
movq %rdx, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
movq %rcx, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
movq %r8, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
movq %r9, 48(%rsp)
leaq 48(%rsp), %rax
movq %rax, 184(%rsp)
movq 256(%rsp), %rax
movq %rax, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 192(%rsp)
movq 264(%rsp), %rax
movq %rax, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, 200(%rsp)
movq 272(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 208(%rsp)
leaq 280(%rsp), %rax
movq %rax, 216(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 264
pushq 88(%rsp)
.cfi_def_cfa_offset 272
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z5sw4_bPdS_S_S_S_S_S_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z41__device_stub__Z5sw4_bPdS_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_i, .-_Z41__device_stub__Z5sw4_bPdS_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_i
.globl _Z5sw4_bPdS_S_S_S_S_S_S_S_i
.type _Z5sw4_bPdS_S_S_S_S_S_S_S_i, @function
_Z5sw4_bPdS_S_S_S_S_S_S_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z41__device_stub__Z5sw4_bPdS_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_i
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z5sw4_bPdS_S_S_S_S_S_S_S_i, .-_Z5sw4_bPdS_S_S_S_S_S_S_S_i
.globl _Z41__device_stub__Z5sw4_cPdS_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_i
.type _Z41__device_stub__Z5sw4_cPdS_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_i, @function
_Z41__device_stub__Z5sw4_cPdS_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_i:
.LFB2087:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsi, 16(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
movq %rdx, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
movq %rcx, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
movq %r8, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
movq %r9, 48(%rsp)
leaq 48(%rsp), %rax
movq %rax, 184(%rsp)
movq 256(%rsp), %rax
movq %rax, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 192(%rsp)
movq 264(%rsp), %rax
movq %rax, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, 200(%rsp)
movq 272(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 208(%rsp)
leaq 280(%rsp), %rax
movq %rax, 216(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 264
pushq 88(%rsp)
.cfi_def_cfa_offset 272
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z5sw4_cPdS_S_S_S_S_S_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z41__device_stub__Z5sw4_cPdS_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_i, .-_Z41__device_stub__Z5sw4_cPdS_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_i
.globl _Z5sw4_cPdS_S_S_S_S_S_S_S_i
.type _Z5sw4_cPdS_S_S_S_S_S_S_S_i, @function
_Z5sw4_cPdS_S_S_S_S_S_S_S_i:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z41__device_stub__Z5sw4_cPdS_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_i
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z5sw4_cPdS_S_S_S_S_S_S_S_i, .-_Z5sw4_cPdS_S_S_S_S_S_S_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Failed to allocate device memory for uacc_0\n"
.align 8
.LC2:
.string "Failed to allocate device memory for uacc_1\n"
.align 8
.LC3:
.string "Failed to allocate device memory for uacc_2\n"
.align 8
.LC4:
.string "Failed to allocate device memory for u_0\n"
.align 8
.LC5:
.string "Failed to allocate device memory for u_1\n"
.align 8
.LC6:
.string "Failed to allocate device memory for u_2\n"
.align 8
.LC7:
.string "Failed to allocate device memory for mu\n"
.align 8
.LC8:
.string "Failed to allocate device memory for la\n"
.align 8
.LC9:
.string "Failed to allocate device memory for strx\n"
.align 8
.LC10:
.string "Failed to allocate device memory for stry\n"
.align 8
.LC11:
.string "Failed to allocate device memory for strz\n"
.text
.globl host_code
.type host_code, @function
host_code:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $248, %rsp
.cfi_def_cfa_offset 304
movq %rdi, (%rsp)
movq %rsi, 8(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 32(%rsp)
movq %r9, 40(%rsp)
movq 304(%rsp), %r15
movq 312(%rsp), %r14
movq 320(%rsp), %r13
movq 328(%rsp), %rax
movq %rax, 48(%rsp)
movq 336(%rsp), %rbx
movq %rbx, 56(%rsp)
movl 344(%rsp), %r12d
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
movslq %r12d, %rbp
movq %rbp, %rbx
imulq %rbp, %rbx
imulq %rbp, %rbx
salq $3, %rbx
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC1(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbx, %rdx
movq (%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
leaq 80(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC2(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
leaq 88(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC3(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
leaq 96(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC4(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq 96(%rsp), %rdi
call cudaMemcpy@PLT
leaq 104(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC5(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbx, %rdx
movq 32(%rsp), %rsi
movq 104(%rsp), %rdi
call cudaMemcpy@PLT
leaq 112(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC6(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq 112(%rsp), %rdi
call cudaMemcpy@PLT
leaq 120(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC7(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbx, %rdx
movq %r15, %rsi
movq 120(%rsp), %rdi
call cudaMemcpy@PLT
leaq 128(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC8(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 128(%rsp), %rdi
call cudaMemcpy@PLT
salq $3, %rbp
leaq 136(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq .LC9(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbp, %rdx
movq %r13, %rsi
movq 136(%rsp), %rdi
call cudaMemcpy@PLT
leaq 144(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq .LC10(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbp, %rdx
movq 48(%rsp), %rsi
movq 144(%rsp), %rdi
call cudaMemcpy@PLT
leaq 152(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq .LC11(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbp, %rdx
movq 56(%rsp), %rsi
movq 152(%rsp), %rdi
call cudaMemcpy@PLT
movl %r12d, %eax
shrl $3, %eax
movl %eax, %ebp
addl $1, %ebp
testb $7, %r12b
cmove %eax, %ebp
movl %r12d, %eax
shrl $4, %eax
movl %eax, %r13d
addl $1, %r13d
testb $15, %r12b
cmove %eax, %r13d
movl %r13d, 172(%rsp)
movl %ebp, 176(%rsp)
movl $16, 160(%rsp)
movl $8, 164(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 160(%rsp), %rdx
movl $1, %ecx
movq 172(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L41
.L36:
movl %r13d, 196(%rsp)
movl %ebp, 200(%rsp)
movl $16, 184(%rsp)
movl $8, 188(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 184(%rsp), %rdx
movl $1, %ecx
movq 196(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L42
.L37:
movl %r13d, 220(%rsp)
movl %ebp, 224(%rsp)
movl $16, 208(%rsp)
movl $8, 212(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 208(%rsp), %rdx
movl $1, %ecx
movq 220(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L43
.L38:
movl $2, %ecx
movq %rbx, %rdx
movq 72(%rsp), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 80(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 88(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 112(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rdi
call cudaFree@PLT
movq 128(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rdi
call cudaFree@PLT
movq 144(%rsp), %rdi
call cudaFree@PLT
movq 152(%rsp), %rdi
call cudaFree@PLT
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L44
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq %r12
.cfi_def_cfa_offset 312
pushq 160(%rsp)
.cfi_def_cfa_offset 320
pushq 160(%rsp)
.cfi_def_cfa_offset 328
pushq 160(%rsp)
.cfi_def_cfa_offset 336
movq 160(%rsp), %r9
movq 152(%rsp), %r8
movq 144(%rsp), %rcx
movq 136(%rsp), %rdx
movq 128(%rsp), %rsi
movq 104(%rsp), %rdi
call _Z41__device_stub__Z5sw4_aPdS_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_i
addq $32, %rsp
.cfi_def_cfa_offset 304
jmp .L36
.L42:
pushq %r12
.cfi_def_cfa_offset 312
pushq 160(%rsp)
.cfi_def_cfa_offset 320
pushq 160(%rsp)
.cfi_def_cfa_offset 328
pushq 160(%rsp)
.cfi_def_cfa_offset 336
movq 160(%rsp), %r9
movq 152(%rsp), %r8
movq 144(%rsp), %rcx
movq 136(%rsp), %rdx
movq 128(%rsp), %rsi
movq 112(%rsp), %rdi
call _Z41__device_stub__Z5sw4_bPdS_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_i
addq $32, %rsp
.cfi_def_cfa_offset 304
jmp .L37
.L43:
pushq %r12
.cfi_def_cfa_offset 312
pushq 160(%rsp)
.cfi_def_cfa_offset 320
pushq 160(%rsp)
.cfi_def_cfa_offset 328
pushq 160(%rsp)
.cfi_def_cfa_offset 336
movq 160(%rsp), %r9
movq 152(%rsp), %r8
movq 144(%rsp), %rcx
movq 136(%rsp), %rdx
movq 128(%rsp), %rsi
movq 120(%rsp), %rdi
call _Z41__device_stub__Z5sw4_cPdS_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_i
addq $32, %rsp
.cfi_def_cfa_offset 304
jmp .L38
.L44:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size host_code, .-host_code
.section .rodata.str1.1
.LC12:
.string "_Z5sw4_cPdS_S_S_S_S_S_S_S_i"
.LC13:
.string "_Z5sw4_bPdS_S_S_S_S_S_S_S_i"
.LC14:
.string "_Z5sw4_aPdS_S_S_S_S_S_S_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z5sw4_cPdS_S_S_S_S_S_S_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z5sw4_bPdS_S_S_S_S_S_S_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z5sw4_aPdS_S_S_S_S_S_S_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "reordered.hip"
.globl _Z11check_errorPKc # -- Begin function _Z11check_errorPKc
.p2align 4, 0x90
.type _Z11check_errorPKc,@function
_Z11check_errorPKc: # @_Z11check_errorPKc
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
callq hipGetLastError
testl %eax, %eax
jne .LBB0_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 16
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rbx, %rsi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end0:
.size _Z11check_errorPKc, .Lfunc_end0-_Z11check_errorPKc
.cfi_endproc
# -- End function
.globl _Z20__device_stub__sw4_aPdS_S_S_S_S_S_S_S_i # -- Begin function _Z20__device_stub__sw4_aPdS_S_S_S_S_S_S_S_i
.p2align 4, 0x90
.type _Z20__device_stub__sw4_aPdS_S_S_S_S_S_S_S_i,@function
_Z20__device_stub__sw4_aPdS_S_S_S_S_S_S_S_i: # @_Z20__device_stub__sw4_aPdS_S_S_S_S_S_S_S_i
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5sw4_aPdS_S_S_S_S_S_S_S_i, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end1:
.size _Z20__device_stub__sw4_aPdS_S_S_S_S_S_S_S_i, .Lfunc_end1-_Z20__device_stub__sw4_aPdS_S_S_S_S_S_S_S_i
.cfi_endproc
# -- End function
.globl _Z20__device_stub__sw4_bPdS_S_S_S_S_S_S_S_i # -- Begin function _Z20__device_stub__sw4_bPdS_S_S_S_S_S_S_S_i
.p2align 4, 0x90
.type _Z20__device_stub__sw4_bPdS_S_S_S_S_S_S_S_i,@function
_Z20__device_stub__sw4_bPdS_S_S_S_S_S_S_S_i: # @_Z20__device_stub__sw4_bPdS_S_S_S_S_S_S_S_i
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5sw4_bPdS_S_S_S_S_S_S_S_i, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end2:
.size _Z20__device_stub__sw4_bPdS_S_S_S_S_S_S_S_i, .Lfunc_end2-_Z20__device_stub__sw4_bPdS_S_S_S_S_S_S_S_i
.cfi_endproc
# -- End function
.globl _Z20__device_stub__sw4_cPdS_S_S_S_S_S_S_S_i # -- Begin function _Z20__device_stub__sw4_cPdS_S_S_S_S_S_S_S_i
.p2align 4, 0x90
.type _Z20__device_stub__sw4_cPdS_S_S_S_S_S_S_S_i,@function
_Z20__device_stub__sw4_cPdS_S_S_S_S_S_S_S_i: # @_Z20__device_stub__sw4_cPdS_S_S_S_S_S_S_S_i
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5sw4_cPdS_S_S_S_S_S_S_S_i, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end3:
.size _Z20__device_stub__sw4_cPdS_S_S_S_S_S_S_S_i, .Lfunc_end3-_Z20__device_stub__sw4_cPdS_S_S_S_S_S_S_S_i
.cfi_endproc
# -- End function
.globl host_code # -- Begin function host_code
.p2align 4, 0x90
.type host_code,@function
host_code: # @host_code
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $344, %rsp # imm = 0x158
.cfi_def_cfa_offset 400
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, 336(%rsp) # 8-byte Spill
movq %r8, %rbx
movq %rcx, %r15
movq %rdx, 312(%rsp) # 8-byte Spill
movq %rsi, 320(%rsp) # 8-byte Spill
movq %rdi, %r12
movslq 440(%rsp), %rbp
leaq (,%rbp,8), %r13
movq %rbp, %r14
imulq %rbp, %r14
imulq %r13, %r14
leaq 216(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB4_1
# %bb.3: # %_Z11check_errorPKc.exit
movq 216(%rsp), %rdi
movq %r12, 328(%rsp) # 8-byte Spill
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 208(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB4_4
# %bb.5: # %_Z11check_errorPKc.exit122
movq 208(%rsp), %rdi
movq 320(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 200(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB4_6
# %bb.7: # %_Z11check_errorPKc.exit124
movq 200(%rsp), %rdi
movq 312(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 72(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB4_8
# %bb.9: # %_Z11check_errorPKc.exit126
movq 72(%rsp), %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 64(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB4_10
# %bb.11: # %_Z11check_errorPKc.exit128
movq 64(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 56(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB4_12
# %bb.13: # %_Z11check_errorPKc.exit130
movq 56(%rsp), %rdi
movq 336(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 48(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB4_14
# %bb.15: # %_Z11check_errorPKc.exit132
movq 400(%rsp), %rsi
movq 48(%rsp), %rdi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 40(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB4_16
# %bb.17: # %_Z11check_errorPKc.exit134
movq 408(%rsp), %rsi
movq 40(%rsp), %rdi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 32(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB4_18
# %bb.19: # %_Z11check_errorPKc.exit136
movq 416(%rsp), %rsi
movq 32(%rsp), %rdi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB4_20
# %bb.21: # %_Z11check_errorPKc.exit138
movq %rbp, %rbx
movq 424(%rsp), %rsi
movq 24(%rsp), %rdi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB4_22
# %bb.23: # %_Z11check_errorPKc.exit140
movq 432(%rsp), %rsi
movabsq $34359738384, %rbp # imm = 0x800000010
movq 16(%rsp), %rdi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq %rbx, %rcx
movl %ecx, %r15d
shrl $4, %r15d
leal 1(%r15), %ebx
testb $15, %cl
movl %ebx, %eax
cmovel %r15d, %eax
movl %ecx, %r12d
shrl $3, %r12d
leal 1(%r12), %r13d
testb $7, %cl
movl %r13d, %edi
cmovel %r12d, %edi
shlq $32, %rdi
orq %rax, %rdi
movl $1, %esi
movq %rbp, %rdx
movq %rcx, %rbp
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_25
# %bb.24:
movq 216(%rsp), %rax
movq 72(%rsp), %rcx
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
movq 40(%rsp), %r8
movq 32(%rsp), %r9
movq 24(%rsp), %r10
movq 16(%rsp), %r11
movq %rax, 192(%rsp)
movq %rcx, 184(%rsp)
movq %rdx, 176(%rsp)
movq %rsi, 168(%rsp)
movq %rdi, 160(%rsp)
movq %r8, 152(%rsp)
movq %r9, 144(%rsp)
movq %r10, 136(%rsp)
movq %r11, 128(%rsp)
movl %ebp, 12(%rsp)
leaq 192(%rsp), %rax
movq %rax, 224(%rsp)
leaq 184(%rsp), %rax
movq %rax, 232(%rsp)
leaq 176(%rsp), %rax
movq %rax, 240(%rsp)
leaq 168(%rsp), %rax
movq %rax, 248(%rsp)
leaq 160(%rsp), %rax
movq %rax, 256(%rsp)
leaq 152(%rsp), %rax
movq %rax, 264(%rsp)
leaq 144(%rsp), %rax
movq %rax, 272(%rsp)
leaq 136(%rsp), %rax
movq %rax, 280(%rsp)
leaq 128(%rsp), %rax
movq %rax, 288(%rsp)
leaq 12(%rsp), %rax
movq %rax, 296(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 224(%rsp), %r9
movl $_Z5sw4_aPdS_S_S_S_S_S_S_S_i, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_25:
testb $15, %bpl
movl %ebx, %eax
cmovel %r15d, %eax
testb $7, %bpl
movl %r13d, %edi
cmovel %r12d, %edi
shlq $32, %rdi
orq %rax, %rdi
movl $1, %esi
movabsq $34359738384, %rdx # imm = 0x800000010
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_27
# %bb.26:
movq 208(%rsp), %rax
movq 72(%rsp), %rcx
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
movq 40(%rsp), %r8
movq 32(%rsp), %r9
movq 24(%rsp), %r10
movq 16(%rsp), %r11
movq %rax, 192(%rsp)
movq %rcx, 184(%rsp)
movq %rdx, 176(%rsp)
movq %rsi, 168(%rsp)
movq %rdi, 160(%rsp)
movq %r8, 152(%rsp)
movq %r9, 144(%rsp)
movq %r10, 136(%rsp)
movq %r11, 128(%rsp)
movl %ebp, 12(%rsp)
leaq 192(%rsp), %rax
movq %rax, 224(%rsp)
leaq 184(%rsp), %rax
movq %rax, 232(%rsp)
leaq 176(%rsp), %rax
movq %rax, 240(%rsp)
leaq 168(%rsp), %rax
movq %rax, 248(%rsp)
leaq 160(%rsp), %rax
movq %rax, 256(%rsp)
leaq 152(%rsp), %rax
movq %rax, 264(%rsp)
leaq 144(%rsp), %rax
movq %rax, 272(%rsp)
leaq 136(%rsp), %rax
movq %rax, 280(%rsp)
leaq 128(%rsp), %rax
movq %rax, 288(%rsp)
leaq 12(%rsp), %rax
movq %rax, 296(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 224(%rsp), %r9
movl $_Z5sw4_bPdS_S_S_S_S_S_S_S_i, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_27:
testb $15, %bpl
cmovel %r15d, %ebx
testb $7, %bpl
cmovel %r12d, %r13d
shlq $32, %r13
orq %rbx, %r13
movq %r13, %rdi
movl $1, %esi
movabsq $34359738384, %rdx # imm = 0x800000010
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_29
# %bb.28:
movq 200(%rsp), %rax
movq 72(%rsp), %rcx
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
movq 40(%rsp), %r8
movq 32(%rsp), %r9
movq 24(%rsp), %r10
movq 16(%rsp), %r11
movq %rax, 192(%rsp)
movq %rcx, 184(%rsp)
movq %rdx, 176(%rsp)
movq %rsi, 168(%rsp)
movq %rdi, 160(%rsp)
movq %r8, 152(%rsp)
movq %r9, 144(%rsp)
movq %r10, 136(%rsp)
movq %r11, 128(%rsp)
movl %ebp, 12(%rsp)
leaq 192(%rsp), %rax
movq %rax, 224(%rsp)
leaq 184(%rsp), %rax
movq %rax, 232(%rsp)
leaq 176(%rsp), %rax
movq %rax, 240(%rsp)
leaq 168(%rsp), %rax
movq %rax, 248(%rsp)
leaq 160(%rsp), %rax
movq %rax, 256(%rsp)
leaq 152(%rsp), %rax
movq %rax, 264(%rsp)
leaq 144(%rsp), %rax
movq %rax, 272(%rsp)
leaq 136(%rsp), %rax
movq %rax, 280(%rsp)
leaq 128(%rsp), %rax
movq %rax, 288(%rsp)
leaq 12(%rsp), %rax
movq %rax, 296(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 224(%rsp), %r9
movl $_Z5sw4_cPdS_S_S_S_S_S_S_S_i, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_29:
movq 216(%rsp), %rsi
movq 328(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 208(%rsp), %rsi
movq 320(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 200(%rsp), %rsi
movq 312(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 216(%rsp), %rdi
callq hipFree
movq 208(%rsp), %rdi
callq hipFree
movq 200(%rsp), %rdi
callq hipFree
movq 72(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
addq $344, %rsp # imm = 0x158
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_1:
.cfi_def_cfa_offset 400
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
jmp .LBB4_2
.LBB4_4:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.2, %esi
jmp .LBB4_2
.LBB4_6:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.3, %esi
jmp .LBB4_2
.LBB4_8:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.4, %esi
jmp .LBB4_2
.LBB4_10:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.5, %esi
jmp .LBB4_2
.LBB4_12:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.6, %esi
jmp .LBB4_2
.LBB4_14:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.7, %esi
jmp .LBB4_2
.LBB4_16:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.8, %esi
jmp .LBB4_2
.LBB4_18:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.9, %esi
jmp .LBB4_2
.LBB4_20:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.10, %esi
jmp .LBB4_2
.LBB4_22:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.11, %esi
.LBB4_2:
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end4:
.size host_code, .Lfunc_end4-host_code
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5sw4_aPdS_S_S_S_S_S_S_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5sw4_bPdS_S_S_S_S_S_S_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5sw4_cPdS_S_S_S_S_S_S_S_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA error : %s, %s\n"
.size .L.str, 21
.type _Z5sw4_aPdS_S_S_S_S_S_S_S_i,@object # @_Z5sw4_aPdS_S_S_S_S_S_S_S_i
.section .rodata,"a",@progbits
.globl _Z5sw4_aPdS_S_S_S_S_S_S_S_i
.p2align 3, 0x0
_Z5sw4_aPdS_S_S_S_S_S_S_S_i:
.quad _Z20__device_stub__sw4_aPdS_S_S_S_S_S_S_S_i
.size _Z5sw4_aPdS_S_S_S_S_S_S_S_i, 8
.type _Z5sw4_bPdS_S_S_S_S_S_S_S_i,@object # @_Z5sw4_bPdS_S_S_S_S_S_S_S_i
.globl _Z5sw4_bPdS_S_S_S_S_S_S_S_i
.p2align 3, 0x0
_Z5sw4_bPdS_S_S_S_S_S_S_S_i:
.quad _Z20__device_stub__sw4_bPdS_S_S_S_S_S_S_S_i
.size _Z5sw4_bPdS_S_S_S_S_S_S_S_i, 8
.type _Z5sw4_cPdS_S_S_S_S_S_S_S_i,@object # @_Z5sw4_cPdS_S_S_S_S_S_S_S_i
.globl _Z5sw4_cPdS_S_S_S_S_S_S_S_i
.p2align 3, 0x0
_Z5sw4_cPdS_S_S_S_S_S_S_S_i:
.quad _Z20__device_stub__sw4_cPdS_S_S_S_S_S_S_S_i
.size _Z5sw4_cPdS_S_S_S_S_S_S_S_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Failed to allocate device memory for uacc_0\n"
.size .L.str.1, 45
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Failed to allocate device memory for uacc_1\n"
.size .L.str.2, 45
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Failed to allocate device memory for uacc_2\n"
.size .L.str.3, 45
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Failed to allocate device memory for u_0\n"
.size .L.str.4, 42
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Failed to allocate device memory for u_1\n"
.size .L.str.5, 42
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Failed to allocate device memory for u_2\n"
.size .L.str.6, 42
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Failed to allocate device memory for mu\n"
.size .L.str.7, 41
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Failed to allocate device memory for la\n"
.size .L.str.8, 41
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Failed to allocate device memory for strx\n"
.size .L.str.9, 43
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Failed to allocate device memory for stry\n"
.size .L.str.10, 43
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Failed to allocate device memory for strz\n"
.size .L.str.11, 43
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5sw4_aPdS_S_S_S_S_S_S_S_i"
.size .L__unnamed_1, 28
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z5sw4_bPdS_S_S_S_S_S_S_S_i"
.size .L__unnamed_2, 28
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z5sw4_cPdS_S_S_S_S_S_S_S_i"
.size .L__unnamed_3, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__sw4_aPdS_S_S_S_S_S_S_S_i
.addrsig_sym _Z20__device_stub__sw4_bPdS_S_S_S_S_S_S_S_i
.addrsig_sym _Z20__device_stub__sw4_cPdS_S_S_S_S_S_S_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5sw4_aPdS_S_S_S_S_S_S_S_i
.addrsig_sym _Z5sw4_bPdS_S_S_S_S_S_S_S_i
.addrsig_sym _Z5sw4_cPdS_S_S_S_S_S_S_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #define THREADS_PER_BLOCK 128
#include <cmath>
#include <chrono>
#include <cstring>
#include <fstream>
#include <iostream>
#include <stdexcept>
#include "tiffio.h"
// saves TIFF file from data in `raster`
void save_tiff(const char *fname, uint32 *raster, uint32 w, uint32 h) {
TIFF *tif = TIFFOpen(fname, "w");
if (! raster) {
throw std::runtime_error("Could not open output file");
}
TIFFSetField(tif, TIFFTAG_IMAGEWIDTH, w);
TIFFSetField(tif, TIFFTAG_IMAGELENGTH, h);
TIFFSetField(tif, TIFFTAG_SAMPLESPERPIXEL, 4);
TIFFSetField(tif, TIFFTAG_BITSPERSAMPLE, 8);
TIFFSetField(tif, TIFFTAG_COMPRESSION, COMPRESSION_DEFLATE);
TIFFSetField(tif, TIFFTAG_ORIENTATION, ORIENTATION_TOPLEFT);
TIFFSetField(tif, TIFFTAG_PHOTOMETRIC, PHOTOMETRIC_RGB);
TIFFSetField(tif, TIFFTAG_PLANARCONFIG, PLANARCONFIG_CONTIG);
TIFFWriteEncodedStrip(tif, 0, raster, w*h*4);
TIFFClose(tif);
}
// loads image data from `fname` (allocating dynamic memory)
// *w and *h are updated with the image dimensions
// raster is a matrix flattened into an array using row-major order
// every uint32 in the array is 4 bytes, enconding 8-bit packed ABGR
// A: transparency attribute (can be ignored)
// B: blue pixel
// G: green pixel
// R: red pixel
uint32 *load_tiff(const char *fname, uint32 *w, uint32 *h) {
TIFF *tif = TIFFOpen(fname, "r");
if (! tif) {
throw std::runtime_error("Could not open input file");
}
TIFFGetField(tif, TIFFTAG_IMAGEWIDTH, w);
TIFFGetField(tif, TIFFTAG_IMAGELENGTH, h);
uint32 *raster = (uint32 *) _TIFFmalloc(*w * *h * sizeof (uint32));
if (! raster) {
TIFFClose(tif);
throw std::runtime_error("Memory allocation error");
}
if (! TIFFReadRGBAImageOriented(tif, *w, *h, raster, ORIENTATION_TOPLEFT, 0)) {
TIFFClose(tif);
throw std::runtime_error("Could not read raster from TIFF image");
}
TIFFClose(tif);
return raster;
}
void clamp(float *val) {
if (*val < 0) *val = 0;
if (*val > 255) *val = 255;
}
__device__ void cuda_clamp(float *val) {
if (*val < 0) *val = 0;
if (*val > 255) *val = 255;
}
void filter_image_seq(uint32 *raster, uint32 w, uint32 h, const float *filter, int f_len) {
// to get RGB values from a pixel, you can either use bitwise masks
// or rely on the following macros:
// TIFFGetR(raster[i]) red
// TIFFGetG(raster[i]) green
// TIFFGetB(raster[i]) blue
// TIFFGetA(raster[i]) this value should be ignored
//
// to modify RGB values from a pixel, you can use bitwise shifts or masks
// each pixel stores values in the order ABGR
//
// TODO: here you will filter the image in raster
//
uint32 *copy = new uint32[w*h];
std::memcpy(copy, raster, sizeof(uint32)*w*h);
uint32 d = (uint32) std::sqrt(f_len);
uint32 idx, pixel;
uint32 st = d / 2;
uint32 end_w = w - d/2;
uint32 end_h = h - d/2;
float sumR, sumG, sumB;
// applies filter
for (uint32 i = st ; i < end_h ; i++) {
for (uint32 j = st ; j < end_w ; j++) {
sumR = sumG = sumB = 0;
for (uint32 k = 0 ; k < d ; k ++) {
idx = (i-st+k)*w + (j-st);
for (uint32 l = 0 ; l < d ; l++) {
pixel = copy[idx++];
sumR += (filter[k*d + l] * TIFFGetR(pixel));
sumG += (filter[k*d + l] * TIFFGetG(pixel));
sumB += (filter[k*d + l] * TIFFGetB(pixel));
}
}
clamp(&sumR);
clamp(&sumG);
clamp(&sumB);
raster[i*w + j] = TIFFGetA(raster[i*w + j]) << 24 | ((uint32) sumB << 16) | ((uint32) sumG << 8) | ((uint32) sumR);
}
}
delete [] copy;
}
__global__ void filter_image_cuda(uint32 *raster, uint32 *copy, uint32 w, uint32 h, const float *filter, int f_len, uint32 d, uint32 st, uint32 end_w, uint32 end_h) {
// applies filter
// Start Indices
uint32 start_i = (blockIdx.y * blockDim.y) + threadIdx.y + st;
uint32 start_j = (blockIdx.x * blockDim.x) + threadIdx.x + st;
uint32 idx, pixel;
float sumR, sumG, sumB;
// applies filter
for (uint32 i = start_i ; i < end_h ; i++) {
for (uint32 j = start_j ; j < end_w ; j++) {
sumR = sumG = sumB = 0;
for (uint32 k = 0 ; k < d ; k ++) {
idx = (i-st+k)*w + (j-st);
for (uint32 l = 0 ; l < d ; l++) {
pixel = copy[idx++];
sumR += (filter[k*d + l] * TIFFGetR(pixel));
sumG += (filter[k*d + l] * TIFFGetG(pixel));
sumB += (filter[k*d + l] * TIFFGetB(pixel));
}
}
cuda_clamp(&sumR);
cuda_clamp(&sumG);
cuda_clamp(&sumB);
raster[i*w + j] = TIFFGetA(raster[i*w + j]) << 24 | ((uint32) sumB << 16) | ((uint32) sumG << 8) | ((uint32) sumR);
}
}
}
void filter_image_par(uint32 *raster, uint32 w, uint32 h, const float *filter, int f_len, int n_threads, int n_blocks) {
//
// TODO: here you will filter the image in raster using GPU threads
//
// Consistent Computations
uint32 d = (uint32) std::sqrt(f_len);
uint32 st = d / 2;
uint32 end_w = w - d/2;
uint32 end_h = h - d/2;
uint32 n = w*h;
// Create Blocks and threads
dim3 threadsPerBlock(n_threads, n_threads, 1);
dim3 numBlocks(n_blocks,n_blocks,1);
// create pointers for the CUDA arrays
uint32 *copy_in;
uint32 *raster_out;
float *filter_in;
// variable to check for CUDA errors
cudaError_t status;
// choose GPU to run
status = cudaSetDevice(0);
if (status != cudaSuccess) std::cerr << "cudaSetDevice failed!" << std::endl;
// allocate space for the arrays in the GPU
status = cudaMalloc(©_in, sizeof(uint32) * n);
if (status != cudaSuccess) std::cerr << "cudaMalloc (copy_in) failed!" << std::endl;
status = cudaMalloc(&raster_out, sizeof(uint32) * n);
if (status != cudaSuccess) std::cerr << "cudaMalloc (raster_out) failed!" << std::endl;
status = cudaMalloc(&filter_in, sizeof(float) * f_len);
if (status != cudaSuccess) std::cerr << "cudaMalloc (filter) failed!" << std::endl;
// transfer data from CPU to GPU
status = cudaMemcpy(copy_in, raster, sizeof(uint32) * n, cudaMemcpyHostToDevice);
if (status != cudaSuccess) std::cerr << "cudaMemcpy H2D failed! - copy" << std::endl;
status = cudaMemcpy(raster_out, raster, sizeof(uint32) * n, cudaMemcpyHostToDevice);
if (status != cudaSuccess) std::cerr << "cudaMemcpy H2D failed! - raster" << std::endl;
status = cudaMemcpy(filter_in, filter, sizeof(float) * f_len, cudaMemcpyHostToDevice);
if (status != cudaSuccess) std::cerr << "cudaMemcpy H2D failed! - filter" << std::endl;
// Do the work in the GPU
//std::cout << "Blocks: " << std::ceil((float)n/THREADS_PER_BLOCK) << std::endl;
filter_image_cuda<<<numBlocks,threadsPerBlock>>>(raster_out, copy_in, w, h, filter_in, f_len, d, st, end_w, end_h);
// wait for the kernel to finish, and check for errors
status = cudaThreadSynchronize();
if (status != cudaSuccess) std::cerr << "error code " << status << " returned after kernel!" << std::endl;
// transfer results from GPU to CPU
status = cudaMemcpy(raster, raster_out, sizeof(uint32) * n, cudaMemcpyDeviceToHost);
if (status != cudaSuccess) std::cerr << "cudaMemcpy D2H failed! - final" << std::endl;
// Free memory
cudaFree(copy_in);
cudaFree(raster_out);
cudaFree(filter_in);
}
float *load_filter(const char *fname, int *n) {
std::ifstream myfile(fname);
if (! myfile) {
throw std::runtime_error("Could not open filter file");
}
myfile >> *n;
float *filter = new float[*n];
for (int i = 0 ; i < *n ; i++) myfile >> filter[i];
myfile.close();
return filter;
}
int main(int argc, char* argv[]) {
if (argc != 7) {
std::cout << "Usage:\t./filter <in_fname> <out_fname> <filter_fname> <algo>" << std::endl;
std::cout << "<in_fname> path to the input image" << std::endl;
std::cout << "<out_fname> path to the output image" << std::endl;
std::cout << "<filter_fname> path to the filter file" << std::endl;
std::cout << "<algo> whether to use the sequential (seq) or parallel algorithm (par)" << std::endl;
std::cout << "<n_threads> number of threads to use (Ex: enter 5 for 25 threads/block)" << std::endl;
std::cout << "<n_blocks> number of blocks to use [Ex: enter 2 for 4 blocks]" << std::endl;
return 0;
}
uint32 width, height;
int n_threads = std::stoi(argv[5]);
int n_blocks = std::stoi(argv[6]);
// loads the filter
int f_len;
float *filter = load_filter(argv[3], &f_len);
// loads image bytes from file name supplied as a command line argument
// this function allocates memory dynamically
uint32 *image = load_tiff(argv[1], &width, &height);
// measure time of the algorithm
auto start = std::chrono::high_resolution_clock::now();
if (! std::strcmp(argv[4], "seq")) {
// call the sequential implementation
filter_image_seq(image, width, height, filter, f_len);
} else if (! std::strcmp(argv[4], "par")) {
// TODO: call the parallel implementation
filter_image_par(image, width, height, filter, f_len, n_threads, n_blocks);
}
auto end = std::chrono::high_resolution_clock::now();
std::chrono::duration<double> diff = end - start;
std::cout << diff.count() << std::endl;
// save new file with filtered image
save_tiff(argv[2], image, width, height);
// frees memory allocated by load_filter and load_tiff
delete [] filter;
_TIFFfree(image);
return 0;
} | code for sm_80
Function : _Z17filter_image_cudaPjS_jjPKfijjjj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002200 */
/*0030*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ IADD3 R3, R0, c[0x0][0x188], RZ ; /* 0x0000620000037a10 */
/* 0x000fc80007ffe0ff */
/*0050*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x190], PT ; /* 0x0000640003007a0c */
/* 0x000fda0003f06070 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0080*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff067624 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00a0*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e640000002100 */
/*00b0*/ IADD3 R8, R6, -0x1, RZ ; /* 0xffffffff06087810 */
/* 0x000fc80007ffe0ff */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R8, 0x3, PT ; /* 0x000000030800780c */
/* 0x000fe20003f06070 */
/*00d0*/ IMAD R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a24 */
/* 0x001fca00078e02ff */
/*00e0*/ LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff027212 */
/* 0x000fe400078e33ff */
/*00f0*/ IADD3 R5, -R7.reuse, c[0x0][0x18c], -R0 ; /* 0x0000630007057a10 */
/* 0x042fe40007ffe900 */
/*0100*/ IADD3 R2, -R7, c[0x0][0x18c], R2 ; /* 0x0000630007027a10 */
/* 0x000fe40007ffe102 */
/*0110*/ IADD3 R0, R0, c[0x0][0x188], R7 ; /* 0x0000620000007a10 */
/* 0x000fe40007ffe007 */
/*0120*/ IADD3 R4, R2, -c[0x0][0x188], RZ ; /* 0x8000620002047a10 */
/* 0x000fe40007ffe0ff */
/*0130*/ LOP3.LUT R2, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306027812 */
/* 0x000fc400078ec0ff */
/*0140*/ IADD3 R7, R5, -c[0x0][0x188], RZ ; /* 0x8000620005077a10 */
/* 0x000fe40007ffe0ff */
/*0150*/ ISETP.GE.U32.AND P1, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f26070 */
/*0160*/ IADD3 R4, R2, -c[0x0][0x184], RZ ; /* 0x8000610002047a10 */
/* 0x000fe40007ffe0ff */
/*0170*/ IADD3 R6, R0.reuse, 0x1, RZ ; /* 0x0000000100067810 */
/* 0x040fe40007ffe0ff */
/*0180*/ IADD3 R8, R0.reuse, 0x2, RZ ; /* 0x0000000200087810 */
/* 0x040fe40007ffe0ff */
/*0190*/ IADD3 R5, R0, 0x3, RZ ; /* 0x0000000300057810 */
/* 0x000fc40007ffe0ff */
/*01a0*/ LOP3.LUT R7, R7, 0x3, RZ, 0xc0, !PT ; /* 0x0000000307077812 */
/* 0x000fe400078ec0ff */
/*01b0*/ ISETP.GE.U32.AND P2, PT, R0, c[0x0][0x18c], PT ; /* 0x0000630000007a0c */
/* 0x000fe20003f46070 */
/*01c0*/ BSSY B0, 0xe00 ; /* 0x00000c3000007945 */
/* 0x000fd80003800000 */
/*01d0*/ @P2 BRA 0xdf0 ; /* 0x00000c1000002947 */
/* 0x003fea0003800000 */
/*01e0*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x184], PT ; /* 0x00006100ff007a0c */
/* 0x000fda0003f45270 */
/*01f0*/ @!P2 BRA 0xaa0 ; /* 0x000008a00000a947 */
/* 0x000fea0003800000 */
/*0200*/ IADD3 R9, R3, -c[0x0][0x188], RZ ; /* 0x8000620003097a10 */
/* 0x000fe20007ffe0ff */
/*0210*/ IMAD.MOV.U32 R10, RZ, RZ, R0 ; /* 0x000000ffff0a7224 */
/* 0x000fc800078e0000 */
/*0220*/ HFMA2.MMA R29, -RZ, RZ, 0, 0 ; /* 0x00000000ff1d7435 */
/* 0x000fe200000001ff */
/*0230*/ IADD3 R11, R10, -c[0x0][0x188], RZ ; /* 0x800062000a0b7a10 */
/* 0x001fe20007ffe0ff */
/*0240*/ CS2R R26, SRZ ; /* 0x00000000001a7805 */
/* 0x000fe2000001ff00 */
/*0250*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fc800078e00ff */
/*0260*/ IMAD.IADD R12, R9, 0x1, R14.reuse ; /* 0x00000001090c7824 */
/* 0x100fe400078e020e */
/*0270*/ IMAD.MOV.U32 R15, RZ, RZ, R14 ; /* 0x000000ffff0f7224 */
/* 0x000fe200078e000e */
/*0280*/ IADD3 R14, R14, 0x1, RZ ; /* 0x000000010e0e7810 */
/* 0x000fe20007ffe0ff */
/*0290*/ IMAD.MOV.U32 R23, RZ, RZ, RZ ; /* 0x000000ffff177224 */
/* 0x000fe400078e00ff */
/*02a0*/ IMAD R19, R12, c[0x0][0x170], R11 ; /* 0x00005c000c137a24 */
/* 0x000fe200078e020b */
/*02b0*/ ISETP.GE.U32.AND P2, PT, R14, c[0x0][0x184], PT ; /* 0x000061000e007a0c */
/* 0x000fe20003f46070 */
/*02c0*/ @!P0 BRA 0x670 ; /* 0x000003a000008947 */
/* 0x000fea0003800000 */
/*02d0*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff0c7624 */
/* 0x000fe200078e00ff */
/*02e0*/ MOV R13, R19 ; /* 0x00000013000d7202 */
/* 0x000fe20000000f00 */
/*02f0*/ IMAD.MOV.U32 R23, RZ, RZ, RZ ; /* 0x000000ffff177224 */
/* 0x000fc400078e00ff */
/*0300*/ IMAD R12, R15, R12, 0x3 ; /* 0x000000030f0c7424 */
/* 0x000fc600078e020c */
/*0310*/ IMAD.MOV.U32 R22, RZ, RZ, 0x4 ; /* 0x00000004ff167424 */
/* 0x000fc800078e00ff */
/*0320*/ IMAD.WIDE.U32 R24, R13, R22, c[0x0][0x168] ; /* 0x00005a000d187625 */
/* 0x000fe200078e0016 */
/*0330*/ IADD3 R17, R12, -0x3, RZ ; /* 0xfffffffd0c117810 */
/* 0x000fca0007ffe0ff */
/*0340*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x0000a2000c1e1900 */
/*0350*/ IMAD.WIDE.U32 R16, R17, R22, c[0x0][0x178] ; /* 0x00005e0011107625 */
/* 0x000fcc00078e0016 */
/*0360*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0004e2000c1e1900 */
/*0370*/ IADD3 R19, R13, 0x1, RZ ; /* 0x000000010d137810 */
/* 0x000fca0007ffe0ff */
/*0380*/ IMAD.WIDE.U32 R18, R19, R22, c[0x0][0x168] ; /* 0x00005a0013127625 */
/* 0x000fca00078e0016 */
/*0390*/ LDG.E R28, [R18.64] ; /* 0x00000004121c7981 */
/* 0x000322000c1e1900 */
/*03a0*/ IADD3 R21, R12, -0x2, RZ ; /* 0xfffffffe0c157810 */
/* 0x000fca0007ffe0ff */
/*03b0*/ IMAD.WIDE.U32 R20, R21, R22, c[0x0][0x178] ; /* 0x00005e0015147625 */
/* 0x000fca00078e0016 */
/*03c0*/ LDG.E R24, [R20.64] ; /* 0x0000000414187981 */
/* 0x001162000c1e1900 */
/*03d0*/ I2F.U8 R17, R25 ; /* 0x0000001900117306 */
/* 0x004ef00000001000 */
/*03e0*/ I2F.U8 R19, R25.B2 ; /* 0x2000001900137306 */
/* 0x002e620000001000 */
/*03f0*/ FFMA R29, R17, R16, R29 ; /* 0x00000010111d7223 */
/* 0x008fce000000001d */
/*0400*/ I2F.U8 R17, R25.B1 ; /* 0x1000001900117306 */
/* 0x0002b00000001000 */
/*0410*/ I2F.U8 R18, R28 ; /* 0x0000001c00127306 */
/* 0x010f620000001000 */
/*0420*/ FFMA R25, R16.reuse, R19, R27 ; /* 0x0000001310197223 */
/* 0x042fe4000000001b */
/*0430*/ FFMA R26, R16, R17, R26 ; /* 0x00000011101a7223 */
/* 0x004fe2000000001a */
/*0440*/ IADD3 R17, R13, 0x2, RZ ; /* 0x000000020d117810 */
/* 0x000fc80007ffe0ff */
/*0450*/ I2F.U8 R21, R28.B1 ; /* 0x1000001c00157306 */
/* 0x001e220000001000 */
/*0460*/ IMAD.WIDE.U32 R16, R17, R22, c[0x0][0x168] ; /* 0x00005a0011107625 */
/* 0x000fe200078e0016 */
/*0470*/ IADD3 R19, R12, -0x1, RZ ; /* 0xffffffff0c137810 */
/* 0x000fca0007ffe0ff */
/*0480*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0000a2000c1e1900 */
/*0490*/ FFMA R29, R18, R24, R29 ; /* 0x00000018121d7223 */
/* 0x020fe2000000001d */
/*04a0*/ IADD3 R27, R13, 0x3, RZ ; /* 0x000000030d1b7810 */
/* 0x000fe20007ffe0ff */
/*04b0*/ IMAD.WIDE.U32 R18, R19, R22, c[0x0][0x178] ; /* 0x00005e0013127625 */
/* 0x000fcc00078e0016 */
/*04c0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0002e2000c1e1900 */
/*04d0*/ FFMA R17, R24, R21, R26 ; /* 0x0000001518117223 */
/* 0x001fe4000000001a */
/*04e0*/ IMAD.WIDE.U32 R20, R27, R22, c[0x0][0x168] ; /* 0x00005a001b147625 */
/* 0x000fcc00078e0016 */
/*04f0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000f22000c1e1900 */
/*0500*/ IMAD.WIDE.U32 R26, R12, R22, c[0x0][0x178] ; /* 0x00005e000c1a7625 */
/* 0x000fcc00078e0016 */
/*0510*/ LDG.E R27, [R26.64] ; /* 0x000000041a1b7981 */
/* 0x000762000c1e1900 */
/*0520*/ I2F.U8 R28, R28.B2 ; /* 0x2000001c001c7306 */
/* 0x000e220000001000 */
/*0530*/ IADD3 R23, R23, 0x4, RZ ; /* 0x0000000417177810 */
/* 0x000fe40007ffe0ff */
/*0540*/ IADD3 R13, R13, 0x4, RZ ; /* 0x000000040d0d7810 */
/* 0x000fe40007ffe0ff */
/*0550*/ IADD3 R12, R12, 0x4, RZ ; /* 0x000000040c0c7810 */
/* 0x000fe20007ffe0ff */
/*0560*/ FFMA R25, R24, R28, R25 ; /* 0x0000001c18197223 */
/* 0x001fe40000000019 */
/*0570*/ I2F.U8 R22, R16 ; /* 0x0000001000167306 */
/* 0x004ef00000001000 */
/*0580*/ I2F.U8 R24, R16.B1 ; /* 0x1000001000187306 */
/* 0x000e300000001000 */
/*0590*/ I2F.U8 R19, R16.B2 ; /* 0x2000001000137306 */
/* 0x002e620000001000 */
/*05a0*/ FFMA R26, R22, R18, R29 ; /* 0x00000012161a7223 */
/* 0x008fc4000000001d */
/*05b0*/ FFMA R22, R18, R24, R17 ; /* 0x0000001812167223 */
/* 0x001fca0000000011 */
/*05c0*/ I2F.U8 R29, R20 ; /* 0x00000014001d7306 */
/* 0x010f620000001000 */
/*05d0*/ FFMA R19, R18, R19, R25 ; /* 0x0000001312137223 */
/* 0x002fce0000000019 */
/*05e0*/ I2F.U8 R17, R20.B1 ; /* 0x1000001400117306 */
/* 0x000e220000001000 */
/*05f0*/ IMAD.IADD R18, R4, 0x1, R23 ; /* 0x0000000104127824 */
/* 0x000fca00078e0217 */
/*0600*/ ISETP.NE.AND P3, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fe40003f65270 */
/*0610*/ I2F.U8 R24, R20.B2 ; /* 0x2000001400187306 */
/* 0x000e620000001000 */
/*0620*/ FFMA R29, R29, R27, R26 ; /* 0x0000001b1d1d7223 */
/* 0x020fe4000000001a */
/*0630*/ FFMA R26, R27.reuse, R17, R22 ; /* 0x000000111b1a7223 */
/* 0x041fe40000000016 */
/*0640*/ FFMA R27, R27, R24, R19 ; /* 0x000000181b1b7223 */
/* 0x002fcc0000000013 */
/*0650*/ @P3 BRA 0x310 ; /* 0xfffffcb000003947 */
/* 0x000fea000383ffff */
/*0660*/ MOV R19, R13 ; /* 0x0000000d00137202 */
/* 0x000fe40000000f00 */
/*0670*/ ISETP.NE.AND P3, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f65270 */
/*0680*/ @!P3 BRA 0x900 ; /* 0x000002700000b947 */
/* 0x000fea0003800000 */
/*0690*/ IMAD.MOV.U32 R22, RZ, RZ, 0x4 ; /* 0x00000004ff167424 */
/* 0x000fc800078e00ff */
/*06a0*/ IMAD.WIDE.U32 R12, R19, R22, c[0x0][0x168] ; /* 0x00005a00130c7625 */
/* 0x000fcc00078e0016 */
/*06b0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea2000c1e1900 */
/*06c0*/ IMAD R23, R15, c[0x0][0x184], R23 ; /* 0x000061000f177a24 */
/* 0x000fc800078e0217 */
/*06d0*/ IMAD.WIDE.U32 R16, R23, R22, c[0x0][0x178] ; /* 0x00005e0017107625 */
/* 0x000fcc00078e0016 */
/*06e0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ee2000c1e1900 */
/*06f0*/ ISETP.NE.AND P3, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f65270 */
/*0700*/ I2F.U8 R18, R12 ; /* 0x0000000c00127306 */
/* 0x004ef00000001000 */
/*0710*/ I2F.U8 R15, R12.B1 ; /* 0x1000000c000f7306 */
/* 0x000e300000001000 */
/*0720*/ I2F.U8 R20, R12.B2 ; /* 0x2000000c00147306 */
/* 0x000e620000001000 */
/*0730*/ FFMA R29, R18, R16, R29 ; /* 0x00000010121d7223 */
/* 0x008fc4000000001d */
/*0740*/ FFMA R26, R16.reuse, R15, R26 ; /* 0x0000000f101a7223 */
/* 0x041fe4000000001a */
/*0750*/ FFMA R27, R16, R20, R27 ; /* 0x00000014101b7223 */
/* 0x002fe2000000001b */
/*0760*/ @!P3 BRA 0x900 ; /* 0x000001900000b947 */
/* 0x000fea0003800000 */
/*0770*/ ISETP.NE.AND P3, PT, R2, 0x2, PT ; /* 0x000000020200780c */
/* 0x000fe40003f65270 */
/*0780*/ IADD3 R21, R19, 0x1, RZ ; /* 0x0000000113157810 */
/* 0x000fca0007ffe0ff */
/*0790*/ IMAD.WIDE.U32 R20, R21, R22, c[0x0][0x168] ; /* 0x00005a0015147625 */
/* 0x000fcc00078e0016 */
/*07a0*/ @P3 IADD3 R19, R19, 0x2, RZ ; /* 0x0000000213133810 */
/* 0x000fe20007ffe0ff */
/*07b0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000ea8000c1e1900 */
/*07c0*/ @P3 IMAD.WIDE.U32 R18, R19, R22, c[0x0][0x168] ; /* 0x00005a0013123625 */
/* 0x000fe200078e0016 */
/*07d0*/ IADD3 R17, R23, 0x1, RZ ; /* 0x0000000117117810 */
/* 0x000fca0007ffe0ff */
/*07e0*/ @P3 LDG.E R18, [R18.64] ; /* 0x0000000412123981 */
/* 0x000ee2000c1e1900 */
/*07f0*/ @P3 IADD3 R13, R23, 0x2, RZ ; /* 0x00000002170d3810 */
/* 0x000fe20007ffe0ff */
/*0800*/ IMAD.WIDE.U32 R16, R17, R22, c[0x0][0x178] ; /* 0x00005e0011107625 */
/* 0x000fc800078e0016 */
/*0810*/ @P3 IMAD.WIDE.U32 R12, R13, R22, c[0x0][0x178] ; /* 0x00005e000d0c3625 */
/* 0x000fe400078e0016 */
/*0820*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*0830*/ @P3 LDG.E R12, [R12.64] ; /* 0x000000040c0c3981 */
/* 0x000f62000c1e1900 */
/*0840*/ I2F.U8 R22, R20 ; /* 0x0000001400167306 */
/* 0x004f300000001000 */
/*0850*/ I2F.U8 R15, R20.B1 ; /* 0x10000014000f7306 */
/* 0x000e300000001000 */
/*0860*/ I2F.U8 R23, R20.B2 ; /* 0x2000001400177306 */
/* 0x000e700000001000 */
/*0870*/ @P3 I2F.U8 R24, R18 ; /* 0x0000001200183306 */
/* 0x008f700000001000 */
/*0880*/ @P3 I2F.U8 R19, R18.B1 ; /* 0x1000001200133306 */
/* 0x000eb00000001000 */
/*0890*/ @P3 I2F.U8 R21, R18.B2 ; /* 0x2000001200153306 */
/* 0x000ee20000001000 */
/*08a0*/ FFMA R29, R22, R16, R29 ; /* 0x00000010161d7223 */
/* 0x010fc4000000001d */
/*08b0*/ FFMA R26, R16.reuse, R15, R26 ; /* 0x0000000f101a7223 */
/* 0x041fe4000000001a */
/*08c0*/ FFMA R27, R16, R23, R27 ; /* 0x00000017101b7223 */
/* 0x002fe4000000001b */
/*08d0*/ @P3 FFMA R29, R24, R12, R29 ; /* 0x0000000c181d3223 */
/* 0x020fe4000000001d */
/*08e0*/ @P3 FFMA R26, R12.reuse, R19, R26 ; /* 0x000000130c1a3223 */
/* 0x044fe4000000001a */
/*08f0*/ @P3 FFMA R27, R12, R21, R27 ; /* 0x000000150c1b3223 */
/* 0x008fe4000000001b */
/*0900*/ @!P2 BRA 0x260 ; /* 0xfffff9500000a947 */
/* 0x000fea000383ffff */
/*0910*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe400078e00ff */
/*0920*/ IMAD R12, R3, c[0x0][0x170], R10 ; /* 0x00005c00030c7a24 */
/* 0x000fc800078e020a */
/*0930*/ IMAD.WIDE.U32 R12, R12, R13, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x000fca00078e000d */
/*0940*/ LDG.E R11, [R12.64] ; /* 0x000000040c0b7981 */
/* 0x000ea2000c1e1900 */
/*0950*/ FSETP.GEU.AND P2, PT, R27.reuse, RZ, PT ; /* 0x000000ff1b00720b */
/* 0x040fe40003f4e000 */
/*0960*/ IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a7810 */
/* 0x000fe40007ffe0ff */
/*0970*/ FSEL R27, R27, RZ, P2 ; /* 0x000000ff1b1b7208 */
/* 0x000fe40001000000 */
/*0980*/ FSETP.GEU.AND P2, PT, R26.reuse, RZ, PT ; /* 0x000000ff1a00720b */
/* 0x040fe40003f4e000 */
/*0990*/ FMNMX.NAN R27, R27, 255, PT ; /* 0x437f00001b1b7809 */
/* 0x000fe40003820000 */
/*09a0*/ FSEL R26, R26, RZ, P2 ; /* 0x000000ff1a1a7208 */
/* 0x000fc40001000000 */
/*09b0*/ FSETP.GEU.AND P2, PT, R29.reuse, RZ, PT ; /* 0x000000ff1d00720b */
/* 0x040fe40003f4e000 */
/*09c0*/ FMNMX.NAN R26, R26, 255, PT ; /* 0x437f00001a1a7809 */
/* 0x000fe20003820000 */
/*09d0*/ F2I.U32.TRUNC.NTZ R27, R27 ; /* 0x0000001b001b7305 */
/* 0x000e22000020f000 */
/*09e0*/ FSEL R29, R29, RZ, P2 ; /* 0x000000ff1d1d7208 */
/* 0x000fe40001000000 */
/*09f0*/ ISETP.GE.U32.AND P2, PT, R10, c[0x0][0x18c], PT ; /* 0x000063000a007a0c */
/* 0x000fe40003f46070 */
/*0a00*/ FMNMX.NAN R29, R29, 255, PT ; /* 0x437f00001d1d7809 */
/* 0x000fc60003820000 */
/*0a10*/ F2I.U32.TRUNC.NTZ R26, R26 ; /* 0x0000001a001a7305 */
/* 0x000e70000020f000 */
/*0a20*/ F2I.U32.TRUNC.NTZ R29, R29 ; /* 0x0000001d001d7305 */
/* 0x000ee2000020f000 */
/*0a30*/ IMAD.U32 R14, R27, 0x10000, RZ ; /* 0x000100001b0e7824 */
/* 0x001fe200078e00ff */
/*0a40*/ SHF.L.U32 R16, R26, 0x8, RZ ; /* 0x000000081a107819 */
/* 0x002fc800000006ff */
/*0a50*/ LOP3.LUT R11, R14, 0xff000000, R11, 0xf8, !PT ; /* 0xff0000000e0b7812 */
/* 0x004fc800078ef80b */
/*0a60*/ LOP3.LUT R11, R29, R11, R16, 0xfe, !PT ; /* 0x0000000b1d0b7212 */
/* 0x008fca00078efe10 */
/*0a70*/ STG.E [R12.64], R11 ; /* 0x0000000b0c007986 */
/* 0x0001e2000c101904 */
/*0a80*/ @!P2 BRA 0x220 ; /* 0xfffff7900000a947 */
/* 0x000fea000383ffff */
/*0a90*/ BRA 0xdf0 ; /* 0x0000035000007947 */
/* 0x000fea0003800000 */
/*0aa0*/ ISETP.NE.AND P2, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f45270 */
/*0ab0*/ BSSY B1, 0xc60 ; /* 0x000001a000017945 */
/* 0x000fe20003800000 */
/*0ac0*/ IMAD.MOV.U32 R16, RZ, RZ, R0 ; /* 0x000000ffff107224 */
/* 0x000fd600078e0000 */
/*0ad0*/ @!P2 BRA 0xc50 ; /* 0x000001700000a947 */
/* 0x000fea0003800000 */
/*0ae0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe400078e00ff */
/*0af0*/ IMAD R10, R3, c[0x0][0x170], R0 ; /* 0x00005c00030a7a24 */
/* 0x000fc800078e0200 */
/*0b00*/ IMAD.WIDE.U32 R10, R10, R13, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fca00078e000d */
/*0b10*/ LDG.E R9, [R10.64] ; /* 0x000000040a097981 */
/* 0x000ea2000c1e1900 */
/*0b20*/ ISETP.NE.AND P2, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fe20003f45270 */
/*0b30*/ IMAD.MOV.U32 R16, RZ, RZ, R6 ; /* 0x000000ffff107224 */
/* 0x000fe200078e0006 */
/*0b40*/ LOP3.LUT R9, R9, 0xff000000, RZ, 0xc0, !PT ; /* 0xff00000009097812 */
/* 0x004fca00078ec0ff */
/*0b50*/ STG.E [R10.64], R9 ; /* 0x000000090a007986 */
/* 0x0001ec000c101904 */
/*0b60*/ @!P2 BRA 0xc50 ; /* 0x000000e00000a947 */
/* 0x000fea0003800000 */
/*0b70*/ IMAD R10, R3, c[0x0][0x170], R6 ; /* 0x00005c00030a7a24 */
/* 0x001fc800078e0206 */
/*0b80*/ IMAD.WIDE.U32 R10, R10, R13, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fca00078e000d */
/*0b90*/ LDG.E R9, [R10.64] ; /* 0x000000040a097981 */
/* 0x000ea2000c1e1900 */
/*0ba0*/ ISETP.NE.AND P2, PT, R7, 0x2, PT ; /* 0x000000020700780c */
/* 0x000fe40003f45270 */
/*0bb0*/ MOV R16, R8 ; /* 0x0000000800107202 */
/* 0x000fe40000000f00 */
/*0bc0*/ LOP3.LUT R9, R9, 0xff000000, RZ, 0xc0, !PT ; /* 0xff00000009097812 */
/* 0x004fca00078ec0ff */
/*0bd0*/ STG.E [R10.64], R9 ; /* 0x000000090a007986 */
/* 0x0001e8000c101904 */
/*0be0*/ @!P2 BRA 0xc50 ; /* 0x000000600000a947 */
/* 0x000fea0003800000 */
/*0bf0*/ IMAD R10, R3, c[0x0][0x170], R8 ; /* 0x00005c00030a7a24 */
/* 0x001fc800078e0208 */
/*0c00*/ IMAD.WIDE.U32 R10, R10, R13, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fca00078e000d */
/*0c10*/ LDG.E R9, [R10.64] ; /* 0x000000040a097981 */
/* 0x000ea2000c1e1900 */
/*0c20*/ IMAD.MOV.U32 R16, RZ, RZ, R5 ; /* 0x000000ffff107224 */
/* 0x000fe200078e0005 */
/*0c30*/ LOP3.LUT R9, R9, 0xff000000, RZ, 0xc0, !PT ; /* 0xff00000009097812 */
/* 0x004fca00078ec0ff */
/*0c40*/ STG.E [R10.64], R9 ; /* 0x000000090a007986 */
/* 0x0001e4000c101904 */
/*0c50*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0c60*/ @!P1 BRA 0xdf0 ; /* 0x0000018000009947 */
/* 0x000fea0003800000 */
/*0c70*/ IMAD.MOV.U32 R20, RZ, RZ, 0x4 ; /* 0x00000004ff147424 */
/* 0x000fe400078e00ff */
/*0c80*/ IMAD R9, R3, c[0x0][0x170], R16 ; /* 0x00005c0003097a24 */
/* 0x003fc800078e0210 */
/*0c90*/ IMAD.WIDE.U32 R10, R9, R20, c[0x0][0x160] ; /* 0x00005800090a7625 */
/* 0x000fca00078e0014 */
/*0ca0*/ LDG.E R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x000ea2000c1e1900 */
/*0cb0*/ IADD3 R13, R9, 0x1, RZ ; /* 0x00000001090d7810 */
/* 0x000fe40007ffe0ff */
/*0cc0*/ LOP3.LUT R17, R12, 0xff000000, RZ, 0xc0, !PT ; /* 0xff0000000c117812 */
/* 0x004fc600078ec0ff */
/*0cd0*/ IMAD.WIDE.U32 R12, R13, R20, c[0x0][0x160] ; /* 0x000058000d0c7625 */
/* 0x000fe400078e0014 */
/*0ce0*/ STG.E [R10.64], R17 ; /* 0x000000110a007986 */
/* 0x0001e8000c101904 */
/*0cf0*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ea2000c1e1900 */
/*0d00*/ IADD3 R15, R9, 0x2, RZ ; /* 0x00000002090f7810 */
/* 0x000fe40007ffe0ff */
/*0d10*/ LOP3.LUT R21, R14, 0xff000000, RZ, 0xc0, !PT ; /* 0xff0000000e157812 */
/* 0x004fc600078ec0ff */
/*0d20*/ IMAD.WIDE.U32 R14, R15, R20, c[0x0][0x160] ; /* 0x000058000f0e7625 */
/* 0x000fe400078e0014 */
/*0d30*/ STG.E [R12.64], R21 ; /* 0x000000150c007986 */
/* 0x0003e8000c101904 */
/*0d40*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000ea2000c1e1900 */
/*0d50*/ IADD3 R19, R9, 0x3, RZ ; /* 0x0000000309137810 */
/* 0x000fe40007ffe0ff */
/*0d60*/ LOP3.LUT R9, R18, 0xff000000, RZ, 0xc0, !PT ; /* 0xff00000012097812 */
/* 0x004fc600078ec0ff */
/*0d70*/ IMAD.WIDE.U32 R18, R19, R20, c[0x0][0x160] ; /* 0x0000580013127625 */
/* 0x000fe400078e0014 */
/*0d80*/ STG.E [R14.64], R9 ; /* 0x000000090e007986 */
/* 0x0003e8000c101904 */
/*0d90*/ LDG.E R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x001ea2000c1e1900 */
/*0da0*/ IADD3 R16, R16, 0x4, RZ ; /* 0x0000000410107810 */
/* 0x000fc80007ffe0ff */
/*0db0*/ ISETP.GE.U32.AND P2, PT, R16, c[0x0][0x18c], PT ; /* 0x0000630010007a0c */
/* 0x000fe40003f46070 */
/*0dc0*/ LOP3.LUT R11, R10, 0xff000000, RZ, 0xc0, !PT ; /* 0xff0000000a0b7812 */
/* 0x004fca00078ec0ff */
/*0dd0*/ STG.E [R18.64], R11 ; /* 0x0000000b12007986 */
/* 0x0003ec000c101904 */
/*0de0*/ @!P2 BRA 0xc70 ; /* 0xfffffe800000a947 */
/* 0x000fea000383ffff */
/*0df0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0e00*/ IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103037810 */
/* 0x000fc80007ffe0ff */
/*0e10*/ ISETP.GE.U32.AND P2, PT, R3, c[0x0][0x190], PT ; /* 0x0000640003007a0c */
/* 0x000fda0003f46070 */
/*0e20*/ @!P2 BRA 0x1b0 ; /* 0xfffff3800000a947 */
/* 0x000fea000383ffff */
/*0e30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0e40*/ BRA 0xe40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define THREADS_PER_BLOCK 128
#include <cmath>
#include <chrono>
#include <cstring>
#include <fstream>
#include <iostream>
#include <stdexcept>
#include "tiffio.h"
// saves TIFF file from data in `raster`
void save_tiff(const char *fname, uint32 *raster, uint32 w, uint32 h) {
TIFF *tif = TIFFOpen(fname, "w");
if (! raster) {
throw std::runtime_error("Could not open output file");
}
TIFFSetField(tif, TIFFTAG_IMAGEWIDTH, w);
TIFFSetField(tif, TIFFTAG_IMAGELENGTH, h);
TIFFSetField(tif, TIFFTAG_SAMPLESPERPIXEL, 4);
TIFFSetField(tif, TIFFTAG_BITSPERSAMPLE, 8);
TIFFSetField(tif, TIFFTAG_COMPRESSION, COMPRESSION_DEFLATE);
TIFFSetField(tif, TIFFTAG_ORIENTATION, ORIENTATION_TOPLEFT);
TIFFSetField(tif, TIFFTAG_PHOTOMETRIC, PHOTOMETRIC_RGB);
TIFFSetField(tif, TIFFTAG_PLANARCONFIG, PLANARCONFIG_CONTIG);
TIFFWriteEncodedStrip(tif, 0, raster, w*h*4);
TIFFClose(tif);
}
// loads image data from `fname` (allocating dynamic memory)
// *w and *h are updated with the image dimensions
// raster is a matrix flattened into an array using row-major order
// every uint32 in the array is 4 bytes, enconding 8-bit packed ABGR
// A: transparency attribute (can be ignored)
// B: blue pixel
// G: green pixel
// R: red pixel
uint32 *load_tiff(const char *fname, uint32 *w, uint32 *h) {
TIFF *tif = TIFFOpen(fname, "r");
if (! tif) {
throw std::runtime_error("Could not open input file");
}
TIFFGetField(tif, TIFFTAG_IMAGEWIDTH, w);
TIFFGetField(tif, TIFFTAG_IMAGELENGTH, h);
uint32 *raster = (uint32 *) _TIFFmalloc(*w * *h * sizeof (uint32));
if (! raster) {
TIFFClose(tif);
throw std::runtime_error("Memory allocation error");
}
if (! TIFFReadRGBAImageOriented(tif, *w, *h, raster, ORIENTATION_TOPLEFT, 0)) {
TIFFClose(tif);
throw std::runtime_error("Could not read raster from TIFF image");
}
TIFFClose(tif);
return raster;
}
void clamp(float *val) {
if (*val < 0) *val = 0;
if (*val > 255) *val = 255;
}
__device__ void cuda_clamp(float *val) {
if (*val < 0) *val = 0;
if (*val > 255) *val = 255;
}
void filter_image_seq(uint32 *raster, uint32 w, uint32 h, const float *filter, int f_len) {
// to get RGB values from a pixel, you can either use bitwise masks
// or rely on the following macros:
// TIFFGetR(raster[i]) red
// TIFFGetG(raster[i]) green
// TIFFGetB(raster[i]) blue
// TIFFGetA(raster[i]) this value should be ignored
//
// to modify RGB values from a pixel, you can use bitwise shifts or masks
// each pixel stores values in the order ABGR
//
// TODO: here you will filter the image in raster
//
uint32 *copy = new uint32[w*h];
std::memcpy(copy, raster, sizeof(uint32)*w*h);
uint32 d = (uint32) std::sqrt(f_len);
uint32 idx, pixel;
uint32 st = d / 2;
uint32 end_w = w - d/2;
uint32 end_h = h - d/2;
float sumR, sumG, sumB;
// applies filter
for (uint32 i = st ; i < end_h ; i++) {
for (uint32 j = st ; j < end_w ; j++) {
sumR = sumG = sumB = 0;
for (uint32 k = 0 ; k < d ; k ++) {
idx = (i-st+k)*w + (j-st);
for (uint32 l = 0 ; l < d ; l++) {
pixel = copy[idx++];
sumR += (filter[k*d + l] * TIFFGetR(pixel));
sumG += (filter[k*d + l] * TIFFGetG(pixel));
sumB += (filter[k*d + l] * TIFFGetB(pixel));
}
}
clamp(&sumR);
clamp(&sumG);
clamp(&sumB);
raster[i*w + j] = TIFFGetA(raster[i*w + j]) << 24 | ((uint32) sumB << 16) | ((uint32) sumG << 8) | ((uint32) sumR);
}
}
delete [] copy;
}
__global__ void filter_image_cuda(uint32 *raster, uint32 *copy, uint32 w, uint32 h, const float *filter, int f_len, uint32 d, uint32 st, uint32 end_w, uint32 end_h) {
// applies filter
// Start Indices
uint32 start_i = (blockIdx.y * blockDim.y) + threadIdx.y + st;
uint32 start_j = (blockIdx.x * blockDim.x) + threadIdx.x + st;
uint32 idx, pixel;
float sumR, sumG, sumB;
// applies filter
for (uint32 i = start_i ; i < end_h ; i++) {
for (uint32 j = start_j ; j < end_w ; j++) {
sumR = sumG = sumB = 0;
for (uint32 k = 0 ; k < d ; k ++) {
idx = (i-st+k)*w + (j-st);
for (uint32 l = 0 ; l < d ; l++) {
pixel = copy[idx++];
sumR += (filter[k*d + l] * TIFFGetR(pixel));
sumG += (filter[k*d + l] * TIFFGetG(pixel));
sumB += (filter[k*d + l] * TIFFGetB(pixel));
}
}
cuda_clamp(&sumR);
cuda_clamp(&sumG);
cuda_clamp(&sumB);
raster[i*w + j] = TIFFGetA(raster[i*w + j]) << 24 | ((uint32) sumB << 16) | ((uint32) sumG << 8) | ((uint32) sumR);
}
}
}
void filter_image_par(uint32 *raster, uint32 w, uint32 h, const float *filter, int f_len, int n_threads, int n_blocks) {
//
// TODO: here you will filter the image in raster using GPU threads
//
// Consistent Computations
uint32 d = (uint32) std::sqrt(f_len);
uint32 st = d / 2;
uint32 end_w = w - d/2;
uint32 end_h = h - d/2;
uint32 n = w*h;
// Create Blocks and threads
dim3 threadsPerBlock(n_threads, n_threads, 1);
dim3 numBlocks(n_blocks,n_blocks,1);
// create pointers for the CUDA arrays
uint32 *copy_in;
uint32 *raster_out;
float *filter_in;
// variable to check for CUDA errors
cudaError_t status;
// choose GPU to run
status = cudaSetDevice(0);
if (status != cudaSuccess) std::cerr << "cudaSetDevice failed!" << std::endl;
// allocate space for the arrays in the GPU
status = cudaMalloc(©_in, sizeof(uint32) * n);
if (status != cudaSuccess) std::cerr << "cudaMalloc (copy_in) failed!" << std::endl;
status = cudaMalloc(&raster_out, sizeof(uint32) * n);
if (status != cudaSuccess) std::cerr << "cudaMalloc (raster_out) failed!" << std::endl;
status = cudaMalloc(&filter_in, sizeof(float) * f_len);
if (status != cudaSuccess) std::cerr << "cudaMalloc (filter) failed!" << std::endl;
// transfer data from CPU to GPU
status = cudaMemcpy(copy_in, raster, sizeof(uint32) * n, cudaMemcpyHostToDevice);
if (status != cudaSuccess) std::cerr << "cudaMemcpy H2D failed! - copy" << std::endl;
status = cudaMemcpy(raster_out, raster, sizeof(uint32) * n, cudaMemcpyHostToDevice);
if (status != cudaSuccess) std::cerr << "cudaMemcpy H2D failed! - raster" << std::endl;
status = cudaMemcpy(filter_in, filter, sizeof(float) * f_len, cudaMemcpyHostToDevice);
if (status != cudaSuccess) std::cerr << "cudaMemcpy H2D failed! - filter" << std::endl;
// Do the work in the GPU
//std::cout << "Blocks: " << std::ceil((float)n/THREADS_PER_BLOCK) << std::endl;
filter_image_cuda<<<numBlocks,threadsPerBlock>>>(raster_out, copy_in, w, h, filter_in, f_len, d, st, end_w, end_h);
// wait for the kernel to finish, and check for errors
status = cudaThreadSynchronize();
if (status != cudaSuccess) std::cerr << "error code " << status << " returned after kernel!" << std::endl;
// transfer results from GPU to CPU
status = cudaMemcpy(raster, raster_out, sizeof(uint32) * n, cudaMemcpyDeviceToHost);
if (status != cudaSuccess) std::cerr << "cudaMemcpy D2H failed! - final" << std::endl;
// Free memory
cudaFree(copy_in);
cudaFree(raster_out);
cudaFree(filter_in);
}
float *load_filter(const char *fname, int *n) {
std::ifstream myfile(fname);
if (! myfile) {
throw std::runtime_error("Could not open filter file");
}
myfile >> *n;
float *filter = new float[*n];
for (int i = 0 ; i < *n ; i++) myfile >> filter[i];
myfile.close();
return filter;
}
int main(int argc, char* argv[]) {
if (argc != 7) {
std::cout << "Usage:\t./filter <in_fname> <out_fname> <filter_fname> <algo>" << std::endl;
std::cout << "<in_fname> path to the input image" << std::endl;
std::cout << "<out_fname> path to the output image" << std::endl;
std::cout << "<filter_fname> path to the filter file" << std::endl;
std::cout << "<algo> whether to use the sequential (seq) or parallel algorithm (par)" << std::endl;
std::cout << "<n_threads> number of threads to use (Ex: enter 5 for 25 threads/block)" << std::endl;
std::cout << "<n_blocks> number of blocks to use [Ex: enter 2 for 4 blocks]" << std::endl;
return 0;
}
uint32 width, height;
int n_threads = std::stoi(argv[5]);
int n_blocks = std::stoi(argv[6]);
// loads the filter
int f_len;
float *filter = load_filter(argv[3], &f_len);
// loads image bytes from file name supplied as a command line argument
// this function allocates memory dynamically
uint32 *image = load_tiff(argv[1], &width, &height);
// measure time of the algorithm
auto start = std::chrono::high_resolution_clock::now();
if (! std::strcmp(argv[4], "seq")) {
// call the sequential implementation
filter_image_seq(image, width, height, filter, f_len);
} else if (! std::strcmp(argv[4], "par")) {
// TODO: call the parallel implementation
filter_image_par(image, width, height, filter, f_len, n_threads, n_blocks);
}
auto end = std::chrono::high_resolution_clock::now();
std::chrono::duration<double> diff = end - start;
std::cout << diff.count() << std::endl;
// save new file with filtered image
save_tiff(argv[2], image, width, height);
// frees memory allocated by load_filter and load_tiff
delete [] filter;
_TIFFfree(image);
return 0;
} | #define THREADS_PER_BLOCK 128
#include <hip/hip_runtime.h>
#include <cmath>
#include <chrono>
#include <cstring>
#include <fstream>
#include <iostream>
#include <stdexcept>
#include "tiffio.h"
// saves TIFF file from data in `raster`
void save_tiff(const char *fname, uint32 *raster, uint32 w, uint32 h) {
TIFF *tif = TIFFOpen(fname, "w");
if (! raster) {
throw std::runtime_error("Could not open output file");
}
TIFFSetField(tif, TIFFTAG_IMAGEWIDTH, w);
TIFFSetField(tif, TIFFTAG_IMAGELENGTH, h);
TIFFSetField(tif, TIFFTAG_SAMPLESPERPIXEL, 4);
TIFFSetField(tif, TIFFTAG_BITSPERSAMPLE, 8);
TIFFSetField(tif, TIFFTAG_COMPRESSION, COMPRESSION_DEFLATE);
TIFFSetField(tif, TIFFTAG_ORIENTATION, ORIENTATION_TOPLEFT);
TIFFSetField(tif, TIFFTAG_PHOTOMETRIC, PHOTOMETRIC_RGB);
TIFFSetField(tif, TIFFTAG_PLANARCONFIG, PLANARCONFIG_CONTIG);
TIFFWriteEncodedStrip(tif, 0, raster, w*h*4);
TIFFClose(tif);
}
// loads image data from `fname` (allocating dynamic memory)
// *w and *h are updated with the image dimensions
// raster is a matrix flattened into an array using row-major order
// every uint32 in the array is 4 bytes, enconding 8-bit packed ABGR
// A: transparency attribute (can be ignored)
// B: blue pixel
// G: green pixel
// R: red pixel
uint32 *load_tiff(const char *fname, uint32 *w, uint32 *h) {
TIFF *tif = TIFFOpen(fname, "r");
if (! tif) {
throw std::runtime_error("Could not open input file");
}
TIFFGetField(tif, TIFFTAG_IMAGEWIDTH, w);
TIFFGetField(tif, TIFFTAG_IMAGELENGTH, h);
uint32 *raster = (uint32 *) _TIFFmalloc(*w * *h * sizeof (uint32));
if (! raster) {
TIFFClose(tif);
throw std::runtime_error("Memory allocation error");
}
if (! TIFFReadRGBAImageOriented(tif, *w, *h, raster, ORIENTATION_TOPLEFT, 0)) {
TIFFClose(tif);
throw std::runtime_error("Could not read raster from TIFF image");
}
TIFFClose(tif);
return raster;
}
void clamp(float *val) {
if (*val < 0) *val = 0;
if (*val > 255) *val = 255;
}
__device__ void cuda_clamp(float *val) {
if (*val < 0) *val = 0;
if (*val > 255) *val = 255;
}
void filter_image_seq(uint32 *raster, uint32 w, uint32 h, const float *filter, int f_len) {
// to get RGB values from a pixel, you can either use bitwise masks
// or rely on the following macros:
// TIFFGetR(raster[i]) red
// TIFFGetG(raster[i]) green
// TIFFGetB(raster[i]) blue
// TIFFGetA(raster[i]) this value should be ignored
//
// to modify RGB values from a pixel, you can use bitwise shifts or masks
// each pixel stores values in the order ABGR
//
// TODO: here you will filter the image in raster
//
uint32 *copy = new uint32[w*h];
std::memcpy(copy, raster, sizeof(uint32)*w*h);
uint32 d = (uint32) std::sqrt(f_len);
uint32 idx, pixel;
uint32 st = d / 2;
uint32 end_w = w - d/2;
uint32 end_h = h - d/2;
float sumR, sumG, sumB;
// applies filter
for (uint32 i = st ; i < end_h ; i++) {
for (uint32 j = st ; j < end_w ; j++) {
sumR = sumG = sumB = 0;
for (uint32 k = 0 ; k < d ; k ++) {
idx = (i-st+k)*w + (j-st);
for (uint32 l = 0 ; l < d ; l++) {
pixel = copy[idx++];
sumR += (filter[k*d + l] * TIFFGetR(pixel));
sumG += (filter[k*d + l] * TIFFGetG(pixel));
sumB += (filter[k*d + l] * TIFFGetB(pixel));
}
}
clamp(&sumR);
clamp(&sumG);
clamp(&sumB);
raster[i*w + j] = TIFFGetA(raster[i*w + j]) << 24 | ((uint32) sumB << 16) | ((uint32) sumG << 8) | ((uint32) sumR);
}
}
delete [] copy;
}
__global__ void filter_image_cuda(uint32 *raster, uint32 *copy, uint32 w, uint32 h, const float *filter, int f_len, uint32 d, uint32 st, uint32 end_w, uint32 end_h) {
// applies filter
// Start Indices
uint32 start_i = (blockIdx.y * blockDim.y) + threadIdx.y + st;
uint32 start_j = (blockIdx.x * blockDim.x) + threadIdx.x + st;
uint32 idx, pixel;
float sumR, sumG, sumB;
// applies filter
for (uint32 i = start_i ; i < end_h ; i++) {
for (uint32 j = start_j ; j < end_w ; j++) {
sumR = sumG = sumB = 0;
for (uint32 k = 0 ; k < d ; k ++) {
idx = (i-st+k)*w + (j-st);
for (uint32 l = 0 ; l < d ; l++) {
pixel = copy[idx++];
sumR += (filter[k*d + l] * TIFFGetR(pixel));
sumG += (filter[k*d + l] * TIFFGetG(pixel));
sumB += (filter[k*d + l] * TIFFGetB(pixel));
}
}
cuda_clamp(&sumR);
cuda_clamp(&sumG);
cuda_clamp(&sumB);
raster[i*w + j] = TIFFGetA(raster[i*w + j]) << 24 | ((uint32) sumB << 16) | ((uint32) sumG << 8) | ((uint32) sumR);
}
}
}
void filter_image_par(uint32 *raster, uint32 w, uint32 h, const float *filter, int f_len, int n_threads, int n_blocks) {
//
// TODO: here you will filter the image in raster using GPU threads
//
// Consistent Computations
uint32 d = (uint32) std::sqrt(f_len);
uint32 st = d / 2;
uint32 end_w = w - d/2;
uint32 end_h = h - d/2;
uint32 n = w*h;
// Create Blocks and threads
dim3 threadsPerBlock(n_threads, n_threads, 1);
dim3 numBlocks(n_blocks,n_blocks,1);
// create pointers for the CUDA arrays
uint32 *copy_in;
uint32 *raster_out;
float *filter_in;
// variable to check for CUDA errors
hipError_t status;
// choose GPU to run
status = hipSetDevice(0);
if (status != hipSuccess) std::cerr << "hipSetDevice failed!" << std::endl;
// allocate space for the arrays in the GPU
status = hipMalloc(©_in, sizeof(uint32) * n);
if (status != hipSuccess) std::cerr << "hipMalloc (copy_in) failed!" << std::endl;
status = hipMalloc(&raster_out, sizeof(uint32) * n);
if (status != hipSuccess) std::cerr << "hipMalloc (raster_out) failed!" << std::endl;
status = hipMalloc(&filter_in, sizeof(float) * f_len);
if (status != hipSuccess) std::cerr << "hipMalloc (filter) failed!" << std::endl;
// transfer data from CPU to GPU
status = hipMemcpy(copy_in, raster, sizeof(uint32) * n, hipMemcpyHostToDevice);
if (status != hipSuccess) std::cerr << "hipMemcpy H2D failed! - copy" << std::endl;
status = hipMemcpy(raster_out, raster, sizeof(uint32) * n, hipMemcpyHostToDevice);
if (status != hipSuccess) std::cerr << "hipMemcpy H2D failed! - raster" << std::endl;
status = hipMemcpy(filter_in, filter, sizeof(float) * f_len, hipMemcpyHostToDevice);
if (status != hipSuccess) std::cerr << "hipMemcpy H2D failed! - filter" << std::endl;
// Do the work in the GPU
//std::cout << "Blocks: " << std::ceil((float)n/THREADS_PER_BLOCK) << std::endl;
filter_image_cuda<<<numBlocks,threadsPerBlock>>>(raster_out, copy_in, w, h, filter_in, f_len, d, st, end_w, end_h);
// wait for the kernel to finish, and check for errors
status = hipDeviceSynchronize();
if (status != hipSuccess) std::cerr << "error code " << status << " returned after kernel!" << std::endl;
// transfer results from GPU to CPU
status = hipMemcpy(raster, raster_out, sizeof(uint32) * n, hipMemcpyDeviceToHost);
if (status != hipSuccess) std::cerr << "hipMemcpy D2H failed! - final" << std::endl;
// Free memory
hipFree(copy_in);
hipFree(raster_out);
hipFree(filter_in);
}
float *load_filter(const char *fname, int *n) {
std::ifstream myfile(fname);
if (! myfile) {
throw std::runtime_error("Could not open filter file");
}
myfile >> *n;
float *filter = new float[*n];
for (int i = 0 ; i < *n ; i++) myfile >> filter[i];
myfile.close();
return filter;
}
int main(int argc, char* argv[]) {
if (argc != 7) {
std::cout << "Usage:\t./filter <in_fname> <out_fname> <filter_fname> <algo>" << std::endl;
std::cout << "<in_fname> path to the input image" << std::endl;
std::cout << "<out_fname> path to the output image" << std::endl;
std::cout << "<filter_fname> path to the filter file" << std::endl;
std::cout << "<algo> whether to use the sequential (seq) or parallel algorithm (par)" << std::endl;
std::cout << "<n_threads> number of threads to use (Ex: enter 5 for 25 threads/block)" << std::endl;
std::cout << "<n_blocks> number of blocks to use [Ex: enter 2 for 4 blocks]" << std::endl;
return 0;
}
uint32 width, height;
int n_threads = std::stoi(argv[5]);
int n_blocks = std::stoi(argv[6]);
// loads the filter
int f_len;
float *filter = load_filter(argv[3], &f_len);
// loads image bytes from file name supplied as a command line argument
// this function allocates memory dynamically
uint32 *image = load_tiff(argv[1], &width, &height);
// measure time of the algorithm
auto start = std::chrono::high_resolution_clock::now();
if (! std::strcmp(argv[4], "seq")) {
// call the sequential implementation
filter_image_seq(image, width, height, filter, f_len);
} else if (! std::strcmp(argv[4], "par")) {
// TODO: call the parallel implementation
filter_image_par(image, width, height, filter, f_len, n_threads, n_blocks);
}
auto end = std::chrono::high_resolution_clock::now();
std::chrono::duration<double> diff = end - start;
std::cout << diff.count() << std::endl;
// save new file with filtered image
save_tiff(argv[2], image, width, height);
// frees memory allocated by load_filter and load_tiff
delete [] filter;
_TIFFfree(image);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #define THREADS_PER_BLOCK 128
#include <hip/hip_runtime.h>
#include <cmath>
#include <chrono>
#include <cstring>
#include <fstream>
#include <iostream>
#include <stdexcept>
#include "tiffio.h"
// saves TIFF file from data in `raster`
void save_tiff(const char *fname, uint32 *raster, uint32 w, uint32 h) {
TIFF *tif = TIFFOpen(fname, "w");
if (! raster) {
throw std::runtime_error("Could not open output file");
}
TIFFSetField(tif, TIFFTAG_IMAGEWIDTH, w);
TIFFSetField(tif, TIFFTAG_IMAGELENGTH, h);
TIFFSetField(tif, TIFFTAG_SAMPLESPERPIXEL, 4);
TIFFSetField(tif, TIFFTAG_BITSPERSAMPLE, 8);
TIFFSetField(tif, TIFFTAG_COMPRESSION, COMPRESSION_DEFLATE);
TIFFSetField(tif, TIFFTAG_ORIENTATION, ORIENTATION_TOPLEFT);
TIFFSetField(tif, TIFFTAG_PHOTOMETRIC, PHOTOMETRIC_RGB);
TIFFSetField(tif, TIFFTAG_PLANARCONFIG, PLANARCONFIG_CONTIG);
TIFFWriteEncodedStrip(tif, 0, raster, w*h*4);
TIFFClose(tif);
}
// loads image data from `fname` (allocating dynamic memory)
// *w and *h are updated with the image dimensions
// raster is a matrix flattened into an array using row-major order
// every uint32 in the array is 4 bytes, enconding 8-bit packed ABGR
// A: transparency attribute (can be ignored)
// B: blue pixel
// G: green pixel
// R: red pixel
uint32 *load_tiff(const char *fname, uint32 *w, uint32 *h) {
TIFF *tif = TIFFOpen(fname, "r");
if (! tif) {
throw std::runtime_error("Could not open input file");
}
TIFFGetField(tif, TIFFTAG_IMAGEWIDTH, w);
TIFFGetField(tif, TIFFTAG_IMAGELENGTH, h);
uint32 *raster = (uint32 *) _TIFFmalloc(*w * *h * sizeof (uint32));
if (! raster) {
TIFFClose(tif);
throw std::runtime_error("Memory allocation error");
}
if (! TIFFReadRGBAImageOriented(tif, *w, *h, raster, ORIENTATION_TOPLEFT, 0)) {
TIFFClose(tif);
throw std::runtime_error("Could not read raster from TIFF image");
}
TIFFClose(tif);
return raster;
}
void clamp(float *val) {
if (*val < 0) *val = 0;
if (*val > 255) *val = 255;
}
__device__ void cuda_clamp(float *val) {
if (*val < 0) *val = 0;
if (*val > 255) *val = 255;
}
void filter_image_seq(uint32 *raster, uint32 w, uint32 h, const float *filter, int f_len) {
// to get RGB values from a pixel, you can either use bitwise masks
// or rely on the following macros:
// TIFFGetR(raster[i]) red
// TIFFGetG(raster[i]) green
// TIFFGetB(raster[i]) blue
// TIFFGetA(raster[i]) this value should be ignored
//
// to modify RGB values from a pixel, you can use bitwise shifts or masks
// each pixel stores values in the order ABGR
//
// TODO: here you will filter the image in raster
//
uint32 *copy = new uint32[w*h];
std::memcpy(copy, raster, sizeof(uint32)*w*h);
uint32 d = (uint32) std::sqrt(f_len);
uint32 idx, pixel;
uint32 st = d / 2;
uint32 end_w = w - d/2;
uint32 end_h = h - d/2;
float sumR, sumG, sumB;
// applies filter
for (uint32 i = st ; i < end_h ; i++) {
for (uint32 j = st ; j < end_w ; j++) {
sumR = sumG = sumB = 0;
for (uint32 k = 0 ; k < d ; k ++) {
idx = (i-st+k)*w + (j-st);
for (uint32 l = 0 ; l < d ; l++) {
pixel = copy[idx++];
sumR += (filter[k*d + l] * TIFFGetR(pixel));
sumG += (filter[k*d + l] * TIFFGetG(pixel));
sumB += (filter[k*d + l] * TIFFGetB(pixel));
}
}
clamp(&sumR);
clamp(&sumG);
clamp(&sumB);
raster[i*w + j] = TIFFGetA(raster[i*w + j]) << 24 | ((uint32) sumB << 16) | ((uint32) sumG << 8) | ((uint32) sumR);
}
}
delete [] copy;
}
__global__ void filter_image_cuda(uint32 *raster, uint32 *copy, uint32 w, uint32 h, const float *filter, int f_len, uint32 d, uint32 st, uint32 end_w, uint32 end_h) {
// applies filter
// Start Indices
uint32 start_i = (blockIdx.y * blockDim.y) + threadIdx.y + st;
uint32 start_j = (blockIdx.x * blockDim.x) + threadIdx.x + st;
uint32 idx, pixel;
float sumR, sumG, sumB;
// applies filter
for (uint32 i = start_i ; i < end_h ; i++) {
for (uint32 j = start_j ; j < end_w ; j++) {
sumR = sumG = sumB = 0;
for (uint32 k = 0 ; k < d ; k ++) {
idx = (i-st+k)*w + (j-st);
for (uint32 l = 0 ; l < d ; l++) {
pixel = copy[idx++];
sumR += (filter[k*d + l] * TIFFGetR(pixel));
sumG += (filter[k*d + l] * TIFFGetG(pixel));
sumB += (filter[k*d + l] * TIFFGetB(pixel));
}
}
cuda_clamp(&sumR);
cuda_clamp(&sumG);
cuda_clamp(&sumB);
raster[i*w + j] = TIFFGetA(raster[i*w + j]) << 24 | ((uint32) sumB << 16) | ((uint32) sumG << 8) | ((uint32) sumR);
}
}
}
void filter_image_par(uint32 *raster, uint32 w, uint32 h, const float *filter, int f_len, int n_threads, int n_blocks) {
//
// TODO: here you will filter the image in raster using GPU threads
//
// Consistent Computations
uint32 d = (uint32) std::sqrt(f_len);
uint32 st = d / 2;
uint32 end_w = w - d/2;
uint32 end_h = h - d/2;
uint32 n = w*h;
// Create Blocks and threads
dim3 threadsPerBlock(n_threads, n_threads, 1);
dim3 numBlocks(n_blocks,n_blocks,1);
// create pointers for the CUDA arrays
uint32 *copy_in;
uint32 *raster_out;
float *filter_in;
// variable to check for CUDA errors
hipError_t status;
// choose GPU to run
status = hipSetDevice(0);
if (status != hipSuccess) std::cerr << "hipSetDevice failed!" << std::endl;
// allocate space for the arrays in the GPU
status = hipMalloc(©_in, sizeof(uint32) * n);
if (status != hipSuccess) std::cerr << "hipMalloc (copy_in) failed!" << std::endl;
status = hipMalloc(&raster_out, sizeof(uint32) * n);
if (status != hipSuccess) std::cerr << "hipMalloc (raster_out) failed!" << std::endl;
status = hipMalloc(&filter_in, sizeof(float) * f_len);
if (status != hipSuccess) std::cerr << "hipMalloc (filter) failed!" << std::endl;
// transfer data from CPU to GPU
status = hipMemcpy(copy_in, raster, sizeof(uint32) * n, hipMemcpyHostToDevice);
if (status != hipSuccess) std::cerr << "hipMemcpy H2D failed! - copy" << std::endl;
status = hipMemcpy(raster_out, raster, sizeof(uint32) * n, hipMemcpyHostToDevice);
if (status != hipSuccess) std::cerr << "hipMemcpy H2D failed! - raster" << std::endl;
status = hipMemcpy(filter_in, filter, sizeof(float) * f_len, hipMemcpyHostToDevice);
if (status != hipSuccess) std::cerr << "hipMemcpy H2D failed! - filter" << std::endl;
// Do the work in the GPU
//std::cout << "Blocks: " << std::ceil((float)n/THREADS_PER_BLOCK) << std::endl;
filter_image_cuda<<<numBlocks,threadsPerBlock>>>(raster_out, copy_in, w, h, filter_in, f_len, d, st, end_w, end_h);
// wait for the kernel to finish, and check for errors
status = hipDeviceSynchronize();
if (status != hipSuccess) std::cerr << "error code " << status << " returned after kernel!" << std::endl;
// transfer results from GPU to CPU
status = hipMemcpy(raster, raster_out, sizeof(uint32) * n, hipMemcpyDeviceToHost);
if (status != hipSuccess) std::cerr << "hipMemcpy D2H failed! - final" << std::endl;
// Free memory
hipFree(copy_in);
hipFree(raster_out);
hipFree(filter_in);
}
float *load_filter(const char *fname, int *n) {
std::ifstream myfile(fname);
if (! myfile) {
throw std::runtime_error("Could not open filter file");
}
myfile >> *n;
float *filter = new float[*n];
for (int i = 0 ; i < *n ; i++) myfile >> filter[i];
myfile.close();
return filter;
}
int main(int argc, char* argv[]) {
if (argc != 7) {
std::cout << "Usage:\t./filter <in_fname> <out_fname> <filter_fname> <algo>" << std::endl;
std::cout << "<in_fname> path to the input image" << std::endl;
std::cout << "<out_fname> path to the output image" << std::endl;
std::cout << "<filter_fname> path to the filter file" << std::endl;
std::cout << "<algo> whether to use the sequential (seq) or parallel algorithm (par)" << std::endl;
std::cout << "<n_threads> number of threads to use (Ex: enter 5 for 25 threads/block)" << std::endl;
std::cout << "<n_blocks> number of blocks to use [Ex: enter 2 for 4 blocks]" << std::endl;
return 0;
}
uint32 width, height;
int n_threads = std::stoi(argv[5]);
int n_blocks = std::stoi(argv[6]);
// loads the filter
int f_len;
float *filter = load_filter(argv[3], &f_len);
// loads image bytes from file name supplied as a command line argument
// this function allocates memory dynamically
uint32 *image = load_tiff(argv[1], &width, &height);
// measure time of the algorithm
auto start = std::chrono::high_resolution_clock::now();
if (! std::strcmp(argv[4], "seq")) {
// call the sequential implementation
filter_image_seq(image, width, height, filter, f_len);
} else if (! std::strcmp(argv[4], "par")) {
// TODO: call the parallel implementation
filter_image_par(image, width, height, filter, f_len, n_threads, n_blocks);
}
auto end = std::chrono::high_resolution_clock::now();
std::chrono::duration<double> diff = end - start;
std::cout << diff.count() << std::endl;
// save new file with filtered image
save_tiff(argv[2], image, width, height);
// frees memory allocated by load_filter and load_tiff
delete [] filter;
_TIFFfree(image);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17filter_image_cudaPjS_jjPKfijjjj
.globl _Z17filter_image_cudaPjS_jjPKfijjjj
.p2align 8
.type _Z17filter_image_cudaPjS_jjPKfijjjj,@function
_Z17filter_image_cudaPjS_jjPKfijjjj:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x44
s_load_b32 s8, s[0:1], 0x28
s_load_b32 s10, s[0:1], 0x30
s_add_u32 s2, s0, 56
v_bfe_u32 v1, v0, 10, 10
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mul_i32 s15, s15, s4
s_mov_b32 s4, exec_lo
v_add3_u32 v2, s15, s8, v1
v_cmpx_gt_u32_e64 s10, v2
s_cbranch_execz .LBB0_11
s_load_b32 s9, s[2:3], 0xc
s_clause 0x4
s_load_b32 s11, s[0:1], 0x10
s_load_b32 s12, s[0:1], 0x24
s_load_b32 s13, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x18
v_add_nc_u32_e32 v1, s15, v1
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s9, 0xffff
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, s11, v1
s_mul_i32 s14, s14, s0
s_cmp_lg_u32 s12, 0
s_mov_b32 s9, 0
s_cselect_b32 s1, -1, 0
v_add3_u32 v4, v0, v1, s14
v_mov_b32_e32 v1, 0
v_add3_u32 v3, s14, s8, v0
s_mov_b32 s14, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u32_e64 s0, s13, v3
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s15
v_add_nc_u32_e32 v2, 1, v2
v_add_nc_u32_e32 v4, s11, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_u32_e32 vcc_lo, s10, v2
s_or_b32 s14, vcc_lo, s14
s_and_not1_b32 exec_lo, exec_lo, s14
s_cbranch_execz .LBB0_11
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s15, s0
s_cbranch_execz .LBB0_2
v_mul_lo_u32 v5, v2, s11
v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v7, v3
s_mov_b32 s16, 0
s_branch .LBB0_6
.LBB0_5:
v_add_nc_u32_e32 v0, v7, v5
v_add_nc_u32_e32 v6, 1, v6
v_add_nc_u32_e32 v7, 1, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[11:12], 2, v[0:1]
v_add_co_u32 v11, vcc_lo, s4, v11
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0, v10
global_load_b32 v0, v[11:12], off
v_cndmask_b32_e32 v10, 0, v10, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0, v8
v_cndmask_b32_e32 v8, 0, v8, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0, v9
v_cndmask_b32_e32 v9, 0, v9, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x437f0000, v10
v_cndmask_b32_e32 v10, 0x437f0000, v10, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x437f0000, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v10, v10
v_cndmask_b32_e32 v8, 0x437f0000, v8, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x437f0000, v9
v_cvt_u32_f32_e32 v8, v8
v_cndmask_b32_e32 v9, 0x437f0000, v9, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s13, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b32_e32 v8, 16, v8
v_cvt_u32_f32_e32 v9, v9
s_or_b32 s16, vcc_lo, s16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshl_or_b32 v9, v10, 8, v9
s_waitcnt vmcnt(0)
v_and_b32_e32 v0, 0xff000000, v0
v_or3_b32 v0, v9, v8, v0
global_store_b32 v[11:12], v0, off
s_and_not1_b32 exec_lo, exec_lo, s16
s_cbranch_execz .LBB0_2
.LBB0_6:
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, 0
v_mov_b32_e32 v10, 0
s_and_not1_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB0_5
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, 0
v_mov_b32_e32 v0, v6
v_mov_b32_e32 v10, 0
s_mov_b32 s17, 0
s_mov_b32 s18, 0
.p2align 6
.LBB0_8:
s_mov_b32 s19, 0
.p2align 6
.LBB0_9:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_dual_mov_b32 v12, 0 :: v_dual_add_nc_u32 v11, s19, v0
s_add_i32 s8, s17, s19
s_lshl_b64 s[20:21], s[8:9], 2
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_add_u32 s20, s2, s20
s_addc_u32 s21, s3, s21
s_add_i32 s19, s19, 1
s_load_b32 s8, s[20:21], 0x0
s_cmp_eq_u32 s12, s19
v_add_co_u32 v11, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
global_load_b32 v11, v[11:12], off
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v12, v11
v_cvt_f32_ubyte1_e32 v13, v11
v_cvt_f32_ubyte2_e32 v11, v11
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_fmac_f32 v9, s8, v12 :: v_dual_fmac_f32 v10, s8, v13
v_fmac_f32_e32 v8, s8, v11
s_cbranch_scc0 .LBB0_9
v_add_nc_u32_e32 v0, s11, v0
s_add_i32 s18, s18, 1
s_add_i32 s17, s17, s12
s_cmp_eq_u32 s18, s12
s_cbranch_scc0 .LBB0_8
s_branch .LBB0_5
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17filter_image_cudaPjS_jjPKfijjjj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 22
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17filter_image_cudaPjS_jjPKfijjjj, .Lfunc_end0-_Z17filter_image_cudaPjS_jjPKfijjjj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17filter_image_cudaPjS_jjPKfijjjj
.private_segment_fixed_size: 0
.sgpr_count: 24
.sgpr_spill_count: 0
.symbol: _Z17filter_image_cudaPjS_jjPKfijjjj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17filter_image_cudaPjS_jjPKfijjjj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002200 */
/*0030*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ IADD3 R3, R0, c[0x0][0x188], RZ ; /* 0x0000620000037a10 */
/* 0x000fc80007ffe0ff */
/*0050*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x190], PT ; /* 0x0000640003007a0c */
/* 0x000fda0003f06070 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0080*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff067624 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00a0*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e640000002100 */
/*00b0*/ IADD3 R8, R6, -0x1, RZ ; /* 0xffffffff06087810 */
/* 0x000fc80007ffe0ff */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R8, 0x3, PT ; /* 0x000000030800780c */
/* 0x000fe20003f06070 */
/*00d0*/ IMAD R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a24 */
/* 0x001fca00078e02ff */
/*00e0*/ LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff027212 */
/* 0x000fe400078e33ff */
/*00f0*/ IADD3 R5, -R7.reuse, c[0x0][0x18c], -R0 ; /* 0x0000630007057a10 */
/* 0x042fe40007ffe900 */
/*0100*/ IADD3 R2, -R7, c[0x0][0x18c], R2 ; /* 0x0000630007027a10 */
/* 0x000fe40007ffe102 */
/*0110*/ IADD3 R0, R0, c[0x0][0x188], R7 ; /* 0x0000620000007a10 */
/* 0x000fe40007ffe007 */
/*0120*/ IADD3 R4, R2, -c[0x0][0x188], RZ ; /* 0x8000620002047a10 */
/* 0x000fe40007ffe0ff */
/*0130*/ LOP3.LUT R2, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306027812 */
/* 0x000fc400078ec0ff */
/*0140*/ IADD3 R7, R5, -c[0x0][0x188], RZ ; /* 0x8000620005077a10 */
/* 0x000fe40007ffe0ff */
/*0150*/ ISETP.GE.U32.AND P1, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f26070 */
/*0160*/ IADD3 R4, R2, -c[0x0][0x184], RZ ; /* 0x8000610002047a10 */
/* 0x000fe40007ffe0ff */
/*0170*/ IADD3 R6, R0.reuse, 0x1, RZ ; /* 0x0000000100067810 */
/* 0x040fe40007ffe0ff */
/*0180*/ IADD3 R8, R0.reuse, 0x2, RZ ; /* 0x0000000200087810 */
/* 0x040fe40007ffe0ff */
/*0190*/ IADD3 R5, R0, 0x3, RZ ; /* 0x0000000300057810 */
/* 0x000fc40007ffe0ff */
/*01a0*/ LOP3.LUT R7, R7, 0x3, RZ, 0xc0, !PT ; /* 0x0000000307077812 */
/* 0x000fe400078ec0ff */
/*01b0*/ ISETP.GE.U32.AND P2, PT, R0, c[0x0][0x18c], PT ; /* 0x0000630000007a0c */
/* 0x000fe20003f46070 */
/*01c0*/ BSSY B0, 0xe00 ; /* 0x00000c3000007945 */
/* 0x000fd80003800000 */
/*01d0*/ @P2 BRA 0xdf0 ; /* 0x00000c1000002947 */
/* 0x003fea0003800000 */
/*01e0*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x184], PT ; /* 0x00006100ff007a0c */
/* 0x000fda0003f45270 */
/*01f0*/ @!P2 BRA 0xaa0 ; /* 0x000008a00000a947 */
/* 0x000fea0003800000 */
/*0200*/ IADD3 R9, R3, -c[0x0][0x188], RZ ; /* 0x8000620003097a10 */
/* 0x000fe20007ffe0ff */
/*0210*/ IMAD.MOV.U32 R10, RZ, RZ, R0 ; /* 0x000000ffff0a7224 */
/* 0x000fc800078e0000 */
/*0220*/ HFMA2.MMA R29, -RZ, RZ, 0, 0 ; /* 0x00000000ff1d7435 */
/* 0x000fe200000001ff */
/*0230*/ IADD3 R11, R10, -c[0x0][0x188], RZ ; /* 0x800062000a0b7a10 */
/* 0x001fe20007ffe0ff */
/*0240*/ CS2R R26, SRZ ; /* 0x00000000001a7805 */
/* 0x000fe2000001ff00 */
/*0250*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fc800078e00ff */
/*0260*/ IMAD.IADD R12, R9, 0x1, R14.reuse ; /* 0x00000001090c7824 */
/* 0x100fe400078e020e */
/*0270*/ IMAD.MOV.U32 R15, RZ, RZ, R14 ; /* 0x000000ffff0f7224 */
/* 0x000fe200078e000e */
/*0280*/ IADD3 R14, R14, 0x1, RZ ; /* 0x000000010e0e7810 */
/* 0x000fe20007ffe0ff */
/*0290*/ IMAD.MOV.U32 R23, RZ, RZ, RZ ; /* 0x000000ffff177224 */
/* 0x000fe400078e00ff */
/*02a0*/ IMAD R19, R12, c[0x0][0x170], R11 ; /* 0x00005c000c137a24 */
/* 0x000fe200078e020b */
/*02b0*/ ISETP.GE.U32.AND P2, PT, R14, c[0x0][0x184], PT ; /* 0x000061000e007a0c */
/* 0x000fe20003f46070 */
/*02c0*/ @!P0 BRA 0x670 ; /* 0x000003a000008947 */
/* 0x000fea0003800000 */
/*02d0*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff0c7624 */
/* 0x000fe200078e00ff */
/*02e0*/ MOV R13, R19 ; /* 0x00000013000d7202 */
/* 0x000fe20000000f00 */
/*02f0*/ IMAD.MOV.U32 R23, RZ, RZ, RZ ; /* 0x000000ffff177224 */
/* 0x000fc400078e00ff */
/*0300*/ IMAD R12, R15, R12, 0x3 ; /* 0x000000030f0c7424 */
/* 0x000fc600078e020c */
/*0310*/ IMAD.MOV.U32 R22, RZ, RZ, 0x4 ; /* 0x00000004ff167424 */
/* 0x000fc800078e00ff */
/*0320*/ IMAD.WIDE.U32 R24, R13, R22, c[0x0][0x168] ; /* 0x00005a000d187625 */
/* 0x000fe200078e0016 */
/*0330*/ IADD3 R17, R12, -0x3, RZ ; /* 0xfffffffd0c117810 */
/* 0x000fca0007ffe0ff */
/*0340*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x0000a2000c1e1900 */
/*0350*/ IMAD.WIDE.U32 R16, R17, R22, c[0x0][0x178] ; /* 0x00005e0011107625 */
/* 0x000fcc00078e0016 */
/*0360*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0004e2000c1e1900 */
/*0370*/ IADD3 R19, R13, 0x1, RZ ; /* 0x000000010d137810 */
/* 0x000fca0007ffe0ff */
/*0380*/ IMAD.WIDE.U32 R18, R19, R22, c[0x0][0x168] ; /* 0x00005a0013127625 */
/* 0x000fca00078e0016 */
/*0390*/ LDG.E R28, [R18.64] ; /* 0x00000004121c7981 */
/* 0x000322000c1e1900 */
/*03a0*/ IADD3 R21, R12, -0x2, RZ ; /* 0xfffffffe0c157810 */
/* 0x000fca0007ffe0ff */
/*03b0*/ IMAD.WIDE.U32 R20, R21, R22, c[0x0][0x178] ; /* 0x00005e0015147625 */
/* 0x000fca00078e0016 */
/*03c0*/ LDG.E R24, [R20.64] ; /* 0x0000000414187981 */
/* 0x001162000c1e1900 */
/*03d0*/ I2F.U8 R17, R25 ; /* 0x0000001900117306 */
/* 0x004ef00000001000 */
/*03e0*/ I2F.U8 R19, R25.B2 ; /* 0x2000001900137306 */
/* 0x002e620000001000 */
/*03f0*/ FFMA R29, R17, R16, R29 ; /* 0x00000010111d7223 */
/* 0x008fce000000001d */
/*0400*/ I2F.U8 R17, R25.B1 ; /* 0x1000001900117306 */
/* 0x0002b00000001000 */
/*0410*/ I2F.U8 R18, R28 ; /* 0x0000001c00127306 */
/* 0x010f620000001000 */
/*0420*/ FFMA R25, R16.reuse, R19, R27 ; /* 0x0000001310197223 */
/* 0x042fe4000000001b */
/*0430*/ FFMA R26, R16, R17, R26 ; /* 0x00000011101a7223 */
/* 0x004fe2000000001a */
/*0440*/ IADD3 R17, R13, 0x2, RZ ; /* 0x000000020d117810 */
/* 0x000fc80007ffe0ff */
/*0450*/ I2F.U8 R21, R28.B1 ; /* 0x1000001c00157306 */
/* 0x001e220000001000 */
/*0460*/ IMAD.WIDE.U32 R16, R17, R22, c[0x0][0x168] ; /* 0x00005a0011107625 */
/* 0x000fe200078e0016 */
/*0470*/ IADD3 R19, R12, -0x1, RZ ; /* 0xffffffff0c137810 */
/* 0x000fca0007ffe0ff */
/*0480*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0000a2000c1e1900 */
/*0490*/ FFMA R29, R18, R24, R29 ; /* 0x00000018121d7223 */
/* 0x020fe2000000001d */
/*04a0*/ IADD3 R27, R13, 0x3, RZ ; /* 0x000000030d1b7810 */
/* 0x000fe20007ffe0ff */
/*04b0*/ IMAD.WIDE.U32 R18, R19, R22, c[0x0][0x178] ; /* 0x00005e0013127625 */
/* 0x000fcc00078e0016 */
/*04c0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0002e2000c1e1900 */
/*04d0*/ FFMA R17, R24, R21, R26 ; /* 0x0000001518117223 */
/* 0x001fe4000000001a */
/*04e0*/ IMAD.WIDE.U32 R20, R27, R22, c[0x0][0x168] ; /* 0x00005a001b147625 */
/* 0x000fcc00078e0016 */
/*04f0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000f22000c1e1900 */
/*0500*/ IMAD.WIDE.U32 R26, R12, R22, c[0x0][0x178] ; /* 0x00005e000c1a7625 */
/* 0x000fcc00078e0016 */
/*0510*/ LDG.E R27, [R26.64] ; /* 0x000000041a1b7981 */
/* 0x000762000c1e1900 */
/*0520*/ I2F.U8 R28, R28.B2 ; /* 0x2000001c001c7306 */
/* 0x000e220000001000 */
/*0530*/ IADD3 R23, R23, 0x4, RZ ; /* 0x0000000417177810 */
/* 0x000fe40007ffe0ff */
/*0540*/ IADD3 R13, R13, 0x4, RZ ; /* 0x000000040d0d7810 */
/* 0x000fe40007ffe0ff */
/*0550*/ IADD3 R12, R12, 0x4, RZ ; /* 0x000000040c0c7810 */
/* 0x000fe20007ffe0ff */
/*0560*/ FFMA R25, R24, R28, R25 ; /* 0x0000001c18197223 */
/* 0x001fe40000000019 */
/*0570*/ I2F.U8 R22, R16 ; /* 0x0000001000167306 */
/* 0x004ef00000001000 */
/*0580*/ I2F.U8 R24, R16.B1 ; /* 0x1000001000187306 */
/* 0x000e300000001000 */
/*0590*/ I2F.U8 R19, R16.B2 ; /* 0x2000001000137306 */
/* 0x002e620000001000 */
/*05a0*/ FFMA R26, R22, R18, R29 ; /* 0x00000012161a7223 */
/* 0x008fc4000000001d */
/*05b0*/ FFMA R22, R18, R24, R17 ; /* 0x0000001812167223 */
/* 0x001fca0000000011 */
/*05c0*/ I2F.U8 R29, R20 ; /* 0x00000014001d7306 */
/* 0x010f620000001000 */
/*05d0*/ FFMA R19, R18, R19, R25 ; /* 0x0000001312137223 */
/* 0x002fce0000000019 */
/*05e0*/ I2F.U8 R17, R20.B1 ; /* 0x1000001400117306 */
/* 0x000e220000001000 */
/*05f0*/ IMAD.IADD R18, R4, 0x1, R23 ; /* 0x0000000104127824 */
/* 0x000fca00078e0217 */
/*0600*/ ISETP.NE.AND P3, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fe40003f65270 */
/*0610*/ I2F.U8 R24, R20.B2 ; /* 0x2000001400187306 */
/* 0x000e620000001000 */
/*0620*/ FFMA R29, R29, R27, R26 ; /* 0x0000001b1d1d7223 */
/* 0x020fe4000000001a */
/*0630*/ FFMA R26, R27.reuse, R17, R22 ; /* 0x000000111b1a7223 */
/* 0x041fe40000000016 */
/*0640*/ FFMA R27, R27, R24, R19 ; /* 0x000000181b1b7223 */
/* 0x002fcc0000000013 */
/*0650*/ @P3 BRA 0x310 ; /* 0xfffffcb000003947 */
/* 0x000fea000383ffff */
/*0660*/ MOV R19, R13 ; /* 0x0000000d00137202 */
/* 0x000fe40000000f00 */
/*0670*/ ISETP.NE.AND P3, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f65270 */
/*0680*/ @!P3 BRA 0x900 ; /* 0x000002700000b947 */
/* 0x000fea0003800000 */
/*0690*/ IMAD.MOV.U32 R22, RZ, RZ, 0x4 ; /* 0x00000004ff167424 */
/* 0x000fc800078e00ff */
/*06a0*/ IMAD.WIDE.U32 R12, R19, R22, c[0x0][0x168] ; /* 0x00005a00130c7625 */
/* 0x000fcc00078e0016 */
/*06b0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea2000c1e1900 */
/*06c0*/ IMAD R23, R15, c[0x0][0x184], R23 ; /* 0x000061000f177a24 */
/* 0x000fc800078e0217 */
/*06d0*/ IMAD.WIDE.U32 R16, R23, R22, c[0x0][0x178] ; /* 0x00005e0017107625 */
/* 0x000fcc00078e0016 */
/*06e0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ee2000c1e1900 */
/*06f0*/ ISETP.NE.AND P3, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f65270 */
/*0700*/ I2F.U8 R18, R12 ; /* 0x0000000c00127306 */
/* 0x004ef00000001000 */
/*0710*/ I2F.U8 R15, R12.B1 ; /* 0x1000000c000f7306 */
/* 0x000e300000001000 */
/*0720*/ I2F.U8 R20, R12.B2 ; /* 0x2000000c00147306 */
/* 0x000e620000001000 */
/*0730*/ FFMA R29, R18, R16, R29 ; /* 0x00000010121d7223 */
/* 0x008fc4000000001d */
/*0740*/ FFMA R26, R16.reuse, R15, R26 ; /* 0x0000000f101a7223 */
/* 0x041fe4000000001a */
/*0750*/ FFMA R27, R16, R20, R27 ; /* 0x00000014101b7223 */
/* 0x002fe2000000001b */
/*0760*/ @!P3 BRA 0x900 ; /* 0x000001900000b947 */
/* 0x000fea0003800000 */
/*0770*/ ISETP.NE.AND P3, PT, R2, 0x2, PT ; /* 0x000000020200780c */
/* 0x000fe40003f65270 */
/*0780*/ IADD3 R21, R19, 0x1, RZ ; /* 0x0000000113157810 */
/* 0x000fca0007ffe0ff */
/*0790*/ IMAD.WIDE.U32 R20, R21, R22, c[0x0][0x168] ; /* 0x00005a0015147625 */
/* 0x000fcc00078e0016 */
/*07a0*/ @P3 IADD3 R19, R19, 0x2, RZ ; /* 0x0000000213133810 */
/* 0x000fe20007ffe0ff */
/*07b0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000ea8000c1e1900 */
/*07c0*/ @P3 IMAD.WIDE.U32 R18, R19, R22, c[0x0][0x168] ; /* 0x00005a0013123625 */
/* 0x000fe200078e0016 */
/*07d0*/ IADD3 R17, R23, 0x1, RZ ; /* 0x0000000117117810 */
/* 0x000fca0007ffe0ff */
/*07e0*/ @P3 LDG.E R18, [R18.64] ; /* 0x0000000412123981 */
/* 0x000ee2000c1e1900 */
/*07f0*/ @P3 IADD3 R13, R23, 0x2, RZ ; /* 0x00000002170d3810 */
/* 0x000fe20007ffe0ff */
/*0800*/ IMAD.WIDE.U32 R16, R17, R22, c[0x0][0x178] ; /* 0x00005e0011107625 */
/* 0x000fc800078e0016 */
/*0810*/ @P3 IMAD.WIDE.U32 R12, R13, R22, c[0x0][0x178] ; /* 0x00005e000d0c3625 */
/* 0x000fe400078e0016 */
/*0820*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*0830*/ @P3 LDG.E R12, [R12.64] ; /* 0x000000040c0c3981 */
/* 0x000f62000c1e1900 */
/*0840*/ I2F.U8 R22, R20 ; /* 0x0000001400167306 */
/* 0x004f300000001000 */
/*0850*/ I2F.U8 R15, R20.B1 ; /* 0x10000014000f7306 */
/* 0x000e300000001000 */
/*0860*/ I2F.U8 R23, R20.B2 ; /* 0x2000001400177306 */
/* 0x000e700000001000 */
/*0870*/ @P3 I2F.U8 R24, R18 ; /* 0x0000001200183306 */
/* 0x008f700000001000 */
/*0880*/ @P3 I2F.U8 R19, R18.B1 ; /* 0x1000001200133306 */
/* 0x000eb00000001000 */
/*0890*/ @P3 I2F.U8 R21, R18.B2 ; /* 0x2000001200153306 */
/* 0x000ee20000001000 */
/*08a0*/ FFMA R29, R22, R16, R29 ; /* 0x00000010161d7223 */
/* 0x010fc4000000001d */
/*08b0*/ FFMA R26, R16.reuse, R15, R26 ; /* 0x0000000f101a7223 */
/* 0x041fe4000000001a */
/*08c0*/ FFMA R27, R16, R23, R27 ; /* 0x00000017101b7223 */
/* 0x002fe4000000001b */
/*08d0*/ @P3 FFMA R29, R24, R12, R29 ; /* 0x0000000c181d3223 */
/* 0x020fe4000000001d */
/*08e0*/ @P3 FFMA R26, R12.reuse, R19, R26 ; /* 0x000000130c1a3223 */
/* 0x044fe4000000001a */
/*08f0*/ @P3 FFMA R27, R12, R21, R27 ; /* 0x000000150c1b3223 */
/* 0x008fe4000000001b */
/*0900*/ @!P2 BRA 0x260 ; /* 0xfffff9500000a947 */
/* 0x000fea000383ffff */
/*0910*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe400078e00ff */
/*0920*/ IMAD R12, R3, c[0x0][0x170], R10 ; /* 0x00005c00030c7a24 */
/* 0x000fc800078e020a */
/*0930*/ IMAD.WIDE.U32 R12, R12, R13, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x000fca00078e000d */
/*0940*/ LDG.E R11, [R12.64] ; /* 0x000000040c0b7981 */
/* 0x000ea2000c1e1900 */
/*0950*/ FSETP.GEU.AND P2, PT, R27.reuse, RZ, PT ; /* 0x000000ff1b00720b */
/* 0x040fe40003f4e000 */
/*0960*/ IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a7810 */
/* 0x000fe40007ffe0ff */
/*0970*/ FSEL R27, R27, RZ, P2 ; /* 0x000000ff1b1b7208 */
/* 0x000fe40001000000 */
/*0980*/ FSETP.GEU.AND P2, PT, R26.reuse, RZ, PT ; /* 0x000000ff1a00720b */
/* 0x040fe40003f4e000 */
/*0990*/ FMNMX.NAN R27, R27, 255, PT ; /* 0x437f00001b1b7809 */
/* 0x000fe40003820000 */
/*09a0*/ FSEL R26, R26, RZ, P2 ; /* 0x000000ff1a1a7208 */
/* 0x000fc40001000000 */
/*09b0*/ FSETP.GEU.AND P2, PT, R29.reuse, RZ, PT ; /* 0x000000ff1d00720b */
/* 0x040fe40003f4e000 */
/*09c0*/ FMNMX.NAN R26, R26, 255, PT ; /* 0x437f00001a1a7809 */
/* 0x000fe20003820000 */
/*09d0*/ F2I.U32.TRUNC.NTZ R27, R27 ; /* 0x0000001b001b7305 */
/* 0x000e22000020f000 */
/*09e0*/ FSEL R29, R29, RZ, P2 ; /* 0x000000ff1d1d7208 */
/* 0x000fe40001000000 */
/*09f0*/ ISETP.GE.U32.AND P2, PT, R10, c[0x0][0x18c], PT ; /* 0x000063000a007a0c */
/* 0x000fe40003f46070 */
/*0a00*/ FMNMX.NAN R29, R29, 255, PT ; /* 0x437f00001d1d7809 */
/* 0x000fc60003820000 */
/*0a10*/ F2I.U32.TRUNC.NTZ R26, R26 ; /* 0x0000001a001a7305 */
/* 0x000e70000020f000 */
/*0a20*/ F2I.U32.TRUNC.NTZ R29, R29 ; /* 0x0000001d001d7305 */
/* 0x000ee2000020f000 */
/*0a30*/ IMAD.U32 R14, R27, 0x10000, RZ ; /* 0x000100001b0e7824 */
/* 0x001fe200078e00ff */
/*0a40*/ SHF.L.U32 R16, R26, 0x8, RZ ; /* 0x000000081a107819 */
/* 0x002fc800000006ff */
/*0a50*/ LOP3.LUT R11, R14, 0xff000000, R11, 0xf8, !PT ; /* 0xff0000000e0b7812 */
/* 0x004fc800078ef80b */
/*0a60*/ LOP3.LUT R11, R29, R11, R16, 0xfe, !PT ; /* 0x0000000b1d0b7212 */
/* 0x008fca00078efe10 */
/*0a70*/ STG.E [R12.64], R11 ; /* 0x0000000b0c007986 */
/* 0x0001e2000c101904 */
/*0a80*/ @!P2 BRA 0x220 ; /* 0xfffff7900000a947 */
/* 0x000fea000383ffff */
/*0a90*/ BRA 0xdf0 ; /* 0x0000035000007947 */
/* 0x000fea0003800000 */
/*0aa0*/ ISETP.NE.AND P2, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f45270 */
/*0ab0*/ BSSY B1, 0xc60 ; /* 0x000001a000017945 */
/* 0x000fe20003800000 */
/*0ac0*/ IMAD.MOV.U32 R16, RZ, RZ, R0 ; /* 0x000000ffff107224 */
/* 0x000fd600078e0000 */
/*0ad0*/ @!P2 BRA 0xc50 ; /* 0x000001700000a947 */
/* 0x000fea0003800000 */
/*0ae0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe400078e00ff */
/*0af0*/ IMAD R10, R3, c[0x0][0x170], R0 ; /* 0x00005c00030a7a24 */
/* 0x000fc800078e0200 */
/*0b00*/ IMAD.WIDE.U32 R10, R10, R13, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fca00078e000d */
/*0b10*/ LDG.E R9, [R10.64] ; /* 0x000000040a097981 */
/* 0x000ea2000c1e1900 */
/*0b20*/ ISETP.NE.AND P2, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fe20003f45270 */
/*0b30*/ IMAD.MOV.U32 R16, RZ, RZ, R6 ; /* 0x000000ffff107224 */
/* 0x000fe200078e0006 */
/*0b40*/ LOP3.LUT R9, R9, 0xff000000, RZ, 0xc0, !PT ; /* 0xff00000009097812 */
/* 0x004fca00078ec0ff */
/*0b50*/ STG.E [R10.64], R9 ; /* 0x000000090a007986 */
/* 0x0001ec000c101904 */
/*0b60*/ @!P2 BRA 0xc50 ; /* 0x000000e00000a947 */
/* 0x000fea0003800000 */
/*0b70*/ IMAD R10, R3, c[0x0][0x170], R6 ; /* 0x00005c00030a7a24 */
/* 0x001fc800078e0206 */
/*0b80*/ IMAD.WIDE.U32 R10, R10, R13, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fca00078e000d */
/*0b90*/ LDG.E R9, [R10.64] ; /* 0x000000040a097981 */
/* 0x000ea2000c1e1900 */
/*0ba0*/ ISETP.NE.AND P2, PT, R7, 0x2, PT ; /* 0x000000020700780c */
/* 0x000fe40003f45270 */
/*0bb0*/ MOV R16, R8 ; /* 0x0000000800107202 */
/* 0x000fe40000000f00 */
/*0bc0*/ LOP3.LUT R9, R9, 0xff000000, RZ, 0xc0, !PT ; /* 0xff00000009097812 */
/* 0x004fca00078ec0ff */
/*0bd0*/ STG.E [R10.64], R9 ; /* 0x000000090a007986 */
/* 0x0001e8000c101904 */
/*0be0*/ @!P2 BRA 0xc50 ; /* 0x000000600000a947 */
/* 0x000fea0003800000 */
/*0bf0*/ IMAD R10, R3, c[0x0][0x170], R8 ; /* 0x00005c00030a7a24 */
/* 0x001fc800078e0208 */
/*0c00*/ IMAD.WIDE.U32 R10, R10, R13, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fca00078e000d */
/*0c10*/ LDG.E R9, [R10.64] ; /* 0x000000040a097981 */
/* 0x000ea2000c1e1900 */
/*0c20*/ IMAD.MOV.U32 R16, RZ, RZ, R5 ; /* 0x000000ffff107224 */
/* 0x000fe200078e0005 */
/*0c30*/ LOP3.LUT R9, R9, 0xff000000, RZ, 0xc0, !PT ; /* 0xff00000009097812 */
/* 0x004fca00078ec0ff */
/*0c40*/ STG.E [R10.64], R9 ; /* 0x000000090a007986 */
/* 0x0001e4000c101904 */
/*0c50*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0c60*/ @!P1 BRA 0xdf0 ; /* 0x0000018000009947 */
/* 0x000fea0003800000 */
/*0c70*/ IMAD.MOV.U32 R20, RZ, RZ, 0x4 ; /* 0x00000004ff147424 */
/* 0x000fe400078e00ff */
/*0c80*/ IMAD R9, R3, c[0x0][0x170], R16 ; /* 0x00005c0003097a24 */
/* 0x003fc800078e0210 */
/*0c90*/ IMAD.WIDE.U32 R10, R9, R20, c[0x0][0x160] ; /* 0x00005800090a7625 */
/* 0x000fca00078e0014 */
/*0ca0*/ LDG.E R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x000ea2000c1e1900 */
/*0cb0*/ IADD3 R13, R9, 0x1, RZ ; /* 0x00000001090d7810 */
/* 0x000fe40007ffe0ff */
/*0cc0*/ LOP3.LUT R17, R12, 0xff000000, RZ, 0xc0, !PT ; /* 0xff0000000c117812 */
/* 0x004fc600078ec0ff */
/*0cd0*/ IMAD.WIDE.U32 R12, R13, R20, c[0x0][0x160] ; /* 0x000058000d0c7625 */
/* 0x000fe400078e0014 */
/*0ce0*/ STG.E [R10.64], R17 ; /* 0x000000110a007986 */
/* 0x0001e8000c101904 */
/*0cf0*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ea2000c1e1900 */
/*0d00*/ IADD3 R15, R9, 0x2, RZ ; /* 0x00000002090f7810 */
/* 0x000fe40007ffe0ff */
/*0d10*/ LOP3.LUT R21, R14, 0xff000000, RZ, 0xc0, !PT ; /* 0xff0000000e157812 */
/* 0x004fc600078ec0ff */
/*0d20*/ IMAD.WIDE.U32 R14, R15, R20, c[0x0][0x160] ; /* 0x000058000f0e7625 */
/* 0x000fe400078e0014 */
/*0d30*/ STG.E [R12.64], R21 ; /* 0x000000150c007986 */
/* 0x0003e8000c101904 */
/*0d40*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000ea2000c1e1900 */
/*0d50*/ IADD3 R19, R9, 0x3, RZ ; /* 0x0000000309137810 */
/* 0x000fe40007ffe0ff */
/*0d60*/ LOP3.LUT R9, R18, 0xff000000, RZ, 0xc0, !PT ; /* 0xff00000012097812 */
/* 0x004fc600078ec0ff */
/*0d70*/ IMAD.WIDE.U32 R18, R19, R20, c[0x0][0x160] ; /* 0x0000580013127625 */
/* 0x000fe400078e0014 */
/*0d80*/ STG.E [R14.64], R9 ; /* 0x000000090e007986 */
/* 0x0003e8000c101904 */
/*0d90*/ LDG.E R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x001ea2000c1e1900 */
/*0da0*/ IADD3 R16, R16, 0x4, RZ ; /* 0x0000000410107810 */
/* 0x000fc80007ffe0ff */
/*0db0*/ ISETP.GE.U32.AND P2, PT, R16, c[0x0][0x18c], PT ; /* 0x0000630010007a0c */
/* 0x000fe40003f46070 */
/*0dc0*/ LOP3.LUT R11, R10, 0xff000000, RZ, 0xc0, !PT ; /* 0xff0000000a0b7812 */
/* 0x004fca00078ec0ff */
/*0dd0*/ STG.E [R18.64], R11 ; /* 0x0000000b12007986 */
/* 0x0003ec000c101904 */
/*0de0*/ @!P2 BRA 0xc70 ; /* 0xfffffe800000a947 */
/* 0x000fea000383ffff */
/*0df0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0e00*/ IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103037810 */
/* 0x000fc80007ffe0ff */
/*0e10*/ ISETP.GE.U32.AND P2, PT, R3, c[0x0][0x190], PT ; /* 0x0000640003007a0c */
/* 0x000fda0003f46070 */
/*0e20*/ @!P2 BRA 0x1b0 ; /* 0xfffff3800000a947 */
/* 0x000fea000383ffff */
/*0e30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0e40*/ BRA 0xe40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17filter_image_cudaPjS_jjPKfijjjj
.globl _Z17filter_image_cudaPjS_jjPKfijjjj
.p2align 8
.type _Z17filter_image_cudaPjS_jjPKfijjjj,@function
_Z17filter_image_cudaPjS_jjPKfijjjj:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x44
s_load_b32 s8, s[0:1], 0x28
s_load_b32 s10, s[0:1], 0x30
s_add_u32 s2, s0, 56
v_bfe_u32 v1, v0, 10, 10
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mul_i32 s15, s15, s4
s_mov_b32 s4, exec_lo
v_add3_u32 v2, s15, s8, v1
v_cmpx_gt_u32_e64 s10, v2
s_cbranch_execz .LBB0_11
s_load_b32 s9, s[2:3], 0xc
s_clause 0x4
s_load_b32 s11, s[0:1], 0x10
s_load_b32 s12, s[0:1], 0x24
s_load_b32 s13, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x18
v_add_nc_u32_e32 v1, s15, v1
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s9, 0xffff
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, s11, v1
s_mul_i32 s14, s14, s0
s_cmp_lg_u32 s12, 0
s_mov_b32 s9, 0
s_cselect_b32 s1, -1, 0
v_add3_u32 v4, v0, v1, s14
v_mov_b32_e32 v1, 0
v_add3_u32 v3, s14, s8, v0
s_mov_b32 s14, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u32_e64 s0, s13, v3
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s15
v_add_nc_u32_e32 v2, 1, v2
v_add_nc_u32_e32 v4, s11, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_u32_e32 vcc_lo, s10, v2
s_or_b32 s14, vcc_lo, s14
s_and_not1_b32 exec_lo, exec_lo, s14
s_cbranch_execz .LBB0_11
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s15, s0
s_cbranch_execz .LBB0_2
v_mul_lo_u32 v5, v2, s11
v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v7, v3
s_mov_b32 s16, 0
s_branch .LBB0_6
.LBB0_5:
v_add_nc_u32_e32 v0, v7, v5
v_add_nc_u32_e32 v6, 1, v6
v_add_nc_u32_e32 v7, 1, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[11:12], 2, v[0:1]
v_add_co_u32 v11, vcc_lo, s4, v11
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0, v10
global_load_b32 v0, v[11:12], off
v_cndmask_b32_e32 v10, 0, v10, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0, v8
v_cndmask_b32_e32 v8, 0, v8, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0, v9
v_cndmask_b32_e32 v9, 0, v9, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x437f0000, v10
v_cndmask_b32_e32 v10, 0x437f0000, v10, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x437f0000, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v10, v10
v_cndmask_b32_e32 v8, 0x437f0000, v8, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x437f0000, v9
v_cvt_u32_f32_e32 v8, v8
v_cndmask_b32_e32 v9, 0x437f0000, v9, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s13, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b32_e32 v8, 16, v8
v_cvt_u32_f32_e32 v9, v9
s_or_b32 s16, vcc_lo, s16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshl_or_b32 v9, v10, 8, v9
s_waitcnt vmcnt(0)
v_and_b32_e32 v0, 0xff000000, v0
v_or3_b32 v0, v9, v8, v0
global_store_b32 v[11:12], v0, off
s_and_not1_b32 exec_lo, exec_lo, s16
s_cbranch_execz .LBB0_2
.LBB0_6:
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, 0
v_mov_b32_e32 v10, 0
s_and_not1_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB0_5
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, 0
v_mov_b32_e32 v0, v6
v_mov_b32_e32 v10, 0
s_mov_b32 s17, 0
s_mov_b32 s18, 0
.p2align 6
.LBB0_8:
s_mov_b32 s19, 0
.p2align 6
.LBB0_9:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_dual_mov_b32 v12, 0 :: v_dual_add_nc_u32 v11, s19, v0
s_add_i32 s8, s17, s19
s_lshl_b64 s[20:21], s[8:9], 2
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_add_u32 s20, s2, s20
s_addc_u32 s21, s3, s21
s_add_i32 s19, s19, 1
s_load_b32 s8, s[20:21], 0x0
s_cmp_eq_u32 s12, s19
v_add_co_u32 v11, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
global_load_b32 v11, v[11:12], off
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v12, v11
v_cvt_f32_ubyte1_e32 v13, v11
v_cvt_f32_ubyte2_e32 v11, v11
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_fmac_f32 v9, s8, v12 :: v_dual_fmac_f32 v10, s8, v13
v_fmac_f32_e32 v8, s8, v11
s_cbranch_scc0 .LBB0_9
v_add_nc_u32_e32 v0, s11, v0
s_add_i32 s18, s18, 1
s_add_i32 s17, s17, s12
s_cmp_eq_u32 s18, s12
s_cbranch_scc0 .LBB0_8
s_branch .LBB0_5
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17filter_image_cudaPjS_jjPKfijjjj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 22
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17filter_image_cudaPjS_jjPKfijjjj, .Lfunc_end0-_Z17filter_image_cudaPjS_jjPKfijjjj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17filter_image_cudaPjS_jjPKfijjjj
.private_segment_fixed_size: 0
.sgpr_count: 24
.sgpr_spill_count: 0
.symbol: _Z17filter_image_cudaPjS_jjPKfijjjj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#define N 2 //Número de colunas das matrizes
#define M 2 //Número de linhas das matrizes
#define T 8 //Número de threads por bloco
//Código device
// blockDim.x é a dimensão do bloco, ou seja,
// a quantidade de threads por bloco.
__global__ void soma_matriz(int *a, int *b, int *c){
int i = blockIdx.x*blockDim.x + threadIdx.x;
int j = blockIdx.y*blockDim.y + threadIdx.y;
if(i < M && j < N)
c[N*i + j] = a[N*i + j] + b[N*i + j];
}
//Código host
int main(){
int a[M*N],b[M*N],c[M*N];
int* dev_a;
int* dev_b;
int* dev_c;
int tam = M*N*sizeof(int);
//Inicializando as variáveis do host:
for(int i = 0; i < M*N; i++){
a[i] = i;
b[i] = i*2;
}
//Alocando espaço para as variáveis da GPU:
cudaMalloc((void**)&dev_a, tam);
cudaMalloc((void**)&dev_b, tam);
cudaMalloc((void**)&dev_c, tam);
//Copiando as variáveis da CPU para a GPU:
cudaMemcpy(dev_a, &a, tam, cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, &b, tam, cudaMemcpyHostToDevice);
//Chamada à função da GPU (kernel):
//Número de blocos é igual à dimensão do vetor
//dividida pela dimensão do bloco: N/M
// O tipo dim3 permite definir a quantidade de
// blocos e threads por dimensão. A terceira dimensão é omitida,
// ficando implícito o valor 1.
dim3 numBlocos (2,2); // número de blocos = 2x2 = 4
dim3 numThreads (2,2); // número de threads por bloco = 2x2 = 4
soma_matriz<<<numBlocos,numThreads>>>(dev_a, dev_b, dev_c);
//Copiando o resultado da GPU para a CPU:
cudaMemcpy(&c, dev_c, tam, cudaMemcpyDeviceToHost);
//Visualizando o resultado:
for(int i = 0; i < N; i++){
for(int j = 0; j < M; j++)
printf("%d ",c[N*i+j]);
printf("\n");
}
printf("\n\n");
//Liberando a memória na GPU:
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
return 0;
} | code for sm_80
Function : _Z11soma_matrizPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GT.AND P0, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fe20003f04270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GT.OR P0, PT, R0, 0x1, P0 ; /* 0x000000010000780c */
/* 0x000fda0000704670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ LEA R0, R0, R3, 0x1 ; /* 0x0000000300007211 */
/* 0x000fe200078e08ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0207 */
/*00f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0207 */
/*0120*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#define N 2 //Número de colunas das matrizes
#define M 2 //Número de linhas das matrizes
#define T 8 //Número de threads por bloco
//Código device
// blockDim.x é a dimensão do bloco, ou seja,
// a quantidade de threads por bloco.
__global__ void soma_matriz(int *a, int *b, int *c){
int i = blockIdx.x*blockDim.x + threadIdx.x;
int j = blockIdx.y*blockDim.y + threadIdx.y;
if(i < M && j < N)
c[N*i + j] = a[N*i + j] + b[N*i + j];
}
//Código host
int main(){
int a[M*N],b[M*N],c[M*N];
int* dev_a;
int* dev_b;
int* dev_c;
int tam = M*N*sizeof(int);
//Inicializando as variáveis do host:
for(int i = 0; i < M*N; i++){
a[i] = i;
b[i] = i*2;
}
//Alocando espaço para as variáveis da GPU:
cudaMalloc((void**)&dev_a, tam);
cudaMalloc((void**)&dev_b, tam);
cudaMalloc((void**)&dev_c, tam);
//Copiando as variáveis da CPU para a GPU:
cudaMemcpy(dev_a, &a, tam, cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, &b, tam, cudaMemcpyHostToDevice);
//Chamada à função da GPU (kernel):
//Número de blocos é igual à dimensão do vetor
//dividida pela dimensão do bloco: N/M
// O tipo dim3 permite definir a quantidade de
// blocos e threads por dimensão. A terceira dimensão é omitida,
// ficando implícito o valor 1.
dim3 numBlocos (2,2); // número de blocos = 2x2 = 4
dim3 numThreads (2,2); // número de threads por bloco = 2x2 = 4
soma_matriz<<<numBlocos,numThreads>>>(dev_a, dev_b, dev_c);
//Copiando o resultado da GPU para a CPU:
cudaMemcpy(&c, dev_c, tam, cudaMemcpyDeviceToHost);
//Visualizando o resultado:
for(int i = 0; i < N; i++){
for(int j = 0; j < M; j++)
printf("%d ",c[N*i+j]);
printf("\n");
}
printf("\n\n");
//Liberando a memória na GPU:
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
return 0;
} | .file "tmpxft_000b6906_00000000-6_soma_matriz.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z11soma_matrizPiS_S_PiS_S_
.type _Z35__device_stub__Z11soma_matrizPiS_S_PiS_S_, @function
_Z35__device_stub__Z11soma_matrizPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11soma_matrizPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z11soma_matrizPiS_S_PiS_S_, .-_Z35__device_stub__Z11soma_matrizPiS_S_PiS_S_
.globl _Z11soma_matrizPiS_S_
.type _Z11soma_matrizPiS_S_, @function
_Z11soma_matrizPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11soma_matrizPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z11soma_matrizPiS_S_, .-_Z11soma_matrizPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.LC2:
.string "\n\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $120, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $0, 48(%rsp)
movl $0, 64(%rsp)
movl $1, 52(%rsp)
movl $2, 68(%rsp)
movl $2, 56(%rsp)
movl $4, 72(%rsp)
movl $3, 60(%rsp)
movl $6, 76(%rsp)
movq %rsp, %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $16, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 64(%rsp), %rsi
movl $1, %ecx
movl $16, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, 24(%rsp)
movl $2, 28(%rsp)
movl $2, 36(%rsp)
movl $2, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 80(%rsp), %rdi
movl $2, %ecx
movl $16, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl 80(%rsp), %edx
leaq .LC0(%rip), %rbx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 84(%rsp), %edx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rbp
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 88(%rsp), %edx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 92(%rsp), %edx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z35__device_stub__Z11soma_matrizPiS_S_PiS_S_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z11soma_matrizPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z11soma_matrizPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#define N 2 //Número de colunas das matrizes
#define M 2 //Número de linhas das matrizes
#define T 8 //Número de threads por bloco
//Código device
// blockDim.x é a dimensão do bloco, ou seja,
// a quantidade de threads por bloco.
__global__ void soma_matriz(int *a, int *b, int *c){
int i = blockIdx.x*blockDim.x + threadIdx.x;
int j = blockIdx.y*blockDim.y + threadIdx.y;
if(i < M && j < N)
c[N*i + j] = a[N*i + j] + b[N*i + j];
}
//Código host
int main(){
int a[M*N],b[M*N],c[M*N];
int* dev_a;
int* dev_b;
int* dev_c;
int tam = M*N*sizeof(int);
//Inicializando as variáveis do host:
for(int i = 0; i < M*N; i++){
a[i] = i;
b[i] = i*2;
}
//Alocando espaço para as variáveis da GPU:
cudaMalloc((void**)&dev_a, tam);
cudaMalloc((void**)&dev_b, tam);
cudaMalloc((void**)&dev_c, tam);
//Copiando as variáveis da CPU para a GPU:
cudaMemcpy(dev_a, &a, tam, cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, &b, tam, cudaMemcpyHostToDevice);
//Chamada à função da GPU (kernel):
//Número de blocos é igual à dimensão do vetor
//dividida pela dimensão do bloco: N/M
// O tipo dim3 permite definir a quantidade de
// blocos e threads por dimensão. A terceira dimensão é omitida,
// ficando implícito o valor 1.
dim3 numBlocos (2,2); // número de blocos = 2x2 = 4
dim3 numThreads (2,2); // número de threads por bloco = 2x2 = 4
soma_matriz<<<numBlocos,numThreads>>>(dev_a, dev_b, dev_c);
//Copiando o resultado da GPU para a CPU:
cudaMemcpy(&c, dev_c, tam, cudaMemcpyDeviceToHost);
//Visualizando o resultado:
for(int i = 0; i < N; i++){
for(int j = 0; j < M; j++)
printf("%d ",c[N*i+j]);
printf("\n");
}
printf("\n\n");
//Liberando a memória na GPU:
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define N 2 //Número de colunas das matrizes
#define M 2 //Número de linhas das matrizes
#define T 8 //Número de threads por bloco
//Código device
// blockDim.x é a dimensão do bloco, ou seja,
// a quantidade de threads por bloco.
__global__ void soma_matriz(int *a, int *b, int *c){
int i = blockIdx.x*blockDim.x + threadIdx.x;
int j = blockIdx.y*blockDim.y + threadIdx.y;
if(i < M && j < N)
c[N*i + j] = a[N*i + j] + b[N*i + j];
}
//Código host
int main(){
int a[M*N],b[M*N],c[M*N];
int* dev_a;
int* dev_b;
int* dev_c;
int tam = M*N*sizeof(int);
//Inicializando as variáveis do host:
for(int i = 0; i < M*N; i++){
a[i] = i;
b[i] = i*2;
}
//Alocando espaço para as variáveis da GPU:
hipMalloc((void**)&dev_a, tam);
hipMalloc((void**)&dev_b, tam);
hipMalloc((void**)&dev_c, tam);
//Copiando as variáveis da CPU para a GPU:
hipMemcpy(dev_a, &a, tam, hipMemcpyHostToDevice);
hipMemcpy(dev_b, &b, tam, hipMemcpyHostToDevice);
//Chamada à função da GPU (kernel):
//Número de blocos é igual à dimensão do vetor
//dividida pela dimensão do bloco: N/M
// O tipo dim3 permite definir a quantidade de
// blocos e threads por dimensão. A terceira dimensão é omitida,
// ficando implícito o valor 1.
dim3 numBlocos (2,2); // número de blocos = 2x2 = 4
dim3 numThreads (2,2); // número de threads por bloco = 2x2 = 4
soma_matriz<<<numBlocos,numThreads>>>(dev_a, dev_b, dev_c);
//Copiando o resultado da GPU para a CPU:
hipMemcpy(&c, dev_c, tam, hipMemcpyDeviceToHost);
//Visualizando o resultado:
for(int i = 0; i < N; i++){
for(int j = 0; j < M; j++)
printf("%d ",c[N*i+j]);
printf("\n");
}
printf("\n\n");
//Liberando a memória na GPU:
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define N 2 //Número de colunas das matrizes
#define M 2 //Número de linhas das matrizes
#define T 8 //Número de threads por bloco
//Código device
// blockDim.x é a dimensão do bloco, ou seja,
// a quantidade de threads por bloco.
__global__ void soma_matriz(int *a, int *b, int *c){
int i = blockIdx.x*blockDim.x + threadIdx.x;
int j = blockIdx.y*blockDim.y + threadIdx.y;
if(i < M && j < N)
c[N*i + j] = a[N*i + j] + b[N*i + j];
}
//Código host
int main(){
int a[M*N],b[M*N],c[M*N];
int* dev_a;
int* dev_b;
int* dev_c;
int tam = M*N*sizeof(int);
//Inicializando as variáveis do host:
for(int i = 0; i < M*N; i++){
a[i] = i;
b[i] = i*2;
}
//Alocando espaço para as variáveis da GPU:
hipMalloc((void**)&dev_a, tam);
hipMalloc((void**)&dev_b, tam);
hipMalloc((void**)&dev_c, tam);
//Copiando as variáveis da CPU para a GPU:
hipMemcpy(dev_a, &a, tam, hipMemcpyHostToDevice);
hipMemcpy(dev_b, &b, tam, hipMemcpyHostToDevice);
//Chamada à função da GPU (kernel):
//Número de blocos é igual à dimensão do vetor
//dividida pela dimensão do bloco: N/M
// O tipo dim3 permite definir a quantidade de
// blocos e threads por dimensão. A terceira dimensão é omitida,
// ficando implícito o valor 1.
dim3 numBlocos (2,2); // número de blocos = 2x2 = 4
dim3 numThreads (2,2); // número de threads por bloco = 2x2 = 4
soma_matriz<<<numBlocos,numThreads>>>(dev_a, dev_b, dev_c);
//Copiando o resultado da GPU para a CPU:
hipMemcpy(&c, dev_c, tam, hipMemcpyDeviceToHost);
//Visualizando o resultado:
for(int i = 0; i < N; i++){
for(int j = 0; j < M; j++)
printf("%d ",c[N*i+j]);
printf("\n");
}
printf("\n\n");
//Liberando a memória na GPU:
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11soma_matrizPiS_S_
.globl _Z11soma_matrizPiS_S_
.p2align 8
.type _Z11soma_matrizPiS_S_,@function
_Z11soma_matrizPiS_S_:
s_load_b32 s2, s[0:1], 0x24
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 2, v2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshl_add_u32 v0, v0, 1, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11soma_matrizPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11soma_matrizPiS_S_, .Lfunc_end0-_Z11soma_matrizPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11soma_matrizPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11soma_matrizPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define N 2 //Número de colunas das matrizes
#define M 2 //Número de linhas das matrizes
#define T 8 //Número de threads por bloco
//Código device
// blockDim.x é a dimensão do bloco, ou seja,
// a quantidade de threads por bloco.
__global__ void soma_matriz(int *a, int *b, int *c){
int i = blockIdx.x*blockDim.x + threadIdx.x;
int j = blockIdx.y*blockDim.y + threadIdx.y;
if(i < M && j < N)
c[N*i + j] = a[N*i + j] + b[N*i + j];
}
//Código host
int main(){
int a[M*N],b[M*N],c[M*N];
int* dev_a;
int* dev_b;
int* dev_c;
int tam = M*N*sizeof(int);
//Inicializando as variáveis do host:
for(int i = 0; i < M*N; i++){
a[i] = i;
b[i] = i*2;
}
//Alocando espaço para as variáveis da GPU:
hipMalloc((void**)&dev_a, tam);
hipMalloc((void**)&dev_b, tam);
hipMalloc((void**)&dev_c, tam);
//Copiando as variáveis da CPU para a GPU:
hipMemcpy(dev_a, &a, tam, hipMemcpyHostToDevice);
hipMemcpy(dev_b, &b, tam, hipMemcpyHostToDevice);
//Chamada à função da GPU (kernel):
//Número de blocos é igual à dimensão do vetor
//dividida pela dimensão do bloco: N/M
// O tipo dim3 permite definir a quantidade de
// blocos e threads por dimensão. A terceira dimensão é omitida,
// ficando implícito o valor 1.
dim3 numBlocos (2,2); // número de blocos = 2x2 = 4
dim3 numThreads (2,2); // número de threads por bloco = 2x2 = 4
soma_matriz<<<numBlocos,numThreads>>>(dev_a, dev_b, dev_c);
//Copiando o resultado da GPU para a CPU:
hipMemcpy(&c, dev_c, tam, hipMemcpyDeviceToHost);
//Visualizando o resultado:
for(int i = 0; i < N; i++){
for(int j = 0; j < M; j++)
printf("%d ",c[N*i+j]);
printf("\n");
}
printf("\n\n");
//Liberando a memória na GPU:
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
return 0;
} | .text
.file "soma_matriz.hip"
.globl _Z26__device_stub__soma_matrizPiS_S_ # -- Begin function _Z26__device_stub__soma_matrizPiS_S_
.p2align 4, 0x90
.type _Z26__device_stub__soma_matrizPiS_S_,@function
_Z26__device_stub__soma_matrizPiS_S_: # @_Z26__device_stub__soma_matrizPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11soma_matrizPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z26__device_stub__soma_matrizPiS_S_, .Lfunc_end0-_Z26__device_stub__soma_matrizPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $160, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %ecx, 144(%rsp,%rcx,4)
movl %eax, 128(%rsp,%rcx,4)
incq %rcx
addl $2, %eax
cmpq $4, %rcx
jne .LBB1_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $16, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $16, %esi
callq hipMalloc
movq %rsp, %rdi
movl $16, %esi
callq hipMalloc
movq 16(%rsp), %rdi
leaq 144(%rsp), %rsi
movl $16, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 128(%rsp), %rsi
movl $16, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $8589934594, %rdi # imm = 0x200000002
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11soma_matrizPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
leaq 96(%rsp), %rbx
movl $16, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_5: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_6: # Parent Loop BB1_5 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%r15,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $1, %r15
je .LBB1_6
# %bb.7: # in Loop: Header=BB1_5 Depth=1
movl $10, %edi
callq putchar@PLT
leaq 1(%r14), %rax
addq $8, %rbx
testq %r14, %r14
movq %rax, %r14
je .LBB1_5
# %bb.8:
movl $.Lstr, %edi
callq puts@PLT
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $160, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11soma_matrizPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11soma_matrizPiS_S_,@object # @_Z11soma_matrizPiS_S_
.section .rodata,"a",@progbits
.globl _Z11soma_matrizPiS_S_
.p2align 3, 0x0
_Z11soma_matrizPiS_S_:
.quad _Z26__device_stub__soma_matrizPiS_S_
.size _Z11soma_matrizPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11soma_matrizPiS_S_"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n"
.size .Lstr, 2
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__soma_matrizPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11soma_matrizPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11soma_matrizPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GT.AND P0, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fe20003f04270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GT.OR P0, PT, R0, 0x1, P0 ; /* 0x000000010000780c */
/* 0x000fda0000704670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ LEA R0, R0, R3, 0x1 ; /* 0x0000000300007211 */
/* 0x000fe200078e08ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0207 */
/*00f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0207 */
/*0120*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11soma_matrizPiS_S_
.globl _Z11soma_matrizPiS_S_
.p2align 8
.type _Z11soma_matrizPiS_S_,@function
_Z11soma_matrizPiS_S_:
s_load_b32 s2, s[0:1], 0x24
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 2, v2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshl_add_u32 v0, v0, 1, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11soma_matrizPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11soma_matrizPiS_S_, .Lfunc_end0-_Z11soma_matrizPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11soma_matrizPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11soma_matrizPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b6906_00000000-6_soma_matriz.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z11soma_matrizPiS_S_PiS_S_
.type _Z35__device_stub__Z11soma_matrizPiS_S_PiS_S_, @function
_Z35__device_stub__Z11soma_matrizPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11soma_matrizPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z11soma_matrizPiS_S_PiS_S_, .-_Z35__device_stub__Z11soma_matrizPiS_S_PiS_S_
.globl _Z11soma_matrizPiS_S_
.type _Z11soma_matrizPiS_S_, @function
_Z11soma_matrizPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11soma_matrizPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z11soma_matrizPiS_S_, .-_Z11soma_matrizPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.LC2:
.string "\n\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $120, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $0, 48(%rsp)
movl $0, 64(%rsp)
movl $1, 52(%rsp)
movl $2, 68(%rsp)
movl $2, 56(%rsp)
movl $4, 72(%rsp)
movl $3, 60(%rsp)
movl $6, 76(%rsp)
movq %rsp, %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $16, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 64(%rsp), %rsi
movl $1, %ecx
movl $16, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, 24(%rsp)
movl $2, 28(%rsp)
movl $2, 36(%rsp)
movl $2, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 80(%rsp), %rdi
movl $2, %ecx
movl $16, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl 80(%rsp), %edx
leaq .LC0(%rip), %rbx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 84(%rsp), %edx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rbp
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 88(%rsp), %edx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 92(%rsp), %edx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z35__device_stub__Z11soma_matrizPiS_S_PiS_S_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z11soma_matrizPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z11soma_matrizPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "soma_matriz.hip"
.globl _Z26__device_stub__soma_matrizPiS_S_ # -- Begin function _Z26__device_stub__soma_matrizPiS_S_
.p2align 4, 0x90
.type _Z26__device_stub__soma_matrizPiS_S_,@function
_Z26__device_stub__soma_matrizPiS_S_: # @_Z26__device_stub__soma_matrizPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11soma_matrizPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z26__device_stub__soma_matrizPiS_S_, .Lfunc_end0-_Z26__device_stub__soma_matrizPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $160, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %ecx, 144(%rsp,%rcx,4)
movl %eax, 128(%rsp,%rcx,4)
incq %rcx
addl $2, %eax
cmpq $4, %rcx
jne .LBB1_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $16, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $16, %esi
callq hipMalloc
movq %rsp, %rdi
movl $16, %esi
callq hipMalloc
movq 16(%rsp), %rdi
leaq 144(%rsp), %rsi
movl $16, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 128(%rsp), %rsi
movl $16, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $8589934594, %rdi # imm = 0x200000002
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11soma_matrizPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
leaq 96(%rsp), %rbx
movl $16, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_5: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_6: # Parent Loop BB1_5 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%r15,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $1, %r15
je .LBB1_6
# %bb.7: # in Loop: Header=BB1_5 Depth=1
movl $10, %edi
callq putchar@PLT
leaq 1(%r14), %rax
addq $8, %rbx
testq %r14, %r14
movq %rax, %r14
je .LBB1_5
# %bb.8:
movl $.Lstr, %edi
callq puts@PLT
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $160, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11soma_matrizPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11soma_matrizPiS_S_,@object # @_Z11soma_matrizPiS_S_
.section .rodata,"a",@progbits
.globl _Z11soma_matrizPiS_S_
.p2align 3, 0x0
_Z11soma_matrizPiS_S_:
.quad _Z26__device_stub__soma_matrizPiS_S_
.size _Z11soma_matrizPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11soma_matrizPiS_S_"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n"
.size .Lstr, 2
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__soma_matrizPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11soma_matrizPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Matrix addition, CPU version
// gcc matrix_cpu.c -o matrix_cpu -std=c99
#include <stdio.h>
#include <math.h>
void printDeviceProperties(){
cudaDeviceProp prop;
cudaGetDeviceProperties(&prop, 0);
printf(" Device name: %s\n", prop.name);
printf(" Memory Clock Rate (KHz): %d\n",
prop.memoryClockRate);
printf(" Memory Bus Width (bits): %d\n",
prop.memoryBusWidth);
printf(" Peak Memory Bandwidth (GB/s): %f\n\n",
2.0*prop.memoryClockRate*(prop.memoryBusWidth/8)/1.0e6);
}
__global__
void add_matrix(float *a, float *b, float *c, int N) {
int indexX = blockIdx.x * blockDim.x + threadIdx.x;
int indexY = blockIdx.y * blockDim.y + threadIdx.y;
int index = indexY * N + indexX;
c[index] = a[index] + b[index];
}
// https://www.youtube.com/watch?v=fu0gbHnRGYk
__global__
void clear_my_bitch_out(float *c, int N) {
int indexX = blockIdx.x * blockDim.x + threadIdx.x;
int indexY = blockIdx.y * blockDim.y + threadIdx.y;
int index = indexY * N + indexX;
c[index] = 0;
}
int main() {
printDeviceProperties();
for (unsigned int i = 5; i < 11; i++) {
const int N = pow(2, i);
const int blockSize = pow(2, 4);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float* a = new float[N*N];
float* b = new float[N*N];
float* c = new float[N*N];
float* ad;
float* bd;
float* cd;
const int size = N * N * sizeof(float);
cudaMalloc((void**)&ad, size);
cudaMalloc((void**)&bd, size);
cudaMalloc((void**)&cd, size);
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
a[i+j*N] = 10 + i;
b[i+j*N] = (float)j / N;
}
}
cudaMemcpy(ad, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(bd, b, size, cudaMemcpyHostToDevice);
dim3 dimBlock(blockSize, blockSize);
dim3 dimGrid(N/blockSize, N/blockSize);
cudaEventRecord(start);
add_matrix<<<dimGrid, dimBlock>>>(ad, bd, cd, N);
cudaEventRecord(stop);
cudaThreadSynchronize();
cudaMemcpy(c, cd, size, cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
printf("%0.2f ", c[i+j*N]);
}
printf("\n");
}
printf(
"GPU execution took %f milliseconds for N=%d, Blocks=%dx%d, Grid=%dx%d.\n",
milliseconds, N, dimBlock.x, dimBlock.y, dimGrid.x, dimGrid.y);
// Try to clean up everything on the GPU, and do it twice!
clear_my_bitch_out<<<dimGrid, dimBlock>>>(cd, N);
cudaDeviceReset();
}
} | code for sm_80
Function : _Z18clear_my_bitch_outPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0040*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*0070*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fe200078e0205 */
/*0080*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fc600000001ff */
/*0090*/ IMAD R3, R3, c[0x0][0x168], R0 ; /* 0x00005a0003037a24 */
/* 0x000fce00078e0200 */
/*00a0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0202 */
/*00b0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10add_matrixPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0050*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0060*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc400078e0203 */
/*0080*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fc800078e0205 */
/*0090*/ IMAD R0, R3, c[0x0][0x178], R0 ; /* 0x00005e0003007a24 */
/* 0x000fc800078e0200 */
/*00a0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0207 */
/*00b0*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0207 */
/*00c0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0207 */
/*00f0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*0100*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Matrix addition, CPU version
// gcc matrix_cpu.c -o matrix_cpu -std=c99
#include <stdio.h>
#include <math.h>
void printDeviceProperties(){
cudaDeviceProp prop;
cudaGetDeviceProperties(&prop, 0);
printf(" Device name: %s\n", prop.name);
printf(" Memory Clock Rate (KHz): %d\n",
prop.memoryClockRate);
printf(" Memory Bus Width (bits): %d\n",
prop.memoryBusWidth);
printf(" Peak Memory Bandwidth (GB/s): %f\n\n",
2.0*prop.memoryClockRate*(prop.memoryBusWidth/8)/1.0e6);
}
__global__
void add_matrix(float *a, float *b, float *c, int N) {
int indexX = blockIdx.x * blockDim.x + threadIdx.x;
int indexY = blockIdx.y * blockDim.y + threadIdx.y;
int index = indexY * N + indexX;
c[index] = a[index] + b[index];
}
// https://www.youtube.com/watch?v=fu0gbHnRGYk
__global__
void clear_my_bitch_out(float *c, int N) {
int indexX = blockIdx.x * blockDim.x + threadIdx.x;
int indexY = blockIdx.y * blockDim.y + threadIdx.y;
int index = indexY * N + indexX;
c[index] = 0;
}
int main() {
printDeviceProperties();
for (unsigned int i = 5; i < 11; i++) {
const int N = pow(2, i);
const int blockSize = pow(2, 4);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float* a = new float[N*N];
float* b = new float[N*N];
float* c = new float[N*N];
float* ad;
float* bd;
float* cd;
const int size = N * N * sizeof(float);
cudaMalloc((void**)&ad, size);
cudaMalloc((void**)&bd, size);
cudaMalloc((void**)&cd, size);
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
a[i+j*N] = 10 + i;
b[i+j*N] = (float)j / N;
}
}
cudaMemcpy(ad, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(bd, b, size, cudaMemcpyHostToDevice);
dim3 dimBlock(blockSize, blockSize);
dim3 dimGrid(N/blockSize, N/blockSize);
cudaEventRecord(start);
add_matrix<<<dimGrid, dimBlock>>>(ad, bd, cd, N);
cudaEventRecord(stop);
cudaThreadSynchronize();
cudaMemcpy(c, cd, size, cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
printf("%0.2f ", c[i+j*N]);
}
printf("\n");
}
printf(
"GPU execution took %f milliseconds for N=%d, Blocks=%dx%d, Grid=%dx%d.\n",
milliseconds, N, dimBlock.x, dimBlock.y, dimGrid.x, dimGrid.y);
// Try to clean up everything on the GPU, and do it twice!
clear_my_bitch_out<<<dimGrid, dimBlock>>>(cd, N);
cudaDeviceReset();
}
} | .file "tmpxft_000cde86_00000000-6_matrix_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " Device name: %s\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string " Memory Clock Rate (KHz): %d\n"
.align 8
.LC2:
.string " Memory Bus Width (bits): %d\n"
.align 8
.LC4:
.string " Peak Memory Bandwidth (GB/s): %f\n\n"
.text
.globl _Z21printDevicePropertiesv
.type _Z21printDevicePropertiesv, @function
_Z21printDevicePropertiesv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $1040, %rsp
.cfi_def_cfa_offset 1056
movq %fs:40, %rax
movq %rax, 1032(%rsp)
xorl %eax, %eax
movq %rsp, %rbx
movl $0, %esi
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %rbx, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 608(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 612(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2sdl 608(%rsp), %xmm0
addsd %xmm0, %xmm0
movl 612(%rsp), %edx
leal 7(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $3, %eax
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
mulsd %xmm1, %xmm0
divsd .LC3(%rip), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $1040, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z21printDevicePropertiesv, .-_Z21printDevicePropertiesv
.globl _Z35__device_stub__Z10add_matrixPfS_S_iPfS_S_i
.type _Z35__device_stub__Z10add_matrixPfS_S_iPfS_S_i, @function
_Z35__device_stub__Z10add_matrixPfS_S_iPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10add_matrixPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z35__device_stub__Z10add_matrixPfS_S_iPfS_S_i, .-_Z35__device_stub__Z10add_matrixPfS_S_iPfS_S_i
.globl _Z10add_matrixPfS_S_i
.type _Z10add_matrixPfS_S_i, @function
_Z10add_matrixPfS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10add_matrixPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z10add_matrixPfS_S_i, .-_Z10add_matrixPfS_S_i
.globl _Z39__device_stub__Z18clear_my_bitch_outPfiPfi
.type _Z39__device_stub__Z18clear_my_bitch_outPfiPfi, @function
_Z39__device_stub__Z18clear_my_bitch_outPfiPfi:
.LFB2086:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z18clear_my_bitch_outPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z39__device_stub__Z18clear_my_bitch_outPfiPfi, .-_Z39__device_stub__Z18clear_my_bitch_outPfiPfi
.globl _Z18clear_my_bitch_outPfi
.type _Z18clear_my_bitch_outPfi, @function
_Z18clear_my_bitch_outPfi:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z18clear_my_bitch_outPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z18clear_my_bitch_outPfi, .-_Z18clear_my_bitch_outPfi
.section .rodata.str1.1
.LC7:
.string "%0.2f "
.LC8:
.string "\n"
.section .rodata.str1.8
.align 8
.LC9:
.string "GPU execution took %f milliseconds for N=%d, Blocks=%dx%d, Grid=%dx%d.\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
call _Z21printDevicePropertiesv
movl $5, 24(%rsp)
leaq .LC7(%rip), %r15
jmp .L34
.L43:
movl %r12d, %ecx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z35__device_stub__Z10add_matrixPfS_S_iPfS_S_i
jmp .L29
.L33:
call cudaDeviceReset@PLT
addl $1, 24(%rsp)
movl 24(%rsp), %eax
cmpl $11, %eax
je .L42
.L34:
movl 24(%rsp), %eax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
movsd .LC5(%rip), %xmm0
call pow@PLT
cvttsd2sil %xmm0, %r12d
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movl %r12d, %r13d
imull %r12d, %r13d
movslq %r13d, %r14
salq $2, %r14
movq %r14, %rdi
call _Znam@PLT
movq %rax, %rbp
movq %r14, %rdi
call _Znam@PLT
movq %rax, %rbx
movq %r14, %rdi
call _Znam@PLT
movq %rax, 8(%rsp)
sall $2, %r13d
movslq %r13d, %r13
leaq 56(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
testl %r12d, %r12d
jle .L26
leal 10(%r12), %edi
movslq %r12d, %rcx
salq $2, %rcx
movl $10, %esi
movl $0, %r8d
pxor %xmm2, %xmm2
cvtsi2ssl %r12d, %xmm2
.L27:
movq %r8, %rdx
movl $0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %esi, %xmm1
.L28:
movss %xmm1, 0(%rbp,%rdx)
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
divss %xmm2, %xmm0
movss %xmm0, (%rbx,%rdx)
addl $1, %eax
addq %rcx, %rdx
cmpl %eax, %r12d
jne .L28
addq $4, %r8
addl $1, %esi
cmpl %edi, %esi
jne .L27
.L26:
movl $1, %ecx
movq %r13, %rdx
movq %rbp, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq %rbx, %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 88(%rsp)
leal 15(%r12), %eax
testl %r12d, %r12d
cmovns %r12d, %eax
sarl $4, %eax
movl %eax, %ebp
movl $1, 100(%rsp)
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl %ebp, 92(%rsp)
movl %ebp, 96(%rsp)
movl $16, 80(%rsp)
movl $16, 84(%rsp)
movl 88(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movq 92(%rsp), %rdi
movl 100(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L43
.L29:
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
call cudaThreadSynchronize@PLT
movl $2, %ecx
movq %r13, %rdx
movq 72(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 36(%rsp)
leaq 36(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
testl %r12d, %r12d
jle .L30
movslq %r12d, %rax
leaq 0(,%rax,4), %r13
movl $0, %r14d
movq %rax, 16(%rsp)
movl %ebp, 28(%rsp)
.L31:
movq 8(%rsp), %rax
leaq (%rax,%r14,4), %rbp
movl $0, %ebx
.L32:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp), %xmm0
movq %r15, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addl $1, %ebx
addq %r13, %rbp
cmpl %ebx, %r12d
jne .L32
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %r14
movq 16(%rsp), %rax
cmpq %rax, %r14
jne .L31
movl 28(%rsp), %ebp
.L30:
pxor %xmm0, %xmm0
cvtss2sd 36(%rsp), %xmm0
subq $8, %rsp
.cfi_def_cfa_offset 184
pushq %rbp
.cfi_def_cfa_offset 192
movl %ebp, %r9d
movl $16, %r8d
movl $16, %ecx
movl %r12d, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
movl 88(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movq 92(%rsp), %rdi
movl 100(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L33
movl %r12d, %esi
movq 72(%rsp), %rdi
call _Z39__device_stub__Z18clear_my_bitch_outPfiPfi
jmp .L33
.L42:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L44
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z18clear_my_bitch_outPfi"
.LC11:
.string "_Z10add_matrixPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z18clear_my_bitch_outPfi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z10add_matrixPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1093567616
.align 8
.LC5:
.long 0
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Matrix addition, CPU version
// gcc matrix_cpu.c -o matrix_cpu -std=c99
#include <stdio.h>
#include <math.h>
void printDeviceProperties(){
cudaDeviceProp prop;
cudaGetDeviceProperties(&prop, 0);
printf(" Device name: %s\n", prop.name);
printf(" Memory Clock Rate (KHz): %d\n",
prop.memoryClockRate);
printf(" Memory Bus Width (bits): %d\n",
prop.memoryBusWidth);
printf(" Peak Memory Bandwidth (GB/s): %f\n\n",
2.0*prop.memoryClockRate*(prop.memoryBusWidth/8)/1.0e6);
}
__global__
void add_matrix(float *a, float *b, float *c, int N) {
int indexX = blockIdx.x * blockDim.x + threadIdx.x;
int indexY = blockIdx.y * blockDim.y + threadIdx.y;
int index = indexY * N + indexX;
c[index] = a[index] + b[index];
}
// https://www.youtube.com/watch?v=fu0gbHnRGYk
__global__
void clear_my_bitch_out(float *c, int N) {
int indexX = blockIdx.x * blockDim.x + threadIdx.x;
int indexY = blockIdx.y * blockDim.y + threadIdx.y;
int index = indexY * N + indexX;
c[index] = 0;
}
int main() {
printDeviceProperties();
for (unsigned int i = 5; i < 11; i++) {
const int N = pow(2, i);
const int blockSize = pow(2, 4);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float* a = new float[N*N];
float* b = new float[N*N];
float* c = new float[N*N];
float* ad;
float* bd;
float* cd;
const int size = N * N * sizeof(float);
cudaMalloc((void**)&ad, size);
cudaMalloc((void**)&bd, size);
cudaMalloc((void**)&cd, size);
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
a[i+j*N] = 10 + i;
b[i+j*N] = (float)j / N;
}
}
cudaMemcpy(ad, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(bd, b, size, cudaMemcpyHostToDevice);
dim3 dimBlock(blockSize, blockSize);
dim3 dimGrid(N/blockSize, N/blockSize);
cudaEventRecord(start);
add_matrix<<<dimGrid, dimBlock>>>(ad, bd, cd, N);
cudaEventRecord(stop);
cudaThreadSynchronize();
cudaMemcpy(c, cd, size, cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
printf("%0.2f ", c[i+j*N]);
}
printf("\n");
}
printf(
"GPU execution took %f milliseconds for N=%d, Blocks=%dx%d, Grid=%dx%d.\n",
milliseconds, N, dimBlock.x, dimBlock.y, dimGrid.x, dimGrid.y);
// Try to clean up everything on the GPU, and do it twice!
clear_my_bitch_out<<<dimGrid, dimBlock>>>(cd, N);
cudaDeviceReset();
}
} | // Matrix addition, CPU version
// gcc matrix_cpu.c -o matrix_cpu -std=c99
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
void printDeviceProperties(){
hipDeviceProp_t prop;
hipGetDeviceProperties(&prop, 0);
printf(" Device name: %s\n", prop.name);
printf(" Memory Clock Rate (KHz): %d\n",
prop.memoryClockRate);
printf(" Memory Bus Width (bits): %d\n",
prop.memoryBusWidth);
printf(" Peak Memory Bandwidth (GB/s): %f\n\n",
2.0*prop.memoryClockRate*(prop.memoryBusWidth/8)/1.0e6);
}
__global__
void add_matrix(float *a, float *b, float *c, int N) {
int indexX = blockIdx.x * blockDim.x + threadIdx.x;
int indexY = blockIdx.y * blockDim.y + threadIdx.y;
int index = indexY * N + indexX;
c[index] = a[index] + b[index];
}
// https://www.youtube.com/watch?v=fu0gbHnRGYk
__global__
void clear_my_bitch_out(float *c, int N) {
int indexX = blockIdx.x * blockDim.x + threadIdx.x;
int indexY = blockIdx.y * blockDim.y + threadIdx.y;
int index = indexY * N + indexX;
c[index] = 0;
}
int main() {
printDeviceProperties();
for (unsigned int i = 5; i < 11; i++) {
const int N = pow(2, i);
const int blockSize = pow(2, 4);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float* a = new float[N*N];
float* b = new float[N*N];
float* c = new float[N*N];
float* ad;
float* bd;
float* cd;
const int size = N * N * sizeof(float);
hipMalloc((void**)&ad, size);
hipMalloc((void**)&bd, size);
hipMalloc((void**)&cd, size);
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
a[i+j*N] = 10 + i;
b[i+j*N] = (float)j / N;
}
}
hipMemcpy(ad, a, size, hipMemcpyHostToDevice);
hipMemcpy(bd, b, size, hipMemcpyHostToDevice);
dim3 dimBlock(blockSize, blockSize);
dim3 dimGrid(N/blockSize, N/blockSize);
hipEventRecord(start);
add_matrix<<<dimGrid, dimBlock>>>(ad, bd, cd, N);
hipEventRecord(stop);
hipDeviceSynchronize();
hipMemcpy(c, cd, size, hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
printf("%0.2f ", c[i+j*N]);
}
printf("\n");
}
printf(
"GPU execution took %f milliseconds for N=%d, Blocks=%dx%d, Grid=%dx%d.\n",
milliseconds, N, dimBlock.x, dimBlock.y, dimGrid.x, dimGrid.y);
// Try to clean up everything on the GPU, and do it twice!
clear_my_bitch_out<<<dimGrid, dimBlock>>>(cd, N);
hipDeviceReset();
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Matrix addition, CPU version
// gcc matrix_cpu.c -o matrix_cpu -std=c99
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
void printDeviceProperties(){
hipDeviceProp_t prop;
hipGetDeviceProperties(&prop, 0);
printf(" Device name: %s\n", prop.name);
printf(" Memory Clock Rate (KHz): %d\n",
prop.memoryClockRate);
printf(" Memory Bus Width (bits): %d\n",
prop.memoryBusWidth);
printf(" Peak Memory Bandwidth (GB/s): %f\n\n",
2.0*prop.memoryClockRate*(prop.memoryBusWidth/8)/1.0e6);
}
__global__
void add_matrix(float *a, float *b, float *c, int N) {
int indexX = blockIdx.x * blockDim.x + threadIdx.x;
int indexY = blockIdx.y * blockDim.y + threadIdx.y;
int index = indexY * N + indexX;
c[index] = a[index] + b[index];
}
// https://www.youtube.com/watch?v=fu0gbHnRGYk
__global__
void clear_my_bitch_out(float *c, int N) {
int indexX = blockIdx.x * blockDim.x + threadIdx.x;
int indexY = blockIdx.y * blockDim.y + threadIdx.y;
int index = indexY * N + indexX;
c[index] = 0;
}
int main() {
printDeviceProperties();
for (unsigned int i = 5; i < 11; i++) {
const int N = pow(2, i);
const int blockSize = pow(2, 4);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float* a = new float[N*N];
float* b = new float[N*N];
float* c = new float[N*N];
float* ad;
float* bd;
float* cd;
const int size = N * N * sizeof(float);
hipMalloc((void**)&ad, size);
hipMalloc((void**)&bd, size);
hipMalloc((void**)&cd, size);
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
a[i+j*N] = 10 + i;
b[i+j*N] = (float)j / N;
}
}
hipMemcpy(ad, a, size, hipMemcpyHostToDevice);
hipMemcpy(bd, b, size, hipMemcpyHostToDevice);
dim3 dimBlock(blockSize, blockSize);
dim3 dimGrid(N/blockSize, N/blockSize);
hipEventRecord(start);
add_matrix<<<dimGrid, dimBlock>>>(ad, bd, cd, N);
hipEventRecord(stop);
hipDeviceSynchronize();
hipMemcpy(c, cd, size, hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
printf("%0.2f ", c[i+j*N]);
}
printf("\n");
}
printf(
"GPU execution took %f milliseconds for N=%d, Blocks=%dx%d, Grid=%dx%d.\n",
milliseconds, N, dimBlock.x, dimBlock.y, dimGrid.x, dimGrid.y);
// Try to clean up everything on the GPU, and do it twice!
clear_my_bitch_out<<<dimGrid, dimBlock>>>(cd, N);
hipDeviceReset();
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10add_matrixPfS_S_i
.globl _Z10add_matrixPfS_S_i
.p2align 8
.type _Z10add_matrixPfS_S_i,@function
_Z10add_matrixPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_load_b128 s[4:7], s[0:1], 0x0
s_mul_i32 s14, s14, s2
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v2, s3
v_add3_u32 v0, s14, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10add_matrixPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10add_matrixPfS_S_i, .Lfunc_end0-_Z10add_matrixPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z18clear_my_bitch_outPfi
.globl _Z18clear_my_bitch_outPfi
.p2align 8
.type _Z18clear_my_bitch_outPfi,@function
_Z18clear_my_bitch_outPfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_mul_i32 s14, s14, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v1, v2, s3
v_mov_b32_e32 v2, 0
v_add3_u32 v0, s14, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18clear_my_bitch_outPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z18clear_my_bitch_outPfi, .Lfunc_end1-_Z18clear_my_bitch_outPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10add_matrixPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10add_matrixPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18clear_my_bitch_outPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18clear_my_bitch_outPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Matrix addition, CPU version
// gcc matrix_cpu.c -o matrix_cpu -std=c99
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
void printDeviceProperties(){
hipDeviceProp_t prop;
hipGetDeviceProperties(&prop, 0);
printf(" Device name: %s\n", prop.name);
printf(" Memory Clock Rate (KHz): %d\n",
prop.memoryClockRate);
printf(" Memory Bus Width (bits): %d\n",
prop.memoryBusWidth);
printf(" Peak Memory Bandwidth (GB/s): %f\n\n",
2.0*prop.memoryClockRate*(prop.memoryBusWidth/8)/1.0e6);
}
__global__
void add_matrix(float *a, float *b, float *c, int N) {
int indexX = blockIdx.x * blockDim.x + threadIdx.x;
int indexY = blockIdx.y * blockDim.y + threadIdx.y;
int index = indexY * N + indexX;
c[index] = a[index] + b[index];
}
// https://www.youtube.com/watch?v=fu0gbHnRGYk
__global__
void clear_my_bitch_out(float *c, int N) {
int indexX = blockIdx.x * blockDim.x + threadIdx.x;
int indexY = blockIdx.y * blockDim.y + threadIdx.y;
int index = indexY * N + indexX;
c[index] = 0;
}
int main() {
printDeviceProperties();
for (unsigned int i = 5; i < 11; i++) {
const int N = pow(2, i);
const int blockSize = pow(2, 4);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float* a = new float[N*N];
float* b = new float[N*N];
float* c = new float[N*N];
float* ad;
float* bd;
float* cd;
const int size = N * N * sizeof(float);
hipMalloc((void**)&ad, size);
hipMalloc((void**)&bd, size);
hipMalloc((void**)&cd, size);
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
a[i+j*N] = 10 + i;
b[i+j*N] = (float)j / N;
}
}
hipMemcpy(ad, a, size, hipMemcpyHostToDevice);
hipMemcpy(bd, b, size, hipMemcpyHostToDevice);
dim3 dimBlock(blockSize, blockSize);
dim3 dimGrid(N/blockSize, N/blockSize);
hipEventRecord(start);
add_matrix<<<dimGrid, dimBlock>>>(ad, bd, cd, N);
hipEventRecord(stop);
hipDeviceSynchronize();
hipMemcpy(c, cd, size, hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
printf("%0.2f ", c[i+j*N]);
}
printf("\n");
}
printf(
"GPU execution took %f milliseconds for N=%d, Blocks=%dx%d, Grid=%dx%d.\n",
milliseconds, N, dimBlock.x, dimBlock.y, dimGrid.x, dimGrid.y);
// Try to clean up everything on the GPU, and do it twice!
clear_my_bitch_out<<<dimGrid, dimBlock>>>(cd, N);
hipDeviceReset();
}
} | .text
.file "matrix_gpu.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z21printDevicePropertiesv
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z21printDevicePropertiesv
.p2align 4, 0x90
.type _Z21printDevicePropertiesv,@function
_Z21printDevicePropertiesv: # @_Z21printDevicePropertiesv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1472, %rsp # imm = 0x5C0
.cfi_def_cfa_offset 1488
.cfi_offset %rbx, -16
movq %rsp, %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl 608(%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl 612(%rsp), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
cvtsi2sdl 608(%rsp), %xmm1
movl 612(%rsp), %eax
leal 7(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $3, %ecx
cvtsi2sd %ecx, %xmm0
addsd %xmm1, %xmm1
mulsd %xmm1, %xmm0
divsd .LCPI0_0(%rip), %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
addq $1472, %rsp # imm = 0x5C0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z21printDevicePropertiesv, .Lfunc_end0-_Z21printDevicePropertiesv
.cfi_endproc
# -- End function
.globl _Z25__device_stub__add_matrixPfS_S_i # -- Begin function _Z25__device_stub__add_matrixPfS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__add_matrixPfS_S_i,@function
_Z25__device_stub__add_matrixPfS_S_i: # @_Z25__device_stub__add_matrixPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10add_matrixPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z25__device_stub__add_matrixPfS_S_i, .Lfunc_end1-_Z25__device_stub__add_matrixPfS_S_i
.cfi_endproc
# -- End function
.globl _Z33__device_stub__clear_my_bitch_outPfi # -- Begin function _Z33__device_stub__clear_my_bitch_outPfi
.p2align 4, 0x90
.type _Z33__device_stub__clear_my_bitch_outPfi,@function
_Z33__device_stub__clear_my_bitch_outPfi: # @_Z33__device_stub__clear_my_bitch_outPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z18clear_my_bitch_outPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z33__device_stub__clear_my_bitch_outPfi, .Lfunc_end2-_Z33__device_stub__clear_my_bitch_outPfi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI3_1:
.quad 0x4014000000000000 # double 5
.LCPI3_2:
.quad 0x3ff0000000000000 # double 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1640, %rsp # imm = 0x668
.cfi_def_cfa_offset 1696
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 160(%rsp), %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl 768(%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl 772(%rsp), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
cvtsi2sdl 768(%rsp), %xmm1
movl 772(%rsp), %eax
leal 7(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $3, %ecx
cvtsi2sd %ecx, %xmm0
addsd %xmm1, %xmm1
mulsd %xmm1, %xmm0
divsd .LCPI3_0(%rip), %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movl $5, %ebx
movsd .LCPI3_1(%rip), %xmm0 # xmm0 = mem[0],zero
jmp .LBB3_1
.p2align 4, 0x90
.LBB3_15: # in Loop: Header=BB3_1 Depth=1
callq hipDeviceReset
movsd 152(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addsd .LCPI3_2(%rip), %xmm0
incl %ebx
cmpl $11, %ebx
je .LBB3_16
.LBB3_1: # =>This Loop Header: Depth=1
# Child Loop BB3_3 Depth 2
# Child Loop BB3_4 Depth 3
# Child Loop BB3_10 Depth 2
# Child Loop BB3_11 Depth 3
movl %ebx, 96(%rsp) # 4-byte Spill
movsd %xmm0, 152(%rsp) # 8-byte Spill
callq exp2@PLT
cvttsd2si %xmm0, %r14d
leaq 120(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movl %r14d, %r15d
imull %r15d, %r15d
leaq (,%r15,4), %r13
movq %r13, %rdi
callq _Znam
movq %rax, %rbx
movq %r13, %rdi
callq _Znam
movq %rax, %r12
movq %r13, %rdi
movq %r14, %r13
callq _Znam
movq %rax, %r14
shll $2, %r15d
movslq %r15d, %rbp
leaq 112(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 104(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movl %r13d, %r15d
testl %r13d, %r13d
jle .LBB3_6
# %bb.2: # %.preheader90.lr.ph
# in Loop: Header=BB3_1 Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %r13d, %xmm0
leaq (,%r15,4), %rax
movq %rbx, %rcx
movq %r12, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB3_3: # %.preheader90
# Parent Loop BB3_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_4 Depth 3
leal 10(%rsi), %edi
xorps %xmm1, %xmm1
cvtsi2ss %edi, %xmm1
xorl %edi, %edi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB3_4: # Parent Loop BB3_1 Depth=1
# Parent Loop BB3_3 Depth=2
# => This Inner Loop Header: Depth=3
movss %xmm1, (%rcx,%rdi)
xorps %xmm2, %xmm2
cvtsi2ss %r8d, %xmm2
divss %xmm0, %xmm2
movss %xmm2, (%rdx,%rdi)
incq %r8
addq %rax, %rdi
cmpq %r8, %r15
jne .LBB3_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB3_3 Depth=2
incq %rsi
addq $4, %rdx
addq $4, %rcx
cmpq %r15, %rsi
jne .LBB3_3
.LBB3_6: # %._crit_edge93
# in Loop: Header=BB3_1 Depth=1
movq 112(%rsp), %rdi
movq %rbx, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 104(%rsp), %rdi
movq %r12, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
leal 15(%r13), %eax
testl %r13d, %r13d
cmovnsl %r13d, %eax
sarl $4, %eax
movq %rax, %rbx
shlq $32, %rbx
movq %rax, 136(%rsp) # 8-byte Spill
orq %rax, %rbx
movq 120(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %rbx, 128(%rsp) # 8-byte Spill
movq %rbx, %rdi
movl $1, %esi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_8
# %bb.7: # in Loop: Header=BB3_1 Depth=1
movq 112(%rsp), %rax
movq 104(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 48(%rsp)
movq %rdx, 40(%rsp)
movl %r13d, 100(%rsp)
leaq 88(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 100(%rsp), %rax
movq %rax, 184(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z10add_matrixPfS_S_i, %edi
leaq 160(%rsp), %r9
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_8: # in Loop: Header=BB3_1 Depth=1
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
callq hipDeviceSynchronize
movq 16(%rsp), %rsi
movq %r14, %rdi
movq %rbp, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipEventSynchronize
movl $0, 8(%rsp)
movq 120(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 8(%rsp), %rdi
callq hipEventElapsedTime
movq %r13, 144(%rsp) # 8-byte Spill
testl %r13d, %r13d
jle .LBB3_13
# %bb.9: # %.preheader.preheader
# in Loop: Header=BB3_1 Depth=1
leaq (,%r15,4), %rbp
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_10: # %.preheader
# Parent Loop BB3_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_11 Depth 3
movq %r15, %rbx
movq %r14, %r13
.p2align 4, 0x90
.LBB3_11: # Parent Loop BB3_1 Depth=1
# Parent Loop BB3_10 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r13), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
addq %rbp, %r13
decq %rbx
jne .LBB3_11
# %bb.12: # %._crit_edge96
# in Loop: Header=BB3_10 Depth=2
movl $10, %edi
callq putchar@PLT
incq %r12
addq $4, %r14
cmpq %r15, %r12
jne .LBB3_10
.LBB3_13: # %._crit_edge98
# in Loop: Header=BB3_1 Depth=1
movss 8(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movq 144(%rsp), %r14 # 8-byte Reload
movl %r14d, %esi
movl $16, %edx
movl $16, %ecx
movq 136(%rsp), %r8 # 8-byte Reload
movl %r8d, %r9d
movb $1, %al
callq printf
movq 128(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
movl 96(%rsp), %ebx # 4-byte Reload
jne .LBB3_15
# %bb.14: # in Loop: Header=BB3_1 Depth=1
movq 16(%rsp), %rax
movq %rax, 88(%rsp)
movl %r14d, 32(%rsp)
leaq 88(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z18clear_my_bitch_outPfi, %edi
leaq 160(%rsp), %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_15
.LBB3_16:
xorl %eax, %eax
addq $1640, %rsp # imm = 0x668
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10add_matrixPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18clear_my_bitch_outPfi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " Device name: %s\n"
.size .L.str, 19
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " Memory Clock Rate (KHz): %d\n"
.size .L.str.1, 31
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " Memory Bus Width (bits): %d\n"
.size .L.str.2, 31
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " Peak Memory Bandwidth (GB/s): %f\n\n"
.size .L.str.3, 37
.type _Z10add_matrixPfS_S_i,@object # @_Z10add_matrixPfS_S_i
.section .rodata,"a",@progbits
.globl _Z10add_matrixPfS_S_i
.p2align 3, 0x0
_Z10add_matrixPfS_S_i:
.quad _Z25__device_stub__add_matrixPfS_S_i
.size _Z10add_matrixPfS_S_i, 8
.type _Z18clear_my_bitch_outPfi,@object # @_Z18clear_my_bitch_outPfi
.globl _Z18clear_my_bitch_outPfi
.p2align 3, 0x0
_Z18clear_my_bitch_outPfi:
.quad _Z33__device_stub__clear_my_bitch_outPfi
.size _Z18clear_my_bitch_outPfi, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "%0.2f "
.size .L.str.4, 7
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "GPU execution took %f milliseconds for N=%d, Blocks=%dx%d, Grid=%dx%d.\n"
.size .L.str.6, 72
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10add_matrixPfS_S_i"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z18clear_my_bitch_outPfi"
.size .L__unnamed_2, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__add_matrixPfS_S_i
.addrsig_sym _Z33__device_stub__clear_my_bitch_outPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10add_matrixPfS_S_i
.addrsig_sym _Z18clear_my_bitch_outPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z18clear_my_bitch_outPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0040*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*0070*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fe200078e0205 */
/*0080*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fc600000001ff */
/*0090*/ IMAD R3, R3, c[0x0][0x168], R0 ; /* 0x00005a0003037a24 */
/* 0x000fce00078e0200 */
/*00a0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0202 */
/*00b0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10add_matrixPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0050*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0060*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc400078e0203 */
/*0080*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fc800078e0205 */
/*0090*/ IMAD R0, R3, c[0x0][0x178], R0 ; /* 0x00005e0003007a24 */
/* 0x000fc800078e0200 */
/*00a0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0207 */
/*00b0*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0207 */
/*00c0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0207 */
/*00f0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*0100*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10add_matrixPfS_S_i
.globl _Z10add_matrixPfS_S_i
.p2align 8
.type _Z10add_matrixPfS_S_i,@function
_Z10add_matrixPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_load_b128 s[4:7], s[0:1], 0x0
s_mul_i32 s14, s14, s2
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v2, s3
v_add3_u32 v0, s14, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10add_matrixPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10add_matrixPfS_S_i, .Lfunc_end0-_Z10add_matrixPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z18clear_my_bitch_outPfi
.globl _Z18clear_my_bitch_outPfi
.p2align 8
.type _Z18clear_my_bitch_outPfi,@function
_Z18clear_my_bitch_outPfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_mul_i32 s14, s14, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v1, v2, s3
v_mov_b32_e32 v2, 0
v_add3_u32 v0, s14, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18clear_my_bitch_outPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z18clear_my_bitch_outPfi, .Lfunc_end1-_Z18clear_my_bitch_outPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10add_matrixPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10add_matrixPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18clear_my_bitch_outPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18clear_my_bitch_outPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000cde86_00000000-6_matrix_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " Device name: %s\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string " Memory Clock Rate (KHz): %d\n"
.align 8
.LC2:
.string " Memory Bus Width (bits): %d\n"
.align 8
.LC4:
.string " Peak Memory Bandwidth (GB/s): %f\n\n"
.text
.globl _Z21printDevicePropertiesv
.type _Z21printDevicePropertiesv, @function
_Z21printDevicePropertiesv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $1040, %rsp
.cfi_def_cfa_offset 1056
movq %fs:40, %rax
movq %rax, 1032(%rsp)
xorl %eax, %eax
movq %rsp, %rbx
movl $0, %esi
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %rbx, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 608(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 612(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2sdl 608(%rsp), %xmm0
addsd %xmm0, %xmm0
movl 612(%rsp), %edx
leal 7(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $3, %eax
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
mulsd %xmm1, %xmm0
divsd .LC3(%rip), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $1040, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z21printDevicePropertiesv, .-_Z21printDevicePropertiesv
.globl _Z35__device_stub__Z10add_matrixPfS_S_iPfS_S_i
.type _Z35__device_stub__Z10add_matrixPfS_S_iPfS_S_i, @function
_Z35__device_stub__Z10add_matrixPfS_S_iPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10add_matrixPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z35__device_stub__Z10add_matrixPfS_S_iPfS_S_i, .-_Z35__device_stub__Z10add_matrixPfS_S_iPfS_S_i
.globl _Z10add_matrixPfS_S_i
.type _Z10add_matrixPfS_S_i, @function
_Z10add_matrixPfS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10add_matrixPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z10add_matrixPfS_S_i, .-_Z10add_matrixPfS_S_i
.globl _Z39__device_stub__Z18clear_my_bitch_outPfiPfi
.type _Z39__device_stub__Z18clear_my_bitch_outPfiPfi, @function
_Z39__device_stub__Z18clear_my_bitch_outPfiPfi:
.LFB2086:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z18clear_my_bitch_outPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z39__device_stub__Z18clear_my_bitch_outPfiPfi, .-_Z39__device_stub__Z18clear_my_bitch_outPfiPfi
.globl _Z18clear_my_bitch_outPfi
.type _Z18clear_my_bitch_outPfi, @function
_Z18clear_my_bitch_outPfi:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z18clear_my_bitch_outPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z18clear_my_bitch_outPfi, .-_Z18clear_my_bitch_outPfi
.section .rodata.str1.1
.LC7:
.string "%0.2f "
.LC8:
.string "\n"
.section .rodata.str1.8
.align 8
.LC9:
.string "GPU execution took %f milliseconds for N=%d, Blocks=%dx%d, Grid=%dx%d.\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
call _Z21printDevicePropertiesv
movl $5, 24(%rsp)
leaq .LC7(%rip), %r15
jmp .L34
.L43:
movl %r12d, %ecx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z35__device_stub__Z10add_matrixPfS_S_iPfS_S_i
jmp .L29
.L33:
call cudaDeviceReset@PLT
addl $1, 24(%rsp)
movl 24(%rsp), %eax
cmpl $11, %eax
je .L42
.L34:
movl 24(%rsp), %eax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
movsd .LC5(%rip), %xmm0
call pow@PLT
cvttsd2sil %xmm0, %r12d
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movl %r12d, %r13d
imull %r12d, %r13d
movslq %r13d, %r14
salq $2, %r14
movq %r14, %rdi
call _Znam@PLT
movq %rax, %rbp
movq %r14, %rdi
call _Znam@PLT
movq %rax, %rbx
movq %r14, %rdi
call _Znam@PLT
movq %rax, 8(%rsp)
sall $2, %r13d
movslq %r13d, %r13
leaq 56(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
testl %r12d, %r12d
jle .L26
leal 10(%r12), %edi
movslq %r12d, %rcx
salq $2, %rcx
movl $10, %esi
movl $0, %r8d
pxor %xmm2, %xmm2
cvtsi2ssl %r12d, %xmm2
.L27:
movq %r8, %rdx
movl $0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %esi, %xmm1
.L28:
movss %xmm1, 0(%rbp,%rdx)
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
divss %xmm2, %xmm0
movss %xmm0, (%rbx,%rdx)
addl $1, %eax
addq %rcx, %rdx
cmpl %eax, %r12d
jne .L28
addq $4, %r8
addl $1, %esi
cmpl %edi, %esi
jne .L27
.L26:
movl $1, %ecx
movq %r13, %rdx
movq %rbp, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq %rbx, %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 88(%rsp)
leal 15(%r12), %eax
testl %r12d, %r12d
cmovns %r12d, %eax
sarl $4, %eax
movl %eax, %ebp
movl $1, 100(%rsp)
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl %ebp, 92(%rsp)
movl %ebp, 96(%rsp)
movl $16, 80(%rsp)
movl $16, 84(%rsp)
movl 88(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movq 92(%rsp), %rdi
movl 100(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L43
.L29:
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
call cudaThreadSynchronize@PLT
movl $2, %ecx
movq %r13, %rdx
movq 72(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 36(%rsp)
leaq 36(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
testl %r12d, %r12d
jle .L30
movslq %r12d, %rax
leaq 0(,%rax,4), %r13
movl $0, %r14d
movq %rax, 16(%rsp)
movl %ebp, 28(%rsp)
.L31:
movq 8(%rsp), %rax
leaq (%rax,%r14,4), %rbp
movl $0, %ebx
.L32:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp), %xmm0
movq %r15, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addl $1, %ebx
addq %r13, %rbp
cmpl %ebx, %r12d
jne .L32
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %r14
movq 16(%rsp), %rax
cmpq %rax, %r14
jne .L31
movl 28(%rsp), %ebp
.L30:
pxor %xmm0, %xmm0
cvtss2sd 36(%rsp), %xmm0
subq $8, %rsp
.cfi_def_cfa_offset 184
pushq %rbp
.cfi_def_cfa_offset 192
movl %ebp, %r9d
movl $16, %r8d
movl $16, %ecx
movl %r12d, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
movl 88(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movq 92(%rsp), %rdi
movl 100(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L33
movl %r12d, %esi
movq 72(%rsp), %rdi
call _Z39__device_stub__Z18clear_my_bitch_outPfiPfi
jmp .L33
.L42:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L44
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z18clear_my_bitch_outPfi"
.LC11:
.string "_Z10add_matrixPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z18clear_my_bitch_outPfi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z10add_matrixPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1093567616
.align 8
.LC5:
.long 0
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrix_gpu.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z21printDevicePropertiesv
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z21printDevicePropertiesv
.p2align 4, 0x90
.type _Z21printDevicePropertiesv,@function
_Z21printDevicePropertiesv: # @_Z21printDevicePropertiesv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1472, %rsp # imm = 0x5C0
.cfi_def_cfa_offset 1488
.cfi_offset %rbx, -16
movq %rsp, %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl 608(%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl 612(%rsp), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
cvtsi2sdl 608(%rsp), %xmm1
movl 612(%rsp), %eax
leal 7(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $3, %ecx
cvtsi2sd %ecx, %xmm0
addsd %xmm1, %xmm1
mulsd %xmm1, %xmm0
divsd .LCPI0_0(%rip), %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
addq $1472, %rsp # imm = 0x5C0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z21printDevicePropertiesv, .Lfunc_end0-_Z21printDevicePropertiesv
.cfi_endproc
# -- End function
.globl _Z25__device_stub__add_matrixPfS_S_i # -- Begin function _Z25__device_stub__add_matrixPfS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__add_matrixPfS_S_i,@function
_Z25__device_stub__add_matrixPfS_S_i: # @_Z25__device_stub__add_matrixPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10add_matrixPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z25__device_stub__add_matrixPfS_S_i, .Lfunc_end1-_Z25__device_stub__add_matrixPfS_S_i
.cfi_endproc
# -- End function
.globl _Z33__device_stub__clear_my_bitch_outPfi # -- Begin function _Z33__device_stub__clear_my_bitch_outPfi
.p2align 4, 0x90
.type _Z33__device_stub__clear_my_bitch_outPfi,@function
_Z33__device_stub__clear_my_bitch_outPfi: # @_Z33__device_stub__clear_my_bitch_outPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z18clear_my_bitch_outPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z33__device_stub__clear_my_bitch_outPfi, .Lfunc_end2-_Z33__device_stub__clear_my_bitch_outPfi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI3_1:
.quad 0x4014000000000000 # double 5
.LCPI3_2:
.quad 0x3ff0000000000000 # double 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1640, %rsp # imm = 0x668
.cfi_def_cfa_offset 1696
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 160(%rsp), %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl 768(%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl 772(%rsp), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
cvtsi2sdl 768(%rsp), %xmm1
movl 772(%rsp), %eax
leal 7(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $3, %ecx
cvtsi2sd %ecx, %xmm0
addsd %xmm1, %xmm1
mulsd %xmm1, %xmm0
divsd .LCPI3_0(%rip), %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movl $5, %ebx
movsd .LCPI3_1(%rip), %xmm0 # xmm0 = mem[0],zero
jmp .LBB3_1
.p2align 4, 0x90
.LBB3_15: # in Loop: Header=BB3_1 Depth=1
callq hipDeviceReset
movsd 152(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addsd .LCPI3_2(%rip), %xmm0
incl %ebx
cmpl $11, %ebx
je .LBB3_16
.LBB3_1: # =>This Loop Header: Depth=1
# Child Loop BB3_3 Depth 2
# Child Loop BB3_4 Depth 3
# Child Loop BB3_10 Depth 2
# Child Loop BB3_11 Depth 3
movl %ebx, 96(%rsp) # 4-byte Spill
movsd %xmm0, 152(%rsp) # 8-byte Spill
callq exp2@PLT
cvttsd2si %xmm0, %r14d
leaq 120(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movl %r14d, %r15d
imull %r15d, %r15d
leaq (,%r15,4), %r13
movq %r13, %rdi
callq _Znam
movq %rax, %rbx
movq %r13, %rdi
callq _Znam
movq %rax, %r12
movq %r13, %rdi
movq %r14, %r13
callq _Znam
movq %rax, %r14
shll $2, %r15d
movslq %r15d, %rbp
leaq 112(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 104(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movl %r13d, %r15d
testl %r13d, %r13d
jle .LBB3_6
# %bb.2: # %.preheader90.lr.ph
# in Loop: Header=BB3_1 Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %r13d, %xmm0
leaq (,%r15,4), %rax
movq %rbx, %rcx
movq %r12, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB3_3: # %.preheader90
# Parent Loop BB3_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_4 Depth 3
leal 10(%rsi), %edi
xorps %xmm1, %xmm1
cvtsi2ss %edi, %xmm1
xorl %edi, %edi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB3_4: # Parent Loop BB3_1 Depth=1
# Parent Loop BB3_3 Depth=2
# => This Inner Loop Header: Depth=3
movss %xmm1, (%rcx,%rdi)
xorps %xmm2, %xmm2
cvtsi2ss %r8d, %xmm2
divss %xmm0, %xmm2
movss %xmm2, (%rdx,%rdi)
incq %r8
addq %rax, %rdi
cmpq %r8, %r15
jne .LBB3_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB3_3 Depth=2
incq %rsi
addq $4, %rdx
addq $4, %rcx
cmpq %r15, %rsi
jne .LBB3_3
.LBB3_6: # %._crit_edge93
# in Loop: Header=BB3_1 Depth=1
movq 112(%rsp), %rdi
movq %rbx, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 104(%rsp), %rdi
movq %r12, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
leal 15(%r13), %eax
testl %r13d, %r13d
cmovnsl %r13d, %eax
sarl $4, %eax
movq %rax, %rbx
shlq $32, %rbx
movq %rax, 136(%rsp) # 8-byte Spill
orq %rax, %rbx
movq 120(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %rbx, 128(%rsp) # 8-byte Spill
movq %rbx, %rdi
movl $1, %esi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_8
# %bb.7: # in Loop: Header=BB3_1 Depth=1
movq 112(%rsp), %rax
movq 104(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 48(%rsp)
movq %rdx, 40(%rsp)
movl %r13d, 100(%rsp)
leaq 88(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 100(%rsp), %rax
movq %rax, 184(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z10add_matrixPfS_S_i, %edi
leaq 160(%rsp), %r9
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_8: # in Loop: Header=BB3_1 Depth=1
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
callq hipDeviceSynchronize
movq 16(%rsp), %rsi
movq %r14, %rdi
movq %rbp, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipEventSynchronize
movl $0, 8(%rsp)
movq 120(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 8(%rsp), %rdi
callq hipEventElapsedTime
movq %r13, 144(%rsp) # 8-byte Spill
testl %r13d, %r13d
jle .LBB3_13
# %bb.9: # %.preheader.preheader
# in Loop: Header=BB3_1 Depth=1
leaq (,%r15,4), %rbp
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_10: # %.preheader
# Parent Loop BB3_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_11 Depth 3
movq %r15, %rbx
movq %r14, %r13
.p2align 4, 0x90
.LBB3_11: # Parent Loop BB3_1 Depth=1
# Parent Loop BB3_10 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r13), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
addq %rbp, %r13
decq %rbx
jne .LBB3_11
# %bb.12: # %._crit_edge96
# in Loop: Header=BB3_10 Depth=2
movl $10, %edi
callq putchar@PLT
incq %r12
addq $4, %r14
cmpq %r15, %r12
jne .LBB3_10
.LBB3_13: # %._crit_edge98
# in Loop: Header=BB3_1 Depth=1
movss 8(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movq 144(%rsp), %r14 # 8-byte Reload
movl %r14d, %esi
movl $16, %edx
movl $16, %ecx
movq 136(%rsp), %r8 # 8-byte Reload
movl %r8d, %r9d
movb $1, %al
callq printf
movq 128(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
movl 96(%rsp), %ebx # 4-byte Reload
jne .LBB3_15
# %bb.14: # in Loop: Header=BB3_1 Depth=1
movq 16(%rsp), %rax
movq %rax, 88(%rsp)
movl %r14d, 32(%rsp)
leaq 88(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z18clear_my_bitch_outPfi, %edi
leaq 160(%rsp), %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_15
.LBB3_16:
xorl %eax, %eax
addq $1640, %rsp # imm = 0x668
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10add_matrixPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18clear_my_bitch_outPfi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " Device name: %s\n"
.size .L.str, 19
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " Memory Clock Rate (KHz): %d\n"
.size .L.str.1, 31
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " Memory Bus Width (bits): %d\n"
.size .L.str.2, 31
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " Peak Memory Bandwidth (GB/s): %f\n\n"
.size .L.str.3, 37
.type _Z10add_matrixPfS_S_i,@object # @_Z10add_matrixPfS_S_i
.section .rodata,"a",@progbits
.globl _Z10add_matrixPfS_S_i
.p2align 3, 0x0
_Z10add_matrixPfS_S_i:
.quad _Z25__device_stub__add_matrixPfS_S_i
.size _Z10add_matrixPfS_S_i, 8
.type _Z18clear_my_bitch_outPfi,@object # @_Z18clear_my_bitch_outPfi
.globl _Z18clear_my_bitch_outPfi
.p2align 3, 0x0
_Z18clear_my_bitch_outPfi:
.quad _Z33__device_stub__clear_my_bitch_outPfi
.size _Z18clear_my_bitch_outPfi, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "%0.2f "
.size .L.str.4, 7
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "GPU execution took %f milliseconds for N=%d, Blocks=%dx%d, Grid=%dx%d.\n"
.size .L.str.6, 72
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10add_matrixPfS_S_i"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z18clear_my_bitch_outPfi"
.size .L__unnamed_2, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__add_matrixPfS_S_i
.addrsig_sym _Z33__device_stub__clear_my_bitch_outPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10add_matrixPfS_S_i
.addrsig_sym _Z18clear_my_bitch_outPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <cuda.h>
#include <iostream>
#include <time.h> /* time */
using namespace std;
__global__
void vecAddKernel(float* A, float* B, float* C, int n)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
if(i<n) C[i] = A[i] + B[i];
}
void print_vec(float* vector, int size)
{
for(int i=0; i<size; i++)
cout << vector[i] << " ";
cout<<endl;
}
void vecAdd(float* A, float* B, float* C, int n)
{
int size = (n * sizeof(float)) * 2;
A = (float*)malloc(size);
C = (float*)malloc(size);
B = (float*)malloc(size);
srand (time(NULL));
for( int i = 0; i < n; i++ )
{
A[i] = rand() % n + 1;;
B[i] = rand() % n + 1;;
}
float *d_A, *d_B, *d_C;
cudaMalloc((void**)&d_A, size);
cudaMemcpy(d_A, A, size, cudaMemcpyHostToDevice);
cudaMalloc((void**)&d_B, size);
cudaMemcpy(d_B, B, size, cudaMemcpyHostToDevice);
cudaMalloc((void**)&d_C, size);
vecAddKernel<<<ceil((float)n/256.0), 256>>>(d_A, d_B, d_C, n);
cudaMemcpy(C, d_C, size, cudaMemcpyDeviceToHost);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
print_vec(C, size);
}
int main()
{
// Size of vectors
int n = 50;
// Host input vectors
float* h_a;
float* h_b;
float* h_c;
vecAdd(h_a, h_b, h_c, n);
return 0;
} | code for sm_80
Function : _Z12vecAddKernelPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <cuda.h>
#include <iostream>
#include <time.h> /* time */
using namespace std;
__global__
void vecAddKernel(float* A, float* B, float* C, int n)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
if(i<n) C[i] = A[i] + B[i];
}
void print_vec(float* vector, int size)
{
for(int i=0; i<size; i++)
cout << vector[i] << " ";
cout<<endl;
}
void vecAdd(float* A, float* B, float* C, int n)
{
int size = (n * sizeof(float)) * 2;
A = (float*)malloc(size);
C = (float*)malloc(size);
B = (float*)malloc(size);
srand (time(NULL));
for( int i = 0; i < n; i++ )
{
A[i] = rand() % n + 1;;
B[i] = rand() % n + 1;;
}
float *d_A, *d_B, *d_C;
cudaMalloc((void**)&d_A, size);
cudaMemcpy(d_A, A, size, cudaMemcpyHostToDevice);
cudaMalloc((void**)&d_B, size);
cudaMemcpy(d_B, B, size, cudaMemcpyHostToDevice);
cudaMalloc((void**)&d_C, size);
vecAddKernel<<<ceil((float)n/256.0), 256>>>(d_A, d_B, d_C, n);
cudaMemcpy(C, d_C, size, cudaMemcpyDeviceToHost);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
print_vec(C, size);
}
int main()
{
// Size of vectors
int n = 50;
// Host input vectors
float* h_a;
float* h_b;
float* h_c;
vecAdd(h_a, h_b, h_c, n);
return 0;
} | .file "tmpxft_0014391b_00000000-6_one.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " "
.text
.globl _Z9print_vecPfi
.type _Z9print_vecPfi, @function
_Z9print_vecPfi:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
testl %esi, %esi
jle .L4
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %r13
leaq _ZSt4cout(%rip), %r12
leaq .LC0(%rip), %rbp
.L5:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %rbp, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbx, %r13
jne .L5
.L4:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %rbx
testq %rbx, %rbx
je .L11
cmpb $0, 56(%rbx)
je .L7
movzbl 67(%rbx), %esi
.L8:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L7:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L8
.cfi_endproc
.LFE3669:
.size _Z9print_vecPfi, .-_Z9print_vecPfi
.globl _Z37__device_stub__Z12vecAddKernelPfS_S_iPfS_S_i
.type _Z37__device_stub__Z12vecAddKernelPfS_S_iPfS_S_i, @function
_Z37__device_stub__Z12vecAddKernelPfS_S_iPfS_S_i:
.LFB3696:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12vecAddKernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z37__device_stub__Z12vecAddKernelPfS_S_iPfS_S_i, .-_Z37__device_stub__Z12vecAddKernelPfS_S_iPfS_S_i
.globl _Z12vecAddKernelPfS_S_i
.type _Z12vecAddKernelPfS_S_i, @function
_Z12vecAddKernelPfS_S_i:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12vecAddKernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z12vecAddKernelPfS_S_i, .-_Z12vecAddKernelPfS_S_i
.globl _Z6vecAddPfS_S_i
.type _Z6vecAddPfS_S_i, @function
_Z6vecAddPfS_S_i:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movslq %ecx, %r14
leal 0(,%rcx,8), %eax
movl %eax, 4(%rsp)
movslq %eax, %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, %r13
movq %r15, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movq %r15, %rdi
call malloc@PLT
movq %rax, %r12
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
testl %ebp, %ebp
jle .L21
salq $2, %r14
movl $0, %ebx
.L22:
call rand@PLT
cltd
idivl %ebp
addl $1, %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, 0(%r13,%rbx)
call rand@PLT
cltd
idivl %ebp
addl $1, %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, (%r12,%rbx)
addq $4, %rbx
cmpq %r14, %rbx
jne .L22
.L21:
leaq 24(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r15, %rdx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 32(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r15, %rdx
movq %r12, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
leaq 40(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl %ebp, %xmm0
cvtss2sd %xmm0, %xmm0
mulsd .LC1(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC5(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC2(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L23
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC4(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L23:
cvttsd2siq %xmm3, %rax
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L24:
movl $2, %ecx
movq %r15, %rdx
movq 40(%rsp), %rsi
movq 8(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movl 4(%rsp), %esi
movq %rbx, %rdi
call _Z9print_vecPfi
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L29
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movl %ebp, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z37__device_stub__Z12vecAddKernelPfS_S_iPfS_S_i
jmp .L24
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size _Z6vecAddPfS_S_i, .-_Z6vecAddPfS_S_i
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $50, %ecx
movl $0, %edx
movl $0, %esi
movl $0, %edi
call _Z6vecAddPfS_S_i
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3671:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z12vecAddKernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z12vecAddKernelPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1064304640
.align 8
.LC2:
.long 0
.long 1127219200
.align 8
.LC4:
.long 0
.long 1072693248
.align 8
.LC5:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <cuda.h>
#include <iostream>
#include <time.h> /* time */
using namespace std;
__global__
void vecAddKernel(float* A, float* B, float* C, int n)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
if(i<n) C[i] = A[i] + B[i];
}
void print_vec(float* vector, int size)
{
for(int i=0; i<size; i++)
cout << vector[i] << " ";
cout<<endl;
}
void vecAdd(float* A, float* B, float* C, int n)
{
int size = (n * sizeof(float)) * 2;
A = (float*)malloc(size);
C = (float*)malloc(size);
B = (float*)malloc(size);
srand (time(NULL));
for( int i = 0; i < n; i++ )
{
A[i] = rand() % n + 1;;
B[i] = rand() % n + 1;;
}
float *d_A, *d_B, *d_C;
cudaMalloc((void**)&d_A, size);
cudaMemcpy(d_A, A, size, cudaMemcpyHostToDevice);
cudaMalloc((void**)&d_B, size);
cudaMemcpy(d_B, B, size, cudaMemcpyHostToDevice);
cudaMalloc((void**)&d_C, size);
vecAddKernel<<<ceil((float)n/256.0), 256>>>(d_A, d_B, d_C, n);
cudaMemcpy(C, d_C, size, cudaMemcpyDeviceToHost);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
print_vec(C, size);
}
int main()
{
// Size of vectors
int n = 50;
// Host input vectors
float* h_a;
float* h_b;
float* h_c;
vecAdd(h_a, h_b, h_c, n);
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <hip/hip_runtime.h>
#include <iostream>
#include <time.h> /* time */
using namespace std;
__global__
void vecAddKernel(float* A, float* B, float* C, int n)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
if(i<n) C[i] = A[i] + B[i];
}
void print_vec(float* vector, int size)
{
for(int i=0; i<size; i++)
cout << vector[i] << " ";
cout<<endl;
}
void vecAdd(float* A, float* B, float* C, int n)
{
int size = (n * sizeof(float)) * 2;
A = (float*)malloc(size);
C = (float*)malloc(size);
B = (float*)malloc(size);
srand (time(NULL));
for( int i = 0; i < n; i++ )
{
A[i] = rand() % n + 1;;
B[i] = rand() % n + 1;;
}
float *d_A, *d_B, *d_C;
hipMalloc((void**)&d_A, size);
hipMemcpy(d_A, A, size, hipMemcpyHostToDevice);
hipMalloc((void**)&d_B, size);
hipMemcpy(d_B, B, size, hipMemcpyHostToDevice);
hipMalloc((void**)&d_C, size);
vecAddKernel<<<ceil((float)n/256.0), 256>>>(d_A, d_B, d_C, n);
hipMemcpy(C, d_C, size, hipMemcpyDeviceToHost);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
print_vec(C, size);
}
int main()
{
// Size of vectors
int n = 50;
// Host input vectors
float* h_a;
float* h_b;
float* h_c;
vecAdd(h_a, h_b, h_c, n);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <hip/hip_runtime.h>
#include <iostream>
#include <time.h> /* time */
using namespace std;
__global__
void vecAddKernel(float* A, float* B, float* C, int n)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
if(i<n) C[i] = A[i] + B[i];
}
void print_vec(float* vector, int size)
{
for(int i=0; i<size; i++)
cout << vector[i] << " ";
cout<<endl;
}
void vecAdd(float* A, float* B, float* C, int n)
{
int size = (n * sizeof(float)) * 2;
A = (float*)malloc(size);
C = (float*)malloc(size);
B = (float*)malloc(size);
srand (time(NULL));
for( int i = 0; i < n; i++ )
{
A[i] = rand() % n + 1;;
B[i] = rand() % n + 1;;
}
float *d_A, *d_B, *d_C;
hipMalloc((void**)&d_A, size);
hipMemcpy(d_A, A, size, hipMemcpyHostToDevice);
hipMalloc((void**)&d_B, size);
hipMemcpy(d_B, B, size, hipMemcpyHostToDevice);
hipMalloc((void**)&d_C, size);
vecAddKernel<<<ceil((float)n/256.0), 256>>>(d_A, d_B, d_C, n);
hipMemcpy(C, d_C, size, hipMemcpyDeviceToHost);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
print_vec(C, size);
}
int main()
{
// Size of vectors
int n = 50;
// Host input vectors
float* h_a;
float* h_b;
float* h_c;
vecAdd(h_a, h_b, h_c, n);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12vecAddKernelPfS_S_i
.globl _Z12vecAddKernelPfS_S_i
.p2align 8
.type _Z12vecAddKernelPfS_S_i,@function
_Z12vecAddKernelPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12vecAddKernelPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12vecAddKernelPfS_S_i, .Lfunc_end0-_Z12vecAddKernelPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12vecAddKernelPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12vecAddKernelPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <hip/hip_runtime.h>
#include <iostream>
#include <time.h> /* time */
using namespace std;
__global__
void vecAddKernel(float* A, float* B, float* C, int n)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
if(i<n) C[i] = A[i] + B[i];
}
void print_vec(float* vector, int size)
{
for(int i=0; i<size; i++)
cout << vector[i] << " ";
cout<<endl;
}
void vecAdd(float* A, float* B, float* C, int n)
{
int size = (n * sizeof(float)) * 2;
A = (float*)malloc(size);
C = (float*)malloc(size);
B = (float*)malloc(size);
srand (time(NULL));
for( int i = 0; i < n; i++ )
{
A[i] = rand() % n + 1;;
B[i] = rand() % n + 1;;
}
float *d_A, *d_B, *d_C;
hipMalloc((void**)&d_A, size);
hipMemcpy(d_A, A, size, hipMemcpyHostToDevice);
hipMalloc((void**)&d_B, size);
hipMemcpy(d_B, B, size, hipMemcpyHostToDevice);
hipMalloc((void**)&d_C, size);
vecAddKernel<<<ceil((float)n/256.0), 256>>>(d_A, d_B, d_C, n);
hipMemcpy(C, d_C, size, hipMemcpyDeviceToHost);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
print_vec(C, size);
}
int main()
{
// Size of vectors
int n = 50;
// Host input vectors
float* h_a;
float* h_b;
float* h_c;
vecAdd(h_a, h_b, h_c, n);
return 0;
} | .text
.file "one.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z27__device_stub__vecAddKernelPfS_S_i # -- Begin function _Z27__device_stub__vecAddKernelPfS_S_i
.p2align 4, 0x90
.type _Z27__device_stub__vecAddKernelPfS_S_i,@function
_Z27__device_stub__vecAddKernelPfS_S_i: # @_Z27__device_stub__vecAddKernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12vecAddKernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__vecAddKernelPfS_S_i, .Lfunc_end0-_Z27__device_stub__vecAddKernelPfS_S_i
.cfi_endproc
# -- End function
.globl _Z9print_vecPfi # -- Begin function _Z9print_vecPfi
.p2align 4, 0x90
.type _Z9print_vecPfi,@function
_Z9print_vecPfi: # @_Z9print_vecPfi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
testl %esi, %esi
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r15
cmpq %r15, %r14
jne .LBB1_2
.LBB1_3: # %._crit_edge
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_8
# %bb.4: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_6
# %bb.5:
movzbl 67(%rbx), %eax
jmp .LBB1_7
.LBB1_6:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_7: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp _ZNSo5flushEv # TAILCALL
.LBB1_8:
.cfi_def_cfa_offset 32
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size _Z9print_vecPfi, .Lfunc_end1-_Z9print_vecPfi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z6vecAddPfS_S_i
.LCPI2_0:
.quad 0x3f70000000000000 # double 0.00390625
.text
.globl _Z6vecAddPfS_S_i
.p2align 4, 0x90
.type _Z6vecAddPfS_S_i,@function
_Z6vecAddPfS_S_i: # @_Z6vecAddPfS_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %r15d
leal (,%r15,8), %eax
movslq %eax, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, %r13
movq %rbx, %rdi
callq malloc
movq %rax, 32(%rsp) # 8-byte Spill
movq %rbx, %rdi
callq malloc
movq %rax, %r12
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
testl %r15d, %r15d
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
movl %r15d, %ebp
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltd
idivl %r15d
incl %edx
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
movss %xmm0, (%r13,%r14,4)
callq rand
cltd
idivl %r15d
incl %edx
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
movss %xmm0, (%r12,%r14,4)
incq %r14
cmpq %r14, %rbp
jne .LBB2_2
.LBB2_3: # %._crit_edge
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r13, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %r12, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq %rsp, %rdi
movq %rbx, %rsi
callq hipMalloc
xorps %xmm0, %xmm0
cvtsi2ss %r15d, %xmm0
cvtss2sd %xmm0, %xmm0
mulsd .LCPI2_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %r15d, 28(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z12vecAddKernelPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_5:
movq (%rsp), %rsi
movq 32(%rsp), %r14 # 8-byte Reload
movq %r14, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq %r14, %rdi
movl %ebx, %esi
callq _Z9print_vecPfi
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z6vecAddPfS_S_i, .Lfunc_end2-_Z6vecAddPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $50, %ecx
callq _Z6vecAddPfS_S_i
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12vecAddKernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12vecAddKernelPfS_S_i,@object # @_Z12vecAddKernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z12vecAddKernelPfS_S_i
.p2align 3, 0x0
_Z12vecAddKernelPfS_S_i:
.quad _Z27__device_stub__vecAddKernelPfS_S_i
.size _Z12vecAddKernelPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12vecAddKernelPfS_S_i"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__vecAddKernelPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12vecAddKernelPfS_S_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12vecAddKernelPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12vecAddKernelPfS_S_i
.globl _Z12vecAddKernelPfS_S_i
.p2align 8
.type _Z12vecAddKernelPfS_S_i,@function
_Z12vecAddKernelPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12vecAddKernelPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12vecAddKernelPfS_S_i, .Lfunc_end0-_Z12vecAddKernelPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12vecAddKernelPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12vecAddKernelPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014391b_00000000-6_one.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " "
.text
.globl _Z9print_vecPfi
.type _Z9print_vecPfi, @function
_Z9print_vecPfi:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
testl %esi, %esi
jle .L4
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %r13
leaq _ZSt4cout(%rip), %r12
leaq .LC0(%rip), %rbp
.L5:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %rbp, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbx, %r13
jne .L5
.L4:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %rbx
testq %rbx, %rbx
je .L11
cmpb $0, 56(%rbx)
je .L7
movzbl 67(%rbx), %esi
.L8:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L7:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L8
.cfi_endproc
.LFE3669:
.size _Z9print_vecPfi, .-_Z9print_vecPfi
.globl _Z37__device_stub__Z12vecAddKernelPfS_S_iPfS_S_i
.type _Z37__device_stub__Z12vecAddKernelPfS_S_iPfS_S_i, @function
_Z37__device_stub__Z12vecAddKernelPfS_S_iPfS_S_i:
.LFB3696:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12vecAddKernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z37__device_stub__Z12vecAddKernelPfS_S_iPfS_S_i, .-_Z37__device_stub__Z12vecAddKernelPfS_S_iPfS_S_i
.globl _Z12vecAddKernelPfS_S_i
.type _Z12vecAddKernelPfS_S_i, @function
_Z12vecAddKernelPfS_S_i:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12vecAddKernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z12vecAddKernelPfS_S_i, .-_Z12vecAddKernelPfS_S_i
.globl _Z6vecAddPfS_S_i
.type _Z6vecAddPfS_S_i, @function
_Z6vecAddPfS_S_i:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movslq %ecx, %r14
leal 0(,%rcx,8), %eax
movl %eax, 4(%rsp)
movslq %eax, %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, %r13
movq %r15, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movq %r15, %rdi
call malloc@PLT
movq %rax, %r12
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
testl %ebp, %ebp
jle .L21
salq $2, %r14
movl $0, %ebx
.L22:
call rand@PLT
cltd
idivl %ebp
addl $1, %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, 0(%r13,%rbx)
call rand@PLT
cltd
idivl %ebp
addl $1, %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, (%r12,%rbx)
addq $4, %rbx
cmpq %r14, %rbx
jne .L22
.L21:
leaq 24(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r15, %rdx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 32(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r15, %rdx
movq %r12, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
leaq 40(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl %ebp, %xmm0
cvtss2sd %xmm0, %xmm0
mulsd .LC1(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC5(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC2(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L23
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC4(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L23:
cvttsd2siq %xmm3, %rax
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L24:
movl $2, %ecx
movq %r15, %rdx
movq 40(%rsp), %rsi
movq 8(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movl 4(%rsp), %esi
movq %rbx, %rdi
call _Z9print_vecPfi
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L29
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movl %ebp, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z37__device_stub__Z12vecAddKernelPfS_S_iPfS_S_i
jmp .L24
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size _Z6vecAddPfS_S_i, .-_Z6vecAddPfS_S_i
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $50, %ecx
movl $0, %edx
movl $0, %esi
movl $0, %edi
call _Z6vecAddPfS_S_i
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3671:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z12vecAddKernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z12vecAddKernelPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1064304640
.align 8
.LC2:
.long 0
.long 1127219200
.align 8
.LC4:
.long 0
.long 1072693248
.align 8
.LC5:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "one.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z27__device_stub__vecAddKernelPfS_S_i # -- Begin function _Z27__device_stub__vecAddKernelPfS_S_i
.p2align 4, 0x90
.type _Z27__device_stub__vecAddKernelPfS_S_i,@function
_Z27__device_stub__vecAddKernelPfS_S_i: # @_Z27__device_stub__vecAddKernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12vecAddKernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__vecAddKernelPfS_S_i, .Lfunc_end0-_Z27__device_stub__vecAddKernelPfS_S_i
.cfi_endproc
# -- End function
.globl _Z9print_vecPfi # -- Begin function _Z9print_vecPfi
.p2align 4, 0x90
.type _Z9print_vecPfi,@function
_Z9print_vecPfi: # @_Z9print_vecPfi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
testl %esi, %esi
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r15
cmpq %r15, %r14
jne .LBB1_2
.LBB1_3: # %._crit_edge
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_8
# %bb.4: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_6
# %bb.5:
movzbl 67(%rbx), %eax
jmp .LBB1_7
.LBB1_6:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_7: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp _ZNSo5flushEv # TAILCALL
.LBB1_8:
.cfi_def_cfa_offset 32
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size _Z9print_vecPfi, .Lfunc_end1-_Z9print_vecPfi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z6vecAddPfS_S_i
.LCPI2_0:
.quad 0x3f70000000000000 # double 0.00390625
.text
.globl _Z6vecAddPfS_S_i
.p2align 4, 0x90
.type _Z6vecAddPfS_S_i,@function
_Z6vecAddPfS_S_i: # @_Z6vecAddPfS_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %r15d
leal (,%r15,8), %eax
movslq %eax, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, %r13
movq %rbx, %rdi
callq malloc
movq %rax, 32(%rsp) # 8-byte Spill
movq %rbx, %rdi
callq malloc
movq %rax, %r12
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
testl %r15d, %r15d
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
movl %r15d, %ebp
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltd
idivl %r15d
incl %edx
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
movss %xmm0, (%r13,%r14,4)
callq rand
cltd
idivl %r15d
incl %edx
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
movss %xmm0, (%r12,%r14,4)
incq %r14
cmpq %r14, %rbp
jne .LBB2_2
.LBB2_3: # %._crit_edge
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r13, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %r12, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq %rsp, %rdi
movq %rbx, %rsi
callq hipMalloc
xorps %xmm0, %xmm0
cvtsi2ss %r15d, %xmm0
cvtss2sd %xmm0, %xmm0
mulsd .LCPI2_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %r15d, 28(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z12vecAddKernelPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_5:
movq (%rsp), %rsi
movq 32(%rsp), %r14 # 8-byte Reload
movq %r14, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq %r14, %rdi
movl %ebx, %esi
callq _Z9print_vecPfi
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z6vecAddPfS_S_i, .Lfunc_end2-_Z6vecAddPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $50, %ecx
callq _Z6vecAddPfS_S_i
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12vecAddKernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12vecAddKernelPfS_S_i,@object # @_Z12vecAddKernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z12vecAddKernelPfS_S_i
.p2align 3, 0x0
_Z12vecAddKernelPfS_S_i:
.quad _Z27__device_stub__vecAddKernelPfS_S_i
.size _Z12vecAddKernelPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12vecAddKernelPfS_S_i"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__vecAddKernelPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12vecAddKernelPfS_S_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "init_eta_temp.cuh"
__global__ void init_eta_temp
(
SimulationParameters sim_params,
AssembledSolution d_assem_sol,
real* etaTemp
)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
if (x < sim_params.cells + 1) etaTemp[x] = d_assem_sol.h_BC[x] + d_assem_sol.z_BC[x];
} | code for sm_80
Function : _Z13init_eta_temp20SimulationParameters17AssembledSolutionPd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R8, c[0x0][0x160], PT ; /* 0x0000580008007a0c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R8, R9, c[0x0][0x198] ; /* 0x0000660008047625 */
/* 0x000fc800078e0209 */
/*0090*/ IMAD.WIDE R2, R8.reuse, R9.reuse, c[0x0][0x190] ; /* 0x0000640008027625 */
/* 0x0c0fe400078e0209 */
/*00a0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x1c0] ; /* 0x0000700008087625 */
/* 0x000fe200078e0209 */
/*00d0*/ DADD R6, R4, R2 ; /* 0x0000000004067229 */
/* 0x004e0e0000000002 */
/*00e0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "init_eta_temp.cuh"
__global__ void init_eta_temp
(
SimulationParameters sim_params,
AssembledSolution d_assem_sol,
real* etaTemp
)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
if (x < sim_params.cells + 1) etaTemp[x] = d_assem_sol.h_BC[x] + d_assem_sol.z_BC[x];
} | .file "tmpxft_0005dec8_00000000-6_init_eta_temp.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z74__device_stub__Z13init_eta_temp20SimulationParameters17AssembledSolutionPdR20SimulationParametersR17AssembledSolutionPd
.type _Z74__device_stub__Z13init_eta_temp20SimulationParameters17AssembledSolutionPdR20SimulationParametersR17AssembledSolutionPd, @function
_Z74__device_stub__Z13init_eta_temp20SimulationParameters17AssembledSolutionPdR20SimulationParametersR17AssembledSolutionPd:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq %rdi, 80(%rsp)
movq %rsi, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13init_eta_temp20SimulationParameters17AssembledSolutionPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z74__device_stub__Z13init_eta_temp20SimulationParameters17AssembledSolutionPdR20SimulationParametersR17AssembledSolutionPd, .-_Z74__device_stub__Z13init_eta_temp20SimulationParameters17AssembledSolutionPdR20SimulationParametersR17AssembledSolutionPd
.globl _Z13init_eta_temp20SimulationParameters17AssembledSolutionPd
.type _Z13init_eta_temp20SimulationParameters17AssembledSolutionPd, @function
_Z13init_eta_temp20SimulationParameters17AssembledSolutionPd:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq %rdi, %rdx
leaq 56(%rsp), %rsi
leaq 16(%rsp), %rdi
call _Z74__device_stub__Z13init_eta_temp20SimulationParameters17AssembledSolutionPdR20SimulationParametersR17AssembledSolutionPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13init_eta_temp20SimulationParameters17AssembledSolutionPd, .-_Z13init_eta_temp20SimulationParameters17AssembledSolutionPd
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z13init_eta_temp20SimulationParameters17AssembledSolutionPd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13init_eta_temp20SimulationParameters17AssembledSolutionPd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "init_eta_temp.cuh"
__global__ void init_eta_temp
(
SimulationParameters sim_params,
AssembledSolution d_assem_sol,
real* etaTemp
)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
if (x < sim_params.cells + 1) etaTemp[x] = d_assem_sol.h_BC[x] + d_assem_sol.z_BC[x];
} | #pragma once
#include "hip/hip_runtime.h"
#include "SimulationParameters.h"
#include "AssembledSolution.h"
__global__ void init_eta_temp
(
SimulationParameters sim_params,
AssembledSolution d_assem_sol,
real* etaTemp
); |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #pragma once
#include "hip/hip_runtime.h"
#include "SimulationParameters.h"
#include "AssembledSolution.h"
__global__ void init_eta_temp
(
SimulationParameters sim_params,
AssembledSolution d_assem_sol,
real* etaTemp
); | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #pragma once
#include "hip/hip_runtime.h"
#include "SimulationParameters.h"
#include "AssembledSolution.h"
__global__ void init_eta_temp
(
SimulationParameters sim_params,
AssembledSolution d_assem_sol,
real* etaTemp
); | .text
.file "init_eta_temp.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13init_eta_temp20SimulationParameters17AssembledSolutionPd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R8, c[0x0][0x160], PT ; /* 0x0000580008007a0c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R8, R9, c[0x0][0x198] ; /* 0x0000660008047625 */
/* 0x000fc800078e0209 */
/*0090*/ IMAD.WIDE R2, R8.reuse, R9.reuse, c[0x0][0x190] ; /* 0x0000640008027625 */
/* 0x0c0fe400078e0209 */
/*00a0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x1c0] ; /* 0x0000700008087625 */
/* 0x000fe200078e0209 */
/*00d0*/ DADD R6, R4, R2 ; /* 0x0000000004067229 */
/* 0x004e0e0000000002 */
/*00e0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005dec8_00000000-6_init_eta_temp.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z74__device_stub__Z13init_eta_temp20SimulationParameters17AssembledSolutionPdR20SimulationParametersR17AssembledSolutionPd
.type _Z74__device_stub__Z13init_eta_temp20SimulationParameters17AssembledSolutionPdR20SimulationParametersR17AssembledSolutionPd, @function
_Z74__device_stub__Z13init_eta_temp20SimulationParameters17AssembledSolutionPdR20SimulationParametersR17AssembledSolutionPd:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq %rdi, 80(%rsp)
movq %rsi, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13init_eta_temp20SimulationParameters17AssembledSolutionPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z74__device_stub__Z13init_eta_temp20SimulationParameters17AssembledSolutionPdR20SimulationParametersR17AssembledSolutionPd, .-_Z74__device_stub__Z13init_eta_temp20SimulationParameters17AssembledSolutionPdR20SimulationParametersR17AssembledSolutionPd
.globl _Z13init_eta_temp20SimulationParameters17AssembledSolutionPd
.type _Z13init_eta_temp20SimulationParameters17AssembledSolutionPd, @function
_Z13init_eta_temp20SimulationParameters17AssembledSolutionPd:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq %rdi, %rdx
leaq 56(%rsp), %rsi
leaq 16(%rsp), %rdi
call _Z74__device_stub__Z13init_eta_temp20SimulationParameters17AssembledSolutionPdR20SimulationParametersR17AssembledSolutionPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13init_eta_temp20SimulationParameters17AssembledSolutionPd, .-_Z13init_eta_temp20SimulationParameters17AssembledSolutionPd
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z13init_eta_temp20SimulationParameters17AssembledSolutionPd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13init_eta_temp20SimulationParameters17AssembledSolutionPd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "init_eta_temp.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#define TILE_SIZE 32
#define KERNEL_RADIUS 8
#define KERNEL_LENGTH (2 * KERNEL_RADIUS + 1)
__constant__ float c_M[KERNEL_LENGTH][KERNEL_LENGTH];
const int Width = 3072;
const int Height = 3072;
const int nIter = 300;
float * h_Kernel,*h_Input,*h_Output;
float * d_Input, *d_Output;
//this optimization is not good.
__global__ void convolution_2D_tiled_kernel(float* P, float* N, int height, int width, int pitch, int Mask_Width){
int tx = threadIdx.x;
int ty = threadIdx.y;
int row_o = blockIdx.y * TILE_SIZE + ty;
int col_o = blockIdx.x * TILE_SIZE + tx;
int row_i = row_o - Mask_Width/2;
int col_i = col_o - Mask_Width/2;
__shared__ float N_ds[TILE_SIZE + KERNEL_LENGTH - 1][TILE_SIZE + KERNEL_LENGTH - 1];
if((row_i >= 0) && (row_i < height) &&
(col_i >= 0) && (col_i < width)){
N_ds[ty][tx] = N[row_i * pitch + col_i];
}else{
N_ds[ty][tx] = 0.0f;
}
__syncthreads();
float output = 0.0f;
if(ty < TILE_SIZE && tx < TILE_SIZE){
for(int i = 0;i<Mask_Width;i++){
for(int j = 0;j<Mask_Width;j++){
output += c_M[i][j] * N_ds[i + ty][j + tx];
}
}
if(row_o < height && col_o < width){
P[row_o * width + col_o] = output;
}
}
}
void gpuRunTiledKernel(){
dim3 blockDim(TILE_SIZE,TILE_SIZE);
dim3 gridDim((Width + TILE_SIZE - 1)/TILE_SIZE,(Height + TILE_SIZE - 1)/TILE_SIZE);
convolution_2D_tiled_kernel<<<gridDim,blockDim>>>(d_Output,d_Input,Height,Width,Width,KERNEL_LENGTH);
cudaDeviceSynchronize();
cudaEvent_t start;
cudaEventCreate(&start);
cudaEvent_t stop;
cudaEventCreate(&stop);
cudaEventRecord(start,NULL);
for(int i = 0;i<nIter;i++){
convolution_2D_tiled_kernel<<<gridDim,blockDim>>>(d_Output,d_Input,Height,Width,Width,KERNEL_LENGTH);
}
cudaEventRecord(stop, NULL);
cudaDeviceSynchronize();
float msecTotal = 0.0f;
cudaEventElapsedTime(&msecTotal,start,stop);
float gpuTime = (msecTotal / nIter) * 0.001;
printf("Tiled Kernel Throughput = %0.4f MPixels/sec, Time= %.5f sec, Size= %u Pixels\n",
(1.0e-6 * (Width*Height)/gpuTime),
gpuTime,
Width);
cudaMemcpy(h_Output,d_Output,Width*Height* sizeof(float),cudaMemcpyDeviceToHost);
bool correct = true;
double eps = 1.e-6;
for(int i = 0;i<Width*Height;i++){
double abs_err = fabs(h_Output[i] - KERNEL_LENGTH * KERNEL_LENGTH * 1.0);
if (abs_err > eps)
{
//printf("Error! Index = %d,h_Output = %f,true value = %d\n",
// i, h_Output[i], KERNEL_LENGTH*KERNEL_LENGTH);
correct = false;
}
}
printf("%s\n", correct ? "Result = PASS" : "Result = FAIL");
}
int main(){
h_Kernel = (float*)malloc(KERNEL_LENGTH * KERNEL_LENGTH * sizeof(float));
h_Input = (float*)malloc(Width * Height * sizeof(float));
h_Output = (float*)malloc(Width * Height * sizeof(float));
for(unsigned int i = 0;i<KERNEL_LENGTH*KERNEL_LENGTH;i++){
h_Kernel[i] = 1.0f;
}
for(unsigned int i = 0;i<Width*Height;i++){
h_Input[i] = 1.0f;
}
cudaMalloc((void**)&d_Input, Width * Height * sizeof(float));
cudaMalloc((void**)&d_Output,Width * Height * sizeof(float));
cudaMemcpy(d_Input,h_Input,Width * Height * sizeof(float),cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(c_M,h_Kernel,KERNEL_LENGTH * KERNEL_LENGTH * sizeof(float));
printf("Running GPU convlution 2D ....\n");
gpuRunTiledKernel();
free(h_Input);
free(h_Kernel);
free(h_Output);
cudaFree(d_Input);
cudaFree(d_Output);
} | code for sm_80
Function : _Z27convolution_2D_tiled_kernelPfS_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0020*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff097624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002600 */
/*0050*/ LEA.HI R4, R9, c[0x0][0x17c], RZ, 0x1 ; /* 0x00005f0009047a11 */
/* 0x000fe400078f08ff */
/*0060*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e640000002100 */
/*0070*/ SHF.R.S32.HI R5, RZ, 0x1, R4 ; /* 0x00000001ff057819 */
/* 0x000fc40000011404 */
/*0080*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e620000002500 */
/*0090*/ LEA R3, R3, R0, 0x5 ; /* 0x0000000003037211 */
/* 0x001fc800078e28ff */
/*00a0*/ IADD3 R6, R3, -R5, RZ ; /* 0x8000000503067210 */
/* 0x000fe20007ffe0ff */
/*00b0*/ IMAD R4, R7, 0x20, R2 ; /* 0x0000002007047824 */
/* 0x002fc800078e0202 */
/*00c0*/ IMAD.IADD R5, R4, 0x1, -R5 ; /* 0x0000000104057824 */
/* 0x000fca00078e0a05 */
/*00d0*/ LOP3.LUT R7, R6, R5, RZ, 0xfc, !PT ; /* 0x0000000506077212 */
/* 0x000fc800078efcff */
/*00e0*/ ISETP.GT.AND P0, PT, R7, -0x1, PT ; /* 0xffffffff0700780c */
/* 0x000fc80003f04270 */
/*00f0*/ ISETP.LT.AND P0, PT, R6, c[0x0][0x170], P0 ; /* 0x00005c0006007a0c */
/* 0x000fc80000701270 */
/*0100*/ ISETP.LT.AND P0, PT, R5, c[0x0][0x174], P0 ; /* 0x00005d0005007a0c */
/* 0x000fda0000701270 */
/*0110*/ @P0 MOV R7, 0x4 ; /* 0x0000000400070802 */
/* 0x000fe20000000f00 */
/*0120*/ @P0 IMAD R6, R6, c[0x0][0x178], R5 ; /* 0x00005e0006060a24 */
/* 0x000fc800078e0205 */
/*0130*/ @P0 IMAD.WIDE R6, R6, R7, c[0x0][0x168] ; /* 0x00005a0006060625 */
/* 0x000fcc00078e0207 */
/*0140*/ @P0 LDG.E R7, [R6.64] ; /* 0x0000000406070981 */
/* 0x000ea2000c1e1900 */
/*0150*/ IMAD.SHL.U32 R5, R2.reuse, 0x4, RZ ; /* 0x0000000402057824 */
/* 0x040fe200078e00ff */
/*0160*/ ISETP.GT.AND P1, PT, R2, 0x1f, PT ; /* 0x0000001f0200780c */
/* 0x000fc60003f24270 */
/*0170*/ IMAD R8, R0.reuse, 0xc0, R5 ; /* 0x000000c000087824 */
/* 0x040fe200078e0205 */
/*0180*/ ISETP.GT.OR P1, PT, R0, 0x1f, P1 ; /* 0x0000001f0000780c */
/* 0x000fc80000f24670 */
/*0190*/ @!P0 STS [R8], RZ ; /* 0x000000ff08008388 */
/* 0x0001e80000000800 */
/*01a0*/ @P0 STS [R8], R7 ; /* 0x0000000708000388 */
/* 0x0041e80000000800 */
/*01b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01c0*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*01d0*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x001fe20003f06270 */
/*01e0*/ HFMA2.MMA R15, -RZ, RZ, 0, 0 ; /* 0x00000000ff0f7435 */
/* 0x000fd800000001ff */
/*01f0*/ @!P0 BRA 0xb40 ; /* 0x0000094000008947 */
/* 0x000fea0003800000 */
/*0200*/ IADD3 R6, R9, -0x1, RZ ; /* 0xffffffff09067810 */
/* 0x000fe20007ffe0ff */
/*0210*/ IMAD.MOV.U32 R15, RZ, RZ, RZ ; /* 0x000000ffff0f7224 */
/* 0x000fe200078e00ff */
/*0220*/ IADD3 R7, R5, 0x8, RZ ; /* 0x0000000805077810 */
/* 0x000fe40007ffe0ff */
/*0230*/ ISETP.GE.U32.AND P1, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe40003f26070 */
/*0240*/ LOP3.LUT R6, R9, 0x3, RZ, 0xc0, !PT ; /* 0x0000000309067812 */
/* 0x000fe400078ec0ff */
/*0250*/ MOV R9, RZ ; /* 0x000000ff00097202 */
/* 0x000fe40000000f00 */
/*0260*/ IADD3 R8, -R6, c[0x0][0x17c], RZ ; /* 0x00005f0006087a10 */
/* 0x000fca0007ffe1ff */
/*0270*/ IMAD.IADD R10, R0, 0x1, R9 ; /* 0x00000001000a7824 */
/* 0x000fe200078e0209 */
/*0280*/ MOV R11, RZ ; /* 0x000000ff000b7202 */
/* 0x000fe20000000f00 */
/*0290*/ @!P1 BRA 0x9e0 ; /* 0x0000074000009947 */
/* 0x000fea0003800000 */
/*02a0*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f04270 */
/*02b0*/ IMAD.MOV.U32 R12, RZ, RZ, 0x44 ; /* 0x00000044ff0c7424 */
/* 0x000fe200078e00ff */
/*02c0*/ HFMA2.MMA R11, -RZ, RZ, 0, 0 ; /* 0x00000000ff0b7435 */
/* 0x000fe200000001ff */
/*02d0*/ IMAD R5, R10, 0xc0, R7 ; /* 0x000000c00a057824 */
/* 0x000fc400078e0207 */
/*02e0*/ IMAD.MOV.U32 R13, RZ, RZ, R8 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0008 */
/*02f0*/ IMAD R12, R9, R12, c[0x2][0x0] ; /* 0x00800000090c7624 */
/* 0x000fcc00078e020c */
/*0300*/ @!P0 BRA 0x8c0 ; /* 0x000005b000008947 */
/* 0x000fea0003800000 */
/*0310*/ ISETP.GT.AND P2, PT, R13, 0xc, PT ; /* 0x0000000c0d00780c */
/* 0x000fe40003f44270 */
/*0320*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0330*/ @!P2 BRA 0x6b0 ; /* 0x000003700000a947 */
/* 0x000fea0003800000 */
/*0340*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0350*/ LDS R16, [R5+-0x8] ; /* 0xfffff80005107984 */
/* 0x000e220000000800 */
/*0360*/ LDC R19, c[0x3][R12+-0x8] ; /* 0x00fffe000c137b82 */
/* 0x000e220000000800 */
/*0370*/ IADD3 R13, R13, -0x10, RZ ; /* 0xfffffff00d0d7810 */
/* 0x000fe40007ffe0ff */
/*0380*/ LDS R21, [R5+-0x4] ; /* 0xfffffc0005157984 */
/* 0x000e620000000800 */
/*0390*/ IADD3 R11, R11, 0x10, RZ ; /* 0x000000100b0b7810 */
/* 0x000fe40007ffe0ff */
/*03a0*/ ISETP.GT.AND P2, PT, R13, 0xc, PT ; /* 0x0000000c0d00780c */
/* 0x000fe20003f44270 */
/*03b0*/ LDS R17, [R5] ; /* 0x0000000005117984 */
/* 0x000ea20000000800 */
/*03c0*/ LDC R26, c[0x3][R12+-0x4] ; /* 0x00ffff000c1a7b82 */
/* 0x000e660000000800 */
/*03d0*/ LDS R23, [R5+0x4] ; /* 0x0000040005177984 */
/* 0x000ee80000000800 */
/*03e0*/ LDS R22, [R5+0x8] ; /* 0x0000080005167984 */
/* 0x000f220000000800 */
/*03f0*/ LDC R18, c[0x3][R12] ; /* 0x00c000000c127b82 */
/* 0x000ea60000000800 */
/*0400*/ LDS R20, [R5+0xc] ; /* 0x00000c0005147984 */
/* 0x000f680000000800 */
/*0410*/ LDS R14, [R5+0x10] ; /* 0x00001000050e7984 */
/* 0x000f620000000800 */
/*0420*/ LDC R24, c[0x3][R12+0x4] ; /* 0x00c001000c187b82 */
/* 0x000ef00000000800 */
/*0430*/ LDC R25, c[0x3][R12+0x8] ; /* 0x00c002000c197b82 */
/* 0x000f220000000800 */
/*0440*/ FFMA R16, R16, R19, R15 ; /* 0x0000001310107223 */
/* 0x001fc4000000000f */
/*0450*/ LDS R15, [R5+0x14] ; /* 0x00001400050f7984 */
/* 0x000e2a0000000800 */
/*0460*/ LDC R19, c[0x3][R12+0x10] ; /* 0x00c004000c137b82 */
/* 0x000f620000000800 */
/*0470*/ FFMA R26, R21, R26, R16 ; /* 0x0000001a151a7223 */
/* 0x002fe40000000010 */
/*0480*/ LDS R16, [R5+0x18] ; /* 0x0000180005107984 */
/* 0x000e640000000800 */
/*0490*/ FFMA R26, R17, R18, R26 ; /* 0x00000012111a7223 */
/* 0x004fc4000000001a */
/*04a0*/ LDS R17, [R5+0x1c] ; /* 0x00001c0005117984 */
/* 0x000ea20000000800 */
/*04b0*/ LDC R21, c[0x3][R12+0xc] ; /* 0x00c003000c157b82 */
/* 0x000f620000000800 */
/*04c0*/ FFMA R24, R23, R24, R26 ; /* 0x0000001817187223 */
/* 0x008fc8000000001a */
/*04d0*/ FFMA R25, R22, R25, R24 ; /* 0x0000001916197223 */
/* 0x010fc60000000018 */
/*04e0*/ LDC R18, c[0x3][R12+0x14] ; /* 0x00c005000c127b82 */
/* 0x000e220000000800 */
/*04f0*/ LDS R22, [R5+0x20] ; /* 0x0000200005167984 */
/* 0x000ee80000000800 */
/*0500*/ LDS R24, [R5+0x24] ; /* 0x0000240005187984 */
/* 0x000f260000000800 */
/*0510*/ LDC R23, c[0x3][R12+0x18] ; /* 0x00c006000c177b82 */
/* 0x000e620000000800 */
/*0520*/ FFMA R21, R20, R21, R25 ; /* 0x0000001514157223 */
/* 0x020fce0000000019 */
/*0530*/ LDC R26, c[0x3][R12+0x1c] ; /* 0x00c007000c1a7b82 */
/* 0x000ea20000000800 */
/*0540*/ LDS R20, [R5+0x28] ; /* 0x0000280005147984 */
/* 0x000f620000000800 */
/*0550*/ FFMA R19, R14, R19, R21 ; /* 0x000000130e137223 */
/* 0x000fc60000000015 */
/*0560*/ LDS R14, [R5+0x2c] ; /* 0x00002c00050e7984 */
/* 0x000f220000000800 */
/*0570*/ FFMA R19, R15, R18, R19 ; /* 0x000000120f137223 */
/* 0x001fe40000000013 */
/*0580*/ LDC R21, c[0x3][R12+0x28] ; /* 0x00c00a000c157b82 */
/* 0x000f620000000800 */
/*0590*/ LDS R18, [R5+0x30] ; /* 0x0000300005127984 */
/* 0x000e220000000800 */
/*05a0*/ FFMA R25, R16, R23, R19 ; /* 0x0000001710197223 */
/* 0x002fcc0000000013 */
/*05b0*/ LDC R15, c[0x3][R12+0x20] ; /* 0x00c008000c0f7b82 */
/* 0x000ee20000000800 */
/*05c0*/ LDS R16, [R5+0x34] ; /* 0x0000340005107984 */
/* 0x00022e0000000800 */
/*05d0*/ LDC R23, c[0x3][R12+0x24] ; /* 0x00c009000c177b82 */
/* 0x000f220000000800 */
/*05e0*/ FFMA R26, R17, R26, R25 ; /* 0x0000001a111a7223 */
/* 0x004fe20000000019 */
/*05f0*/ IADD3 R5, R5, 0x40, RZ ; /* 0x0000004005057810 */
/* 0x002fcc0007ffe0ff */
/*0600*/ LDC R19, c[0x3][R12+0x2c] ; /* 0x00c00b000c137b82 */
/* 0x0002b00000000800 */
/*0610*/ LDC R25, c[0x3][R12+0x30] ; /* 0x00c00c000c197b82 */
/* 0x0002220000000800 */
/*0620*/ FFMA R15, R22, R15, R26 ; /* 0x0000000f160f7223 */
/* 0x008fce000000001a */
/*0630*/ LDC R17, c[0x3][R12+0x34] ; /* 0x00c00d000c117b82 */
/* 0x0002e20000000800 */
/*0640*/ FFMA R15, R24, R23, R15 ; /* 0x00000017180f7223 */
/* 0x010fc8000000000f */
/*0650*/ FFMA R15, R20, R21, R15 ; /* 0x00000015140f7223 */
/* 0x020fe2000000000f */
/*0660*/ IADD3 R12, R12, 0x40, RZ ; /* 0x000000400c0c7810 */
/* 0x002fc60007ffe0ff */
/*0670*/ FFMA R14, R14, R19, R15 ; /* 0x000000130e0e7223 */
/* 0x004fc8000000000f */
/*0680*/ FFMA R14, R18, R25, R14 ; /* 0x00000019120e7223 */
/* 0x001fc8000000000e */
/*0690*/ FFMA R15, R16, R17, R14 ; /* 0x00000011100f7223 */
/* 0x008fe2000000000e */
/*06a0*/ @P2 BRA 0x350 ; /* 0xfffffca000002947 */
/* 0x000fea000383ffff */
/*06b0*/ ISETP.GT.AND P2, PT, R13, 0x4, PT ; /* 0x000000040d00780c */
/* 0x000fda0003f44270 */
/*06c0*/ @!P2 BRA 0x8a0 ; /* 0x000001d00000a947 */
/* 0x000fea0003800000 */
/*06d0*/ LDS R24, [R5+-0x8] ; /* 0xfffff80005187984 */
/* 0x000e220000000800 */
/*06e0*/ LDC R23, c[0x3][R12+-0x8] ; /* 0x00fffe000c177b82 */
/* 0x000e220000000800 */
/*06f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0700*/ LDS R26, [R5+-0x4] ; /* 0xfffffc00051a7984 */
/* 0x000e620000000800 */
/*0710*/ IADD3 R11, R11, 0x8, RZ ; /* 0x000000080b0b7810 */
/* 0x000fe40007ffe0ff */
/*0720*/ IADD3 R13, R13, -0x8, RZ ; /* 0xfffffff80d0d7810 */
/* 0x000fe20007ffe0ff */
/*0730*/ LDS R14, [R5] ; /* 0x00000000050e7984 */
/* 0x000ea20000000800 */
/*0740*/ LDC R25, c[0x3][R12+-0x4] ; /* 0x00ffff000c197b82 */
/* 0x000e660000000800 */
/*0750*/ LDS R16, [R5+0x4] ; /* 0x0000040005107984 */
/* 0x000ee80000000800 */
/*0760*/ LDS R17, [R5+0x8] ; /* 0x0000080005117984 */
/* 0x000f220000000800 */
/*0770*/ LDC R19, c[0x3][R12] ; /* 0x00c000000c137b82 */
/* 0x000ea60000000800 */
/*0780*/ LDS R18, [R5+0xc] ; /* 0x00000c0005127984 */
/* 0x000f680000000800 */
/*0790*/ LDS R20, [R5+0x10] ; /* 0x0000100005147984 */
/* 0x000f220000000800 */
/*07a0*/ LDC R21, c[0x3][R12+0x4] ; /* 0x00c001000c157b82 */
/* 0x000ee60000000800 */
/*07b0*/ LDS R22, [R5+0x14] ; /* 0x0000140005167984 */
/* 0x0001640000000800 */
/*07c0*/ IADD3 R5, R5, 0x20, RZ ; /* 0x0000002005057810 */
/* 0x001fe20007ffe0ff */
/*07d0*/ FFMA R23, R24, R23, R15 ; /* 0x0000001718177223 */
/* 0x000fc4000000000f */
/*07e0*/ LDC R24, c[0x3][R12+0x8] ; /* 0x00c002000c187b82 */
/* 0x000f240000000800 */
/*07f0*/ FFMA R26, R26, R25, R23 ; /* 0x000000191a1a7223 */
/* 0x002fc80000000017 */
/*0800*/ FFMA R14, R14, R19, R26 ; /* 0x000000130e0e7223 */
/* 0x004fe4000000001a */
/*0810*/ LDC R15, c[0x3][R12+0xc] ; /* 0x00c003000c0f7b82 */
/* 0x000f640000000800 */
/*0820*/ FFMA R14, R16, R21, R14 ; /* 0x00000015100e7223 */
/* 0x008fcc000000000e */
/*0830*/ LDC R25, c[0x3][R12+0x10] ; /* 0x00c004000c197b82 */
/* 0x0000700000000800 */
/*0840*/ LDC R23, c[0x3][R12+0x14] ; /* 0x00c005000c177b82 */
/* 0x0000a20000000800 */
/*0850*/ FFMA R14, R17, R24, R14 ; /* 0x00000018110e7223 */
/* 0x010fc8000000000e */
/*0860*/ FFMA R14, R18, R15, R14 ; /* 0x0000000f120e7223 */
/* 0x020fe2000000000e */
/*0870*/ IADD3 R12, R12, 0x20, RZ ; /* 0x000000200c0c7810 */
/* 0x001fc60007ffe0ff */
/*0880*/ FFMA R14, R20, R25, R14 ; /* 0x00000019140e7223 */
/* 0x002fc8000000000e */
/*0890*/ FFMA R15, R22, R23, R14 ; /* 0x00000017160f7223 */
/* 0x004fe4000000000e */
/*08a0*/ ISETP.NE.OR P0, PT, R13, RZ, P0 ; /* 0x000000ff0d00720c */
/* 0x000fda0000705670 */
/*08b0*/ @!P0 BRA 0x9e0 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*08c0*/ LDS R14, [R5+-0x8] ; /* 0xfffff800050e7984 */
/* 0x000e220000000800 */
/*08d0*/ LDC R16, c[0x3][R12+-0x8] ; /* 0x00fffe000c107b82 */
/* 0x0002220000000800 */
/*08e0*/ IADD3 R13, R13, -0x4, RZ ; /* 0xfffffffc0d0d7810 */
/* 0x000fe40007ffe0ff */
/*08f0*/ LDS R17, [R5+-0x4] ; /* 0xfffffc0005117984 */
/* 0x000ea20000000800 */
/*0900*/ IADD3 R11, R11, 0x4, RZ ; /* 0x000000040b0b7810 */
/* 0x000fe40007ffe0ff */
/*0910*/ ISETP.NE.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe20003f05270 */
/*0920*/ LDS R19, [R5] ; /* 0x0000000005137984 */
/* 0x000ee20000000800 */
/*0930*/ LDC R18, c[0x3][R12+-0x4] ; /* 0x00ffff000c127b82 */
/* 0x0002a60000000800 */
/*0940*/ LDS R21, [R5+0x4] ; /* 0x0000040005157984 */
/* 0x00096a0000000800 */
/*0950*/ LDC R20, c[0x3][R12] ; /* 0x00c000000c147b82 */
/* 0x0002e20000000800 */
/*0960*/ IADD3 R5, R5, 0x10, RZ ; /* 0x0000001005057810 */
/* 0x010fce0007ffe0ff */
/*0970*/ LDC R22, c[0x3][R12+0x4] ; /* 0x00c001000c167b82 */
/* 0x0003640000000800 */
/*0980*/ IADD3 R12, R12, 0x10, RZ ; /* 0x000000100c0c7810 */
/* 0x002fe20007ffe0ff */
/*0990*/ FFMA R14, R14, R16, R15 ; /* 0x000000100e0e7223 */
/* 0x001fc8000000000f */
/*09a0*/ FFMA R14, R17, R18, R14 ; /* 0x00000012110e7223 */
/* 0x004fc8000000000e */
/*09b0*/ FFMA R14, R19, R20, R14 ; /* 0x00000014130e7223 */
/* 0x008fc8000000000e */
/*09c0*/ FFMA R15, R21, R22, R14 ; /* 0x00000016150f7223 */
/* 0x020fe2000000000e */
/*09d0*/ @P0 BRA 0x8c0 ; /* 0xfffffee000000947 */
/* 0x000fea000383ffff */
/*09e0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05270 */
/*09f0*/ @!P0 BRA 0xb10 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*0a00*/ IADD3 R5, R2, R11, RZ ; /* 0x0000000b02057210 */
/* 0x000fe40007ffe0ff */
/*0a10*/ ISETP.NE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fc60003f05270 */
/*0a20*/ IMAD R5, R10, 0x30, R5 ; /* 0x000000300a057824 */
/* 0x000fe200078e0205 */
/*0a30*/ SHF.L.U32 R10, R11, 0x2, RZ ; /* 0x000000020b0a7819 */
/* 0x000fc600000006ff */
/*0a40*/ IMAD.SHL.U32 R14, R5, 0x4, RZ ; /* 0x00000004050e7824 */
/* 0x000fe400078e00ff */
/*0a50*/ IMAD R13, R9, 0x44, R10 ; /* 0x00000044090d7824 */
/* 0x000fc600078e020a */
/*0a60*/ LDS R12, [R14] ; /* 0x000000000e0c7984 */
/* 0x000e220000000800 */
/*0a70*/ LDC R5, c[0x3][R13] ; /* 0x00c000000d057b82 */
/* 0x000e240000000800 */
/*0a80*/ FFMA R15, R12, R5, R15 ; /* 0x000000050c0f7223 */
/* 0x001fe2000000000f */
/*0a90*/ @!P0 BRA 0xb10 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*0aa0*/ ISETP.NE.AND P0, PT, R6, 0x2, PT ; /* 0x000000020600780c */
/* 0x000fe20003f05270 */
/*0ab0*/ LDS R10, [R14+0x4] ; /* 0x000004000e0a7984 */
/* 0x000e220000000800 */
/*0ac0*/ LDC R5, c[0x3][R13+0x4] ; /* 0x00c001000d057b82 */
/* 0x000e360000000800 */
/*0ad0*/ @P0 LDS R12, [R14+0x8] ; /* 0x000008000e0c0984 */
/* 0x000e620000000800 */
/*0ae0*/ @P0 LDC R11, c[0x3][R13+0x8] ; /* 0x00c002000d0b0b82 */
/* 0x000e620000000800 */
/*0af0*/ FFMA R15, R10, R5, R15 ; /* 0x000000050a0f7223 */
/* 0x001fc8000000000f */
/*0b00*/ @P0 FFMA R15, R12, R11, R15 ; /* 0x0000000b0c0f0223 */
/* 0x002fc6000000000f */
/*0b10*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fc80007ffe0ff */
/*0b20*/ ISETP.GE.AND P0, PT, R9, c[0x0][0x17c], PT ; /* 0x00005f0009007a0c */
/* 0x000fda0003f06270 */
/*0b30*/ @!P0 BRA 0x270 ; /* 0xfffff73000008947 */
/* 0x000fea000383ffff */
/*0b40*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x174], PT ; /* 0x00005d0004007a0c */
/* 0x000fc80003f06270 */
/*0b50*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x170], P0 ; /* 0x00005c0003007a0c */
/* 0x000fda0000706670 */
/*0b60*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0b70*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe400078e00ff */
/*0b80*/ IMAD R3, R3, c[0x0][0x174], R4 ; /* 0x00005d0003037a24 */
/* 0x000fc800078e0204 */
/*0b90*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0202 */
/*0ba0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x000fe2000c101904 */
/*0bb0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0bc0*/ BRA 0xbc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#define TILE_SIZE 32
#define KERNEL_RADIUS 8
#define KERNEL_LENGTH (2 * KERNEL_RADIUS + 1)
__constant__ float c_M[KERNEL_LENGTH][KERNEL_LENGTH];
const int Width = 3072;
const int Height = 3072;
const int nIter = 300;
float * h_Kernel,*h_Input,*h_Output;
float * d_Input, *d_Output;
//this optimization is not good.
__global__ void convolution_2D_tiled_kernel(float* P, float* N, int height, int width, int pitch, int Mask_Width){
int tx = threadIdx.x;
int ty = threadIdx.y;
int row_o = blockIdx.y * TILE_SIZE + ty;
int col_o = blockIdx.x * TILE_SIZE + tx;
int row_i = row_o - Mask_Width/2;
int col_i = col_o - Mask_Width/2;
__shared__ float N_ds[TILE_SIZE + KERNEL_LENGTH - 1][TILE_SIZE + KERNEL_LENGTH - 1];
if((row_i >= 0) && (row_i < height) &&
(col_i >= 0) && (col_i < width)){
N_ds[ty][tx] = N[row_i * pitch + col_i];
}else{
N_ds[ty][tx] = 0.0f;
}
__syncthreads();
float output = 0.0f;
if(ty < TILE_SIZE && tx < TILE_SIZE){
for(int i = 0;i<Mask_Width;i++){
for(int j = 0;j<Mask_Width;j++){
output += c_M[i][j] * N_ds[i + ty][j + tx];
}
}
if(row_o < height && col_o < width){
P[row_o * width + col_o] = output;
}
}
}
void gpuRunTiledKernel(){
dim3 blockDim(TILE_SIZE,TILE_SIZE);
dim3 gridDim((Width + TILE_SIZE - 1)/TILE_SIZE,(Height + TILE_SIZE - 1)/TILE_SIZE);
convolution_2D_tiled_kernel<<<gridDim,blockDim>>>(d_Output,d_Input,Height,Width,Width,KERNEL_LENGTH);
cudaDeviceSynchronize();
cudaEvent_t start;
cudaEventCreate(&start);
cudaEvent_t stop;
cudaEventCreate(&stop);
cudaEventRecord(start,NULL);
for(int i = 0;i<nIter;i++){
convolution_2D_tiled_kernel<<<gridDim,blockDim>>>(d_Output,d_Input,Height,Width,Width,KERNEL_LENGTH);
}
cudaEventRecord(stop, NULL);
cudaDeviceSynchronize();
float msecTotal = 0.0f;
cudaEventElapsedTime(&msecTotal,start,stop);
float gpuTime = (msecTotal / nIter) * 0.001;
printf("Tiled Kernel Throughput = %0.4f MPixels/sec, Time= %.5f sec, Size= %u Pixels\n",
(1.0e-6 * (Width*Height)/gpuTime),
gpuTime,
Width);
cudaMemcpy(h_Output,d_Output,Width*Height* sizeof(float),cudaMemcpyDeviceToHost);
bool correct = true;
double eps = 1.e-6;
for(int i = 0;i<Width*Height;i++){
double abs_err = fabs(h_Output[i] - KERNEL_LENGTH * KERNEL_LENGTH * 1.0);
if (abs_err > eps)
{
//printf("Error! Index = %d,h_Output = %f,true value = %d\n",
// i, h_Output[i], KERNEL_LENGTH*KERNEL_LENGTH);
correct = false;
}
}
printf("%s\n", correct ? "Result = PASS" : "Result = FAIL");
}
int main(){
h_Kernel = (float*)malloc(KERNEL_LENGTH * KERNEL_LENGTH * sizeof(float));
h_Input = (float*)malloc(Width * Height * sizeof(float));
h_Output = (float*)malloc(Width * Height * sizeof(float));
for(unsigned int i = 0;i<KERNEL_LENGTH*KERNEL_LENGTH;i++){
h_Kernel[i] = 1.0f;
}
for(unsigned int i = 0;i<Width*Height;i++){
h_Input[i] = 1.0f;
}
cudaMalloc((void**)&d_Input, Width * Height * sizeof(float));
cudaMalloc((void**)&d_Output,Width * Height * sizeof(float));
cudaMemcpy(d_Input,h_Input,Width * Height * sizeof(float),cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(c_M,h_Kernel,KERNEL_LENGTH * KERNEL_LENGTH * sizeof(float));
printf("Running GPU convlution 2D ....\n");
gpuRunTiledKernel();
free(h_Input);
free(h_Kernel);
free(h_Output);
cudaFree(d_Input);
cudaFree(d_Output);
} | .file "tmpxft_0017c248_00000000-6_Conv2D.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z53__device_stub__Z27convolution_2D_tiled_kernelPfS_iiiiPfS_iiii
.type _Z53__device_stub__Z27convolution_2D_tiled_kernelPfS_iiiiPfS_iiii, @function
_Z53__device_stub__Z27convolution_2D_tiled_kernelPfS_iiiiPfS_iiii:
.LFB2083:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z27convolution_2D_tiled_kernelPfS_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z53__device_stub__Z27convolution_2D_tiled_kernelPfS_iiiiPfS_iiii, .-_Z53__device_stub__Z27convolution_2D_tiled_kernelPfS_iiiiPfS_iiii
.globl _Z27convolution_2D_tiled_kernelPfS_iiii
.type _Z27convolution_2D_tiled_kernelPfS_iiii, @function
_Z27convolution_2D_tiled_kernelPfS_iiii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z27convolution_2D_tiled_kernelPfS_iiiiPfS_iiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z27convolution_2D_tiled_kernelPfS_iiii, .-_Z27convolution_2D_tiled_kernelPfS_iiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Result = PASS"
.LC1:
.string "Result = FAIL"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "Tiled Kernel Throughput = %0.4f MPixels/sec, Time= %.5f sec, Size= %u Pixels\n"
.section .rodata.str1.1
.LC10:
.string "%s\n"
.text
.globl _Z17gpuRunTiledKernelv
.type _Z17gpuRunTiledKernelv, @function
_Z17gpuRunTiledKernelv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $32, 32(%rsp)
movl $32, 36(%rsp)
movl $1, 40(%rsp)
movl $96, 44(%rsp)
movl $96, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L12:
call cudaDeviceSynchronize@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $300, %ebx
jmp .L14
.L24:
movl $17, %r9d
movl $3072, %r8d
movl $3072, %ecx
movl $3072, %edx
movq d_Input(%rip), %rsi
movq d_Output(%rip), %rdi
call _Z53__device_stub__Z27convolution_2D_tiled_kernelPfS_iiiiPfS_iiii
jmp .L12
.L13:
subl $1, %ebx
je .L25
.L14:
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L13
movl $17, %r9d
movl $3072, %r8d
movl $3072, %ecx
movl $3072, %edx
movq d_Input(%rip), %rsi
movq d_Output(%rip), %rdi
call _Z53__device_stub__Z27convolution_2D_tiled_kernelPfS_iiiiPfS_iiii
jmp .L13
.L25:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
call cudaDeviceSynchronize@PLT
movl $0x00000000, 12(%rsp)
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 12(%rsp), %xmm1
divss .LC3(%rip), %xmm1
cvtss2sd %xmm1, %xmm1
mulsd .LC4(%rip), %xmm1
cvtsd2ss %xmm1, %xmm1
cvtss2sd %xmm1, %xmm1
movsd .LC5(%rip), %xmm0
divsd %xmm1, %xmm0
movl $3072, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $37748736, %edx
movq d_Output(%rip), %rsi
movq h_Output(%rip), %rdi
call cudaMemcpy@PLT
movq h_Output(%rip), %rax
leaq 37748736(%rax), %rsi
movl $1, %edx
movsd .LC7(%rip), %xmm3
movq .LC8(%rip), %xmm2
movsd .LC9(%rip), %xmm1
movl $0, %ecx
.L16:
pxor %xmm0, %xmm0
cvtss2sd (%rax), %xmm0
subsd %xmm3, %xmm0
andpd %xmm2, %xmm0
ucomisd %xmm1, %xmm0
cmova %ecx, %edx
addq $4, %rax
cmpq %rsi, %rax
jne .L16
testb %dl, %dl
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rax
cmovne %rax, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z17gpuRunTiledKernelv, .-_Z17gpuRunTiledKernelv
.section .rodata.str1.8
.align 8
.LC12:
.string "Running GPU convlution 2D ....\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $1156, %edi
call malloc@PLT
movq %rax, h_Kernel(%rip)
movl $37748736, %edi
call malloc@PLT
movq %rax, h_Input(%rip)
movl $37748736, %edi
call malloc@PLT
movq %rax, h_Output(%rip)
movl $0, %eax
movss .LC11(%rip), %xmm0
.L28:
movq h_Kernel(%rip), %rdx
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $1156, %rax
jne .L28
movl $0, %eax
movss .LC11(%rip), %xmm0
.L29:
movq h_Input(%rip), %rdx
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $37748736, %rax
jne .L29
movl $37748736, %esi
leaq d_Input(%rip), %rdi
call cudaMalloc@PLT
movl $37748736, %esi
leaq d_Output(%rip), %rdi
call cudaMalloc@PLT
movl $1, %ecx
movl $37748736, %edx
movq h_Input(%rip), %rsi
movq d_Input(%rip), %rdi
call cudaMemcpy@PLT
movl $1, %r8d
movl $0, %ecx
movl $1156, %edx
movq h_Kernel(%rip), %rsi
leaq _ZL3c_M(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z17gpuRunTiledKernelv
movq h_Input(%rip), %rdi
call free@PLT
movq h_Kernel(%rip), %rdi
call free@PLT
movq h_Output(%rip), %rdi
call free@PLT
movq d_Input(%rip), %rdi
call cudaFree@PLT
movq d_Output(%rip), %rdi
call cudaFree@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC13:
.string "_Z27convolution_2D_tiled_kernelPfS_iiii"
.section .rodata.str1.1
.LC14:
.string "c_M"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z27convolution_2D_tiled_kernelPfS_iiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $1156, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL3c_M(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl d_Output
.bss
.align 8
.type d_Output, @object
.size d_Output, 8
d_Output:
.zero 8
.globl d_Input
.align 8
.type d_Input, @object
.size d_Input, 8
d_Input:
.zero 8
.globl h_Output
.align 8
.type h_Output, @object
.size h_Output, 8
h_Output:
.zero 8
.globl h_Input
.align 8
.type h_Input, @object
.size h_Input, 8
h_Input:
.zero 8
.globl h_Kernel
.align 8
.type h_Kernel, @object
.size h_Kernel, 8
h_Kernel:
.zero 8
.local _ZL3c_M
.comm _ZL3c_M,1156,32
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 1133903872
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long -755914244
.long 1062232653
.align 8
.LC5:
.long -1798526145
.long 1076027350
.align 8
.LC7:
.long 0
.long 1081217024
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC8:
.long -1
.long 2147483647
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC9:
.long -1598689907
.long 1051772663
.section .rodata.cst4
.align 4
.LC11:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#define TILE_SIZE 32
#define KERNEL_RADIUS 8
#define KERNEL_LENGTH (2 * KERNEL_RADIUS + 1)
__constant__ float c_M[KERNEL_LENGTH][KERNEL_LENGTH];
const int Width = 3072;
const int Height = 3072;
const int nIter = 300;
float * h_Kernel,*h_Input,*h_Output;
float * d_Input, *d_Output;
//this optimization is not good.
__global__ void convolution_2D_tiled_kernel(float* P, float* N, int height, int width, int pitch, int Mask_Width){
int tx = threadIdx.x;
int ty = threadIdx.y;
int row_o = blockIdx.y * TILE_SIZE + ty;
int col_o = blockIdx.x * TILE_SIZE + tx;
int row_i = row_o - Mask_Width/2;
int col_i = col_o - Mask_Width/2;
__shared__ float N_ds[TILE_SIZE + KERNEL_LENGTH - 1][TILE_SIZE + KERNEL_LENGTH - 1];
if((row_i >= 0) && (row_i < height) &&
(col_i >= 0) && (col_i < width)){
N_ds[ty][tx] = N[row_i * pitch + col_i];
}else{
N_ds[ty][tx] = 0.0f;
}
__syncthreads();
float output = 0.0f;
if(ty < TILE_SIZE && tx < TILE_SIZE){
for(int i = 0;i<Mask_Width;i++){
for(int j = 0;j<Mask_Width;j++){
output += c_M[i][j] * N_ds[i + ty][j + tx];
}
}
if(row_o < height && col_o < width){
P[row_o * width + col_o] = output;
}
}
}
void gpuRunTiledKernel(){
dim3 blockDim(TILE_SIZE,TILE_SIZE);
dim3 gridDim((Width + TILE_SIZE - 1)/TILE_SIZE,(Height + TILE_SIZE - 1)/TILE_SIZE);
convolution_2D_tiled_kernel<<<gridDim,blockDim>>>(d_Output,d_Input,Height,Width,Width,KERNEL_LENGTH);
cudaDeviceSynchronize();
cudaEvent_t start;
cudaEventCreate(&start);
cudaEvent_t stop;
cudaEventCreate(&stop);
cudaEventRecord(start,NULL);
for(int i = 0;i<nIter;i++){
convolution_2D_tiled_kernel<<<gridDim,blockDim>>>(d_Output,d_Input,Height,Width,Width,KERNEL_LENGTH);
}
cudaEventRecord(stop, NULL);
cudaDeviceSynchronize();
float msecTotal = 0.0f;
cudaEventElapsedTime(&msecTotal,start,stop);
float gpuTime = (msecTotal / nIter) * 0.001;
printf("Tiled Kernel Throughput = %0.4f MPixels/sec, Time= %.5f sec, Size= %u Pixels\n",
(1.0e-6 * (Width*Height)/gpuTime),
gpuTime,
Width);
cudaMemcpy(h_Output,d_Output,Width*Height* sizeof(float),cudaMemcpyDeviceToHost);
bool correct = true;
double eps = 1.e-6;
for(int i = 0;i<Width*Height;i++){
double abs_err = fabs(h_Output[i] - KERNEL_LENGTH * KERNEL_LENGTH * 1.0);
if (abs_err > eps)
{
//printf("Error! Index = %d,h_Output = %f,true value = %d\n",
// i, h_Output[i], KERNEL_LENGTH*KERNEL_LENGTH);
correct = false;
}
}
printf("%s\n", correct ? "Result = PASS" : "Result = FAIL");
}
int main(){
h_Kernel = (float*)malloc(KERNEL_LENGTH * KERNEL_LENGTH * sizeof(float));
h_Input = (float*)malloc(Width * Height * sizeof(float));
h_Output = (float*)malloc(Width * Height * sizeof(float));
for(unsigned int i = 0;i<KERNEL_LENGTH*KERNEL_LENGTH;i++){
h_Kernel[i] = 1.0f;
}
for(unsigned int i = 0;i<Width*Height;i++){
h_Input[i] = 1.0f;
}
cudaMalloc((void**)&d_Input, Width * Height * sizeof(float));
cudaMalloc((void**)&d_Output,Width * Height * sizeof(float));
cudaMemcpy(d_Input,h_Input,Width * Height * sizeof(float),cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(c_M,h_Kernel,KERNEL_LENGTH * KERNEL_LENGTH * sizeof(float));
printf("Running GPU convlution 2D ....\n");
gpuRunTiledKernel();
free(h_Input);
free(h_Kernel);
free(h_Output);
cudaFree(d_Input);
cudaFree(d_Output);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define TILE_SIZE 32
#define KERNEL_RADIUS 8
#define KERNEL_LENGTH (2 * KERNEL_RADIUS + 1)
__constant__ float c_M[KERNEL_LENGTH][KERNEL_LENGTH];
const int Width = 3072;
const int Height = 3072;
const int nIter = 300;
float * h_Kernel,*h_Input,*h_Output;
float * d_Input, *d_Output;
//this optimization is not good.
__global__ void convolution_2D_tiled_kernel(float* P, float* N, int height, int width, int pitch, int Mask_Width){
int tx = threadIdx.x;
int ty = threadIdx.y;
int row_o = blockIdx.y * TILE_SIZE + ty;
int col_o = blockIdx.x * TILE_SIZE + tx;
int row_i = row_o - Mask_Width/2;
int col_i = col_o - Mask_Width/2;
__shared__ float N_ds[TILE_SIZE + KERNEL_LENGTH - 1][TILE_SIZE + KERNEL_LENGTH - 1];
if((row_i >= 0) && (row_i < height) &&
(col_i >= 0) && (col_i < width)){
N_ds[ty][tx] = N[row_i * pitch + col_i];
}else{
N_ds[ty][tx] = 0.0f;
}
__syncthreads();
float output = 0.0f;
if(ty < TILE_SIZE && tx < TILE_SIZE){
for(int i = 0;i<Mask_Width;i++){
for(int j = 0;j<Mask_Width;j++){
output += c_M[i][j] * N_ds[i + ty][j + tx];
}
}
if(row_o < height && col_o < width){
P[row_o * width + col_o] = output;
}
}
}
void gpuRunTiledKernel(){
dim3 blockDim(TILE_SIZE,TILE_SIZE);
dim3 gridDim((Width + TILE_SIZE - 1)/TILE_SIZE,(Height + TILE_SIZE - 1)/TILE_SIZE);
convolution_2D_tiled_kernel<<<gridDim,blockDim>>>(d_Output,d_Input,Height,Width,Width,KERNEL_LENGTH);
hipDeviceSynchronize();
hipEvent_t start;
hipEventCreate(&start);
hipEvent_t stop;
hipEventCreate(&stop);
hipEventRecord(start,NULL);
for(int i = 0;i<nIter;i++){
convolution_2D_tiled_kernel<<<gridDim,blockDim>>>(d_Output,d_Input,Height,Width,Width,KERNEL_LENGTH);
}
hipEventRecord(stop, NULL);
hipDeviceSynchronize();
float msecTotal = 0.0f;
hipEventElapsedTime(&msecTotal,start,stop);
float gpuTime = (msecTotal / nIter) * 0.001;
printf("Tiled Kernel Throughput = %0.4f MPixels/sec, Time= %.5f sec, Size= %u Pixels\n",
(1.0e-6 * (Width*Height)/gpuTime),
gpuTime,
Width);
hipMemcpy(h_Output,d_Output,Width*Height* sizeof(float),hipMemcpyDeviceToHost);
bool correct = true;
double eps = 1.e-6;
for(int i = 0;i<Width*Height;i++){
double abs_err = fabs(h_Output[i] - KERNEL_LENGTH * KERNEL_LENGTH * 1.0);
if (abs_err > eps)
{
//printf("Error! Index = %d,h_Output = %f,true value = %d\n",
// i, h_Output[i], KERNEL_LENGTH*KERNEL_LENGTH);
correct = false;
}
}
printf("%s\n", correct ? "Result = PASS" : "Result = FAIL");
}
int main(){
h_Kernel = (float*)malloc(KERNEL_LENGTH * KERNEL_LENGTH * sizeof(float));
h_Input = (float*)malloc(Width * Height * sizeof(float));
h_Output = (float*)malloc(Width * Height * sizeof(float));
for(unsigned int i = 0;i<KERNEL_LENGTH*KERNEL_LENGTH;i++){
h_Kernel[i] = 1.0f;
}
for(unsigned int i = 0;i<Width*Height;i++){
h_Input[i] = 1.0f;
}
hipMalloc((void**)&d_Input, Width * Height * sizeof(float));
hipMalloc((void**)&d_Output,Width * Height * sizeof(float));
hipMemcpy(d_Input,h_Input,Width * Height * sizeof(float),hipMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(c_M),h_Kernel,KERNEL_LENGTH * KERNEL_LENGTH * sizeof(float));
printf("Running GPU convlution 2D ....\n");
gpuRunTiledKernel();
free(h_Input);
free(h_Kernel);
free(h_Output);
hipFree(d_Input);
hipFree(d_Output);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define TILE_SIZE 32
#define KERNEL_RADIUS 8
#define KERNEL_LENGTH (2 * KERNEL_RADIUS + 1)
__constant__ float c_M[KERNEL_LENGTH][KERNEL_LENGTH];
const int Width = 3072;
const int Height = 3072;
const int nIter = 300;
float * h_Kernel,*h_Input,*h_Output;
float * d_Input, *d_Output;
//this optimization is not good.
__global__ void convolution_2D_tiled_kernel(float* P, float* N, int height, int width, int pitch, int Mask_Width){
int tx = threadIdx.x;
int ty = threadIdx.y;
int row_o = blockIdx.y * TILE_SIZE + ty;
int col_o = blockIdx.x * TILE_SIZE + tx;
int row_i = row_o - Mask_Width/2;
int col_i = col_o - Mask_Width/2;
__shared__ float N_ds[TILE_SIZE + KERNEL_LENGTH - 1][TILE_SIZE + KERNEL_LENGTH - 1];
if((row_i >= 0) && (row_i < height) &&
(col_i >= 0) && (col_i < width)){
N_ds[ty][tx] = N[row_i * pitch + col_i];
}else{
N_ds[ty][tx] = 0.0f;
}
__syncthreads();
float output = 0.0f;
if(ty < TILE_SIZE && tx < TILE_SIZE){
for(int i = 0;i<Mask_Width;i++){
for(int j = 0;j<Mask_Width;j++){
output += c_M[i][j] * N_ds[i + ty][j + tx];
}
}
if(row_o < height && col_o < width){
P[row_o * width + col_o] = output;
}
}
}
void gpuRunTiledKernel(){
dim3 blockDim(TILE_SIZE,TILE_SIZE);
dim3 gridDim((Width + TILE_SIZE - 1)/TILE_SIZE,(Height + TILE_SIZE - 1)/TILE_SIZE);
convolution_2D_tiled_kernel<<<gridDim,blockDim>>>(d_Output,d_Input,Height,Width,Width,KERNEL_LENGTH);
hipDeviceSynchronize();
hipEvent_t start;
hipEventCreate(&start);
hipEvent_t stop;
hipEventCreate(&stop);
hipEventRecord(start,NULL);
for(int i = 0;i<nIter;i++){
convolution_2D_tiled_kernel<<<gridDim,blockDim>>>(d_Output,d_Input,Height,Width,Width,KERNEL_LENGTH);
}
hipEventRecord(stop, NULL);
hipDeviceSynchronize();
float msecTotal = 0.0f;
hipEventElapsedTime(&msecTotal,start,stop);
float gpuTime = (msecTotal / nIter) * 0.001;
printf("Tiled Kernel Throughput = %0.4f MPixels/sec, Time= %.5f sec, Size= %u Pixels\n",
(1.0e-6 * (Width*Height)/gpuTime),
gpuTime,
Width);
hipMemcpy(h_Output,d_Output,Width*Height* sizeof(float),hipMemcpyDeviceToHost);
bool correct = true;
double eps = 1.e-6;
for(int i = 0;i<Width*Height;i++){
double abs_err = fabs(h_Output[i] - KERNEL_LENGTH * KERNEL_LENGTH * 1.0);
if (abs_err > eps)
{
//printf("Error! Index = %d,h_Output = %f,true value = %d\n",
// i, h_Output[i], KERNEL_LENGTH*KERNEL_LENGTH);
correct = false;
}
}
printf("%s\n", correct ? "Result = PASS" : "Result = FAIL");
}
int main(){
h_Kernel = (float*)malloc(KERNEL_LENGTH * KERNEL_LENGTH * sizeof(float));
h_Input = (float*)malloc(Width * Height * sizeof(float));
h_Output = (float*)malloc(Width * Height * sizeof(float));
for(unsigned int i = 0;i<KERNEL_LENGTH*KERNEL_LENGTH;i++){
h_Kernel[i] = 1.0f;
}
for(unsigned int i = 0;i<Width*Height;i++){
h_Input[i] = 1.0f;
}
hipMalloc((void**)&d_Input, Width * Height * sizeof(float));
hipMalloc((void**)&d_Output,Width * Height * sizeof(float));
hipMemcpy(d_Input,h_Input,Width * Height * sizeof(float),hipMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(c_M),h_Kernel,KERNEL_LENGTH * KERNEL_LENGTH * sizeof(float));
printf("Running GPU convlution 2D ....\n");
gpuRunTiledKernel();
free(h_Input);
free(h_Kernel);
free(h_Output);
hipFree(d_Input);
hipFree(d_Output);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z27convolution_2D_tiled_kernelPfS_iiii
.globl _Z27convolution_2D_tiled_kernelPfS_iiii
.p2align 8
.type _Z27convolution_2D_tiled_kernelPfS_iiii,@function
_Z27convolution_2D_tiled_kernelPfS_iiii:
s_clause 0x1
s_load_b32 s8, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x10
v_bfe_u32 v3, v0, 10, 10
v_dual_mov_b32 v5, 0 :: v_dual_and_b32 v4, 0x3ff, v0
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v2, s15, 5, v3
v_lshl_add_u32 v0, s14, 5, v4
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s8, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s8, s2
s_ashr_i32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v6, s2, v2
v_cmpx_lt_i32_e32 -1, v6
s_cbranch_execz .LBB0_4
v_subrev_nc_u32_e32 v1, s2, v0
v_cmp_gt_i32_e32 vcc_lo, s4, v6
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e64 s2, s5, v1
v_cmp_lt_i32_e64 s3, -1, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_3
s_clause 0x1
s_load_b32 s3, s[0:1], 0x18
s_load_b64 s[10:11], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[7:8], null, v6, s3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[5:6], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s10, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s11, v6, vcc_lo
global_load_b32 v5, v[5:6], off
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
s_or_b32 exec_lo, exec_lo, s6
v_lshlrev_b32_e32 v1, 2, v4
v_or_b32_e32 v6, v3, v4
s_mov_b32 s2, exec_lo
v_mad_u32_u24 v1, v3, 0xc0, v1
s_waitcnt vmcnt(0)
ds_store_b32 v1, v5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 32, v6
s_cbranch_execz .LBB0_13
s_cmp_lt_i32 s8, 1
s_cbranch_scc1 .LBB0_10
v_lshlrev_b32_e32 v1, 2, v4
s_mov_b32 s9, 0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, c_M@rel32@lo+4
s_addc_u32 s3, s3, c_M@rel32@hi+12
v_mad_u32_u24 v3, v3, 0xc0, v1
v_mov_b32_e32 v1, 0
.p2align 6
.LBB0_7:
s_delay_alu instid0(VALU_DEP_2)
v_mov_b32_e32 v4, v3
s_mov_b64 s[6:7], s[2:3]
s_mov_b32 s10, s8
.LBB0_8:
s_load_b32 s11, s[6:7], 0x0
ds_load_b32 v5, v4
s_add_i32 s10, s10, -1
v_add_nc_u32_e32 v4, 4, v4
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_cmp_eq_u32 s10, 0
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v1, s11, v5
s_cbranch_scc0 .LBB0_8
s_add_i32 s9, s9, 1
v_add_nc_u32_e32 v3, 0xc0, v3
s_add_u32 s2, s2, 0x44
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s9, s8
s_cbranch_scc0 .LBB0_7
s_branch .LBB0_11
.LBB0_10:
v_mov_b32_e32 v1, 0
.LBB0_11:
v_cmp_gt_i32_e32 vcc_lo, s4, v2
v_cmp_gt_i32_e64 s2, s5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_13
s_load_b64 s[0:1], s[0:1], 0x0
v_mad_u64_u32 v[3:4], null, v2, s5, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[2:3], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[2:3], v1, off
.LBB0_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z27convolution_2D_tiled_kernelPfS_iiii
.amdhsa_group_segment_fixed_size 9216
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z27convolution_2D_tiled_kernelPfS_iiii, .Lfunc_end0-_Z27convolution_2D_tiled_kernelPfS_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected c_M
.type c_M,@object
.section .bss,"aw",@nobits
.globl c_M
.p2align 4, 0x0
c_M:
.zero 1156
.size c_M, 1156
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym c_M
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 9216
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z27convolution_2D_tiled_kernelPfS_iiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z27convolution_2D_tiled_kernelPfS_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define TILE_SIZE 32
#define KERNEL_RADIUS 8
#define KERNEL_LENGTH (2 * KERNEL_RADIUS + 1)
__constant__ float c_M[KERNEL_LENGTH][KERNEL_LENGTH];
const int Width = 3072;
const int Height = 3072;
const int nIter = 300;
float * h_Kernel,*h_Input,*h_Output;
float * d_Input, *d_Output;
//this optimization is not good.
__global__ void convolution_2D_tiled_kernel(float* P, float* N, int height, int width, int pitch, int Mask_Width){
int tx = threadIdx.x;
int ty = threadIdx.y;
int row_o = blockIdx.y * TILE_SIZE + ty;
int col_o = blockIdx.x * TILE_SIZE + tx;
int row_i = row_o - Mask_Width/2;
int col_i = col_o - Mask_Width/2;
__shared__ float N_ds[TILE_SIZE + KERNEL_LENGTH - 1][TILE_SIZE + KERNEL_LENGTH - 1];
if((row_i >= 0) && (row_i < height) &&
(col_i >= 0) && (col_i < width)){
N_ds[ty][tx] = N[row_i * pitch + col_i];
}else{
N_ds[ty][tx] = 0.0f;
}
__syncthreads();
float output = 0.0f;
if(ty < TILE_SIZE && tx < TILE_SIZE){
for(int i = 0;i<Mask_Width;i++){
for(int j = 0;j<Mask_Width;j++){
output += c_M[i][j] * N_ds[i + ty][j + tx];
}
}
if(row_o < height && col_o < width){
P[row_o * width + col_o] = output;
}
}
}
void gpuRunTiledKernel(){
dim3 blockDim(TILE_SIZE,TILE_SIZE);
dim3 gridDim((Width + TILE_SIZE - 1)/TILE_SIZE,(Height + TILE_SIZE - 1)/TILE_SIZE);
convolution_2D_tiled_kernel<<<gridDim,blockDim>>>(d_Output,d_Input,Height,Width,Width,KERNEL_LENGTH);
hipDeviceSynchronize();
hipEvent_t start;
hipEventCreate(&start);
hipEvent_t stop;
hipEventCreate(&stop);
hipEventRecord(start,NULL);
for(int i = 0;i<nIter;i++){
convolution_2D_tiled_kernel<<<gridDim,blockDim>>>(d_Output,d_Input,Height,Width,Width,KERNEL_LENGTH);
}
hipEventRecord(stop, NULL);
hipDeviceSynchronize();
float msecTotal = 0.0f;
hipEventElapsedTime(&msecTotal,start,stop);
float gpuTime = (msecTotal / nIter) * 0.001;
printf("Tiled Kernel Throughput = %0.4f MPixels/sec, Time= %.5f sec, Size= %u Pixels\n",
(1.0e-6 * (Width*Height)/gpuTime),
gpuTime,
Width);
hipMemcpy(h_Output,d_Output,Width*Height* sizeof(float),hipMemcpyDeviceToHost);
bool correct = true;
double eps = 1.e-6;
for(int i = 0;i<Width*Height;i++){
double abs_err = fabs(h_Output[i] - KERNEL_LENGTH * KERNEL_LENGTH * 1.0);
if (abs_err > eps)
{
//printf("Error! Index = %d,h_Output = %f,true value = %d\n",
// i, h_Output[i], KERNEL_LENGTH*KERNEL_LENGTH);
correct = false;
}
}
printf("%s\n", correct ? "Result = PASS" : "Result = FAIL");
}
int main(){
h_Kernel = (float*)malloc(KERNEL_LENGTH * KERNEL_LENGTH * sizeof(float));
h_Input = (float*)malloc(Width * Height * sizeof(float));
h_Output = (float*)malloc(Width * Height * sizeof(float));
for(unsigned int i = 0;i<KERNEL_LENGTH*KERNEL_LENGTH;i++){
h_Kernel[i] = 1.0f;
}
for(unsigned int i = 0;i<Width*Height;i++){
h_Input[i] = 1.0f;
}
hipMalloc((void**)&d_Input, Width * Height * sizeof(float));
hipMalloc((void**)&d_Output,Width * Height * sizeof(float));
hipMemcpy(d_Input,h_Input,Width * Height * sizeof(float),hipMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(c_M),h_Kernel,KERNEL_LENGTH * KERNEL_LENGTH * sizeof(float));
printf("Running GPU convlution 2D ....\n");
gpuRunTiledKernel();
free(h_Input);
free(h_Kernel);
free(h_Output);
hipFree(d_Input);
hipFree(d_Output);
} | .text
.file "Conv2D.hip"
.globl _Z42__device_stub__convolution_2D_tiled_kernelPfS_iiii # -- Begin function _Z42__device_stub__convolution_2D_tiled_kernelPfS_iiii
.p2align 4, 0x90
.type _Z42__device_stub__convolution_2D_tiled_kernelPfS_iiii,@function
_Z42__device_stub__convolution_2D_tiled_kernelPfS_iiii: # @_Z42__device_stub__convolution_2D_tiled_kernelPfS_iiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z27convolution_2D_tiled_kernelPfS_iiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z42__device_stub__convolution_2D_tiled_kernelPfS_iiii, .Lfunc_end0-_Z42__device_stub__convolution_2D_tiled_kernelPfS_iiii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z17gpuRunTiledKernelv
.LCPI1_0:
.long 0x43960000 # float 300
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_1:
.quad 0x3f50624dd2f1a9fc # double 0.001
.LCPI1_2:
.quad 0x4022dfd694ccab3f # double 9.4371840000000002
.LCPI1_3:
.quad 0xc072100000000000 # double -289
.LCPI1_5:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_4:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl _Z17gpuRunTiledKernelv
.p2align 4, 0x90
.type _Z17gpuRunTiledKernelv,@function
_Z17gpuRunTiledKernelv: # @_Z17gpuRunTiledKernelv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $412316860512, %rbx # imm = 0x6000000060
movabsq $137438953504, %r14 # imm = 0x2000000020
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq d_Output(%rip), %rax
movq d_Input(%rip), %rcx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movl $3072, 16(%rsp) # imm = 0xC00
movl $3072, 8(%rsp) # imm = 0xC00
movl $3072, 4(%rsp) # imm = 0xC00
movl $17, (%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z27convolution_2D_tiled_kernelPfS_iiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $300, %r12d # imm = 0x12C
leaq 32(%rsp), %r13
leaq 24(%rsp), %rbp
leaq 96(%rsp), %r15
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_3 Depth=1
decl %r12d
je .LBB1_6
.LBB1_3: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4: # in Loop: Header=BB1_3 Depth=1
movq d_Output(%rip), %rax
movq d_Input(%rip), %rcx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movl $3072, 4(%rsp) # imm = 0xC00
movl $3072, (%rsp) # imm = 0xC00
movl $3072, 92(%rsp) # imm = 0xC00
movl $17, 88(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 92(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z27convolution_2D_tiled_kernelPfS_iiii, %edi
movq %r15, %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_5
.LBB1_6:
movq 8(%rsp), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq hipEventRecord
callq hipDeviceSynchronize
movl $0, 96(%rsp)
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 96(%rsp), %rdi
callq hipEventElapsedTime
movss 96(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
mulsd .LCPI1_1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm1
movsd .LCPI1_2(%rip), %xmm0 # xmm0 = mem[0],zero
divsd %xmm1, %xmm0
movl $.L.str, %edi
movl $3072, %esi # imm = 0xC00
movb $2, %al
callq printf
movq h_Output(%rip), %rdi
movq d_Output(%rip), %rsi
movl $37748736, %edx # imm = 0x2400000
movl $2, %ecx
callq hipMemcpy
movb $1, %cl
movq h_Output(%rip), %rax
movsd .LCPI1_3(%rip), %xmm0 # xmm0 = mem[0],zero
movapd .LCPI1_4(%rip), %xmm1 # xmm1 = [NaN,NaN]
movsd .LCPI1_5(%rip), %xmm2 # xmm2 = mem[0],zero
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_9: # in Loop: Header=BB1_7 Depth=1
movl %edx, %ecx
incq %rbx
cmpq $9437184, %rbx # imm = 0x900000
je .LBB1_10
.LBB1_7: # =>This Inner Loop Header: Depth=1
movss (%rax,%rbx,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
cvtss2sd %xmm3, %xmm3
addsd %xmm0, %xmm3
andpd %xmm1, %xmm3
ucomisd %xmm2, %xmm3
movl $0, %edx
ja .LBB1_9
# %bb.8: # in Loop: Header=BB1_7 Depth=1
movzbl %cl, %edx
jmp .LBB1_9
.LBB1_10:
testb $1, %cl
movl $.L.str.3, %eax
movl $.L.str.2, %edi
cmoveq %rax, %rdi
callq puts@PLT
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z17gpuRunTiledKernelv, .Lfunc_end1-_Z17gpuRunTiledKernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $1156, %edi # imm = 0x484
callq malloc
movq %rax, %r14
movq %rax, h_Kernel(%rip)
movl $37748736, %edi # imm = 0x2400000
callq malloc
movq %rax, %rbx
movq %rax, h_Input(%rip)
movl $37748736, %edi # imm = 0x2400000
callq malloc
movq %rax, h_Output(%rip)
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%r14,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $289, %rax # imm = 0x121
jne .LBB2_1
# %bb.2: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_3: # %.preheader
# =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $9437184, %rax # imm = 0x900000
jne .LBB2_3
# %bb.4:
movl $d_Input, %edi
movl $37748736, %esi # imm = 0x2400000
callq hipMalloc
movl $d_Output, %edi
movl $37748736, %esi # imm = 0x2400000
callq hipMalloc
movq d_Input(%rip), %rdi
movq h_Input(%rip), %rsi
movl $37748736, %edx # imm = 0x2400000
movl $1, %ecx
callq hipMemcpy
movq h_Kernel(%rip), %rsi
movl $c_M, %edi
movl $1156, %edx # imm = 0x484
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movl $.Lstr, %edi
callq puts@PLT
callq _Z17gpuRunTiledKernelv
movq h_Input(%rip), %rdi
callq free
movq h_Kernel(%rip), %rdi
callq free
movq h_Output(%rip), %rdi
callq free
movq d_Input(%rip), %rdi
callq hipFree
movq d_Output(%rip), %rdi
callq hipFree
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27convolution_2D_tiled_kernelPfS_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $c_M, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $1156, %r9d # imm = 0x484
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type c_M,@object # @c_M
.local c_M
.comm c_M,1156,16
.type h_Kernel,@object # @h_Kernel
.bss
.globl h_Kernel
.p2align 3, 0x0
h_Kernel:
.quad 0
.size h_Kernel, 8
.type h_Input,@object # @h_Input
.globl h_Input
.p2align 3, 0x0
h_Input:
.quad 0
.size h_Input, 8
.type h_Output,@object # @h_Output
.globl h_Output
.p2align 3, 0x0
h_Output:
.quad 0
.size h_Output, 8
.type d_Input,@object # @d_Input
.globl d_Input
.p2align 3, 0x0
d_Input:
.quad 0
.size d_Input, 8
.type d_Output,@object # @d_Output
.globl d_Output
.p2align 3, 0x0
d_Output:
.quad 0
.size d_Output, 8
.type _Z27convolution_2D_tiled_kernelPfS_iiii,@object # @_Z27convolution_2D_tiled_kernelPfS_iiii
.section .rodata,"a",@progbits
.globl _Z27convolution_2D_tiled_kernelPfS_iiii
.p2align 3, 0x0
_Z27convolution_2D_tiled_kernelPfS_iiii:
.quad _Z42__device_stub__convolution_2D_tiled_kernelPfS_iiii
.size _Z27convolution_2D_tiled_kernelPfS_iiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Tiled Kernel Throughput = %0.4f MPixels/sec, Time= %.5f sec, Size= %u Pixels\n"
.size .L.str, 78
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Result = PASS"
.size .L.str.2, 14
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Result = FAIL"
.size .L.str.3, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z27convolution_2D_tiled_kernelPfS_iiii"
.size .L__unnamed_1, 40
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "c_M"
.size .L__unnamed_2, 4
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Running GPU convlution 2D ...."
.size .Lstr, 31
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z42__device_stub__convolution_2D_tiled_kernelPfS_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym c_M
.addrsig_sym d_Input
.addrsig_sym d_Output
.addrsig_sym _Z27convolution_2D_tiled_kernelPfS_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z27convolution_2D_tiled_kernelPfS_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0020*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff097624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002600 */
/*0050*/ LEA.HI R4, R9, c[0x0][0x17c], RZ, 0x1 ; /* 0x00005f0009047a11 */
/* 0x000fe400078f08ff */
/*0060*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e640000002100 */
/*0070*/ SHF.R.S32.HI R5, RZ, 0x1, R4 ; /* 0x00000001ff057819 */
/* 0x000fc40000011404 */
/*0080*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e620000002500 */
/*0090*/ LEA R3, R3, R0, 0x5 ; /* 0x0000000003037211 */
/* 0x001fc800078e28ff */
/*00a0*/ IADD3 R6, R3, -R5, RZ ; /* 0x8000000503067210 */
/* 0x000fe20007ffe0ff */
/*00b0*/ IMAD R4, R7, 0x20, R2 ; /* 0x0000002007047824 */
/* 0x002fc800078e0202 */
/*00c0*/ IMAD.IADD R5, R4, 0x1, -R5 ; /* 0x0000000104057824 */
/* 0x000fca00078e0a05 */
/*00d0*/ LOP3.LUT R7, R6, R5, RZ, 0xfc, !PT ; /* 0x0000000506077212 */
/* 0x000fc800078efcff */
/*00e0*/ ISETP.GT.AND P0, PT, R7, -0x1, PT ; /* 0xffffffff0700780c */
/* 0x000fc80003f04270 */
/*00f0*/ ISETP.LT.AND P0, PT, R6, c[0x0][0x170], P0 ; /* 0x00005c0006007a0c */
/* 0x000fc80000701270 */
/*0100*/ ISETP.LT.AND P0, PT, R5, c[0x0][0x174], P0 ; /* 0x00005d0005007a0c */
/* 0x000fda0000701270 */
/*0110*/ @P0 MOV R7, 0x4 ; /* 0x0000000400070802 */
/* 0x000fe20000000f00 */
/*0120*/ @P0 IMAD R6, R6, c[0x0][0x178], R5 ; /* 0x00005e0006060a24 */
/* 0x000fc800078e0205 */
/*0130*/ @P0 IMAD.WIDE R6, R6, R7, c[0x0][0x168] ; /* 0x00005a0006060625 */
/* 0x000fcc00078e0207 */
/*0140*/ @P0 LDG.E R7, [R6.64] ; /* 0x0000000406070981 */
/* 0x000ea2000c1e1900 */
/*0150*/ IMAD.SHL.U32 R5, R2.reuse, 0x4, RZ ; /* 0x0000000402057824 */
/* 0x040fe200078e00ff */
/*0160*/ ISETP.GT.AND P1, PT, R2, 0x1f, PT ; /* 0x0000001f0200780c */
/* 0x000fc60003f24270 */
/*0170*/ IMAD R8, R0.reuse, 0xc0, R5 ; /* 0x000000c000087824 */
/* 0x040fe200078e0205 */
/*0180*/ ISETP.GT.OR P1, PT, R0, 0x1f, P1 ; /* 0x0000001f0000780c */
/* 0x000fc80000f24670 */
/*0190*/ @!P0 STS [R8], RZ ; /* 0x000000ff08008388 */
/* 0x0001e80000000800 */
/*01a0*/ @P0 STS [R8], R7 ; /* 0x0000000708000388 */
/* 0x0041e80000000800 */
/*01b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01c0*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*01d0*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x001fe20003f06270 */
/*01e0*/ HFMA2.MMA R15, -RZ, RZ, 0, 0 ; /* 0x00000000ff0f7435 */
/* 0x000fd800000001ff */
/*01f0*/ @!P0 BRA 0xb40 ; /* 0x0000094000008947 */
/* 0x000fea0003800000 */
/*0200*/ IADD3 R6, R9, -0x1, RZ ; /* 0xffffffff09067810 */
/* 0x000fe20007ffe0ff */
/*0210*/ IMAD.MOV.U32 R15, RZ, RZ, RZ ; /* 0x000000ffff0f7224 */
/* 0x000fe200078e00ff */
/*0220*/ IADD3 R7, R5, 0x8, RZ ; /* 0x0000000805077810 */
/* 0x000fe40007ffe0ff */
/*0230*/ ISETP.GE.U32.AND P1, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe40003f26070 */
/*0240*/ LOP3.LUT R6, R9, 0x3, RZ, 0xc0, !PT ; /* 0x0000000309067812 */
/* 0x000fe400078ec0ff */
/*0250*/ MOV R9, RZ ; /* 0x000000ff00097202 */
/* 0x000fe40000000f00 */
/*0260*/ IADD3 R8, -R6, c[0x0][0x17c], RZ ; /* 0x00005f0006087a10 */
/* 0x000fca0007ffe1ff */
/*0270*/ IMAD.IADD R10, R0, 0x1, R9 ; /* 0x00000001000a7824 */
/* 0x000fe200078e0209 */
/*0280*/ MOV R11, RZ ; /* 0x000000ff000b7202 */
/* 0x000fe20000000f00 */
/*0290*/ @!P1 BRA 0x9e0 ; /* 0x0000074000009947 */
/* 0x000fea0003800000 */
/*02a0*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f04270 */
/*02b0*/ IMAD.MOV.U32 R12, RZ, RZ, 0x44 ; /* 0x00000044ff0c7424 */
/* 0x000fe200078e00ff */
/*02c0*/ HFMA2.MMA R11, -RZ, RZ, 0, 0 ; /* 0x00000000ff0b7435 */
/* 0x000fe200000001ff */
/*02d0*/ IMAD R5, R10, 0xc0, R7 ; /* 0x000000c00a057824 */
/* 0x000fc400078e0207 */
/*02e0*/ IMAD.MOV.U32 R13, RZ, RZ, R8 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0008 */
/*02f0*/ IMAD R12, R9, R12, c[0x2][0x0] ; /* 0x00800000090c7624 */
/* 0x000fcc00078e020c */
/*0300*/ @!P0 BRA 0x8c0 ; /* 0x000005b000008947 */
/* 0x000fea0003800000 */
/*0310*/ ISETP.GT.AND P2, PT, R13, 0xc, PT ; /* 0x0000000c0d00780c */
/* 0x000fe40003f44270 */
/*0320*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0330*/ @!P2 BRA 0x6b0 ; /* 0x000003700000a947 */
/* 0x000fea0003800000 */
/*0340*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0350*/ LDS R16, [R5+-0x8] ; /* 0xfffff80005107984 */
/* 0x000e220000000800 */
/*0360*/ LDC R19, c[0x3][R12+-0x8] ; /* 0x00fffe000c137b82 */
/* 0x000e220000000800 */
/*0370*/ IADD3 R13, R13, -0x10, RZ ; /* 0xfffffff00d0d7810 */
/* 0x000fe40007ffe0ff */
/*0380*/ LDS R21, [R5+-0x4] ; /* 0xfffffc0005157984 */
/* 0x000e620000000800 */
/*0390*/ IADD3 R11, R11, 0x10, RZ ; /* 0x000000100b0b7810 */
/* 0x000fe40007ffe0ff */
/*03a0*/ ISETP.GT.AND P2, PT, R13, 0xc, PT ; /* 0x0000000c0d00780c */
/* 0x000fe20003f44270 */
/*03b0*/ LDS R17, [R5] ; /* 0x0000000005117984 */
/* 0x000ea20000000800 */
/*03c0*/ LDC R26, c[0x3][R12+-0x4] ; /* 0x00ffff000c1a7b82 */
/* 0x000e660000000800 */
/*03d0*/ LDS R23, [R5+0x4] ; /* 0x0000040005177984 */
/* 0x000ee80000000800 */
/*03e0*/ LDS R22, [R5+0x8] ; /* 0x0000080005167984 */
/* 0x000f220000000800 */
/*03f0*/ LDC R18, c[0x3][R12] ; /* 0x00c000000c127b82 */
/* 0x000ea60000000800 */
/*0400*/ LDS R20, [R5+0xc] ; /* 0x00000c0005147984 */
/* 0x000f680000000800 */
/*0410*/ LDS R14, [R5+0x10] ; /* 0x00001000050e7984 */
/* 0x000f620000000800 */
/*0420*/ LDC R24, c[0x3][R12+0x4] ; /* 0x00c001000c187b82 */
/* 0x000ef00000000800 */
/*0430*/ LDC R25, c[0x3][R12+0x8] ; /* 0x00c002000c197b82 */
/* 0x000f220000000800 */
/*0440*/ FFMA R16, R16, R19, R15 ; /* 0x0000001310107223 */
/* 0x001fc4000000000f */
/*0450*/ LDS R15, [R5+0x14] ; /* 0x00001400050f7984 */
/* 0x000e2a0000000800 */
/*0460*/ LDC R19, c[0x3][R12+0x10] ; /* 0x00c004000c137b82 */
/* 0x000f620000000800 */
/*0470*/ FFMA R26, R21, R26, R16 ; /* 0x0000001a151a7223 */
/* 0x002fe40000000010 */
/*0480*/ LDS R16, [R5+0x18] ; /* 0x0000180005107984 */
/* 0x000e640000000800 */
/*0490*/ FFMA R26, R17, R18, R26 ; /* 0x00000012111a7223 */
/* 0x004fc4000000001a */
/*04a0*/ LDS R17, [R5+0x1c] ; /* 0x00001c0005117984 */
/* 0x000ea20000000800 */
/*04b0*/ LDC R21, c[0x3][R12+0xc] ; /* 0x00c003000c157b82 */
/* 0x000f620000000800 */
/*04c0*/ FFMA R24, R23, R24, R26 ; /* 0x0000001817187223 */
/* 0x008fc8000000001a */
/*04d0*/ FFMA R25, R22, R25, R24 ; /* 0x0000001916197223 */
/* 0x010fc60000000018 */
/*04e0*/ LDC R18, c[0x3][R12+0x14] ; /* 0x00c005000c127b82 */
/* 0x000e220000000800 */
/*04f0*/ LDS R22, [R5+0x20] ; /* 0x0000200005167984 */
/* 0x000ee80000000800 */
/*0500*/ LDS R24, [R5+0x24] ; /* 0x0000240005187984 */
/* 0x000f260000000800 */
/*0510*/ LDC R23, c[0x3][R12+0x18] ; /* 0x00c006000c177b82 */
/* 0x000e620000000800 */
/*0520*/ FFMA R21, R20, R21, R25 ; /* 0x0000001514157223 */
/* 0x020fce0000000019 */
/*0530*/ LDC R26, c[0x3][R12+0x1c] ; /* 0x00c007000c1a7b82 */
/* 0x000ea20000000800 */
/*0540*/ LDS R20, [R5+0x28] ; /* 0x0000280005147984 */
/* 0x000f620000000800 */
/*0550*/ FFMA R19, R14, R19, R21 ; /* 0x000000130e137223 */
/* 0x000fc60000000015 */
/*0560*/ LDS R14, [R5+0x2c] ; /* 0x00002c00050e7984 */
/* 0x000f220000000800 */
/*0570*/ FFMA R19, R15, R18, R19 ; /* 0x000000120f137223 */
/* 0x001fe40000000013 */
/*0580*/ LDC R21, c[0x3][R12+0x28] ; /* 0x00c00a000c157b82 */
/* 0x000f620000000800 */
/*0590*/ LDS R18, [R5+0x30] ; /* 0x0000300005127984 */
/* 0x000e220000000800 */
/*05a0*/ FFMA R25, R16, R23, R19 ; /* 0x0000001710197223 */
/* 0x002fcc0000000013 */
/*05b0*/ LDC R15, c[0x3][R12+0x20] ; /* 0x00c008000c0f7b82 */
/* 0x000ee20000000800 */
/*05c0*/ LDS R16, [R5+0x34] ; /* 0x0000340005107984 */
/* 0x00022e0000000800 */
/*05d0*/ LDC R23, c[0x3][R12+0x24] ; /* 0x00c009000c177b82 */
/* 0x000f220000000800 */
/*05e0*/ FFMA R26, R17, R26, R25 ; /* 0x0000001a111a7223 */
/* 0x004fe20000000019 */
/*05f0*/ IADD3 R5, R5, 0x40, RZ ; /* 0x0000004005057810 */
/* 0x002fcc0007ffe0ff */
/*0600*/ LDC R19, c[0x3][R12+0x2c] ; /* 0x00c00b000c137b82 */
/* 0x0002b00000000800 */
/*0610*/ LDC R25, c[0x3][R12+0x30] ; /* 0x00c00c000c197b82 */
/* 0x0002220000000800 */
/*0620*/ FFMA R15, R22, R15, R26 ; /* 0x0000000f160f7223 */
/* 0x008fce000000001a */
/*0630*/ LDC R17, c[0x3][R12+0x34] ; /* 0x00c00d000c117b82 */
/* 0x0002e20000000800 */
/*0640*/ FFMA R15, R24, R23, R15 ; /* 0x00000017180f7223 */
/* 0x010fc8000000000f */
/*0650*/ FFMA R15, R20, R21, R15 ; /* 0x00000015140f7223 */
/* 0x020fe2000000000f */
/*0660*/ IADD3 R12, R12, 0x40, RZ ; /* 0x000000400c0c7810 */
/* 0x002fc60007ffe0ff */
/*0670*/ FFMA R14, R14, R19, R15 ; /* 0x000000130e0e7223 */
/* 0x004fc8000000000f */
/*0680*/ FFMA R14, R18, R25, R14 ; /* 0x00000019120e7223 */
/* 0x001fc8000000000e */
/*0690*/ FFMA R15, R16, R17, R14 ; /* 0x00000011100f7223 */
/* 0x008fe2000000000e */
/*06a0*/ @P2 BRA 0x350 ; /* 0xfffffca000002947 */
/* 0x000fea000383ffff */
/*06b0*/ ISETP.GT.AND P2, PT, R13, 0x4, PT ; /* 0x000000040d00780c */
/* 0x000fda0003f44270 */
/*06c0*/ @!P2 BRA 0x8a0 ; /* 0x000001d00000a947 */
/* 0x000fea0003800000 */
/*06d0*/ LDS R24, [R5+-0x8] ; /* 0xfffff80005187984 */
/* 0x000e220000000800 */
/*06e0*/ LDC R23, c[0x3][R12+-0x8] ; /* 0x00fffe000c177b82 */
/* 0x000e220000000800 */
/*06f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0700*/ LDS R26, [R5+-0x4] ; /* 0xfffffc00051a7984 */
/* 0x000e620000000800 */
/*0710*/ IADD3 R11, R11, 0x8, RZ ; /* 0x000000080b0b7810 */
/* 0x000fe40007ffe0ff */
/*0720*/ IADD3 R13, R13, -0x8, RZ ; /* 0xfffffff80d0d7810 */
/* 0x000fe20007ffe0ff */
/*0730*/ LDS R14, [R5] ; /* 0x00000000050e7984 */
/* 0x000ea20000000800 */
/*0740*/ LDC R25, c[0x3][R12+-0x4] ; /* 0x00ffff000c197b82 */
/* 0x000e660000000800 */
/*0750*/ LDS R16, [R5+0x4] ; /* 0x0000040005107984 */
/* 0x000ee80000000800 */
/*0760*/ LDS R17, [R5+0x8] ; /* 0x0000080005117984 */
/* 0x000f220000000800 */
/*0770*/ LDC R19, c[0x3][R12] ; /* 0x00c000000c137b82 */
/* 0x000ea60000000800 */
/*0780*/ LDS R18, [R5+0xc] ; /* 0x00000c0005127984 */
/* 0x000f680000000800 */
/*0790*/ LDS R20, [R5+0x10] ; /* 0x0000100005147984 */
/* 0x000f220000000800 */
/*07a0*/ LDC R21, c[0x3][R12+0x4] ; /* 0x00c001000c157b82 */
/* 0x000ee60000000800 */
/*07b0*/ LDS R22, [R5+0x14] ; /* 0x0000140005167984 */
/* 0x0001640000000800 */
/*07c0*/ IADD3 R5, R5, 0x20, RZ ; /* 0x0000002005057810 */
/* 0x001fe20007ffe0ff */
/*07d0*/ FFMA R23, R24, R23, R15 ; /* 0x0000001718177223 */
/* 0x000fc4000000000f */
/*07e0*/ LDC R24, c[0x3][R12+0x8] ; /* 0x00c002000c187b82 */
/* 0x000f240000000800 */
/*07f0*/ FFMA R26, R26, R25, R23 ; /* 0x000000191a1a7223 */
/* 0x002fc80000000017 */
/*0800*/ FFMA R14, R14, R19, R26 ; /* 0x000000130e0e7223 */
/* 0x004fe4000000001a */
/*0810*/ LDC R15, c[0x3][R12+0xc] ; /* 0x00c003000c0f7b82 */
/* 0x000f640000000800 */
/*0820*/ FFMA R14, R16, R21, R14 ; /* 0x00000015100e7223 */
/* 0x008fcc000000000e */
/*0830*/ LDC R25, c[0x3][R12+0x10] ; /* 0x00c004000c197b82 */
/* 0x0000700000000800 */
/*0840*/ LDC R23, c[0x3][R12+0x14] ; /* 0x00c005000c177b82 */
/* 0x0000a20000000800 */
/*0850*/ FFMA R14, R17, R24, R14 ; /* 0x00000018110e7223 */
/* 0x010fc8000000000e */
/*0860*/ FFMA R14, R18, R15, R14 ; /* 0x0000000f120e7223 */
/* 0x020fe2000000000e */
/*0870*/ IADD3 R12, R12, 0x20, RZ ; /* 0x000000200c0c7810 */
/* 0x001fc60007ffe0ff */
/*0880*/ FFMA R14, R20, R25, R14 ; /* 0x00000019140e7223 */
/* 0x002fc8000000000e */
/*0890*/ FFMA R15, R22, R23, R14 ; /* 0x00000017160f7223 */
/* 0x004fe4000000000e */
/*08a0*/ ISETP.NE.OR P0, PT, R13, RZ, P0 ; /* 0x000000ff0d00720c */
/* 0x000fda0000705670 */
/*08b0*/ @!P0 BRA 0x9e0 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*08c0*/ LDS R14, [R5+-0x8] ; /* 0xfffff800050e7984 */
/* 0x000e220000000800 */
/*08d0*/ LDC R16, c[0x3][R12+-0x8] ; /* 0x00fffe000c107b82 */
/* 0x0002220000000800 */
/*08e0*/ IADD3 R13, R13, -0x4, RZ ; /* 0xfffffffc0d0d7810 */
/* 0x000fe40007ffe0ff */
/*08f0*/ LDS R17, [R5+-0x4] ; /* 0xfffffc0005117984 */
/* 0x000ea20000000800 */
/*0900*/ IADD3 R11, R11, 0x4, RZ ; /* 0x000000040b0b7810 */
/* 0x000fe40007ffe0ff */
/*0910*/ ISETP.NE.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe20003f05270 */
/*0920*/ LDS R19, [R5] ; /* 0x0000000005137984 */
/* 0x000ee20000000800 */
/*0930*/ LDC R18, c[0x3][R12+-0x4] ; /* 0x00ffff000c127b82 */
/* 0x0002a60000000800 */
/*0940*/ LDS R21, [R5+0x4] ; /* 0x0000040005157984 */
/* 0x00096a0000000800 */
/*0950*/ LDC R20, c[0x3][R12] ; /* 0x00c000000c147b82 */
/* 0x0002e20000000800 */
/*0960*/ IADD3 R5, R5, 0x10, RZ ; /* 0x0000001005057810 */
/* 0x010fce0007ffe0ff */
/*0970*/ LDC R22, c[0x3][R12+0x4] ; /* 0x00c001000c167b82 */
/* 0x0003640000000800 */
/*0980*/ IADD3 R12, R12, 0x10, RZ ; /* 0x000000100c0c7810 */
/* 0x002fe20007ffe0ff */
/*0990*/ FFMA R14, R14, R16, R15 ; /* 0x000000100e0e7223 */
/* 0x001fc8000000000f */
/*09a0*/ FFMA R14, R17, R18, R14 ; /* 0x00000012110e7223 */
/* 0x004fc8000000000e */
/*09b0*/ FFMA R14, R19, R20, R14 ; /* 0x00000014130e7223 */
/* 0x008fc8000000000e */
/*09c0*/ FFMA R15, R21, R22, R14 ; /* 0x00000016150f7223 */
/* 0x020fe2000000000e */
/*09d0*/ @P0 BRA 0x8c0 ; /* 0xfffffee000000947 */
/* 0x000fea000383ffff */
/*09e0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05270 */
/*09f0*/ @!P0 BRA 0xb10 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*0a00*/ IADD3 R5, R2, R11, RZ ; /* 0x0000000b02057210 */
/* 0x000fe40007ffe0ff */
/*0a10*/ ISETP.NE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fc60003f05270 */
/*0a20*/ IMAD R5, R10, 0x30, R5 ; /* 0x000000300a057824 */
/* 0x000fe200078e0205 */
/*0a30*/ SHF.L.U32 R10, R11, 0x2, RZ ; /* 0x000000020b0a7819 */
/* 0x000fc600000006ff */
/*0a40*/ IMAD.SHL.U32 R14, R5, 0x4, RZ ; /* 0x00000004050e7824 */
/* 0x000fe400078e00ff */
/*0a50*/ IMAD R13, R9, 0x44, R10 ; /* 0x00000044090d7824 */
/* 0x000fc600078e020a */
/*0a60*/ LDS R12, [R14] ; /* 0x000000000e0c7984 */
/* 0x000e220000000800 */
/*0a70*/ LDC R5, c[0x3][R13] ; /* 0x00c000000d057b82 */
/* 0x000e240000000800 */
/*0a80*/ FFMA R15, R12, R5, R15 ; /* 0x000000050c0f7223 */
/* 0x001fe2000000000f */
/*0a90*/ @!P0 BRA 0xb10 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*0aa0*/ ISETP.NE.AND P0, PT, R6, 0x2, PT ; /* 0x000000020600780c */
/* 0x000fe20003f05270 */
/*0ab0*/ LDS R10, [R14+0x4] ; /* 0x000004000e0a7984 */
/* 0x000e220000000800 */
/*0ac0*/ LDC R5, c[0x3][R13+0x4] ; /* 0x00c001000d057b82 */
/* 0x000e360000000800 */
/*0ad0*/ @P0 LDS R12, [R14+0x8] ; /* 0x000008000e0c0984 */
/* 0x000e620000000800 */
/*0ae0*/ @P0 LDC R11, c[0x3][R13+0x8] ; /* 0x00c002000d0b0b82 */
/* 0x000e620000000800 */
/*0af0*/ FFMA R15, R10, R5, R15 ; /* 0x000000050a0f7223 */
/* 0x001fc8000000000f */
/*0b00*/ @P0 FFMA R15, R12, R11, R15 ; /* 0x0000000b0c0f0223 */
/* 0x002fc6000000000f */
/*0b10*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fc80007ffe0ff */
/*0b20*/ ISETP.GE.AND P0, PT, R9, c[0x0][0x17c], PT ; /* 0x00005f0009007a0c */
/* 0x000fda0003f06270 */
/*0b30*/ @!P0 BRA 0x270 ; /* 0xfffff73000008947 */
/* 0x000fea000383ffff */
/*0b40*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x174], PT ; /* 0x00005d0004007a0c */
/* 0x000fc80003f06270 */
/*0b50*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x170], P0 ; /* 0x00005c0003007a0c */
/* 0x000fda0000706670 */
/*0b60*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0b70*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe400078e00ff */
/*0b80*/ IMAD R3, R3, c[0x0][0x174], R4 ; /* 0x00005d0003037a24 */
/* 0x000fc800078e0204 */
/*0b90*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0202 */
/*0ba0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x000fe2000c101904 */
/*0bb0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0bc0*/ BRA 0xbc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z27convolution_2D_tiled_kernelPfS_iiii
.globl _Z27convolution_2D_tiled_kernelPfS_iiii
.p2align 8
.type _Z27convolution_2D_tiled_kernelPfS_iiii,@function
_Z27convolution_2D_tiled_kernelPfS_iiii:
s_clause 0x1
s_load_b32 s8, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x10
v_bfe_u32 v3, v0, 10, 10
v_dual_mov_b32 v5, 0 :: v_dual_and_b32 v4, 0x3ff, v0
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v2, s15, 5, v3
v_lshl_add_u32 v0, s14, 5, v4
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s8, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s8, s2
s_ashr_i32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v6, s2, v2
v_cmpx_lt_i32_e32 -1, v6
s_cbranch_execz .LBB0_4
v_subrev_nc_u32_e32 v1, s2, v0
v_cmp_gt_i32_e32 vcc_lo, s4, v6
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e64 s2, s5, v1
v_cmp_lt_i32_e64 s3, -1, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_3
s_clause 0x1
s_load_b32 s3, s[0:1], 0x18
s_load_b64 s[10:11], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[7:8], null, v6, s3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[5:6], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s10, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s11, v6, vcc_lo
global_load_b32 v5, v[5:6], off
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
s_or_b32 exec_lo, exec_lo, s6
v_lshlrev_b32_e32 v1, 2, v4
v_or_b32_e32 v6, v3, v4
s_mov_b32 s2, exec_lo
v_mad_u32_u24 v1, v3, 0xc0, v1
s_waitcnt vmcnt(0)
ds_store_b32 v1, v5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 32, v6
s_cbranch_execz .LBB0_13
s_cmp_lt_i32 s8, 1
s_cbranch_scc1 .LBB0_10
v_lshlrev_b32_e32 v1, 2, v4
s_mov_b32 s9, 0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, c_M@rel32@lo+4
s_addc_u32 s3, s3, c_M@rel32@hi+12
v_mad_u32_u24 v3, v3, 0xc0, v1
v_mov_b32_e32 v1, 0
.p2align 6
.LBB0_7:
s_delay_alu instid0(VALU_DEP_2)
v_mov_b32_e32 v4, v3
s_mov_b64 s[6:7], s[2:3]
s_mov_b32 s10, s8
.LBB0_8:
s_load_b32 s11, s[6:7], 0x0
ds_load_b32 v5, v4
s_add_i32 s10, s10, -1
v_add_nc_u32_e32 v4, 4, v4
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_cmp_eq_u32 s10, 0
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v1, s11, v5
s_cbranch_scc0 .LBB0_8
s_add_i32 s9, s9, 1
v_add_nc_u32_e32 v3, 0xc0, v3
s_add_u32 s2, s2, 0x44
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s9, s8
s_cbranch_scc0 .LBB0_7
s_branch .LBB0_11
.LBB0_10:
v_mov_b32_e32 v1, 0
.LBB0_11:
v_cmp_gt_i32_e32 vcc_lo, s4, v2
v_cmp_gt_i32_e64 s2, s5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_13
s_load_b64 s[0:1], s[0:1], 0x0
v_mad_u64_u32 v[3:4], null, v2, s5, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[2:3], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[2:3], v1, off
.LBB0_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z27convolution_2D_tiled_kernelPfS_iiii
.amdhsa_group_segment_fixed_size 9216
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z27convolution_2D_tiled_kernelPfS_iiii, .Lfunc_end0-_Z27convolution_2D_tiled_kernelPfS_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected c_M
.type c_M,@object
.section .bss,"aw",@nobits
.globl c_M
.p2align 4, 0x0
c_M:
.zero 1156
.size c_M, 1156
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym c_M
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 9216
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z27convolution_2D_tiled_kernelPfS_iiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z27convolution_2D_tiled_kernelPfS_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0017c248_00000000-6_Conv2D.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z53__device_stub__Z27convolution_2D_tiled_kernelPfS_iiiiPfS_iiii
.type _Z53__device_stub__Z27convolution_2D_tiled_kernelPfS_iiiiPfS_iiii, @function
_Z53__device_stub__Z27convolution_2D_tiled_kernelPfS_iiiiPfS_iiii:
.LFB2083:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z27convolution_2D_tiled_kernelPfS_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z53__device_stub__Z27convolution_2D_tiled_kernelPfS_iiiiPfS_iiii, .-_Z53__device_stub__Z27convolution_2D_tiled_kernelPfS_iiiiPfS_iiii
.globl _Z27convolution_2D_tiled_kernelPfS_iiii
.type _Z27convolution_2D_tiled_kernelPfS_iiii, @function
_Z27convolution_2D_tiled_kernelPfS_iiii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z27convolution_2D_tiled_kernelPfS_iiiiPfS_iiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z27convolution_2D_tiled_kernelPfS_iiii, .-_Z27convolution_2D_tiled_kernelPfS_iiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Result = PASS"
.LC1:
.string "Result = FAIL"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "Tiled Kernel Throughput = %0.4f MPixels/sec, Time= %.5f sec, Size= %u Pixels\n"
.section .rodata.str1.1
.LC10:
.string "%s\n"
.text
.globl _Z17gpuRunTiledKernelv
.type _Z17gpuRunTiledKernelv, @function
_Z17gpuRunTiledKernelv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $32, 32(%rsp)
movl $32, 36(%rsp)
movl $1, 40(%rsp)
movl $96, 44(%rsp)
movl $96, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L12:
call cudaDeviceSynchronize@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $300, %ebx
jmp .L14
.L24:
movl $17, %r9d
movl $3072, %r8d
movl $3072, %ecx
movl $3072, %edx
movq d_Input(%rip), %rsi
movq d_Output(%rip), %rdi
call _Z53__device_stub__Z27convolution_2D_tiled_kernelPfS_iiiiPfS_iiii
jmp .L12
.L13:
subl $1, %ebx
je .L25
.L14:
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L13
movl $17, %r9d
movl $3072, %r8d
movl $3072, %ecx
movl $3072, %edx
movq d_Input(%rip), %rsi
movq d_Output(%rip), %rdi
call _Z53__device_stub__Z27convolution_2D_tiled_kernelPfS_iiiiPfS_iiii
jmp .L13
.L25:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
call cudaDeviceSynchronize@PLT
movl $0x00000000, 12(%rsp)
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 12(%rsp), %xmm1
divss .LC3(%rip), %xmm1
cvtss2sd %xmm1, %xmm1
mulsd .LC4(%rip), %xmm1
cvtsd2ss %xmm1, %xmm1
cvtss2sd %xmm1, %xmm1
movsd .LC5(%rip), %xmm0
divsd %xmm1, %xmm0
movl $3072, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $37748736, %edx
movq d_Output(%rip), %rsi
movq h_Output(%rip), %rdi
call cudaMemcpy@PLT
movq h_Output(%rip), %rax
leaq 37748736(%rax), %rsi
movl $1, %edx
movsd .LC7(%rip), %xmm3
movq .LC8(%rip), %xmm2
movsd .LC9(%rip), %xmm1
movl $0, %ecx
.L16:
pxor %xmm0, %xmm0
cvtss2sd (%rax), %xmm0
subsd %xmm3, %xmm0
andpd %xmm2, %xmm0
ucomisd %xmm1, %xmm0
cmova %ecx, %edx
addq $4, %rax
cmpq %rsi, %rax
jne .L16
testb %dl, %dl
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rax
cmovne %rax, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z17gpuRunTiledKernelv, .-_Z17gpuRunTiledKernelv
.section .rodata.str1.8
.align 8
.LC12:
.string "Running GPU convlution 2D ....\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $1156, %edi
call malloc@PLT
movq %rax, h_Kernel(%rip)
movl $37748736, %edi
call malloc@PLT
movq %rax, h_Input(%rip)
movl $37748736, %edi
call malloc@PLT
movq %rax, h_Output(%rip)
movl $0, %eax
movss .LC11(%rip), %xmm0
.L28:
movq h_Kernel(%rip), %rdx
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $1156, %rax
jne .L28
movl $0, %eax
movss .LC11(%rip), %xmm0
.L29:
movq h_Input(%rip), %rdx
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $37748736, %rax
jne .L29
movl $37748736, %esi
leaq d_Input(%rip), %rdi
call cudaMalloc@PLT
movl $37748736, %esi
leaq d_Output(%rip), %rdi
call cudaMalloc@PLT
movl $1, %ecx
movl $37748736, %edx
movq h_Input(%rip), %rsi
movq d_Input(%rip), %rdi
call cudaMemcpy@PLT
movl $1, %r8d
movl $0, %ecx
movl $1156, %edx
movq h_Kernel(%rip), %rsi
leaq _ZL3c_M(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z17gpuRunTiledKernelv
movq h_Input(%rip), %rdi
call free@PLT
movq h_Kernel(%rip), %rdi
call free@PLT
movq h_Output(%rip), %rdi
call free@PLT
movq d_Input(%rip), %rdi
call cudaFree@PLT
movq d_Output(%rip), %rdi
call cudaFree@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC13:
.string "_Z27convolution_2D_tiled_kernelPfS_iiii"
.section .rodata.str1.1
.LC14:
.string "c_M"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z27convolution_2D_tiled_kernelPfS_iiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $1156, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL3c_M(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl d_Output
.bss
.align 8
.type d_Output, @object
.size d_Output, 8
d_Output:
.zero 8
.globl d_Input
.align 8
.type d_Input, @object
.size d_Input, 8
d_Input:
.zero 8
.globl h_Output
.align 8
.type h_Output, @object
.size h_Output, 8
h_Output:
.zero 8
.globl h_Input
.align 8
.type h_Input, @object
.size h_Input, 8
h_Input:
.zero 8
.globl h_Kernel
.align 8
.type h_Kernel, @object
.size h_Kernel, 8
h_Kernel:
.zero 8
.local _ZL3c_M
.comm _ZL3c_M,1156,32
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 1133903872
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long -755914244
.long 1062232653
.align 8
.LC5:
.long -1798526145
.long 1076027350
.align 8
.LC7:
.long 0
.long 1081217024
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC8:
.long -1
.long 2147483647
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC9:
.long -1598689907
.long 1051772663
.section .rodata.cst4
.align 4
.LC11:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Conv2D.hip"
.globl _Z42__device_stub__convolution_2D_tiled_kernelPfS_iiii # -- Begin function _Z42__device_stub__convolution_2D_tiled_kernelPfS_iiii
.p2align 4, 0x90
.type _Z42__device_stub__convolution_2D_tiled_kernelPfS_iiii,@function
_Z42__device_stub__convolution_2D_tiled_kernelPfS_iiii: # @_Z42__device_stub__convolution_2D_tiled_kernelPfS_iiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z27convolution_2D_tiled_kernelPfS_iiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z42__device_stub__convolution_2D_tiled_kernelPfS_iiii, .Lfunc_end0-_Z42__device_stub__convolution_2D_tiled_kernelPfS_iiii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z17gpuRunTiledKernelv
.LCPI1_0:
.long 0x43960000 # float 300
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_1:
.quad 0x3f50624dd2f1a9fc # double 0.001
.LCPI1_2:
.quad 0x4022dfd694ccab3f # double 9.4371840000000002
.LCPI1_3:
.quad 0xc072100000000000 # double -289
.LCPI1_5:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_4:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl _Z17gpuRunTiledKernelv
.p2align 4, 0x90
.type _Z17gpuRunTiledKernelv,@function
_Z17gpuRunTiledKernelv: # @_Z17gpuRunTiledKernelv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $412316860512, %rbx # imm = 0x6000000060
movabsq $137438953504, %r14 # imm = 0x2000000020
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq d_Output(%rip), %rax
movq d_Input(%rip), %rcx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movl $3072, 16(%rsp) # imm = 0xC00
movl $3072, 8(%rsp) # imm = 0xC00
movl $3072, 4(%rsp) # imm = 0xC00
movl $17, (%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z27convolution_2D_tiled_kernelPfS_iiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $300, %r12d # imm = 0x12C
leaq 32(%rsp), %r13
leaq 24(%rsp), %rbp
leaq 96(%rsp), %r15
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_3 Depth=1
decl %r12d
je .LBB1_6
.LBB1_3: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4: # in Loop: Header=BB1_3 Depth=1
movq d_Output(%rip), %rax
movq d_Input(%rip), %rcx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movl $3072, 4(%rsp) # imm = 0xC00
movl $3072, (%rsp) # imm = 0xC00
movl $3072, 92(%rsp) # imm = 0xC00
movl $17, 88(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 92(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z27convolution_2D_tiled_kernelPfS_iiii, %edi
movq %r15, %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_5
.LBB1_6:
movq 8(%rsp), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq hipEventRecord
callq hipDeviceSynchronize
movl $0, 96(%rsp)
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 96(%rsp), %rdi
callq hipEventElapsedTime
movss 96(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
mulsd .LCPI1_1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm1
movsd .LCPI1_2(%rip), %xmm0 # xmm0 = mem[0],zero
divsd %xmm1, %xmm0
movl $.L.str, %edi
movl $3072, %esi # imm = 0xC00
movb $2, %al
callq printf
movq h_Output(%rip), %rdi
movq d_Output(%rip), %rsi
movl $37748736, %edx # imm = 0x2400000
movl $2, %ecx
callq hipMemcpy
movb $1, %cl
movq h_Output(%rip), %rax
movsd .LCPI1_3(%rip), %xmm0 # xmm0 = mem[0],zero
movapd .LCPI1_4(%rip), %xmm1 # xmm1 = [NaN,NaN]
movsd .LCPI1_5(%rip), %xmm2 # xmm2 = mem[0],zero
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_9: # in Loop: Header=BB1_7 Depth=1
movl %edx, %ecx
incq %rbx
cmpq $9437184, %rbx # imm = 0x900000
je .LBB1_10
.LBB1_7: # =>This Inner Loop Header: Depth=1
movss (%rax,%rbx,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
cvtss2sd %xmm3, %xmm3
addsd %xmm0, %xmm3
andpd %xmm1, %xmm3
ucomisd %xmm2, %xmm3
movl $0, %edx
ja .LBB1_9
# %bb.8: # in Loop: Header=BB1_7 Depth=1
movzbl %cl, %edx
jmp .LBB1_9
.LBB1_10:
testb $1, %cl
movl $.L.str.3, %eax
movl $.L.str.2, %edi
cmoveq %rax, %rdi
callq puts@PLT
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z17gpuRunTiledKernelv, .Lfunc_end1-_Z17gpuRunTiledKernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $1156, %edi # imm = 0x484
callq malloc
movq %rax, %r14
movq %rax, h_Kernel(%rip)
movl $37748736, %edi # imm = 0x2400000
callq malloc
movq %rax, %rbx
movq %rax, h_Input(%rip)
movl $37748736, %edi # imm = 0x2400000
callq malloc
movq %rax, h_Output(%rip)
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%r14,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $289, %rax # imm = 0x121
jne .LBB2_1
# %bb.2: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_3: # %.preheader
# =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $9437184, %rax # imm = 0x900000
jne .LBB2_3
# %bb.4:
movl $d_Input, %edi
movl $37748736, %esi # imm = 0x2400000
callq hipMalloc
movl $d_Output, %edi
movl $37748736, %esi # imm = 0x2400000
callq hipMalloc
movq d_Input(%rip), %rdi
movq h_Input(%rip), %rsi
movl $37748736, %edx # imm = 0x2400000
movl $1, %ecx
callq hipMemcpy
movq h_Kernel(%rip), %rsi
movl $c_M, %edi
movl $1156, %edx # imm = 0x484
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movl $.Lstr, %edi
callq puts@PLT
callq _Z17gpuRunTiledKernelv
movq h_Input(%rip), %rdi
callq free
movq h_Kernel(%rip), %rdi
callq free
movq h_Output(%rip), %rdi
callq free
movq d_Input(%rip), %rdi
callq hipFree
movq d_Output(%rip), %rdi
callq hipFree
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27convolution_2D_tiled_kernelPfS_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $c_M, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $1156, %r9d # imm = 0x484
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type c_M,@object # @c_M
.local c_M
.comm c_M,1156,16
.type h_Kernel,@object # @h_Kernel
.bss
.globl h_Kernel
.p2align 3, 0x0
h_Kernel:
.quad 0
.size h_Kernel, 8
.type h_Input,@object # @h_Input
.globl h_Input
.p2align 3, 0x0
h_Input:
.quad 0
.size h_Input, 8
.type h_Output,@object # @h_Output
.globl h_Output
.p2align 3, 0x0
h_Output:
.quad 0
.size h_Output, 8
.type d_Input,@object # @d_Input
.globl d_Input
.p2align 3, 0x0
d_Input:
.quad 0
.size d_Input, 8
.type d_Output,@object # @d_Output
.globl d_Output
.p2align 3, 0x0
d_Output:
.quad 0
.size d_Output, 8
.type _Z27convolution_2D_tiled_kernelPfS_iiii,@object # @_Z27convolution_2D_tiled_kernelPfS_iiii
.section .rodata,"a",@progbits
.globl _Z27convolution_2D_tiled_kernelPfS_iiii
.p2align 3, 0x0
_Z27convolution_2D_tiled_kernelPfS_iiii:
.quad _Z42__device_stub__convolution_2D_tiled_kernelPfS_iiii
.size _Z27convolution_2D_tiled_kernelPfS_iiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Tiled Kernel Throughput = %0.4f MPixels/sec, Time= %.5f sec, Size= %u Pixels\n"
.size .L.str, 78
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Result = PASS"
.size .L.str.2, 14
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Result = FAIL"
.size .L.str.3, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z27convolution_2D_tiled_kernelPfS_iiii"
.size .L__unnamed_1, 40
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "c_M"
.size .L__unnamed_2, 4
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Running GPU convlution 2D ...."
.size .Lstr, 31
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z42__device_stub__convolution_2D_tiled_kernelPfS_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym c_M
.addrsig_sym d_Input
.addrsig_sym d_Output
.addrsig_sym _Z27convolution_2D_tiled_kernelPfS_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void solution_inter(float *z, float *g, float lambda, int nx, int ny)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int idx = x + y*nx;
if (x<nx && y<ny) g[idx] = -z[3 * idx + 2] * lambda;
} | code for sm_80
Function : _Z14solution_interPfS_fii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x174], P0 ; /* 0x00005d0000007a0c */
/* 0x000fe20000706670 */
/*0090*/ IMAD R0, R3, c[0x0][0x174], R0 ; /* 0x00005d0003007a24 */
/* 0x000fd800078e0200 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00c0*/ LEA R2, R0, R0, 0x1 ; /* 0x0000000000027211 */
/* 0x000fe200078e08ff */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00e0*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0205 */
/*00f0*/ LDG.E R2, [R2.64+0x8] ; /* 0x0000080402027981 */
/* 0x000ea2000c1e1900 */
/*0100*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0205 */
/*0110*/ FFMA R7, -R2, c[0x0][0x170], -RZ ; /* 0x00005c0002077a23 */
/* 0x004fca00000009ff */
/*0120*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void solution_inter(float *z, float *g, float lambda, int nx, int ny)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int idx = x + y*nx;
if (x<nx && y<ny) g[idx] = -z[3 * idx + 2] * lambda;
} | .file "tmpxft_00145a7f_00000000-6_solution_inter.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z14solution_interPfS_fiiPfS_fii
.type _Z39__device_stub__Z14solution_interPfS_fiiPfS_fii, @function
_Z39__device_stub__Z14solution_interPfS_fiiPfS_fii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14solution_interPfS_fii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z14solution_interPfS_fiiPfS_fii, .-_Z39__device_stub__Z14solution_interPfS_fiiPfS_fii
.globl _Z14solution_interPfS_fii
.type _Z14solution_interPfS_fii, @function
_Z14solution_interPfS_fii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z14solution_interPfS_fiiPfS_fii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14solution_interPfS_fii, .-_Z14solution_interPfS_fii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14solution_interPfS_fii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14solution_interPfS_fii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void solution_inter(float *z, float *g, float lambda, int nx, int ny)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int idx = x + y*nx;
if (x<nx && y<ny) g[idx] = -z[3 * idx + 2] * lambda;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void solution_inter(float *z, float *g, float lambda, int nx, int ny)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int idx = x + y*nx;
if (x<nx && y<ny) g[idx] = -z[3 * idx + 2] * lambda;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void solution_inter(float *z, float *g, float lambda, int nx, int ny)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int idx = x + y*nx;
if (x<nx && y<ny) g[idx] = -z[3 * idx + 2] * lambda;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14solution_interPfS_fii
.globl _Z14solution_interPfS_fii
.p2align 8
.type _Z14solution_interPfS_fii,@function
_Z14solution_interPfS_fii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x14
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshl_add_u32 v0, v2, 1, v2
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v4, v[0:1], off offset:8
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e64 v2, -v4, s0
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14solution_interPfS_fii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14solution_interPfS_fii, .Lfunc_end0-_Z14solution_interPfS_fii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14solution_interPfS_fii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14solution_interPfS_fii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void solution_inter(float *z, float *g, float lambda, int nx, int ny)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int idx = x + y*nx;
if (x<nx && y<ny) g[idx] = -z[3 * idx + 2] * lambda;
} | .text
.file "solution_inter.hip"
.globl _Z29__device_stub__solution_interPfS_fii # -- Begin function _Z29__device_stub__solution_interPfS_fii
.p2align 4, 0x90
.type _Z29__device_stub__solution_interPfS_fii,@function
_Z29__device_stub__solution_interPfS_fii: # @_Z29__device_stub__solution_interPfS_fii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14solution_interPfS_fii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__solution_interPfS_fii, .Lfunc_end0-_Z29__device_stub__solution_interPfS_fii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14solution_interPfS_fii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14solution_interPfS_fii,@object # @_Z14solution_interPfS_fii
.section .rodata,"a",@progbits
.globl _Z14solution_interPfS_fii
.p2align 3, 0x0
_Z14solution_interPfS_fii:
.quad _Z29__device_stub__solution_interPfS_fii
.size _Z14solution_interPfS_fii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14solution_interPfS_fii"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__solution_interPfS_fii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14solution_interPfS_fii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14solution_interPfS_fii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x174], P0 ; /* 0x00005d0000007a0c */
/* 0x000fe20000706670 */
/*0090*/ IMAD R0, R3, c[0x0][0x174], R0 ; /* 0x00005d0003007a24 */
/* 0x000fd800078e0200 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00c0*/ LEA R2, R0, R0, 0x1 ; /* 0x0000000000027211 */
/* 0x000fe200078e08ff */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00e0*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0205 */
/*00f0*/ LDG.E R2, [R2.64+0x8] ; /* 0x0000080402027981 */
/* 0x000ea2000c1e1900 */
/*0100*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0205 */
/*0110*/ FFMA R7, -R2, c[0x0][0x170], -RZ ; /* 0x00005c0002077a23 */
/* 0x004fca00000009ff */
/*0120*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14solution_interPfS_fii
.globl _Z14solution_interPfS_fii
.p2align 8
.type _Z14solution_interPfS_fii,@function
_Z14solution_interPfS_fii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x14
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshl_add_u32 v0, v2, 1, v2
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v4, v[0:1], off offset:8
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e64 v2, -v4, s0
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14solution_interPfS_fii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14solution_interPfS_fii, .Lfunc_end0-_Z14solution_interPfS_fii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14solution_interPfS_fii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14solution_interPfS_fii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00145a7f_00000000-6_solution_inter.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z14solution_interPfS_fiiPfS_fii
.type _Z39__device_stub__Z14solution_interPfS_fiiPfS_fii, @function
_Z39__device_stub__Z14solution_interPfS_fiiPfS_fii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14solution_interPfS_fii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z14solution_interPfS_fiiPfS_fii, .-_Z39__device_stub__Z14solution_interPfS_fiiPfS_fii
.globl _Z14solution_interPfS_fii
.type _Z14solution_interPfS_fii, @function
_Z14solution_interPfS_fii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z14solution_interPfS_fiiPfS_fii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14solution_interPfS_fii, .-_Z14solution_interPfS_fii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14solution_interPfS_fii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14solution_interPfS_fii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "solution_inter.hip"
.globl _Z29__device_stub__solution_interPfS_fii # -- Begin function _Z29__device_stub__solution_interPfS_fii
.p2align 4, 0x90
.type _Z29__device_stub__solution_interPfS_fii,@function
_Z29__device_stub__solution_interPfS_fii: # @_Z29__device_stub__solution_interPfS_fii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14solution_interPfS_fii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__solution_interPfS_fii, .Lfunc_end0-_Z29__device_stub__solution_interPfS_fii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14solution_interPfS_fii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14solution_interPfS_fii,@object # @_Z14solution_interPfS_fii
.section .rodata,"a",@progbits
.globl _Z14solution_interPfS_fii
.p2align 3, 0x0
_Z14solution_interPfS_fii:
.quad _Z29__device_stub__solution_interPfS_fii
.size _Z14solution_interPfS_fii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14solution_interPfS_fii"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__solution_interPfS_fii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14solution_interPfS_fii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "seq.hh"
#include <cassert>
#include <stdexcept>
#include "graph.hh"
#include "mse-grad.hh"
#include "ops-builder.hh"
#include "../runtime/node.hh"
#include "../memory/alloc.hh"
namespace ops
{
Seq::Seq(std::vector<Op*> ops)
: Op("seq", ops.back()->shape_get(), ops)
{}
void Seq::compile()
{
auto& g = Graph::instance();
auto& clast = g.compiled(preds().back());
std::vector<rt::Node*> nodes;
for (auto p : preds())
nodes.push_back(g.compiled(p).out_node);
auto out_node = rt::Node::nop(nodes);
g.add_compiled(this, {out_node}, {}, out_node, clast.out_shape, clast.out_data);
}
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "seq.hh"
#include <cassert>
#include <stdexcept>
#include "graph.hh"
#include "mse-grad.hh"
#include "ops-builder.hh"
#include "../runtime/node.hh"
#include "../memory/alloc.hh"
namespace ops
{
Seq::Seq(std::vector<Op*> ops)
: Op("seq", ops.back()->shape_get(), ops)
{}
void Seq::compile()
{
auto& g = Graph::instance();
auto& clast = g.compiled(preds().back());
std::vector<rt::Node*> nodes;
for (auto p : preds())
nodes.push_back(g.compiled(p).out_node);
auto out_node = rt::Node::nop(nodes);
g.add_compiled(this, {out_node}, {}, out_node, clast.out_shape, clast.out_data);
}
} | .file "tmpxft_00037ff4_00000000-6_seq.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4639:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4639:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .text._ZN3ops3SeqD2Ev,"axG",@progbits,_ZN3ops3SeqD5Ev,comdat
.align 2
.weak _ZN3ops3SeqD2Ev
.type _ZN3ops3SeqD2Ev, @function
_ZN3ops3SeqD2Ev:
.LFB5659:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
leaq 16+_ZTVN3ops2OpE(%rip), %rax
movq %rax, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .L4
movq 104(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L4:
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .L5
movq 80(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L5:
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .L6
movq 56(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L6:
movq 8(%rbx), %rdi
leaq 24(%rbx), %rax
cmpq %rax, %rdi
je .L3
movq 24(%rbx), %rsi
addq $1, %rsi
call _ZdlPvm@PLT
.L3:
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5659:
.size _ZN3ops3SeqD2Ev, .-_ZN3ops3SeqD2Ev
.weak _ZN3ops3SeqD1Ev
.set _ZN3ops3SeqD1Ev,_ZN3ops3SeqD2Ev
.section .text._ZN3ops3SeqD0Ev,"axG",@progbits,_ZN3ops3SeqD5Ev,comdat
.align 2
.weak _ZN3ops3SeqD0Ev
.type _ZN3ops3SeqD0Ev, @function
_ZN3ops3SeqD0Ev:
.LFB5661:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
leaq 16+_ZTVN3ops2OpE(%rip), %rax
movq %rax, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .L10
movq 104(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L10:
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .L11
movq 80(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L11:
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .L12
movq 56(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L12:
movq 8(%rbx), %rdi
leaq 24(%rbx), %rax
cmpq %rax, %rdi
je .L13
movq 24(%rbx), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L13:
movl $112, %esi
movq %rbx, %rdi
call _ZdlPvm@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5661:
.size _ZN3ops3SeqD0Ev, .-_ZN3ops3SeqD0Ev
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4662:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4662:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev,"axG",@progbits,_ZNSt6vectorIPN2rt4NodeESaIS2_EED5Ev,comdat
.align 2
.weak _ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev
.type _ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev, @function
_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev:
.LFB4966:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L20
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L20:
ret
.cfi_endproc
.LFE4966:
.size _ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev, .-_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev
.weak _ZNSt6vectorIPN2rt4NodeESaIS2_EED1Ev
.set _ZNSt6vectorIPN2rt4NodeESaIS2_EED1Ev,_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev
.section .text._ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev,"axG",@progbits,_ZNSt6vectorIPN3ops2OpESaIS2_EED5Ev,comdat
.align 2
.weak _ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev
.type _ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev, @function
_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev:
.LFB4994:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L26
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L26:
ret
.cfi_endproc
.LFE4994:
.size _ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev, .-_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev
.weak _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
.set _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev,_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev
.text
.align 2
.globl _ZN3ops3SeqC2ESt6vectorIPNS_2OpESaIS3_EE
.type _ZN3ops3SeqC2ESt6vectorIPNS_2OpESaIS3_EE, @function
_ZN3ops3SeqC2ESt6vectorIPNS_2OpESaIS3_EE:
.LFB4615:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4615
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $112, %rsp
.cfi_def_cfa_offset 160
movq %rdi, %r12
movq %rsi, %r13
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq $0, 32(%rsp)
movq $0, 40(%rsp)
movq $0, 48(%rsp)
movq 8(%rsi), %rax
movq $0, (%rsp)
movq $0, 8(%rsp)
movq $0, 16(%rsp)
subq (%rsi), %rax
movq %rax, %rbp
je .L43
movabsq $9223372036854775800, %rax
cmpq %rbp, %rax
jb .L49
movq %rbp, %rdi
.LEHB0:
call _Znwm@PLT
jmp .L50
.L49:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L51
call _ZSt28__throw_bad_array_new_lengthv@PLT
.LEHE0:
.L44:
endbr64
movq %rax, %rbx
jmp .L40
.L51:
call __stack_chk_fail@PLT
.L50:
movq %rax, %rbx
.L30:
movq %rbx, (%rsp)
movq %rbx, 8(%rsp)
leaq (%rbx,%rbp), %rax
movq %rax, 16(%rsp)
movq 8(%r13), %r14
movq 0(%r13), %rsi
movq %r14, %rbp
subq %rsi, %rbp
cmpq $8, %rbp
jle .L33
movq %rbp, %rdx
movq %rbx, %rdi
call memmove@PLT
.L34:
addq %rbp, %rbx
movq %rbx, 8(%rsp)
movq -8(%r14), %rdi
.LEHB1:
call _ZNK3ops2Op9shape_getEv@PLT
.LEHE1:
jmp .L52
.L43:
movl $0, %ebx
jmp .L30
.L33:
jne .L34
movq (%rsi), %rax
movq %rax, (%rbx)
jmp .L34
.L52:
movq %rax, %rdx
leaq 64(%rsp), %rsi
leaq 80(%rsp), %rax
movq %rax, 64(%rsp)
movw $25971, 80(%rsp)
movb $113, 82(%rsp)
movq $3, 72(%rsp)
movb $0, 83(%rsp)
movq %rsp, %rcx
leaq 32(%rsp), %r8
movq %r12, %rdi
.LEHB2:
call _ZN3ops2OpC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERKNS_5ShapeESt6vectorIPS0_SaISD_EESF_@PLT
.LEHE2:
movq 64(%rsp), %rdi
leaq 80(%rsp), %rax
cmpq %rax, %rdi
je .L35
movq 80(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L35:
movq (%rsp), %rdi
testq %rdi, %rdi
je .L36
movq 16(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L36:
movq 32(%rsp), %rdi
testq %rdi, %rdi
je .L37
movq 48(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L37:
leaq 16+_ZTVN3ops3SeqE(%rip), %rax
movq %rax, (%r12)
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L53
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L39:
movq %rsp, %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
.L40:
leaq 32(%rsp), %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L41
call __stack_chk_fail@PLT
.L45:
endbr64
movq %rax, %rbx
jmp .L39
.L41:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L53:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4615:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4615:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4615-.LLSDACSB4615
.LLSDACSB4615:
.uleb128 .LEHB0-.LFB4615
.uleb128 .LEHE0-.LEHB0
.uleb128 .L44-.LFB4615
.uleb128 0
.uleb128 .LEHB1-.LFB4615
.uleb128 .LEHE1-.LEHB1
.uleb128 .L45-.LFB4615
.uleb128 0
.uleb128 .LEHB2-.LFB4615
.uleb128 .LEHE2-.LEHB2
.uleb128 .L46-.LFB4615
.uleb128 0
.uleb128 .LEHB3-.LFB4615
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.LLSDACSE4615:
.text
.size _ZN3ops3SeqC2ESt6vectorIPNS_2OpESaIS3_EE, .-_ZN3ops3SeqC2ESt6vectorIPNS_2OpESaIS3_EE
.globl _ZN3ops3SeqC1ESt6vectorIPNS_2OpESaIS3_EE
.set _ZN3ops3SeqC1ESt6vectorIPNS_2OpESaIS3_EE,_ZN3ops3SeqC2ESt6vectorIPNS_2OpESaIS3_EE
.section .rodata._ZNSt6vectorIPN2rt4NodeESaIS2_EE17_M_realloc_insertIJRKS2_EEEvN9__gnu_cxx17__normal_iteratorIPS2_S4_EEDpOT_.str1.1,"aMS",@progbits,1
.LC0:
.string "vector::_M_realloc_insert"
.section .text._ZNSt6vectorIPN2rt4NodeESaIS2_EE17_M_realloc_insertIJRKS2_EEEvN9__gnu_cxx17__normal_iteratorIPS2_S4_EEDpOT_,"axG",@progbits,_ZNSt6vectorIPN2rt4NodeESaIS2_EE17_M_realloc_insertIJRKS2_EEEvN9__gnu_cxx17__normal_iteratorIPS2_S4_EEDpOT_,comdat
.align 2
.weak _ZNSt6vectorIPN2rt4NodeESaIS2_EE17_M_realloc_insertIJRKS2_EEEvN9__gnu_cxx17__normal_iteratorIPS2_S4_EEDpOT_
.type _ZNSt6vectorIPN2rt4NodeESaIS2_EE17_M_realloc_insertIJRKS2_EEEvN9__gnu_cxx17__normal_iteratorIPS2_S4_EEDpOT_, @function
_ZNSt6vectorIPN2rt4NodeESaIS2_EE17_M_realloc_insertIJRKS2_EEEvN9__gnu_cxx17__normal_iteratorIPS2_S4_EEDpOT_:
.LFB5259:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, (%rsp)
movq %rdx, 8(%rsp)
movq 8(%rdi), %rbp
movq (%rdi), %r13
movq %rbp, %rax
subq %r13, %rax
sarq $3, %rax
movabsq $1152921504606846975, %rdx
cmpq %rdx, %rax
je .L71
movq %rdi, %rbx
cmpq %r13, %rbp
movl $1, %edx
cmovne %rax, %rdx
addq %rdx, %rax
jc .L57
movabsq $1152921504606846975, %r14
cmpq %r14, %rax
cmovbe %rax, %r14
movq (%rsp), %r15
subq %r13, %r15
movl $0, %r12d
testq %rax, %rax
je .L58
jmp .L65
.L71:
leaq .LC0(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L72:
movq %r15, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memmove@PLT
leaq 8(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jg .L60
addq %rbp, %r15
movq 16(%rbx), %rsi
subq %r13, %rsi
jmp .L64
.L57:
movq (%rsp), %r15
subq %r13, %r15
movabsq $1152921504606846975, %r14
.L65:
leaq 0(,%r14,8), %rdi
call _Znwm@PLT
movq %rax, %r12
.L58:
movq 8(%rsp), %rax
movq (%rax), %rax
movq %rax, (%r12,%r15)
testq %r15, %r15
jg .L72
leaq 8(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jle .L62
.L60:
movq %rbp, %rdx
movq (%rsp), %rsi
movq %r15, %rdi
call memcpy@PLT
.L62:
addq %rbp, %r15
testq %r13, %r13
je .L63
movq 16(%rbx), %rsi
subq %r13, %rsi
.L64:
movq %r13, %rdi
call _ZdlPvm@PLT
.L63:
movq %r12, (%rbx)
movq %r15, 8(%rbx)
leaq (%r12,%r14,8), %rax
movq %rax, 16(%rbx)
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5259:
.size _ZNSt6vectorIPN2rt4NodeESaIS2_EE17_M_realloc_insertIJRKS2_EEEvN9__gnu_cxx17__normal_iteratorIPS2_S4_EEDpOT_, .-_ZNSt6vectorIPN2rt4NodeESaIS2_EE17_M_realloc_insertIJRKS2_EEEvN9__gnu_cxx17__normal_iteratorIPS2_S4_EEDpOT_
.text
.align 2
.globl _ZN3ops3Seq7compileEv
.type _ZN3ops3Seq7compileEv, @function
_ZN3ops3Seq7compileEv:
.LFB4617:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4617
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $120, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %rdi, %r14
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
.LEHB4:
call _ZN3ops5Graph8instanceEv@PLT
movq %rax, %rbx
movq %rax, -152(%rbp)
leaq -80(%rbp), %rdi
movq %r14, %rsi
call _ZN3ops2Op5predsEv@PLT
.LEHE4:
movq -72(%rbp), %rax
movq -8(%rax), %rsi
movq %rbx, %rdi
.LEHB5:
call _ZN3ops5Graph8compiledEPNS_2OpE@PLT
.LEHE5:
movq %rax, %r13
movq -80(%rbp), %rdi
testq %rdi, %rdi
je .L74
movq -64(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L74:
movq $0, -144(%rbp)
movq $0, -136(%rbp)
movq $0, -128(%rbp)
leaq -80(%rbp), %rdi
movq %r14, %rsi
.LEHB6:
call _ZN3ops2Op5predsEv@PLT
.LEHE6:
movq -80(%rbp), %rbx
movq -72(%rbp), %r12
cmpq %r12, %rbx
je .L75
leaq -144(%rbp), %r15
jmp .L78
.L103:
movq -136(%rbp), %rsi
cmpq -128(%rbp), %rsi
je .L76
movq 56(%rax), %rax
movq %rax, (%rsi)
addq $8, -136(%rbp)
.L77:
addq $8, %rbx
cmpq %rbx, %r12
je .L75
.L78:
movq (%rbx), %rsi
movq -152(%rbp), %rdi
.LEHB7:
call _ZN3ops5Graph8compiledEPNS_2OpE@PLT
jmp .L103
.L76:
leaq 56(%rax), %rdx
movq %r15, %rdi
call _ZNSt6vectorIPN2rt4NodeESaIS2_EE17_M_realloc_insertIJRKS2_EEEvN9__gnu_cxx17__normal_iteratorIPS2_S4_EEDpOT_
.LEHE7:
jmp .L77
.L75:
movq -80(%rbp), %rdi
testq %rdi, %rdi
je .L79
movq -64(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L79:
leaq -144(%rbp), %rdi
.LEHB8:
call _ZN2rt4Node3nopERKSt6vectorIPS0_SaIS2_EE@PLT
.LEHE8:
movq %rax, %rbx
movq 88(%r13), %r12
addq $64, %r13
movq $0, -80(%rbp)
movq $0, -72(%rbp)
movq $0, -64(%rbp)
movq $0, -112(%rbp)
movq $0, -104(%rbp)
movq $0, -96(%rbp)
movl $8, %edi
.LEHB9:
call _Znwm@PLT
.LEHE9:
movq %rax, -112(%rbp)
leaq 8(%rax), %rdx
movq %rdx, -96(%rbp)
movq %rbx, (%rax)
movq %rdx, -104(%rbp)
leaq -80(%rbp), %rcx
leaq -112(%rbp), %rdx
subq $8, %rsp
pushq %r12
movq %r13, %r9
movq %rbx, %r8
movq %r14, %rsi
movq -152(%rbp), %rdi
.LEHB10:
.cfi_escape 0x2e,0x10
call _ZN3ops5Graph12add_compiledEPNS_2OpESt6vectorIPN2rt4NodeESaIS6_EES3_IPfSaIS9_EES6_RKNS_5ShapeES9_@PLT
.LEHE10:
addq $16, %rsp
movq -112(%rbp), %rdi
testq %rdi, %rdi
je .L84
movq -96(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L84:
movq -80(%rbp), %rdi
testq %rdi, %rdi
je .L85
movq -64(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L85:
movq -144(%rbp), %rdi
testq %rdi, %rdi
je .L73
movq -128(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L73:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L104
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L99:
.cfi_restore_state
endbr64
movq %rax, %rbx
movq -112(%rbp), %rdi
movq -96(%rbp), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L83
call _ZdlPvm@PLT
.L83:
movq -80(%rbp), %rdi
movq -64(%rbp), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L90
call _ZdlPvm@PLT
jmp .L90
.L95:
endbr64
movq %rax, %rbx
leaq -80(%rbp), %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L88
call __stack_chk_fail@PLT
.L88:
movq %rbx, %rdi
.LEHB11:
call _Unwind_Resume@PLT
.L96:
endbr64
movq %rax, %rbx
leaq -80(%rbp), %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
.L90:
leaq -144(%rbp), %rdi
call _ZNSt6vectorIPN2rt4NodeESaIS2_EED1Ev
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L93
call __stack_chk_fail@PLT
.L98:
endbr64
movq %rax, %rbx
leaq -112(%rbp), %rdi
call _ZNSt6vectorIPN2rt4NodeESaIS2_EED1Ev
jmp .L83
.L97:
endbr64
movq %rax, %rbx
jmp .L90
.L93:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE11:
.L104:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4617:
.section .gcc_except_table
.LLSDA4617:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4617-.LLSDACSB4617
.LLSDACSB4617:
.uleb128 .LEHB4-.LFB4617
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.uleb128 .LEHB5-.LFB4617
.uleb128 .LEHE5-.LEHB5
.uleb128 .L95-.LFB4617
.uleb128 0
.uleb128 .LEHB6-.LFB4617
.uleb128 .LEHE6-.LEHB6
.uleb128 .L97-.LFB4617
.uleb128 0
.uleb128 .LEHB7-.LFB4617
.uleb128 .LEHE7-.LEHB7
.uleb128 .L96-.LFB4617
.uleb128 0
.uleb128 .LEHB8-.LFB4617
.uleb128 .LEHE8-.LEHB8
.uleb128 .L97-.LFB4617
.uleb128 0
.uleb128 .LEHB9-.LFB4617
.uleb128 .LEHE9-.LEHB9
.uleb128 .L99-.LFB4617
.uleb128 0
.uleb128 .LEHB10-.LFB4617
.uleb128 .LEHE10-.LEHB10
.uleb128 .L98-.LFB4617
.uleb128 0
.uleb128 .LEHB11-.LFB4617
.uleb128 .LEHE11-.LEHB11
.uleb128 0
.uleb128 0
.LLSDACSE4617:
.text
.size _ZN3ops3Seq7compileEv, .-_ZN3ops3Seq7compileEv
.weak _ZTSN3ops3SeqE
.section .rodata._ZTSN3ops3SeqE,"aG",@progbits,_ZTSN3ops3SeqE,comdat
.align 8
.type _ZTSN3ops3SeqE, @object
.size _ZTSN3ops3SeqE, 11
_ZTSN3ops3SeqE:
.string "N3ops3SeqE"
.weak _ZTIN3ops3SeqE
.section .data.rel.ro._ZTIN3ops3SeqE,"awG",@progbits,_ZTIN3ops3SeqE,comdat
.align 8
.type _ZTIN3ops3SeqE, @object
.size _ZTIN3ops3SeqE, 24
_ZTIN3ops3SeqE:
.quad _ZTVN10__cxxabiv120__si_class_type_infoE+16
.quad _ZTSN3ops3SeqE
.quad _ZTIN3ops2OpE
.weak _ZTVN3ops3SeqE
.section .data.rel.ro._ZTVN3ops3SeqE,"awG",@progbits,_ZTVN3ops3SeqE,comdat
.align 8
.type _ZTVN3ops3SeqE, @object
.size _ZTVN3ops3SeqE, 48
_ZTVN3ops3SeqE:
.quad 0
.quad _ZTIN3ops3SeqE
.quad _ZN3ops3SeqD1Ev
.quad _ZN3ops3SeqD0Ev
.quad _ZN3ops3Seq7compileEv
.quad _ZN3ops2Op10child_gradEmPS0_
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "seq.hh"
#include <cassert>
#include <stdexcept>
#include "graph.hh"
#include "mse-grad.hh"
#include "ops-builder.hh"
#include "../runtime/node.hh"
#include "../memory/alloc.hh"
namespace ops
{
Seq::Seq(std::vector<Op*> ops)
: Op("seq", ops.back()->shape_get(), ops)
{}
void Seq::compile()
{
auto& g = Graph::instance();
auto& clast = g.compiled(preds().back());
std::vector<rt::Node*> nodes;
for (auto p : preds())
nodes.push_back(g.compiled(p).out_node);
auto out_node = rt::Node::nop(nodes);
g.add_compiled(this, {out_node}, {}, out_node, clast.out_shape, clast.out_data);
}
} | #include <hip/hip_runtime.h>
#include "seq.hh"
#include <cassert>
#include <stdexcept>
#include "graph.hh"
#include "mse-grad.hh"
#include "ops-builder.hh"
#include "../runtime/node.hh"
#include "../memory/alloc.hh"
namespace ops
{
Seq::Seq(std::vector<Op*> ops)
: Op("seq", ops.back()->shape_get(), ops)
{}
void Seq::compile()
{
auto& g = Graph::instance();
auto& clast = g.compiled(preds().back());
std::vector<rt::Node*> nodes;
for (auto p : preds())
nodes.push_back(g.compiled(p).out_node);
auto out_node = rt::Node::nop(nodes);
g.add_compiled(this, {out_node}, {}, out_node, clast.out_shape, clast.out_data);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "seq.hh"
#include <cassert>
#include <stdexcept>
#include "graph.hh"
#include "mse-grad.hh"
#include "ops-builder.hh"
#include "../runtime/node.hh"
#include "../memory/alloc.hh"
namespace ops
{
Seq::Seq(std::vector<Op*> ops)
: Op("seq", ops.back()->shape_get(), ops)
{}
void Seq::compile()
{
auto& g = Graph::instance();
auto& clast = g.compiled(preds().back());
std::vector<rt::Node*> nodes;
for (auto p : preds())
nodes.push_back(g.compiled(p).out_node);
auto out_node = rt::Node::nop(nodes);
g.add_compiled(this, {out_node}, {}, out_node, clast.out_shape, clast.out_data);
}
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "seq.hh"
#include <cassert>
#include <stdexcept>
#include "graph.hh"
#include "mse-grad.hh"
#include "ops-builder.hh"
#include "../runtime/node.hh"
#include "../memory/alloc.hh"
namespace ops
{
Seq::Seq(std::vector<Op*> ops)
: Op("seq", ops.back()->shape_get(), ops)
{}
void Seq::compile()
{
auto& g = Graph::instance();
auto& clast = g.compiled(preds().back());
std::vector<rt::Node*> nodes;
for (auto p : preds())
nodes.push_back(g.compiled(p).out_node);
auto out_node = rt::Node::nop(nodes);
g.add_compiled(this, {out_node}, {}, out_node, clast.out_shape, clast.out_data);
}
} | .text
.file "seq.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _ZN3ops3SeqC2ESt6vectorIPNS_2OpESaIS3_EE # -- Begin function _ZN3ops3SeqC2ESt6vectorIPNS_2OpESaIS3_EE
.p2align 4, 0x90
.type _ZN3ops3SeqC2ESt6vectorIPNS_2OpESaIS3_EE,@function
_ZN3ops3SeqC2ESt6vectorIPNS_2OpESaIS3_EE: # @_ZN3ops3SeqC2ESt6vectorIPNS_2OpESaIS3_EE
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $88, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r15
movq %rdi, %rbx
leaq 48(%rsp), %rax
movq %rax, 32(%rsp)
movl $7431539, 48(%rsp) # imm = 0x716573
movq $3, 40(%rsp)
movq 8(%rsi), %rax
movq -8(%rax), %rdi
.Ltmp0:
callq _ZNK3ops2Op9shape_getEv
.Ltmp1:
# %bb.1:
movq %rax, %r14
movq (%r15), %r12
movq 8(%r15), %rbp
movq %rbp, %r15
subq %r12, %r15
sarq $3, %r15
xorps %xmm0, %xmm0
movaps %xmm0, (%rsp)
movq $0, 16(%rsp)
subq %r12, %rbp
je .LBB0_2
# %bb.3:
movq %r15, %rax
shrq $60, %rax
jne .LBB0_4
# %bb.9: # %_ZNSt16allocator_traitsISaIPN3ops2OpEEE8allocateERS3_m.exit.i.i.i.i
.Ltmp2:
movq %rbp, %rdi
callq _Znwm
.Ltmp3:
# %bb.10:
movq %rax, %r13
jmp .LBB0_11
.LBB0_2:
xorl %r13d, %r13d
.LBB0_11: # %_ZNSt12_Vector_baseIPN3ops2OpESaIS2_EEC2EmRKS3_.exit.i
movq %r13, (%rsp)
movq %r13, 8(%rsp)
leaq (,%r15,8), %rax
addq %r13, %rax
movq %rax, 16(%rsp)
cmpq $9, %rbp
jl .LBB0_13
# %bb.12:
movq %r13, %rdi
movq %r12, %rsi
movq %rbp, %rdx
callq memmove@PLT
.LBB0_15: # %_ZNSt6vectorIPN3ops2OpESaIS2_EEC2ERKS4_.exit
addq %rbp, %r13
movq %r13, 8(%rsp)
xorps %xmm0, %xmm0
movaps %xmm0, 64(%rsp)
movq $0, 80(%rsp)
.Ltmp9:
leaq 32(%rsp), %rsi
movq %rsp, %rcx
leaq 64(%rsp), %r8
movq %rbx, %rdi
movq %r14, %rdx
callq _ZN3ops2OpC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERKNS_5ShapeESt6vectorIPS0_SaISD_EESF_
.Ltmp10:
# %bb.16:
movq 64(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_18
# %bb.17:
callq _ZdlPv
.LBB0_18: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit
movq (%rsp), %rdi
testq %rdi, %rdi
je .LBB0_20
# %bb.19:
callq _ZdlPv
.LBB0_20: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit12
movq 32(%rsp), %rdi
leaq 48(%rsp), %rax
cmpq %rax, %rdi
je .LBB0_22
# %bb.21: # %.critedge.i.i
callq _ZdlPv
.LBB0_22: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
movq $_ZTVN3ops3SeqE+16, (%rbx)
addq $88, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_13:
.cfi_def_cfa_offset 144
cmpq $8, %rbp
jne .LBB0_15
# %bb.14:
movq (%r12), %rax
movq %rax, (%r13)
jmp .LBB0_15
.LBB0_4:
shrq $61, %r15
je .LBB0_7
# %bb.5: # %.noexc.i.i
.Ltmp6:
callq _ZSt28__throw_bad_array_new_lengthv
.Ltmp7:
# %bb.6: # %.noexc8
.LBB0_7: # %.noexc4.i.i
.Ltmp4:
callq _ZSt17__throw_bad_allocv
.Ltmp5:
# %bb.8: # %.noexc9
.LBB0_24:
.Ltmp11:
movq %rax, %rbx
movq 64(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_26
# %bb.25:
callq _ZdlPv
.LBB0_26: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit14
movq (%rsp), %rdi
testq %rdi, %rdi
je .LBB0_28
# %bb.27:
callq _ZdlPv
jmp .LBB0_28
.LBB0_23:
.Ltmp8:
movq %rax, %rbx
.LBB0_28: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit16
movq 32(%rsp), %rdi
leaq 48(%rsp), %rax
cmpq %rax, %rdi
je .LBB0_30
# %bb.29: # %.critedge.i.i17
callq _ZdlPv
.LBB0_30: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit19
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end0:
.size _ZN3ops3SeqC2ESt6vectorIPNS_2OpESaIS3_EE, .Lfunc_end0-_ZN3ops3SeqC2ESt6vectorIPNS_2OpESaIS3_EE
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table0:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp3-.Ltmp0 # Call between .Ltmp0 and .Ltmp3
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp9-.Ltmp3 # Call between .Ltmp3 and .Ltmp9
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp5-.Ltmp6 # Call between .Ltmp6 and .Ltmp5
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp5-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Lfunc_end0-.Ltmp5 # Call between .Ltmp5 and .Lfunc_end0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _ZN3ops3Seq7compileEv
.LCPI1_0:
.zero 16
.text
.globl _ZN3ops3Seq7compileEv
.p2align 4, 0x90
.type _ZN3ops3Seq7compileEv,@function
_ZN3ops3Seq7compileEv: # @_ZN3ops3Seq7compileEv
.Lfunc_begin1:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception1
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
callq _ZN3ops5Graph8instanceEv
movq %rax, %r14
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq _ZN3ops2Op5predsEv
movq 24(%rsp), %rax
movq -8(%rax), %rsi
.Ltmp12:
movq %r14, 72(%rsp) # 8-byte Spill
movq %r14, %rdi
callq _ZN3ops5Graph8compiledEPNS_2OpE
movq %rax, 80(%rsp) # 8-byte Spill
.Ltmp13:
# %bb.1:
movq 16(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_3
# %bb.2:
callq _ZdlPv
.LBB1_3: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit
xorps %xmm0, %xmm0
movaps %xmm0, 16(%rsp)
movq $0, 32(%rsp)
.Ltmp15:
leaq 144(%rsp), %rdi
movq %rbx, 88(%rsp) # 8-byte Spill
movq %rbx, %rsi
callq _ZN3ops2Op5predsEv
.Ltmp16:
# %bb.4:
movq 144(%rsp), %r15
movq 152(%rsp), %rax
movq %rax, 104(%rsp) # 8-byte Spill
cmpq %rax, %r15
jne .LBB1_19
.LBB1_5: # %._crit_edge
movq 144(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_7
# %bb.6:
callq _ZdlPv
.LBB1_7: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit24
.Ltmp26:
leaq 16(%rsp), %rdi
callq _ZN2rt4Node3nopERKSt6vectorIPS0_SaIS2_EE
.Ltmp27:
movq 88(%rsp), %rbx # 8-byte Reload
# %bb.8:
movq %rax, %r12
xorps %xmm0, %xmm0
movaps %xmm0, 48(%rsp)
movq $0, 64(%rsp)
.Ltmp29:
movl $8, %edi
callq _Znwm
.Ltmp30:
# %bb.9: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EEC2ESt16initializer_listIS2_ERKS3_.exit
movq %rax, 48(%rsp)
movq %rax, %rcx
addq $8, %rcx
movq %rcx, 64(%rsp)
movq %r12, (%rax)
movq %rcx, 56(%rsp)
movq 80(%rsp), %rax # 8-byte Reload
movq %rax, %r9
addq $64, %r9
xorps %xmm0, %xmm0
movaps %xmm0, 112(%rsp)
movq $0, 128(%rsp)
movq 88(%rax), %rax
.Ltmp32:
movq %rax, (%rsp)
leaq 48(%rsp), %rdx
leaq 112(%rsp), %rcx
movq 72(%rsp), %rdi # 8-byte Reload
movq %rbx, %rsi
movq %r12, %r8
callq _ZN3ops5Graph12add_compiledEPNS_2OpESt6vectorIPN2rt4NodeESaIS6_EES3_IPfSaIS9_EES6_RKNS_5ShapeES9_
.Ltmp33:
# %bb.10:
movq 112(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_12
# %bb.11:
callq _ZdlPv
.LBB1_12: # %_ZNSt6vectorIPfSaIS0_EED2Ev.exit
movq 48(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_14
# %bb.13:
callq _ZdlPv
.LBB1_14: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev.exit
movq 16(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_16
# %bb.15:
callq _ZdlPv
.LBB1_16: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev.exit37
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.p2align 4, 0x90
.LBB1_21: # in Loop: Header=BB1_19 Depth=1
.cfi_def_cfa_offset 224
movq 56(%rax), %rax
movq %rax, (%r12)
addq $8, 24(%rsp)
.LBB1_33: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EE9push_backERKS2_.exit
# in Loop: Header=BB1_19 Depth=1
addq $8, %r15
cmpq 104(%rsp), %r15 # 8-byte Folded Reload
je .LBB1_5
.LBB1_19: # =>This Inner Loop Header: Depth=1
movq (%r15), %rsi
.Ltmp18:
movq 72(%rsp), %rdi # 8-byte Reload
callq _ZN3ops5Graph8compiledEPNS_2OpE
.Ltmp19:
# %bb.20: # in Loop: Header=BB1_19 Depth=1
movq 24(%rsp), %r12
cmpq 32(%rsp), %r12
jne .LBB1_21
# %bb.22: # in Loop: Header=BB1_19 Depth=1
movq 16(%rsp), %r13
subq %r13, %r12
movabsq $9223372036854775800, %rcx # imm = 0x7FFFFFFFFFFFFFF8
cmpq %rcx, %r12
je .LBB1_23
# %bb.25: # %_ZNKSt6vectorIPN2rt4NodeESaIS2_EE12_M_check_lenEmPKc.exit.i.i
# in Loop: Header=BB1_19 Depth=1
movq %r12, %rbx
sarq $3, %rbx
cmpq $1, %rbx
movq %rbx, %rcx
adcq $0, %rcx
leaq (%rcx,%rbx), %r14
movabsq $1152921504606846975, %rdx # imm = 0xFFFFFFFFFFFFFFF
cmpq %rdx, %r14
cmovaeq %rdx, %r14
addq %rbx, %rcx
cmovbq %rdx, %r14
testq %r14, %r14
je .LBB1_26
# %bb.27: # in Loop: Header=BB1_19 Depth=1
leaq (,%r14,8), %rdi
.Ltmp20:
movq %rax, 96(%rsp) # 8-byte Spill
callq _Znwm
movq %rax, %rbp
movq 96(%rsp), %rax # 8-byte Reload
.Ltmp21:
jmp .LBB1_28
.LBB1_26: # in Loop: Header=BB1_19 Depth=1
xorl %ebp, %ebp
.LBB1_28: # %_ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EE11_M_allocateEm.exit.i.i
# in Loop: Header=BB1_19 Depth=1
movq 56(%rax), %rax
movq %rax, (%rbp,%rbx,8)
testq %r12, %r12
jle .LBB1_30
# %bb.29: # in Loop: Header=BB1_19 Depth=1
movq %rbp, %rdi
movq %r13, %rsi
movq %r12, %rdx
callq memmove@PLT
.LBB1_30: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EE11_S_relocateEPS2_S5_S5_RS3_.exit.i.i
# in Loop: Header=BB1_19 Depth=1
testq %r13, %r13
je .LBB1_32
# %bb.31: # in Loop: Header=BB1_19 Depth=1
movq %r13, %rdi
callq _ZdlPv
.LBB1_32: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EE17_M_realloc_insertIJRKS2_EEEvN9__gnu_cxx17__normal_iteratorIPS2_S4_EEDpOT_.exit.i
# in Loop: Header=BB1_19 Depth=1
leaq (%r12,%rbp), %rax
addq $8, %rax
movq %rbp, 16(%rsp)
movq %rax, 24(%rsp)
leaq (,%r14,8), %rax
addq %rbp, %rax
movq %rax, 32(%rsp)
jmp .LBB1_33
.LBB1_23:
.Ltmp23:
movl $.L.str.3, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp24:
# %bb.24: # %.noexc
.LBB1_39:
.Ltmp34:
movq %rax, %rbx
movq 112(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_41
# %bb.40:
callq _ZdlPv
jmp .LBB1_41
.LBB1_37:
.Ltmp31:
movq %rax, %rbx
.LBB1_41: # %_ZNSt6vectorIPfSaIS0_EED2Ev.exit39
movq 48(%rsp), %rdi
jmp .LBB1_42
.LBB1_38:
.Ltmp28:
movq %rax, %rbx
jmp .LBB1_44
.LBB1_18:
.Ltmp17:
movq %rax, %rbx
jmp .LBB1_44
.LBB1_17:
.Ltmp14:
movq %rax, %rbx
jmp .LBB1_44
.LBB1_35: # %.loopexit.split-lp
.Ltmp25:
jmp .LBB1_36
.LBB1_34: # %.loopexit
.Ltmp22:
.LBB1_36:
movq %rax, %rbx
movq 144(%rsp), %rdi
.LBB1_42: # %_ZNSt6vectorIPfSaIS0_EED2Ev.exit39
testq %rdi, %rdi
je .LBB1_44
# %bb.43:
callq _ZdlPv
.LBB1_44: # %.body
movq 16(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_46
# %bb.45:
callq _ZdlPv
.LBB1_46:
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size _ZN3ops3Seq7compileEv, .Lfunc_end1-_ZN3ops3Seq7compileEv
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception1:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end1-.Lcst_begin1
.Lcst_begin1:
.uleb128 .Lfunc_begin1-.Lfunc_begin1 # >> Call Site 1 <<
.uleb128 .Ltmp12-.Lfunc_begin1 # Call between .Lfunc_begin1 and .Ltmp12
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp12-.Lfunc_begin1 # >> Call Site 2 <<
.uleb128 .Ltmp13-.Ltmp12 # Call between .Ltmp12 and .Ltmp13
.uleb128 .Ltmp14-.Lfunc_begin1 # jumps to .Ltmp14
.byte 0 # On action: cleanup
.uleb128 .Ltmp15-.Lfunc_begin1 # >> Call Site 3 <<
.uleb128 .Ltmp16-.Ltmp15 # Call between .Ltmp15 and .Ltmp16
.uleb128 .Ltmp17-.Lfunc_begin1 # jumps to .Ltmp17
.byte 0 # On action: cleanup
.uleb128 .Ltmp26-.Lfunc_begin1 # >> Call Site 4 <<
.uleb128 .Ltmp27-.Ltmp26 # Call between .Ltmp26 and .Ltmp27
.uleb128 .Ltmp28-.Lfunc_begin1 # jumps to .Ltmp28
.byte 0 # On action: cleanup
.uleb128 .Ltmp29-.Lfunc_begin1 # >> Call Site 5 <<
.uleb128 .Ltmp30-.Ltmp29 # Call between .Ltmp29 and .Ltmp30
.uleb128 .Ltmp31-.Lfunc_begin1 # jumps to .Ltmp31
.byte 0 # On action: cleanup
.uleb128 .Ltmp32-.Lfunc_begin1 # >> Call Site 6 <<
.uleb128 .Ltmp33-.Ltmp32 # Call between .Ltmp32 and .Ltmp33
.uleb128 .Ltmp34-.Lfunc_begin1 # jumps to .Ltmp34
.byte 0 # On action: cleanup
.uleb128 .Ltmp18-.Lfunc_begin1 # >> Call Site 7 <<
.uleb128 .Ltmp21-.Ltmp18 # Call between .Ltmp18 and .Ltmp21
.uleb128 .Ltmp22-.Lfunc_begin1 # jumps to .Ltmp22
.byte 0 # On action: cleanup
.uleb128 .Ltmp21-.Lfunc_begin1 # >> Call Site 8 <<
.uleb128 .Ltmp23-.Ltmp21 # Call between .Ltmp21 and .Ltmp23
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp23-.Lfunc_begin1 # >> Call Site 9 <<
.uleb128 .Ltmp24-.Ltmp23 # Call between .Ltmp23 and .Ltmp24
.uleb128 .Ltmp25-.Lfunc_begin1 # jumps to .Ltmp25
.byte 0 # On action: cleanup
.uleb128 .Ltmp24-.Lfunc_begin1 # >> Call Site 10 <<
.uleb128 .Lfunc_end1-.Ltmp24 # Call between .Ltmp24 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end1:
.p2align 2, 0x0
# -- End function
.section .text._ZN3ops2OpD2Ev,"axG",@progbits,_ZN3ops2OpD2Ev,comdat
.weak _ZN3ops2OpD2Ev # -- Begin function _ZN3ops2OpD2Ev
.p2align 4, 0x90
.type _ZN3ops2OpD2Ev,@function
_ZN3ops2OpD2Ev: # @_ZN3ops2OpD2Ev
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq $_ZTVN3ops2OpE+16, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
callq _ZdlPv
.LBB2_2: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .LBB2_4
# %bb.3:
callq _ZdlPv
.LBB2_4: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit2
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .LBB2_6
# %bb.5:
callq _ZdlPv
.LBB2_6: # %_ZN3ops5ShapeD2Ev.exit
movq 8(%rbx), %rdi
addq $24, %rbx
cmpq %rbx, %rdi
je .LBB2_7
# %bb.8: # %.critedge.i.i
popq %rbx
.cfi_def_cfa_offset 8
jmp _ZdlPv # TAILCALL
.LBB2_7: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _ZN3ops2OpD2Ev, .Lfunc_end2-_ZN3ops2OpD2Ev
.cfi_endproc
# -- End function
.section .text._ZN3ops3SeqD0Ev,"axG",@progbits,_ZN3ops3SeqD0Ev,comdat
.weak _ZN3ops3SeqD0Ev # -- Begin function _ZN3ops3SeqD0Ev
.p2align 4, 0x90
.type _ZN3ops3SeqD0Ev,@function
_ZN3ops3SeqD0Ev: # @_ZN3ops3SeqD0Ev
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq $_ZTVN3ops2OpE+16, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
callq _ZdlPv
.LBB3_2: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit.i
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .LBB3_4
# %bb.3:
callq _ZdlPv
.LBB3_4: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit2.i
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .LBB3_6
# %bb.5:
callq _ZdlPv
.LBB3_6: # %_ZN3ops5ShapeD2Ev.exit.i
movq 8(%rbx), %rdi
leaq 24(%rbx), %rax
cmpq %rax, %rdi
je .LBB3_8
# %bb.7: # %.critedge.i.i.i
callq _ZdlPv
.LBB3_8: # %_ZN3ops2OpD2Ev.exit
movq %rbx, %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp _ZdlPv # TAILCALL
.Lfunc_end3:
.size _ZN3ops3SeqD0Ev, .Lfunc_end3-_ZN3ops3SeqD0Ev
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "seq"
.size .L.str, 4
.type _ZTVN3ops3SeqE,@object # @_ZTVN3ops3SeqE
.section .rodata,"a",@progbits
.globl _ZTVN3ops3SeqE
.p2align 3, 0x0
_ZTVN3ops3SeqE:
.quad 0
.quad _ZTIN3ops3SeqE
.quad _ZN3ops2OpD2Ev
.quad _ZN3ops3SeqD0Ev
.quad _ZN3ops3Seq7compileEv
.quad _ZN3ops2Op10child_gradEmPS0_
.size _ZTVN3ops3SeqE, 48
.type _ZTSN3ops3SeqE,@object # @_ZTSN3ops3SeqE
.globl _ZTSN3ops3SeqE
_ZTSN3ops3SeqE:
.asciz "N3ops3SeqE"
.size _ZTSN3ops3SeqE, 11
.type _ZTIN3ops3SeqE,@object # @_ZTIN3ops3SeqE
.globl _ZTIN3ops3SeqE
.p2align 3, 0x0
_ZTIN3ops3SeqE:
.quad _ZTVN10__cxxabiv120__si_class_type_infoE+16
.quad _ZTSN3ops3SeqE
.quad _ZTIN3ops2OpE
.size _ZTIN3ops3SeqE, 24
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "vector::_M_realloc_insert"
.size .L.str.3, 26
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.globl _ZN3ops3SeqC1ESt6vectorIPNS_2OpESaIS3_EE
.type _ZN3ops3SeqC1ESt6vectorIPNS_2OpESaIS3_EE,@function
.set _ZN3ops3SeqC1ESt6vectorIPNS_2OpESaIS3_EE, _ZN3ops3SeqC2ESt6vectorIPNS_2OpESaIS3_EE
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZTVN10__cxxabiv120__si_class_type_infoE
.addrsig_sym _ZTSN3ops3SeqE
.addrsig_sym _ZTIN3ops2OpE
.addrsig_sym _ZTIN3ops3SeqE
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00037ff4_00000000-6_seq.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4639:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4639:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .text._ZN3ops3SeqD2Ev,"axG",@progbits,_ZN3ops3SeqD5Ev,comdat
.align 2
.weak _ZN3ops3SeqD2Ev
.type _ZN3ops3SeqD2Ev, @function
_ZN3ops3SeqD2Ev:
.LFB5659:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
leaq 16+_ZTVN3ops2OpE(%rip), %rax
movq %rax, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .L4
movq 104(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L4:
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .L5
movq 80(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L5:
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .L6
movq 56(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L6:
movq 8(%rbx), %rdi
leaq 24(%rbx), %rax
cmpq %rax, %rdi
je .L3
movq 24(%rbx), %rsi
addq $1, %rsi
call _ZdlPvm@PLT
.L3:
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5659:
.size _ZN3ops3SeqD2Ev, .-_ZN3ops3SeqD2Ev
.weak _ZN3ops3SeqD1Ev
.set _ZN3ops3SeqD1Ev,_ZN3ops3SeqD2Ev
.section .text._ZN3ops3SeqD0Ev,"axG",@progbits,_ZN3ops3SeqD5Ev,comdat
.align 2
.weak _ZN3ops3SeqD0Ev
.type _ZN3ops3SeqD0Ev, @function
_ZN3ops3SeqD0Ev:
.LFB5661:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
leaq 16+_ZTVN3ops2OpE(%rip), %rax
movq %rax, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .L10
movq 104(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L10:
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .L11
movq 80(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L11:
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .L12
movq 56(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L12:
movq 8(%rbx), %rdi
leaq 24(%rbx), %rax
cmpq %rax, %rdi
je .L13
movq 24(%rbx), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L13:
movl $112, %esi
movq %rbx, %rdi
call _ZdlPvm@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5661:
.size _ZN3ops3SeqD0Ev, .-_ZN3ops3SeqD0Ev
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4662:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4662:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev,"axG",@progbits,_ZNSt6vectorIPN2rt4NodeESaIS2_EED5Ev,comdat
.align 2
.weak _ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev
.type _ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev, @function
_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev:
.LFB4966:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L20
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L20:
ret
.cfi_endproc
.LFE4966:
.size _ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev, .-_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev
.weak _ZNSt6vectorIPN2rt4NodeESaIS2_EED1Ev
.set _ZNSt6vectorIPN2rt4NodeESaIS2_EED1Ev,_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev
.section .text._ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev,"axG",@progbits,_ZNSt6vectorIPN3ops2OpESaIS2_EED5Ev,comdat
.align 2
.weak _ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev
.type _ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev, @function
_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev:
.LFB4994:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L26
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L26:
ret
.cfi_endproc
.LFE4994:
.size _ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev, .-_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev
.weak _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
.set _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev,_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev
.text
.align 2
.globl _ZN3ops3SeqC2ESt6vectorIPNS_2OpESaIS3_EE
.type _ZN3ops3SeqC2ESt6vectorIPNS_2OpESaIS3_EE, @function
_ZN3ops3SeqC2ESt6vectorIPNS_2OpESaIS3_EE:
.LFB4615:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4615
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $112, %rsp
.cfi_def_cfa_offset 160
movq %rdi, %r12
movq %rsi, %r13
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq $0, 32(%rsp)
movq $0, 40(%rsp)
movq $0, 48(%rsp)
movq 8(%rsi), %rax
movq $0, (%rsp)
movq $0, 8(%rsp)
movq $0, 16(%rsp)
subq (%rsi), %rax
movq %rax, %rbp
je .L43
movabsq $9223372036854775800, %rax
cmpq %rbp, %rax
jb .L49
movq %rbp, %rdi
.LEHB0:
call _Znwm@PLT
jmp .L50
.L49:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L51
call _ZSt28__throw_bad_array_new_lengthv@PLT
.LEHE0:
.L44:
endbr64
movq %rax, %rbx
jmp .L40
.L51:
call __stack_chk_fail@PLT
.L50:
movq %rax, %rbx
.L30:
movq %rbx, (%rsp)
movq %rbx, 8(%rsp)
leaq (%rbx,%rbp), %rax
movq %rax, 16(%rsp)
movq 8(%r13), %r14
movq 0(%r13), %rsi
movq %r14, %rbp
subq %rsi, %rbp
cmpq $8, %rbp
jle .L33
movq %rbp, %rdx
movq %rbx, %rdi
call memmove@PLT
.L34:
addq %rbp, %rbx
movq %rbx, 8(%rsp)
movq -8(%r14), %rdi
.LEHB1:
call _ZNK3ops2Op9shape_getEv@PLT
.LEHE1:
jmp .L52
.L43:
movl $0, %ebx
jmp .L30
.L33:
jne .L34
movq (%rsi), %rax
movq %rax, (%rbx)
jmp .L34
.L52:
movq %rax, %rdx
leaq 64(%rsp), %rsi
leaq 80(%rsp), %rax
movq %rax, 64(%rsp)
movw $25971, 80(%rsp)
movb $113, 82(%rsp)
movq $3, 72(%rsp)
movb $0, 83(%rsp)
movq %rsp, %rcx
leaq 32(%rsp), %r8
movq %r12, %rdi
.LEHB2:
call _ZN3ops2OpC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERKNS_5ShapeESt6vectorIPS0_SaISD_EESF_@PLT
.LEHE2:
movq 64(%rsp), %rdi
leaq 80(%rsp), %rax
cmpq %rax, %rdi
je .L35
movq 80(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L35:
movq (%rsp), %rdi
testq %rdi, %rdi
je .L36
movq 16(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L36:
movq 32(%rsp), %rdi
testq %rdi, %rdi
je .L37
movq 48(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L37:
leaq 16+_ZTVN3ops3SeqE(%rip), %rax
movq %rax, (%r12)
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L53
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L39:
movq %rsp, %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
.L40:
leaq 32(%rsp), %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L41
call __stack_chk_fail@PLT
.L45:
endbr64
movq %rax, %rbx
jmp .L39
.L41:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L53:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4615:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4615:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4615-.LLSDACSB4615
.LLSDACSB4615:
.uleb128 .LEHB0-.LFB4615
.uleb128 .LEHE0-.LEHB0
.uleb128 .L44-.LFB4615
.uleb128 0
.uleb128 .LEHB1-.LFB4615
.uleb128 .LEHE1-.LEHB1
.uleb128 .L45-.LFB4615
.uleb128 0
.uleb128 .LEHB2-.LFB4615
.uleb128 .LEHE2-.LEHB2
.uleb128 .L46-.LFB4615
.uleb128 0
.uleb128 .LEHB3-.LFB4615
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.LLSDACSE4615:
.text
.size _ZN3ops3SeqC2ESt6vectorIPNS_2OpESaIS3_EE, .-_ZN3ops3SeqC2ESt6vectorIPNS_2OpESaIS3_EE
.globl _ZN3ops3SeqC1ESt6vectorIPNS_2OpESaIS3_EE
.set _ZN3ops3SeqC1ESt6vectorIPNS_2OpESaIS3_EE,_ZN3ops3SeqC2ESt6vectorIPNS_2OpESaIS3_EE
.section .rodata._ZNSt6vectorIPN2rt4NodeESaIS2_EE17_M_realloc_insertIJRKS2_EEEvN9__gnu_cxx17__normal_iteratorIPS2_S4_EEDpOT_.str1.1,"aMS",@progbits,1
.LC0:
.string "vector::_M_realloc_insert"
.section .text._ZNSt6vectorIPN2rt4NodeESaIS2_EE17_M_realloc_insertIJRKS2_EEEvN9__gnu_cxx17__normal_iteratorIPS2_S4_EEDpOT_,"axG",@progbits,_ZNSt6vectorIPN2rt4NodeESaIS2_EE17_M_realloc_insertIJRKS2_EEEvN9__gnu_cxx17__normal_iteratorIPS2_S4_EEDpOT_,comdat
.align 2
.weak _ZNSt6vectorIPN2rt4NodeESaIS2_EE17_M_realloc_insertIJRKS2_EEEvN9__gnu_cxx17__normal_iteratorIPS2_S4_EEDpOT_
.type _ZNSt6vectorIPN2rt4NodeESaIS2_EE17_M_realloc_insertIJRKS2_EEEvN9__gnu_cxx17__normal_iteratorIPS2_S4_EEDpOT_, @function
_ZNSt6vectorIPN2rt4NodeESaIS2_EE17_M_realloc_insertIJRKS2_EEEvN9__gnu_cxx17__normal_iteratorIPS2_S4_EEDpOT_:
.LFB5259:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, (%rsp)
movq %rdx, 8(%rsp)
movq 8(%rdi), %rbp
movq (%rdi), %r13
movq %rbp, %rax
subq %r13, %rax
sarq $3, %rax
movabsq $1152921504606846975, %rdx
cmpq %rdx, %rax
je .L71
movq %rdi, %rbx
cmpq %r13, %rbp
movl $1, %edx
cmovne %rax, %rdx
addq %rdx, %rax
jc .L57
movabsq $1152921504606846975, %r14
cmpq %r14, %rax
cmovbe %rax, %r14
movq (%rsp), %r15
subq %r13, %r15
movl $0, %r12d
testq %rax, %rax
je .L58
jmp .L65
.L71:
leaq .LC0(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L72:
movq %r15, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memmove@PLT
leaq 8(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jg .L60
addq %rbp, %r15
movq 16(%rbx), %rsi
subq %r13, %rsi
jmp .L64
.L57:
movq (%rsp), %r15
subq %r13, %r15
movabsq $1152921504606846975, %r14
.L65:
leaq 0(,%r14,8), %rdi
call _Znwm@PLT
movq %rax, %r12
.L58:
movq 8(%rsp), %rax
movq (%rax), %rax
movq %rax, (%r12,%r15)
testq %r15, %r15
jg .L72
leaq 8(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jle .L62
.L60:
movq %rbp, %rdx
movq (%rsp), %rsi
movq %r15, %rdi
call memcpy@PLT
.L62:
addq %rbp, %r15
testq %r13, %r13
je .L63
movq 16(%rbx), %rsi
subq %r13, %rsi
.L64:
movq %r13, %rdi
call _ZdlPvm@PLT
.L63:
movq %r12, (%rbx)
movq %r15, 8(%rbx)
leaq (%r12,%r14,8), %rax
movq %rax, 16(%rbx)
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5259:
.size _ZNSt6vectorIPN2rt4NodeESaIS2_EE17_M_realloc_insertIJRKS2_EEEvN9__gnu_cxx17__normal_iteratorIPS2_S4_EEDpOT_, .-_ZNSt6vectorIPN2rt4NodeESaIS2_EE17_M_realloc_insertIJRKS2_EEEvN9__gnu_cxx17__normal_iteratorIPS2_S4_EEDpOT_
.text
.align 2
.globl _ZN3ops3Seq7compileEv
.type _ZN3ops3Seq7compileEv, @function
_ZN3ops3Seq7compileEv:
.LFB4617:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4617
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $120, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %rdi, %r14
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
.LEHB4:
call _ZN3ops5Graph8instanceEv@PLT
movq %rax, %rbx
movq %rax, -152(%rbp)
leaq -80(%rbp), %rdi
movq %r14, %rsi
call _ZN3ops2Op5predsEv@PLT
.LEHE4:
movq -72(%rbp), %rax
movq -8(%rax), %rsi
movq %rbx, %rdi
.LEHB5:
call _ZN3ops5Graph8compiledEPNS_2OpE@PLT
.LEHE5:
movq %rax, %r13
movq -80(%rbp), %rdi
testq %rdi, %rdi
je .L74
movq -64(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L74:
movq $0, -144(%rbp)
movq $0, -136(%rbp)
movq $0, -128(%rbp)
leaq -80(%rbp), %rdi
movq %r14, %rsi
.LEHB6:
call _ZN3ops2Op5predsEv@PLT
.LEHE6:
movq -80(%rbp), %rbx
movq -72(%rbp), %r12
cmpq %r12, %rbx
je .L75
leaq -144(%rbp), %r15
jmp .L78
.L103:
movq -136(%rbp), %rsi
cmpq -128(%rbp), %rsi
je .L76
movq 56(%rax), %rax
movq %rax, (%rsi)
addq $8, -136(%rbp)
.L77:
addq $8, %rbx
cmpq %rbx, %r12
je .L75
.L78:
movq (%rbx), %rsi
movq -152(%rbp), %rdi
.LEHB7:
call _ZN3ops5Graph8compiledEPNS_2OpE@PLT
jmp .L103
.L76:
leaq 56(%rax), %rdx
movq %r15, %rdi
call _ZNSt6vectorIPN2rt4NodeESaIS2_EE17_M_realloc_insertIJRKS2_EEEvN9__gnu_cxx17__normal_iteratorIPS2_S4_EEDpOT_
.LEHE7:
jmp .L77
.L75:
movq -80(%rbp), %rdi
testq %rdi, %rdi
je .L79
movq -64(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L79:
leaq -144(%rbp), %rdi
.LEHB8:
call _ZN2rt4Node3nopERKSt6vectorIPS0_SaIS2_EE@PLT
.LEHE8:
movq %rax, %rbx
movq 88(%r13), %r12
addq $64, %r13
movq $0, -80(%rbp)
movq $0, -72(%rbp)
movq $0, -64(%rbp)
movq $0, -112(%rbp)
movq $0, -104(%rbp)
movq $0, -96(%rbp)
movl $8, %edi
.LEHB9:
call _Znwm@PLT
.LEHE9:
movq %rax, -112(%rbp)
leaq 8(%rax), %rdx
movq %rdx, -96(%rbp)
movq %rbx, (%rax)
movq %rdx, -104(%rbp)
leaq -80(%rbp), %rcx
leaq -112(%rbp), %rdx
subq $8, %rsp
pushq %r12
movq %r13, %r9
movq %rbx, %r8
movq %r14, %rsi
movq -152(%rbp), %rdi
.LEHB10:
.cfi_escape 0x2e,0x10
call _ZN3ops5Graph12add_compiledEPNS_2OpESt6vectorIPN2rt4NodeESaIS6_EES3_IPfSaIS9_EES6_RKNS_5ShapeES9_@PLT
.LEHE10:
addq $16, %rsp
movq -112(%rbp), %rdi
testq %rdi, %rdi
je .L84
movq -96(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L84:
movq -80(%rbp), %rdi
testq %rdi, %rdi
je .L85
movq -64(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L85:
movq -144(%rbp), %rdi
testq %rdi, %rdi
je .L73
movq -128(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L73:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L104
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L99:
.cfi_restore_state
endbr64
movq %rax, %rbx
movq -112(%rbp), %rdi
movq -96(%rbp), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L83
call _ZdlPvm@PLT
.L83:
movq -80(%rbp), %rdi
movq -64(%rbp), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L90
call _ZdlPvm@PLT
jmp .L90
.L95:
endbr64
movq %rax, %rbx
leaq -80(%rbp), %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L88
call __stack_chk_fail@PLT
.L88:
movq %rbx, %rdi
.LEHB11:
call _Unwind_Resume@PLT
.L96:
endbr64
movq %rax, %rbx
leaq -80(%rbp), %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
.L90:
leaq -144(%rbp), %rdi
call _ZNSt6vectorIPN2rt4NodeESaIS2_EED1Ev
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L93
call __stack_chk_fail@PLT
.L98:
endbr64
movq %rax, %rbx
leaq -112(%rbp), %rdi
call _ZNSt6vectorIPN2rt4NodeESaIS2_EED1Ev
jmp .L83
.L97:
endbr64
movq %rax, %rbx
jmp .L90
.L93:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE11:
.L104:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4617:
.section .gcc_except_table
.LLSDA4617:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4617-.LLSDACSB4617
.LLSDACSB4617:
.uleb128 .LEHB4-.LFB4617
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.uleb128 .LEHB5-.LFB4617
.uleb128 .LEHE5-.LEHB5
.uleb128 .L95-.LFB4617
.uleb128 0
.uleb128 .LEHB6-.LFB4617
.uleb128 .LEHE6-.LEHB6
.uleb128 .L97-.LFB4617
.uleb128 0
.uleb128 .LEHB7-.LFB4617
.uleb128 .LEHE7-.LEHB7
.uleb128 .L96-.LFB4617
.uleb128 0
.uleb128 .LEHB8-.LFB4617
.uleb128 .LEHE8-.LEHB8
.uleb128 .L97-.LFB4617
.uleb128 0
.uleb128 .LEHB9-.LFB4617
.uleb128 .LEHE9-.LEHB9
.uleb128 .L99-.LFB4617
.uleb128 0
.uleb128 .LEHB10-.LFB4617
.uleb128 .LEHE10-.LEHB10
.uleb128 .L98-.LFB4617
.uleb128 0
.uleb128 .LEHB11-.LFB4617
.uleb128 .LEHE11-.LEHB11
.uleb128 0
.uleb128 0
.LLSDACSE4617:
.text
.size _ZN3ops3Seq7compileEv, .-_ZN3ops3Seq7compileEv
.weak _ZTSN3ops3SeqE
.section .rodata._ZTSN3ops3SeqE,"aG",@progbits,_ZTSN3ops3SeqE,comdat
.align 8
.type _ZTSN3ops3SeqE, @object
.size _ZTSN3ops3SeqE, 11
_ZTSN3ops3SeqE:
.string "N3ops3SeqE"
.weak _ZTIN3ops3SeqE
.section .data.rel.ro._ZTIN3ops3SeqE,"awG",@progbits,_ZTIN3ops3SeqE,comdat
.align 8
.type _ZTIN3ops3SeqE, @object
.size _ZTIN3ops3SeqE, 24
_ZTIN3ops3SeqE:
.quad _ZTVN10__cxxabiv120__si_class_type_infoE+16
.quad _ZTSN3ops3SeqE
.quad _ZTIN3ops2OpE
.weak _ZTVN3ops3SeqE
.section .data.rel.ro._ZTVN3ops3SeqE,"awG",@progbits,_ZTVN3ops3SeqE,comdat
.align 8
.type _ZTVN3ops3SeqE, @object
.size _ZTVN3ops3SeqE, 48
_ZTVN3ops3SeqE:
.quad 0
.quad _ZTIN3ops3SeqE
.quad _ZN3ops3SeqD1Ev
.quad _ZN3ops3SeqD0Ev
.quad _ZN3ops3Seq7compileEv
.quad _ZN3ops2Op10child_gradEmPS0_
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "seq.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _ZN3ops3SeqC2ESt6vectorIPNS_2OpESaIS3_EE # -- Begin function _ZN3ops3SeqC2ESt6vectorIPNS_2OpESaIS3_EE
.p2align 4, 0x90
.type _ZN3ops3SeqC2ESt6vectorIPNS_2OpESaIS3_EE,@function
_ZN3ops3SeqC2ESt6vectorIPNS_2OpESaIS3_EE: # @_ZN3ops3SeqC2ESt6vectorIPNS_2OpESaIS3_EE
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $88, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r15
movq %rdi, %rbx
leaq 48(%rsp), %rax
movq %rax, 32(%rsp)
movl $7431539, 48(%rsp) # imm = 0x716573
movq $3, 40(%rsp)
movq 8(%rsi), %rax
movq -8(%rax), %rdi
.Ltmp0:
callq _ZNK3ops2Op9shape_getEv
.Ltmp1:
# %bb.1:
movq %rax, %r14
movq (%r15), %r12
movq 8(%r15), %rbp
movq %rbp, %r15
subq %r12, %r15
sarq $3, %r15
xorps %xmm0, %xmm0
movaps %xmm0, (%rsp)
movq $0, 16(%rsp)
subq %r12, %rbp
je .LBB0_2
# %bb.3:
movq %r15, %rax
shrq $60, %rax
jne .LBB0_4
# %bb.9: # %_ZNSt16allocator_traitsISaIPN3ops2OpEEE8allocateERS3_m.exit.i.i.i.i
.Ltmp2:
movq %rbp, %rdi
callq _Znwm
.Ltmp3:
# %bb.10:
movq %rax, %r13
jmp .LBB0_11
.LBB0_2:
xorl %r13d, %r13d
.LBB0_11: # %_ZNSt12_Vector_baseIPN3ops2OpESaIS2_EEC2EmRKS3_.exit.i
movq %r13, (%rsp)
movq %r13, 8(%rsp)
leaq (,%r15,8), %rax
addq %r13, %rax
movq %rax, 16(%rsp)
cmpq $9, %rbp
jl .LBB0_13
# %bb.12:
movq %r13, %rdi
movq %r12, %rsi
movq %rbp, %rdx
callq memmove@PLT
.LBB0_15: # %_ZNSt6vectorIPN3ops2OpESaIS2_EEC2ERKS4_.exit
addq %rbp, %r13
movq %r13, 8(%rsp)
xorps %xmm0, %xmm0
movaps %xmm0, 64(%rsp)
movq $0, 80(%rsp)
.Ltmp9:
leaq 32(%rsp), %rsi
movq %rsp, %rcx
leaq 64(%rsp), %r8
movq %rbx, %rdi
movq %r14, %rdx
callq _ZN3ops2OpC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERKNS_5ShapeESt6vectorIPS0_SaISD_EESF_
.Ltmp10:
# %bb.16:
movq 64(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_18
# %bb.17:
callq _ZdlPv
.LBB0_18: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit
movq (%rsp), %rdi
testq %rdi, %rdi
je .LBB0_20
# %bb.19:
callq _ZdlPv
.LBB0_20: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit12
movq 32(%rsp), %rdi
leaq 48(%rsp), %rax
cmpq %rax, %rdi
je .LBB0_22
# %bb.21: # %.critedge.i.i
callq _ZdlPv
.LBB0_22: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
movq $_ZTVN3ops3SeqE+16, (%rbx)
addq $88, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_13:
.cfi_def_cfa_offset 144
cmpq $8, %rbp
jne .LBB0_15
# %bb.14:
movq (%r12), %rax
movq %rax, (%r13)
jmp .LBB0_15
.LBB0_4:
shrq $61, %r15
je .LBB0_7
# %bb.5: # %.noexc.i.i
.Ltmp6:
callq _ZSt28__throw_bad_array_new_lengthv
.Ltmp7:
# %bb.6: # %.noexc8
.LBB0_7: # %.noexc4.i.i
.Ltmp4:
callq _ZSt17__throw_bad_allocv
.Ltmp5:
# %bb.8: # %.noexc9
.LBB0_24:
.Ltmp11:
movq %rax, %rbx
movq 64(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_26
# %bb.25:
callq _ZdlPv
.LBB0_26: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit14
movq (%rsp), %rdi
testq %rdi, %rdi
je .LBB0_28
# %bb.27:
callq _ZdlPv
jmp .LBB0_28
.LBB0_23:
.Ltmp8:
movq %rax, %rbx
.LBB0_28: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit16
movq 32(%rsp), %rdi
leaq 48(%rsp), %rax
cmpq %rax, %rdi
je .LBB0_30
# %bb.29: # %.critedge.i.i17
callq _ZdlPv
.LBB0_30: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit19
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end0:
.size _ZN3ops3SeqC2ESt6vectorIPNS_2OpESaIS3_EE, .Lfunc_end0-_ZN3ops3SeqC2ESt6vectorIPNS_2OpESaIS3_EE
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table0:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp3-.Ltmp0 # Call between .Ltmp0 and .Ltmp3
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp9-.Ltmp3 # Call between .Ltmp3 and .Ltmp9
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp5-.Ltmp6 # Call between .Ltmp6 and .Ltmp5
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp5-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Lfunc_end0-.Ltmp5 # Call between .Ltmp5 and .Lfunc_end0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _ZN3ops3Seq7compileEv
.LCPI1_0:
.zero 16
.text
.globl _ZN3ops3Seq7compileEv
.p2align 4, 0x90
.type _ZN3ops3Seq7compileEv,@function
_ZN3ops3Seq7compileEv: # @_ZN3ops3Seq7compileEv
.Lfunc_begin1:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception1
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
callq _ZN3ops5Graph8instanceEv
movq %rax, %r14
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq _ZN3ops2Op5predsEv
movq 24(%rsp), %rax
movq -8(%rax), %rsi
.Ltmp12:
movq %r14, 72(%rsp) # 8-byte Spill
movq %r14, %rdi
callq _ZN3ops5Graph8compiledEPNS_2OpE
movq %rax, 80(%rsp) # 8-byte Spill
.Ltmp13:
# %bb.1:
movq 16(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_3
# %bb.2:
callq _ZdlPv
.LBB1_3: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit
xorps %xmm0, %xmm0
movaps %xmm0, 16(%rsp)
movq $0, 32(%rsp)
.Ltmp15:
leaq 144(%rsp), %rdi
movq %rbx, 88(%rsp) # 8-byte Spill
movq %rbx, %rsi
callq _ZN3ops2Op5predsEv
.Ltmp16:
# %bb.4:
movq 144(%rsp), %r15
movq 152(%rsp), %rax
movq %rax, 104(%rsp) # 8-byte Spill
cmpq %rax, %r15
jne .LBB1_19
.LBB1_5: # %._crit_edge
movq 144(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_7
# %bb.6:
callq _ZdlPv
.LBB1_7: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit24
.Ltmp26:
leaq 16(%rsp), %rdi
callq _ZN2rt4Node3nopERKSt6vectorIPS0_SaIS2_EE
.Ltmp27:
movq 88(%rsp), %rbx # 8-byte Reload
# %bb.8:
movq %rax, %r12
xorps %xmm0, %xmm0
movaps %xmm0, 48(%rsp)
movq $0, 64(%rsp)
.Ltmp29:
movl $8, %edi
callq _Znwm
.Ltmp30:
# %bb.9: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EEC2ESt16initializer_listIS2_ERKS3_.exit
movq %rax, 48(%rsp)
movq %rax, %rcx
addq $8, %rcx
movq %rcx, 64(%rsp)
movq %r12, (%rax)
movq %rcx, 56(%rsp)
movq 80(%rsp), %rax # 8-byte Reload
movq %rax, %r9
addq $64, %r9
xorps %xmm0, %xmm0
movaps %xmm0, 112(%rsp)
movq $0, 128(%rsp)
movq 88(%rax), %rax
.Ltmp32:
movq %rax, (%rsp)
leaq 48(%rsp), %rdx
leaq 112(%rsp), %rcx
movq 72(%rsp), %rdi # 8-byte Reload
movq %rbx, %rsi
movq %r12, %r8
callq _ZN3ops5Graph12add_compiledEPNS_2OpESt6vectorIPN2rt4NodeESaIS6_EES3_IPfSaIS9_EES6_RKNS_5ShapeES9_
.Ltmp33:
# %bb.10:
movq 112(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_12
# %bb.11:
callq _ZdlPv
.LBB1_12: # %_ZNSt6vectorIPfSaIS0_EED2Ev.exit
movq 48(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_14
# %bb.13:
callq _ZdlPv
.LBB1_14: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev.exit
movq 16(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_16
# %bb.15:
callq _ZdlPv
.LBB1_16: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev.exit37
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.p2align 4, 0x90
.LBB1_21: # in Loop: Header=BB1_19 Depth=1
.cfi_def_cfa_offset 224
movq 56(%rax), %rax
movq %rax, (%r12)
addq $8, 24(%rsp)
.LBB1_33: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EE9push_backERKS2_.exit
# in Loop: Header=BB1_19 Depth=1
addq $8, %r15
cmpq 104(%rsp), %r15 # 8-byte Folded Reload
je .LBB1_5
.LBB1_19: # =>This Inner Loop Header: Depth=1
movq (%r15), %rsi
.Ltmp18:
movq 72(%rsp), %rdi # 8-byte Reload
callq _ZN3ops5Graph8compiledEPNS_2OpE
.Ltmp19:
# %bb.20: # in Loop: Header=BB1_19 Depth=1
movq 24(%rsp), %r12
cmpq 32(%rsp), %r12
jne .LBB1_21
# %bb.22: # in Loop: Header=BB1_19 Depth=1
movq 16(%rsp), %r13
subq %r13, %r12
movabsq $9223372036854775800, %rcx # imm = 0x7FFFFFFFFFFFFFF8
cmpq %rcx, %r12
je .LBB1_23
# %bb.25: # %_ZNKSt6vectorIPN2rt4NodeESaIS2_EE12_M_check_lenEmPKc.exit.i.i
# in Loop: Header=BB1_19 Depth=1
movq %r12, %rbx
sarq $3, %rbx
cmpq $1, %rbx
movq %rbx, %rcx
adcq $0, %rcx
leaq (%rcx,%rbx), %r14
movabsq $1152921504606846975, %rdx # imm = 0xFFFFFFFFFFFFFFF
cmpq %rdx, %r14
cmovaeq %rdx, %r14
addq %rbx, %rcx
cmovbq %rdx, %r14
testq %r14, %r14
je .LBB1_26
# %bb.27: # in Loop: Header=BB1_19 Depth=1
leaq (,%r14,8), %rdi
.Ltmp20:
movq %rax, 96(%rsp) # 8-byte Spill
callq _Znwm
movq %rax, %rbp
movq 96(%rsp), %rax # 8-byte Reload
.Ltmp21:
jmp .LBB1_28
.LBB1_26: # in Loop: Header=BB1_19 Depth=1
xorl %ebp, %ebp
.LBB1_28: # %_ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EE11_M_allocateEm.exit.i.i
# in Loop: Header=BB1_19 Depth=1
movq 56(%rax), %rax
movq %rax, (%rbp,%rbx,8)
testq %r12, %r12
jle .LBB1_30
# %bb.29: # in Loop: Header=BB1_19 Depth=1
movq %rbp, %rdi
movq %r13, %rsi
movq %r12, %rdx
callq memmove@PLT
.LBB1_30: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EE11_S_relocateEPS2_S5_S5_RS3_.exit.i.i
# in Loop: Header=BB1_19 Depth=1
testq %r13, %r13
je .LBB1_32
# %bb.31: # in Loop: Header=BB1_19 Depth=1
movq %r13, %rdi
callq _ZdlPv
.LBB1_32: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EE17_M_realloc_insertIJRKS2_EEEvN9__gnu_cxx17__normal_iteratorIPS2_S4_EEDpOT_.exit.i
# in Loop: Header=BB1_19 Depth=1
leaq (%r12,%rbp), %rax
addq $8, %rax
movq %rbp, 16(%rsp)
movq %rax, 24(%rsp)
leaq (,%r14,8), %rax
addq %rbp, %rax
movq %rax, 32(%rsp)
jmp .LBB1_33
.LBB1_23:
.Ltmp23:
movl $.L.str.3, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp24:
# %bb.24: # %.noexc
.LBB1_39:
.Ltmp34:
movq %rax, %rbx
movq 112(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_41
# %bb.40:
callq _ZdlPv
jmp .LBB1_41
.LBB1_37:
.Ltmp31:
movq %rax, %rbx
.LBB1_41: # %_ZNSt6vectorIPfSaIS0_EED2Ev.exit39
movq 48(%rsp), %rdi
jmp .LBB1_42
.LBB1_38:
.Ltmp28:
movq %rax, %rbx
jmp .LBB1_44
.LBB1_18:
.Ltmp17:
movq %rax, %rbx
jmp .LBB1_44
.LBB1_17:
.Ltmp14:
movq %rax, %rbx
jmp .LBB1_44
.LBB1_35: # %.loopexit.split-lp
.Ltmp25:
jmp .LBB1_36
.LBB1_34: # %.loopexit
.Ltmp22:
.LBB1_36:
movq %rax, %rbx
movq 144(%rsp), %rdi
.LBB1_42: # %_ZNSt6vectorIPfSaIS0_EED2Ev.exit39
testq %rdi, %rdi
je .LBB1_44
# %bb.43:
callq _ZdlPv
.LBB1_44: # %.body
movq 16(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_46
# %bb.45:
callq _ZdlPv
.LBB1_46:
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size _ZN3ops3Seq7compileEv, .Lfunc_end1-_ZN3ops3Seq7compileEv
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception1:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end1-.Lcst_begin1
.Lcst_begin1:
.uleb128 .Lfunc_begin1-.Lfunc_begin1 # >> Call Site 1 <<
.uleb128 .Ltmp12-.Lfunc_begin1 # Call between .Lfunc_begin1 and .Ltmp12
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp12-.Lfunc_begin1 # >> Call Site 2 <<
.uleb128 .Ltmp13-.Ltmp12 # Call between .Ltmp12 and .Ltmp13
.uleb128 .Ltmp14-.Lfunc_begin1 # jumps to .Ltmp14
.byte 0 # On action: cleanup
.uleb128 .Ltmp15-.Lfunc_begin1 # >> Call Site 3 <<
.uleb128 .Ltmp16-.Ltmp15 # Call between .Ltmp15 and .Ltmp16
.uleb128 .Ltmp17-.Lfunc_begin1 # jumps to .Ltmp17
.byte 0 # On action: cleanup
.uleb128 .Ltmp26-.Lfunc_begin1 # >> Call Site 4 <<
.uleb128 .Ltmp27-.Ltmp26 # Call between .Ltmp26 and .Ltmp27
.uleb128 .Ltmp28-.Lfunc_begin1 # jumps to .Ltmp28
.byte 0 # On action: cleanup
.uleb128 .Ltmp29-.Lfunc_begin1 # >> Call Site 5 <<
.uleb128 .Ltmp30-.Ltmp29 # Call between .Ltmp29 and .Ltmp30
.uleb128 .Ltmp31-.Lfunc_begin1 # jumps to .Ltmp31
.byte 0 # On action: cleanup
.uleb128 .Ltmp32-.Lfunc_begin1 # >> Call Site 6 <<
.uleb128 .Ltmp33-.Ltmp32 # Call between .Ltmp32 and .Ltmp33
.uleb128 .Ltmp34-.Lfunc_begin1 # jumps to .Ltmp34
.byte 0 # On action: cleanup
.uleb128 .Ltmp18-.Lfunc_begin1 # >> Call Site 7 <<
.uleb128 .Ltmp21-.Ltmp18 # Call between .Ltmp18 and .Ltmp21
.uleb128 .Ltmp22-.Lfunc_begin1 # jumps to .Ltmp22
.byte 0 # On action: cleanup
.uleb128 .Ltmp21-.Lfunc_begin1 # >> Call Site 8 <<
.uleb128 .Ltmp23-.Ltmp21 # Call between .Ltmp21 and .Ltmp23
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp23-.Lfunc_begin1 # >> Call Site 9 <<
.uleb128 .Ltmp24-.Ltmp23 # Call between .Ltmp23 and .Ltmp24
.uleb128 .Ltmp25-.Lfunc_begin1 # jumps to .Ltmp25
.byte 0 # On action: cleanup
.uleb128 .Ltmp24-.Lfunc_begin1 # >> Call Site 10 <<
.uleb128 .Lfunc_end1-.Ltmp24 # Call between .Ltmp24 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end1:
.p2align 2, 0x0
# -- End function
.section .text._ZN3ops2OpD2Ev,"axG",@progbits,_ZN3ops2OpD2Ev,comdat
.weak _ZN3ops2OpD2Ev # -- Begin function _ZN3ops2OpD2Ev
.p2align 4, 0x90
.type _ZN3ops2OpD2Ev,@function
_ZN3ops2OpD2Ev: # @_ZN3ops2OpD2Ev
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq $_ZTVN3ops2OpE+16, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
callq _ZdlPv
.LBB2_2: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .LBB2_4
# %bb.3:
callq _ZdlPv
.LBB2_4: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit2
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .LBB2_6
# %bb.5:
callq _ZdlPv
.LBB2_6: # %_ZN3ops5ShapeD2Ev.exit
movq 8(%rbx), %rdi
addq $24, %rbx
cmpq %rbx, %rdi
je .LBB2_7
# %bb.8: # %.critedge.i.i
popq %rbx
.cfi_def_cfa_offset 8
jmp _ZdlPv # TAILCALL
.LBB2_7: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _ZN3ops2OpD2Ev, .Lfunc_end2-_ZN3ops2OpD2Ev
.cfi_endproc
# -- End function
.section .text._ZN3ops3SeqD0Ev,"axG",@progbits,_ZN3ops3SeqD0Ev,comdat
.weak _ZN3ops3SeqD0Ev # -- Begin function _ZN3ops3SeqD0Ev
.p2align 4, 0x90
.type _ZN3ops3SeqD0Ev,@function
_ZN3ops3SeqD0Ev: # @_ZN3ops3SeqD0Ev
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq $_ZTVN3ops2OpE+16, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
callq _ZdlPv
.LBB3_2: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit.i
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .LBB3_4
# %bb.3:
callq _ZdlPv
.LBB3_4: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit2.i
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .LBB3_6
# %bb.5:
callq _ZdlPv
.LBB3_6: # %_ZN3ops5ShapeD2Ev.exit.i
movq 8(%rbx), %rdi
leaq 24(%rbx), %rax
cmpq %rax, %rdi
je .LBB3_8
# %bb.7: # %.critedge.i.i.i
callq _ZdlPv
.LBB3_8: # %_ZN3ops2OpD2Ev.exit
movq %rbx, %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp _ZdlPv # TAILCALL
.Lfunc_end3:
.size _ZN3ops3SeqD0Ev, .Lfunc_end3-_ZN3ops3SeqD0Ev
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "seq"
.size .L.str, 4
.type _ZTVN3ops3SeqE,@object # @_ZTVN3ops3SeqE
.section .rodata,"a",@progbits
.globl _ZTVN3ops3SeqE
.p2align 3, 0x0
_ZTVN3ops3SeqE:
.quad 0
.quad _ZTIN3ops3SeqE
.quad _ZN3ops2OpD2Ev
.quad _ZN3ops3SeqD0Ev
.quad _ZN3ops3Seq7compileEv
.quad _ZN3ops2Op10child_gradEmPS0_
.size _ZTVN3ops3SeqE, 48
.type _ZTSN3ops3SeqE,@object # @_ZTSN3ops3SeqE
.globl _ZTSN3ops3SeqE
_ZTSN3ops3SeqE:
.asciz "N3ops3SeqE"
.size _ZTSN3ops3SeqE, 11
.type _ZTIN3ops3SeqE,@object # @_ZTIN3ops3SeqE
.globl _ZTIN3ops3SeqE
.p2align 3, 0x0
_ZTIN3ops3SeqE:
.quad _ZTVN10__cxxabiv120__si_class_type_infoE+16
.quad _ZTSN3ops3SeqE
.quad _ZTIN3ops2OpE
.size _ZTIN3ops3SeqE, 24
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "vector::_M_realloc_insert"
.size .L.str.3, 26
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.globl _ZN3ops3SeqC1ESt6vectorIPNS_2OpESaIS3_EE
.type _ZN3ops3SeqC1ESt6vectorIPNS_2OpESaIS3_EE,@function
.set _ZN3ops3SeqC1ESt6vectorIPNS_2OpESaIS3_EE, _ZN3ops3SeqC2ESt6vectorIPNS_2OpESaIS3_EE
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZTVN10__cxxabiv120__si_class_type_infoE
.addrsig_sym _ZTSN3ops3SeqE
.addrsig_sym _ZTIN3ops2OpE
.addrsig_sym _ZTIN3ops3SeqE
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void add(int a, int b, int *c)
{
//Add 2 numbers together and store in location pointed by *c
*c = a + b;
} | code for sm_80
Function : _Z3addiiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fe40000000f00 */
/*0050*/ IADD3 R5, R5, c[0x0][0x160], RZ ; /* 0x0000580005057a10 */
/* 0x000fca0007ffe0ff */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void add(int a, int b, int *c)
{
//Add 2 numbers together and store in location pointed by *c
*c = a + b;
} | .file "tmpxft_0018cd6a_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z3addiiPiiiPi
.type _Z24__device_stub__Z3addiiPiiiPi, @function
_Z24__device_stub__Z3addiiPiiiPi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3addiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z24__device_stub__Z3addiiPiiiPi, .-_Z24__device_stub__Z3addiiPiiiPi
.globl _Z3addiiPi
.type _Z3addiiPi, @function
_Z3addiiPi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3addiiPiiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3addiiPi, .-_Z3addiiPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addiiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiiPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void add(int a, int b, int *c)
{
//Add 2 numbers together and store in location pointed by *c
*c = a + b;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void add(int a, int b, int *c)
{
//Add 2 numbers together and store in location pointed by *c
*c = a + b;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void add(int a, int b, int *c)
{
//Add 2 numbers together and store in location pointed by *c
*c = a + b;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiiPi
.globl _Z3addiiPi
.p2align 8
.type _Z3addiiPi,@function
_Z3addiiPi:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addiiPi, .Lfunc_end0-_Z3addiiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiiPi
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z3addiiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void add(int a, int b, int *c)
{
//Add 2 numbers together and store in location pointed by *c
*c = a + b;
} | .text
.file "add.hip"
.globl _Z18__device_stub__addiiPi # -- Begin function _Z18__device_stub__addiiPi
.p2align 4, 0x90
.type _Z18__device_stub__addiiPi,@function
_Z18__device_stub__addiiPi: # @_Z18__device_stub__addiiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3addiiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__addiiPi, .Lfunc_end0-_Z18__device_stub__addiiPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addiiPi,@object # @_Z3addiiPi
.section .rodata,"a",@progbits
.globl _Z3addiiPi
.p2align 3, 0x0
_Z3addiiPi:
.quad _Z18__device_stub__addiiPi
.size _Z3addiiPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addiiPi"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addiiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addiiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addiiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fe40000000f00 */
/*0050*/ IADD3 R5, R5, c[0x0][0x160], RZ ; /* 0x0000580005057a10 */
/* 0x000fca0007ffe0ff */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiiPi
.globl _Z3addiiPi
.p2align 8
.type _Z3addiiPi,@function
_Z3addiiPi:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addiiPi, .Lfunc_end0-_Z3addiiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiiPi
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z3addiiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018cd6a_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z3addiiPiiiPi
.type _Z24__device_stub__Z3addiiPiiiPi, @function
_Z24__device_stub__Z3addiiPiiiPi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3addiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z24__device_stub__Z3addiiPiiiPi, .-_Z24__device_stub__Z3addiiPiiiPi
.globl _Z3addiiPi
.type _Z3addiiPi, @function
_Z3addiiPi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3addiiPiiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3addiiPi, .-_Z3addiiPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addiiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiiPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "add.hip"
.globl _Z18__device_stub__addiiPi # -- Begin function _Z18__device_stub__addiiPi
.p2align 4, 0x90
.type _Z18__device_stub__addiiPi,@function
_Z18__device_stub__addiiPi: # @_Z18__device_stub__addiiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3addiiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__addiiPi, .Lfunc_end0-_Z18__device_stub__addiiPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addiiPi,@object # @_Z3addiiPi
.section .rodata,"a",@progbits
.globl _Z3addiiPi
.p2align 3, 0x0
_Z3addiiPi:
.quad _Z18__device_stub__addiiPi
.size _Z3addiiPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addiiPi"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addiiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addiiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // C = A * B
const int TILE_SIZE = 16;
__global__
void matrixMultiplication(float* C, float* A, float* B, int rowsC, int colsC, int rowsA, int colsA, int rowsB, int colsB) {
__device__ __shared__ float ds_A[TILE_SIZE][TILE_SIZE];
__device__ __shared__ float ds_B[TILE_SIZE][TILE_SIZE];
const int tx = threadIdx.x;
const int ty = threadIdx.y;
const int row = blockIdx.y * blockDim.y + ty;
const int col = blockIdx.x * blockDim.x + tx;
float cValue = 0.0;
for (int t = 0; t < (colsA-1) / TILE_SIZE+1; t++) {
if (t * TILE_SIZE + tx < colsA && row < rowsA) {
ds_A[ty][tx] = A[row * colsA + t * TILE_SIZE + tx];
} else {
ds_A[ty][tx] = 0.0;
}
if (t * TILE_SIZE + ty < rowsB && col < colsB) {
ds_B[ty][tx] = B[(t * TILE_SIZE + ty) * colsB + col];
} else {
ds_B[ty][tx] = 0.0;
}
__syncthreads();
for (int i = 0; i < TILE_SIZE; i++) {
cValue += ds_A[ty][i] * ds_B[i][tx];
}
__syncthreads();
}
if (row < rowsC && col < colsC) {
C[row * colsC + col] = cValue;
}
} | code for sm_80
Function : _Z20matrixMultiplicationPfS_S_iiiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R4, c[0x0][0x184] ; /* 0x0000610000047a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R21, -RZ, RZ, 0, 0 ; /* 0x00000000ff157435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0060*/ ISETP.GE.AND P1, PT, R4, -0xe, PT ; /* 0xfffffff20400780c */
/* 0x000fc60003f26270 */
/*0070*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0080*/ S2R R13, SR_TID.Y ; /* 0x00000000000d7919 */
/* 0x000e620000002200 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R2 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0202 */
/*00a0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fe20003f06270 */
/*00b0*/ IMAD R3, R3, c[0x0][0x4], R13 ; /* 0x0000010003037a24 */
/* 0x002fca00078e020d */
/*00c0*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fe20000706670 */
/*00d0*/ @!P1 BRA 0x590 ; /* 0x000004b000009947 */
/* 0x000fd80003800000 */
/*00e0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe20007ffe0ff */
/*00f0*/ IMAD R14, R3, c[0x0][0x184], R2 ; /* 0x00006100030e7a24 */
/* 0x000fe200078e0202 */
/*0100*/ MOV R15, 0x4 ; /* 0x00000004000f7802 */
/* 0x000fe20000000f00 */
/*0110*/ IMAD R12, R13.reuse, c[0x0][0x18c], R0 ; /* 0x000063000d0c7a24 */
/* 0x040fe200078e0200 */
/*0120*/ SHF.R.S32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x000fe20000011404 */
/*0130*/ UMOV UR4, 0xffffffff ; /* 0xffffffff00047882 */
/* 0x000fe20000000000 */
/*0140*/ SHF.L.U32 R17, R13, 0x6, RZ ; /* 0x000000060d117819 */
/* 0x000fe200000006ff */
/*0150*/ IMAD.WIDE R14, R14, R15, c[0x0][0x168] ; /* 0x00005a000e0e7625 */
/* 0x000fe200078e020f */
/*0160*/ LEA.HI R5, R5, R4, RZ, 0x4 ; /* 0x0000000405057211 */
/* 0x000fe400078f20ff */
/*0170*/ MOV R21, RZ ; /* 0x000000ff00157202 */
/* 0x000fe20000000f00 */
/*0180*/ IMAD.MOV.U32 R18, RZ, RZ, R14 ; /* 0x000000ffff127224 */
/* 0x000fe200078e000e */
/*0190*/ LEA R16, R2, 0x400, 0x2 ; /* 0x0000040002107811 */
/* 0x000fc400078e10ff */
/*01a0*/ LEA R19, R2, R17, 0x2 ; /* 0x0000001102137211 */
/* 0x000fe400078e10ff */
/*01b0*/ SHF.R.S32.HI R14, RZ, 0x4, R5 ; /* 0x00000004ff0e7819 */
/* 0x000fe40000011405 */
/*01c0*/ ISETP.GE.AND P1, PT, R13, c[0x0][0x188], PT ; /* 0x000062000d007a0c */
/* 0x000fe20003f26270 */
/*01d0*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*01e0*/ ISETP.GE.AND P2, PT, R2, c[0x0][0x184], PT ; /* 0x0000610002007a0c */
/* 0x000fe40003f46270 */
/*01f0*/ ISETP.GE.OR P1, PT, R0, c[0x0][0x18c], P1 ; /* 0x0000630000007a0c */
/* 0x000fe40000f26670 */
/*0200*/ ISETP.GE.OR P2, PT, R3, c[0x0][0x180], P2 ; /* 0x0000600003007a0c */
/* 0x000fe40001746670 */
/*0210*/ MOV R22, RZ ; /* 0x000000ff00167202 */
/* 0x000fd20000000f00 */
/*0220*/ @!P1 IMAD.MOV.U32 R25, RZ, RZ, 0x4 ; /* 0x00000004ff199424 */
/* 0x000fe400078e00ff */
/*0230*/ @!P2 MOV R4, R18 ; /* 0x000000120004a202 */
/* 0x000fe20000000f00 */
/*0240*/ @!P2 IMAD.MOV.U32 R5, RZ, RZ, R15 ; /* 0x000000ffff05a224 */
/* 0x000fe400078e000f */
/*0250*/ @!P1 IMAD.WIDE R24, R12, R25, c[0x0][0x170] ; /* 0x00005c000c189625 */
/* 0x000fc600078e0219 */
/*0260*/ @!P2 LDG.E R22, [R4.64] ; /* 0x000000060416a981 */
/* 0x000ea8000c1e1900 */
/*0270*/ @!P1 LDG.E R28, [R24.64] ; /* 0x00000006181c9981 */
/* 0x000ee2000c1e1900 */
/*0280*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*0290*/ IADD3 R18, P2, R18, 0x40, RZ ; /* 0x0000004012127810 */
/* 0x000fe40007f5e0ff */
/*02a0*/ IADD3 R13, R13, 0x10, RZ ; /* 0x000000100d0d7810 */
/* 0x000fe40007ffe0ff */
/*02b0*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fc40007ffe0ff */
/*02c0*/ ISETP.LE.AND P1, PT, R14, UR4, PT ; /* 0x000000040e007c0c */
/* 0x000fe4000bf23270 */
/*02d0*/ IADD3.X R15, RZ, R15, RZ, P2, !PT ; /* 0x0000000fff0f7210 */
/* 0x000fe200017fe4ff */
/*02e0*/ STS [R19], R22 ; /* 0x0000001613007388 */
/* 0x004fe80000000800 */
/*02f0*/ STS [R19+0x400], R28 ; /* 0x0004001c13007388 */
/* 0x008fe80000000800 */
/*0300*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0310*/ LDS R29, [R16] ; /* 0x00000000101d7984 */
/* 0x000fe80000000800 */
/*0320*/ LDS.128 R8, [R17] ; /* 0x0000000011087984 */
/* 0x000e280000000c00 */
/*0330*/ LDS R24, [R16+0x40] ; /* 0x0000400010187984 */
/* 0x000e680000000800 */
/*0340*/ LDS R27, [R16+0x80] ; /* 0x00008000101b7984 */
/* 0x000ea80000000800 */
/*0350*/ LDS R26, [R16+0xc0] ; /* 0x0000c000101a7984 */
/* 0x000ee80000000800 */
/*0360*/ LDS R23, [R16+0x100] ; /* 0x0001000010177984 */
/* 0x000fe80000000800 */
/*0370*/ LDS.128 R4, [R17+0x10] ; /* 0x0000100011047984 */
/* 0x000f280000000c00 */
/*0380*/ LDS R20, [R16+0x140] ; /* 0x0001400010147984 */
/* 0x000f680000000800 */
/*0390*/ LDS R25, [R16+0x180] ; /* 0x0001800010197984 */
/* 0x000f680000000800 */
/*03a0*/ LDS R22, [R16+0x1c0] ; /* 0x0001c00010167984 */
/* 0x000f620000000800 */
/*03b0*/ FFMA R8, R29, R8, R21 ; /* 0x000000081d087223 */
/* 0x001fc60000000015 */
/*03c0*/ LDS R21, [R16+0x200] ; /* 0x0002000010157984 */
/* 0x000fe20000000800 */
/*03d0*/ FFMA R8, R24, R9, R8 ; /* 0x0000000918087223 */
/* 0x002fc60000000008 */
/*03e0*/ LDS R24, [R16+0x240] ; /* 0x0002400010187984 */
/* 0x000fe20000000800 */
/*03f0*/ FFMA R8, R27, R10, R8 ; /* 0x0000000a1b087223 */
/* 0x004fc80000000008 */
/*0400*/ FFMA R26, R26, R11, R8 ; /* 0x0000000b1a1a7223 */
/* 0x008fe40000000008 */
/*0410*/ LDS.128 R8, [R17+0x20] ; /* 0x0000200011087984 */
/* 0x000e240000000c00 */
/*0420*/ FFMA R4, R23, R4, R26 ; /* 0x0000000417047223 */
/* 0x010fe4000000001a */
/*0430*/ LDS R23, [R16+0x280] ; /* 0x0002800010177984 */
/* 0x000e640000000800 */
/*0440*/ FFMA R4, R20, R5, R4 ; /* 0x0000000514047223 */
/* 0x020fe40000000004 */
/*0450*/ LDS R20, [R16+0x2c0] ; /* 0x0002c00010147984 */
/* 0x000ea40000000800 */
/*0460*/ FFMA R4, R25, R6, R4 ; /* 0x0000000619047223 */
/* 0x000fc40000000004 */
/*0470*/ LDS R25, [R16+0x300] ; /* 0x0003000010197984 */
/* 0x000fe40000000800 */
/*0480*/ FFMA R26, R22, R7, R4 ; /* 0x00000007161a7223 */
/* 0x000fe40000000004 */
/*0490*/ LDS.128 R4, [R17+0x30] ; /* 0x0000300011047984 */
/* 0x000ee80000000c00 */
/*04a0*/ LDS R22, [R16+0x340] ; /* 0x0003400010167984 */
/* 0x000f220000000800 */
/*04b0*/ FFMA R26, R21, R8, R26 ; /* 0x00000008151a7223 */
/* 0x001fc6000000001a */
/*04c0*/ LDS R21, [R16+0x380] ; /* 0x0003800010157984 */
/* 0x000e220000000800 */
/*04d0*/ FFMA R9, R24, R9, R26 ; /* 0x0000000918097223 */
/* 0x000fc6000000001a */
/*04e0*/ LDS R8, [R16+0x3c0] ; /* 0x0003c00010087984 */
/* 0x000f620000000800 */
/*04f0*/ FFMA R9, R23, R10, R9 ; /* 0x0000000a17097223 */
/* 0x002fc80000000009 */
/*0500*/ FFMA R9, R20, R11, R9 ; /* 0x0000000b14097223 */
/* 0x004fc80000000009 */
/*0510*/ FFMA R4, R25, R4, R9 ; /* 0x0000000419047223 */
/* 0x008fc80000000009 */
/*0520*/ FFMA R4, R22, R5, R4 ; /* 0x0000000516047223 */
/* 0x010fe20000000004 */
/*0530*/ HFMA2.MMA R5, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff057435 */
/* 0x000fd400000001ff */
/*0540*/ IMAD R12, R5, c[0x0][0x18c], R12 ; /* 0x00006300050c7a24 */
/* 0x000fe400078e020c */
/*0550*/ FFMA R21, R21, R6, R4 ; /* 0x0000000615157223 */
/* 0x001fc80000000004 */
/*0560*/ FFMA R21, R8, R7, R21 ; /* 0x0000000708157223 */
/* 0x020fe20000000015 */
/*0570*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0580*/ @!P1 BRA 0x1c0 ; /* 0xfffffc3000009947 */
/* 0x000fea000383ffff */
/*0590*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*05a0*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*05b0*/ IMAD R3, R3, c[0x0][0x17c], R0 ; /* 0x00005f0003037a24 */
/* 0x000fc800078e0200 */
/*05c0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0202 */
/*05d0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x000fe2000c101906 */
/*05e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05f0*/ BRA 0x5f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // C = A * B
const int TILE_SIZE = 16;
__global__
void matrixMultiplication(float* C, float* A, float* B, int rowsC, int colsC, int rowsA, int colsA, int rowsB, int colsB) {
__device__ __shared__ float ds_A[TILE_SIZE][TILE_SIZE];
__device__ __shared__ float ds_B[TILE_SIZE][TILE_SIZE];
const int tx = threadIdx.x;
const int ty = threadIdx.y;
const int row = blockIdx.y * blockDim.y + ty;
const int col = blockIdx.x * blockDim.x + tx;
float cValue = 0.0;
for (int t = 0; t < (colsA-1) / TILE_SIZE+1; t++) {
if (t * TILE_SIZE + tx < colsA && row < rowsA) {
ds_A[ty][tx] = A[row * colsA + t * TILE_SIZE + tx];
} else {
ds_A[ty][tx] = 0.0;
}
if (t * TILE_SIZE + ty < rowsB && col < colsB) {
ds_B[ty][tx] = B[(t * TILE_SIZE + ty) * colsB + col];
} else {
ds_B[ty][tx] = 0.0;
}
__syncthreads();
for (int i = 0; i < TILE_SIZE; i++) {
cValue += ds_A[ty][i] * ds_B[i][tx];
}
__syncthreads();
}
if (row < rowsC && col < colsC) {
C[row * colsC + col] = cValue;
}
} | .file "tmpxft_0013f61b_00000000-6_matrix.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z20matrixMultiplicationPfS_S_iiiiiiPfS_S_iiiiii
.type _Z50__device_stub__Z20matrixMultiplicationPfS_S_iiiiiiPfS_S_iiiiii, @function
_Z50__device_stub__Z20matrixMultiplicationPfS_S_iiiiiiPfS_S_iiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z20matrixMultiplicationPfS_S_iiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z20matrixMultiplicationPfS_S_iiiiiiPfS_S_iiiiii, .-_Z50__device_stub__Z20matrixMultiplicationPfS_S_iiiiiiPfS_S_iiiiii
.globl _Z20matrixMultiplicationPfS_S_iiiiii
.type _Z20matrixMultiplicationPfS_S_iiiiii, @function
_Z20matrixMultiplicationPfS_S_iiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z50__device_stub__Z20matrixMultiplicationPfS_S_iiiiiiPfS_S_iiiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20matrixMultiplicationPfS_S_iiiiii, .-_Z20matrixMultiplicationPfS_S_iiiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20matrixMultiplicationPfS_S_iiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20matrixMultiplicationPfS_S_iiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // C = A * B
const int TILE_SIZE = 16;
__global__
void matrixMultiplication(float* C, float* A, float* B, int rowsC, int colsC, int rowsA, int colsA, int rowsB, int colsB) {
__device__ __shared__ float ds_A[TILE_SIZE][TILE_SIZE];
__device__ __shared__ float ds_B[TILE_SIZE][TILE_SIZE];
const int tx = threadIdx.x;
const int ty = threadIdx.y;
const int row = blockIdx.y * blockDim.y + ty;
const int col = blockIdx.x * blockDim.x + tx;
float cValue = 0.0;
for (int t = 0; t < (colsA-1) / TILE_SIZE+1; t++) {
if (t * TILE_SIZE + tx < colsA && row < rowsA) {
ds_A[ty][tx] = A[row * colsA + t * TILE_SIZE + tx];
} else {
ds_A[ty][tx] = 0.0;
}
if (t * TILE_SIZE + ty < rowsB && col < colsB) {
ds_B[ty][tx] = B[(t * TILE_SIZE + ty) * colsB + col];
} else {
ds_B[ty][tx] = 0.0;
}
__syncthreads();
for (int i = 0; i < TILE_SIZE; i++) {
cValue += ds_A[ty][i] * ds_B[i][tx];
}
__syncthreads();
}
if (row < rowsC && col < colsC) {
C[row * colsC + col] = cValue;
}
} | #include <hip/hip_runtime.h>
__global__
void matrixMultiplication(float* C, float* A, float* B, int rowsC, int colsC, int rowsA, int colsA, int rowsB, int colsB); |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__
void matrixMultiplication(float* C, float* A, float* B, int rowsC, int colsC, int rowsA, int colsA, int rowsB, int colsB); | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__
void matrixMultiplication(float* C, float* A, float* B, int rowsC, int colsC, int rowsA, int colsA, int rowsB, int colsB); | .text
.file "matrix.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z20matrixMultiplicationPfS_S_iiiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R4, c[0x0][0x184] ; /* 0x0000610000047a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R21, -RZ, RZ, 0, 0 ; /* 0x00000000ff157435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0060*/ ISETP.GE.AND P1, PT, R4, -0xe, PT ; /* 0xfffffff20400780c */
/* 0x000fc60003f26270 */
/*0070*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0080*/ S2R R13, SR_TID.Y ; /* 0x00000000000d7919 */
/* 0x000e620000002200 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R2 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0202 */
/*00a0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fe20003f06270 */
/*00b0*/ IMAD R3, R3, c[0x0][0x4], R13 ; /* 0x0000010003037a24 */
/* 0x002fca00078e020d */
/*00c0*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fe20000706670 */
/*00d0*/ @!P1 BRA 0x590 ; /* 0x000004b000009947 */
/* 0x000fd80003800000 */
/*00e0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe20007ffe0ff */
/*00f0*/ IMAD R14, R3, c[0x0][0x184], R2 ; /* 0x00006100030e7a24 */
/* 0x000fe200078e0202 */
/*0100*/ MOV R15, 0x4 ; /* 0x00000004000f7802 */
/* 0x000fe20000000f00 */
/*0110*/ IMAD R12, R13.reuse, c[0x0][0x18c], R0 ; /* 0x000063000d0c7a24 */
/* 0x040fe200078e0200 */
/*0120*/ SHF.R.S32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x000fe20000011404 */
/*0130*/ UMOV UR4, 0xffffffff ; /* 0xffffffff00047882 */
/* 0x000fe20000000000 */
/*0140*/ SHF.L.U32 R17, R13, 0x6, RZ ; /* 0x000000060d117819 */
/* 0x000fe200000006ff */
/*0150*/ IMAD.WIDE R14, R14, R15, c[0x0][0x168] ; /* 0x00005a000e0e7625 */
/* 0x000fe200078e020f */
/*0160*/ LEA.HI R5, R5, R4, RZ, 0x4 ; /* 0x0000000405057211 */
/* 0x000fe400078f20ff */
/*0170*/ MOV R21, RZ ; /* 0x000000ff00157202 */
/* 0x000fe20000000f00 */
/*0180*/ IMAD.MOV.U32 R18, RZ, RZ, R14 ; /* 0x000000ffff127224 */
/* 0x000fe200078e000e */
/*0190*/ LEA R16, R2, 0x400, 0x2 ; /* 0x0000040002107811 */
/* 0x000fc400078e10ff */
/*01a0*/ LEA R19, R2, R17, 0x2 ; /* 0x0000001102137211 */
/* 0x000fe400078e10ff */
/*01b0*/ SHF.R.S32.HI R14, RZ, 0x4, R5 ; /* 0x00000004ff0e7819 */
/* 0x000fe40000011405 */
/*01c0*/ ISETP.GE.AND P1, PT, R13, c[0x0][0x188], PT ; /* 0x000062000d007a0c */
/* 0x000fe20003f26270 */
/*01d0*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*01e0*/ ISETP.GE.AND P2, PT, R2, c[0x0][0x184], PT ; /* 0x0000610002007a0c */
/* 0x000fe40003f46270 */
/*01f0*/ ISETP.GE.OR P1, PT, R0, c[0x0][0x18c], P1 ; /* 0x0000630000007a0c */
/* 0x000fe40000f26670 */
/*0200*/ ISETP.GE.OR P2, PT, R3, c[0x0][0x180], P2 ; /* 0x0000600003007a0c */
/* 0x000fe40001746670 */
/*0210*/ MOV R22, RZ ; /* 0x000000ff00167202 */
/* 0x000fd20000000f00 */
/*0220*/ @!P1 IMAD.MOV.U32 R25, RZ, RZ, 0x4 ; /* 0x00000004ff199424 */
/* 0x000fe400078e00ff */
/*0230*/ @!P2 MOV R4, R18 ; /* 0x000000120004a202 */
/* 0x000fe20000000f00 */
/*0240*/ @!P2 IMAD.MOV.U32 R5, RZ, RZ, R15 ; /* 0x000000ffff05a224 */
/* 0x000fe400078e000f */
/*0250*/ @!P1 IMAD.WIDE R24, R12, R25, c[0x0][0x170] ; /* 0x00005c000c189625 */
/* 0x000fc600078e0219 */
/*0260*/ @!P2 LDG.E R22, [R4.64] ; /* 0x000000060416a981 */
/* 0x000ea8000c1e1900 */
/*0270*/ @!P1 LDG.E R28, [R24.64] ; /* 0x00000006181c9981 */
/* 0x000ee2000c1e1900 */
/*0280*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*0290*/ IADD3 R18, P2, R18, 0x40, RZ ; /* 0x0000004012127810 */
/* 0x000fe40007f5e0ff */
/*02a0*/ IADD3 R13, R13, 0x10, RZ ; /* 0x000000100d0d7810 */
/* 0x000fe40007ffe0ff */
/*02b0*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fc40007ffe0ff */
/*02c0*/ ISETP.LE.AND P1, PT, R14, UR4, PT ; /* 0x000000040e007c0c */
/* 0x000fe4000bf23270 */
/*02d0*/ IADD3.X R15, RZ, R15, RZ, P2, !PT ; /* 0x0000000fff0f7210 */
/* 0x000fe200017fe4ff */
/*02e0*/ STS [R19], R22 ; /* 0x0000001613007388 */
/* 0x004fe80000000800 */
/*02f0*/ STS [R19+0x400], R28 ; /* 0x0004001c13007388 */
/* 0x008fe80000000800 */
/*0300*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0310*/ LDS R29, [R16] ; /* 0x00000000101d7984 */
/* 0x000fe80000000800 */
/*0320*/ LDS.128 R8, [R17] ; /* 0x0000000011087984 */
/* 0x000e280000000c00 */
/*0330*/ LDS R24, [R16+0x40] ; /* 0x0000400010187984 */
/* 0x000e680000000800 */
/*0340*/ LDS R27, [R16+0x80] ; /* 0x00008000101b7984 */
/* 0x000ea80000000800 */
/*0350*/ LDS R26, [R16+0xc0] ; /* 0x0000c000101a7984 */
/* 0x000ee80000000800 */
/*0360*/ LDS R23, [R16+0x100] ; /* 0x0001000010177984 */
/* 0x000fe80000000800 */
/*0370*/ LDS.128 R4, [R17+0x10] ; /* 0x0000100011047984 */
/* 0x000f280000000c00 */
/*0380*/ LDS R20, [R16+0x140] ; /* 0x0001400010147984 */
/* 0x000f680000000800 */
/*0390*/ LDS R25, [R16+0x180] ; /* 0x0001800010197984 */
/* 0x000f680000000800 */
/*03a0*/ LDS R22, [R16+0x1c0] ; /* 0x0001c00010167984 */
/* 0x000f620000000800 */
/*03b0*/ FFMA R8, R29, R8, R21 ; /* 0x000000081d087223 */
/* 0x001fc60000000015 */
/*03c0*/ LDS R21, [R16+0x200] ; /* 0x0002000010157984 */
/* 0x000fe20000000800 */
/*03d0*/ FFMA R8, R24, R9, R8 ; /* 0x0000000918087223 */
/* 0x002fc60000000008 */
/*03e0*/ LDS R24, [R16+0x240] ; /* 0x0002400010187984 */
/* 0x000fe20000000800 */
/*03f0*/ FFMA R8, R27, R10, R8 ; /* 0x0000000a1b087223 */
/* 0x004fc80000000008 */
/*0400*/ FFMA R26, R26, R11, R8 ; /* 0x0000000b1a1a7223 */
/* 0x008fe40000000008 */
/*0410*/ LDS.128 R8, [R17+0x20] ; /* 0x0000200011087984 */
/* 0x000e240000000c00 */
/*0420*/ FFMA R4, R23, R4, R26 ; /* 0x0000000417047223 */
/* 0x010fe4000000001a */
/*0430*/ LDS R23, [R16+0x280] ; /* 0x0002800010177984 */
/* 0x000e640000000800 */
/*0440*/ FFMA R4, R20, R5, R4 ; /* 0x0000000514047223 */
/* 0x020fe40000000004 */
/*0450*/ LDS R20, [R16+0x2c0] ; /* 0x0002c00010147984 */
/* 0x000ea40000000800 */
/*0460*/ FFMA R4, R25, R6, R4 ; /* 0x0000000619047223 */
/* 0x000fc40000000004 */
/*0470*/ LDS R25, [R16+0x300] ; /* 0x0003000010197984 */
/* 0x000fe40000000800 */
/*0480*/ FFMA R26, R22, R7, R4 ; /* 0x00000007161a7223 */
/* 0x000fe40000000004 */
/*0490*/ LDS.128 R4, [R17+0x30] ; /* 0x0000300011047984 */
/* 0x000ee80000000c00 */
/*04a0*/ LDS R22, [R16+0x340] ; /* 0x0003400010167984 */
/* 0x000f220000000800 */
/*04b0*/ FFMA R26, R21, R8, R26 ; /* 0x00000008151a7223 */
/* 0x001fc6000000001a */
/*04c0*/ LDS R21, [R16+0x380] ; /* 0x0003800010157984 */
/* 0x000e220000000800 */
/*04d0*/ FFMA R9, R24, R9, R26 ; /* 0x0000000918097223 */
/* 0x000fc6000000001a */
/*04e0*/ LDS R8, [R16+0x3c0] ; /* 0x0003c00010087984 */
/* 0x000f620000000800 */
/*04f0*/ FFMA R9, R23, R10, R9 ; /* 0x0000000a17097223 */
/* 0x002fc80000000009 */
/*0500*/ FFMA R9, R20, R11, R9 ; /* 0x0000000b14097223 */
/* 0x004fc80000000009 */
/*0510*/ FFMA R4, R25, R4, R9 ; /* 0x0000000419047223 */
/* 0x008fc80000000009 */
/*0520*/ FFMA R4, R22, R5, R4 ; /* 0x0000000516047223 */
/* 0x010fe20000000004 */
/*0530*/ HFMA2.MMA R5, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff057435 */
/* 0x000fd400000001ff */
/*0540*/ IMAD R12, R5, c[0x0][0x18c], R12 ; /* 0x00006300050c7a24 */
/* 0x000fe400078e020c */
/*0550*/ FFMA R21, R21, R6, R4 ; /* 0x0000000615157223 */
/* 0x001fc80000000004 */
/*0560*/ FFMA R21, R8, R7, R21 ; /* 0x0000000708157223 */
/* 0x020fe20000000015 */
/*0570*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0580*/ @!P1 BRA 0x1c0 ; /* 0xfffffc3000009947 */
/* 0x000fea000383ffff */
/*0590*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*05a0*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*05b0*/ IMAD R3, R3, c[0x0][0x17c], R0 ; /* 0x00005f0003037a24 */
/* 0x000fc800078e0200 */
/*05c0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0202 */
/*05d0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x000fe2000c101906 */
/*05e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05f0*/ BRA 0x5f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013f61b_00000000-6_matrix.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z20matrixMultiplicationPfS_S_iiiiiiPfS_S_iiiiii
.type _Z50__device_stub__Z20matrixMultiplicationPfS_S_iiiiiiPfS_S_iiiiii, @function
_Z50__device_stub__Z20matrixMultiplicationPfS_S_iiiiiiPfS_S_iiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z20matrixMultiplicationPfS_S_iiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z20matrixMultiplicationPfS_S_iiiiiiPfS_S_iiiiii, .-_Z50__device_stub__Z20matrixMultiplicationPfS_S_iiiiiiPfS_S_iiiiii
.globl _Z20matrixMultiplicationPfS_S_iiiiii
.type _Z20matrixMultiplicationPfS_S_iiiiii, @function
_Z20matrixMultiplicationPfS_S_iiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z50__device_stub__Z20matrixMultiplicationPfS_S_iiiiiiPfS_S_iiiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20matrixMultiplicationPfS_S_iiiiii, .-_Z20matrixMultiplicationPfS_S_iiiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20matrixMultiplicationPfS_S_iiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20matrixMultiplicationPfS_S_iiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrix.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void kernel_update(float *img1, float *img, int nx, int ny, int nz, float lambda){
int ix = 16 * blockIdx.x + threadIdx.x;
int iy = 16 * blockIdx.y + threadIdx.y;
int iz = 4 * blockIdx.z + threadIdx.z;
if (ix >= nx || iy >= ny || iz >= nz)
return;
int id = ix + iy * nx + iz * nx * ny;
img1[id] -= lambda * img[id];
if (img1[id] < 0.0f)
img1[id] = 0.0f;
if (img1[id] > 5000.0f)
img1[id] = 0.0f;
} | code for sm_80
Function : _Z13kernel_updatePfS_iiif
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002600 */
/*0020*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e680000002100 */
/*0050*/ S2R R4, SR_CTAID.Z ; /* 0x0000000000047919 */
/* 0x000ea80000002700 */
/*0060*/ S2R R7, SR_TID.Z ; /* 0x0000000000077919 */
/* 0x000ea20000002300 */
/*0070*/ LEA R2, R2, R5, 0x4 ; /* 0x0000000502027211 */
/* 0x001fc800078e20ff */
/*0080*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x174], PT ; /* 0x00005d0002007a0c */
/* 0x000fe20003f06270 */
/*0090*/ IMAD R0, R0, 0x10, R3 ; /* 0x0000001000007824 */
/* 0x002fca00078e0203 */
/*00a0*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fe40000706670 */
/*00b0*/ LEA R3, R4, R7, 0x2 ; /* 0x0000000704037211 */
/* 0x004fc800078e10ff */
/*00c0*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ IMAD R3, R3, c[0x0][0x174], R2 ; /* 0x00005d0003037a24 */
/* 0x000fe200078e0202 */
/*00f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0100*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe400078e00ff */
/*0110*/ IMAD R0, R3, c[0x0][0x170], R0 ; /* 0x00005c0003007a24 */
/* 0x000fc800078e0200 */
/*0120*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0205 */
/*0130*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fe400078e0205 */
/*0140*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0150*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1900 */
/*0160*/ FFMA R7, -R2, c[0x0][0x17c], R7 ; /* 0x00005f0002077a23 */
/* 0x004fca0000000107 */
/*0170*/ FSETP.GEU.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720b */
/* 0x000fc80003f0e000 */
/*0180*/ FSEL R7, R7, RZ, P0 ; /* 0x000000ff07077208 */
/* 0x000fc80000000000 */
/*0190*/ FSETP.GT.AND P0, PT, R7, 5000, PT ; /* 0x459c40000700780b */
/* 0x000fe20003f04000 */
/*01a0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001d8000c101904 */
/*01b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*01c0*/ STG.E [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x001fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void kernel_update(float *img1, float *img, int nx, int ny, int nz, float lambda){
int ix = 16 * blockIdx.x + threadIdx.x;
int iy = 16 * blockIdx.y + threadIdx.y;
int iz = 4 * blockIdx.z + threadIdx.z;
if (ix >= nx || iy >= ny || iz >= nz)
return;
int id = ix + iy * nx + iz * nx * ny;
img1[id] -= lambda * img[id];
if (img1[id] < 0.0f)
img1[id] = 0.0f;
if (img1[id] > 5000.0f)
img1[id] = 0.0f;
} | .file "tmpxft_00063db9_00000000-6_kernel_update.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z13kernel_updatePfS_iiifPfS_iiif
.type _Z39__device_stub__Z13kernel_updatePfS_iiifPfS_iiif, @function
_Z39__device_stub__Z13kernel_updatePfS_iiifPfS_iiif:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movss %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13kernel_updatePfS_iiif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z13kernel_updatePfS_iiifPfS_iiif, .-_Z39__device_stub__Z13kernel_updatePfS_iiifPfS_iiif
.globl _Z13kernel_updatePfS_iiif
.type _Z13kernel_updatePfS_iiif, @function
_Z13kernel_updatePfS_iiif:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z13kernel_updatePfS_iiifPfS_iiif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13kernel_updatePfS_iiif, .-_Z13kernel_updatePfS_iiif
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13kernel_updatePfS_iiif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13kernel_updatePfS_iiif(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void kernel_update(float *img1, float *img, int nx, int ny, int nz, float lambda){
int ix = 16 * blockIdx.x + threadIdx.x;
int iy = 16 * blockIdx.y + threadIdx.y;
int iz = 4 * blockIdx.z + threadIdx.z;
if (ix >= nx || iy >= ny || iz >= nz)
return;
int id = ix + iy * nx + iz * nx * ny;
img1[id] -= lambda * img[id];
if (img1[id] < 0.0f)
img1[id] = 0.0f;
if (img1[id] > 5000.0f)
img1[id] = 0.0f;
} | #include <hip/hip_runtime.h>
__global__ void kernel_update(float *img1, float *img, int nx, int ny, int nz, float lambda){
int ix = 16 * blockIdx.x + threadIdx.x;
int iy = 16 * blockIdx.y + threadIdx.y;
int iz = 4 * blockIdx.z + threadIdx.z;
if (ix >= nx || iy >= ny || iz >= nz)
return;
int id = ix + iy * nx + iz * nx * ny;
img1[id] -= lambda * img[id];
if (img1[id] < 0.0f)
img1[id] = 0.0f;
if (img1[id] > 5000.0f)
img1[id] = 0.0f;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void kernel_update(float *img1, float *img, int nx, int ny, int nz, float lambda){
int ix = 16 * blockIdx.x + threadIdx.x;
int iy = 16 * blockIdx.y + threadIdx.y;
int iz = 4 * blockIdx.z + threadIdx.z;
if (ix >= nx || iy >= ny || iz >= nz)
return;
int id = ix + iy * nx + iz * nx * ny;
img1[id] -= lambda * img[id];
if (img1[id] < 0.0f)
img1[id] = 0.0f;
if (img1[id] > 5000.0f)
img1[id] = 0.0f;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13kernel_updatePfS_iiif
.globl _Z13kernel_updatePfS_iiif
.p2align 8
.type _Z13kernel_updatePfS_iiif,@function
_Z13kernel_updatePfS_iiif:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b32 s3, s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v2, v0, 10, 10
v_bfe_u32 v3, v0, 20, 10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshl_add_u32 v0, s13, 4, v1
v_lshl_add_u32 v1, s14, 4, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshl_add_u32 v2, s15, 2, v3
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e64 s2, s5, v1
v_cmp_gt_i32_e64 s3, s3, v2
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
v_mad_u64_u32 v[3:4], null, v2, s5, v[1:2]
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x1c
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, v3, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s10, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_fma_f32 v2, -v2, s0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_ngt_f32_e32 vcc_lo, 0, v2
v_cndmask_b32_e32 v2, 0, v2, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x459c4000, v2
v_cndmask_b32_e32 v2, 0, v2, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13kernel_updatePfS_iiif
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13kernel_updatePfS_iiif, .Lfunc_end0-_Z13kernel_updatePfS_iiif
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13kernel_updatePfS_iiif
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13kernel_updatePfS_iiif.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void kernel_update(float *img1, float *img, int nx, int ny, int nz, float lambda){
int ix = 16 * blockIdx.x + threadIdx.x;
int iy = 16 * blockIdx.y + threadIdx.y;
int iz = 4 * blockIdx.z + threadIdx.z;
if (ix >= nx || iy >= ny || iz >= nz)
return;
int id = ix + iy * nx + iz * nx * ny;
img1[id] -= lambda * img[id];
if (img1[id] < 0.0f)
img1[id] = 0.0f;
if (img1[id] > 5000.0f)
img1[id] = 0.0f;
} | .text
.file "kernel_update.hip"
.globl _Z28__device_stub__kernel_updatePfS_iiif # -- Begin function _Z28__device_stub__kernel_updatePfS_iiif
.p2align 4, 0x90
.type _Z28__device_stub__kernel_updatePfS_iiif,@function
_Z28__device_stub__kernel_updatePfS_iiif: # @_Z28__device_stub__kernel_updatePfS_iiif
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movss %xmm0, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13kernel_updatePfS_iiif, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z28__device_stub__kernel_updatePfS_iiif, .Lfunc_end0-_Z28__device_stub__kernel_updatePfS_iiif
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13kernel_updatePfS_iiif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13kernel_updatePfS_iiif,@object # @_Z13kernel_updatePfS_iiif
.section .rodata,"a",@progbits
.globl _Z13kernel_updatePfS_iiif
.p2align 3, 0x0
_Z13kernel_updatePfS_iiif:
.quad _Z28__device_stub__kernel_updatePfS_iiif
.size _Z13kernel_updatePfS_iiif, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13kernel_updatePfS_iiif"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__kernel_updatePfS_iiif
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13kernel_updatePfS_iiif
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13kernel_updatePfS_iiif
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002600 */
/*0020*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e680000002100 */
/*0050*/ S2R R4, SR_CTAID.Z ; /* 0x0000000000047919 */
/* 0x000ea80000002700 */
/*0060*/ S2R R7, SR_TID.Z ; /* 0x0000000000077919 */
/* 0x000ea20000002300 */
/*0070*/ LEA R2, R2, R5, 0x4 ; /* 0x0000000502027211 */
/* 0x001fc800078e20ff */
/*0080*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x174], PT ; /* 0x00005d0002007a0c */
/* 0x000fe20003f06270 */
/*0090*/ IMAD R0, R0, 0x10, R3 ; /* 0x0000001000007824 */
/* 0x002fca00078e0203 */
/*00a0*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fe40000706670 */
/*00b0*/ LEA R3, R4, R7, 0x2 ; /* 0x0000000704037211 */
/* 0x004fc800078e10ff */
/*00c0*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ IMAD R3, R3, c[0x0][0x174], R2 ; /* 0x00005d0003037a24 */
/* 0x000fe200078e0202 */
/*00f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0100*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe400078e00ff */
/*0110*/ IMAD R0, R3, c[0x0][0x170], R0 ; /* 0x00005c0003007a24 */
/* 0x000fc800078e0200 */
/*0120*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0205 */
/*0130*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fe400078e0205 */
/*0140*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0150*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1900 */
/*0160*/ FFMA R7, -R2, c[0x0][0x17c], R7 ; /* 0x00005f0002077a23 */
/* 0x004fca0000000107 */
/*0170*/ FSETP.GEU.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720b */
/* 0x000fc80003f0e000 */
/*0180*/ FSEL R7, R7, RZ, P0 ; /* 0x000000ff07077208 */
/* 0x000fc80000000000 */
/*0190*/ FSETP.GT.AND P0, PT, R7, 5000, PT ; /* 0x459c40000700780b */
/* 0x000fe20003f04000 */
/*01a0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001d8000c101904 */
/*01b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*01c0*/ STG.E [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x001fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13kernel_updatePfS_iiif
.globl _Z13kernel_updatePfS_iiif
.p2align 8
.type _Z13kernel_updatePfS_iiif,@function
_Z13kernel_updatePfS_iiif:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b32 s3, s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v2, v0, 10, 10
v_bfe_u32 v3, v0, 20, 10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshl_add_u32 v0, s13, 4, v1
v_lshl_add_u32 v1, s14, 4, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshl_add_u32 v2, s15, 2, v3
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e64 s2, s5, v1
v_cmp_gt_i32_e64 s3, s3, v2
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
v_mad_u64_u32 v[3:4], null, v2, s5, v[1:2]
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x1c
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, v3, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s10, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_fma_f32 v2, -v2, s0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_ngt_f32_e32 vcc_lo, 0, v2
v_cndmask_b32_e32 v2, 0, v2, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x459c4000, v2
v_cndmask_b32_e32 v2, 0, v2, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13kernel_updatePfS_iiif
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13kernel_updatePfS_iiif, .Lfunc_end0-_Z13kernel_updatePfS_iiif
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13kernel_updatePfS_iiif
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13kernel_updatePfS_iiif.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00063db9_00000000-6_kernel_update.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z13kernel_updatePfS_iiifPfS_iiif
.type _Z39__device_stub__Z13kernel_updatePfS_iiifPfS_iiif, @function
_Z39__device_stub__Z13kernel_updatePfS_iiifPfS_iiif:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movss %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13kernel_updatePfS_iiif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z13kernel_updatePfS_iiifPfS_iiif, .-_Z39__device_stub__Z13kernel_updatePfS_iiifPfS_iiif
.globl _Z13kernel_updatePfS_iiif
.type _Z13kernel_updatePfS_iiif, @function
_Z13kernel_updatePfS_iiif:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z13kernel_updatePfS_iiifPfS_iiif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13kernel_updatePfS_iiif, .-_Z13kernel_updatePfS_iiif
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13kernel_updatePfS_iiif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13kernel_updatePfS_iiif(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel_update.hip"
.globl _Z28__device_stub__kernel_updatePfS_iiif # -- Begin function _Z28__device_stub__kernel_updatePfS_iiif
.p2align 4, 0x90
.type _Z28__device_stub__kernel_updatePfS_iiif,@function
_Z28__device_stub__kernel_updatePfS_iiif: # @_Z28__device_stub__kernel_updatePfS_iiif
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movss %xmm0, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13kernel_updatePfS_iiif, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z28__device_stub__kernel_updatePfS_iiif, .Lfunc_end0-_Z28__device_stub__kernel_updatePfS_iiif
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13kernel_updatePfS_iiif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13kernel_updatePfS_iiif,@object # @_Z13kernel_updatePfS_iiif
.section .rodata,"a",@progbits
.globl _Z13kernel_updatePfS_iiif
.p2align 3, 0x0
_Z13kernel_updatePfS_iiif:
.quad _Z28__device_stub__kernel_updatePfS_iiif
.size _Z13kernel_updatePfS_iiif, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13kernel_updatePfS_iiif"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__kernel_updatePfS_iiif
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13kernel_updatePfS_iiif
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h> | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h> | .file "tmpxft_00155c98_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
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