system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <fstream>
#include <vector>
#include <string>
#include <sstream>
#include <iostream>
#include <cuda.h>
using namespace std;
__global__ void Dim2_Calculation(float * __restrict__ d_tem_res, float * __restrict__ d_tem_meo,
const float * __restrict__ d_tem_fix, const int width, const int height, const float k)
{
const int curId = blockIdx.x * blockDim.x + threadIdx.x;
const int w = curId/height;
const int h = curId - w*height;
int top, down, left, right;
if( w<width && h<height){
//float tmp = 0;
if (w>0){
//printf("(w-1)*height+h = %d\n", (w-1)*height+h);
//tmp += k * ( - d_tem_meo[curId] + d_tem_meo[(w-1)*height+h]);
left = w-1;
}else{
left=w;
}
if (w<width-1){
//printf("(w+1)*height+h = %d\n", (w+1)*height+h);
//tmp += k * ( - d_tem_meo[curId] + d_tem_meo[(w+1)*height+h]);
right = w+1;
}else{
right = w;
}
if (h>0){
//printf("(w)*height+h-1 = %d\n", (w)*height+h-1);
//tmp += k * ( - d_tem_meo[curId] + d_tem_meo[w*height+(h-1)]);
top = h-1;
}else{
top = h;
}
if (h<height-1){
//printf("(w)*height+h+1 = %d\n", (w)*height+h+1);
//tmp += k * ( - d_tem_meo[curId] + d_tem_meo[w*height+(h+1)]);
down = h+1;
}else{
down = h;
}
d_tem_res[curId] = d_tem_meo[curId]+k*(d_tem_meo[left*height+h]+d_tem_meo[right*height+h]
+ d_tem_meo[w*height+top] + d_tem_meo[w*height+down] - 4*d_tem_meo[curId]);
}
if ( d_tem_fix[curId] != -1){
d_tem_res[curId] = d_tem_fix[curId];
}
// wait until other thread if finished.
__syncthreads();
d_tem_meo[curId] = d_tem_res[curId];
}
__global__ void Dim3_Calculation(float * __restrict__ d_tem_res, float * __restrict__ d_tem_meo,
const float * __restrict__ d_tem_fix, const int width, const int height, const int depth, const float k)
{
const int curId = blockIdx.x * blockDim.x + threadIdx.x;
const int d = curId/(height*width);
const int w = (curId-d*(height*width))/height;
const int h = curId-d*(height*width) - w*height;
int top, down, left, right, front, back;
if( w<width && h<height && d<depth){
if (w>0){
left = w-1;
}else{
left=w;
}
if (w<width-1){
right = w+1;
}else{
right = w;
}
if (h>0){
top = h-1;
}else{
top = h;
}
if (h<height-1){
down = h+1;
}else{
down = h;
}
if (d>0){
front = d-1;
}else{
front = d;
}
if (d<depth-1){
back = d+1;
}else{
back = d;
}
d_tem_res[curId] = d_tem_meo[curId]+k*(d_tem_meo[d*(height*width)+left*height+h]+d_tem_meo[d*(height*width)+right*height+h]
+ d_tem_meo[d*(height*width)+w*height+top] + d_tem_meo[d*(height*width)+w*height+down]
+ d_tem_meo[front*(height*width)+w*height+h] + d_tem_meo[back*(height*width)+w*height+h] - 6*d_tem_meo[curId]);
}
if ( d_tem_fix[curId] != -1){
d_tem_res[curId] = d_tem_fix[curId];
}
// wait until other thread if finished.
__syncthreads();
d_tem_meo[curId] = d_tem_res[curId];
}
int main(int argc,char**argv)
{
// ------------------------------------ initial parameter --------------------------------------
string Dimension;
string path = argv[1];
ifstream cfile(path.c_str());
int timestep, width, height, depth, totalLength;
int location_x, location_y, location_z, fix_width, fix_height, fix_depth;
float init_temp, ftemp, k;
float *tem_res, *tem_meo, *tem_fix;
float *d_tem_res, *d_tem_meo, *d_tem_fix;
// ------------------------------------Reading the config file ---------------------------------------
string l;
vector<string> fileContent;
while(getline(cfile, l))
{
if(l[0] != '#' && !l.empty())
{fileContent.push_back(l);}
}
// -------------------------Dimension, k, timestep, init_temp---------------------------
Dimension = fileContent[0];
if(fileContent[1][0]=='.')
{fileContent[1].insert(fileContent[1].begin(), '0');}
k = (float)atof(fileContent[1].c_str());
timestep = atoi(fileContent[2].c_str());
init_temp = (float)atof(fileContent[4].c_str());
cout << "k=" << k << " timestep=" << timestep << " BeginTemperture=" << init_temp << endl;
// --------------------begin calculation based on Dimension----------------------
// read width and height, then build the matrix.
if(Dimension=="2D")
{
string::size_type pos = fileContent[3].find(",");
width = atoi(fileContent[3].substr(0, pos).c_str());
height = atoi(fileContent[3].substr(pos+1).c_str());
cout << "Width=" << width << " Height=" << height << endl;
totalLength = width*height;
}
else{
string::size_type pos = fileContent[3].find(",");
string::size_type pos2 = fileContent[3].find_last_of(",");
width = atoi(fileContent[3].substr(0, pos).c_str());
height = atoi(fileContent[3].substr(pos+1,pos2-pos-1).c_str());
depth = atoi(fileContent[3].substr(pos2+1).c_str());
cout << "Width=" << width << " Height=" << height << " Depth="<< depth << endl;
totalLength = width*height*depth;
}
tem_res = (float *)malloc(totalLength * sizeof(float));
tem_meo = (float *)malloc(totalLength * sizeof(float));
tem_fix = (float *)malloc(totalLength * sizeof(float));
for (int i = 0; i < totalLength; ++i)
{
tem_res[i] = init_temp;
tem_meo[i] = init_temp;
tem_fix[i] = -1;
}
// ------------------------ initialize matrix ----------------------------------
if(Dimension=="2D")
{
for(int i=5; i<fileContent.size(); i++)
{
string s = fileContent[i];
location_x = atoi(s.substr(0,s.find(",")).c_str());
s.erase(0,s.find(",")+1);
location_y = atoi(s.substr(0,s.find(",")).c_str());
s.erase(0,s.find(",")+1);
fix_width = atoi(s.substr(0,s.find(",")).c_str());
s.erase(0,s.find(",")+1);
fix_height = atoi(s.substr(0,s.find(",")).c_str());
s.erase(0,s.find(",")+1);
ftemp = (float)atof(s.c_str());
for(int w=location_x; w<location_x+fix_width; w++)
{
for(int h=location_y; h<location_y+fix_height; h++)
{
tem_res[w*height+h] = ftemp;
tem_meo[w*height+h] = ftemp;
tem_fix[w*height+h] = ftemp;
}
}
}
//for (int i=0; i<totalLength; i++){cout << tem_fix[i] << endl;}
}
else{
for(int i=5; i<fileContent.size(); i++)
{
string s = fileContent[i];
location_x = atoi(s.substr(0,s.find(",")).c_str());
s.erase(0,s.find(",")+1);
location_y = atoi(s.substr(0,s.find(",")).c_str());
s.erase(0,s.find(",")+1);
location_z = atoi(s.substr(0,s.find(",")).c_str());
s.erase(0,s.find(",")+1);
fix_width = atoi(s.substr(0,s.find(",")).c_str());
s.erase(0,s.find(",")+1);
fix_height = atoi(s.substr(0,s.find(",")).c_str());
s.erase(0,s.find(",")+1);
fix_depth = atoi(s.substr(0,s.find(",")).c_str());
s.erase(0,s.find(",")+1);
ftemp = (float)atof(s.c_str());
for(int w=location_x; w<location_x+fix_width; w++)
{
for(int h=location_y; h<location_y+fix_height; h++)
{
for(int d=location_z; d<location_z+fix_depth; d++)
{
tem_res[d*width*height + w*height + h] = ftemp;
tem_meo[d*width*height + w*height + h] = ftemp;
tem_fix[d*width*height + w*height + h] = ftemp;
}
}
}
}
//for (int i=0; i<totalLength; i++){cout << tem_fix[i] << endl;}
}
cudaMalloc((void **)&d_tem_res, totalLength * sizeof(float));
cudaMalloc((void **)&d_tem_meo, totalLength * sizeof(float));
cudaMalloc((void **)&d_tem_fix, totalLength * sizeof(float));
cudaMemcpy(d_tem_res, tem_res, totalLength * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_tem_meo, tem_meo, totalLength * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_tem_fix, tem_fix, totalLength * sizeof(float), cudaMemcpyHostToDevice);
// ----------------------- call Cuda Calculation -----------------------------------
cout << "You begin Cuda Calculation" << endl;
int bknum = 128;
if(Dimension=="2D")
{
for (int i = 0; i < timestep; i++)
{
//cout << "Cuda Calculation " << i <<endl;
Dim2_Calculation <<<(totalLength+bknum-1)/bknum, bknum>>>(d_tem_res, d_tem_meo, d_tem_fix, width, height, k);
}
cudaMemcpy(tem_res, d_tem_res, totalLength*sizeof(float), cudaMemcpyDeviceToHost);
}
else
{
for (int i = 0; i < timestep; i++)
{
Dim3_Calculation <<<(totalLength+bknum-1)/bknum, bknum>>>(d_tem_res, d_tem_meo, d_tem_fix, width, height, depth, k);
}
cudaMemcpy(tem_res, d_tem_res, totalLength*sizeof(float), cudaMemcpyDeviceToHost);
}
// ------------------------- Writing into output.csv -------------------------------
ofstream result;
result.open("heatOutput.csv");
if(Dimension=="2D")
{
for (int w = 0; w < width; w++)
{
for (int h = 0; h < height; h++)
{
result << tem_res[w*height+h];
if(h<height-1)
{result << ",";}
}
result << '\n';
}
}
else
{
for(int d=0; d<depth; d++)
{
for (int w = 0; w < width; w++)
{
for (int h = 0; h < height; h++)
{
result << tem_res[d*width*height+w*height+h];
if(h<height-1)
{result << ",";}
}
result << '\n';
}
result << '\n';
}
}
result.close();
// -------------------- free meomery -------------------
cudaFree(d_tem_res);
cudaFree(d_tem_meo);
cudaFree(d_tem_fix);
free(tem_res);
free(tem_meo);
free(tem_fix);
return 0;
} | code for sm_80
Function : _Z16Dim3_CalculationPfS_PKfiiif
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R9, R9, c[0x0][0x0], R0 ; /* 0x0000000009097a24 */
/* 0x001fca00078e0200 */
/*0050*/ SHF.R.S32.HI R0, RZ, 0x1f, R9 ; /* 0x0000001fff007819 */
/* 0x000fe40000011409 */
/*0060*/ LEA R2, P0, R9, c[0x0][0x170], 0x2 ; /* 0x00005c0009027a11 */
/* 0x000fc800078010ff */
/*0070*/ LEA.HI.X R3, R9, c[0x0][0x174], R0, 0x2, P0 ; /* 0x00005d0009037a11 */
/* 0x000fca00000f1400 */
/*0080*/ LDG.E.CONSTANT R7, [R2.64] ; /* 0x0000000602077981 */
/* 0x0000a2000c1e9900 */
/*0090*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff087624 */
/* 0x000fe200078e00ff */
/*00a0*/ IABS R12, R9 ; /* 0x00000009000c7213 */
/* 0x000fe20000000000 */
/*00b0*/ BSSY B0, 0x7c0 ; /* 0x0000070000007945 */
/* 0x000fe40003800000 */
/*00c0*/ IMAD R0, R8, c[0x0][0x178], RZ ; /* 0x00005e0008007a24 */
/* 0x000fca00078e02ff */
/*00d0*/ IABS R10, R0.reuse ; /* 0x00000000000a7213 */
/* 0x080fe40000000000 */
/*00e0*/ IABS R2, R0 ; /* 0x0000000000027213 */
/* 0x001fe40000000000 */
/*00f0*/ I2F.RP R6, R10 ; /* 0x0000000a00067306 */
/* 0x000e300000209400 */
/*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0130*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*0140*/ IMAD.MOV R11, RZ, RZ, -R5 ; /* 0x000000ffff0b7224 */
/* 0x002fc800078e0a05 */
/*0150*/ IMAD R3, R11, R10, RZ ; /* 0x0000000a0b037224 */
/* 0x000fe200078e02ff */
/*0160*/ IABS R11, c[0x0][0x17c] ; /* 0x00005f00000b7a13 */
/* 0x000fc80000000000 */
/*0170*/ IMAD.HI.U32 R5, R5, R3, R4 ; /* 0x0000000305057227 */
/* 0x000fc800078e0004 */
/*0180*/ IMAD.MOV R3, RZ, RZ, -R2 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0a02 */
/*0190*/ IMAD.MOV.U32 R2, RZ, RZ, R11 ; /* 0x000000ffff027224 */
/* 0x000fe400078e000b */
/*01a0*/ IMAD.HI.U32 R13, R5, R12, RZ ; /* 0x0000000c050d7227 */
/* 0x000fe400078e00ff */
/*01b0*/ I2F.RP R6, R2 ; /* 0x0000000200067306 */
/* 0x000e240000209400 */
/*01c0*/ IMAD R3, R13, R3, R12 ; /* 0x000000030d037224 */
/* 0x000fca00078e020c */
/*01d0*/ ISETP.GT.U32.AND P1, PT, R10, R3, PT ; /* 0x000000030a00720c */
/* 0x000fe20003f24070 */
/*01e0*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e180000001000 */
/*01f0*/ @!P1 IADD3 R3, R3, -R10.reuse, RZ ; /* 0x8000000a03039210 */
/* 0x080fe40007ffe0ff */
/*0200*/ @!P1 IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d9810 */
/* 0x000fe40007ffe0ff */
/*0210*/ ISETP.GE.U32.AND P0, PT, R3, R10, PT ; /* 0x0000000a0300720c */
/* 0x000fe40003f06070 */
/*0220*/ LOP3.LUT R3, R9, R0, RZ, 0x3c, !PT ; /* 0x0000000009037212 */
/* 0x000fe400078e3cff */
/*0230*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f25270 */
/*0240*/ ISETP.GE.AND P2, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fc40003f46270 */
/*0250*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fc80007ffe0ff */
/*0260*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000062000021f000 */
/*0270*/ @P0 IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d0810 */
/* 0x000fcc0007ffe0ff */
/*0280*/ @!P2 IMAD.MOV R13, RZ, RZ, -R13 ; /* 0x000000ffff0da224 */
/* 0x000fe200078e0a0d */
/*0290*/ @!P1 LOP3.LUT R13, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff0d9212 */
/* 0x000fe200078e33ff */
/*02a0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fc800078e00ff */
/*02b0*/ IMAD R10, R0, R13, RZ ; /* 0x0000000d000a7224 */
/* 0x000fe400078e02ff */
/*02c0*/ IMAD.MOV R3, RZ, RZ, -R5 ; /* 0x000000ffff037224 */
/* 0x002fc600078e0a05 */
/*02d0*/ IADD3 R11, R9, -R10, RZ ; /* 0x8000000a090b7210 */
/* 0x000fe20007ffe0ff */
/*02e0*/ IMAD R3, R3, R2, RZ ; /* 0x0000000203037224 */
/* 0x000fc600078e02ff */
/*02f0*/ IABS R6, R11 ; /* 0x0000000b00067213 */
/* 0x000fe20000000000 */
/*0300*/ IMAD.HI.U32 R4, R5, R3, R4 ; /* 0x0000000305047227 */
/* 0x000fc800078e0004 */
/*0310*/ IMAD.MOV.U32 R3, RZ, RZ, R6 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0006 */
/*0320*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x000fe400078e00ff */
/*0330*/ IMAD.HI.U32 R4, R4, R3, RZ ; /* 0x0000000304047227 */
/* 0x000fca00078e00ff */
/*0340*/ IADD3 R5, -R4, RZ, RZ ; /* 0x000000ff04057210 */
/* 0x000fca0007ffe1ff */
/*0350*/ IMAD R3, R2, R5, R3 ; /* 0x0000000502037224 */
/* 0x000fca00078e0203 */
/*0360*/ ISETP.GT.U32.AND P1, PT, R2, R3, PT ; /* 0x000000030200720c */
/* 0x000fda0003f24070 */
/*0370*/ @!P1 IMAD.IADD R3, R3, 0x1, -R2 ; /* 0x0000000103039824 */
/* 0x000fe200078e0a02 */
/*0380*/ @!P1 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104049810 */
/* 0x000fe40007ffe0ff */
/*0390*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fe40003f25270 */
/*03a0*/ ISETP.GE.U32.AND P0, PT, R3, R2, PT ; /* 0x000000020300720c */
/* 0x000fe40003f06070 */
/*03b0*/ LOP3.LUT R2, R11, c[0x0][0x17c], RZ, 0x3c, !PT ; /* 0x00005f000b027a12 */
/* 0x000fc800078e3cff */
/*03c0*/ ISETP.GE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fce0003f46270 */
/*03d0*/ @P0 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104040810 */
/* 0x000fca0007ffe0ff */
/*03e0*/ IMAD.MOV.U32 R14, RZ, RZ, R4 ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e0004 */
/*03f0*/ IMAD.WIDE R4, R9, R6, c[0x0][0x160] ; /* 0x0000580009047625 */
/* 0x000fc600078e0206 */
/*0400*/ @!P2 IADD3 R14, -R14, RZ, RZ ; /* 0x000000ff0e0ea210 */
/* 0x000fe40007ffe1ff */
/*0410*/ @!P1 LOP3.LUT R14, RZ, c[0x0][0x17c], RZ, 0x33, !PT ; /* 0x00005f00ff0e9a12 */
/* 0x000fca00078e33ff */
/*0420*/ IMAD.MOV R2, RZ, RZ, -R14 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0a0e */
/*0430*/ IMAD R17, R2, c[0x0][0x17c], R11 ; /* 0x00005f0002117a24 */
/* 0x000fe400078e020b */
/*0440*/ IMAD.WIDE R2, R9, R6, c[0x0][0x168] ; /* 0x00005a0009027625 */
/* 0x000fc600078e0206 */
/*0450*/ ISETP.GE.AND P0, PT, R17, c[0x0][0x17c], PT ; /* 0x00005f0011007a0c */
/* 0x000fc80003f06270 */
/*0460*/ ISETP.LT.AND P0, PT, R14, c[0x0][0x178], !P0 ; /* 0x00005e000e007a0c */
/* 0x000fc80004701270 */
/*0470*/ ISETP.LT.AND P0, PT, R13, c[0x0][0x180], P0 ; /* 0x000060000d007a0c */
/* 0x000fe40000701270 */
/*0480*/ FSETP.NEU.AND P1, PT, R7, -1, PT ; /* 0xbf8000000700780b */
/* 0x004fd60003f2d000 */
/*0490*/ @!P0 BRA 0x7b0 ; /* 0x0000031000008947 */
/* 0x000fea0003800000 */
/*04a0*/ ULDC UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe20000000800 */
/*04b0*/ ISETP.GT.AND P3, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe20003f64270 */
/*04c0*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*04d0*/ IADD3 R12, R8, -0x1, RZ ; /* 0xffffffff080c7810 */
/* 0x000fe40007ffe0ff */
/*04e0*/ ISETP.GT.AND P0, PT, R17.reuse, RZ, PT ; /* 0x000000ff1100720c */
/* 0x040fe40003f04270 */
/*04f0*/ ISETP.GE.AND P2, PT, R17, R12, PT ; /* 0x0000000c1100720c */
/* 0x000fe40003f46270 */
/*0500*/ ISETP.GE.AND P4, PT, R14.reuse, UR4, PT ; /* 0x000000040e007c0c */
/* 0x040fe2000bf86270 */
/*0510*/ ULDC UR4, c[0x0][0x180] ; /* 0x0000600000047ab9 */
/* 0x000fe20000000800 */
/*0520*/ IADD3 R8, R14, -0x1, RZ ; /* 0xffffffff0e087810 */
/* 0x000fe20007ffe0ff */
/*0530*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*0540*/ IADD3 R15, R10, R17, RZ ; /* 0x000000110a0f7210 */
/* 0x000fe20007ffe0ff */
/*0550*/ @!P3 IMAD.MOV R8, RZ, RZ, R14 ; /* 0x000000ffff08b224 */
/* 0x000fe200078e020e */
/*0560*/ IADD3 R10, R14, 0x1, RZ ; /* 0x000000010e0a7810 */
/* 0x000fc40007ffe0ff */
/*0570*/ ISETP.GT.AND P3, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe20003f64270 */
/*0580*/ IMAD R17, R8, c[0x0][0x17c], R15 ; /* 0x00005f0008117a24 */
/* 0x000fe200078e020f */
/*0590*/ IADD3 R21, R9.reuse, -0x1, RZ ; /* 0xffffffff09157810 */
/* 0x040fe40007ffe0ff */
/*05a0*/ IADD3 R23, R9, 0x1, RZ ; /* 0x0000000109177810 */
/* 0x000fe20007ffe0ff */
/*05b0*/ @P4 IMAD.MOV R10, RZ, RZ, R14 ; /* 0x000000ffff0a4224 */
/* 0x000fe200078e020e */
/*05c0*/ ISETP.GE.AND P4, PT, R13, UR4, PT ; /* 0x000000040d007c0c */
/* 0x000fe2000bf86270 */
/*05d0*/ @P2 IMAD.MOV R23, RZ, RZ, R9 ; /* 0x000000ffff172224 */
/* 0x000fe200078e0209 */
/*05e0*/ @!P0 IADD3 R21, R9, RZ, RZ ; /* 0x000000ff09158210 */
/* 0x000fe20007ffe0ff */
/*05f0*/ IMAD R19, R10, c[0x0][0x17c], R15 ; /* 0x00005f000a137a24 */
/* 0x000fe200078e020f */
/*0600*/ IADD3 R10, R13, -0x1, RZ ; /* 0xffffffff0d0a7810 */
/* 0x000fe20007ffe0ff */
/*0610*/ IMAD.WIDE R14, R17, R6, c[0x0][0x168] ; /* 0x00005a00110e7625 */
/* 0x000fe200078e0206 */
/*0620*/ IADD3 R18, R13, 0x1, RZ ; /* 0x000000010d127810 */
/* 0x000fc60007ffe0ff */
/*0630*/ IMAD.WIDE R8, R19, R6, c[0x0][0x168] ; /* 0x00005a0013087625 */
/* 0x000fe400078e0206 */
/*0640*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000ea4000c1e1900 */
/*0650*/ @!P3 IMAD.MOV R10, RZ, RZ, R13 ; /* 0x000000ffff0ab224 */
/* 0x000fe400078e020d */
/*0660*/ IMAD.WIDE R16, R6, R21, c[0x0][0x168] ; /* 0x00005a0006107625 */
/* 0x000fe200078e0215 */
/*0670*/ LDG.E R9, [R8.64] ; /* 0x0000000608097981 */
/* 0x000ea2000c1e1900 */
/*0680*/ @P4 IADD3 R18, R13, RZ, RZ ; /* 0x000000ff0d124210 */
/* 0x000fe40007ffe0ff */
/*0690*/ IMAD R19, R0, R10, R11 ; /* 0x0000000a00137224 */
/* 0x000fc400078e020b */
/*06a0*/ IMAD.WIDE R12, R6, R23, c[0x0][0x168] ; /* 0x00005a00060c7625 */
/* 0x000fe200078e0217 */
/*06b0*/ LDG.E R16, [R16.64] ; /* 0x0000000610107981 */
/* 0x000ee6000c1e1900 */
/*06c0*/ IMAD R21, R0, R18, R11 ; /* 0x0000001200157224 */
/* 0x000fe400078e020b */
/*06d0*/ IMAD.WIDE R10, R19, R6.reuse, c[0x0][0x168] ; /* 0x00005a00130a7625 */
/* 0x080fe200078e0206 */
/*06e0*/ LDG.E R12, [R12.64] ; /* 0x000000060c0c7981 */
/* 0x000f26000c1e1900 */
/*06f0*/ IMAD.WIDE R18, R21, R6, c[0x0][0x168] ; /* 0x00005a0015127625 */
/* 0x000fe200078e0206 */
/*0700*/ LDG.E R0, [R2.64] ; /* 0x0000000602007981 */
/* 0x000f68000c1e1900 */
/*0710*/ LDG.E R10, [R10.64] ; /* 0x000000060a0a7981 */
/* 0x000f68000c1e1900 */
/*0720*/ LDG.E R18, [R18.64] ; /* 0x0000000612127981 */
/* 0x000f62000c1e1900 */
/*0730*/ FADD R9, R9, R14 ; /* 0x0000000e09097221 */
/* 0x004fc80000000000 */
/*0740*/ FADD R9, R9, R16 ; /* 0x0000001009097221 */
/* 0x008fc80000000000 */
/*0750*/ FADD R9, R9, R12 ; /* 0x0000000c09097221 */
/* 0x010fc80000000000 */
/*0760*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x020fc80000000000 */
/*0770*/ FADD R9, R9, R18 ; /* 0x0000001209097221 */
/* 0x000fc80000000000 */
/*0780*/ FFMA R9, R0, -6, R9 ; /* 0xc0c0000000097823 */
/* 0x000fc80000000009 */
/*0790*/ FFMA R9, R9, c[0x0][0x184], R0 ; /* 0x0000610009097a23 */
/* 0x000fca0000000000 */
/*07a0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e4000c101906 */
/*07b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*07c0*/ BSSY B0, 0x820 ; /* 0x0000005000007945 */
/* 0x000fe20003800000 */
/*07d0*/ @P1 BRA 0x800 ; /* 0x0000002000001947 */
/* 0x000fea0003800000 */
/*07e0*/ LDG.E R7, [R4.64] ; /* 0x0000000604077981 */
/* 0x000362000c1e1900 */
/*07f0*/ BRA 0x810 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0800*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0003e4000c101906 */
/*0810*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0820*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0830*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x020fe2000c101906 */
/*0840*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0850*/ BRA 0x850; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z16Dim2_CalculationPfS_PKfiif
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0050*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fe40000011400 */
/*0060*/ LEA R2, P0, R0, c[0x0][0x170], 0x2 ; /* 0x00005c0000027a11 */
/* 0x000fc800078010ff */
/*0070*/ LEA.HI.X R3, R0, c[0x0][0x174], R3, 0x2, P0 ; /* 0x00005d0000037a11 */
/* 0x000fca00000f1403 */
/*0080*/ LDG.E.CONSTANT R7, [R2.64] ; /* 0x0000000602077981 */
/* 0x0000a2000c1e9900 */
/*0090*/ IABS R9, c[0x0][0x17c] ; /* 0x00005f0000097a13 */
/* 0x000fe20000000000 */
/*00a0*/ HFMA2.MMA R15, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0f7435 */
/* 0x000fe200000001ff */
/*00b0*/ BSSY B0, 0x4c0 ; /* 0x0000040000007945 */
/* 0x000fe40003800000 */
/*00c0*/ I2F.RP R6, R9 ; /* 0x0000000900067306 */
/* 0x000e620000209400 */
/*00d0*/ IABS R2, R0 ; /* 0x0000000000027213 */
/* 0x001fce0000000000 */
/*00e0*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x002e240000001000 */
/*00f0*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0100*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0110*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*0120*/ IMAD.MOV R8, RZ, RZ, -R5 ; /* 0x000000ffff087224 */
/* 0x002fc800078e0a05 */
/*0130*/ IMAD R11, R8, R9, RZ ; /* 0x00000009080b7224 */
/* 0x000fca00078e02ff */
/*0140*/ IMAD.HI.U32 R5, R5, R11, R4 ; /* 0x0000000b05057227 */
/* 0x000fcc00078e0004 */
/*0150*/ IMAD.HI.U32 R5, R5, R2, RZ ; /* 0x0000000205057227 */
/* 0x000fc800078e00ff */
/*0160*/ IMAD.MOV R3, RZ, RZ, -R5 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a05 */
/*0170*/ IMAD R2, R9, R3, R2 ; /* 0x0000000309027224 */
/* 0x000fca00078e0202 */
/*0180*/ ISETP.GT.U32.AND P1, PT, R9, R2, PT ; /* 0x000000020900720c */
/* 0x000fda0003f24070 */
/*0190*/ @!P1 IMAD.IADD R2, R2, 0x1, -R9 ; /* 0x0000000102029824 */
/* 0x000fe200078e0a09 */
/*01a0*/ @!P1 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105059810 */
/* 0x000fe40007ffe0ff */
/*01b0*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fe40003f25270 */
/*01c0*/ ISETP.GE.U32.AND P0, PT, R2, R9, PT ; /* 0x000000090200720c */
/* 0x000fe40003f06070 */
/*01d0*/ LOP3.LUT R2, R0, c[0x0][0x17c], RZ, 0x3c, !PT ; /* 0x00005f0000027a12 */
/* 0x000fc800078e3cff */
/*01e0*/ ISETP.GE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fce0003f46270 */
/*01f0*/ @P0 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105050810 */
/* 0x000fc80007ffe0ff */
/*0200*/ MOV R9, R5 ; /* 0x0000000500097202 */
/* 0x000fe20000000f00 */
/*0210*/ IMAD.WIDE R4, R0, R15, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc800078e020f */
/*0220*/ @!P2 IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff09a224 */
/* 0x000fe200078e0a09 */
/*0230*/ @!P1 LOP3.LUT R9, RZ, c[0x0][0x17c], RZ, 0x33, !PT ; /* 0x00005f00ff099a12 */
/* 0x000fca00078e33ff */
/*0240*/ IMAD.MOV R3, RZ, RZ, -R9 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a09 */
/*0250*/ IMAD R11, R3, c[0x0][0x17c], R0 ; /* 0x00005f00030b7a24 */
/* 0x000fe400078e0200 */
/*0260*/ IMAD.WIDE R2, R0, R15, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc600078e020f */
/*0270*/ ISETP.GE.AND P0, PT, R11, c[0x0][0x17c], PT ; /* 0x00005f000b007a0c */
/* 0x000fc80003f06270 */
/*0280*/ ISETP.LT.AND P0, PT, R9, c[0x0][0x178], !P0 ; /* 0x00005e0009007a0c */
/* 0x000fe40004701270 */
/*0290*/ FSETP.NEU.AND P1, PT, R7, -1, PT ; /* 0xbf8000000700780b */
/* 0x004fd60003f2d000 */
/*02a0*/ @!P0 BRA 0x4b0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*02b0*/ ULDC.64 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe20000000a00 */
/*02c0*/ ISETP.GT.AND P3, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f64270 */
/*02d0*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*02e0*/ ISETP.GT.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003f04270 */
/*02f0*/ LDG.E R17, [R2.64] ; /* 0x0000000602117981 */
/* 0x000ea2000c1e1900 */
/*0300*/ IADD3 R6, R9.reuse, -0x1, RZ ; /* 0xffffffff09067810 */
/* 0x040fe40007ffe0ff */
/*0310*/ IADD3 R8, R9.reuse, 0x1, RZ ; /* 0x0000000109087810 */
/* 0x040fe40007ffe0ff */
/*0320*/ ISETP.GE.AND P2, PT, R9, UR4, PT ; /* 0x0000000409007c0c */
/* 0x000fe2000bf46270 */
/*0330*/ UIADD3 UR4, UR5, -0x1, URZ ; /* 0xffffffff05047890 */
/* 0x000fe2000fffe03f */
/*0340*/ IADD3 R12, R0, -0x1, RZ ; /* 0xffffffff000c7810 */
/* 0x000fc40007ffe0ff */
/*0350*/ IADD3 R14, R0, 0x1, RZ ; /* 0x00000001000e7810 */
/* 0x000fe20007ffe0ff */
/*0360*/ @!P3 IMAD.MOV R6, RZ, RZ, R9 ; /* 0x000000ffff06b224 */
/* 0x000fe400078e0209 */
/*0370*/ ISETP.GE.AND P3, PT, R11, UR4, PT ; /* 0x000000040b007c0c */
/* 0x000fe2000bf66270 */
/*0380*/ @!P0 IMAD.MOV R12, RZ, RZ, R0 ; /* 0x000000ffff0c8224 */
/* 0x000fe400078e0200 */
/*0390*/ IMAD R6, R6, c[0x0][0x17c], R11 ; /* 0x00005f0006067a24 */
/* 0x000fc600078e020b */
/*03a0*/ @P2 IADD3 R8, R9, RZ, RZ ; /* 0x000000ff09082210 */
/* 0x000fca0007ffe0ff */
/*03b0*/ IMAD R10, R8, c[0x0][0x17c], R11 ; /* 0x00005f00080a7a24 */
/* 0x000fe400078e020b */
/*03c0*/ IMAD.WIDE R8, R6, R15, c[0x0][0x168] ; /* 0x00005a0006087625 */
/* 0x000fe200078e020f */
/*03d0*/ @P3 IADD3 R14, R0, RZ, RZ ; /* 0x000000ff000e3210 */
/* 0x000fc60007ffe0ff */
/*03e0*/ IMAD.WIDE R10, R10, R15, c[0x0][0x168] ; /* 0x00005a000a0a7625 */
/* 0x000fe400078e020f */
/*03f0*/ LDG.E R9, [R8.64] ; /* 0x0000000608097981 */
/* 0x000ee4000c1e1900 */
/*0400*/ IMAD.WIDE R12, R15.reuse, R12, c[0x0][0x168] ; /* 0x00005a000f0c7625 */
/* 0x040fe400078e020c */
/*0410*/ LDG.E R10, [R10.64] ; /* 0x000000060a0a7981 */
/* 0x000ee4000c1e1900 */
/*0420*/ IMAD.WIDE R14, R15, R14, c[0x0][0x168] ; /* 0x00005a000f0e7625 */
/* 0x000fe400078e020e */
/*0430*/ LDG.E R13, [R12.64] ; /* 0x000000060c0d7981 */
/* 0x000f28000c1e1900 */
/*0440*/ LDG.E R15, [R14.64] ; /* 0x000000060e0f7981 */
/* 0x000f62000c1e1900 */
/*0450*/ FADD R0, R10, R9 ; /* 0x000000090a007221 */
/* 0x008fc80000000000 */
/*0460*/ FADD R0, R0, R13 ; /* 0x0000000d00007221 */
/* 0x010fc80000000000 */
/*0470*/ FADD R0, R0, R15 ; /* 0x0000000f00007221 */
/* 0x020fc80000000000 */
/*0480*/ FFMA R0, R17, -4, R0 ; /* 0xc080000011007823 */
/* 0x004fc80000000000 */
/*0490*/ FFMA R17, R0, c[0x0][0x180], R17 ; /* 0x0000600000117a23 */
/* 0x000fca0000000011 */
/*04a0*/ STG.E [R4.64], R17 ; /* 0x0000001104007986 */
/* 0x0001e4000c101906 */
/*04b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04c0*/ BSSY B0, 0x520 ; /* 0x0000005000007945 */
/* 0x000fe20003800000 */
/*04d0*/ @P1 BRA 0x500 ; /* 0x0000002000001947 */
/* 0x000fea0003800000 */
/*04e0*/ LDG.E R7, [R4.64] ; /* 0x0000000604077981 */
/* 0x000362000c1e1900 */
/*04f0*/ BRA 0x510 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0500*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0003e4000c101906 */
/*0510*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0520*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0530*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x020fe2000c101906 */
/*0540*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0550*/ BRA 0x550; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <fstream>
#include <vector>
#include <string>
#include <sstream>
#include <iostream>
#include <cuda.h>
using namespace std;
__global__ void Dim2_Calculation(float * __restrict__ d_tem_res, float * __restrict__ d_tem_meo,
const float * __restrict__ d_tem_fix, const int width, const int height, const float k)
{
const int curId = blockIdx.x * blockDim.x + threadIdx.x;
const int w = curId/height;
const int h = curId - w*height;
int top, down, left, right;
if( w<width && h<height){
//float tmp = 0;
if (w>0){
//printf("(w-1)*height+h = %d\n", (w-1)*height+h);
//tmp += k * ( - d_tem_meo[curId] + d_tem_meo[(w-1)*height+h]);
left = w-1;
}else{
left=w;
}
if (w<width-1){
//printf("(w+1)*height+h = %d\n", (w+1)*height+h);
//tmp += k * ( - d_tem_meo[curId] + d_tem_meo[(w+1)*height+h]);
right = w+1;
}else{
right = w;
}
if (h>0){
//printf("(w)*height+h-1 = %d\n", (w)*height+h-1);
//tmp += k * ( - d_tem_meo[curId] + d_tem_meo[w*height+(h-1)]);
top = h-1;
}else{
top = h;
}
if (h<height-1){
//printf("(w)*height+h+1 = %d\n", (w)*height+h+1);
//tmp += k * ( - d_tem_meo[curId] + d_tem_meo[w*height+(h+1)]);
down = h+1;
}else{
down = h;
}
d_tem_res[curId] = d_tem_meo[curId]+k*(d_tem_meo[left*height+h]+d_tem_meo[right*height+h]
+ d_tem_meo[w*height+top] + d_tem_meo[w*height+down] - 4*d_tem_meo[curId]);
}
if ( d_tem_fix[curId] != -1){
d_tem_res[curId] = d_tem_fix[curId];
}
// wait until other thread if finished.
__syncthreads();
d_tem_meo[curId] = d_tem_res[curId];
}
__global__ void Dim3_Calculation(float * __restrict__ d_tem_res, float * __restrict__ d_tem_meo,
const float * __restrict__ d_tem_fix, const int width, const int height, const int depth, const float k)
{
const int curId = blockIdx.x * blockDim.x + threadIdx.x;
const int d = curId/(height*width);
const int w = (curId-d*(height*width))/height;
const int h = curId-d*(height*width) - w*height;
int top, down, left, right, front, back;
if( w<width && h<height && d<depth){
if (w>0){
left = w-1;
}else{
left=w;
}
if (w<width-1){
right = w+1;
}else{
right = w;
}
if (h>0){
top = h-1;
}else{
top = h;
}
if (h<height-1){
down = h+1;
}else{
down = h;
}
if (d>0){
front = d-1;
}else{
front = d;
}
if (d<depth-1){
back = d+1;
}else{
back = d;
}
d_tem_res[curId] = d_tem_meo[curId]+k*(d_tem_meo[d*(height*width)+left*height+h]+d_tem_meo[d*(height*width)+right*height+h]
+ d_tem_meo[d*(height*width)+w*height+top] + d_tem_meo[d*(height*width)+w*height+down]
+ d_tem_meo[front*(height*width)+w*height+h] + d_tem_meo[back*(height*width)+w*height+h] - 6*d_tem_meo[curId]);
}
if ( d_tem_fix[curId] != -1){
d_tem_res[curId] = d_tem_fix[curId];
}
// wait until other thread if finished.
__syncthreads();
d_tem_meo[curId] = d_tem_res[curId];
}
int main(int argc,char**argv)
{
// ------------------------------------ initial parameter --------------------------------------
string Dimension;
string path = argv[1];
ifstream cfile(path.c_str());
int timestep, width, height, depth, totalLength;
int location_x, location_y, location_z, fix_width, fix_height, fix_depth;
float init_temp, ftemp, k;
float *tem_res, *tem_meo, *tem_fix;
float *d_tem_res, *d_tem_meo, *d_tem_fix;
// ------------------------------------Reading the config file ---------------------------------------
string l;
vector<string> fileContent;
while(getline(cfile, l))
{
if(l[0] != '#' && !l.empty())
{fileContent.push_back(l);}
}
// -------------------------Dimension, k, timestep, init_temp---------------------------
Dimension = fileContent[0];
if(fileContent[1][0]=='.')
{fileContent[1].insert(fileContent[1].begin(), '0');}
k = (float)atof(fileContent[1].c_str());
timestep = atoi(fileContent[2].c_str());
init_temp = (float)atof(fileContent[4].c_str());
cout << "k=" << k << " timestep=" << timestep << " BeginTemperture=" << init_temp << endl;
// --------------------begin calculation based on Dimension----------------------
// read width and height, then build the matrix.
if(Dimension=="2D")
{
string::size_type pos = fileContent[3].find(",");
width = atoi(fileContent[3].substr(0, pos).c_str());
height = atoi(fileContent[3].substr(pos+1).c_str());
cout << "Width=" << width << " Height=" << height << endl;
totalLength = width*height;
}
else{
string::size_type pos = fileContent[3].find(",");
string::size_type pos2 = fileContent[3].find_last_of(",");
width = atoi(fileContent[3].substr(0, pos).c_str());
height = atoi(fileContent[3].substr(pos+1,pos2-pos-1).c_str());
depth = atoi(fileContent[3].substr(pos2+1).c_str());
cout << "Width=" << width << " Height=" << height << " Depth="<< depth << endl;
totalLength = width*height*depth;
}
tem_res = (float *)malloc(totalLength * sizeof(float));
tem_meo = (float *)malloc(totalLength * sizeof(float));
tem_fix = (float *)malloc(totalLength * sizeof(float));
for (int i = 0; i < totalLength; ++i)
{
tem_res[i] = init_temp;
tem_meo[i] = init_temp;
tem_fix[i] = -1;
}
// ------------------------ initialize matrix ----------------------------------
if(Dimension=="2D")
{
for(int i=5; i<fileContent.size(); i++)
{
string s = fileContent[i];
location_x = atoi(s.substr(0,s.find(",")).c_str());
s.erase(0,s.find(",")+1);
location_y = atoi(s.substr(0,s.find(",")).c_str());
s.erase(0,s.find(",")+1);
fix_width = atoi(s.substr(0,s.find(",")).c_str());
s.erase(0,s.find(",")+1);
fix_height = atoi(s.substr(0,s.find(",")).c_str());
s.erase(0,s.find(",")+1);
ftemp = (float)atof(s.c_str());
for(int w=location_x; w<location_x+fix_width; w++)
{
for(int h=location_y; h<location_y+fix_height; h++)
{
tem_res[w*height+h] = ftemp;
tem_meo[w*height+h] = ftemp;
tem_fix[w*height+h] = ftemp;
}
}
}
//for (int i=0; i<totalLength; i++){cout << tem_fix[i] << endl;}
}
else{
for(int i=5; i<fileContent.size(); i++)
{
string s = fileContent[i];
location_x = atoi(s.substr(0,s.find(",")).c_str());
s.erase(0,s.find(",")+1);
location_y = atoi(s.substr(0,s.find(",")).c_str());
s.erase(0,s.find(",")+1);
location_z = atoi(s.substr(0,s.find(",")).c_str());
s.erase(0,s.find(",")+1);
fix_width = atoi(s.substr(0,s.find(",")).c_str());
s.erase(0,s.find(",")+1);
fix_height = atoi(s.substr(0,s.find(",")).c_str());
s.erase(0,s.find(",")+1);
fix_depth = atoi(s.substr(0,s.find(",")).c_str());
s.erase(0,s.find(",")+1);
ftemp = (float)atof(s.c_str());
for(int w=location_x; w<location_x+fix_width; w++)
{
for(int h=location_y; h<location_y+fix_height; h++)
{
for(int d=location_z; d<location_z+fix_depth; d++)
{
tem_res[d*width*height + w*height + h] = ftemp;
tem_meo[d*width*height + w*height + h] = ftemp;
tem_fix[d*width*height + w*height + h] = ftemp;
}
}
}
}
//for (int i=0; i<totalLength; i++){cout << tem_fix[i] << endl;}
}
cudaMalloc((void **)&d_tem_res, totalLength * sizeof(float));
cudaMalloc((void **)&d_tem_meo, totalLength * sizeof(float));
cudaMalloc((void **)&d_tem_fix, totalLength * sizeof(float));
cudaMemcpy(d_tem_res, tem_res, totalLength * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_tem_meo, tem_meo, totalLength * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_tem_fix, tem_fix, totalLength * sizeof(float), cudaMemcpyHostToDevice);
// ----------------------- call Cuda Calculation -----------------------------------
cout << "You begin Cuda Calculation" << endl;
int bknum = 128;
if(Dimension=="2D")
{
for (int i = 0; i < timestep; i++)
{
//cout << "Cuda Calculation " << i <<endl;
Dim2_Calculation <<<(totalLength+bknum-1)/bknum, bknum>>>(d_tem_res, d_tem_meo, d_tem_fix, width, height, k);
}
cudaMemcpy(tem_res, d_tem_res, totalLength*sizeof(float), cudaMemcpyDeviceToHost);
}
else
{
for (int i = 0; i < timestep; i++)
{
Dim3_Calculation <<<(totalLength+bknum-1)/bknum, bknum>>>(d_tem_res, d_tem_meo, d_tem_fix, width, height, depth, k);
}
cudaMemcpy(tem_res, d_tem_res, totalLength*sizeof(float), cudaMemcpyDeviceToHost);
}
// ------------------------- Writing into output.csv -------------------------------
ofstream result;
result.open("heatOutput.csv");
if(Dimension=="2D")
{
for (int w = 0; w < width; w++)
{
for (int h = 0; h < height; h++)
{
result << tem_res[w*height+h];
if(h<height-1)
{result << ",";}
}
result << '\n';
}
}
else
{
for(int d=0; d<depth; d++)
{
for (int w = 0; w < width; w++)
{
for (int h = 0; h < height; h++)
{
result << tem_res[d*width*height+w*height+h];
if(h<height-1)
{result << ",";}
}
result << '\n';
}
result << '\n';
}
}
result.close();
// -------------------- free meomery -------------------
cudaFree(d_tem_res);
cudaFree(d_tem_meo);
cudaFree(d_tem_fix);
free(tem_res);
free(tem_meo);
free(tem_fix);
return 0;
} | #include <fstream>
#include <vector>
#include <string>
#include <sstream>
#include <iostream>
#include <hip/hip_runtime.h>
using namespace std;
__global__ void Dim2_Calculation(float * __restrict__ d_tem_res, float * __restrict__ d_tem_meo,
const float * __restrict__ d_tem_fix, const int width, const int height, const float k)
{
const int curId = blockIdx.x * blockDim.x + threadIdx.x;
const int w = curId/height;
const int h = curId - w*height;
int top, down, left, right;
if( w<width && h<height){
//float tmp = 0;
if (w>0){
//printf("(w-1)*height+h = %d\n", (w-1)*height+h);
//tmp += k * ( - d_tem_meo[curId] + d_tem_meo[(w-1)*height+h]);
left = w-1;
}else{
left=w;
}
if (w<width-1){
//printf("(w+1)*height+h = %d\n", (w+1)*height+h);
//tmp += k * ( - d_tem_meo[curId] + d_tem_meo[(w+1)*height+h]);
right = w+1;
}else{
right = w;
}
if (h>0){
//printf("(w)*height+h-1 = %d\n", (w)*height+h-1);
//tmp += k * ( - d_tem_meo[curId] + d_tem_meo[w*height+(h-1)]);
top = h-1;
}else{
top = h;
}
if (h<height-1){
//printf("(w)*height+h+1 = %d\n", (w)*height+h+1);
//tmp += k * ( - d_tem_meo[curId] + d_tem_meo[w*height+(h+1)]);
down = h+1;
}else{
down = h;
}
d_tem_res[curId] = d_tem_meo[curId]+k*(d_tem_meo[left*height+h]+d_tem_meo[right*height+h]
+ d_tem_meo[w*height+top] + d_tem_meo[w*height+down] - 4*d_tem_meo[curId]);
}
if ( d_tem_fix[curId] != -1){
d_tem_res[curId] = d_tem_fix[curId];
}
// wait until other thread if finished.
__syncthreads();
d_tem_meo[curId] = d_tem_res[curId];
}
__global__ void Dim3_Calculation(float * __restrict__ d_tem_res, float * __restrict__ d_tem_meo,
const float * __restrict__ d_tem_fix, const int width, const int height, const int depth, const float k)
{
const int curId = blockIdx.x * blockDim.x + threadIdx.x;
const int d = curId/(height*width);
const int w = (curId-d*(height*width))/height;
const int h = curId-d*(height*width) - w*height;
int top, down, left, right, front, back;
if( w<width && h<height && d<depth){
if (w>0){
left = w-1;
}else{
left=w;
}
if (w<width-1){
right = w+1;
}else{
right = w;
}
if (h>0){
top = h-1;
}else{
top = h;
}
if (h<height-1){
down = h+1;
}else{
down = h;
}
if (d>0){
front = d-1;
}else{
front = d;
}
if (d<depth-1){
back = d+1;
}else{
back = d;
}
d_tem_res[curId] = d_tem_meo[curId]+k*(d_tem_meo[d*(height*width)+left*height+h]+d_tem_meo[d*(height*width)+right*height+h]
+ d_tem_meo[d*(height*width)+w*height+top] + d_tem_meo[d*(height*width)+w*height+down]
+ d_tem_meo[front*(height*width)+w*height+h] + d_tem_meo[back*(height*width)+w*height+h] - 6*d_tem_meo[curId]);
}
if ( d_tem_fix[curId] != -1){
d_tem_res[curId] = d_tem_fix[curId];
}
// wait until other thread if finished.
__syncthreads();
d_tem_meo[curId] = d_tem_res[curId];
}
int main(int argc,char**argv)
{
// ------------------------------------ initial parameter --------------------------------------
string Dimension;
string path = argv[1];
ifstream cfile(path.c_str());
int timestep, width, height, depth, totalLength;
int location_x, location_y, location_z, fix_width, fix_height, fix_depth;
float init_temp, ftemp, k;
float *tem_res, *tem_meo, *tem_fix;
float *d_tem_res, *d_tem_meo, *d_tem_fix;
// ------------------------------------Reading the config file ---------------------------------------
string l;
vector<string> fileContent;
while(getline(cfile, l))
{
if(l[0] != '#' && !l.empty())
{fileContent.push_back(l);}
}
// -------------------------Dimension, k, timestep, init_temp---------------------------
Dimension = fileContent[0];
if(fileContent[1][0]=='.')
{fileContent[1].insert(fileContent[1].begin(), '0');}
k = (float)atof(fileContent[1].c_str());
timestep = atoi(fileContent[2].c_str());
init_temp = (float)atof(fileContent[4].c_str());
cout << "k=" << k << " timestep=" << timestep << " BeginTemperture=" << init_temp << endl;
// --------------------begin calculation based on Dimension----------------------
// read width and height, then build the matrix.
if(Dimension=="2D")
{
string::size_type pos = fileContent[3].find(",");
width = atoi(fileContent[3].substr(0, pos).c_str());
height = atoi(fileContent[3].substr(pos+1).c_str());
cout << "Width=" << width << " Height=" << height << endl;
totalLength = width*height;
}
else{
string::size_type pos = fileContent[3].find(",");
string::size_type pos2 = fileContent[3].find_last_of(",");
width = atoi(fileContent[3].substr(0, pos).c_str());
height = atoi(fileContent[3].substr(pos+1,pos2-pos-1).c_str());
depth = atoi(fileContent[3].substr(pos2+1).c_str());
cout << "Width=" << width << " Height=" << height << " Depth="<< depth << endl;
totalLength = width*height*depth;
}
tem_res = (float *)malloc(totalLength * sizeof(float));
tem_meo = (float *)malloc(totalLength * sizeof(float));
tem_fix = (float *)malloc(totalLength * sizeof(float));
for (int i = 0; i < totalLength; ++i)
{
tem_res[i] = init_temp;
tem_meo[i] = init_temp;
tem_fix[i] = -1;
}
// ------------------------ initialize matrix ----------------------------------
if(Dimension=="2D")
{
for(int i=5; i<fileContent.size(); i++)
{
string s = fileContent[i];
location_x = atoi(s.substr(0,s.find(",")).c_str());
s.erase(0,s.find(",")+1);
location_y = atoi(s.substr(0,s.find(",")).c_str());
s.erase(0,s.find(",")+1);
fix_width = atoi(s.substr(0,s.find(",")).c_str());
s.erase(0,s.find(",")+1);
fix_height = atoi(s.substr(0,s.find(",")).c_str());
s.erase(0,s.find(",")+1);
ftemp = (float)atof(s.c_str());
for(int w=location_x; w<location_x+fix_width; w++)
{
for(int h=location_y; h<location_y+fix_height; h++)
{
tem_res[w*height+h] = ftemp;
tem_meo[w*height+h] = ftemp;
tem_fix[w*height+h] = ftemp;
}
}
}
//for (int i=0; i<totalLength; i++){cout << tem_fix[i] << endl;}
}
else{
for(int i=5; i<fileContent.size(); i++)
{
string s = fileContent[i];
location_x = atoi(s.substr(0,s.find(",")).c_str());
s.erase(0,s.find(",")+1);
location_y = atoi(s.substr(0,s.find(",")).c_str());
s.erase(0,s.find(",")+1);
location_z = atoi(s.substr(0,s.find(",")).c_str());
s.erase(0,s.find(",")+1);
fix_width = atoi(s.substr(0,s.find(",")).c_str());
s.erase(0,s.find(",")+1);
fix_height = atoi(s.substr(0,s.find(",")).c_str());
s.erase(0,s.find(",")+1);
fix_depth = atoi(s.substr(0,s.find(",")).c_str());
s.erase(0,s.find(",")+1);
ftemp = (float)atof(s.c_str());
for(int w=location_x; w<location_x+fix_width; w++)
{
for(int h=location_y; h<location_y+fix_height; h++)
{
for(int d=location_z; d<location_z+fix_depth; d++)
{
tem_res[d*width*height + w*height + h] = ftemp;
tem_meo[d*width*height + w*height + h] = ftemp;
tem_fix[d*width*height + w*height + h] = ftemp;
}
}
}
}
//for (int i=0; i<totalLength; i++){cout << tem_fix[i] << endl;}
}
hipMalloc((void **)&d_tem_res, totalLength * sizeof(float));
hipMalloc((void **)&d_tem_meo, totalLength * sizeof(float));
hipMalloc((void **)&d_tem_fix, totalLength * sizeof(float));
hipMemcpy(d_tem_res, tem_res, totalLength * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_tem_meo, tem_meo, totalLength * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_tem_fix, tem_fix, totalLength * sizeof(float), hipMemcpyHostToDevice);
// ----------------------- call Cuda Calculation -----------------------------------
cout << "You begin Cuda Calculation" << endl;
int bknum = 128;
if(Dimension=="2D")
{
for (int i = 0; i < timestep; i++)
{
//cout << "Cuda Calculation " << i <<endl;
Dim2_Calculation <<<(totalLength+bknum-1)/bknum, bknum>>>(d_tem_res, d_tem_meo, d_tem_fix, width, height, k);
}
hipMemcpy(tem_res, d_tem_res, totalLength*sizeof(float), hipMemcpyDeviceToHost);
}
else
{
for (int i = 0; i < timestep; i++)
{
Dim3_Calculation <<<(totalLength+bknum-1)/bknum, bknum>>>(d_tem_res, d_tem_meo, d_tem_fix, width, height, depth, k);
}
hipMemcpy(tem_res, d_tem_res, totalLength*sizeof(float), hipMemcpyDeviceToHost);
}
// ------------------------- Writing into output.csv -------------------------------
ofstream result;
result.open("heatOutput.csv");
if(Dimension=="2D")
{
for (int w = 0; w < width; w++)
{
for (int h = 0; h < height; h++)
{
result << tem_res[w*height+h];
if(h<height-1)
{result << ",";}
}
result << '\n';
}
}
else
{
for(int d=0; d<depth; d++)
{
for (int w = 0; w < width; w++)
{
for (int h = 0; h < height; h++)
{
result << tem_res[d*width*height+w*height+h];
if(h<height-1)
{result << ",";}
}
result << '\n';
}
result << '\n';
}
}
result.close();
// -------------------- free meomery -------------------
hipFree(d_tem_res);
hipFree(d_tem_meo);
hipFree(d_tem_fix);
free(tem_res);
free(tem_meo);
free(tem_fix);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <fstream>
#include <vector>
#include <string>
#include <sstream>
#include <iostream>
#include <hip/hip_runtime.h>
using namespace std;
__global__ void Dim2_Calculation(float * __restrict__ d_tem_res, float * __restrict__ d_tem_meo,
const float * __restrict__ d_tem_fix, const int width, const int height, const float k)
{
const int curId = blockIdx.x * blockDim.x + threadIdx.x;
const int w = curId/height;
const int h = curId - w*height;
int top, down, left, right;
if( w<width && h<height){
//float tmp = 0;
if (w>0){
//printf("(w-1)*height+h = %d\n", (w-1)*height+h);
//tmp += k * ( - d_tem_meo[curId] + d_tem_meo[(w-1)*height+h]);
left = w-1;
}else{
left=w;
}
if (w<width-1){
//printf("(w+1)*height+h = %d\n", (w+1)*height+h);
//tmp += k * ( - d_tem_meo[curId] + d_tem_meo[(w+1)*height+h]);
right = w+1;
}else{
right = w;
}
if (h>0){
//printf("(w)*height+h-1 = %d\n", (w)*height+h-1);
//tmp += k * ( - d_tem_meo[curId] + d_tem_meo[w*height+(h-1)]);
top = h-1;
}else{
top = h;
}
if (h<height-1){
//printf("(w)*height+h+1 = %d\n", (w)*height+h+1);
//tmp += k * ( - d_tem_meo[curId] + d_tem_meo[w*height+(h+1)]);
down = h+1;
}else{
down = h;
}
d_tem_res[curId] = d_tem_meo[curId]+k*(d_tem_meo[left*height+h]+d_tem_meo[right*height+h]
+ d_tem_meo[w*height+top] + d_tem_meo[w*height+down] - 4*d_tem_meo[curId]);
}
if ( d_tem_fix[curId] != -1){
d_tem_res[curId] = d_tem_fix[curId];
}
// wait until other thread if finished.
__syncthreads();
d_tem_meo[curId] = d_tem_res[curId];
}
__global__ void Dim3_Calculation(float * __restrict__ d_tem_res, float * __restrict__ d_tem_meo,
const float * __restrict__ d_tem_fix, const int width, const int height, const int depth, const float k)
{
const int curId = blockIdx.x * blockDim.x + threadIdx.x;
const int d = curId/(height*width);
const int w = (curId-d*(height*width))/height;
const int h = curId-d*(height*width) - w*height;
int top, down, left, right, front, back;
if( w<width && h<height && d<depth){
if (w>0){
left = w-1;
}else{
left=w;
}
if (w<width-1){
right = w+1;
}else{
right = w;
}
if (h>0){
top = h-1;
}else{
top = h;
}
if (h<height-1){
down = h+1;
}else{
down = h;
}
if (d>0){
front = d-1;
}else{
front = d;
}
if (d<depth-1){
back = d+1;
}else{
back = d;
}
d_tem_res[curId] = d_tem_meo[curId]+k*(d_tem_meo[d*(height*width)+left*height+h]+d_tem_meo[d*(height*width)+right*height+h]
+ d_tem_meo[d*(height*width)+w*height+top] + d_tem_meo[d*(height*width)+w*height+down]
+ d_tem_meo[front*(height*width)+w*height+h] + d_tem_meo[back*(height*width)+w*height+h] - 6*d_tem_meo[curId]);
}
if ( d_tem_fix[curId] != -1){
d_tem_res[curId] = d_tem_fix[curId];
}
// wait until other thread if finished.
__syncthreads();
d_tem_meo[curId] = d_tem_res[curId];
}
int main(int argc,char**argv)
{
// ------------------------------------ initial parameter --------------------------------------
string Dimension;
string path = argv[1];
ifstream cfile(path.c_str());
int timestep, width, height, depth, totalLength;
int location_x, location_y, location_z, fix_width, fix_height, fix_depth;
float init_temp, ftemp, k;
float *tem_res, *tem_meo, *tem_fix;
float *d_tem_res, *d_tem_meo, *d_tem_fix;
// ------------------------------------Reading the config file ---------------------------------------
string l;
vector<string> fileContent;
while(getline(cfile, l))
{
if(l[0] != '#' && !l.empty())
{fileContent.push_back(l);}
}
// -------------------------Dimension, k, timestep, init_temp---------------------------
Dimension = fileContent[0];
if(fileContent[1][0]=='.')
{fileContent[1].insert(fileContent[1].begin(), '0');}
k = (float)atof(fileContent[1].c_str());
timestep = atoi(fileContent[2].c_str());
init_temp = (float)atof(fileContent[4].c_str());
cout << "k=" << k << " timestep=" << timestep << " BeginTemperture=" << init_temp << endl;
// --------------------begin calculation based on Dimension----------------------
// read width and height, then build the matrix.
if(Dimension=="2D")
{
string::size_type pos = fileContent[3].find(",");
width = atoi(fileContent[3].substr(0, pos).c_str());
height = atoi(fileContent[3].substr(pos+1).c_str());
cout << "Width=" << width << " Height=" << height << endl;
totalLength = width*height;
}
else{
string::size_type pos = fileContent[3].find(",");
string::size_type pos2 = fileContent[3].find_last_of(",");
width = atoi(fileContent[3].substr(0, pos).c_str());
height = atoi(fileContent[3].substr(pos+1,pos2-pos-1).c_str());
depth = atoi(fileContent[3].substr(pos2+1).c_str());
cout << "Width=" << width << " Height=" << height << " Depth="<< depth << endl;
totalLength = width*height*depth;
}
tem_res = (float *)malloc(totalLength * sizeof(float));
tem_meo = (float *)malloc(totalLength * sizeof(float));
tem_fix = (float *)malloc(totalLength * sizeof(float));
for (int i = 0; i < totalLength; ++i)
{
tem_res[i] = init_temp;
tem_meo[i] = init_temp;
tem_fix[i] = -1;
}
// ------------------------ initialize matrix ----------------------------------
if(Dimension=="2D")
{
for(int i=5; i<fileContent.size(); i++)
{
string s = fileContent[i];
location_x = atoi(s.substr(0,s.find(",")).c_str());
s.erase(0,s.find(",")+1);
location_y = atoi(s.substr(0,s.find(",")).c_str());
s.erase(0,s.find(",")+1);
fix_width = atoi(s.substr(0,s.find(",")).c_str());
s.erase(0,s.find(",")+1);
fix_height = atoi(s.substr(0,s.find(",")).c_str());
s.erase(0,s.find(",")+1);
ftemp = (float)atof(s.c_str());
for(int w=location_x; w<location_x+fix_width; w++)
{
for(int h=location_y; h<location_y+fix_height; h++)
{
tem_res[w*height+h] = ftemp;
tem_meo[w*height+h] = ftemp;
tem_fix[w*height+h] = ftemp;
}
}
}
//for (int i=0; i<totalLength; i++){cout << tem_fix[i] << endl;}
}
else{
for(int i=5; i<fileContent.size(); i++)
{
string s = fileContent[i];
location_x = atoi(s.substr(0,s.find(",")).c_str());
s.erase(0,s.find(",")+1);
location_y = atoi(s.substr(0,s.find(",")).c_str());
s.erase(0,s.find(",")+1);
location_z = atoi(s.substr(0,s.find(",")).c_str());
s.erase(0,s.find(",")+1);
fix_width = atoi(s.substr(0,s.find(",")).c_str());
s.erase(0,s.find(",")+1);
fix_height = atoi(s.substr(0,s.find(",")).c_str());
s.erase(0,s.find(",")+1);
fix_depth = atoi(s.substr(0,s.find(",")).c_str());
s.erase(0,s.find(",")+1);
ftemp = (float)atof(s.c_str());
for(int w=location_x; w<location_x+fix_width; w++)
{
for(int h=location_y; h<location_y+fix_height; h++)
{
for(int d=location_z; d<location_z+fix_depth; d++)
{
tem_res[d*width*height + w*height + h] = ftemp;
tem_meo[d*width*height + w*height + h] = ftemp;
tem_fix[d*width*height + w*height + h] = ftemp;
}
}
}
}
//for (int i=0; i<totalLength; i++){cout << tem_fix[i] << endl;}
}
hipMalloc((void **)&d_tem_res, totalLength * sizeof(float));
hipMalloc((void **)&d_tem_meo, totalLength * sizeof(float));
hipMalloc((void **)&d_tem_fix, totalLength * sizeof(float));
hipMemcpy(d_tem_res, tem_res, totalLength * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_tem_meo, tem_meo, totalLength * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_tem_fix, tem_fix, totalLength * sizeof(float), hipMemcpyHostToDevice);
// ----------------------- call Cuda Calculation -----------------------------------
cout << "You begin Cuda Calculation" << endl;
int bknum = 128;
if(Dimension=="2D")
{
for (int i = 0; i < timestep; i++)
{
//cout << "Cuda Calculation " << i <<endl;
Dim2_Calculation <<<(totalLength+bknum-1)/bknum, bknum>>>(d_tem_res, d_tem_meo, d_tem_fix, width, height, k);
}
hipMemcpy(tem_res, d_tem_res, totalLength*sizeof(float), hipMemcpyDeviceToHost);
}
else
{
for (int i = 0; i < timestep; i++)
{
Dim3_Calculation <<<(totalLength+bknum-1)/bknum, bknum>>>(d_tem_res, d_tem_meo, d_tem_fix, width, height, depth, k);
}
hipMemcpy(tem_res, d_tem_res, totalLength*sizeof(float), hipMemcpyDeviceToHost);
}
// ------------------------- Writing into output.csv -------------------------------
ofstream result;
result.open("heatOutput.csv");
if(Dimension=="2D")
{
for (int w = 0; w < width; w++)
{
for (int h = 0; h < height; h++)
{
result << tem_res[w*height+h];
if(h<height-1)
{result << ",";}
}
result << '\n';
}
}
else
{
for(int d=0; d<depth; d++)
{
for (int w = 0; w < width; w++)
{
for (int h = 0; h < height; h++)
{
result << tem_res[d*width*height+w*height+h];
if(h<height-1)
{result << ",";}
}
result << '\n';
}
result << '\n';
}
}
result.close();
// -------------------- free meomery -------------------
hipFree(d_tem_res);
hipFree(d_tem_meo);
hipFree(d_tem_fix);
free(tem_res);
free(tem_meo);
free(tem_fix);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16Dim2_CalculationPfS_PKfiif
.globl _Z16Dim2_CalculationPfS_PKfiif
.p2align 8
.type _Z16Dim2_CalculationPfS_PKfiif,@function
_Z16Dim2_CalculationPfS_PKfiif:
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x0
s_load_b32 s12, s[0:1], 0x34
s_waitcnt lgkmcnt(0)
s_ashr_i32 s2, s11, 31
s_and_b32 s12, s12, 0xffff
s_add_i32 s3, s11, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s3, s3, s2
v_cvt_f32_u32_e32 v1, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s15, s12, v[0:1]
s_sub_i32 s12, 0, s3
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v0, s12, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_mul_hi_u32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v2
v_xor_b32_e32 v4, v4, v2
v_xor_b32_e32 v2, s2, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v3, v0
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v0, s3
v_sub_nc_u32_e32 v3, v4, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s3, v3
v_cmp_le_u32_e32 vcc_lo, s3, v3
v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s3, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_xor_b32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v3, v0, v2
v_ashrrev_i32_e32 v2, 31, v1
v_mul_lo_u32 v0, v3, s11
v_cmp_gt_i32_e32 vcc_lo, s10, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v1, v0
v_cmp_gt_i32_e64 s2, s11, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, vcc_lo, s2
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_2
v_cmp_lt_i32_e32 vcc_lo, 0, v3
s_add_i32 s3, s10, -1
v_lshlrev_b64 v[11:12], 2, v[1:2]
s_load_b32 s0, s[0:1], 0x20
v_subrev_co_ci_u32_e32 v5, vcc_lo, 0, v3, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, s3, v3
s_add_i32 s3, s11, -1
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[3:4], null, v5, s11, v[0:1]
v_cmp_lt_i32_e32 vcc_lo, 0, v0
v_mad_u64_u32 v[5:6], null, v7, s11, v[0:1]
v_subrev_co_ci_u32_e32 v7, vcc_lo, 0, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, s3, v0
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v1, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v10, 31, v9
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_clause 0x2
global_load_b32 v0, v[3:4], off
global_load_b32 v13, v[5:6], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v3, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v10, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v12, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(3)
v_add_f32_e32 v0, v0, v13
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v0, v0, v7
s_waitcnt vmcnt(1)
v_add_f32_e32 v0, v0, v3
v_add_co_u32 v3, vcc_lo, s4, v11
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v12, vcc_lo
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v0, -4.0, v5
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v5, s0, v0
global_store_b32 v[3:4], v5, off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmpx_neq_f32_e32 -1.0, v2
s_cbranch_execz .LBB0_4
v_add_co_u32 v3, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v1, vcc_lo
global_store_b32 v[3:4], v2, off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s0
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
global_load_b32 v2, v[2:3], off
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16Dim2_CalculationPfS_PKfiif
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16Dim2_CalculationPfS_PKfiif, .Lfunc_end0-_Z16Dim2_CalculationPfS_PKfiif
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z16Dim3_CalculationPfS_PKfiiif
.globl _Z16Dim3_CalculationPfS_PKfiiif
.p2align 8
.type _Z16Dim3_CalculationPfS_PKfiiif,@function
_Z16Dim3_CalculationPfS_PKfiiif:
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x0
s_load_b32 s13, s[0:1], 0x34
s_waitcnt lgkmcnt(0)
s_mul_i32 s12, s11, s10
s_and_b32 s13, s13, 0xffff
s_ashr_i32 s2, s12, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s12, s2
s_xor_b32 s3, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s3
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1)
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s15, s13, v[0:1]
s_sub_i32 s13, 0, s3
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v0, s13, v3
s_ashr_i32 s13, s11, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_add_i32 s14, s11, s13
v_ashrrev_i32_e32 v2, 31, v1
s_xor_b32 s14, s14, s13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v0, v3, v0
v_add_nc_u32_e32 v4, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_xor_b32_e32 v4, v4, v2
v_xor_b32_e32 v2, s2, v2
v_add_nc_u32_e32 v0, v3, v0
s_sub_i32 s2, 0, s14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v4, v0
v_mul_lo_u32 v3, v0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v3, v4, v3
v_add_nc_u32_e32 v4, 1, v0
v_subrev_nc_u32_e32 v5, s3, v3
v_cmp_le_u32_e32 vcc_lo, s3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
v_cvt_f32_u32_e32 v5, s14
v_cmp_le_u32_e32 vcc_lo, s3, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, 1, v0
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v4, v5
v_xor_b32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v3, v0, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v4
v_mul_lo_u32 v5, v3, s12
v_cvt_u32_f32_e32 v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_lo_u32 v4, s2, v2
v_sub_nc_u32_e32 v0, v1, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v6, 31, v0
v_mul_hi_u32 v4, v2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v7, v0, v6
v_add_nc_u32_e32 v2, v2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_xor_b32_e32 v4, v7, v6
v_xor_b32_e32 v6, s13, v6
s_load_b32 s13, s[0:1], 0x20
v_mul_hi_u32 v2, v4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v7, v2, s14
v_sub_nc_u32_e32 v4, v4, v7
v_add_nc_u32_e32 v7, 1, v2
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e64 s3, s13, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v8, s14, v4
v_cmp_le_u32_e32 vcc_lo, s14, v4
v_cndmask_b32_e32 v2, v2, v7, vcc_lo
v_dual_cndmask_b32 v4, v4, v8 :: v_dual_add_nc_u32 v7, 1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s14, v4
v_cndmask_b32_e32 v2, v2, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v2, v2, v6
v_sub_nc_u32_e32 v6, v2, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v6, s11
v_cmp_gt_i32_e32 vcc_lo, s10, v6
v_sub_nc_u32_e32 v4, v0, v2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s11, v4
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s3, s2
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB1_2
v_cmp_lt_i32_e32 vcc_lo, 0, v6
s_add_i32 s3, s10, -1
v_add_nc_u32_e32 v5, v4, v5
s_add_i32 s13, s13, -1
s_add_i32 s10, s11, -1
v_subrev_co_ci_u32_e32 v9, vcc_lo, 0, v6, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, s3, v6
s_load_b32 s0, s[0:1], 0x24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[7:8], null, v9, s11, v[5:6]
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, 0, v3
v_mad_u64_u32 v[9:10], null, v6, s11, v[5:6]
v_subrev_co_ci_u32_e32 v13, vcc_lo, 0, v3, vcc_lo
v_ashrrev_i32_e32 v8, 31, v7
v_cmp_lt_i32_e32 vcc_lo, 0, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[11:12], null, v13, s12, v[0:1]
v_lshlrev_b64 v[5:6], 2, v[7:8]
v_subrev_co_ci_u32_e32 v7, vcc_lo, 0, v1, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, s13, v3
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_3)
v_ashrrev_i32_e32 v8, 31, v7
v_ashrrev_i32_e32 v12, 31, v11
v_add_co_ci_u32_e32 v15, vcc_lo, 0, v3, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, s10, v4
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_mad_u64_u32 v[13:14], null, v15, s12, v[0:1]
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v9, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
v_ashrrev_i32_e32 v4, 31, v3
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_clause 0x2
global_load_b32 v0, v[5:6], off
global_load_b32 v15, v[9:10], off
global_load_b32 v16, v[7:8], off
v_lshlrev_b64 v[5:6], 2, v[11:12]
v_ashrrev_i32_e32 v14, 31, v13
v_lshlrev_b64 v[9:10], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v5
v_lshlrev_b64 v[7:8], 2, v[13:14]
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
s_clause 0x1
global_load_b32 v11, v[3:4], off
global_load_b32 v12, v[5:6], off
v_add_co_u32 v3, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v8, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v10, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(5)
v_add_f32_e32 v0, v0, v15
s_waitcnt vmcnt(4)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v0, v0, v16
s_waitcnt vmcnt(3)
v_add_f32_e32 v0, v0, v11
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v0, v0, v12
s_waitcnt vmcnt(1)
v_add_f32_e32 v0, v0, v3
v_add_co_u32 v3, vcc_lo, s4, v9
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v10, vcc_lo
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmamk_f32 v0, v5, 0xc0c00000, v0
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v5, s0, v0
global_store_b32 v[3:4], v5, off
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s2
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmpx_neq_f32_e32 -1.0, v2
s_cbranch_execz .LBB1_4
v_add_co_u32 v3, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v1, vcc_lo
global_store_b32 v[3:4], v2, off
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s0
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
global_load_b32 v2, v[2:3], off
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16Dim3_CalculationPfS_PKfiiif
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z16Dim3_CalculationPfS_PKfiiif, .Lfunc_end1-_Z16Dim3_CalculationPfS_PKfiiif
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16Dim2_CalculationPfS_PKfiif
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16Dim2_CalculationPfS_PKfiif.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16Dim3_CalculationPfS_PKfiiif
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16Dim3_CalculationPfS_PKfiiif.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda.h"
/*---------------------------------------------------------------------
______ ______ _____ ______ _____
| ____|___ // ____| ____/ ____|
| |__ / /| (___ | |__ | | __
| __| / / \___ \| __|| | |_ |
| |____ / /__ ____) | |___| |__| |
|______/_____|_____/|______\_____|
GPU-enabled version using CUDA
Version 1.01
EZSEG: Routine to segment an image using a two-threshold
variable-connectivity region growing method utilizing
GPU acceleration through CUDA.
void ezseg_cuda(float *IMG, float *SEG, int nt, int np,
float thresh1, float thresh2, int nc, int* iters)
INPUT/OUTPUT:
IMG: Input image.
SEG:
ON INPUT:
Matrix of size (nt,np) which contain
1's where there is valid IMG data, and
non-zero values for areas with invalid/no IMG data.
ON OUTPUT:
Segmentation map (0:detection ,same as input o.w.).
nt,np: Dimensions of image.
thresh1: Seeding threshold value.
thresh2: Growing threshold value.
nc: # of consecutive pixels needed for connectivity.
iters:
ON INPUT:
maximum limit on number of iterations.
ON OUTPUT:
number of iterations performed.
----------------------------------------------------------------------
Copyright (c) 2015 Predictive Science Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files
(the "Software"), to deal in the Software without restriction,
including without limitation the rights to use, copy, modify, merge,
publish, distribute, sublicense, and/or sell copies of the Software,
and to permit persons to whom the Software is furnished to do so,
subject to the following conditions:
The above copyright notice and this permission notice shall be
included in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
----------------------------------------------------------------------
*/
/*Define block size.*/
const int BLOCK_SIZE = 16;
/*** Kernel for ezseg iteration ***/
__global__ void ezseg_kernel(float *EUV, float *CHM, float *CHM_TMP, int nt, int np,
float thresh1, float thresh2, int nc, int *val_modded)
{
int fillit,ij,ii,jj;
int i = blockIdx.x*blockDim.x + threadIdx.x;
int j = blockIdx.y*blockDim.y + threadIdx.y;
float local_vec[15],tmp_sum;
if((i>0 && i<nt-1) && (j>0 && j<np-1))
{
ij = nt*j+i; /*Location of i,j in 1D global arrays*/
fillit = 0;
if(CHM_TMP[ij] == 1 ){ /*Good data not marked yet*/
if(EUV[ij] <= thresh1){
fillit = 1;
}
else if(EUV[ij] <= thresh2){
local_vec[ 0] = CHM_TMP[nt*(j+1)+(i-1)];
local_vec[ 1] = CHM_TMP[nt*(j+1)+(i )];
local_vec[ 2] = CHM_TMP[nt*(j+1)+(i+1)];
local_vec[ 3] = CHM_TMP[nt*(j )+(i+1)];
local_vec[ 4] = CHM_TMP[nt*(j-1)+(i+1)];
local_vec[ 5] = CHM_TMP[nt*(j-1)+(i )];
local_vec[ 6] = CHM_TMP[nt*(j-1)+(i-1)];
local_vec[ 7] = CHM_TMP[nt*(j )+(i-1)];
local_vec[ 8] = local_vec[0];
local_vec[ 9] = local_vec[1];
local_vec[10] = local_vec[2];
local_vec[11] = local_vec[3];
local_vec[12] = local_vec[4];
local_vec[13] = local_vec[5];
local_vec[14] = local_vec[6];
for(ii=0;ii<8;ii++){
tmp_sum = 0.0f;
for(jj=0;jj<nc;jj++){
tmp_sum = tmp_sum + local_vec[ii+jj];
}
if(tmp_sum == 0){
fillit = 1;
break;
}
}
} /*euv<thresh2*/
if (fillit == 1) {
CHM[ij] = 0.0f;
if(*val_modded == 0) {
atomicAdd(val_modded, 1);
}
}
} /*good data no mark*/
} /*valid point*/
}
/*********************************************************************/
/*********************************************************************/
/*********************************************************************/
extern "C" void ezseg_cuda(float *EUV, float *CHM, int nt, int np,
float thresh1, float thresh2, int nc, int* iters )
{
int val_modded,max_iters,k;
/*GPU variables:*/
float *EUVgpu,*CHMgpu,*CHM_TMPgpu;
int *val_modded_gpu;
/*Allocate GPU arrays:*/
cudaMalloc((void **) &EUVgpu, sizeof(float)*nt*np);
cudaMalloc((void **) &CHMgpu, sizeof(float)*nt*np);
cudaMalloc((void **) &CHM_TMPgpu, sizeof(float)*nt*np);
cudaMalloc((void **) &val_modded_gpu, sizeof(int));
/*Copy euv and chm to GPU*/
cudaMemcpy(EUVgpu, EUV, sizeof(float)*nt*np, cudaMemcpyHostToDevice);
cudaMemcpy(CHMgpu, CHM, sizeof(float)*nt*np, cudaMemcpyHostToDevice);
cudaMemcpy(CHM_TMPgpu, CHMgpu, sizeof(float)*nt*np, cudaMemcpyDeviceToDevice);
/*Set up CUDA grid*/
dim3 dimBlock(BLOCK_SIZE,BLOCK_SIZE);
dim3 dimGrid((int)ceil((nt+0.0)/dimBlock.x),
(int)ceil((np+0.0)/dimBlock.y));
/*Start main loop*/
max_iters = *iters;
*iters = 0;
for(k=0;k<max_iters;k++){
/*Reset val_modded*/
val_modded = 0;
cudaMemcpy(val_modded_gpu, &val_modded, sizeof(int), cudaMemcpyHostToDevice);
/*Perform iteration:*/
ezseg_kernel<<<dimGrid,dimBlock>>>(EUVgpu,CHMgpu,CHM_TMPgpu,nt,np,thresh1,
thresh2,nc,val_modded_gpu);
*iters = *iters + 1;
/*Make sure everything is done*/
cudaDeviceSynchronize();
/*Get data mod flag*/
cudaMemcpy(&val_modded, val_modded_gpu, sizeof(int), cudaMemcpyDeviceToHost);
/*If no new CH points, break out of iterations*/
if(val_modded == 0){
break;
}
/*Reset tmp to be new map iterate for next iteration:*/
cudaMemcpy(CHM_TMPgpu,CHMgpu,sizeof(float)*nt*np,cudaMemcpyDeviceToDevice);
}
/*Copy result from GPU back to CPU*/
cudaMemcpy(CHM,CHMgpu,sizeof(float)*nt*np,cudaMemcpyDeviceToHost);
/*Free up GPU memory*/
cudaFree(EUVgpu);
cudaFree(CHMgpu);
cudaFree(CHM_TMPgpu);
cudaFree(val_modded_gpu);
} | .file "tmpxft_00011747_00000000-6_ezseg_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z12ezseg_kernelPfS_S_iiffiPiPfS_S_iiffiPi
.type _Z43__device_stub__Z12ezseg_kernelPfS_S_iiffiPiPfS_S_iiffiPi, @function
_Z43__device_stub__Z12ezseg_kernelPfS_S_iiffiPiPfS_S_iiffiPi:
.LFB2052:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movl %ecx, 36(%rsp)
movl %r8d, 32(%rsp)
movss %xmm0, 28(%rsp)
movss %xmm1, 24(%rsp)
movl %r9d, 20(%rsp)
movq 224(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 28(%rsp), %rax
movq %rax, 168(%rsp)
leaq 24(%rsp), %rax
movq %rax, 176(%rsp)
leaq 20(%rsp), %rax
movq %rax, 184(%rsp)
leaq 8(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z12ezseg_kernelPfS_S_iiffiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z43__device_stub__Z12ezseg_kernelPfS_S_iiffiPiPfS_S_iiffiPi, .-_Z43__device_stub__Z12ezseg_kernelPfS_S_iiffiPiPfS_S_iiffiPi
.globl _Z12ezseg_kernelPfS_S_iiffiPi
.type _Z12ezseg_kernelPfS_S_iiffiPi, @function
_Z12ezseg_kernelPfS_S_iiffiPi:
.LFB2053:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z43__device_stub__Z12ezseg_kernelPfS_S_iiffiPiPfS_S_iiffiPi
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z12ezseg_kernelPfS_S_iiffiPi, .-_Z12ezseg_kernelPfS_S_iiffiPi
.globl ezseg_cuda
.type ezseg_cuda, @function
ezseg_cuda:
.LFB2027:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %rdi, %rbx
movq %rsi, %r14
movq %rsi, 24(%rsp)
movl %edx, 8(%rsp)
movl %ecx, %r15d
movss %xmm0, 12(%rsp)
movss %xmm1, 16(%rsp)
movl %r8d, 20(%rsp)
movq %r9, %rbp
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movslq %edx, %r12
movslq %ecx, %rax
imulq %rax, %r12
salq $2, %r12
leaq 48(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq %rbx, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq %r14, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $3, %ecx
movq %r12, %rdx
movq 56(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 88(%rsp)
pxor %xmm0, %xmm0
cvtsi2sdl %r15d, %xmm0
mulsd .LC0(%rip), %xmm0
movapd %xmm0, %xmm1
movsd .LC4(%rip), %xmm3
movapd %xmm0, %xmm2
andpd %xmm3, %xmm2
movsd .LC1(%rip), %xmm4
ucomisd %xmm2, %xmm4
jbe .L12
cvttsd2siq %xmm0, %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
cmpnlesd %xmm2, %xmm1
movsd .LC3(%rip), %xmm4
andpd %xmm4, %xmm1
addsd %xmm2, %xmm1
andnpd %xmm0, %xmm3
orpd %xmm3, %xmm1
.L12:
pxor %xmm0, %xmm0
cvtsi2sdl 8(%rsp), %xmm0
mulsd .LC0(%rip), %xmm0
movapd %xmm0, %xmm4
movsd .LC4(%rip), %xmm3
movapd %xmm0, %xmm2
andpd %xmm3, %xmm2
movsd .LC1(%rip), %xmm5
ucomisd %xmm2, %xmm5
jbe .L13
cvttsd2siq %xmm0, %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
cmpnlesd %xmm2, %xmm4
movsd .LC3(%rip), %xmm5
andpd %xmm5, %xmm4
addsd %xmm2, %xmm4
andnpd %xmm0, %xmm3
orpd %xmm3, %xmm4
.L13:
cvttsd2sil %xmm4, %eax
movl %eax, 92(%rsp)
cvttsd2sil %xmm1, %eax
movl %eax, 96(%rsp)
movl $1, 100(%rsp)
movl 0(%rbp), %r14d
movl $0, 0(%rbp)
testl %r14d, %r14d
jle .L14
movl $0, %ebx
leaq 44(%rsp), %r13
jmp .L16
.L15:
addl $1, 0(%rbp)
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $4, %edx
movq 72(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
cmpl $0, 44(%rsp)
je .L14
movl $3, %ecx
movq %r12, %rdx
movq 56(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
addl $1, %ebx
cmpl %ebx, %r14d
je .L14
.L16:
movl $0, 44(%rsp)
movl $1, %ecx
movl $4, %edx
movq %r13, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 80(%rsp)
movl $16, 84(%rsp)
movl 88(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movq 92(%rsp), %rdi
movl 100(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L15
subq $8, %rsp
.cfi_def_cfa_offset 184
pushq 80(%rsp)
.cfi_def_cfa_offset 192
movl 36(%rsp), %r9d
movss 32(%rsp), %xmm1
movss 28(%rsp), %xmm0
movl %r15d, %r8d
movl 24(%rsp), %ecx
movq 80(%rsp), %rdx
movq 72(%rsp), %rsi
movq 64(%rsp), %rdi
call _Z43__device_stub__Z12ezseg_kernelPfS_S_iiffiPiPfS_S_iiffiPi
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L15
.L14:
movl $2, %ecx
movq %r12, %rdx
movq 56(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size ezseg_cuda, .-ezseg_cuda
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "_Z12ezseg_kernelPfS_S_iiffiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z12ezseg_kernelPfS_S_iiffiPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1068498944
.align 8
.LC1:
.long 0
.long 1127219200
.align 8
.LC3:
.long 0
.long 1072693248
.align 8
.LC4:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda.h"
/*---------------------------------------------------------------------
______ ______ _____ ______ _____
| ____|___ // ____| ____/ ____|
| |__ / /| (___ | |__ | | __
| __| / / \___ \| __|| | |_ |
| |____ / /__ ____) | |___| |__| |
|______/_____|_____/|______\_____|
GPU-enabled version using CUDA
Version 1.01
EZSEG: Routine to segment an image using a two-threshold
variable-connectivity region growing method utilizing
GPU acceleration through CUDA.
void ezseg_cuda(float *IMG, float *SEG, int nt, int np,
float thresh1, float thresh2, int nc, int* iters)
INPUT/OUTPUT:
IMG: Input image.
SEG:
ON INPUT:
Matrix of size (nt,np) which contain
1's where there is valid IMG data, and
non-zero values for areas with invalid/no IMG data.
ON OUTPUT:
Segmentation map (0:detection ,same as input o.w.).
nt,np: Dimensions of image.
thresh1: Seeding threshold value.
thresh2: Growing threshold value.
nc: # of consecutive pixels needed for connectivity.
iters:
ON INPUT:
maximum limit on number of iterations.
ON OUTPUT:
number of iterations performed.
----------------------------------------------------------------------
Copyright (c) 2015 Predictive Science Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files
(the "Software"), to deal in the Software without restriction,
including without limitation the rights to use, copy, modify, merge,
publish, distribute, sublicense, and/or sell copies of the Software,
and to permit persons to whom the Software is furnished to do so,
subject to the following conditions:
The above copyright notice and this permission notice shall be
included in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
----------------------------------------------------------------------
*/
/*Define block size.*/
const int BLOCK_SIZE = 16;
/*** Kernel for ezseg iteration ***/
__global__ void ezseg_kernel(float *EUV, float *CHM, float *CHM_TMP, int nt, int np,
float thresh1, float thresh2, int nc, int *val_modded)
{
int fillit,ij,ii,jj;
int i = blockIdx.x*blockDim.x + threadIdx.x;
int j = blockIdx.y*blockDim.y + threadIdx.y;
float local_vec[15],tmp_sum;
if((i>0 && i<nt-1) && (j>0 && j<np-1))
{
ij = nt*j+i; /*Location of i,j in 1D global arrays*/
fillit = 0;
if(CHM_TMP[ij] == 1 ){ /*Good data not marked yet*/
if(EUV[ij] <= thresh1){
fillit = 1;
}
else if(EUV[ij] <= thresh2){
local_vec[ 0] = CHM_TMP[nt*(j+1)+(i-1)];
local_vec[ 1] = CHM_TMP[nt*(j+1)+(i )];
local_vec[ 2] = CHM_TMP[nt*(j+1)+(i+1)];
local_vec[ 3] = CHM_TMP[nt*(j )+(i+1)];
local_vec[ 4] = CHM_TMP[nt*(j-1)+(i+1)];
local_vec[ 5] = CHM_TMP[nt*(j-1)+(i )];
local_vec[ 6] = CHM_TMP[nt*(j-1)+(i-1)];
local_vec[ 7] = CHM_TMP[nt*(j )+(i-1)];
local_vec[ 8] = local_vec[0];
local_vec[ 9] = local_vec[1];
local_vec[10] = local_vec[2];
local_vec[11] = local_vec[3];
local_vec[12] = local_vec[4];
local_vec[13] = local_vec[5];
local_vec[14] = local_vec[6];
for(ii=0;ii<8;ii++){
tmp_sum = 0.0f;
for(jj=0;jj<nc;jj++){
tmp_sum = tmp_sum + local_vec[ii+jj];
}
if(tmp_sum == 0){
fillit = 1;
break;
}
}
} /*euv<thresh2*/
if (fillit == 1) {
CHM[ij] = 0.0f;
if(*val_modded == 0) {
atomicAdd(val_modded, 1);
}
}
} /*good data no mark*/
} /*valid point*/
}
/*********************************************************************/
/*********************************************************************/
/*********************************************************************/
extern "C" void ezseg_cuda(float *EUV, float *CHM, int nt, int np,
float thresh1, float thresh2, int nc, int* iters )
{
int val_modded,max_iters,k;
/*GPU variables:*/
float *EUVgpu,*CHMgpu,*CHM_TMPgpu;
int *val_modded_gpu;
/*Allocate GPU arrays:*/
cudaMalloc((void **) &EUVgpu, sizeof(float)*nt*np);
cudaMalloc((void **) &CHMgpu, sizeof(float)*nt*np);
cudaMalloc((void **) &CHM_TMPgpu, sizeof(float)*nt*np);
cudaMalloc((void **) &val_modded_gpu, sizeof(int));
/*Copy euv and chm to GPU*/
cudaMemcpy(EUVgpu, EUV, sizeof(float)*nt*np, cudaMemcpyHostToDevice);
cudaMemcpy(CHMgpu, CHM, sizeof(float)*nt*np, cudaMemcpyHostToDevice);
cudaMemcpy(CHM_TMPgpu, CHMgpu, sizeof(float)*nt*np, cudaMemcpyDeviceToDevice);
/*Set up CUDA grid*/
dim3 dimBlock(BLOCK_SIZE,BLOCK_SIZE);
dim3 dimGrid((int)ceil((nt+0.0)/dimBlock.x),
(int)ceil((np+0.0)/dimBlock.y));
/*Start main loop*/
max_iters = *iters;
*iters = 0;
for(k=0;k<max_iters;k++){
/*Reset val_modded*/
val_modded = 0;
cudaMemcpy(val_modded_gpu, &val_modded, sizeof(int), cudaMemcpyHostToDevice);
/*Perform iteration:*/
ezseg_kernel<<<dimGrid,dimBlock>>>(EUVgpu,CHMgpu,CHM_TMPgpu,nt,np,thresh1,
thresh2,nc,val_modded_gpu);
*iters = *iters + 1;
/*Make sure everything is done*/
cudaDeviceSynchronize();
/*Get data mod flag*/
cudaMemcpy(&val_modded, val_modded_gpu, sizeof(int), cudaMemcpyDeviceToHost);
/*If no new CH points, break out of iterations*/
if(val_modded == 0){
break;
}
/*Reset tmp to be new map iterate for next iteration:*/
cudaMemcpy(CHM_TMPgpu,CHMgpu,sizeof(float)*nt*np,cudaMemcpyDeviceToDevice);
}
/*Copy result from GPU back to CPU*/
cudaMemcpy(CHM,CHMgpu,sizeof(float)*nt*np,cudaMemcpyDeviceToHost);
/*Free up GPU memory*/
cudaFree(EUVgpu);
cudaFree(CHMgpu);
cudaFree(CHM_TMPgpu);
cudaFree(val_modded_gpu);
} | #include "hip/hip_runtime.h"
/*---------------------------------------------------------------------
______ ______ _____ ______ _____
| ____|___ // ____| ____/ ____|
| |__ / /| (___ | |__ | | __
| __| / / \___ \| __|| | |_ |
| |____ / /__ ____) | |___| |__| |
|______/_____|_____/|______\_____|
GPU-enabled version using CUDA
Version 1.01
EZSEG: Routine to segment an image using a two-threshold
variable-connectivity region growing method utilizing
GPU acceleration through CUDA.
void ezseg_cuda(float *IMG, float *SEG, int nt, int np,
float thresh1, float thresh2, int nc, int* iters)
INPUT/OUTPUT:
IMG: Input image.
SEG:
ON INPUT:
Matrix of size (nt,np) which contain
1's where there is valid IMG data, and
non-zero values for areas with invalid/no IMG data.
ON OUTPUT:
Segmentation map (0:detection ,same as input o.w.).
nt,np: Dimensions of image.
thresh1: Seeding threshold value.
thresh2: Growing threshold value.
nc: # of consecutive pixels needed for connectivity.
iters:
ON INPUT:
maximum limit on number of iterations.
ON OUTPUT:
number of iterations performed.
----------------------------------------------------------------------
Copyright (c) 2015 Predictive Science Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files
(the "Software"), to deal in the Software without restriction,
including without limitation the rights to use, copy, modify, merge,
publish, distribute, sublicense, and/or sell copies of the Software,
and to permit persons to whom the Software is furnished to do so,
subject to the following conditions:
The above copyright notice and this permission notice shall be
included in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
----------------------------------------------------------------------
*/
/*Define block size.*/
const int BLOCK_SIZE = 16;
/*** Kernel for ezseg iteration ***/
__global__ void ezseg_kernel(float *EUV, float *CHM, float *CHM_TMP, int nt, int np,
float thresh1, float thresh2, int nc, int *val_modded)
{
int fillit,ij,ii,jj;
int i = blockIdx.x*blockDim.x + threadIdx.x;
int j = blockIdx.y*blockDim.y + threadIdx.y;
float local_vec[15],tmp_sum;
if((i>0 && i<nt-1) && (j>0 && j<np-1))
{
ij = nt*j+i; /*Location of i,j in 1D global arrays*/
fillit = 0;
if(CHM_TMP[ij] == 1 ){ /*Good data not marked yet*/
if(EUV[ij] <= thresh1){
fillit = 1;
}
else if(EUV[ij] <= thresh2){
local_vec[ 0] = CHM_TMP[nt*(j+1)+(i-1)];
local_vec[ 1] = CHM_TMP[nt*(j+1)+(i )];
local_vec[ 2] = CHM_TMP[nt*(j+1)+(i+1)];
local_vec[ 3] = CHM_TMP[nt*(j )+(i+1)];
local_vec[ 4] = CHM_TMP[nt*(j-1)+(i+1)];
local_vec[ 5] = CHM_TMP[nt*(j-1)+(i )];
local_vec[ 6] = CHM_TMP[nt*(j-1)+(i-1)];
local_vec[ 7] = CHM_TMP[nt*(j )+(i-1)];
local_vec[ 8] = local_vec[0];
local_vec[ 9] = local_vec[1];
local_vec[10] = local_vec[2];
local_vec[11] = local_vec[3];
local_vec[12] = local_vec[4];
local_vec[13] = local_vec[5];
local_vec[14] = local_vec[6];
for(ii=0;ii<8;ii++){
tmp_sum = 0.0f;
for(jj=0;jj<nc;jj++){
tmp_sum = tmp_sum + local_vec[ii+jj];
}
if(tmp_sum == 0){
fillit = 1;
break;
}
}
} /*euv<thresh2*/
if (fillit == 1) {
CHM[ij] = 0.0f;
if(*val_modded == 0) {
atomicAdd(val_modded, 1);
}
}
} /*good data no mark*/
} /*valid point*/
}
/*********************************************************************/
/*********************************************************************/
/*********************************************************************/
extern "C" void ezseg_cuda(float *EUV, float *CHM, int nt, int np,
float thresh1, float thresh2, int nc, int* iters )
{
int val_modded,max_iters,k;
/*GPU variables:*/
float *EUVgpu,*CHMgpu,*CHM_TMPgpu;
int *val_modded_gpu;
/*Allocate GPU arrays:*/
hipMalloc((void **) &EUVgpu, sizeof(float)*nt*np);
hipMalloc((void **) &CHMgpu, sizeof(float)*nt*np);
hipMalloc((void **) &CHM_TMPgpu, sizeof(float)*nt*np);
hipMalloc((void **) &val_modded_gpu, sizeof(int));
/*Copy euv and chm to GPU*/
hipMemcpy(EUVgpu, EUV, sizeof(float)*nt*np, hipMemcpyHostToDevice);
hipMemcpy(CHMgpu, CHM, sizeof(float)*nt*np, hipMemcpyHostToDevice);
hipMemcpy(CHM_TMPgpu, CHMgpu, sizeof(float)*nt*np, hipMemcpyDeviceToDevice);
/*Set up CUDA grid*/
dim3 dimBlock(BLOCK_SIZE,BLOCK_SIZE);
dim3 dimGrid((int)ceil((nt+0.0)/dimBlock.x),
(int)ceil((np+0.0)/dimBlock.y));
/*Start main loop*/
max_iters = *iters;
*iters = 0;
for(k=0;k<max_iters;k++){
/*Reset val_modded*/
val_modded = 0;
hipMemcpy(val_modded_gpu, &val_modded, sizeof(int), hipMemcpyHostToDevice);
/*Perform iteration:*/
ezseg_kernel<<<dimGrid,dimBlock>>>(EUVgpu,CHMgpu,CHM_TMPgpu,nt,np,thresh1,
thresh2,nc,val_modded_gpu);
*iters = *iters + 1;
/*Make sure everything is done*/
hipDeviceSynchronize();
/*Get data mod flag*/
hipMemcpy(&val_modded, val_modded_gpu, sizeof(int), hipMemcpyDeviceToHost);
/*If no new CH points, break out of iterations*/
if(val_modded == 0){
break;
}
/*Reset tmp to be new map iterate for next iteration:*/
hipMemcpy(CHM_TMPgpu,CHMgpu,sizeof(float)*nt*np,hipMemcpyDeviceToDevice);
}
/*Copy result from GPU back to CPU*/
hipMemcpy(CHM,CHMgpu,sizeof(float)*nt*np,hipMemcpyDeviceToHost);
/*Free up GPU memory*/
hipFree(EUVgpu);
hipFree(CHMgpu);
hipFree(CHM_TMPgpu);
hipFree(val_modded_gpu);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
/*---------------------------------------------------------------------
______ ______ _____ ______ _____
| ____|___ // ____| ____/ ____|
| |__ / /| (___ | |__ | | __
| __| / / \___ \| __|| | |_ |
| |____ / /__ ____) | |___| |__| |
|______/_____|_____/|______\_____|
GPU-enabled version using CUDA
Version 1.01
EZSEG: Routine to segment an image using a two-threshold
variable-connectivity region growing method utilizing
GPU acceleration through CUDA.
void ezseg_cuda(float *IMG, float *SEG, int nt, int np,
float thresh1, float thresh2, int nc, int* iters)
INPUT/OUTPUT:
IMG: Input image.
SEG:
ON INPUT:
Matrix of size (nt,np) which contain
1's where there is valid IMG data, and
non-zero values for areas with invalid/no IMG data.
ON OUTPUT:
Segmentation map (0:detection ,same as input o.w.).
nt,np: Dimensions of image.
thresh1: Seeding threshold value.
thresh2: Growing threshold value.
nc: # of consecutive pixels needed for connectivity.
iters:
ON INPUT:
maximum limit on number of iterations.
ON OUTPUT:
number of iterations performed.
----------------------------------------------------------------------
Copyright (c) 2015 Predictive Science Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files
(the "Software"), to deal in the Software without restriction,
including without limitation the rights to use, copy, modify, merge,
publish, distribute, sublicense, and/or sell copies of the Software,
and to permit persons to whom the Software is furnished to do so,
subject to the following conditions:
The above copyright notice and this permission notice shall be
included in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
----------------------------------------------------------------------
*/
/*Define block size.*/
const int BLOCK_SIZE = 16;
/*** Kernel for ezseg iteration ***/
__global__ void ezseg_kernel(float *EUV, float *CHM, float *CHM_TMP, int nt, int np,
float thresh1, float thresh2, int nc, int *val_modded)
{
int fillit,ij,ii,jj;
int i = blockIdx.x*blockDim.x + threadIdx.x;
int j = blockIdx.y*blockDim.y + threadIdx.y;
float local_vec[15],tmp_sum;
if((i>0 && i<nt-1) && (j>0 && j<np-1))
{
ij = nt*j+i; /*Location of i,j in 1D global arrays*/
fillit = 0;
if(CHM_TMP[ij] == 1 ){ /*Good data not marked yet*/
if(EUV[ij] <= thresh1){
fillit = 1;
}
else if(EUV[ij] <= thresh2){
local_vec[ 0] = CHM_TMP[nt*(j+1)+(i-1)];
local_vec[ 1] = CHM_TMP[nt*(j+1)+(i )];
local_vec[ 2] = CHM_TMP[nt*(j+1)+(i+1)];
local_vec[ 3] = CHM_TMP[nt*(j )+(i+1)];
local_vec[ 4] = CHM_TMP[nt*(j-1)+(i+1)];
local_vec[ 5] = CHM_TMP[nt*(j-1)+(i )];
local_vec[ 6] = CHM_TMP[nt*(j-1)+(i-1)];
local_vec[ 7] = CHM_TMP[nt*(j )+(i-1)];
local_vec[ 8] = local_vec[0];
local_vec[ 9] = local_vec[1];
local_vec[10] = local_vec[2];
local_vec[11] = local_vec[3];
local_vec[12] = local_vec[4];
local_vec[13] = local_vec[5];
local_vec[14] = local_vec[6];
for(ii=0;ii<8;ii++){
tmp_sum = 0.0f;
for(jj=0;jj<nc;jj++){
tmp_sum = tmp_sum + local_vec[ii+jj];
}
if(tmp_sum == 0){
fillit = 1;
break;
}
}
} /*euv<thresh2*/
if (fillit == 1) {
CHM[ij] = 0.0f;
if(*val_modded == 0) {
atomicAdd(val_modded, 1);
}
}
} /*good data no mark*/
} /*valid point*/
}
/*********************************************************************/
/*********************************************************************/
/*********************************************************************/
extern "C" void ezseg_cuda(float *EUV, float *CHM, int nt, int np,
float thresh1, float thresh2, int nc, int* iters )
{
int val_modded,max_iters,k;
/*GPU variables:*/
float *EUVgpu,*CHMgpu,*CHM_TMPgpu;
int *val_modded_gpu;
/*Allocate GPU arrays:*/
hipMalloc((void **) &EUVgpu, sizeof(float)*nt*np);
hipMalloc((void **) &CHMgpu, sizeof(float)*nt*np);
hipMalloc((void **) &CHM_TMPgpu, sizeof(float)*nt*np);
hipMalloc((void **) &val_modded_gpu, sizeof(int));
/*Copy euv and chm to GPU*/
hipMemcpy(EUVgpu, EUV, sizeof(float)*nt*np, hipMemcpyHostToDevice);
hipMemcpy(CHMgpu, CHM, sizeof(float)*nt*np, hipMemcpyHostToDevice);
hipMemcpy(CHM_TMPgpu, CHMgpu, sizeof(float)*nt*np, hipMemcpyDeviceToDevice);
/*Set up CUDA grid*/
dim3 dimBlock(BLOCK_SIZE,BLOCK_SIZE);
dim3 dimGrid((int)ceil((nt+0.0)/dimBlock.x),
(int)ceil((np+0.0)/dimBlock.y));
/*Start main loop*/
max_iters = *iters;
*iters = 0;
for(k=0;k<max_iters;k++){
/*Reset val_modded*/
val_modded = 0;
hipMemcpy(val_modded_gpu, &val_modded, sizeof(int), hipMemcpyHostToDevice);
/*Perform iteration:*/
ezseg_kernel<<<dimGrid,dimBlock>>>(EUVgpu,CHMgpu,CHM_TMPgpu,nt,np,thresh1,
thresh2,nc,val_modded_gpu);
*iters = *iters + 1;
/*Make sure everything is done*/
hipDeviceSynchronize();
/*Get data mod flag*/
hipMemcpy(&val_modded, val_modded_gpu, sizeof(int), hipMemcpyDeviceToHost);
/*If no new CH points, break out of iterations*/
if(val_modded == 0){
break;
}
/*Reset tmp to be new map iterate for next iteration:*/
hipMemcpy(CHM_TMPgpu,CHMgpu,sizeof(float)*nt*np,hipMemcpyDeviceToDevice);
}
/*Copy result from GPU back to CPU*/
hipMemcpy(CHM,CHMgpu,sizeof(float)*nt*np,hipMemcpyDeviceToHost);
/*Free up GPU memory*/
hipFree(EUVgpu);
hipFree(CHMgpu);
hipFree(CHM_TMPgpu);
hipFree(val_modded_gpu);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12ezseg_kernelPfS_S_iiffiPi
.globl _Z12ezseg_kernelPfS_S_iiffiPi
.p2align 8
.type _Z12ezseg_kernelPfS_S_iiffiPi,@function
_Z12ezseg_kernelPfS_S_iiffiPi:
s_load_b32 s4, s[0:1], 0x44
v_and_b32_e32 v3, 0x3ff, v0
s_add_u32 s2, s0, 56
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s4, v[3:4]
s_mov_b32 s4, exec_lo
v_cmpx_lt_i32_e32 0, v1
s_cbranch_execz .LBB0_18
s_load_b32 s2, s[2:3], 0xc
s_load_b64 s[4:5], s[0:1], 0x18
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s2, 16
s_add_i32 s3, s5, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
s_add_i32 s2, s4, -1
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e64 s2, s3, v2
v_cmp_lt_i32_e64 s3, 0, v2
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_18
v_mul_lo_u32 v0, v2, s4
s_load_b64 s[2:3], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v15, v0, v1
v_ashrrev_i32_e32 v16, 31, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[15:16]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v4, vcc_lo
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0)
v_cmp_eq_f32_e32 vcc_lo, 1.0, v5
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_18
s_clause 0x1
s_load_b64 s[6:7], s[0:1], 0x0
s_load_b32 s5, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_cmp_nge_f32_e32 vcc_lo, s5, v3
s_mov_b32 s5, -1
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz .LBB0_14
s_load_b32 s5, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
v_cmp_ge_f32_e32 vcc_lo, s5, v3
s_mov_b32 s5, 0
s_and_saveexec_b32 s7, vcc_lo
s_cbranch_execz .LBB0_13
v_mad_u64_u32 v[3:4], null, s4, v2, s[4:5]
v_add_nc_u32_e32 v14, -1, v1
v_add_nc_u32_e32 v4, -1, v2
v_add_nc_u32_e32 v10, 1, v1
s_load_b32 s8, s[0:1], 0x28
s_mov_b32 s10, 0
s_delay_alu instid0(VALU_DEP_2)
v_mul_lo_u32 v17, v4, s4
v_add_nc_u32_e32 v2, v3, v14
v_add_nc_u32_e32 v4, v3, v1
v_add_nc_u32_e32 v6, v3, v10
v_add_nc_u32_e32 v8, v0, v10
v_add_nc_u32_e32 v0, v0, v14
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
v_ashrrev_i32_e32 v7, 31, v6
v_add_nc_u32_e32 v10, v17, v10
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_nc_u32_e32 v12, v17, v1
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_ashrrev_i32_e32 v11, 31, v10
v_add_nc_u32_e32 v17, v17, v14
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v4
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_ashrrev_i32_e32 v13, 31, v12
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_add_co_u32 v6, vcc_lo, s2, v6
v_lshlrev_b64 v[10:11], 2, v[10:11]
v_ashrrev_i32_e32 v18, 31, v17
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
v_add_co_u32 v8, vcc_lo, s2, v8
v_lshlrev_b64 v[12:13], 2, v[12:13]
v_ashrrev_i32_e32 v1, 31, v0
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
v_add_co_u32 v10, vcc_lo, s2, v10
v_lshlrev_b64 v[17:18], 2, v[17:18]
v_add_co_ci_u32_e32 v11, vcc_lo, s3, v11, vcc_lo
v_add_co_u32 v12, vcc_lo, s2, v12
v_lshlrev_b64 v[19:20], 2, v[0:1]
v_add_co_ci_u32_e32 v13, vcc_lo, s3, v13, vcc_lo
v_add_co_u32 v17, vcc_lo, s2, v17
v_add_co_ci_u32_e32 v18, vcc_lo, s3, v18, vcc_lo
s_clause 0x6
global_load_b32 v0, v[2:3], off
global_load_b32 v1, v[4:5], off
global_load_b32 v2, v[6:7], off
global_load_b32 v3, v[8:9], off
global_load_b32 v4, v[10:11], off
global_load_b32 v5, v[12:13], off
global_load_b32 v6, v[17:18], off
v_add_co_u32 v7, vcc_lo, s2, v19
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v20, vcc_lo
s_waitcnt lgkmcnt(0)
s_cmp_gt_i32 s8, 0
s_mov_b64 s[2:3], 0
s_cselect_b32 s9, -1, 0
global_load_b32 v7, v[7:8], off
s_waitcnt vmcnt(6)
v_dual_mov_b32 v8, v0 :: v_dual_mov_b32 v9, v1
s_waitcnt vmcnt(4)
v_dual_mov_b32 v10, v2 :: v_dual_mov_b32 v11, v3
s_waitcnt vmcnt(2)
v_dual_mov_b32 v12, v4 :: v_dual_mov_b32 v13, v5
s_waitcnt vmcnt(1)
v_mov_b32_e32 v14, v6
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_7
.p2align 6
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s4, exec_lo, s5
s_or_b32 s10, s4, s10
s_and_not1_b32 s4, s11, exec_lo
s_and_b32 s5, s12, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s11, s4, s5
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execz .LBB0_12
.LBB0_7:
v_mov_b32_e32 v17, 0
s_and_not1_b32 vcc_lo, exec_lo, s9
s_cbranch_vccnz .LBB0_10
s_mov_b64 s[4:5], s[2:3]
s_mov_b32 s13, s8
.LBB0_9:
s_mov_b32 m0, s4
s_add_i32 s13, s13, -1
s_waitcnt vmcnt(0)
v_movrels_b32_e32 v18, v0
s_add_u32 s4, s4, 1
s_addc_u32 s5, s5, 0
s_cmp_lg_u32 s13, 0
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v17, v17, v18
s_cbranch_scc1 .LBB0_9
.LBB0_10:
s_mov_b32 s5, -1
s_or_b32 s12, s12, exec_lo
s_mov_b32 s4, exec_lo
v_cmpx_neq_f32_e32 0, v17
s_cbranch_execz .LBB0_6
s_add_u32 s2, s2, 1
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s2, 8
s_cselect_b32 s5, -1, 0
s_and_not1_b32 s12, s12, exec_lo
s_or_not1_b32 s5, s5, exec_lo
s_branch .LBB0_6
.LBB0_12:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s5, s11, exec_lo
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_or_not1_b32 s5, s5, exec_lo
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s5
s_cbranch_execz .LBB0_18
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x30
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 2, v[15:16]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_load_b32 s4, s[2:3], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s4, 0
s_cbranch_scc1 .LBB0_18
s_mov_b32 s0, exec_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mbcnt_lo_u32_b32 v0, s0, 0
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_and_b32 s1, exec_lo, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 exec_lo, s1
s_cbranch_execz .LBB0_18
s_bcnt1_i32_b32 s0, s0
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
global_atomic_add_u32 v0, v1, s[2:3]
.LBB0_18:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12ezseg_kernelPfS_S_iiffiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12ezseg_kernelPfS_S_iiffiPi, .Lfunc_end0-_Z12ezseg_kernelPfS_S_iiffiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12ezseg_kernelPfS_S_iiffiPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12ezseg_kernelPfS_S_iiffiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
/*---------------------------------------------------------------------
______ ______ _____ ______ _____
| ____|___ // ____| ____/ ____|
| |__ / /| (___ | |__ | | __
| __| / / \___ \| __|| | |_ |
| |____ / /__ ____) | |___| |__| |
|______/_____|_____/|______\_____|
GPU-enabled version using CUDA
Version 1.01
EZSEG: Routine to segment an image using a two-threshold
variable-connectivity region growing method utilizing
GPU acceleration through CUDA.
void ezseg_cuda(float *IMG, float *SEG, int nt, int np,
float thresh1, float thresh2, int nc, int* iters)
INPUT/OUTPUT:
IMG: Input image.
SEG:
ON INPUT:
Matrix of size (nt,np) which contain
1's where there is valid IMG data, and
non-zero values for areas with invalid/no IMG data.
ON OUTPUT:
Segmentation map (0:detection ,same as input o.w.).
nt,np: Dimensions of image.
thresh1: Seeding threshold value.
thresh2: Growing threshold value.
nc: # of consecutive pixels needed for connectivity.
iters:
ON INPUT:
maximum limit on number of iterations.
ON OUTPUT:
number of iterations performed.
----------------------------------------------------------------------
Copyright (c) 2015 Predictive Science Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files
(the "Software"), to deal in the Software without restriction,
including without limitation the rights to use, copy, modify, merge,
publish, distribute, sublicense, and/or sell copies of the Software,
and to permit persons to whom the Software is furnished to do so,
subject to the following conditions:
The above copyright notice and this permission notice shall be
included in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
----------------------------------------------------------------------
*/
/*Define block size.*/
const int BLOCK_SIZE = 16;
/*** Kernel for ezseg iteration ***/
__global__ void ezseg_kernel(float *EUV, float *CHM, float *CHM_TMP, int nt, int np,
float thresh1, float thresh2, int nc, int *val_modded)
{
int fillit,ij,ii,jj;
int i = blockIdx.x*blockDim.x + threadIdx.x;
int j = blockIdx.y*blockDim.y + threadIdx.y;
float local_vec[15],tmp_sum;
if((i>0 && i<nt-1) && (j>0 && j<np-1))
{
ij = nt*j+i; /*Location of i,j in 1D global arrays*/
fillit = 0;
if(CHM_TMP[ij] == 1 ){ /*Good data not marked yet*/
if(EUV[ij] <= thresh1){
fillit = 1;
}
else if(EUV[ij] <= thresh2){
local_vec[ 0] = CHM_TMP[nt*(j+1)+(i-1)];
local_vec[ 1] = CHM_TMP[nt*(j+1)+(i )];
local_vec[ 2] = CHM_TMP[nt*(j+1)+(i+1)];
local_vec[ 3] = CHM_TMP[nt*(j )+(i+1)];
local_vec[ 4] = CHM_TMP[nt*(j-1)+(i+1)];
local_vec[ 5] = CHM_TMP[nt*(j-1)+(i )];
local_vec[ 6] = CHM_TMP[nt*(j-1)+(i-1)];
local_vec[ 7] = CHM_TMP[nt*(j )+(i-1)];
local_vec[ 8] = local_vec[0];
local_vec[ 9] = local_vec[1];
local_vec[10] = local_vec[2];
local_vec[11] = local_vec[3];
local_vec[12] = local_vec[4];
local_vec[13] = local_vec[5];
local_vec[14] = local_vec[6];
for(ii=0;ii<8;ii++){
tmp_sum = 0.0f;
for(jj=0;jj<nc;jj++){
tmp_sum = tmp_sum + local_vec[ii+jj];
}
if(tmp_sum == 0){
fillit = 1;
break;
}
}
} /*euv<thresh2*/
if (fillit == 1) {
CHM[ij] = 0.0f;
if(*val_modded == 0) {
atomicAdd(val_modded, 1);
}
}
} /*good data no mark*/
} /*valid point*/
}
/*********************************************************************/
/*********************************************************************/
/*********************************************************************/
extern "C" void ezseg_cuda(float *EUV, float *CHM, int nt, int np,
float thresh1, float thresh2, int nc, int* iters )
{
int val_modded,max_iters,k;
/*GPU variables:*/
float *EUVgpu,*CHMgpu,*CHM_TMPgpu;
int *val_modded_gpu;
/*Allocate GPU arrays:*/
hipMalloc((void **) &EUVgpu, sizeof(float)*nt*np);
hipMalloc((void **) &CHMgpu, sizeof(float)*nt*np);
hipMalloc((void **) &CHM_TMPgpu, sizeof(float)*nt*np);
hipMalloc((void **) &val_modded_gpu, sizeof(int));
/*Copy euv and chm to GPU*/
hipMemcpy(EUVgpu, EUV, sizeof(float)*nt*np, hipMemcpyHostToDevice);
hipMemcpy(CHMgpu, CHM, sizeof(float)*nt*np, hipMemcpyHostToDevice);
hipMemcpy(CHM_TMPgpu, CHMgpu, sizeof(float)*nt*np, hipMemcpyDeviceToDevice);
/*Set up CUDA grid*/
dim3 dimBlock(BLOCK_SIZE,BLOCK_SIZE);
dim3 dimGrid((int)ceil((nt+0.0)/dimBlock.x),
(int)ceil((np+0.0)/dimBlock.y));
/*Start main loop*/
max_iters = *iters;
*iters = 0;
for(k=0;k<max_iters;k++){
/*Reset val_modded*/
val_modded = 0;
hipMemcpy(val_modded_gpu, &val_modded, sizeof(int), hipMemcpyHostToDevice);
/*Perform iteration:*/
ezseg_kernel<<<dimGrid,dimBlock>>>(EUVgpu,CHMgpu,CHM_TMPgpu,nt,np,thresh1,
thresh2,nc,val_modded_gpu);
*iters = *iters + 1;
/*Make sure everything is done*/
hipDeviceSynchronize();
/*Get data mod flag*/
hipMemcpy(&val_modded, val_modded_gpu, sizeof(int), hipMemcpyDeviceToHost);
/*If no new CH points, break out of iterations*/
if(val_modded == 0){
break;
}
/*Reset tmp to be new map iterate for next iteration:*/
hipMemcpy(CHM_TMPgpu,CHMgpu,sizeof(float)*nt*np,hipMemcpyDeviceToDevice);
}
/*Copy result from GPU back to CPU*/
hipMemcpy(CHM,CHMgpu,sizeof(float)*nt*np,hipMemcpyDeviceToHost);
/*Free up GPU memory*/
hipFree(EUVgpu);
hipFree(CHMgpu);
hipFree(CHM_TMPgpu);
hipFree(val_modded_gpu);
} | .text
.file "ezseg_cuda.hip"
.globl _Z27__device_stub__ezseg_kernelPfS_S_iiffiPi # -- Begin function _Z27__device_stub__ezseg_kernelPfS_S_iiffiPi
.p2align 4, 0x90
.type _Z27__device_stub__ezseg_kernelPfS_S_iiffiPi,@function
_Z27__device_stub__ezseg_kernelPfS_S_iiffiPi: # @_Z27__device_stub__ezseg_kernelPfS_S_iiffiPi
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 176(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12ezseg_kernelPfS_S_iiffiPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z27__device_stub__ezseg_kernelPfS_S_iiffiPi, .Lfunc_end0-_Z27__device_stub__ezseg_kernelPfS_S_iiffiPi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function ezseg_cuda
.LCPI1_0:
.quad 0x3fb0000000000000 # double 0.0625
.text
.globl ezseg_cuda
.p2align 4, 0x90
.type ezseg_cuda,@function
ezseg_cuda: # @ezseg_cuda
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movl %r8d, 56(%rsp) # 4-byte Spill
movss %xmm1, 52(%rsp) # 4-byte Spill
movss %xmm0, 48(%rsp) # 4-byte Spill
movq %rsi, %rbp
movq %rdi, %r14
movl %edx, 40(%rsp) # 4-byte Spill
movslq %edx, %r13
movl %ecx, 44(%rsp) # 4-byte Spill
movslq %ecx, %r15
movq %r13, %r12
imulq %r15, %r12
shlq $2, %r12
leaq 32(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq %rsp, %rdi
movq %r12, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 32(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movq %rbp, 88(%rsp) # 8-byte Spill
movq %rbp, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq (%rsp), %rsi
movq %r12, %rdx
movl $3, %ecx
callq hipMemcpy
xorps %xmm0, %xmm0
cvtsi2sd %r13d, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
callq ceil@PLT
movsd %xmm0, 80(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sd %r15d, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
callq ceil@PLT
movl (%rbx), %r13d
movl $0, (%rbx)
testl %r13d, %r13d
jle .LBB1_6
# %bb.1: # %.lr.ph
cvttsd2si 80(%rsp), %eax # 8-byte Folded Reload
cvttsd2si %xmm0, %r14d
shlq $32, %r14
orq %rax, %r14
leaq 12(%rsp), %rbp
movabsq $68719476752, %r15 # imm = 0x1000000010
.p2align 4, 0x90
.LBB1_2: # =>This Inner Loop Header: Depth=1
movl $0, 12(%rsp)
movq 16(%rsp), %rdi
movl $4, %edx
movq %rbp, %rsi
movl $1, %ecx
callq hipMemcpy
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3: # in Loop: Header=BB1_2 Depth=1
movq 32(%rsp), %rax
movq %rax, 168(%rsp)
movq (%rsp), %rax
movq %rax, 160(%rsp)
movq 24(%rsp), %rax
movq %rax, 152(%rsp)
movq 16(%rsp), %rax
movq %rax, 144(%rsp)
movl 40(%rsp), %eax # 4-byte Reload
movl %eax, 76(%rsp)
movl 44(%rsp), %eax # 4-byte Reload
movl %eax, 72(%rsp)
movss 48(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 68(%rsp)
movss 52(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 64(%rsp)
movl 56(%rsp), %eax # 4-byte Reload
movl %eax, 60(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 76(%rsp), %rax
movq %rax, 200(%rsp)
leaq 72(%rsp), %rax
movq %rax, 208(%rsp)
leaq 68(%rsp), %rax
movq %rax, 216(%rsp)
leaq 64(%rsp), %rax
movq %rax, 224(%rsp)
leaq 60(%rsp), %rax
movq %rax, 232(%rsp)
leaq 144(%rsp), %rax
movq %rax, 240(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
movl $_Z12ezseg_kernelPfS_S_iiffiPi, %edi
leaq 176(%rsp), %r9
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4: # in Loop: Header=BB1_2 Depth=1
incl (%rbx)
callq hipDeviceSynchronize
movq 16(%rsp), %rsi
movl $4, %edx
movq %rbp, %rdi
movl $2, %ecx
callq hipMemcpy
cmpl $0, 12(%rsp)
je .LBB1_6
# %bb.5: # in Loop: Header=BB1_2 Depth=1
movq 24(%rsp), %rdi
movq (%rsp), %rsi
movq %r12, %rdx
movl $3, %ecx
callq hipMemcpy
decl %r13d
jne .LBB1_2
.LBB1_6: # %._crit_edge
movq (%rsp), %rsi
movq 88(%rsp), %rdi # 8-byte Reload
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size ezseg_cuda, .Lfunc_end1-ezseg_cuda
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12ezseg_kernelPfS_S_iiffiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12ezseg_kernelPfS_S_iiffiPi,@object # @_Z12ezseg_kernelPfS_S_iiffiPi
.section .rodata,"a",@progbits
.globl _Z12ezseg_kernelPfS_S_iiffiPi
.p2align 3, 0x0
_Z12ezseg_kernelPfS_S_iiffiPi:
.quad _Z27__device_stub__ezseg_kernelPfS_S_iiffiPi
.size _Z12ezseg_kernelPfS_S_iiffiPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12ezseg_kernelPfS_S_iiffiPi"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__ezseg_kernelPfS_S_iiffiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12ezseg_kernelPfS_S_iiffiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00011747_00000000-6_ezseg_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z12ezseg_kernelPfS_S_iiffiPiPfS_S_iiffiPi
.type _Z43__device_stub__Z12ezseg_kernelPfS_S_iiffiPiPfS_S_iiffiPi, @function
_Z43__device_stub__Z12ezseg_kernelPfS_S_iiffiPiPfS_S_iiffiPi:
.LFB2052:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movl %ecx, 36(%rsp)
movl %r8d, 32(%rsp)
movss %xmm0, 28(%rsp)
movss %xmm1, 24(%rsp)
movl %r9d, 20(%rsp)
movq 224(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 28(%rsp), %rax
movq %rax, 168(%rsp)
leaq 24(%rsp), %rax
movq %rax, 176(%rsp)
leaq 20(%rsp), %rax
movq %rax, 184(%rsp)
leaq 8(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z12ezseg_kernelPfS_S_iiffiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z43__device_stub__Z12ezseg_kernelPfS_S_iiffiPiPfS_S_iiffiPi, .-_Z43__device_stub__Z12ezseg_kernelPfS_S_iiffiPiPfS_S_iiffiPi
.globl _Z12ezseg_kernelPfS_S_iiffiPi
.type _Z12ezseg_kernelPfS_S_iiffiPi, @function
_Z12ezseg_kernelPfS_S_iiffiPi:
.LFB2053:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z43__device_stub__Z12ezseg_kernelPfS_S_iiffiPiPfS_S_iiffiPi
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z12ezseg_kernelPfS_S_iiffiPi, .-_Z12ezseg_kernelPfS_S_iiffiPi
.globl ezseg_cuda
.type ezseg_cuda, @function
ezseg_cuda:
.LFB2027:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %rdi, %rbx
movq %rsi, %r14
movq %rsi, 24(%rsp)
movl %edx, 8(%rsp)
movl %ecx, %r15d
movss %xmm0, 12(%rsp)
movss %xmm1, 16(%rsp)
movl %r8d, 20(%rsp)
movq %r9, %rbp
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movslq %edx, %r12
movslq %ecx, %rax
imulq %rax, %r12
salq $2, %r12
leaq 48(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq %rbx, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq %r14, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $3, %ecx
movq %r12, %rdx
movq 56(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 88(%rsp)
pxor %xmm0, %xmm0
cvtsi2sdl %r15d, %xmm0
mulsd .LC0(%rip), %xmm0
movapd %xmm0, %xmm1
movsd .LC4(%rip), %xmm3
movapd %xmm0, %xmm2
andpd %xmm3, %xmm2
movsd .LC1(%rip), %xmm4
ucomisd %xmm2, %xmm4
jbe .L12
cvttsd2siq %xmm0, %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
cmpnlesd %xmm2, %xmm1
movsd .LC3(%rip), %xmm4
andpd %xmm4, %xmm1
addsd %xmm2, %xmm1
andnpd %xmm0, %xmm3
orpd %xmm3, %xmm1
.L12:
pxor %xmm0, %xmm0
cvtsi2sdl 8(%rsp), %xmm0
mulsd .LC0(%rip), %xmm0
movapd %xmm0, %xmm4
movsd .LC4(%rip), %xmm3
movapd %xmm0, %xmm2
andpd %xmm3, %xmm2
movsd .LC1(%rip), %xmm5
ucomisd %xmm2, %xmm5
jbe .L13
cvttsd2siq %xmm0, %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
cmpnlesd %xmm2, %xmm4
movsd .LC3(%rip), %xmm5
andpd %xmm5, %xmm4
addsd %xmm2, %xmm4
andnpd %xmm0, %xmm3
orpd %xmm3, %xmm4
.L13:
cvttsd2sil %xmm4, %eax
movl %eax, 92(%rsp)
cvttsd2sil %xmm1, %eax
movl %eax, 96(%rsp)
movl $1, 100(%rsp)
movl 0(%rbp), %r14d
movl $0, 0(%rbp)
testl %r14d, %r14d
jle .L14
movl $0, %ebx
leaq 44(%rsp), %r13
jmp .L16
.L15:
addl $1, 0(%rbp)
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $4, %edx
movq 72(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
cmpl $0, 44(%rsp)
je .L14
movl $3, %ecx
movq %r12, %rdx
movq 56(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
addl $1, %ebx
cmpl %ebx, %r14d
je .L14
.L16:
movl $0, 44(%rsp)
movl $1, %ecx
movl $4, %edx
movq %r13, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 80(%rsp)
movl $16, 84(%rsp)
movl 88(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movq 92(%rsp), %rdi
movl 100(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L15
subq $8, %rsp
.cfi_def_cfa_offset 184
pushq 80(%rsp)
.cfi_def_cfa_offset 192
movl 36(%rsp), %r9d
movss 32(%rsp), %xmm1
movss 28(%rsp), %xmm0
movl %r15d, %r8d
movl 24(%rsp), %ecx
movq 80(%rsp), %rdx
movq 72(%rsp), %rsi
movq 64(%rsp), %rdi
call _Z43__device_stub__Z12ezseg_kernelPfS_S_iiffiPiPfS_S_iiffiPi
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L15
.L14:
movl $2, %ecx
movq %r12, %rdx
movq 56(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size ezseg_cuda, .-ezseg_cuda
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "_Z12ezseg_kernelPfS_S_iiffiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z12ezseg_kernelPfS_S_iiffiPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1068498944
.align 8
.LC1:
.long 0
.long 1127219200
.align 8
.LC3:
.long 0
.long 1072693248
.align 8
.LC4:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ezseg_cuda.hip"
.globl _Z27__device_stub__ezseg_kernelPfS_S_iiffiPi # -- Begin function _Z27__device_stub__ezseg_kernelPfS_S_iiffiPi
.p2align 4, 0x90
.type _Z27__device_stub__ezseg_kernelPfS_S_iiffiPi,@function
_Z27__device_stub__ezseg_kernelPfS_S_iiffiPi: # @_Z27__device_stub__ezseg_kernelPfS_S_iiffiPi
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 176(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12ezseg_kernelPfS_S_iiffiPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z27__device_stub__ezseg_kernelPfS_S_iiffiPi, .Lfunc_end0-_Z27__device_stub__ezseg_kernelPfS_S_iiffiPi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function ezseg_cuda
.LCPI1_0:
.quad 0x3fb0000000000000 # double 0.0625
.text
.globl ezseg_cuda
.p2align 4, 0x90
.type ezseg_cuda,@function
ezseg_cuda: # @ezseg_cuda
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movl %r8d, 56(%rsp) # 4-byte Spill
movss %xmm1, 52(%rsp) # 4-byte Spill
movss %xmm0, 48(%rsp) # 4-byte Spill
movq %rsi, %rbp
movq %rdi, %r14
movl %edx, 40(%rsp) # 4-byte Spill
movslq %edx, %r13
movl %ecx, 44(%rsp) # 4-byte Spill
movslq %ecx, %r15
movq %r13, %r12
imulq %r15, %r12
shlq $2, %r12
leaq 32(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq %rsp, %rdi
movq %r12, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 32(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movq %rbp, 88(%rsp) # 8-byte Spill
movq %rbp, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq (%rsp), %rsi
movq %r12, %rdx
movl $3, %ecx
callq hipMemcpy
xorps %xmm0, %xmm0
cvtsi2sd %r13d, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
callq ceil@PLT
movsd %xmm0, 80(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sd %r15d, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
callq ceil@PLT
movl (%rbx), %r13d
movl $0, (%rbx)
testl %r13d, %r13d
jle .LBB1_6
# %bb.1: # %.lr.ph
cvttsd2si 80(%rsp), %eax # 8-byte Folded Reload
cvttsd2si %xmm0, %r14d
shlq $32, %r14
orq %rax, %r14
leaq 12(%rsp), %rbp
movabsq $68719476752, %r15 # imm = 0x1000000010
.p2align 4, 0x90
.LBB1_2: # =>This Inner Loop Header: Depth=1
movl $0, 12(%rsp)
movq 16(%rsp), %rdi
movl $4, %edx
movq %rbp, %rsi
movl $1, %ecx
callq hipMemcpy
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3: # in Loop: Header=BB1_2 Depth=1
movq 32(%rsp), %rax
movq %rax, 168(%rsp)
movq (%rsp), %rax
movq %rax, 160(%rsp)
movq 24(%rsp), %rax
movq %rax, 152(%rsp)
movq 16(%rsp), %rax
movq %rax, 144(%rsp)
movl 40(%rsp), %eax # 4-byte Reload
movl %eax, 76(%rsp)
movl 44(%rsp), %eax # 4-byte Reload
movl %eax, 72(%rsp)
movss 48(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 68(%rsp)
movss 52(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 64(%rsp)
movl 56(%rsp), %eax # 4-byte Reload
movl %eax, 60(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 76(%rsp), %rax
movq %rax, 200(%rsp)
leaq 72(%rsp), %rax
movq %rax, 208(%rsp)
leaq 68(%rsp), %rax
movq %rax, 216(%rsp)
leaq 64(%rsp), %rax
movq %rax, 224(%rsp)
leaq 60(%rsp), %rax
movq %rax, 232(%rsp)
leaq 144(%rsp), %rax
movq %rax, 240(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
movl $_Z12ezseg_kernelPfS_S_iiffiPi, %edi
leaq 176(%rsp), %r9
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4: # in Loop: Header=BB1_2 Depth=1
incl (%rbx)
callq hipDeviceSynchronize
movq 16(%rsp), %rsi
movl $4, %edx
movq %rbp, %rdi
movl $2, %ecx
callq hipMemcpy
cmpl $0, 12(%rsp)
je .LBB1_6
# %bb.5: # in Loop: Header=BB1_2 Depth=1
movq 24(%rsp), %rdi
movq (%rsp), %rsi
movq %r12, %rdx
movl $3, %ecx
callq hipMemcpy
decl %r13d
jne .LBB1_2
.LBB1_6: # %._crit_edge
movq (%rsp), %rsi
movq 88(%rsp), %rdi # 8-byte Reload
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size ezseg_cuda, .Lfunc_end1-ezseg_cuda
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12ezseg_kernelPfS_S_iiffiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12ezseg_kernelPfS_S_iiffiPi,@object # @_Z12ezseg_kernelPfS_S_iiffiPi
.section .rodata,"a",@progbits
.globl _Z12ezseg_kernelPfS_S_iiffiPi
.p2align 3, 0x0
_Z12ezseg_kernelPfS_S_iiffiPi:
.quad _Z27__device_stub__ezseg_kernelPfS_S_iiffiPi
.size _Z12ezseg_kernelPfS_S_iiffiPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12ezseg_kernelPfS_S_iiffiPi"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__ezseg_kernelPfS_S_iiffiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12ezseg_kernelPfS_S_iiffiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "../ginkgo/loaddata.hpp"
#include "../ginkgo/GOrder.h"
#include "../ginkgo/GOrderList.h"
#include "../ginkgo/GOrderHandler.h"
#include "../include/lglist.h"
#include <thrust/device_vector.h>
#include <thrust/copy.h>
#include <thrust/sequence.h>
#include <thrust/execution_policy.h>
#define to_ptr(x) thrust::raw_pointer_cast(&x[0])
#define gpu_copy(x, y) thrust::copy((x).begin(), (x).end(), (y).begin())
#define gpu_copy_to(x, y, pos) thrust::copy((x).begin(), (x).end(), (y).begin() + (pos))
#define gpu_seq(x) thrust::sequence((x).begin(), (x).end())
#define def_dvec(t) thrust::device_vector<t>
using namespace std;
const int level_lim = 90;
const int order_lim = 100;
__global__ void simKernel(int N_tstamp, int base_p, int *booksize, int *ask, int *bid,
int *tprice, int *tsize, int *tside, float *t_stamp, float *ltcy, int *ans){
int max_position = 15;
int level_order_lim = 5;
gpu_ginkgo::OrderHandler<order_lim, level_lim> ohandler(base_p, level_order_lim);
ohandler.loadStrategy(max_position, 0., 0.);
for(int t=0;t<N_tstamp;++t){
ohandler.getTimeInfo(t_stamp[t], ltcy[t]);
if(!tside[t]){
ohandler.bookUpdateSim(booksize+t*level_lim, ask[t], bid[t], 0.5*(ask[t] + bid[t]));
ohandler.cancelAndSendNewOrders();
}
else{
bool sell = (tside[t] == -1);
ohandler.processTrade(sell, tprice[t], tsize[t]);
ohandler.cancelAndSendNewOrders();
}
if(t%100 == 0){
ohandler.showBasicInfo();
}
}
ans[0] = ohandler.total_pnl;
ans[1] = ohandler.pos;
ans[2] = ohandler.total_qty;
}
int main(int argc, char* argv[]){
assert(argc > 1);
LoadData ld(argv[1], 0.1);
int Level_lim = ld.preProcess();
auto bzs = ld.getBookSize();
auto ask = ld.getAsk();
auto bid = ld.getBid();
auto tsz = ld.getTradeSize();
auto tsd = ld.getTradeSide();
auto tp = ld.getTradePrice();
auto tstamps = ld.getTimeStamp();
auto base_p = ld.getBasePrice();
int Ns = (int)ask.size();
cout<<endl;
cout<<ask[0]<<' '<<bid[0]<<endl;
cout<<tsz[0]<<' '<<tsd[0]<<' '<<tp[0]<<endl;
cout<<tstamps[0]<<endl;
cout<<Level_lim <<' '<<base_p<<endl;
cout<<"====================== Start simulation ======================"<<endl<<endl;
def_dvec(int) d_bz(Ns * level_lim, 0), d_ap(Ns), d_bp(Ns), d_tsz(Ns), d_tp(Ns), d_tsd(Ns);
def_dvec(float) d_t(Ns), d_ltcy(Ns, 0.);
gpu_copy(ask, d_ap);
gpu_copy(bid, d_bp);
gpu_copy(tsz, d_tsz);
gpu_copy(tsd, d_tsd);
gpu_copy(tp, d_tp);
gpu_copy(tstamps, d_t);
for(int i=0;i<Ns;++i){
gpu_copy_to(bzs[i], d_bz, i*level_lim);
}
def_dvec(int) ans(3, 0);
cudaEvent_t start, stop;
float cuda_time;
cudaEventCreate(&start); // creating the event 1
cudaEventCreate(&stop); // creating the event 2
cudaEventRecord(start, 0);
//Running the kernel
simKernel<<<1, 2>>>(Ns, base_p, to_ptr(d_bz), to_ptr(d_ap), to_ptr(d_bp),
to_ptr(d_tp), to_ptr(d_tsz), to_ptr(d_tsd), to_ptr(d_t), to_ptr(d_ltcy), to_ptr(ans));
cudaEventRecord(stop, 0); // Stop time measuring
cudaEventSynchronize(stop);
cudaEventElapsedTime(&cuda_time, start, stop); // Saving the time measured
cout<<"Time Usage for sim is: "<<cuda_time/1000<<"s"<<endl;
cout<<"Total pnl = "<<ans[0]<<endl;
cout<<"Current Position = "<<ans[1]<<endl;
cout<<"Total trades = "<<ans[2]<<endl;
return 0;
} | #include <hip/hip_runtime.h>
#include "../ginkgo/loaddata.hpp"
#include "../ginkgo/GOrder.h"
#include "../ginkgo/GOrderList.h"
#include "../ginkgo/GOrderHandler.h"
#include "../include/lglist.h"
#include <thrust/device_vector.h>
#include <thrust/copy.h>
#include <thrust/sequence.h>
#include <thrust/execution_policy.h>
#define to_ptr(x) thrust::raw_pointer_cast(&x[0])
#define gpu_copy(x, y) thrust::copy((x).begin(), (x).end(), (y).begin())
#define gpu_copy_to(x, y, pos) thrust::copy((x).begin(), (x).end(), (y).begin() + (pos))
#define gpu_seq(x) thrust::sequence((x).begin(), (x).end())
#define def_dvec(t) thrust::device_vector<t>
using namespace std;
const int level_lim = 90;
const int order_lim = 100;
__global__ void simKernel(int N_tstamp, int base_p, int *booksize, int *ask, int *bid,
int *tprice, int *tsize, int *tside, float *t_stamp, float *ltcy, int *ans){
int max_position = 15;
int level_order_lim = 5;
gpu_ginkgo::OrderHandler<order_lim, level_lim> ohandler(base_p, level_order_lim);
ohandler.loadStrategy(max_position, 0., 0.);
for(int t=0;t<N_tstamp;++t){
ohandler.getTimeInfo(t_stamp[t], ltcy[t]);
if(!tside[t]){
ohandler.bookUpdateSim(booksize+t*level_lim, ask[t], bid[t], 0.5*(ask[t] + bid[t]));
ohandler.cancelAndSendNewOrders();
}
else{
bool sell = (tside[t] == -1);
ohandler.processTrade(sell, tprice[t], tsize[t]);
ohandler.cancelAndSendNewOrders();
}
if(t%100 == 0){
ohandler.showBasicInfo();
}
}
ans[0] = ohandler.total_pnl;
ans[1] = ohandler.pos;
ans[2] = ohandler.total_qty;
}
int main(int argc, char* argv[]){
assert(argc > 1);
LoadData ld(argv[1], 0.1);
int Level_lim = ld.preProcess();
auto bzs = ld.getBookSize();
auto ask = ld.getAsk();
auto bid = ld.getBid();
auto tsz = ld.getTradeSize();
auto tsd = ld.getTradeSide();
auto tp = ld.getTradePrice();
auto tstamps = ld.getTimeStamp();
auto base_p = ld.getBasePrice();
int Ns = (int)ask.size();
cout<<endl;
cout<<ask[0]<<' '<<bid[0]<<endl;
cout<<tsz[0]<<' '<<tsd[0]<<' '<<tp[0]<<endl;
cout<<tstamps[0]<<endl;
cout<<Level_lim <<' '<<base_p<<endl;
cout<<"====================== Start simulation ======================"<<endl<<endl;
def_dvec(int) d_bz(Ns * level_lim, 0), d_ap(Ns), d_bp(Ns), d_tsz(Ns), d_tp(Ns), d_tsd(Ns);
def_dvec(float) d_t(Ns), d_ltcy(Ns, 0.);
gpu_copy(ask, d_ap);
gpu_copy(bid, d_bp);
gpu_copy(tsz, d_tsz);
gpu_copy(tsd, d_tsd);
gpu_copy(tp, d_tp);
gpu_copy(tstamps, d_t);
for(int i=0;i<Ns;++i){
gpu_copy_to(bzs[i], d_bz, i*level_lim);
}
def_dvec(int) ans(3, 0);
hipEvent_t start, stop;
float cuda_time;
hipEventCreate(&start); // creating the event 1
hipEventCreate(&stop); // creating the event 2
hipEventRecord(start, 0);
//Running the kernel
simKernel<<<1, 2>>>(Ns, base_p, to_ptr(d_bz), to_ptr(d_ap), to_ptr(d_bp),
to_ptr(d_tp), to_ptr(d_tsz), to_ptr(d_tsd), to_ptr(d_t), to_ptr(d_ltcy), to_ptr(ans));
hipEventRecord(stop, 0); // Stop time measuring
hipEventSynchronize(stop);
hipEventElapsedTime(&cuda_time, start, stop); // Saving the time measured
cout<<"Time Usage for sim is: "<<cuda_time/1000<<"s"<<endl;
cout<<"Total pnl = "<<ans[0]<<endl;
cout<<"Current Position = "<<ans[1]<<endl;
cout<<"Total trades = "<<ans[2]<<endl;
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <stdio.h>
#define BLOCKSIZE 256
__global__ void kern_set_val (float *gpu_ptr, float value, int nb) {
int i;
i=blockDim.x * blockIdx.x+threadIdx.x;
gpu_ptr[i] = value;
}
extern "C" void set_value (float *ptr, float value, int nb) {
float *gpu_ptr;
cudaMalloc (&gpu_ptr, sizeof(float)*nb);
//UP TO YOU : write kernel invocation here
kern_set_val <<<nb/BLOCKSIZE,BLOCKSIZE>>>(gpu_ptr,value,nb);
cudaThreadSynchronize ();
cudaMemcpy(ptr,gpu_ptr,nb*sizeof(float),cudaMemcpyDeviceToHost);
cudaFree (gpu_ptr);
} | code for sm_80
Function : _Z12kern_set_valPffi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R7, c[0x0][0x168] ; /* 0x00005a0000077a02 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0070*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0205 */
/*0080*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <stdio.h>
#define BLOCKSIZE 256
__global__ void kern_set_val (float *gpu_ptr, float value, int nb) {
int i;
i=blockDim.x * blockIdx.x+threadIdx.x;
gpu_ptr[i] = value;
}
extern "C" void set_value (float *ptr, float value, int nb) {
float *gpu_ptr;
cudaMalloc (&gpu_ptr, sizeof(float)*nb);
//UP TO YOU : write kernel invocation here
kern_set_val <<<nb/BLOCKSIZE,BLOCKSIZE>>>(gpu_ptr,value,nb);
cudaThreadSynchronize ();
cudaMemcpy(ptr,gpu_ptr,nb*sizeof(float),cudaMemcpyDeviceToHost);
cudaFree (gpu_ptr);
} | .file "tmpxft_00186c20_00000000-6_setvec.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z12kern_set_valPffiPffi
.type _Z34__device_stub__Z12kern_set_valPffiPffi, @function
_Z34__device_stub__Z12kern_set_valPffiPffi:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movss %xmm0, 4(%rsp)
movl %esi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12kern_set_valPffi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z12kern_set_valPffiPffi, .-_Z34__device_stub__Z12kern_set_valPffiPffi
.globl _Z12kern_set_valPffi
.type _Z12kern_set_valPffi, @function
_Z12kern_set_valPffi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z12kern_set_valPffiPffi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12kern_set_valPffi, .-_Z12kern_set_valPffi
.globl set_value
.type set_value, @function
set_value:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r12
movss %xmm0, 12(%rsp)
movl %esi, %ebx
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movslq %esi, %rbp
salq $2, %rbp
leaq 24(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $256, 44(%rsp)
movl $1, 48(%rsp)
leal 255(%rbx), %eax
testl %ebx, %ebx
cmovns %ebx, %eax
sarl $8, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl %ebx, %esi
movss 12(%rsp), %xmm0
movq 24(%rsp), %rdi
call _Z34__device_stub__Z12kern_set_valPffiPffi
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size set_value, .-set_value
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12kern_set_valPffi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12kern_set_valPffi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <stdio.h>
#define BLOCKSIZE 256
__global__ void kern_set_val (float *gpu_ptr, float value, int nb) {
int i;
i=blockDim.x * blockIdx.x+threadIdx.x;
gpu_ptr[i] = value;
}
extern "C" void set_value (float *ptr, float value, int nb) {
float *gpu_ptr;
cudaMalloc (&gpu_ptr, sizeof(float)*nb);
//UP TO YOU : write kernel invocation here
kern_set_val <<<nb/BLOCKSIZE,BLOCKSIZE>>>(gpu_ptr,value,nb);
cudaThreadSynchronize ();
cudaMemcpy(ptr,gpu_ptr,nb*sizeof(float),cudaMemcpyDeviceToHost);
cudaFree (gpu_ptr);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define BLOCKSIZE 256
__global__ void kern_set_val (float *gpu_ptr, float value, int nb) {
int i;
i=blockDim.x * blockIdx.x+threadIdx.x;
gpu_ptr[i] = value;
}
extern "C" void set_value (float *ptr, float value, int nb) {
float *gpu_ptr;
hipMalloc (&gpu_ptr, sizeof(float)*nb);
//UP TO YOU : write kernel invocation here
kern_set_val <<<nb/BLOCKSIZE,BLOCKSIZE>>>(gpu_ptr,value,nb);
hipDeviceSynchronize ();
hipMemcpy(ptr,gpu_ptr,nb*sizeof(float),hipMemcpyDeviceToHost);
hipFree (gpu_ptr);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define BLOCKSIZE 256
__global__ void kern_set_val (float *gpu_ptr, float value, int nb) {
int i;
i=blockDim.x * blockIdx.x+threadIdx.x;
gpu_ptr[i] = value;
}
extern "C" void set_value (float *ptr, float value, int nb) {
float *gpu_ptr;
hipMalloc (&gpu_ptr, sizeof(float)*nb);
//UP TO YOU : write kernel invocation here
kern_set_val <<<nb/BLOCKSIZE,BLOCKSIZE>>>(gpu_ptr,value,nb);
hipDeviceSynchronize ();
hipMemcpy(ptr,gpu_ptr,nb*sizeof(float),hipMemcpyDeviceToHost);
hipFree (gpu_ptr);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12kern_set_valPffi
.globl _Z12kern_set_valPffi
.p2align 8
.type _Z12kern_set_valPffi,@function
_Z12kern_set_valPffi:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_load_b64 s[2:3], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_load_b32 s0, s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_mov_b32_e32 v2, s0
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12kern_set_valPffi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12kern_set_valPffi, .Lfunc_end0-_Z12kern_set_valPffi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12kern_set_valPffi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12kern_set_valPffi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define BLOCKSIZE 256
__global__ void kern_set_val (float *gpu_ptr, float value, int nb) {
int i;
i=blockDim.x * blockIdx.x+threadIdx.x;
gpu_ptr[i] = value;
}
extern "C" void set_value (float *ptr, float value, int nb) {
float *gpu_ptr;
hipMalloc (&gpu_ptr, sizeof(float)*nb);
//UP TO YOU : write kernel invocation here
kern_set_val <<<nb/BLOCKSIZE,BLOCKSIZE>>>(gpu_ptr,value,nb);
hipDeviceSynchronize ();
hipMemcpy(ptr,gpu_ptr,nb*sizeof(float),hipMemcpyDeviceToHost);
hipFree (gpu_ptr);
} | .text
.file "setvec.hip"
.globl _Z27__device_stub__kern_set_valPffi # -- Begin function _Z27__device_stub__kern_set_valPffi
.p2align 4, 0x90
.type _Z27__device_stub__kern_set_valPffi,@function
_Z27__device_stub__kern_set_valPffi: # @_Z27__device_stub__kern_set_valPffi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movss %xmm0, 4(%rsp)
movl %esi, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12kern_set_valPffi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z27__device_stub__kern_set_valPffi, .Lfunc_end0-_Z27__device_stub__kern_set_valPffi
.cfi_endproc
# -- End function
.globl set_value # -- Begin function set_value
.p2align 4, 0x90
.type set_value,@function
set_value: # @set_value
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $104, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movss %xmm0, 12(%rsp) # 4-byte Spill
movq %rdi, %r14
movslq %esi, %r15
leaq (,%r15,4), %rbx
movq %rsp, %rdi
movq %rbx, %rsi
callq hipMalloc
leal 255(%r15), %edi
testl %r15d, %r15d
cmovnsl %ebp, %edi
sarl $8, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq (%rsp), %rax
movq %rax, 72(%rsp)
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 20(%rsp)
movl %ebp, 16(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12kern_set_valPffi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
movq (%rsp), %rsi
movq %r14, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
callq hipFree
addq $104, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size set_value, .Lfunc_end1-set_value
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12kern_set_valPffi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12kern_set_valPffi,@object # @_Z12kern_set_valPffi
.section .rodata,"a",@progbits
.globl _Z12kern_set_valPffi
.p2align 3, 0x0
_Z12kern_set_valPffi:
.quad _Z27__device_stub__kern_set_valPffi
.size _Z12kern_set_valPffi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12kern_set_valPffi"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__kern_set_valPffi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12kern_set_valPffi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12kern_set_valPffi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R7, c[0x0][0x168] ; /* 0x00005a0000077a02 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0070*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0205 */
/*0080*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12kern_set_valPffi
.globl _Z12kern_set_valPffi
.p2align 8
.type _Z12kern_set_valPffi,@function
_Z12kern_set_valPffi:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_load_b64 s[2:3], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_load_b32 s0, s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_mov_b32_e32 v2, s0
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12kern_set_valPffi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12kern_set_valPffi, .Lfunc_end0-_Z12kern_set_valPffi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12kern_set_valPffi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12kern_set_valPffi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00186c20_00000000-6_setvec.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z12kern_set_valPffiPffi
.type _Z34__device_stub__Z12kern_set_valPffiPffi, @function
_Z34__device_stub__Z12kern_set_valPffiPffi:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movss %xmm0, 4(%rsp)
movl %esi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12kern_set_valPffi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z12kern_set_valPffiPffi, .-_Z34__device_stub__Z12kern_set_valPffiPffi
.globl _Z12kern_set_valPffi
.type _Z12kern_set_valPffi, @function
_Z12kern_set_valPffi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z12kern_set_valPffiPffi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12kern_set_valPffi, .-_Z12kern_set_valPffi
.globl set_value
.type set_value, @function
set_value:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r12
movss %xmm0, 12(%rsp)
movl %esi, %ebx
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movslq %esi, %rbp
salq $2, %rbp
leaq 24(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $256, 44(%rsp)
movl $1, 48(%rsp)
leal 255(%rbx), %eax
testl %ebx, %ebx
cmovns %ebx, %eax
sarl $8, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl %ebx, %esi
movss 12(%rsp), %xmm0
movq 24(%rsp), %rdi
call _Z34__device_stub__Z12kern_set_valPffiPffi
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size set_value, .-set_value
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12kern_set_valPffi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12kern_set_valPffi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "setvec.hip"
.globl _Z27__device_stub__kern_set_valPffi # -- Begin function _Z27__device_stub__kern_set_valPffi
.p2align 4, 0x90
.type _Z27__device_stub__kern_set_valPffi,@function
_Z27__device_stub__kern_set_valPffi: # @_Z27__device_stub__kern_set_valPffi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movss %xmm0, 4(%rsp)
movl %esi, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12kern_set_valPffi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z27__device_stub__kern_set_valPffi, .Lfunc_end0-_Z27__device_stub__kern_set_valPffi
.cfi_endproc
# -- End function
.globl set_value # -- Begin function set_value
.p2align 4, 0x90
.type set_value,@function
set_value: # @set_value
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $104, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movss %xmm0, 12(%rsp) # 4-byte Spill
movq %rdi, %r14
movslq %esi, %r15
leaq (,%r15,4), %rbx
movq %rsp, %rdi
movq %rbx, %rsi
callq hipMalloc
leal 255(%r15), %edi
testl %r15d, %r15d
cmovnsl %ebp, %edi
sarl $8, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq (%rsp), %rax
movq %rax, 72(%rsp)
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 20(%rsp)
movl %ebp, 16(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12kern_set_valPffi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
movq (%rsp), %rsi
movq %r14, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
callq hipFree
addq $104, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size set_value, .Lfunc_end1-set_value
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12kern_set_valPffi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12kern_set_valPffi,@object # @_Z12kern_set_valPffi
.section .rodata,"a",@progbits
.globl _Z12kern_set_valPffi
.p2align 3, 0x0
_Z12kern_set_valPffi:
.quad _Z27__device_stub__kern_set_valPffi
.size _Z12kern_set_valPffi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12kern_set_valPffi"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__kern_set_valPffi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12kern_set_valPffi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __device__ float backwardSigmoid (float forward, float chain)
{
return forward * (1.0 - forward) * chain;
}
extern "C"
__global__ void backwardSigmoidKernel (int length, float *forward, float *chain, float *destination)
{
int index = blockDim.x * blockIdx.x + threadIdx.x;
if(index < length) {
destination[index] = backwardSigmoid(forward[index], chain[index]);
}
} | code for sm_80
Function : backwardSigmoidKernel
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R13, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0d7435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R13, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e020d */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R0, R13, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fcc00078e020d */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee2000c1e1900 */
/*00c0*/ F2F.F64.F32 R6, R2 ; /* 0x0000000200067310 */
/* 0x004e300000201800 */
/*00d0*/ F2F.F64.F32 R10, R4 ; /* 0x00000004000a7310 */
/* 0x008e620000201800 */
/*00e0*/ DADD R8, -R6, 1 ; /* 0x3ff0000006087429 */
/* 0x001e0c0000000100 */
/*00f0*/ DMUL R8, R6, R8 ; /* 0x0000000806087228 */
/* 0x0010640000000000 */
/*0100*/ IMAD.WIDE R6, R0, R13, c[0x0][0x178] ; /* 0x00005e0000067625 */
/* 0x001fc800078e020d */
/*0110*/ DMUL R8, R8, R10 ; /* 0x0000000a08087228 */
/* 0x002e140000000000 */
/*0120*/ F2F.F32.F64 R9, R8 ; /* 0x0000000800097310 */
/* 0x001e240000301000 */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x001fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __device__ float backwardSigmoid (float forward, float chain)
{
return forward * (1.0 - forward) * chain;
}
extern "C"
__global__ void backwardSigmoidKernel (int length, float *forward, float *chain, float *destination)
{
int index = blockDim.x * blockIdx.x + threadIdx.x;
if(index < length) {
destination[index] = backwardSigmoid(forward[index], chain[index]);
}
} | .file "tmpxft_0010434e_00000000-6_BackwardSigmoidKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15backwardSigmoidff
.type _Z15backwardSigmoidff, @function
_Z15backwardSigmoidff:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z15backwardSigmoidff, .-_Z15backwardSigmoidff
.globl _Z46__device_stub__Z21backwardSigmoidKerneliPfS_S_iPfS_S_
.type _Z46__device_stub__Z21backwardSigmoidKerneliPfS_S_iPfS_S_, @function
_Z46__device_stub__Z21backwardSigmoidKerneliPfS_S_iPfS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq backwardSigmoidKernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z46__device_stub__Z21backwardSigmoidKerneliPfS_S_iPfS_S_, .-_Z46__device_stub__Z21backwardSigmoidKerneliPfS_S_iPfS_S_
.globl backwardSigmoidKernel
.type backwardSigmoidKernel, @function
backwardSigmoidKernel:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z21backwardSigmoidKerneliPfS_S_iPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size backwardSigmoidKernel, .-backwardSigmoidKernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "backwardSigmoidKernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq backwardSigmoidKernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __device__ float backwardSigmoid (float forward, float chain)
{
return forward * (1.0 - forward) * chain;
}
extern "C"
__global__ void backwardSigmoidKernel (int length, float *forward, float *chain, float *destination)
{
int index = blockDim.x * blockIdx.x + threadIdx.x;
if(index < length) {
destination[index] = backwardSigmoid(forward[index], chain[index]);
}
} | #include <hip/hip_runtime.h>
__device__ float backwardSigmoid (float forward, float chain)
{
return forward * (1.0 - forward) * chain;
}
extern "C"
__global__ void backwardSigmoidKernel (int length, float *forward, float *chain, float *destination)
{
int index = blockDim.x * blockIdx.x + threadIdx.x;
if(index < length) {
destination[index] = backwardSigmoid(forward[index], chain[index]);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__device__ float backwardSigmoid (float forward, float chain)
{
return forward * (1.0 - forward) * chain;
}
extern "C"
__global__ void backwardSigmoidKernel (int length, float *forward, float *chain, float *destination)
{
int index = blockDim.x * blockIdx.x + threadIdx.x;
if(index < length) {
destination[index] = backwardSigmoid(forward[index], chain[index]);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected backwardSigmoidKernel
.globl backwardSigmoidKernel
.p2align 8
.type backwardSigmoidKernel,@function
backwardSigmoidKernel:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
global_load_b32 v4, v[2:3], off
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v6, v[2:3], off
s_waitcnt vmcnt(1)
v_cvt_f64_f32_e32 v[2:3], v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], -v[2:3], 1.0
v_mul_f64 v[2:3], v[4:5], v[2:3]
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[4:5], v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[2:3], v[2:3], v[4:5]
v_cvt_f32_f64_e32 v2, v[2:3]
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel backwardSigmoidKernel
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size backwardSigmoidKernel, .Lfunc_end0-backwardSigmoidKernel
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: backwardSigmoidKernel
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: backwardSigmoidKernel.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__device__ float backwardSigmoid (float forward, float chain)
{
return forward * (1.0 - forward) * chain;
}
extern "C"
__global__ void backwardSigmoidKernel (int length, float *forward, float *chain, float *destination)
{
int index = blockDim.x * blockIdx.x + threadIdx.x;
if(index < length) {
destination[index] = backwardSigmoid(forward[index], chain[index]);
}
} | .text
.file "BackwardSigmoidKernel.hip"
.globl __device_stub__backwardSigmoidKernel # -- Begin function __device_stub__backwardSigmoidKernel
.p2align 4, 0x90
.type __device_stub__backwardSigmoidKernel,@function
__device_stub__backwardSigmoidKernel: # @__device_stub__backwardSigmoidKernel
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $backwardSigmoidKernel, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__backwardSigmoidKernel, .Lfunc_end0-__device_stub__backwardSigmoidKernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $backwardSigmoidKernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type backwardSigmoidKernel,@object # @backwardSigmoidKernel
.section .rodata,"a",@progbits
.globl backwardSigmoidKernel
.p2align 3, 0x0
backwardSigmoidKernel:
.quad __device_stub__backwardSigmoidKernel
.size backwardSigmoidKernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "backwardSigmoidKernel"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__backwardSigmoidKernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym backwardSigmoidKernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : backwardSigmoidKernel
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R13, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0d7435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R13, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e020d */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R0, R13, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fcc00078e020d */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee2000c1e1900 */
/*00c0*/ F2F.F64.F32 R6, R2 ; /* 0x0000000200067310 */
/* 0x004e300000201800 */
/*00d0*/ F2F.F64.F32 R10, R4 ; /* 0x00000004000a7310 */
/* 0x008e620000201800 */
/*00e0*/ DADD R8, -R6, 1 ; /* 0x3ff0000006087429 */
/* 0x001e0c0000000100 */
/*00f0*/ DMUL R8, R6, R8 ; /* 0x0000000806087228 */
/* 0x0010640000000000 */
/*0100*/ IMAD.WIDE R6, R0, R13, c[0x0][0x178] ; /* 0x00005e0000067625 */
/* 0x001fc800078e020d */
/*0110*/ DMUL R8, R8, R10 ; /* 0x0000000a08087228 */
/* 0x002e140000000000 */
/*0120*/ F2F.F32.F64 R9, R8 ; /* 0x0000000800097310 */
/* 0x001e240000301000 */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x001fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected backwardSigmoidKernel
.globl backwardSigmoidKernel
.p2align 8
.type backwardSigmoidKernel,@function
backwardSigmoidKernel:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
global_load_b32 v4, v[2:3], off
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v6, v[2:3], off
s_waitcnt vmcnt(1)
v_cvt_f64_f32_e32 v[2:3], v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], -v[2:3], 1.0
v_mul_f64 v[2:3], v[4:5], v[2:3]
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[4:5], v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[2:3], v[2:3], v[4:5]
v_cvt_f32_f64_e32 v2, v[2:3]
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel backwardSigmoidKernel
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size backwardSigmoidKernel, .Lfunc_end0-backwardSigmoidKernel
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: backwardSigmoidKernel
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: backwardSigmoidKernel.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010434e_00000000-6_BackwardSigmoidKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15backwardSigmoidff
.type _Z15backwardSigmoidff, @function
_Z15backwardSigmoidff:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z15backwardSigmoidff, .-_Z15backwardSigmoidff
.globl _Z46__device_stub__Z21backwardSigmoidKerneliPfS_S_iPfS_S_
.type _Z46__device_stub__Z21backwardSigmoidKerneliPfS_S_iPfS_S_, @function
_Z46__device_stub__Z21backwardSigmoidKerneliPfS_S_iPfS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq backwardSigmoidKernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z46__device_stub__Z21backwardSigmoidKerneliPfS_S_iPfS_S_, .-_Z46__device_stub__Z21backwardSigmoidKerneliPfS_S_iPfS_S_
.globl backwardSigmoidKernel
.type backwardSigmoidKernel, @function
backwardSigmoidKernel:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z21backwardSigmoidKerneliPfS_S_iPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size backwardSigmoidKernel, .-backwardSigmoidKernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "backwardSigmoidKernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq backwardSigmoidKernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "BackwardSigmoidKernel.hip"
.globl __device_stub__backwardSigmoidKernel # -- Begin function __device_stub__backwardSigmoidKernel
.p2align 4, 0x90
.type __device_stub__backwardSigmoidKernel,@function
__device_stub__backwardSigmoidKernel: # @__device_stub__backwardSigmoidKernel
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $backwardSigmoidKernel, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__backwardSigmoidKernel, .Lfunc_end0-__device_stub__backwardSigmoidKernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $backwardSigmoidKernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type backwardSigmoidKernel,@object # @backwardSigmoidKernel
.section .rodata,"a",@progbits
.globl backwardSigmoidKernel
.p2align 3, 0x0
backwardSigmoidKernel:
.quad __device_stub__backwardSigmoidKernel
.size backwardSigmoidKernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "backwardSigmoidKernel"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__backwardSigmoidKernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym backwardSigmoidKernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
#include <assert.h>
__global__ void matrixMult(int *A, int *B, int *C, int N){
// Calculate the global row and column for each thread
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if(row < N && col < N){
// def temprary variable for storing sum
int tmp = 0;
for(int i = 0; i < N; i++){
tmp += A[row * N + i] * B[i * N + col];
}
// storing results back
C[row * N + col] = tmp;
}
}
// We will check whether our results are reight or not
/* void verify_result(int *A, int *B, int *C, int N){
int tmp;
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
tmp = 0;
for(int k = 0; k < N; k++){
tmp += A[i * N + k] * B[k * N + j];
}
// use the assert for checking the final answer
assert(tmp == C[i * N + j]);
}
}
} */
int main(int argc, char **argv){
int N = atoi(argv[1]);
clock_t start, end; /* timing */
double elapsed;
int size = sizeof(double)*N*N ;
start = clock();
// memory allocation in host RAM
int *h_A, *h_B, *h_C;
cudaMallocHost((void **) &h_A, size);
cudaMallocHost((void **) &h_B, size);
cudaMallocHost((void **) &h_C, size);
for(int i = 0; i < N; ++i)
{for( int j = 0; j < N; ++j)
{ h_A[i*N+j] = (double)rand()/RAND_MAX*100;
h_B[i*N+j] = (double)rand()/RAND_MAX*100;
h_C[i*N+j] = 0;
}
}
int *dev_A, *dev_B, *dev_C;
cudaMalloc((void **) &dev_A, size);
cudaMalloc((void **) &dev_B, size);
cudaMalloc((void **) &dev_C, size);
// copy A and B from host to device
cudaMemcpy(dev_A, h_A, sizeof(int)*N*N, cudaMemcpyHostToDevice);
cudaMemcpy(dev_B, h_B, sizeof(int)*N*N, cudaMemcpyHostToDevice);
// Set our CTA and Grid dimensions
int threads = 16;
int blocks = (N + threads - 1) / threads;
// Setup our kernel launch parameters
dim3 THREADS(threads, threads);
dim3 BLOCKS(blocks, blocks);
// Launch our kernel
matrixMult<<<BLOCKS, THREADS>>>(dev_A, dev_B, dev_C, N);
cudaMemcpy(h_C, dev_C, size, cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
end = clock();
elapsed = ((double) (end - start)) / CLOCKS_PER_SEC;
printf(" \n Time taken for size %d is %f \n",N,elapsed);
// Verify the result
// verify_result(h_A, h_B, h_C, N);
// printf("All Results are correct");
// Free allocated memory
cudaFree(h_A);
cudaFree(h_B);
cudaFree(h_C);
cudaFree(dev_A);
cudaFree(dev_B);
cudaFree(dev_C);
return 0;
} | code for sm_80
Function : _Z10matrixMultPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0030*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */
/* 0x000fe200078e02ff */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xbf0 ; /* 0x00000af000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0110*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0130*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fd20000000f00 */
/*0150*/ @!P0 BRA 0xaf0 ; /* 0x0000099000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0180*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0190*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe40000000f00 */
/*01a0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fcc0003f04270 */
/*01b0*/ IMAD.WIDE R24, R0, R25, c[0x0][0x168] ; /* 0x00005a0000187625 */
/* 0x000fce00078e0219 */
/*01c0*/ @!P0 BRA 0x960 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01f0*/ @!P1 BRA 0x6a0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0220*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0230*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0240*/ IMAD.WIDE R12, R3, 0x4, R12 ; /* 0x00000004030c7825 */
/* 0x000fca00078e020c */
/*0250*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0260*/ IMAD.WIDE R10, R2, 0x4, R24 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0218 */
/*0270*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0280*/ IMAD.WIDE R18, R2.reuse, 0x4, R10 ; /* 0x0000000402127825 */
/* 0x040fe200078e020a */
/*0290*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*02a0*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*02b0*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */
/* 0x000fc600078e0212 */
/*02c0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02d0*/ IMAD.WIDE R20, R2.reuse, 0x4, R14 ; /* 0x0000000402147825 */
/* 0x040fe200078e020e */
/*02e0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*02f0*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*0300*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*0310*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */
/* 0x001fc600078e0214 */
/*0320*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0330*/ IMAD.WIDE R22, R2.reuse, 0x4, R14 ; /* 0x0000000402167825 */
/* 0x040fe200078e020e */
/*0340*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0350*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0360*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc600078e0216 */
/*0370*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0380*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*0390*/ IMAD R29, R29, R27, R28 ; /* 0x0000001b1d1d7224 */
/* 0x004fc600078e021c */
/*03a0*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*03b0*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*03c0*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fc800078e0218 */
/*03d0*/ IMAD R29, R16, R17, R29 ; /* 0x00000011101d7224 */
/* 0x008fe400078e021d */
/*03e0*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fe400078e020e */
/*03f0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*0400*/ IMAD R29, R18, R19, R29 ; /* 0x00000013121d7224 */
/* 0x010fe400078e021d */
/*0410*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fe400078e0210 */
/*0420*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0430*/ IMAD R26, R26, R7, R29 ; /* 0x000000071a1a7224 */
/* 0x000fc400078e021d */
/*0440*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */
/* 0x042fe200078e0212 */
/*0450*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0460*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0470*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x001fc600078e0216 */
/*0480*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*0490*/ IMAD R9, R20, R9, R26 ; /* 0x0000000914097224 */
/* 0x020fc600078e021a */
/*04a0*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*04b0*/ IMAD R11, R8, R11, R9 ; /* 0x0000000b080b7224 */
/* 0x000fe400078e0209 */
/*04c0*/ IMAD.WIDE R8, R2, 0x4, R24 ; /* 0x0000000402087825 */
/* 0x000fe200078e0218 */
/*04d0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04e0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*04f0*/ IMAD R21, R10, R21, R11 ; /* 0x000000150a157224 */
/* 0x000fc600078e020b */
/*0500*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*0510*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0208 */
/*0520*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0530*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0540*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0550*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0560*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0570*/ IMAD R9, R28, R27, R21 ; /* 0x0000001b1c097224 */
/* 0x004fc600078e0215 */
/*0580*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0590*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fca00078e020a */
/*05a0*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*05b0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05c0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05d0*/ IMAD R7, R14, R7, R9 ; /* 0x000000070e077224 */
/* 0x000fc800078e0209 */
/*05e0*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x000fc800078e0207 */
/*05f0*/ IMAD R7, R18, R26, R7 ; /* 0x0000001a12077224 */
/* 0x020fc800078e0207 */
/*0600*/ IMAD R7, R22, R17, R7 ; /* 0x0000001116077224 */
/* 0x010fe200078e0207 */
/*0610*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0620*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0630*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0640*/ IMAD R7, R15, R24, R7 ; /* 0x000000180f077224 */
/* 0x008fc800078e0207 */
/*0650*/ IMAD R28, R19, R28, R7 ; /* 0x0000001c131c7224 */
/* 0x004fc800078e0207 */
/*0660*/ IMAD R28, R23, R25, R28 ; /* 0x00000019171c7224 */
/* 0x000fe400078e021c */
/*0670*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */
/* 0x000fc800078e0214 */
/*0680*/ IMAD R28, R27, R8, R28 ; /* 0x000000081b1c7224 */
/* 0x000fe200078e021c */
/*0690*/ @P1 BRA 0x210 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06a0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*06b0*/ @!P1 BRA 0x940 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06c0*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fe200078e0218 */
/*06d0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06e0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*06f0*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*0700*/ IMAD.WIDE R12, R2.reuse, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x040fe200078e0210 */
/*0710*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*0720*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fe200078e0208 */
/*0730*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0740*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*0750*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0760*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0770*/ IMAD.WIDE R10, R2, 0x4, R14 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020e */
/*0780*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*0790*/ IMAD.WIDE R16, R2.reuse, 0x4, R10 ; /* 0x0000000402107825 */
/* 0x042fe200078e020a */
/*07a0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07b0*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*07c0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fc600078e0210 */
/*07d0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07e0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*07f0*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0212 */
/*0800*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*0810*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0830*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0840*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0850*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0860*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0870*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0880*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*0890*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*08a0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08b0*/ IMAD R7, R7, R20, R28 ; /* 0x0000001407077224 */
/* 0x004fc800078e021c */
/*08c0*/ IMAD R7, R21, R22, R7 ; /* 0x0000001615077224 */
/* 0x008fc800078e0207 */
/*08d0*/ IMAD R7, R23, R26, R7 ; /* 0x0000001a17077224 */
/* 0x020fc800078e0207 */
/*08e0*/ IMAD R7, R14, R27, R7 ; /* 0x0000001b0e077224 */
/* 0x000fc800078e0207 */
/*08f0*/ IMAD R7, R10, R25, R7 ; /* 0x000000190a077224 */
/* 0x000fc800078e0207 */
/*0900*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x010fc800078e0207 */
/*0910*/ IMAD R7, R24, R11, R7 ; /* 0x0000000b18077224 */
/* 0x000fe400078e0207 */
/*0920*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */
/* 0x000fc800078e020c */
/*0930*/ IMAD R28, R15, R18, R7 ; /* 0x000000120f1c7224 */
/* 0x000fe400078e0207 */
/*0940*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0950*/ @!P0 BRA 0xaf0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0960*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0970*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0218 */
/*0980*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0990*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fc800078e0208 */
/*09b0*/ IMAD.WIDE R12, R2.reuse, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x040fe200078e020e */
/*09c0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09d0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09e0*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020c */
/*09f0*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*0a00*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*0a10*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a30*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a40*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a50*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a60*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a70*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a80*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a90*/ IMAD R7, R25, R7, R28 ; /* 0x0000000719077224 */
/* 0x004fc800078e021c */
/*0aa0*/ IMAD R7, R14, R16, R7 ; /* 0x000000100e077224 */
/* 0x008fe400078e0207 */
/*0ab0*/ IMAD.WIDE R24, R2, 0x4, R10 ; /* 0x0000000402187825 */
/* 0x000fc800078e020a */
/*0ac0*/ IMAD R7, R18, R17, R7 ; /* 0x0000001112077224 */
/* 0x010fc800078e0207 */
/*0ad0*/ IMAD R28, R20, R19, R7 ; /* 0x00000013141c7224 */
/* 0x020fe200078e0207 */
/*0ae0*/ @P0 BRA 0x960 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0af0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b00*/ @!P0 BRA 0xbf0 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0b10*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b20*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x000fe20007ffe0ff */
/*0b30*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x000fd000078e0200 */
/*0b40*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b50*/ IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fca00078e0209 */
/*0b60*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a8000c1e1900 */
/*0b70*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002a2000c1e1900 */
/*0b80*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0b90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0ba0*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0bb0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0bc0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0bd0*/ IMAD R28, R11, R4, R28 ; /* 0x000000040b1c7224 */
/* 0x004fcc00078e021c */
/*0be0*/ @P0 BRA 0xb60 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0bf0*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c00*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fca0000000f00 */
/*0c10*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c20*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c40*/ BRA 0xc40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
#include <assert.h>
__global__ void matrixMult(int *A, int *B, int *C, int N){
// Calculate the global row and column for each thread
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if(row < N && col < N){
// def temprary variable for storing sum
int tmp = 0;
for(int i = 0; i < N; i++){
tmp += A[row * N + i] * B[i * N + col];
}
// storing results back
C[row * N + col] = tmp;
}
}
// We will check whether our results are reight or not
/* void verify_result(int *A, int *B, int *C, int N){
int tmp;
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
tmp = 0;
for(int k = 0; k < N; k++){
tmp += A[i * N + k] * B[k * N + j];
}
// use the assert for checking the final answer
assert(tmp == C[i * N + j]);
}
}
} */
int main(int argc, char **argv){
int N = atoi(argv[1]);
clock_t start, end; /* timing */
double elapsed;
int size = sizeof(double)*N*N ;
start = clock();
// memory allocation in host RAM
int *h_A, *h_B, *h_C;
cudaMallocHost((void **) &h_A, size);
cudaMallocHost((void **) &h_B, size);
cudaMallocHost((void **) &h_C, size);
for(int i = 0; i < N; ++i)
{for( int j = 0; j < N; ++j)
{ h_A[i*N+j] = (double)rand()/RAND_MAX*100;
h_B[i*N+j] = (double)rand()/RAND_MAX*100;
h_C[i*N+j] = 0;
}
}
int *dev_A, *dev_B, *dev_C;
cudaMalloc((void **) &dev_A, size);
cudaMalloc((void **) &dev_B, size);
cudaMalloc((void **) &dev_C, size);
// copy A and B from host to device
cudaMemcpy(dev_A, h_A, sizeof(int)*N*N, cudaMemcpyHostToDevice);
cudaMemcpy(dev_B, h_B, sizeof(int)*N*N, cudaMemcpyHostToDevice);
// Set our CTA and Grid dimensions
int threads = 16;
int blocks = (N + threads - 1) / threads;
// Setup our kernel launch parameters
dim3 THREADS(threads, threads);
dim3 BLOCKS(blocks, blocks);
// Launch our kernel
matrixMult<<<BLOCKS, THREADS>>>(dev_A, dev_B, dev_C, N);
cudaMemcpy(h_C, dev_C, size, cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
end = clock();
elapsed = ((double) (end - start)) / CLOCKS_PER_SEC;
printf(" \n Time taken for size %d is %f \n",N,elapsed);
// Verify the result
// verify_result(h_A, h_B, h_C, N);
// printf("All Results are correct");
// Free allocated memory
cudaFree(h_A);
cudaFree(h_B);
cudaFree(h_C);
cudaFree(dev_A);
cudaFree(dev_B);
cudaFree(dev_C);
return 0;
} | .file "tmpxft_00102f2a_00000000-6_cuda_c.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i
.type _Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i, @function
_Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10matrixMultPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i, .-_Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i
.globl _Z10matrixMultPiS_S_i
.type _Z10matrixMultPiS_S_i, @function
_Z10matrixMultPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10matrixMultPiS_S_i, .-_Z10matrixMultPiS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string " \n Time taken for size %d is %f \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movq %rax, 24(%rsp)
movl %eax, %r14d
movslq %eax, %rbp
movq %rbp, 8(%rsp)
call clock@PLT
movq %rax, 16(%rsp)
movl %ebp, %eax
imull %ebp, %eax
sall $3, %eax
movslq %eax, %r15
movq %r15, (%rsp)
leaq 32(%rsp), %rdi
movq %r15, %rsi
call cudaMallocHost@PLT
leaq 40(%rsp), %rdi
movq %r15, %rsi
call cudaMallocHost@PLT
leaq 48(%rsp), %rdi
movq %r15, %rsi
call cudaMallocHost@PLT
testl %ebx, %ebx
jle .L12
leaq 0(,%rbp,4), %r15
leal -1(%rbx), %r13d
leaq 4(,%r13,4), %rbp
movl $0, %r12d
notq %r13
salq $2, %r13
.L13:
leaq 0(%r13,%rbp), %rbx
.L14:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC0(%rip), %xmm0
mulsd .LC1(%rip), %xmm0
cvttsd2sil %xmm0, %edx
movq 32(%rsp), %rax
movl %edx, (%rax,%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC0(%rip), %xmm0
mulsd .LC1(%rip), %xmm0
cvttsd2sil %xmm0, %edx
movq 40(%rsp), %rax
movl %edx, (%rax,%rbx)
movq 48(%rsp), %rax
movl $0, (%rax,%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L14
addl $1, %r12d
addq %r15, %rbp
cmpl %r14d, %r12d
jne .L13
.L12:
leaq 56(%rsp), %rdi
movq (%rsp), %rbx
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq 8(%rsp), %rbx
imulq %rbx, %rbx
salq $2, %rbx
movl $1, %ecx
movq %rbx, %rdx
movq 32(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 80(%rsp)
movl $16, 84(%rsp)
movq 24(%rsp), %rax
leal 30(%rax), %edx
addl $15, %eax
cmovs %edx, %eax
sarl $4, %eax
movl %eax, 92(%rsp)
movl %eax, 96(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 92(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movl $2, %ecx
movq (%rsp), %rdx
movq 72(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
call clock@PLT
movq 16(%rsp), %rcx
subq %rcx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC2(%rip), %xmm0
movl %r14d, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl %r14d, %ecx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "_Z10matrixMultPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z10matrixMultPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -4194304
.long 1105199103
.align 8
.LC1:
.long 0
.long 1079574528
.align 8
.LC2:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
#include <assert.h>
__global__ void matrixMult(int *A, int *B, int *C, int N){
// Calculate the global row and column for each thread
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if(row < N && col < N){
// def temprary variable for storing sum
int tmp = 0;
for(int i = 0; i < N; i++){
tmp += A[row * N + i] * B[i * N + col];
}
// storing results back
C[row * N + col] = tmp;
}
}
// We will check whether our results are reight or not
/* void verify_result(int *A, int *B, int *C, int N){
int tmp;
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
tmp = 0;
for(int k = 0; k < N; k++){
tmp += A[i * N + k] * B[k * N + j];
}
// use the assert for checking the final answer
assert(tmp == C[i * N + j]);
}
}
} */
int main(int argc, char **argv){
int N = atoi(argv[1]);
clock_t start, end; /* timing */
double elapsed;
int size = sizeof(double)*N*N ;
start = clock();
// memory allocation in host RAM
int *h_A, *h_B, *h_C;
cudaMallocHost((void **) &h_A, size);
cudaMallocHost((void **) &h_B, size);
cudaMallocHost((void **) &h_C, size);
for(int i = 0; i < N; ++i)
{for( int j = 0; j < N; ++j)
{ h_A[i*N+j] = (double)rand()/RAND_MAX*100;
h_B[i*N+j] = (double)rand()/RAND_MAX*100;
h_C[i*N+j] = 0;
}
}
int *dev_A, *dev_B, *dev_C;
cudaMalloc((void **) &dev_A, size);
cudaMalloc((void **) &dev_B, size);
cudaMalloc((void **) &dev_C, size);
// copy A and B from host to device
cudaMemcpy(dev_A, h_A, sizeof(int)*N*N, cudaMemcpyHostToDevice);
cudaMemcpy(dev_B, h_B, sizeof(int)*N*N, cudaMemcpyHostToDevice);
// Set our CTA and Grid dimensions
int threads = 16;
int blocks = (N + threads - 1) / threads;
// Setup our kernel launch parameters
dim3 THREADS(threads, threads);
dim3 BLOCKS(blocks, blocks);
// Launch our kernel
matrixMult<<<BLOCKS, THREADS>>>(dev_A, dev_B, dev_C, N);
cudaMemcpy(h_C, dev_C, size, cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
end = clock();
elapsed = ((double) (end - start)) / CLOCKS_PER_SEC;
printf(" \n Time taken for size %d is %f \n",N,elapsed);
// Verify the result
// verify_result(h_A, h_B, h_C, N);
// printf("All Results are correct");
// Free allocated memory
cudaFree(h_A);
cudaFree(h_B);
cudaFree(h_C);
cudaFree(dev_A);
cudaFree(dev_B);
cudaFree(dev_C);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
#include <assert.h>
__global__ void matrixMult(int *A, int *B, int *C, int N){
// Calculate the global row and column for each thread
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if(row < N && col < N){
// def temprary variable for storing sum
int tmp = 0;
for(int i = 0; i < N; i++){
tmp += A[row * N + i] * B[i * N + col];
}
// storing results back
C[row * N + col] = tmp;
}
}
// We will check whether our results are reight or not
/* void verify_result(int *A, int *B, int *C, int N){
int tmp;
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
tmp = 0;
for(int k = 0; k < N; k++){
tmp += A[i * N + k] * B[k * N + j];
}
// use the assert for checking the final answer
assert(tmp == C[i * N + j]);
}
}
} */
int main(int argc, char **argv){
int N = atoi(argv[1]);
clock_t start, end; /* timing */
double elapsed;
int size = sizeof(double)*N*N ;
start = clock();
// memory allocation in host RAM
int *h_A, *h_B, *h_C;
hipHostMalloc((void **) &h_A, size, hipHostMallocDefault);
hipHostMalloc((void **) &h_B, size, hipHostMallocDefault);
hipHostMalloc((void **) &h_C, size, hipHostMallocDefault);
for(int i = 0; i < N; ++i)
{for( int j = 0; j < N; ++j)
{ h_A[i*N+j] = (double)rand()/RAND_MAX*100;
h_B[i*N+j] = (double)rand()/RAND_MAX*100;
h_C[i*N+j] = 0;
}
}
int *dev_A, *dev_B, *dev_C;
hipMalloc((void **) &dev_A, size);
hipMalloc((void **) &dev_B, size);
hipMalloc((void **) &dev_C, size);
// copy A and B from host to device
hipMemcpy(dev_A, h_A, sizeof(int)*N*N, hipMemcpyHostToDevice);
hipMemcpy(dev_B, h_B, sizeof(int)*N*N, hipMemcpyHostToDevice);
// Set our CTA and Grid dimensions
int threads = 16;
int blocks = (N + threads - 1) / threads;
// Setup our kernel launch parameters
dim3 THREADS(threads, threads);
dim3 BLOCKS(blocks, blocks);
// Launch our kernel
matrixMult<<<BLOCKS, THREADS>>>(dev_A, dev_B, dev_C, N);
hipMemcpy(h_C, dev_C, size, hipMemcpyDeviceToHost);
hipDeviceSynchronize();
end = clock();
elapsed = ((double) (end - start)) / CLOCKS_PER_SEC;
printf(" \n Time taken for size %d is %f \n",N,elapsed);
// Verify the result
// verify_result(h_A, h_B, h_C, N);
// printf("All Results are correct");
// Free allocated memory
hipFree(h_A);
hipFree(h_B);
hipFree(h_C);
hipFree(dev_A);
hipFree(dev_B);
hipFree(dev_C);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
#include <assert.h>
__global__ void matrixMult(int *A, int *B, int *C, int N){
// Calculate the global row and column for each thread
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if(row < N && col < N){
// def temprary variable for storing sum
int tmp = 0;
for(int i = 0; i < N; i++){
tmp += A[row * N + i] * B[i * N + col];
}
// storing results back
C[row * N + col] = tmp;
}
}
// We will check whether our results are reight or not
/* void verify_result(int *A, int *B, int *C, int N){
int tmp;
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
tmp = 0;
for(int k = 0; k < N; k++){
tmp += A[i * N + k] * B[k * N + j];
}
// use the assert for checking the final answer
assert(tmp == C[i * N + j]);
}
}
} */
int main(int argc, char **argv){
int N = atoi(argv[1]);
clock_t start, end; /* timing */
double elapsed;
int size = sizeof(double)*N*N ;
start = clock();
// memory allocation in host RAM
int *h_A, *h_B, *h_C;
hipHostMalloc((void **) &h_A, size, hipHostMallocDefault);
hipHostMalloc((void **) &h_B, size, hipHostMallocDefault);
hipHostMalloc((void **) &h_C, size, hipHostMallocDefault);
for(int i = 0; i < N; ++i)
{for( int j = 0; j < N; ++j)
{ h_A[i*N+j] = (double)rand()/RAND_MAX*100;
h_B[i*N+j] = (double)rand()/RAND_MAX*100;
h_C[i*N+j] = 0;
}
}
int *dev_A, *dev_B, *dev_C;
hipMalloc((void **) &dev_A, size);
hipMalloc((void **) &dev_B, size);
hipMalloc((void **) &dev_C, size);
// copy A and B from host to device
hipMemcpy(dev_A, h_A, sizeof(int)*N*N, hipMemcpyHostToDevice);
hipMemcpy(dev_B, h_B, sizeof(int)*N*N, hipMemcpyHostToDevice);
// Set our CTA and Grid dimensions
int threads = 16;
int blocks = (N + threads - 1) / threads;
// Setup our kernel launch parameters
dim3 THREADS(threads, threads);
dim3 BLOCKS(blocks, blocks);
// Launch our kernel
matrixMult<<<BLOCKS, THREADS>>>(dev_A, dev_B, dev_C, N);
hipMemcpy(h_C, dev_C, size, hipMemcpyDeviceToHost);
hipDeviceSynchronize();
end = clock();
elapsed = ((double) (end - start)) / CLOCKS_PER_SEC;
printf(" \n Time taken for size %d is %f \n",N,elapsed);
// Verify the result
// verify_result(h_A, h_B, h_C, N);
// printf("All Results are correct");
// Free allocated memory
hipFree(h_A);
hipFree(h_B);
hipFree(h_C);
hipFree(dev_A);
hipFree(dev_B);
hipFree(dev_C);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10matrixMultPiS_S_i
.globl _Z10matrixMultPiS_S_i
.p2align 8
.type _Z10matrixMultPiS_S_i,@function
_Z10matrixMultPiS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
s_mov_b32 s3, s2
v_mov_b32_e32 v5, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v6, 31, v5
s_add_i32 s3, s3, -1
s_cmp_eq_u32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_load_b32 v8, v[3:4], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[6:7], null, v9, v8, v[2:3]
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_dual_mov_b32 v2, v6 :: v_dual_add_nc_u32 v5, s2, v5
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10matrixMultPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10matrixMultPiS_S_i, .Lfunc_end0-_Z10matrixMultPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10matrixMultPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10matrixMultPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
#include <assert.h>
__global__ void matrixMult(int *A, int *B, int *C, int N){
// Calculate the global row and column for each thread
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if(row < N && col < N){
// def temprary variable for storing sum
int tmp = 0;
for(int i = 0; i < N; i++){
tmp += A[row * N + i] * B[i * N + col];
}
// storing results back
C[row * N + col] = tmp;
}
}
// We will check whether our results are reight or not
/* void verify_result(int *A, int *B, int *C, int N){
int tmp;
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
tmp = 0;
for(int k = 0; k < N; k++){
tmp += A[i * N + k] * B[k * N + j];
}
// use the assert for checking the final answer
assert(tmp == C[i * N + j]);
}
}
} */
int main(int argc, char **argv){
int N = atoi(argv[1]);
clock_t start, end; /* timing */
double elapsed;
int size = sizeof(double)*N*N ;
start = clock();
// memory allocation in host RAM
int *h_A, *h_B, *h_C;
hipHostMalloc((void **) &h_A, size, hipHostMallocDefault);
hipHostMalloc((void **) &h_B, size, hipHostMallocDefault);
hipHostMalloc((void **) &h_C, size, hipHostMallocDefault);
for(int i = 0; i < N; ++i)
{for( int j = 0; j < N; ++j)
{ h_A[i*N+j] = (double)rand()/RAND_MAX*100;
h_B[i*N+j] = (double)rand()/RAND_MAX*100;
h_C[i*N+j] = 0;
}
}
int *dev_A, *dev_B, *dev_C;
hipMalloc((void **) &dev_A, size);
hipMalloc((void **) &dev_B, size);
hipMalloc((void **) &dev_C, size);
// copy A and B from host to device
hipMemcpy(dev_A, h_A, sizeof(int)*N*N, hipMemcpyHostToDevice);
hipMemcpy(dev_B, h_B, sizeof(int)*N*N, hipMemcpyHostToDevice);
// Set our CTA and Grid dimensions
int threads = 16;
int blocks = (N + threads - 1) / threads;
// Setup our kernel launch parameters
dim3 THREADS(threads, threads);
dim3 BLOCKS(blocks, blocks);
// Launch our kernel
matrixMult<<<BLOCKS, THREADS>>>(dev_A, dev_B, dev_C, N);
hipMemcpy(h_C, dev_C, size, hipMemcpyDeviceToHost);
hipDeviceSynchronize();
end = clock();
elapsed = ((double) (end - start)) / CLOCKS_PER_SEC;
printf(" \n Time taken for size %d is %f \n",N,elapsed);
// Verify the result
// verify_result(h_A, h_B, h_C, N);
// printf("All Results are correct");
// Free allocated memory
hipFree(h_A);
hipFree(h_B);
hipFree(h_C);
hipFree(dev_A);
hipFree(dev_B);
hipFree(dev_C);
return 0;
} | .text
.file "cuda_c.hip"
.globl _Z25__device_stub__matrixMultPiS_S_i # -- Begin function _Z25__device_stub__matrixMultPiS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__matrixMultPiS_S_i,@function
_Z25__device_stub__matrixMultPiS_S_i: # @_Z25__device_stub__matrixMultPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10matrixMultPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__matrixMultPiS_S_i, .Lfunc_end0-_Z25__device_stub__matrixMultPiS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x41dfffffffc00000 # double 2147483647
.LCPI1_1:
.quad 0x4059000000000000 # double 100
.LCPI1_2:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq 8(%rsi), %rdi
xorl %r13d, %r13d
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
shlq $32, %rax
movq %rax, 56(%rsp) # 8-byte Spill
movslq %ebx, %r15
movl %r15d, %ebp
imull %r15d, %ebp
shll $3, %ebp
callq clock
movq %rax, 80(%rsp) # 8-byte Spill
movslq %ebp, %r14
leaq 40(%rsp), %rdi
movq %r14, %rsi
xorl %edx, %edx
callq hipHostMalloc
leaq 32(%rsp), %rdi
movq %r14, %rsi
xorl %edx, %edx
callq hipHostMalloc
leaq 24(%rsp), %rdi
movq %r14, 72(%rsp) # 8-byte Spill
movq %r14, %rsi
xorl %edx, %edx
callq hipHostMalloc
movq %r15, 64(%rsp) # 8-byte Spill
testl %r15d, %r15d
jle .LBB1_5
# %bb.1: # %.preheader.lr.ph
movl %ebx, %r12d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
movl %r13d, %r13d
movq %r12, %r14
movq %r13, %rbp
.p2align 4, 0x90
.LBB1_3: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
mulsd .LCPI1_1(%rip), %xmm0
cvttsd2si %xmm0, %eax
movq 40(%rsp), %rcx
movl %eax, (%rcx,%rbp,4)
callq rand
movsd .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd %xmm1, %xmm0
movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
cvttsd2si %xmm0, %eax
movq 32(%rsp), %rcx
movl %eax, (%rcx,%rbp,4)
movq 24(%rsp), %rax
movl $0, (%rax,%rbp,4)
incq %rbp
decq %r14
jne .LBB1_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %r15
addl %ebx, %r13d
cmpq %r12, %r15
jne .LBB1_2
.LBB1_5: # %._crit_edge53
leaq 16(%rsp), %rdi
movq 72(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq 40(%rsp), %rsi
movq 56(%rsp), %r12 # 8-byte Reload
sarq $30, %r12
movq 64(%rsp), %r15 # 8-byte Reload
imulq %r15, %r12
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq 32(%rsp), %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
leal 15(%r15), %eax
addl $30, %r15d
testl %eax, %eax
cmovnsl %eax, %r15d
sarl $4, %r15d
movq %r15, %rdi
shlq $32, %rdi
orq %r15, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
movl %ebx, 52(%rsp)
leaq 152(%rsp), %rax
movq %rax, 160(%rsp)
leaq 144(%rsp), %rax
movq %rax, 168(%rsp)
leaq 136(%rsp), %rax
movq %rax, 176(%rsp)
leaq 52(%rsp), %rax
movq %rax, 184(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z10matrixMultPiS_S_i, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_7:
movq 24(%rsp), %rdi
movq (%rsp), %rsi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
callq clock
subq 80(%rsp), %rax # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI1_2(%rip), %xmm0
movl $.L.str, %edi
movl %ebx, %esi
movb $1, %al
callq printf
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10matrixMultPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10matrixMultPiS_S_i,@object # @_Z10matrixMultPiS_S_i
.section .rodata,"a",@progbits
.globl _Z10matrixMultPiS_S_i
.p2align 3, 0x0
_Z10matrixMultPiS_S_i:
.quad _Z25__device_stub__matrixMultPiS_S_i
.size _Z10matrixMultPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " \n Time taken for size %d is %f \n"
.size .L.str, 34
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10matrixMultPiS_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__matrixMultPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10matrixMultPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10matrixMultPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0030*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */
/* 0x000fe200078e02ff */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xbf0 ; /* 0x00000af000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0110*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0130*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fd20000000f00 */
/*0150*/ @!P0 BRA 0xaf0 ; /* 0x0000099000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0180*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0190*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe40000000f00 */
/*01a0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fcc0003f04270 */
/*01b0*/ IMAD.WIDE R24, R0, R25, c[0x0][0x168] ; /* 0x00005a0000187625 */
/* 0x000fce00078e0219 */
/*01c0*/ @!P0 BRA 0x960 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01f0*/ @!P1 BRA 0x6a0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0220*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0230*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0240*/ IMAD.WIDE R12, R3, 0x4, R12 ; /* 0x00000004030c7825 */
/* 0x000fca00078e020c */
/*0250*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0260*/ IMAD.WIDE R10, R2, 0x4, R24 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0218 */
/*0270*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0280*/ IMAD.WIDE R18, R2.reuse, 0x4, R10 ; /* 0x0000000402127825 */
/* 0x040fe200078e020a */
/*0290*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*02a0*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*02b0*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */
/* 0x000fc600078e0212 */
/*02c0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02d0*/ IMAD.WIDE R20, R2.reuse, 0x4, R14 ; /* 0x0000000402147825 */
/* 0x040fe200078e020e */
/*02e0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*02f0*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*0300*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*0310*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */
/* 0x001fc600078e0214 */
/*0320*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0330*/ IMAD.WIDE R22, R2.reuse, 0x4, R14 ; /* 0x0000000402167825 */
/* 0x040fe200078e020e */
/*0340*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0350*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0360*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc600078e0216 */
/*0370*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0380*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*0390*/ IMAD R29, R29, R27, R28 ; /* 0x0000001b1d1d7224 */
/* 0x004fc600078e021c */
/*03a0*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*03b0*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*03c0*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fc800078e0218 */
/*03d0*/ IMAD R29, R16, R17, R29 ; /* 0x00000011101d7224 */
/* 0x008fe400078e021d */
/*03e0*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fe400078e020e */
/*03f0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*0400*/ IMAD R29, R18, R19, R29 ; /* 0x00000013121d7224 */
/* 0x010fe400078e021d */
/*0410*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fe400078e0210 */
/*0420*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0430*/ IMAD R26, R26, R7, R29 ; /* 0x000000071a1a7224 */
/* 0x000fc400078e021d */
/*0440*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */
/* 0x042fe200078e0212 */
/*0450*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0460*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0470*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x001fc600078e0216 */
/*0480*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*0490*/ IMAD R9, R20, R9, R26 ; /* 0x0000000914097224 */
/* 0x020fc600078e021a */
/*04a0*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*04b0*/ IMAD R11, R8, R11, R9 ; /* 0x0000000b080b7224 */
/* 0x000fe400078e0209 */
/*04c0*/ IMAD.WIDE R8, R2, 0x4, R24 ; /* 0x0000000402087825 */
/* 0x000fe200078e0218 */
/*04d0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04e0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*04f0*/ IMAD R21, R10, R21, R11 ; /* 0x000000150a157224 */
/* 0x000fc600078e020b */
/*0500*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*0510*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0208 */
/*0520*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0530*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0540*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0550*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0560*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0570*/ IMAD R9, R28, R27, R21 ; /* 0x0000001b1c097224 */
/* 0x004fc600078e0215 */
/*0580*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0590*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fca00078e020a */
/*05a0*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*05b0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05c0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05d0*/ IMAD R7, R14, R7, R9 ; /* 0x000000070e077224 */
/* 0x000fc800078e0209 */
/*05e0*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x000fc800078e0207 */
/*05f0*/ IMAD R7, R18, R26, R7 ; /* 0x0000001a12077224 */
/* 0x020fc800078e0207 */
/*0600*/ IMAD R7, R22, R17, R7 ; /* 0x0000001116077224 */
/* 0x010fe200078e0207 */
/*0610*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0620*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0630*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0640*/ IMAD R7, R15, R24, R7 ; /* 0x000000180f077224 */
/* 0x008fc800078e0207 */
/*0650*/ IMAD R28, R19, R28, R7 ; /* 0x0000001c131c7224 */
/* 0x004fc800078e0207 */
/*0660*/ IMAD R28, R23, R25, R28 ; /* 0x00000019171c7224 */
/* 0x000fe400078e021c */
/*0670*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */
/* 0x000fc800078e0214 */
/*0680*/ IMAD R28, R27, R8, R28 ; /* 0x000000081b1c7224 */
/* 0x000fe200078e021c */
/*0690*/ @P1 BRA 0x210 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06a0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*06b0*/ @!P1 BRA 0x940 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06c0*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fe200078e0218 */
/*06d0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06e0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*06f0*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*0700*/ IMAD.WIDE R12, R2.reuse, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x040fe200078e0210 */
/*0710*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*0720*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fe200078e0208 */
/*0730*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0740*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*0750*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0760*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0770*/ IMAD.WIDE R10, R2, 0x4, R14 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020e */
/*0780*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*0790*/ IMAD.WIDE R16, R2.reuse, 0x4, R10 ; /* 0x0000000402107825 */
/* 0x042fe200078e020a */
/*07a0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07b0*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*07c0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fc600078e0210 */
/*07d0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07e0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*07f0*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0212 */
/*0800*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*0810*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0830*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0840*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0850*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0860*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0870*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0880*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*0890*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*08a0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08b0*/ IMAD R7, R7, R20, R28 ; /* 0x0000001407077224 */
/* 0x004fc800078e021c */
/*08c0*/ IMAD R7, R21, R22, R7 ; /* 0x0000001615077224 */
/* 0x008fc800078e0207 */
/*08d0*/ IMAD R7, R23, R26, R7 ; /* 0x0000001a17077224 */
/* 0x020fc800078e0207 */
/*08e0*/ IMAD R7, R14, R27, R7 ; /* 0x0000001b0e077224 */
/* 0x000fc800078e0207 */
/*08f0*/ IMAD R7, R10, R25, R7 ; /* 0x000000190a077224 */
/* 0x000fc800078e0207 */
/*0900*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x010fc800078e0207 */
/*0910*/ IMAD R7, R24, R11, R7 ; /* 0x0000000b18077224 */
/* 0x000fe400078e0207 */
/*0920*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */
/* 0x000fc800078e020c */
/*0930*/ IMAD R28, R15, R18, R7 ; /* 0x000000120f1c7224 */
/* 0x000fe400078e0207 */
/*0940*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0950*/ @!P0 BRA 0xaf0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0960*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0970*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0218 */
/*0980*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0990*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fc800078e0208 */
/*09b0*/ IMAD.WIDE R12, R2.reuse, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x040fe200078e020e */
/*09c0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09d0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09e0*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020c */
/*09f0*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*0a00*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*0a10*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a30*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a40*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a50*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a60*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a70*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a80*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a90*/ IMAD R7, R25, R7, R28 ; /* 0x0000000719077224 */
/* 0x004fc800078e021c */
/*0aa0*/ IMAD R7, R14, R16, R7 ; /* 0x000000100e077224 */
/* 0x008fe400078e0207 */
/*0ab0*/ IMAD.WIDE R24, R2, 0x4, R10 ; /* 0x0000000402187825 */
/* 0x000fc800078e020a */
/*0ac0*/ IMAD R7, R18, R17, R7 ; /* 0x0000001112077224 */
/* 0x010fc800078e0207 */
/*0ad0*/ IMAD R28, R20, R19, R7 ; /* 0x00000013141c7224 */
/* 0x020fe200078e0207 */
/*0ae0*/ @P0 BRA 0x960 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0af0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b00*/ @!P0 BRA 0xbf0 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0b10*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b20*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x000fe20007ffe0ff */
/*0b30*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x000fd000078e0200 */
/*0b40*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b50*/ IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fca00078e0209 */
/*0b60*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a8000c1e1900 */
/*0b70*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002a2000c1e1900 */
/*0b80*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0b90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0ba0*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0bb0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0bc0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0bd0*/ IMAD R28, R11, R4, R28 ; /* 0x000000040b1c7224 */
/* 0x004fcc00078e021c */
/*0be0*/ @P0 BRA 0xb60 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0bf0*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c00*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fca0000000f00 */
/*0c10*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c20*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c40*/ BRA 0xc40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10matrixMultPiS_S_i
.globl _Z10matrixMultPiS_S_i
.p2align 8
.type _Z10matrixMultPiS_S_i,@function
_Z10matrixMultPiS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
s_mov_b32 s3, s2
v_mov_b32_e32 v5, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v6, 31, v5
s_add_i32 s3, s3, -1
s_cmp_eq_u32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_load_b32 v8, v[3:4], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[6:7], null, v9, v8, v[2:3]
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_dual_mov_b32 v2, v6 :: v_dual_add_nc_u32 v5, s2, v5
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10matrixMultPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10matrixMultPiS_S_i, .Lfunc_end0-_Z10matrixMultPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10matrixMultPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10matrixMultPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00102f2a_00000000-6_cuda_c.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i
.type _Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i, @function
_Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10matrixMultPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i, .-_Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i
.globl _Z10matrixMultPiS_S_i
.type _Z10matrixMultPiS_S_i, @function
_Z10matrixMultPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10matrixMultPiS_S_i, .-_Z10matrixMultPiS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string " \n Time taken for size %d is %f \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movq %rax, 24(%rsp)
movl %eax, %r14d
movslq %eax, %rbp
movq %rbp, 8(%rsp)
call clock@PLT
movq %rax, 16(%rsp)
movl %ebp, %eax
imull %ebp, %eax
sall $3, %eax
movslq %eax, %r15
movq %r15, (%rsp)
leaq 32(%rsp), %rdi
movq %r15, %rsi
call cudaMallocHost@PLT
leaq 40(%rsp), %rdi
movq %r15, %rsi
call cudaMallocHost@PLT
leaq 48(%rsp), %rdi
movq %r15, %rsi
call cudaMallocHost@PLT
testl %ebx, %ebx
jle .L12
leaq 0(,%rbp,4), %r15
leal -1(%rbx), %r13d
leaq 4(,%r13,4), %rbp
movl $0, %r12d
notq %r13
salq $2, %r13
.L13:
leaq 0(%r13,%rbp), %rbx
.L14:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC0(%rip), %xmm0
mulsd .LC1(%rip), %xmm0
cvttsd2sil %xmm0, %edx
movq 32(%rsp), %rax
movl %edx, (%rax,%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC0(%rip), %xmm0
mulsd .LC1(%rip), %xmm0
cvttsd2sil %xmm0, %edx
movq 40(%rsp), %rax
movl %edx, (%rax,%rbx)
movq 48(%rsp), %rax
movl $0, (%rax,%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L14
addl $1, %r12d
addq %r15, %rbp
cmpl %r14d, %r12d
jne .L13
.L12:
leaq 56(%rsp), %rdi
movq (%rsp), %rbx
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq 8(%rsp), %rbx
imulq %rbx, %rbx
salq $2, %rbx
movl $1, %ecx
movq %rbx, %rdx
movq 32(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 80(%rsp)
movl $16, 84(%rsp)
movq 24(%rsp), %rax
leal 30(%rax), %edx
addl $15, %eax
cmovs %edx, %eax
sarl $4, %eax
movl %eax, 92(%rsp)
movl %eax, 96(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 92(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movl $2, %ecx
movq (%rsp), %rdx
movq 72(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
call clock@PLT
movq 16(%rsp), %rcx
subq %rcx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC2(%rip), %xmm0
movl %r14d, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl %r14d, %ecx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "_Z10matrixMultPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z10matrixMultPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -4194304
.long 1105199103
.align 8
.LC1:
.long 0
.long 1079574528
.align 8
.LC2:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_c.hip"
.globl _Z25__device_stub__matrixMultPiS_S_i # -- Begin function _Z25__device_stub__matrixMultPiS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__matrixMultPiS_S_i,@function
_Z25__device_stub__matrixMultPiS_S_i: # @_Z25__device_stub__matrixMultPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10matrixMultPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__matrixMultPiS_S_i, .Lfunc_end0-_Z25__device_stub__matrixMultPiS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x41dfffffffc00000 # double 2147483647
.LCPI1_1:
.quad 0x4059000000000000 # double 100
.LCPI1_2:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq 8(%rsi), %rdi
xorl %r13d, %r13d
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
shlq $32, %rax
movq %rax, 56(%rsp) # 8-byte Spill
movslq %ebx, %r15
movl %r15d, %ebp
imull %r15d, %ebp
shll $3, %ebp
callq clock
movq %rax, 80(%rsp) # 8-byte Spill
movslq %ebp, %r14
leaq 40(%rsp), %rdi
movq %r14, %rsi
xorl %edx, %edx
callq hipHostMalloc
leaq 32(%rsp), %rdi
movq %r14, %rsi
xorl %edx, %edx
callq hipHostMalloc
leaq 24(%rsp), %rdi
movq %r14, 72(%rsp) # 8-byte Spill
movq %r14, %rsi
xorl %edx, %edx
callq hipHostMalloc
movq %r15, 64(%rsp) # 8-byte Spill
testl %r15d, %r15d
jle .LBB1_5
# %bb.1: # %.preheader.lr.ph
movl %ebx, %r12d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
movl %r13d, %r13d
movq %r12, %r14
movq %r13, %rbp
.p2align 4, 0x90
.LBB1_3: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
mulsd .LCPI1_1(%rip), %xmm0
cvttsd2si %xmm0, %eax
movq 40(%rsp), %rcx
movl %eax, (%rcx,%rbp,4)
callq rand
movsd .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd %xmm1, %xmm0
movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
cvttsd2si %xmm0, %eax
movq 32(%rsp), %rcx
movl %eax, (%rcx,%rbp,4)
movq 24(%rsp), %rax
movl $0, (%rax,%rbp,4)
incq %rbp
decq %r14
jne .LBB1_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %r15
addl %ebx, %r13d
cmpq %r12, %r15
jne .LBB1_2
.LBB1_5: # %._crit_edge53
leaq 16(%rsp), %rdi
movq 72(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq 40(%rsp), %rsi
movq 56(%rsp), %r12 # 8-byte Reload
sarq $30, %r12
movq 64(%rsp), %r15 # 8-byte Reload
imulq %r15, %r12
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq 32(%rsp), %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
leal 15(%r15), %eax
addl $30, %r15d
testl %eax, %eax
cmovnsl %eax, %r15d
sarl $4, %r15d
movq %r15, %rdi
shlq $32, %rdi
orq %r15, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
movl %ebx, 52(%rsp)
leaq 152(%rsp), %rax
movq %rax, 160(%rsp)
leaq 144(%rsp), %rax
movq %rax, 168(%rsp)
leaq 136(%rsp), %rax
movq %rax, 176(%rsp)
leaq 52(%rsp), %rax
movq %rax, 184(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z10matrixMultPiS_S_i, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_7:
movq 24(%rsp), %rdi
movq (%rsp), %rsi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
callq clock
subq 80(%rsp), %rax # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI1_2(%rip), %xmm0
movl $.L.str, %edi
movl %ebx, %esi
movb $1, %al
callq printf
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10matrixMultPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10matrixMultPiS_S_i,@object # @_Z10matrixMultPiS_S_i
.section .rodata,"a",@progbits
.globl _Z10matrixMultPiS_S_i
.p2align 3, 0x0
_Z10matrixMultPiS_S_i:
.quad _Z25__device_stub__matrixMultPiS_S_i
.size _Z10matrixMultPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " \n Time taken for size %d is %f \n"
.size .L.str, 34
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10matrixMultPiS_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__matrixMultPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10matrixMultPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__global__ void add(int* d_a, int* d_b, int* d_c){
int tid = threadIdx.x + blockIdx.x*blockDim.x;
if(tid < 2000){
d_c[tid] = d_a[tid] + d_b[tid];
}
}
int main(int argc, char* argv[]){
cudaSetDevice(1);
return 0;
} | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GT.AND P0, PT, R6, 0x7cf, PT ; /* 0x000007cf0600780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__ void add(int* d_a, int* d_b, int* d_c){
int tid = threadIdx.x + blockIdx.x*blockDim.x;
if(tid < 2000){
d_c[tid] = d_a[tid] + d_b[tid];
}
}
int main(int argc, char* argv[]){
cudaSetDevice(1);
return 0;
} | .file "tmpxft_0002d498_00000000-6_vector_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $1, %edi
call cudaSetDevice@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size main, .-main
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__ void add(int* d_a, int* d_b, int* d_c){
int tid = threadIdx.x + blockIdx.x*blockDim.x;
if(tid < 2000){
d_c[tid] = d_a[tid] + d_b[tid];
}
}
int main(int argc, char* argv[]){
cudaSetDevice(1);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void add(int* d_a, int* d_b, int* d_c){
int tid = threadIdx.x + blockIdx.x*blockDim.x;
if(tid < 2000){
d_c[tid] = d_a[tid] + d_b[tid];
}
}
int main(int argc, char* argv[]){
hipSetDevice(1);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void add(int* d_a, int* d_b, int* d_c){
int tid = threadIdx.x + blockIdx.x*blockDim.x;
if(tid < 2000){
d_c[tid] = d_a[tid] + d_b[tid];
}
}
int main(int argc, char* argv[]){
hipSetDevice(1);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x7d0, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void add(int* d_a, int* d_b, int* d_c){
int tid = threadIdx.x + blockIdx.x*blockDim.x;
if(tid < 2000){
d_c[tid] = d_a[tid] + d_b[tid];
}
}
int main(int argc, char* argv[]){
hipSetDevice(1);
return 0;
} | .text
.file "vector_add.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $1, %edi
callq hipSetDevice
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GT.AND P0, PT, R6, 0x7cf, PT ; /* 0x000007cf0600780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x7d0, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0002d498_00000000-6_vector_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $1, %edi
call cudaSetDevice@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size main, .-main
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vector_add.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $1, %edi
callq hipSetDevice
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#include <sys/resource.h>
//134217728
double dwalltime(){
double sec;
struct timeval tv;
gettimeofday(&tv,NULL);
sec = tv.tv_sec + tv.tv_usec/1000000.0;
return sec;
}
__global__ void sumM_kernel_cuda(double *d_matA,double *d_matB, unsigned long n){
unsigned long int global_id = blockIdx.x * blockDim.x + threadIdx.x;
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
}
void checkparams(unsigned long *n, unsigned int *cb);
int main(int argc, char *argv[]){
if (argc != 2){
printf("Falta argumento: N\n");
return 0;
}
unsigned long N = atoi (argv[1]),tam_tot = N*N;
unsigned int CUDA_BLK = 16;
unsigned long numBytes = sizeof(double)*tam_tot;
checkparams(&tam_tot,&CUDA_BLK);
double *matA,*matB,*d_matA,*d_matB,timetick;
unsigned int i,j;
matA = (double *)malloc(numBytes);
matB = (double *)malloc(numBytes);
for (i = 0; i < tam_tot; i++){
matA[i] = i;
matB[i] = i;
}
cudaMalloc((void **) &d_matA, numBytes);
cudaMalloc((void **) &d_matB, numBytes);
cudaMemcpy(d_matA, matA, numBytes, cudaMemcpyHostToDevice); // CPU -> GPU
cudaMemcpy(d_matB, matB, numBytes, cudaMemcpyHostToDevice); // CPU -> GPU
// Bloque unidimensional de hilos (*cb* hilos)
dim3 dimBlock(CUDA_BLK);
// Grid unidimensional (*ceil(n/cb)* bloques)
dim3 dimGrid((tam_tot + dimBlock.x - 1) / dimBlock.x);
timetick = dwalltime();
sumM_kernel_cuda<<<dimGrid, dimBlock>>>(d_matA, d_matB, tam_tot);
cudaThreadSynchronize();
printf("Tiempo para sumar las matrices: %f\n",dwalltime() - timetick);
cudaMemcpy(matA, d_matA, numBytes, cudaMemcpyDeviceToHost); // GPU -> CPU
/* for(i = 0; i < N; i++){
for(j = 0; j < N; j++){
printf("%f|",matA[i*N+j]);
}
printf("\n");
}
printf("\n");*/
cudaFree(d_matA);
cudaFree(d_matB);
free(matA);
free(matB);
return 0;
}
void checkparams(unsigned long *n, unsigned int *cb){
struct cudaDeviceProp capabilities;
// Si menos numero total de hilos que tamaño bloque, reducimos bloque
if (*cb > *n)
*cb = *n;
cudaGetDeviceProperties (&capabilities, 0);
if (*cb > capabilities.maxThreadsDim[0]) {
*cb = capabilities.maxThreadsDim[0];
printf("->Núm. hilos/bloq cambiado a %d (máx por bloque para dev)\n\n",
*cb);
}
if (((*n + *cb - 1) / *cb) > capabilities.maxGridSize[0]) {
*cb = 2 * (*n - 1) / (capabilities.maxGridSize[0] - 1);
if (*cb > capabilities.maxThreadsDim[0]) {
*cb = capabilities.maxThreadsDim[0];
printf("->Núm. hilos/bloq cambiado a %d (máx por bloque para dev)\n",
*cb);
if (*n > (capabilities.maxGridSize[0] * *cb)) {
*n = capabilities.maxGridSize[0] * *cb;
printf("->Núm. total de hilos cambiado a %lu (máx por grid para \
dev)\n\n", *n);
} else {
printf("\n");
}
} else {
printf("->Núm. hilos/bloq cambiado a %d (%d máx. bloq/grid para \
dev)\n\n",
*cb, capabilities.maxGridSize[0]);
}
}
} | code for sm_80
Function : _Z16sumM_kernel_cudaPdS_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x174], PT, P0 ; /* 0x00005d00ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.SHL.U32 R4, R0, 0x8, RZ ; /* 0x0000000800047824 */
/* 0x000fe200078e00ff */
/*0080*/ SHF.R.U32.HI R0, RZ, 0x1d, R0 ; /* 0x0000001dff007819 */
/* 0x000fe20000011600 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ IADD3 R2, P0, R4.reuse, c[0x0][0x160], RZ ; /* 0x0000580004027a10 */
/* 0x040fe40007f1e0ff */
/*00b0*/ IADD3 R4, P1, R4, c[0x0][0x168], RZ ; /* 0x00005a0004047a10 */
/* 0x000fe40007f3e0ff */
/*00c0*/ IADD3.X R3, R0.reuse, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590000037a10 */
/* 0x040fe400007fe4ff */
/*00d0*/ IADD3.X R5, R0, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0000057a10 */
/* 0x000fc60000ffe4ff */
/*00e0*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea8000c1e1b00 */
/*00f0*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1b00 */
/*0100*/ DADD R6, R6, R8 ; /* 0x0000000006067229 */
/* 0x004e0e0000000008 */
/*0110*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x0011e8000c101b04 */
/*0120*/ LDG.E.64 R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea4000c1e1b00 */
/*0130*/ DADD R8, R6, R8 ; /* 0x0000000006087229 */
/* 0x004e4e0000000008 */
/*0140*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0023e8000c101b04 */
/*0150*/ LDG.E.64 R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea4000c1e1b00 */
/*0160*/ DADD R10, R8, R10 ; /* 0x00000000080a7229 */
/* 0x004e8e000000000a */
/*0170*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0045e8000c101b04 */
/*0180*/ LDG.E.64 R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ee4000c1e1b00 */
/*0190*/ DADD R12, R10, R12 ; /* 0x000000000a0c7229 */
/* 0x008ece000000000c */
/*01a0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0087e8000c101b04 */
/*01b0*/ LDG.E.64 R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000f24000c1e1b00 */
/*01c0*/ DADD R14, R12, R14 ; /* 0x000000000c0e7229 */
/* 0x010f0e000000000e */
/*01d0*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0109e8000c101b04 */
/*01e0*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x001f64000c1e1b00 */
/*01f0*/ DADD R6, R14, R6 ; /* 0x000000000e067229 */
/* 0x020e0e0000000006 */
/*0200*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x0011e8000c101b04 */
/*0210*/ LDG.E.64 R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x002f64000c1e1b00 */
/*0220*/ DADD R8, R6, R8 ; /* 0x0000000006087229 */
/* 0x020e4e0000000008 */
/*0230*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0023e8000c101b04 */
/*0240*/ LDG.E.64 R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x004ea4000c1e1b00 */
/*0250*/ DADD R10, R8, R10 ; /* 0x00000000080a7229 */
/* 0x004e8e000000000a */
/*0260*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0045e8000c101b04 */
/*0270*/ LDG.E.64 R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x008ee4000c1e1b00 */
/*0280*/ DADD R12, R10, R12 ; /* 0x000000000a0c7229 */
/* 0x008ece000000000c */
/*0290*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0087e8000c101b04 */
/*02a0*/ LDG.E.64 R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x010f24000c1e1b00 */
/*02b0*/ DADD R14, R12, R14 ; /* 0x000000000c0e7229 */
/* 0x010f0e000000000e */
/*02c0*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0109e8000c101b04 */
/*02d0*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x001f64000c1e1b00 */
/*02e0*/ DADD R6, R14, R6 ; /* 0x000000000e067229 */
/* 0x020e0e0000000006 */
/*02f0*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x0011e8000c101b04 */
/*0300*/ LDG.E.64 R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x002f64000c1e1b00 */
/*0310*/ DADD R8, R6, R8 ; /* 0x0000000006087229 */
/* 0x020e4e0000000008 */
/*0320*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x002fe8000c101b04 */
/*0330*/ LDG.E.64 R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x004ea4000c1e1b00 */
/*0340*/ DADD R10, R8, R10 ; /* 0x00000000080a7229 */
/* 0x004e4e000000000a */
/*0350*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x002fe8000c101b04 */
/*0360*/ LDG.E.64 R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x008ea4000c1e1b00 */
/*0370*/ DADD R12, R10, R12 ; /* 0x000000000a0c7229 */
/* 0x004e4e000000000c */
/*0380*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x002fe8000c101b04 */
/*0390*/ LDG.E.64 R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x010ea4000c1e1b00 */
/*03a0*/ DADD R14, R12, R14 ; /* 0x000000000c0e7229 */
/* 0x004e4e000000000e */
/*03b0*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x002fe8000c101b04 */
/*03c0*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x001ea4000c1e1b00 */
/*03d0*/ DADD R6, R14, R6 ; /* 0x000000000e067229 */
/* 0x004e0e0000000006 */
/*03e0*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x001fe2000c101b04 */
/*03f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0400*/ BRA 0x400; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#include <sys/resource.h>
//134217728
double dwalltime(){
double sec;
struct timeval tv;
gettimeofday(&tv,NULL);
sec = tv.tv_sec + tv.tv_usec/1000000.0;
return sec;
}
__global__ void sumM_kernel_cuda(double *d_matA,double *d_matB, unsigned long n){
unsigned long int global_id = blockIdx.x * blockDim.x + threadIdx.x;
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
}
void checkparams(unsigned long *n, unsigned int *cb);
int main(int argc, char *argv[]){
if (argc != 2){
printf("Falta argumento: N\n");
return 0;
}
unsigned long N = atoi (argv[1]),tam_tot = N*N;
unsigned int CUDA_BLK = 16;
unsigned long numBytes = sizeof(double)*tam_tot;
checkparams(&tam_tot,&CUDA_BLK);
double *matA,*matB,*d_matA,*d_matB,timetick;
unsigned int i,j;
matA = (double *)malloc(numBytes);
matB = (double *)malloc(numBytes);
for (i = 0; i < tam_tot; i++){
matA[i] = i;
matB[i] = i;
}
cudaMalloc((void **) &d_matA, numBytes);
cudaMalloc((void **) &d_matB, numBytes);
cudaMemcpy(d_matA, matA, numBytes, cudaMemcpyHostToDevice); // CPU -> GPU
cudaMemcpy(d_matB, matB, numBytes, cudaMemcpyHostToDevice); // CPU -> GPU
// Bloque unidimensional de hilos (*cb* hilos)
dim3 dimBlock(CUDA_BLK);
// Grid unidimensional (*ceil(n/cb)* bloques)
dim3 dimGrid((tam_tot + dimBlock.x - 1) / dimBlock.x);
timetick = dwalltime();
sumM_kernel_cuda<<<dimGrid, dimBlock>>>(d_matA, d_matB, tam_tot);
cudaThreadSynchronize();
printf("Tiempo para sumar las matrices: %f\n",dwalltime() - timetick);
cudaMemcpy(matA, d_matA, numBytes, cudaMemcpyDeviceToHost); // GPU -> CPU
/* for(i = 0; i < N; i++){
for(j = 0; j < N; j++){
printf("%f|",matA[i*N+j]);
}
printf("\n");
}
printf("\n");*/
cudaFree(d_matA);
cudaFree(d_matB);
free(matA);
free(matB);
return 0;
}
void checkparams(unsigned long *n, unsigned int *cb){
struct cudaDeviceProp capabilities;
// Si menos numero total de hilos que tamaño bloque, reducimos bloque
if (*cb > *n)
*cb = *n;
cudaGetDeviceProperties (&capabilities, 0);
if (*cb > capabilities.maxThreadsDim[0]) {
*cb = capabilities.maxThreadsDim[0];
printf("->Núm. hilos/bloq cambiado a %d (máx por bloque para dev)\n\n",
*cb);
}
if (((*n + *cb - 1) / *cb) > capabilities.maxGridSize[0]) {
*cb = 2 * (*n - 1) / (capabilities.maxGridSize[0] - 1);
if (*cb > capabilities.maxThreadsDim[0]) {
*cb = capabilities.maxThreadsDim[0];
printf("->Núm. hilos/bloq cambiado a %d (máx por bloque para dev)\n",
*cb);
if (*n > (capabilities.maxGridSize[0] * *cb)) {
*n = capabilities.maxGridSize[0] * *cb;
printf("->Núm. total de hilos cambiado a %lu (máx por grid para \
dev)\n\n", *n);
} else {
printf("\n");
}
} else {
printf("->Núm. hilos/bloq cambiado a %d (%d máx. bloq/grid para \
dev)\n\n",
*cb, capabilities.maxGridSize[0]);
}
}
} | .file "tmpxft_0011e2a6_00000000-6_sumMatrixGPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9dwalltimev
.type _Z9dwalltimev, @function
_Z9dwalltimev:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
divsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z9dwalltimev, .-_Z9dwalltimev
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "->N\303\272m. hilos/bloq cambiado a %d (m\303\241x por bloque para dev)\n\n"
.align 8
.LC2:
.string "->N\303\272m. hilos/bloq cambiado a %d (m\303\241x por bloque para dev)\n"
.align 8
.LC3:
.string "->N\303\272m. total de hilos cambiado a %lu (m\303\241x por grid para dev)\n\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "\n"
.section .rodata.str1.8
.align 8
.LC5:
.string "->N\303\272m. hilos/bloq cambiado a %d (%d m\303\241x. bloq/grid para dev)\n\n"
.text
.globl _Z11checkparamsPmPj
.type _Z11checkparamsPmPj, @function
_Z11checkparamsPmPj:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $1048, %rsp
.cfi_def_cfa_offset 1072
movq %rdi, %rbp
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 1032(%rsp)
xorl %eax, %eax
movq (%rdi), %rax
movl (%rsi), %edx
cmpq %rdx, %rax
jnb .L8
movl %eax, (%rsi)
.L8:
movq %rsp, %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
movl 324(%rsp), %edx
cmpl (%rbx), %edx
jb .L15
.L9:
movl (%rbx), %esi
movq 0(%rbp), %rax
leaq -1(%rax), %rcx
movl 336(%rsp), %edi
leaq (%rsi,%rcx), %rax
movl $0, %edx
divq %rsi
movslq %edi, %rdx
cmpq %rax, %rdx
jnb .L7
leaq (%rcx,%rcx), %rax
leal -1(%rdi), %ecx
movslq %ecx, %rcx
movl $0, %edx
divq %rcx
movl %eax, (%rbx)
movl 324(%rsp), %edx
cmpl %eax, %edx
jnb .L11
movl %edx, (%rbx)
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
imull (%rbx), %edx
cmpq 0(%rbp), %rdx
jnb .L12
movq %rdx, 0(%rbp)
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L7
.L15:
movl %edx, (%rbx)
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L9
.L12:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L7
.L11:
movl %edi, %ecx
movl %eax, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L7:
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $1048, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z11checkparamsPmPj, .-_Z11checkparamsPmPj
.globl _Z39__device_stub__Z16sumM_kernel_cudaPdS_mPdS_m
.type _Z39__device_stub__Z16sumM_kernel_cudaPdS_mPdS_m, @function
_Z39__device_stub__Z16sumM_kernel_cudaPdS_mPdS_m:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16sumM_kernel_cudaPdS_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z39__device_stub__Z16sumM_kernel_cudaPdS_mPdS_m, .-_Z39__device_stub__Z16sumM_kernel_cudaPdS_mPdS_m
.globl _Z16sumM_kernel_cudaPdS_m
.type _Z16sumM_kernel_cudaPdS_m, @function
_Z16sumM_kernel_cudaPdS_m:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z16sumM_kernel_cudaPdS_mPdS_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z16sumM_kernel_cudaPdS_m, .-_Z16sumM_kernel_cudaPdS_m
.section .rodata.str1.1
.LC6:
.string "Falta argumento: N\n"
.section .rodata.str1.8
.align 8
.LC7:
.string "Tiempo para sumar las matrices: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
cmpl $2, %edi
je .L26
leaq .LC6(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
.L27:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L36
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movslq %eax, %rbx
imulq %rbx, %rbx
movq %rbx, 24(%rsp)
movl $16, 20(%rsp)
salq $3, %rbx
leaq 20(%rsp), %rsi
leaq 24(%rsp), %rdi
call _Z11checkparamsPmPj
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movq 24(%rsp), %r13
testq %r13, %r13
je .L28
movl $0, %edx
movl $0, %eax
.L31:
movl %edx, %ecx
pxor %xmm0, %xmm0
cvtsi2sdq %rcx, %xmm0
movsd %xmm0, 0(%rbp,%rax,8)
movsd %xmm0, (%r12,%rax,8)
addl $1, %edx
movl %edx, %eax
cmpq %r13, %rax
jb .L31
.L28:
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl 20(%rsp), %r14d
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl %r14d, %ecx
leaq -1(%rcx,%r13), %rax
movl $0, %edx
divq %rcx
movl %eax, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
call _Z9dwalltimev
movsd %xmm0, 8(%rsp)
movl %r14d, 48(%rsp)
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L32:
call cudaThreadSynchronize@PLT
call _Z9dwalltimev
subsd 8(%rsp), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 32(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
jmp .L27
.L37:
movq %r13, %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z39__device_stub__Z16sumM_kernel_cudaPdS_mPdS_m
jmp .L32
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z16sumM_kernel_cudaPdS_m"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z16sumM_kernel_cudaPdS_m(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#include <sys/resource.h>
//134217728
double dwalltime(){
double sec;
struct timeval tv;
gettimeofday(&tv,NULL);
sec = tv.tv_sec + tv.tv_usec/1000000.0;
return sec;
}
__global__ void sumM_kernel_cuda(double *d_matA,double *d_matB, unsigned long n){
unsigned long int global_id = blockIdx.x * blockDim.x + threadIdx.x;
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
}
void checkparams(unsigned long *n, unsigned int *cb);
int main(int argc, char *argv[]){
if (argc != 2){
printf("Falta argumento: N\n");
return 0;
}
unsigned long N = atoi (argv[1]),tam_tot = N*N;
unsigned int CUDA_BLK = 16;
unsigned long numBytes = sizeof(double)*tam_tot;
checkparams(&tam_tot,&CUDA_BLK);
double *matA,*matB,*d_matA,*d_matB,timetick;
unsigned int i,j;
matA = (double *)malloc(numBytes);
matB = (double *)malloc(numBytes);
for (i = 0; i < tam_tot; i++){
matA[i] = i;
matB[i] = i;
}
cudaMalloc((void **) &d_matA, numBytes);
cudaMalloc((void **) &d_matB, numBytes);
cudaMemcpy(d_matA, matA, numBytes, cudaMemcpyHostToDevice); // CPU -> GPU
cudaMemcpy(d_matB, matB, numBytes, cudaMemcpyHostToDevice); // CPU -> GPU
// Bloque unidimensional de hilos (*cb* hilos)
dim3 dimBlock(CUDA_BLK);
// Grid unidimensional (*ceil(n/cb)* bloques)
dim3 dimGrid((tam_tot + dimBlock.x - 1) / dimBlock.x);
timetick = dwalltime();
sumM_kernel_cuda<<<dimGrid, dimBlock>>>(d_matA, d_matB, tam_tot);
cudaThreadSynchronize();
printf("Tiempo para sumar las matrices: %f\n",dwalltime() - timetick);
cudaMemcpy(matA, d_matA, numBytes, cudaMemcpyDeviceToHost); // GPU -> CPU
/* for(i = 0; i < N; i++){
for(j = 0; j < N; j++){
printf("%f|",matA[i*N+j]);
}
printf("\n");
}
printf("\n");*/
cudaFree(d_matA);
cudaFree(d_matB);
free(matA);
free(matB);
return 0;
}
void checkparams(unsigned long *n, unsigned int *cb){
struct cudaDeviceProp capabilities;
// Si menos numero total de hilos que tamaño bloque, reducimos bloque
if (*cb > *n)
*cb = *n;
cudaGetDeviceProperties (&capabilities, 0);
if (*cb > capabilities.maxThreadsDim[0]) {
*cb = capabilities.maxThreadsDim[0];
printf("->Núm. hilos/bloq cambiado a %d (máx por bloque para dev)\n\n",
*cb);
}
if (((*n + *cb - 1) / *cb) > capabilities.maxGridSize[0]) {
*cb = 2 * (*n - 1) / (capabilities.maxGridSize[0] - 1);
if (*cb > capabilities.maxThreadsDim[0]) {
*cb = capabilities.maxThreadsDim[0];
printf("->Núm. hilos/bloq cambiado a %d (máx por bloque para dev)\n",
*cb);
if (*n > (capabilities.maxGridSize[0] * *cb)) {
*n = capabilities.maxGridSize[0] * *cb;
printf("->Núm. total de hilos cambiado a %lu (máx por grid para \
dev)\n\n", *n);
} else {
printf("\n");
}
} else {
printf("->Núm. hilos/bloq cambiado a %d (%d máx. bloq/grid para \
dev)\n\n",
*cb, capabilities.maxGridSize[0]);
}
}
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#include <sys/resource.h>
//134217728
double dwalltime(){
double sec;
struct timeval tv;
gettimeofday(&tv,NULL);
sec = tv.tv_sec + tv.tv_usec/1000000.0;
return sec;
}
__global__ void sumM_kernel_cuda(double *d_matA,double *d_matB, unsigned long n){
unsigned long int global_id = blockIdx.x * blockDim.x + threadIdx.x;
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
}
void checkparams(unsigned long *n, unsigned int *cb);
int main(int argc, char *argv[]){
if (argc != 2){
printf("Falta argumento: N\n");
return 0;
}
unsigned long N = atoi (argv[1]),tam_tot = N*N;
unsigned int CUDA_BLK = 16;
unsigned long numBytes = sizeof(double)*tam_tot;
checkparams(&tam_tot,&CUDA_BLK);
double *matA,*matB,*d_matA,*d_matB,timetick;
unsigned int i,j;
matA = (double *)malloc(numBytes);
matB = (double *)malloc(numBytes);
for (i = 0; i < tam_tot; i++){
matA[i] = i;
matB[i] = i;
}
hipMalloc((void **) &d_matA, numBytes);
hipMalloc((void **) &d_matB, numBytes);
hipMemcpy(d_matA, matA, numBytes, hipMemcpyHostToDevice); // CPU -> GPU
hipMemcpy(d_matB, matB, numBytes, hipMemcpyHostToDevice); // CPU -> GPU
// Bloque unidimensional de hilos (*cb* hilos)
dim3 dimBlock(CUDA_BLK);
// Grid unidimensional (*ceil(n/cb)* bloques)
dim3 dimGrid((tam_tot + dimBlock.x - 1) / dimBlock.x);
timetick = dwalltime();
sumM_kernel_cuda<<<dimGrid, dimBlock>>>(d_matA, d_matB, tam_tot);
hipDeviceSynchronize();
printf("Tiempo para sumar las matrices: %f\n",dwalltime() - timetick);
hipMemcpy(matA, d_matA, numBytes, hipMemcpyDeviceToHost); // GPU -> CPU
/* for(i = 0; i < N; i++){
for(j = 0; j < N; j++){
printf("%f|",matA[i*N+j]);
}
printf("\n");
}
printf("\n");*/
hipFree(d_matA);
hipFree(d_matB);
free(matA);
free(matB);
return 0;
}
void checkparams(unsigned long *n, unsigned int *cb){
struct hipDeviceProp_t capabilities;
// Si menos numero total de hilos que tamaño bloque, reducimos bloque
if (*cb > *n)
*cb = *n;
hipGetDeviceProperties (&capabilities, 0);
if (*cb > capabilities.maxThreadsDim[0]) {
*cb = capabilities.maxThreadsDim[0];
printf("->Núm. hilos/bloq cambiado a %d (máx por bloque para dev)\n\n",
*cb);
}
if (((*n + *cb - 1) / *cb) > capabilities.maxGridSize[0]) {
*cb = 2 * (*n - 1) / (capabilities.maxGridSize[0] - 1);
if (*cb > capabilities.maxThreadsDim[0]) {
*cb = capabilities.maxThreadsDim[0];
printf("->Núm. hilos/bloq cambiado a %d (máx por bloque para dev)\n",
*cb);
if (*n > (capabilities.maxGridSize[0] * *cb)) {
*n = capabilities.maxGridSize[0] * *cb;
printf("->Núm. total de hilos cambiado a %lu (máx por grid para \
dev)\n\n", *n);
} else {
printf("\n");
}
} else {
printf("->Núm. hilos/bloq cambiado a %d (%d máx. bloq/grid para \
dev)\n\n",
*cb, capabilities.maxGridSize[0]);
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#include <sys/resource.h>
//134217728
double dwalltime(){
double sec;
struct timeval tv;
gettimeofday(&tv,NULL);
sec = tv.tv_sec + tv.tv_usec/1000000.0;
return sec;
}
__global__ void sumM_kernel_cuda(double *d_matA,double *d_matB, unsigned long n){
unsigned long int global_id = blockIdx.x * blockDim.x + threadIdx.x;
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
}
void checkparams(unsigned long *n, unsigned int *cb);
int main(int argc, char *argv[]){
if (argc != 2){
printf("Falta argumento: N\n");
return 0;
}
unsigned long N = atoi (argv[1]),tam_tot = N*N;
unsigned int CUDA_BLK = 16;
unsigned long numBytes = sizeof(double)*tam_tot;
checkparams(&tam_tot,&CUDA_BLK);
double *matA,*matB,*d_matA,*d_matB,timetick;
unsigned int i,j;
matA = (double *)malloc(numBytes);
matB = (double *)malloc(numBytes);
for (i = 0; i < tam_tot; i++){
matA[i] = i;
matB[i] = i;
}
hipMalloc((void **) &d_matA, numBytes);
hipMalloc((void **) &d_matB, numBytes);
hipMemcpy(d_matA, matA, numBytes, hipMemcpyHostToDevice); // CPU -> GPU
hipMemcpy(d_matB, matB, numBytes, hipMemcpyHostToDevice); // CPU -> GPU
// Bloque unidimensional de hilos (*cb* hilos)
dim3 dimBlock(CUDA_BLK);
// Grid unidimensional (*ceil(n/cb)* bloques)
dim3 dimGrid((tam_tot + dimBlock.x - 1) / dimBlock.x);
timetick = dwalltime();
sumM_kernel_cuda<<<dimGrid, dimBlock>>>(d_matA, d_matB, tam_tot);
hipDeviceSynchronize();
printf("Tiempo para sumar las matrices: %f\n",dwalltime() - timetick);
hipMemcpy(matA, d_matA, numBytes, hipMemcpyDeviceToHost); // GPU -> CPU
/* for(i = 0; i < N; i++){
for(j = 0; j < N; j++){
printf("%f|",matA[i*N+j]);
}
printf("\n");
}
printf("\n");*/
hipFree(d_matA);
hipFree(d_matB);
free(matA);
free(matB);
return 0;
}
void checkparams(unsigned long *n, unsigned int *cb){
struct hipDeviceProp_t capabilities;
// Si menos numero total de hilos que tamaño bloque, reducimos bloque
if (*cb > *n)
*cb = *n;
hipGetDeviceProperties (&capabilities, 0);
if (*cb > capabilities.maxThreadsDim[0]) {
*cb = capabilities.maxThreadsDim[0];
printf("->Núm. hilos/bloq cambiado a %d (máx por bloque para dev)\n\n",
*cb);
}
if (((*n + *cb - 1) / *cb) > capabilities.maxGridSize[0]) {
*cb = 2 * (*n - 1) / (capabilities.maxGridSize[0] - 1);
if (*cb > capabilities.maxThreadsDim[0]) {
*cb = capabilities.maxThreadsDim[0];
printf("->Núm. hilos/bloq cambiado a %d (máx por bloque para dev)\n",
*cb);
if (*n > (capabilities.maxGridSize[0] * *cb)) {
*n = capabilities.maxGridSize[0] * *cb;
printf("->Núm. total de hilos cambiado a %lu (máx por grid para \
dev)\n\n", *n);
} else {
printf("\n");
}
} else {
printf("->Núm. hilos/bloq cambiado a %d (%d máx. bloq/grid para \
dev)\n\n",
*cb, capabilities.maxGridSize[0]);
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16sumM_kernel_cudaPdS_m
.globl _Z16sumM_kernel_cudaPdS_m
.p2align 8
.type _Z16sumM_kernel_cudaPdS_m,@function
_Z16sumM_kernel_cudaPdS_m:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b64 v[4:5], v[2:3], off
global_load_b64 v[6:7], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], v[6:7]
global_store_b64 v[2:3], v[4:5], off
global_load_b64 v[6:7], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], v[6:7]
global_store_b64 v[2:3], v[4:5], off
global_load_b64 v[6:7], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], v[6:7]
global_store_b64 v[2:3], v[4:5], off
global_load_b64 v[6:7], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], v[6:7]
global_store_b64 v[2:3], v[4:5], off
global_load_b64 v[6:7], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], v[6:7]
global_store_b64 v[2:3], v[4:5], off
global_load_b64 v[6:7], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], v[6:7]
global_store_b64 v[2:3], v[4:5], off
global_load_b64 v[6:7], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], v[6:7]
global_store_b64 v[2:3], v[4:5], off
global_load_b64 v[6:7], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], v[6:7]
global_store_b64 v[2:3], v[4:5], off
global_load_b64 v[6:7], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], v[6:7]
global_store_b64 v[2:3], v[4:5], off
global_load_b64 v[6:7], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], v[6:7]
global_store_b64 v[2:3], v[4:5], off
global_load_b64 v[6:7], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], v[6:7]
global_store_b64 v[2:3], v[4:5], off
global_load_b64 v[6:7], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], v[6:7]
global_store_b64 v[2:3], v[4:5], off
global_load_b64 v[6:7], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], v[6:7]
global_store_b64 v[2:3], v[4:5], off
global_load_b64 v[6:7], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], v[6:7]
global_store_b64 v[2:3], v[4:5], off
global_load_b64 v[6:7], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], v[6:7]
global_store_b64 v[2:3], v[4:5], off
global_load_b64 v[0:1], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[0:1], v[4:5], v[0:1]
global_store_b64 v[2:3], v[0:1], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16sumM_kernel_cudaPdS_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16sumM_kernel_cudaPdS_m, .Lfunc_end0-_Z16sumM_kernel_cudaPdS_m
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16sumM_kernel_cudaPdS_m
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16sumM_kernel_cudaPdS_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#include <sys/resource.h>
//134217728
double dwalltime(){
double sec;
struct timeval tv;
gettimeofday(&tv,NULL);
sec = tv.tv_sec + tv.tv_usec/1000000.0;
return sec;
}
__global__ void sumM_kernel_cuda(double *d_matA,double *d_matB, unsigned long n){
unsigned long int global_id = blockIdx.x * blockDim.x + threadIdx.x;
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
if (global_id < n)
d_matA[global_id] = d_matA[global_id] + d_matB[global_id];
}
void checkparams(unsigned long *n, unsigned int *cb);
int main(int argc, char *argv[]){
if (argc != 2){
printf("Falta argumento: N\n");
return 0;
}
unsigned long N = atoi (argv[1]),tam_tot = N*N;
unsigned int CUDA_BLK = 16;
unsigned long numBytes = sizeof(double)*tam_tot;
checkparams(&tam_tot,&CUDA_BLK);
double *matA,*matB,*d_matA,*d_matB,timetick;
unsigned int i,j;
matA = (double *)malloc(numBytes);
matB = (double *)malloc(numBytes);
for (i = 0; i < tam_tot; i++){
matA[i] = i;
matB[i] = i;
}
hipMalloc((void **) &d_matA, numBytes);
hipMalloc((void **) &d_matB, numBytes);
hipMemcpy(d_matA, matA, numBytes, hipMemcpyHostToDevice); // CPU -> GPU
hipMemcpy(d_matB, matB, numBytes, hipMemcpyHostToDevice); // CPU -> GPU
// Bloque unidimensional de hilos (*cb* hilos)
dim3 dimBlock(CUDA_BLK);
// Grid unidimensional (*ceil(n/cb)* bloques)
dim3 dimGrid((tam_tot + dimBlock.x - 1) / dimBlock.x);
timetick = dwalltime();
sumM_kernel_cuda<<<dimGrid, dimBlock>>>(d_matA, d_matB, tam_tot);
hipDeviceSynchronize();
printf("Tiempo para sumar las matrices: %f\n",dwalltime() - timetick);
hipMemcpy(matA, d_matA, numBytes, hipMemcpyDeviceToHost); // GPU -> CPU
/* for(i = 0; i < N; i++){
for(j = 0; j < N; j++){
printf("%f|",matA[i*N+j]);
}
printf("\n");
}
printf("\n");*/
hipFree(d_matA);
hipFree(d_matB);
free(matA);
free(matB);
return 0;
}
void checkparams(unsigned long *n, unsigned int *cb){
struct hipDeviceProp_t capabilities;
// Si menos numero total de hilos que tamaño bloque, reducimos bloque
if (*cb > *n)
*cb = *n;
hipGetDeviceProperties (&capabilities, 0);
if (*cb > capabilities.maxThreadsDim[0]) {
*cb = capabilities.maxThreadsDim[0];
printf("->Núm. hilos/bloq cambiado a %d (máx por bloque para dev)\n\n",
*cb);
}
if (((*n + *cb - 1) / *cb) > capabilities.maxGridSize[0]) {
*cb = 2 * (*n - 1) / (capabilities.maxGridSize[0] - 1);
if (*cb > capabilities.maxThreadsDim[0]) {
*cb = capabilities.maxThreadsDim[0];
printf("->Núm. hilos/bloq cambiado a %d (máx por bloque para dev)\n",
*cb);
if (*n > (capabilities.maxGridSize[0] * *cb)) {
*n = capabilities.maxGridSize[0] * *cb;
printf("->Núm. total de hilos cambiado a %lu (máx por grid para \
dev)\n\n", *n);
} else {
printf("\n");
}
} else {
printf("->Núm. hilos/bloq cambiado a %d (%d máx. bloq/grid para \
dev)\n\n",
*cb, capabilities.maxGridSize[0]);
}
}
} | .text
.file "sumMatrixGPU.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z9dwalltimev
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z9dwalltimev
.p2align 4, 0x90
.type _Z9dwalltimev,@function
_Z9dwalltimev: # @_Z9dwalltimev
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm1
cvtsi2sdq 16(%rsp), %xmm0
divsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z9dwalltimev, .Lfunc_end0-_Z9dwalltimev
.cfi_endproc
# -- End function
.globl _Z31__device_stub__sumM_kernel_cudaPdS_m # -- Begin function _Z31__device_stub__sumM_kernel_cudaPdS_m
.p2align 4, 0x90
.type _Z31__device_stub__sumM_kernel_cudaPdS_m,@function
_Z31__device_stub__sumM_kernel_cudaPdS_m: # @_Z31__device_stub__sumM_kernel_cudaPdS_m
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16sumM_kernel_cudaPdS_m, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z31__device_stub__sumM_kernel_cudaPdS_m, .Lfunc_end1-_Z31__device_stub__sumM_kernel_cudaPdS_m
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB2_1
# %bb.2:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movslq %eax, %rbx
imulq %rbx, %rbx
movq %rbx, 64(%rsp)
movl $16, 12(%rsp)
shlq $3, %rbx
leaq 64(%rsp), %rdi
leaq 12(%rsp), %rsi
callq _Z11checkparamsPmPj
movq %rbx, %rdi
callq malloc
movq %rax, %r14
movq %rbx, %rdi
callq malloc
movq %rax, %r15
movq 64(%rsp), %rbp
testq %rbp, %rbp
je .LBB2_5
# %bb.3: # %.lr.ph.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %eax, %ecx
xorps %xmm0, %xmm0
cvtsi2sd %rcx, %xmm0
movsd %xmm0, (%r14,%rax,8)
movsd %xmm0, (%r15,%rax,8)
incq %rax
movl %eax, %ecx
cmpq %rcx, %rbp
ja .LBB2_4
.LBB2_5: # %._crit_edge
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq %r15, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movl 12(%rsp), %ecx
movabsq $4294967296, %rsi # imm = 0x100000000
leaq (%rcx,%rsi), %r12
leaq (%rcx,%rbp), %rax
decq %rax
xorl %edx, %edx
divq %rcx
movl %eax, %r13d
orq %rsi, %r13
leaq 32(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 32(%rsp), %xmm0
cvtsi2sdq 40(%rsp), %xmm1
divsd .LCPI2_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 72(%rsp) # 8-byte Spill
movq %r13, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_7
# %bb.6:
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movq %rbp, 128(%rsp)
leaq 144(%rsp), %rax
movq %rax, 32(%rsp)
leaq 136(%rsp), %rax
movq %rax, 40(%rsp)
leaq 128(%rsp), %rax
movq %rax, 48(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z16sumM_kernel_cudaPdS_m, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_7:
callq hipDeviceSynchronize
leaq 32(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq 32(%rsp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 40(%rsp), %xmm0
divsd .LCPI2_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd 72(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rsi
movq %r14, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
jmp .LBB2_8
.LBB2_1:
movl $.Lstr, %edi
callq puts@PLT
.LBB2_8:
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.globl _Z11checkparamsPmPj # -- Begin function _Z11checkparamsPmPj
.p2align 4, 0x90
.type _Z11checkparamsPmPj,@function
_Z11checkparamsPmPj: # @_Z11checkparamsPmPj
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %r14
movq %rdi, %rbx
movl (%rsi), %ecx
movq (%rdi), %rax
cmpq %rcx, %rax
jae .LBB3_2
# %bb.1:
movl %eax, (%r14)
.LBB3_2:
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl 332(%rsp), %esi
cmpl %esi, (%r14)
jbe .LBB3_4
# %bb.3:
movl %esi, (%r14)
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
.LBB3_4:
movq (%rbx), %rsi
movl (%r14), %ecx
leaq (%rsi,%rcx), %rax
decq %rax
xorl %edx, %edx
divq %rcx
movslq 344(%rsp), %rcx
cmpq %rcx, %rax
jbe .LBB3_10
# %bb.5:
leaq -2(,%rsi,2), %rax
leaq -1(%rcx), %rsi
xorl %edx, %edx
divq %rsi
movl %eax, (%r14)
movl 332(%rsp), %esi
cmpl %eax, %esi
jae .LBB3_9
# %bb.6:
movl %esi, (%r14)
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl (%r14), %esi
imull 344(%rsp), %esi
cmpq %rsi, (%rbx)
jbe .LBB3_8
# %bb.7:
movq %rsi, (%rbx)
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
jmp .LBB3_10
.LBB3_9:
movl $.L.str.6, %edi
movl %eax, %esi
movl %ecx, %edx
xorl %eax, %eax
callq printf
jmp .LBB3_10
.LBB3_8:
movl $10, %edi
callq putchar@PLT
.LBB3_10:
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z11checkparamsPmPj, .Lfunc_end3-_Z11checkparamsPmPj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16sumM_kernel_cudaPdS_m, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16sumM_kernel_cudaPdS_m,@object # @_Z16sumM_kernel_cudaPdS_m
.section .rodata,"a",@progbits
.globl _Z16sumM_kernel_cudaPdS_m
.p2align 3, 0x0
_Z16sumM_kernel_cudaPdS_m:
.quad _Z31__device_stub__sumM_kernel_cudaPdS_m
.size _Z16sumM_kernel_cudaPdS_m, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Tiempo para sumar las matrices: %f\n"
.size .L.str.1, 36
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "->N\303\272m. hilos/bloq cambiado a %d (m\303\241x por bloque para dev)\n\n"
.size .L.str.2, 62
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "->N\303\272m. hilos/bloq cambiado a %d (m\303\241x por bloque para dev)\n"
.size .L.str.3, 61
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "->N\303\272m. total de hilos cambiado a %lu (m\303\241x por grid para dev)\n\n"
.size .L.str.4, 65
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "->N\303\272m. hilos/bloq cambiado a %d (%d m\303\241x. bloq/grid para dev)\n\n"
.size .L.str.6, 65
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16sumM_kernel_cudaPdS_m"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Falta argumento: N"
.size .Lstr, 19
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__sumM_kernel_cudaPdS_m
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16sumM_kernel_cudaPdS_m
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16sumM_kernel_cudaPdS_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x174], PT, P0 ; /* 0x00005d00ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.SHL.U32 R4, R0, 0x8, RZ ; /* 0x0000000800047824 */
/* 0x000fe200078e00ff */
/*0080*/ SHF.R.U32.HI R0, RZ, 0x1d, R0 ; /* 0x0000001dff007819 */
/* 0x000fe20000011600 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ IADD3 R2, P0, R4.reuse, c[0x0][0x160], RZ ; /* 0x0000580004027a10 */
/* 0x040fe40007f1e0ff */
/*00b0*/ IADD3 R4, P1, R4, c[0x0][0x168], RZ ; /* 0x00005a0004047a10 */
/* 0x000fe40007f3e0ff */
/*00c0*/ IADD3.X R3, R0.reuse, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590000037a10 */
/* 0x040fe400007fe4ff */
/*00d0*/ IADD3.X R5, R0, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0000057a10 */
/* 0x000fc60000ffe4ff */
/*00e0*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea8000c1e1b00 */
/*00f0*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1b00 */
/*0100*/ DADD R6, R6, R8 ; /* 0x0000000006067229 */
/* 0x004e0e0000000008 */
/*0110*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x0011e8000c101b04 */
/*0120*/ LDG.E.64 R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea4000c1e1b00 */
/*0130*/ DADD R8, R6, R8 ; /* 0x0000000006087229 */
/* 0x004e4e0000000008 */
/*0140*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0023e8000c101b04 */
/*0150*/ LDG.E.64 R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea4000c1e1b00 */
/*0160*/ DADD R10, R8, R10 ; /* 0x00000000080a7229 */
/* 0x004e8e000000000a */
/*0170*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0045e8000c101b04 */
/*0180*/ LDG.E.64 R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ee4000c1e1b00 */
/*0190*/ DADD R12, R10, R12 ; /* 0x000000000a0c7229 */
/* 0x008ece000000000c */
/*01a0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0087e8000c101b04 */
/*01b0*/ LDG.E.64 R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000f24000c1e1b00 */
/*01c0*/ DADD R14, R12, R14 ; /* 0x000000000c0e7229 */
/* 0x010f0e000000000e */
/*01d0*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0109e8000c101b04 */
/*01e0*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x001f64000c1e1b00 */
/*01f0*/ DADD R6, R14, R6 ; /* 0x000000000e067229 */
/* 0x020e0e0000000006 */
/*0200*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x0011e8000c101b04 */
/*0210*/ LDG.E.64 R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x002f64000c1e1b00 */
/*0220*/ DADD R8, R6, R8 ; /* 0x0000000006087229 */
/* 0x020e4e0000000008 */
/*0230*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0023e8000c101b04 */
/*0240*/ LDG.E.64 R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x004ea4000c1e1b00 */
/*0250*/ DADD R10, R8, R10 ; /* 0x00000000080a7229 */
/* 0x004e8e000000000a */
/*0260*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0045e8000c101b04 */
/*0270*/ LDG.E.64 R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x008ee4000c1e1b00 */
/*0280*/ DADD R12, R10, R12 ; /* 0x000000000a0c7229 */
/* 0x008ece000000000c */
/*0290*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0087e8000c101b04 */
/*02a0*/ LDG.E.64 R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x010f24000c1e1b00 */
/*02b0*/ DADD R14, R12, R14 ; /* 0x000000000c0e7229 */
/* 0x010f0e000000000e */
/*02c0*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0109e8000c101b04 */
/*02d0*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x001f64000c1e1b00 */
/*02e0*/ DADD R6, R14, R6 ; /* 0x000000000e067229 */
/* 0x020e0e0000000006 */
/*02f0*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x0011e8000c101b04 */
/*0300*/ LDG.E.64 R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x002f64000c1e1b00 */
/*0310*/ DADD R8, R6, R8 ; /* 0x0000000006087229 */
/* 0x020e4e0000000008 */
/*0320*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x002fe8000c101b04 */
/*0330*/ LDG.E.64 R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x004ea4000c1e1b00 */
/*0340*/ DADD R10, R8, R10 ; /* 0x00000000080a7229 */
/* 0x004e4e000000000a */
/*0350*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x002fe8000c101b04 */
/*0360*/ LDG.E.64 R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x008ea4000c1e1b00 */
/*0370*/ DADD R12, R10, R12 ; /* 0x000000000a0c7229 */
/* 0x004e4e000000000c */
/*0380*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x002fe8000c101b04 */
/*0390*/ LDG.E.64 R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x010ea4000c1e1b00 */
/*03a0*/ DADD R14, R12, R14 ; /* 0x000000000c0e7229 */
/* 0x004e4e000000000e */
/*03b0*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x002fe8000c101b04 */
/*03c0*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x001ea4000c1e1b00 */
/*03d0*/ DADD R6, R14, R6 ; /* 0x000000000e067229 */
/* 0x004e0e0000000006 */
/*03e0*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x001fe2000c101b04 */
/*03f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0400*/ BRA 0x400; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16sumM_kernel_cudaPdS_m
.globl _Z16sumM_kernel_cudaPdS_m
.p2align 8
.type _Z16sumM_kernel_cudaPdS_m,@function
_Z16sumM_kernel_cudaPdS_m:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b64 v[4:5], v[2:3], off
global_load_b64 v[6:7], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], v[6:7]
global_store_b64 v[2:3], v[4:5], off
global_load_b64 v[6:7], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], v[6:7]
global_store_b64 v[2:3], v[4:5], off
global_load_b64 v[6:7], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], v[6:7]
global_store_b64 v[2:3], v[4:5], off
global_load_b64 v[6:7], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], v[6:7]
global_store_b64 v[2:3], v[4:5], off
global_load_b64 v[6:7], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], v[6:7]
global_store_b64 v[2:3], v[4:5], off
global_load_b64 v[6:7], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], v[6:7]
global_store_b64 v[2:3], v[4:5], off
global_load_b64 v[6:7], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], v[6:7]
global_store_b64 v[2:3], v[4:5], off
global_load_b64 v[6:7], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], v[6:7]
global_store_b64 v[2:3], v[4:5], off
global_load_b64 v[6:7], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], v[6:7]
global_store_b64 v[2:3], v[4:5], off
global_load_b64 v[6:7], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], v[6:7]
global_store_b64 v[2:3], v[4:5], off
global_load_b64 v[6:7], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], v[6:7]
global_store_b64 v[2:3], v[4:5], off
global_load_b64 v[6:7], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], v[6:7]
global_store_b64 v[2:3], v[4:5], off
global_load_b64 v[6:7], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], v[6:7]
global_store_b64 v[2:3], v[4:5], off
global_load_b64 v[6:7], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], v[6:7]
global_store_b64 v[2:3], v[4:5], off
global_load_b64 v[6:7], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], v[6:7]
global_store_b64 v[2:3], v[4:5], off
global_load_b64 v[0:1], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[0:1], v[4:5], v[0:1]
global_store_b64 v[2:3], v[0:1], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16sumM_kernel_cudaPdS_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16sumM_kernel_cudaPdS_m, .Lfunc_end0-_Z16sumM_kernel_cudaPdS_m
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16sumM_kernel_cudaPdS_m
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16sumM_kernel_cudaPdS_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0011e2a6_00000000-6_sumMatrixGPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9dwalltimev
.type _Z9dwalltimev, @function
_Z9dwalltimev:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
divsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z9dwalltimev, .-_Z9dwalltimev
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "->N\303\272m. hilos/bloq cambiado a %d (m\303\241x por bloque para dev)\n\n"
.align 8
.LC2:
.string "->N\303\272m. hilos/bloq cambiado a %d (m\303\241x por bloque para dev)\n"
.align 8
.LC3:
.string "->N\303\272m. total de hilos cambiado a %lu (m\303\241x por grid para dev)\n\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "\n"
.section .rodata.str1.8
.align 8
.LC5:
.string "->N\303\272m. hilos/bloq cambiado a %d (%d m\303\241x. bloq/grid para dev)\n\n"
.text
.globl _Z11checkparamsPmPj
.type _Z11checkparamsPmPj, @function
_Z11checkparamsPmPj:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $1048, %rsp
.cfi_def_cfa_offset 1072
movq %rdi, %rbp
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 1032(%rsp)
xorl %eax, %eax
movq (%rdi), %rax
movl (%rsi), %edx
cmpq %rdx, %rax
jnb .L8
movl %eax, (%rsi)
.L8:
movq %rsp, %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
movl 324(%rsp), %edx
cmpl (%rbx), %edx
jb .L15
.L9:
movl (%rbx), %esi
movq 0(%rbp), %rax
leaq -1(%rax), %rcx
movl 336(%rsp), %edi
leaq (%rsi,%rcx), %rax
movl $0, %edx
divq %rsi
movslq %edi, %rdx
cmpq %rax, %rdx
jnb .L7
leaq (%rcx,%rcx), %rax
leal -1(%rdi), %ecx
movslq %ecx, %rcx
movl $0, %edx
divq %rcx
movl %eax, (%rbx)
movl 324(%rsp), %edx
cmpl %eax, %edx
jnb .L11
movl %edx, (%rbx)
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
imull (%rbx), %edx
cmpq 0(%rbp), %rdx
jnb .L12
movq %rdx, 0(%rbp)
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L7
.L15:
movl %edx, (%rbx)
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L9
.L12:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L7
.L11:
movl %edi, %ecx
movl %eax, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L7:
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $1048, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z11checkparamsPmPj, .-_Z11checkparamsPmPj
.globl _Z39__device_stub__Z16sumM_kernel_cudaPdS_mPdS_m
.type _Z39__device_stub__Z16sumM_kernel_cudaPdS_mPdS_m, @function
_Z39__device_stub__Z16sumM_kernel_cudaPdS_mPdS_m:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16sumM_kernel_cudaPdS_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z39__device_stub__Z16sumM_kernel_cudaPdS_mPdS_m, .-_Z39__device_stub__Z16sumM_kernel_cudaPdS_mPdS_m
.globl _Z16sumM_kernel_cudaPdS_m
.type _Z16sumM_kernel_cudaPdS_m, @function
_Z16sumM_kernel_cudaPdS_m:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z16sumM_kernel_cudaPdS_mPdS_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z16sumM_kernel_cudaPdS_m, .-_Z16sumM_kernel_cudaPdS_m
.section .rodata.str1.1
.LC6:
.string "Falta argumento: N\n"
.section .rodata.str1.8
.align 8
.LC7:
.string "Tiempo para sumar las matrices: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
cmpl $2, %edi
je .L26
leaq .LC6(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
.L27:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L36
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movslq %eax, %rbx
imulq %rbx, %rbx
movq %rbx, 24(%rsp)
movl $16, 20(%rsp)
salq $3, %rbx
leaq 20(%rsp), %rsi
leaq 24(%rsp), %rdi
call _Z11checkparamsPmPj
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movq 24(%rsp), %r13
testq %r13, %r13
je .L28
movl $0, %edx
movl $0, %eax
.L31:
movl %edx, %ecx
pxor %xmm0, %xmm0
cvtsi2sdq %rcx, %xmm0
movsd %xmm0, 0(%rbp,%rax,8)
movsd %xmm0, (%r12,%rax,8)
addl $1, %edx
movl %edx, %eax
cmpq %r13, %rax
jb .L31
.L28:
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl 20(%rsp), %r14d
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl %r14d, %ecx
leaq -1(%rcx,%r13), %rax
movl $0, %edx
divq %rcx
movl %eax, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
call _Z9dwalltimev
movsd %xmm0, 8(%rsp)
movl %r14d, 48(%rsp)
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L32:
call cudaThreadSynchronize@PLT
call _Z9dwalltimev
subsd 8(%rsp), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 32(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
jmp .L27
.L37:
movq %r13, %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z39__device_stub__Z16sumM_kernel_cudaPdS_mPdS_m
jmp .L32
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z16sumM_kernel_cudaPdS_m"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z16sumM_kernel_cudaPdS_m(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sumMatrixGPU.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z9dwalltimev
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z9dwalltimev
.p2align 4, 0x90
.type _Z9dwalltimev,@function
_Z9dwalltimev: # @_Z9dwalltimev
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm1
cvtsi2sdq 16(%rsp), %xmm0
divsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z9dwalltimev, .Lfunc_end0-_Z9dwalltimev
.cfi_endproc
# -- End function
.globl _Z31__device_stub__sumM_kernel_cudaPdS_m # -- Begin function _Z31__device_stub__sumM_kernel_cudaPdS_m
.p2align 4, 0x90
.type _Z31__device_stub__sumM_kernel_cudaPdS_m,@function
_Z31__device_stub__sumM_kernel_cudaPdS_m: # @_Z31__device_stub__sumM_kernel_cudaPdS_m
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16sumM_kernel_cudaPdS_m, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z31__device_stub__sumM_kernel_cudaPdS_m, .Lfunc_end1-_Z31__device_stub__sumM_kernel_cudaPdS_m
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB2_1
# %bb.2:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movslq %eax, %rbx
imulq %rbx, %rbx
movq %rbx, 64(%rsp)
movl $16, 12(%rsp)
shlq $3, %rbx
leaq 64(%rsp), %rdi
leaq 12(%rsp), %rsi
callq _Z11checkparamsPmPj
movq %rbx, %rdi
callq malloc
movq %rax, %r14
movq %rbx, %rdi
callq malloc
movq %rax, %r15
movq 64(%rsp), %rbp
testq %rbp, %rbp
je .LBB2_5
# %bb.3: # %.lr.ph.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %eax, %ecx
xorps %xmm0, %xmm0
cvtsi2sd %rcx, %xmm0
movsd %xmm0, (%r14,%rax,8)
movsd %xmm0, (%r15,%rax,8)
incq %rax
movl %eax, %ecx
cmpq %rcx, %rbp
ja .LBB2_4
.LBB2_5: # %._crit_edge
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq %r15, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movl 12(%rsp), %ecx
movabsq $4294967296, %rsi # imm = 0x100000000
leaq (%rcx,%rsi), %r12
leaq (%rcx,%rbp), %rax
decq %rax
xorl %edx, %edx
divq %rcx
movl %eax, %r13d
orq %rsi, %r13
leaq 32(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 32(%rsp), %xmm0
cvtsi2sdq 40(%rsp), %xmm1
divsd .LCPI2_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 72(%rsp) # 8-byte Spill
movq %r13, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_7
# %bb.6:
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movq %rbp, 128(%rsp)
leaq 144(%rsp), %rax
movq %rax, 32(%rsp)
leaq 136(%rsp), %rax
movq %rax, 40(%rsp)
leaq 128(%rsp), %rax
movq %rax, 48(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z16sumM_kernel_cudaPdS_m, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_7:
callq hipDeviceSynchronize
leaq 32(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq 32(%rsp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 40(%rsp), %xmm0
divsd .LCPI2_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd 72(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rsi
movq %r14, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
jmp .LBB2_8
.LBB2_1:
movl $.Lstr, %edi
callq puts@PLT
.LBB2_8:
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.globl _Z11checkparamsPmPj # -- Begin function _Z11checkparamsPmPj
.p2align 4, 0x90
.type _Z11checkparamsPmPj,@function
_Z11checkparamsPmPj: # @_Z11checkparamsPmPj
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %r14
movq %rdi, %rbx
movl (%rsi), %ecx
movq (%rdi), %rax
cmpq %rcx, %rax
jae .LBB3_2
# %bb.1:
movl %eax, (%r14)
.LBB3_2:
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl 332(%rsp), %esi
cmpl %esi, (%r14)
jbe .LBB3_4
# %bb.3:
movl %esi, (%r14)
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
.LBB3_4:
movq (%rbx), %rsi
movl (%r14), %ecx
leaq (%rsi,%rcx), %rax
decq %rax
xorl %edx, %edx
divq %rcx
movslq 344(%rsp), %rcx
cmpq %rcx, %rax
jbe .LBB3_10
# %bb.5:
leaq -2(,%rsi,2), %rax
leaq -1(%rcx), %rsi
xorl %edx, %edx
divq %rsi
movl %eax, (%r14)
movl 332(%rsp), %esi
cmpl %eax, %esi
jae .LBB3_9
# %bb.6:
movl %esi, (%r14)
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl (%r14), %esi
imull 344(%rsp), %esi
cmpq %rsi, (%rbx)
jbe .LBB3_8
# %bb.7:
movq %rsi, (%rbx)
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
jmp .LBB3_10
.LBB3_9:
movl $.L.str.6, %edi
movl %eax, %esi
movl %ecx, %edx
xorl %eax, %eax
callq printf
jmp .LBB3_10
.LBB3_8:
movl $10, %edi
callq putchar@PLT
.LBB3_10:
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z11checkparamsPmPj, .Lfunc_end3-_Z11checkparamsPmPj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16sumM_kernel_cudaPdS_m, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16sumM_kernel_cudaPdS_m,@object # @_Z16sumM_kernel_cudaPdS_m
.section .rodata,"a",@progbits
.globl _Z16sumM_kernel_cudaPdS_m
.p2align 3, 0x0
_Z16sumM_kernel_cudaPdS_m:
.quad _Z31__device_stub__sumM_kernel_cudaPdS_m
.size _Z16sumM_kernel_cudaPdS_m, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Tiempo para sumar las matrices: %f\n"
.size .L.str.1, 36
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "->N\303\272m. hilos/bloq cambiado a %d (m\303\241x por bloque para dev)\n\n"
.size .L.str.2, 62
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "->N\303\272m. hilos/bloq cambiado a %d (m\303\241x por bloque para dev)\n"
.size .L.str.3, 61
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "->N\303\272m. total de hilos cambiado a %lu (m\303\241x por grid para dev)\n\n"
.size .L.str.4, 65
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "->N\303\272m. hilos/bloq cambiado a %d (%d m\303\241x. bloq/grid para dev)\n\n"
.size .L.str.6, 65
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16sumM_kernel_cudaPdS_m"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Falta argumento: N"
.size .Lstr, 19
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__sumM_kernel_cudaPdS_m
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16sumM_kernel_cudaPdS_m
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <cstdio>
__global__ void hello_cuda() {
printf("hello CUDA world\n");
}
int main(void)
{
// hello_cuda<<<1, 1>>>();
//hello_cuda<<<1, 20>>>();
// dim3 block(4);
// dim3 grid(8);
dim3 block(8, 2);
dim3 grid(2, 2);
hello_cuda<<<block, grid>>>();
cudaDeviceSynchronize();
cudaDeviceReset();
return 0;
} | code for sm_80
Function : _Z10hello_cudav
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <cstdio>
__global__ void hello_cuda() {
printf("hello CUDA world\n");
}
int main(void)
{
// hello_cuda<<<1, 1>>>();
//hello_cuda<<<1, 20>>>();
// dim3 block(4);
// dim3 grid(8);
dim3 block(8, 2);
dim3 grid(2, 2);
hello_cuda<<<block, grid>>>();
cudaDeviceSynchronize();
cudaDeviceReset();
return 0;
} | .file "tmpxft_001b501d_00000000-6_hello_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10hello_cudavv
.type _Z29__device_stub__Z10hello_cudavv, @function
_Z29__device_stub__Z10hello_cudavv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10hello_cudav(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z10hello_cudavv, .-_Z29__device_stub__Z10hello_cudavv
.globl _Z10hello_cudav
.type _Z10hello_cudav, @function
_Z10hello_cudav:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10hello_cudavv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10hello_cudav, .-_Z10hello_cudav
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $8, 8(%rsp)
movl $2, 12(%rsp)
movl $2, 20(%rsp)
movl $2, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z29__device_stub__Z10hello_cudavv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10hello_cudav"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10hello_cudav(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <cstdio>
__global__ void hello_cuda() {
printf("hello CUDA world\n");
}
int main(void)
{
// hello_cuda<<<1, 1>>>();
//hello_cuda<<<1, 20>>>();
// dim3 block(4);
// dim3 grid(8);
dim3 block(8, 2);
dim3 grid(2, 2);
hello_cuda<<<block, grid>>>();
cudaDeviceSynchronize();
cudaDeviceReset();
return 0;
} | #include "hip/hip_runtime.h"
#include <cstdio>
__global__ void hello_cuda() {
printf("hello CUDA world\n");
}
int main(void)
{
// hello_cuda<<<1, 1>>>();
//hello_cuda<<<1, 20>>>();
// dim3 block(4);
// dim3 grid(8);
dim3 block(8, 2);
dim3 grid(2, 2);
hello_cuda<<<block, grid>>>();
hipDeviceSynchronize();
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <cstdio>
__global__ void hello_cuda() {
printf("hello CUDA world\n");
}
int main(void)
{
// hello_cuda<<<1, 1>>>();
//hello_cuda<<<1, 20>>>();
// dim3 block(4);
// dim3 grid(8);
dim3 block(8, 2);
dim3 grid(2, 2);
hello_cuda<<<block, grid>>>();
hipDeviceSynchronize();
hipDeviceReset();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10hello_cudav
.globl _Z10hello_cudav
.p2align 8
.type _Z10hello_cudav,@function
_Z10hello_cudav:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 18
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10hello_cudav
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10hello_cudav, .Lfunc_end0-_Z10hello_cudav
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "hello CUDA world\n"
.size .str, 18
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10hello_cudav
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z10hello_cudav.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <cstdio>
__global__ void hello_cuda() {
printf("hello CUDA world\n");
}
int main(void)
{
// hello_cuda<<<1, 1>>>();
//hello_cuda<<<1, 20>>>();
// dim3 block(4);
// dim3 grid(8);
dim3 block(8, 2);
dim3 grid(2, 2);
hello_cuda<<<block, grid>>>();
hipDeviceSynchronize();
hipDeviceReset();
return 0;
} | .text
.file "hello_cuda.hip"
.globl _Z25__device_stub__hello_cudav # -- Begin function _Z25__device_stub__hello_cudav
.p2align 4, 0x90
.type _Z25__device_stub__hello_cudav,@function
_Z25__device_stub__hello_cudav: # @_Z25__device_stub__hello_cudav
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10hello_cudav, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z25__device_stub__hello_cudav, .Lfunc_end0-_Z25__device_stub__hello_cudav
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $8589934594, %rdx # imm = 0x200000002
leaq 6(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10hello_cudav, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
callq hipDeviceReset
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10hello_cudav, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10hello_cudav,@object # @_Z10hello_cudav
.section .rodata,"a",@progbits
.globl _Z10hello_cudav
.p2align 3, 0x0
_Z10hello_cudav:
.quad _Z25__device_stub__hello_cudav
.size _Z10hello_cudav, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10hello_cudav"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__hello_cudav
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10hello_cudav
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10hello_cudav
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10hello_cudav
.globl _Z10hello_cudav
.p2align 8
.type _Z10hello_cudav,@function
_Z10hello_cudav:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 18
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10hello_cudav
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10hello_cudav, .Lfunc_end0-_Z10hello_cudav
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "hello CUDA world\n"
.size .str, 18
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10hello_cudav
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z10hello_cudav.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b501d_00000000-6_hello_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10hello_cudavv
.type _Z29__device_stub__Z10hello_cudavv, @function
_Z29__device_stub__Z10hello_cudavv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10hello_cudav(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z10hello_cudavv, .-_Z29__device_stub__Z10hello_cudavv
.globl _Z10hello_cudav
.type _Z10hello_cudav, @function
_Z10hello_cudav:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10hello_cudavv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10hello_cudav, .-_Z10hello_cudav
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $8, 8(%rsp)
movl $2, 12(%rsp)
movl $2, 20(%rsp)
movl $2, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z29__device_stub__Z10hello_cudavv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10hello_cudav"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10hello_cudav(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hello_cuda.hip"
.globl _Z25__device_stub__hello_cudav # -- Begin function _Z25__device_stub__hello_cudav
.p2align 4, 0x90
.type _Z25__device_stub__hello_cudav,@function
_Z25__device_stub__hello_cudav: # @_Z25__device_stub__hello_cudav
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10hello_cudav, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z25__device_stub__hello_cudav, .Lfunc_end0-_Z25__device_stub__hello_cudav
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $8589934594, %rdx # imm = 0x200000002
leaq 6(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10hello_cudav, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
callq hipDeviceReset
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10hello_cudav, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10hello_cudav,@object # @_Z10hello_cudav
.section .rodata,"a",@progbits
.globl _Z10hello_cudav
.p2align 3, 0x0
_Z10hello_cudav:
.quad _Z25__device_stub__hello_cudav
.size _Z10hello_cudav, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10hello_cudav"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__hello_cudav
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10hello_cudav
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <cmath>
#include <chrono>
// Addition of arrays using a stride loop
void checkError(cudaError_t e)
{
if (e != cudaSuccess)
{
std::cerr << "CUDA error: " << int(e) << " : " << cudaGetErrorString(e) << '\n';
abort();
}
}
__global__
void add(int n, double* x, double const* y)
{
// This version will fail if the number of blocks is insufficient to cover the whole array
int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i < n)
{
x[i] = x[i] + y[i];
}
}
int main()
{
int N = 1<<20; // pow(2,20) = 1,048,576
// allocate memory on the host
double* x = new double[N];
double* y = new double[N];
// initialize arrays
for (int i = 0; i < N; i++)
{
x[i] = 1.0;
y[i] = 2.0;
}
// allocate memory on the device
double* xDevice;
double* yDevice;
checkError(cudaMalloc(&xDevice, N*sizeof(double)));
checkError(cudaMalloc(&yDevice, N*sizeof(double)));
// copy memory from host to device
checkError(cudaMemcpy(xDevice, x, N*sizeof(double), cudaMemcpyHostToDevice));
checkError(cudaMemcpy(yDevice, y, N*sizeof(double), cudaMemcpyHostToDevice));
int Threads = 256;
int Blocks = (N+Threads-1)/Threads;
auto t1 = std::chrono::high_resolution_clock::now();
add<<<Blocks, Threads>>>(N, xDevice, yDevice);
checkError(cudaDeviceSynchronize());
auto t2 = std::chrono::high_resolution_clock::now();
// copy memory from device back to host
checkError(cudaMemcpy(x, xDevice, N*sizeof(double), cudaMemcpyDeviceToHost));
auto duration = std::chrono::duration_cast<std::chrono::microseconds>(t2-t1).count();
std::cout << "Time = " << duration << " us\n";
// clean up
checkError(cudaFree(xDevice));
checkError(cudaFree(yDevice));
delete[] x;
delete[] y;
} | code for sm_80
Function : _Z3addiPdPKd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R2, R3, c[0x0][0x170] ; /* 0x00005c0002047625 */
/* 0x000fc800078e0203 */
/*0090*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fe400078e0203 */
/*00a0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea4000c1e1b00 */
/*00c0*/ DADD R6, R4, R6 ; /* 0x0000000004067229 */
/* 0x004e0e0000000006 */
/*00d0*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x001fe2000c101b04 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <cmath>
#include <chrono>
// Addition of arrays using a stride loop
void checkError(cudaError_t e)
{
if (e != cudaSuccess)
{
std::cerr << "CUDA error: " << int(e) << " : " << cudaGetErrorString(e) << '\n';
abort();
}
}
__global__
void add(int n, double* x, double const* y)
{
// This version will fail if the number of blocks is insufficient to cover the whole array
int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i < n)
{
x[i] = x[i] + y[i];
}
}
int main()
{
int N = 1<<20; // pow(2,20) = 1,048,576
// allocate memory on the host
double* x = new double[N];
double* y = new double[N];
// initialize arrays
for (int i = 0; i < N; i++)
{
x[i] = 1.0;
y[i] = 2.0;
}
// allocate memory on the device
double* xDevice;
double* yDevice;
checkError(cudaMalloc(&xDevice, N*sizeof(double)));
checkError(cudaMalloc(&yDevice, N*sizeof(double)));
// copy memory from host to device
checkError(cudaMemcpy(xDevice, x, N*sizeof(double), cudaMemcpyHostToDevice));
checkError(cudaMemcpy(yDevice, y, N*sizeof(double), cudaMemcpyHostToDevice));
int Threads = 256;
int Blocks = (N+Threads-1)/Threads;
auto t1 = std::chrono::high_resolution_clock::now();
add<<<Blocks, Threads>>>(N, xDevice, yDevice);
checkError(cudaDeviceSynchronize());
auto t2 = std::chrono::high_resolution_clock::now();
// copy memory from device back to host
checkError(cudaMemcpy(x, xDevice, N*sizeof(double), cudaMemcpyDeviceToHost));
auto duration = std::chrono::duration_cast<std::chrono::microseconds>(t2-t1).count();
std::cout << "Time = " << duration << " us\n";
// clean up
checkError(cudaFree(xDevice));
checkError(cudaFree(yDevice));
delete[] x;
delete[] y;
} | .file "tmpxft_0006b4a7_00000000-6_sumarrays-gpu-v3.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3774:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3774:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA error: "
.LC1:
.string " : "
.text
.globl _Z10checkError9cudaError
.type _Z10checkError9cudaError, @function
_Z10checkError9cudaError:
.LFB3768:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L8
ret
.L8:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl %edi, %ebx
leaq .LC0(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbp
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $10, %esi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
call abort@PLT
.cfi_endproc
.LFE3768:
.size _Z10checkError9cudaError, .-_Z10checkError9cudaError
.globl _Z26__device_stub__Z3addiPdPKdiPdPKd
.type _Z26__device_stub__Z3addiPdPKdiPdPKd, @function
_Z26__device_stub__Z3addiPdPKdiPdPKd:
.LFB3796:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addiPdPKd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3796:
.size _Z26__device_stub__Z3addiPdPKdiPdPKd, .-_Z26__device_stub__Z3addiPdPKdiPdPKd
.globl _Z3addiPdPKd
.type _Z3addiPdPKd, @function
_Z3addiPdPKd:
.LFB3797:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addiPdPKdiPdPKd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3797:
.size _Z3addiPdPKd, .-_Z3addiPdPKd
.section .rodata.str1.1
.LC4:
.string "Time = "
.LC5:
.string " us\n"
.text
.globl main
.type main, @function
main:
.LFB3769:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $8388608, %edi
call _Znam@PLT
movq %rax, %rbx
movl $8388608, %edi
call _Znam@PLT
movq %rax, %rbp
movl $0, %eax
movsd .LC2(%rip), %xmm1
movsd .LC3(%rip), %xmm0
.L18:
movsd %xmm1, (%rbx,%rax)
movsd %xmm0, 0(%rbp,%rax)
addq $8, %rax
cmpq $8388608, %rax
jne .L18
movq %rsp, %rdi
movl $8388608, %esi
call cudaMalloc@PLT
movl %eax, %edi
call _Z10checkError9cudaError
leaq 8(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
movl %eax, %edi
call _Z10checkError9cudaError
movl $1, %ecx
movl $8388608, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z10checkError9cudaError
movl $1, %ecx
movl $8388608, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z10checkError9cudaError
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r13
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $4096, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
call cudaDeviceSynchronize@PLT
movl %eax, %edi
call _Z10checkError9cudaError
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r12
movl $2, %ecx
movl $8388608, %edx
movq (%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z10checkError9cudaError
movq %r12, %rcx
subq %r13, %rcx
movabsq $2361183241434822607, %rdx
movq %rcx, %rax
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
subq %rcx, %rdx
movq %rdx, %r12
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r12, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
call _Z10checkError9cudaError
movq 8(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
call _Z10checkError9cudaError
movq %rbx, %rdi
call _ZdaPv@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movl $1048576, %edi
call _Z26__device_stub__Z3addiPdPKdiPdPKd
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3769:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z3addiPdPKd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3799:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiPdPKd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3799:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1072693248
.align 8
.LC3:
.long 0
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cmath>
#include <chrono>
// Addition of arrays using a stride loop
void checkError(cudaError_t e)
{
if (e != cudaSuccess)
{
std::cerr << "CUDA error: " << int(e) << " : " << cudaGetErrorString(e) << '\n';
abort();
}
}
__global__
void add(int n, double* x, double const* y)
{
// This version will fail if the number of blocks is insufficient to cover the whole array
int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i < n)
{
x[i] = x[i] + y[i];
}
}
int main()
{
int N = 1<<20; // pow(2,20) = 1,048,576
// allocate memory on the host
double* x = new double[N];
double* y = new double[N];
// initialize arrays
for (int i = 0; i < N; i++)
{
x[i] = 1.0;
y[i] = 2.0;
}
// allocate memory on the device
double* xDevice;
double* yDevice;
checkError(cudaMalloc(&xDevice, N*sizeof(double)));
checkError(cudaMalloc(&yDevice, N*sizeof(double)));
// copy memory from host to device
checkError(cudaMemcpy(xDevice, x, N*sizeof(double), cudaMemcpyHostToDevice));
checkError(cudaMemcpy(yDevice, y, N*sizeof(double), cudaMemcpyHostToDevice));
int Threads = 256;
int Blocks = (N+Threads-1)/Threads;
auto t1 = std::chrono::high_resolution_clock::now();
add<<<Blocks, Threads>>>(N, xDevice, yDevice);
checkError(cudaDeviceSynchronize());
auto t2 = std::chrono::high_resolution_clock::now();
// copy memory from device back to host
checkError(cudaMemcpy(x, xDevice, N*sizeof(double), cudaMemcpyDeviceToHost));
auto duration = std::chrono::duration_cast<std::chrono::microseconds>(t2-t1).count();
std::cout << "Time = " << duration << " us\n";
// clean up
checkError(cudaFree(xDevice));
checkError(cudaFree(yDevice));
delete[] x;
delete[] y;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <cmath>
#include <chrono>
// Addition of arrays using a stride loop
void checkError(hipError_t e)
{
if (e != hipSuccess)
{
std::cerr << "CUDA error: " << int(e) << " : " << hipGetErrorString(e) << '\n';
abort();
}
}
__global__
void add(int n, double* x, double const* y)
{
// This version will fail if the number of blocks is insufficient to cover the whole array
int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i < n)
{
x[i] = x[i] + y[i];
}
}
int main()
{
int N = 1<<20; // pow(2,20) = 1,048,576
// allocate memory on the host
double* x = new double[N];
double* y = new double[N];
// initialize arrays
for (int i = 0; i < N; i++)
{
x[i] = 1.0;
y[i] = 2.0;
}
// allocate memory on the device
double* xDevice;
double* yDevice;
checkError(hipMalloc(&xDevice, N*sizeof(double)));
checkError(hipMalloc(&yDevice, N*sizeof(double)));
// copy memory from host to device
checkError(hipMemcpy(xDevice, x, N*sizeof(double), hipMemcpyHostToDevice));
checkError(hipMemcpy(yDevice, y, N*sizeof(double), hipMemcpyHostToDevice));
int Threads = 256;
int Blocks = (N+Threads-1)/Threads;
auto t1 = std::chrono::high_resolution_clock::now();
add<<<Blocks, Threads>>>(N, xDevice, yDevice);
checkError(hipDeviceSynchronize());
auto t2 = std::chrono::high_resolution_clock::now();
// copy memory from device back to host
checkError(hipMemcpy(x, xDevice, N*sizeof(double), hipMemcpyDeviceToHost));
auto duration = std::chrono::duration_cast<std::chrono::microseconds>(t2-t1).count();
std::cout << "Time = " << duration << " us\n";
// clean up
checkError(hipFree(xDevice));
checkError(hipFree(yDevice));
delete[] x;
delete[] y;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cmath>
#include <chrono>
// Addition of arrays using a stride loop
void checkError(hipError_t e)
{
if (e != hipSuccess)
{
std::cerr << "CUDA error: " << int(e) << " : " << hipGetErrorString(e) << '\n';
abort();
}
}
__global__
void add(int n, double* x, double const* y)
{
// This version will fail if the number of blocks is insufficient to cover the whole array
int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i < n)
{
x[i] = x[i] + y[i];
}
}
int main()
{
int N = 1<<20; // pow(2,20) = 1,048,576
// allocate memory on the host
double* x = new double[N];
double* y = new double[N];
// initialize arrays
for (int i = 0; i < N; i++)
{
x[i] = 1.0;
y[i] = 2.0;
}
// allocate memory on the device
double* xDevice;
double* yDevice;
checkError(hipMalloc(&xDevice, N*sizeof(double)));
checkError(hipMalloc(&yDevice, N*sizeof(double)));
// copy memory from host to device
checkError(hipMemcpy(xDevice, x, N*sizeof(double), hipMemcpyHostToDevice));
checkError(hipMemcpy(yDevice, y, N*sizeof(double), hipMemcpyHostToDevice));
int Threads = 256;
int Blocks = (N+Threads-1)/Threads;
auto t1 = std::chrono::high_resolution_clock::now();
add<<<Blocks, Threads>>>(N, xDevice, yDevice);
checkError(hipDeviceSynchronize());
auto t2 = std::chrono::high_resolution_clock::now();
// copy memory from device back to host
checkError(hipMemcpy(x, xDevice, N*sizeof(double), hipMemcpyDeviceToHost));
auto duration = std::chrono::duration_cast<std::chrono::microseconds>(t2-t1).count();
std::cout << "Time = " << duration << " us\n";
// clean up
checkError(hipFree(xDevice));
checkError(hipFree(yDevice));
delete[] x;
delete[] y;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiPdPKd
.globl _Z3addiPdPKd
.p2align 8
.type _Z3addiPdPKd,@function
_Z3addiPdPKd:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b64 v[4:5], v[2:3], off
global_load_b64 v[0:1], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[0:1], v[4:5], v[0:1]
global_store_b64 v[2:3], v[0:1], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiPdPKd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addiPdPKd, .Lfunc_end0-_Z3addiPdPKd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiPdPKd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addiPdPKd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cmath>
#include <chrono>
// Addition of arrays using a stride loop
void checkError(hipError_t e)
{
if (e != hipSuccess)
{
std::cerr << "CUDA error: " << int(e) << " : " << hipGetErrorString(e) << '\n';
abort();
}
}
__global__
void add(int n, double* x, double const* y)
{
// This version will fail if the number of blocks is insufficient to cover the whole array
int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i < n)
{
x[i] = x[i] + y[i];
}
}
int main()
{
int N = 1<<20; // pow(2,20) = 1,048,576
// allocate memory on the host
double* x = new double[N];
double* y = new double[N];
// initialize arrays
for (int i = 0; i < N; i++)
{
x[i] = 1.0;
y[i] = 2.0;
}
// allocate memory on the device
double* xDevice;
double* yDevice;
checkError(hipMalloc(&xDevice, N*sizeof(double)));
checkError(hipMalloc(&yDevice, N*sizeof(double)));
// copy memory from host to device
checkError(hipMemcpy(xDevice, x, N*sizeof(double), hipMemcpyHostToDevice));
checkError(hipMemcpy(yDevice, y, N*sizeof(double), hipMemcpyHostToDevice));
int Threads = 256;
int Blocks = (N+Threads-1)/Threads;
auto t1 = std::chrono::high_resolution_clock::now();
add<<<Blocks, Threads>>>(N, xDevice, yDevice);
checkError(hipDeviceSynchronize());
auto t2 = std::chrono::high_resolution_clock::now();
// copy memory from device back to host
checkError(hipMemcpy(x, xDevice, N*sizeof(double), hipMemcpyDeviceToHost));
auto duration = std::chrono::duration_cast<std::chrono::microseconds>(t2-t1).count();
std::cout << "Time = " << duration << " us\n";
// clean up
checkError(hipFree(xDevice));
checkError(hipFree(yDevice));
delete[] x;
delete[] y;
} | .text
.file "sumarrays-gpu-v3.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z10checkError10hipError_t # -- Begin function _Z10checkError10hipError_t
.p2align 4, 0x90
.type _Z10checkError10hipError_t,@function
_Z10checkError10hipError_t: # @_Z10checkError10hipError_t
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB0_2
# %bb.1:
retq
.LBB0_2:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %edi, %ebx
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebx, %esi
callq _ZNSolsEi
movl $.L.str.1, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $10, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c
callq abort
.Lfunc_end0:
.size _Z10checkError10hipError_t, .Lfunc_end0-_Z10checkError10hipError_t
.cfi_endproc
# -- End function
.globl _Z18__device_stub__addiPdPKd # -- Begin function _Z18__device_stub__addiPdPKd
.p2align 4, 0x90
.type _Z18__device_stub__addiPdPKd,@function
_Z18__device_stub__addiPdPKd: # @_Z18__device_stub__addiPdPKd
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addiPdPKd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z18__device_stub__addiPdPKd, .Lfunc_end1-_Z18__device_stub__addiPdPKd
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $8388608, %edi # imm = 0x800000
callq _Znam
movq %rax, %rbx
movl $8388608, %edi # imm = 0x800000
callq _Znam
movq %rax, %r14
xorl %eax, %eax
movabsq $4607182418800017408, %rcx # imm = 0x3FF0000000000000
movabsq $4611686018427387904, %rdx # imm = 0x4000000000000000
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movq %rcx, (%rbx,%rax,8)
movq %rdx, (%r14,%rax,8)
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB2_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
callq hipMalloc
movl %eax, %edi
callq _Z10checkError10hipError_t
leaq 16(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
callq hipMalloc
movl %eax, %edi
callq _Z10checkError10hipError_t
movq 8(%rsp), %rdi
movl $8388608, %edx # imm = 0x800000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl %eax, %edi
callq _Z10checkError10hipError_t
movq 16(%rsp), %rdi
movl $8388608, %edx # imm = 0x800000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movl %eax, %edi
callq _Z10checkError10hipError_t
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r15
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 3840(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movl $1048576, 28(%rsp) # imm = 0x100000
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addiPdPKd, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
movl %eax, %edi
callq _Z10checkError10hipError_t
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r12
movq 8(%rsp), %rsi
movl $8388608, %edx # imm = 0x800000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl %eax, %edi
callq _Z10checkError10hipError_t
subq %r15, %r12
movabsq $2361183241434822607, %rcx # imm = 0x20C49BA5E353F7CF
movq %r12, %rax
imulq %rcx
movq %rdx, %r15
shrq $63, %r15
sarq $7, %rdx
addq %rdx, %r15
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movq %r15, %rsi
callq _ZNSo9_M_insertIlEERSoT_
movl $.L.str.3, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 8(%rsp), %rdi
callq hipFree
movl %eax, %edi
callq _Z10checkError10hipError_t
movq 16(%rsp), %rdi
callq hipFree
movl %eax, %edi
callq _Z10checkError10hipError_t
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiPdPKd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA error: "
.size .L.str, 13
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " : "
.size .L.str.1, 4
.type _Z3addiPdPKd,@object # @_Z3addiPdPKd
.section .rodata,"a",@progbits
.globl _Z3addiPdPKd
.p2align 3, 0x0
_Z3addiPdPKd:
.quad _Z18__device_stub__addiPdPKd
.size _Z3addiPdPKd, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Time = "
.size .L.str.2, 8
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " us\n"
.size .L.str.3, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addiPdPKd"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addiPdPKd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZSt4cerr
.addrsig_sym _Z3addiPdPKd
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addiPdPKd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R2, R3, c[0x0][0x170] ; /* 0x00005c0002047625 */
/* 0x000fc800078e0203 */
/*0090*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fe400078e0203 */
/*00a0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea4000c1e1b00 */
/*00c0*/ DADD R6, R4, R6 ; /* 0x0000000004067229 */
/* 0x004e0e0000000006 */
/*00d0*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x001fe2000c101b04 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiPdPKd
.globl _Z3addiPdPKd
.p2align 8
.type _Z3addiPdPKd,@function
_Z3addiPdPKd:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b64 v[4:5], v[2:3], off
global_load_b64 v[0:1], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[0:1], v[4:5], v[0:1]
global_store_b64 v[2:3], v[0:1], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiPdPKd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addiPdPKd, .Lfunc_end0-_Z3addiPdPKd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiPdPKd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addiPdPKd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0006b4a7_00000000-6_sumarrays-gpu-v3.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3774:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3774:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA error: "
.LC1:
.string " : "
.text
.globl _Z10checkError9cudaError
.type _Z10checkError9cudaError, @function
_Z10checkError9cudaError:
.LFB3768:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L8
ret
.L8:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl %edi, %ebx
leaq .LC0(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbp
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $10, %esi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
call abort@PLT
.cfi_endproc
.LFE3768:
.size _Z10checkError9cudaError, .-_Z10checkError9cudaError
.globl _Z26__device_stub__Z3addiPdPKdiPdPKd
.type _Z26__device_stub__Z3addiPdPKdiPdPKd, @function
_Z26__device_stub__Z3addiPdPKdiPdPKd:
.LFB3796:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addiPdPKd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3796:
.size _Z26__device_stub__Z3addiPdPKdiPdPKd, .-_Z26__device_stub__Z3addiPdPKdiPdPKd
.globl _Z3addiPdPKd
.type _Z3addiPdPKd, @function
_Z3addiPdPKd:
.LFB3797:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addiPdPKdiPdPKd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3797:
.size _Z3addiPdPKd, .-_Z3addiPdPKd
.section .rodata.str1.1
.LC4:
.string "Time = "
.LC5:
.string " us\n"
.text
.globl main
.type main, @function
main:
.LFB3769:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $8388608, %edi
call _Znam@PLT
movq %rax, %rbx
movl $8388608, %edi
call _Znam@PLT
movq %rax, %rbp
movl $0, %eax
movsd .LC2(%rip), %xmm1
movsd .LC3(%rip), %xmm0
.L18:
movsd %xmm1, (%rbx,%rax)
movsd %xmm0, 0(%rbp,%rax)
addq $8, %rax
cmpq $8388608, %rax
jne .L18
movq %rsp, %rdi
movl $8388608, %esi
call cudaMalloc@PLT
movl %eax, %edi
call _Z10checkError9cudaError
leaq 8(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
movl %eax, %edi
call _Z10checkError9cudaError
movl $1, %ecx
movl $8388608, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z10checkError9cudaError
movl $1, %ecx
movl $8388608, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z10checkError9cudaError
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r13
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $4096, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
call cudaDeviceSynchronize@PLT
movl %eax, %edi
call _Z10checkError9cudaError
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r12
movl $2, %ecx
movl $8388608, %edx
movq (%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z10checkError9cudaError
movq %r12, %rcx
subq %r13, %rcx
movabsq $2361183241434822607, %rdx
movq %rcx, %rax
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
subq %rcx, %rdx
movq %rdx, %r12
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r12, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
call _Z10checkError9cudaError
movq 8(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
call _Z10checkError9cudaError
movq %rbx, %rdi
call _ZdaPv@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movl $1048576, %edi
call _Z26__device_stub__Z3addiPdPKdiPdPKd
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3769:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z3addiPdPKd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3799:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiPdPKd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3799:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1072693248
.align 8
.LC3:
.long 0
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sumarrays-gpu-v3.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z10checkError10hipError_t # -- Begin function _Z10checkError10hipError_t
.p2align 4, 0x90
.type _Z10checkError10hipError_t,@function
_Z10checkError10hipError_t: # @_Z10checkError10hipError_t
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB0_2
# %bb.1:
retq
.LBB0_2:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %edi, %ebx
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebx, %esi
callq _ZNSolsEi
movl $.L.str.1, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $10, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c
callq abort
.Lfunc_end0:
.size _Z10checkError10hipError_t, .Lfunc_end0-_Z10checkError10hipError_t
.cfi_endproc
# -- End function
.globl _Z18__device_stub__addiPdPKd # -- Begin function _Z18__device_stub__addiPdPKd
.p2align 4, 0x90
.type _Z18__device_stub__addiPdPKd,@function
_Z18__device_stub__addiPdPKd: # @_Z18__device_stub__addiPdPKd
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addiPdPKd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z18__device_stub__addiPdPKd, .Lfunc_end1-_Z18__device_stub__addiPdPKd
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $8388608, %edi # imm = 0x800000
callq _Znam
movq %rax, %rbx
movl $8388608, %edi # imm = 0x800000
callq _Znam
movq %rax, %r14
xorl %eax, %eax
movabsq $4607182418800017408, %rcx # imm = 0x3FF0000000000000
movabsq $4611686018427387904, %rdx # imm = 0x4000000000000000
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movq %rcx, (%rbx,%rax,8)
movq %rdx, (%r14,%rax,8)
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB2_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
callq hipMalloc
movl %eax, %edi
callq _Z10checkError10hipError_t
leaq 16(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
callq hipMalloc
movl %eax, %edi
callq _Z10checkError10hipError_t
movq 8(%rsp), %rdi
movl $8388608, %edx # imm = 0x800000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl %eax, %edi
callq _Z10checkError10hipError_t
movq 16(%rsp), %rdi
movl $8388608, %edx # imm = 0x800000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movl %eax, %edi
callq _Z10checkError10hipError_t
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r15
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 3840(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movl $1048576, 28(%rsp) # imm = 0x100000
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addiPdPKd, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
movl %eax, %edi
callq _Z10checkError10hipError_t
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r12
movq 8(%rsp), %rsi
movl $8388608, %edx # imm = 0x800000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl %eax, %edi
callq _Z10checkError10hipError_t
subq %r15, %r12
movabsq $2361183241434822607, %rcx # imm = 0x20C49BA5E353F7CF
movq %r12, %rax
imulq %rcx
movq %rdx, %r15
shrq $63, %r15
sarq $7, %rdx
addq %rdx, %r15
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movq %r15, %rsi
callq _ZNSo9_M_insertIlEERSoT_
movl $.L.str.3, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 8(%rsp), %rdi
callq hipFree
movl %eax, %edi
callq _Z10checkError10hipError_t
movq 16(%rsp), %rdi
callq hipFree
movl %eax, %edi
callq _Z10checkError10hipError_t
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiPdPKd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA error: "
.size .L.str, 13
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " : "
.size .L.str.1, 4
.type _Z3addiPdPKd,@object # @_Z3addiPdPKd
.section .rodata,"a",@progbits
.globl _Z3addiPdPKd
.p2align 3, 0x0
_Z3addiPdPKd:
.quad _Z18__device_stub__addiPdPKd
.size _Z3addiPdPKd, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Time = "
.size .L.str.2, 8
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " us\n"
.size .L.str.3, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addiPdPKd"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addiPdPKd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZSt4cerr
.addrsig_sym _Z3addiPdPKd
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime.h>
#include <stdio.h>
__global__ void doublevector(int* vec, int N)
{
int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
if (idx < N) {
vec[idx] *= 2;
}
}
__global__ void init(int* vec, int N)
{
int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
if (idx < N) {
vec[idx] = idx;
}
}
bool check(int* vec, int N)
{
for (int i=0; i<N; ++i) {
if (vec[i] != i*2) {
return false;
}
}
return true;
}
int main(int argc, char** argv)
{
const int N = 4096;
int* vec;
// managed memory in cuda
cudaError_t result = cudaMallocManaged(&vec, N * sizeof(int));
if (result != cudaSuccess) {
printf("cudaMalloc failed\n");
}
// initialize the vector on the gpu
init<<<4, N/4>>>(vec, N);
// launch a gpu kernel with 4 blocks and 1024 threads in each block.
doublevector<<<4,N/4>>>(vec, N);
// block the cpu for the gpu to finish execution
cudaDeviceSynchronize();
if (!check(vec, N)) {
printf("test failed\n");
}
cudaFree(vec);
return 0;
} | code for sm_80
Function : _Z4initPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fca00078e0202 */
/*0090*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z12doublevectorPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ SHF.L.U32 R5, R0, 0x1, RZ ; /* 0x0000000100057819 */
/* 0x004fca00000006ff */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
#include <stdio.h>
__global__ void doublevector(int* vec, int N)
{
int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
if (idx < N) {
vec[idx] *= 2;
}
}
__global__ void init(int* vec, int N)
{
int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
if (idx < N) {
vec[idx] = idx;
}
}
bool check(int* vec, int N)
{
for (int i=0; i<N; ++i) {
if (vec[i] != i*2) {
return false;
}
}
return true;
}
int main(int argc, char** argv)
{
const int N = 4096;
int* vec;
// managed memory in cuda
cudaError_t result = cudaMallocManaged(&vec, N * sizeof(int));
if (result != cudaSuccess) {
printf("cudaMalloc failed\n");
}
// initialize the vector on the gpu
init<<<4, N/4>>>(vec, N);
// launch a gpu kernel with 4 blocks and 1024 threads in each block.
doublevector<<<4,N/4>>>(vec, N);
// block the cpu for the gpu to finish execution
cudaDeviceSynchronize();
if (!check(vec, N)) {
printf("test failed\n");
}
cudaFree(vec);
return 0;
} | .file "tmpxft_0006070b_00000000-6_double_vector.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5checkPii
.type _Z5checkPii, @function
_Z5checkPii:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L6
movslq %esi, %rsi
movl $0, %eax
.L5:
leal (%rax,%rax), %edx
cmpl %edx, (%rdi,%rax,4)
jne .L7
addq $1, %rax
cmpq %rsi, %rax
jne .L5
movl $1, %eax
ret
.L6:
movl $1, %eax
ret
.L7:
movl $0, %eax
ret
.cfi_endproc
.LFE2057:
.size _Z5checkPii, .-_Z5checkPii
.globl _Z33__device_stub__Z12doublevectorPiiPii
.type _Z33__device_stub__Z12doublevectorPiiPii, @function
_Z33__device_stub__Z12doublevectorPiiPii:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12doublevectorPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z33__device_stub__Z12doublevectorPiiPii, .-_Z33__device_stub__Z12doublevectorPiiPii
.globl _Z12doublevectorPii
.type _Z12doublevectorPii, @function
_Z12doublevectorPii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z12doublevectorPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z12doublevectorPii, .-_Z12doublevectorPii
.globl _Z24__device_stub__Z4initPiiPii
.type _Z24__device_stub__Z4initPiiPii, @function
_Z24__device_stub__Z4initPiiPii:
.LFB2085:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4initPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z24__device_stub__Z4initPiiPii, .-_Z24__device_stub__Z4initPiiPii
.globl _Z4initPii
.type _Z4initPii, @function
_Z4initPii:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z4initPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z4initPii, .-_Z4initPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "cudaMalloc failed\n"
.LC1:
.string "test failed\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $16384, %esi
call cudaMallocManaged@PLT
testl %eax, %eax
jne .L32
.L26:
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $4, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L27:
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $4, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L28:
call cudaDeviceSynchronize@PLT
movl $4096, %esi
movq 8(%rsp), %rdi
call _Z5checkPii
testb %al, %al
je .L35
.L29:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L36
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L26
.L33:
movl $4096, %esi
movq 8(%rsp), %rdi
call _Z24__device_stub__Z4initPiiPii
jmp .L27
.L34:
movl $4096, %esi
movq 8(%rsp), %rdi
call _Z33__device_stub__Z12doublevectorPiiPii
jmp .L28
.L35:
leaq .LC1(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
jmp .L29
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z4initPii"
.LC3:
.string "_Z12doublevectorPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z4initPii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z12doublevectorPii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
#include <stdio.h>
__global__ void doublevector(int* vec, int N)
{
int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
if (idx < N) {
vec[idx] *= 2;
}
}
__global__ void init(int* vec, int N)
{
int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
if (idx < N) {
vec[idx] = idx;
}
}
bool check(int* vec, int N)
{
for (int i=0; i<N; ++i) {
if (vec[i] != i*2) {
return false;
}
}
return true;
}
int main(int argc, char** argv)
{
const int N = 4096;
int* vec;
// managed memory in cuda
cudaError_t result = cudaMallocManaged(&vec, N * sizeof(int));
if (result != cudaSuccess) {
printf("cudaMalloc failed\n");
}
// initialize the vector on the gpu
init<<<4, N/4>>>(vec, N);
// launch a gpu kernel with 4 blocks and 1024 threads in each block.
doublevector<<<4,N/4>>>(vec, N);
// block the cpu for the gpu to finish execution
cudaDeviceSynchronize();
if (!check(vec, N)) {
printf("test failed\n");
}
cudaFree(vec);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void doublevector(int* vec, int N)
{
int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
if (idx < N) {
vec[idx] *= 2;
}
}
__global__ void init(int* vec, int N)
{
int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
if (idx < N) {
vec[idx] = idx;
}
}
bool check(int* vec, int N)
{
for (int i=0; i<N; ++i) {
if (vec[i] != i*2) {
return false;
}
}
return true;
}
int main(int argc, char** argv)
{
const int N = 4096;
int* vec;
// managed memory in cuda
hipError_t result = hipMallocManaged(&vec, N * sizeof(int));
if (result != hipSuccess) {
printf("hipMalloc failed\n");
}
// initialize the vector on the gpu
init<<<4, N/4>>>(vec, N);
// launch a gpu kernel with 4 blocks and 1024 threads in each block.
doublevector<<<4,N/4>>>(vec, N);
// block the cpu for the gpu to finish execution
hipDeviceSynchronize();
if (!check(vec, N)) {
printf("test failed\n");
}
hipFree(vec);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void doublevector(int* vec, int N)
{
int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
if (idx < N) {
vec[idx] *= 2;
}
}
__global__ void init(int* vec, int N)
{
int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
if (idx < N) {
vec[idx] = idx;
}
}
bool check(int* vec, int N)
{
for (int i=0; i<N; ++i) {
if (vec[i] != i*2) {
return false;
}
}
return true;
}
int main(int argc, char** argv)
{
const int N = 4096;
int* vec;
// managed memory in cuda
hipError_t result = hipMallocManaged(&vec, N * sizeof(int));
if (result != hipSuccess) {
printf("hipMalloc failed\n");
}
// initialize the vector on the gpu
init<<<4, N/4>>>(vec, N);
// launch a gpu kernel with 4 blocks and 1024 threads in each block.
doublevector<<<4,N/4>>>(vec, N);
// block the cpu for the gpu to finish execution
hipDeviceSynchronize();
if (!check(vec, N)) {
printf("test failed\n");
}
hipFree(vec);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12doublevectorPii
.globl _Z12doublevectorPii
.p2align 8
.type _Z12doublevectorPii,@function
_Z12doublevectorPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v2, 1, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12doublevectorPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12doublevectorPii, .Lfunc_end0-_Z12doublevectorPii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z4initPii
.globl _Z4initPii
.p2align 8
.type _Z4initPii,@function
_Z4initPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB1_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[2:3], v1, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4initPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z4initPii, .Lfunc_end1-_Z4initPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12doublevectorPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12doublevectorPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4initPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4initPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void doublevector(int* vec, int N)
{
int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
if (idx < N) {
vec[idx] *= 2;
}
}
__global__ void init(int* vec, int N)
{
int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
if (idx < N) {
vec[idx] = idx;
}
}
bool check(int* vec, int N)
{
for (int i=0; i<N; ++i) {
if (vec[i] != i*2) {
return false;
}
}
return true;
}
int main(int argc, char** argv)
{
const int N = 4096;
int* vec;
// managed memory in cuda
hipError_t result = hipMallocManaged(&vec, N * sizeof(int));
if (result != hipSuccess) {
printf("hipMalloc failed\n");
}
// initialize the vector on the gpu
init<<<4, N/4>>>(vec, N);
// launch a gpu kernel with 4 blocks and 1024 threads in each block.
doublevector<<<4,N/4>>>(vec, N);
// block the cpu for the gpu to finish execution
hipDeviceSynchronize();
if (!check(vec, N)) {
printf("test failed\n");
}
hipFree(vec);
return 0;
} | .text
.file "double_vector.hip"
.globl _Z27__device_stub__doublevectorPii # -- Begin function _Z27__device_stub__doublevectorPii
.p2align 4, 0x90
.type _Z27__device_stub__doublevectorPii,@function
_Z27__device_stub__doublevectorPii: # @_Z27__device_stub__doublevectorPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12doublevectorPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z27__device_stub__doublevectorPii, .Lfunc_end0-_Z27__device_stub__doublevectorPii
.cfi_endproc
# -- End function
.globl _Z19__device_stub__initPii # -- Begin function _Z19__device_stub__initPii
.p2align 4, 0x90
.type _Z19__device_stub__initPii,@function
_Z19__device_stub__initPii: # @_Z19__device_stub__initPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4initPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z19__device_stub__initPii, .Lfunc_end1-_Z19__device_stub__initPii
.cfi_endproc
# -- End function
.globl _Z5checkPii # -- Begin function _Z5checkPii
.p2align 4, 0x90
.type _Z5checkPii,@function
_Z5checkPii: # @_Z5checkPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
setle %al
jle .LBB2_6
# %bb.1: # %.lr.ph.preheader
cmpl $0, (%rdi)
je .LBB2_2
.LBB2_6: # %._crit_edge
retq
.LBB2_2: # %.lr.ph14.preheader
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_3: # %.lr.ph14
# =>This Inner Loop Header: Depth=1
incq %rcx
cmpq %rax, %rcx
je .LBB2_5
# %bb.4: # %.lr.ph
# in Loop: Header=BB2_3 Depth=1
movl (%rdi,%rcx,4), %edx
leaq (%rcx,%rcx), %rsi
cmpq %rdx, %rsi
je .LBB2_3
.LBB2_5: # %._crit_edge.loopexit
cmpq %rax, %rcx
setae %al
retq
.Lfunc_end2:
.size _Z5checkPii, .Lfunc_end2-_Z5checkPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 16(%rsp), %rdi
movl $16384, %esi # imm = 0x4000
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
je .LBB3_2
# %bb.1:
movl $.Lstr, %edi
callq puts@PLT
.LBB3_2:
movabsq $4294967300, %r14 # imm = 0x100000004
leaq 1020(%r14), %rbx
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3:
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl $4096, 12(%rsp) # imm = 0x1000
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4initPii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_4:
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5:
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl $4096, 12(%rsp) # imm = 0x1000
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12doublevectorPii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6:
callq hipDeviceSynchronize
movq 16(%rsp), %rax
cmpl $0, (%rax)
jne .LBB3_11
# %bb.7: # %.lr.ph.preheader
xorl %ecx, %ecx
xorl %esi, %esi
.p2align 4, 0x90
.LBB3_8: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %rsi, %rdx
cmpq $4095, %rsi # imm = 0xFFF
je .LBB3_10
# %bb.9: # %.lr.ph.i
# in Loop: Header=BB3_8 Depth=1
movl 4(%rax,%rdx,4), %edi
addq $2, %rcx
leaq 1(%rdx), %rsi
cmpq %rdi, %rcx
je .LBB3_8
.LBB3_10: # %_Z5checkPii.exit
cmpq $4094, %rdx # imm = 0xFFE
ja .LBB3_12
.LBB3_11: # %.critedge
movl $.Lstr.1, %edi
callq puts@PLT
.LBB3_12:
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12doublevectorPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4initPii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12doublevectorPii,@object # @_Z12doublevectorPii
.section .rodata,"a",@progbits
.globl _Z12doublevectorPii
.p2align 3, 0x0
_Z12doublevectorPii:
.quad _Z27__device_stub__doublevectorPii
.size _Z12doublevectorPii, 8
.type _Z4initPii,@object # @_Z4initPii
.globl _Z4initPii
.p2align 3, 0x0
_Z4initPii:
.quad _Z19__device_stub__initPii
.size _Z4initPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12doublevectorPii"
.size .L__unnamed_1, 20
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z4initPii"
.size .L__unnamed_2, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "hipMalloc failed"
.size .Lstr, 17
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "test failed"
.size .Lstr.1, 12
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__doublevectorPii
.addrsig_sym _Z19__device_stub__initPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12doublevectorPii
.addrsig_sym _Z4initPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4initPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fca00078e0202 */
/*0090*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z12doublevectorPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ SHF.L.U32 R5, R0, 0x1, RZ ; /* 0x0000000100057819 */
/* 0x004fca00000006ff */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12doublevectorPii
.globl _Z12doublevectorPii
.p2align 8
.type _Z12doublevectorPii,@function
_Z12doublevectorPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v2, 1, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12doublevectorPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12doublevectorPii, .Lfunc_end0-_Z12doublevectorPii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z4initPii
.globl _Z4initPii
.p2align 8
.type _Z4initPii,@function
_Z4initPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB1_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[2:3], v1, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4initPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z4initPii, .Lfunc_end1-_Z4initPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12doublevectorPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12doublevectorPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4initPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4initPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0006070b_00000000-6_double_vector.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5checkPii
.type _Z5checkPii, @function
_Z5checkPii:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L6
movslq %esi, %rsi
movl $0, %eax
.L5:
leal (%rax,%rax), %edx
cmpl %edx, (%rdi,%rax,4)
jne .L7
addq $1, %rax
cmpq %rsi, %rax
jne .L5
movl $1, %eax
ret
.L6:
movl $1, %eax
ret
.L7:
movl $0, %eax
ret
.cfi_endproc
.LFE2057:
.size _Z5checkPii, .-_Z5checkPii
.globl _Z33__device_stub__Z12doublevectorPiiPii
.type _Z33__device_stub__Z12doublevectorPiiPii, @function
_Z33__device_stub__Z12doublevectorPiiPii:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12doublevectorPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z33__device_stub__Z12doublevectorPiiPii, .-_Z33__device_stub__Z12doublevectorPiiPii
.globl _Z12doublevectorPii
.type _Z12doublevectorPii, @function
_Z12doublevectorPii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z12doublevectorPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z12doublevectorPii, .-_Z12doublevectorPii
.globl _Z24__device_stub__Z4initPiiPii
.type _Z24__device_stub__Z4initPiiPii, @function
_Z24__device_stub__Z4initPiiPii:
.LFB2085:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4initPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z24__device_stub__Z4initPiiPii, .-_Z24__device_stub__Z4initPiiPii
.globl _Z4initPii
.type _Z4initPii, @function
_Z4initPii:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z4initPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z4initPii, .-_Z4initPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "cudaMalloc failed\n"
.LC1:
.string "test failed\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $16384, %esi
call cudaMallocManaged@PLT
testl %eax, %eax
jne .L32
.L26:
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $4, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L27:
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $4, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L28:
call cudaDeviceSynchronize@PLT
movl $4096, %esi
movq 8(%rsp), %rdi
call _Z5checkPii
testb %al, %al
je .L35
.L29:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L36
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L26
.L33:
movl $4096, %esi
movq 8(%rsp), %rdi
call _Z24__device_stub__Z4initPiiPii
jmp .L27
.L34:
movl $4096, %esi
movq 8(%rsp), %rdi
call _Z33__device_stub__Z12doublevectorPiiPii
jmp .L28
.L35:
leaq .LC1(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
jmp .L29
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z4initPii"
.LC3:
.string "_Z12doublevectorPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z4initPii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z12doublevectorPii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "double_vector.hip"
.globl _Z27__device_stub__doublevectorPii # -- Begin function _Z27__device_stub__doublevectorPii
.p2align 4, 0x90
.type _Z27__device_stub__doublevectorPii,@function
_Z27__device_stub__doublevectorPii: # @_Z27__device_stub__doublevectorPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12doublevectorPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z27__device_stub__doublevectorPii, .Lfunc_end0-_Z27__device_stub__doublevectorPii
.cfi_endproc
# -- End function
.globl _Z19__device_stub__initPii # -- Begin function _Z19__device_stub__initPii
.p2align 4, 0x90
.type _Z19__device_stub__initPii,@function
_Z19__device_stub__initPii: # @_Z19__device_stub__initPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4initPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z19__device_stub__initPii, .Lfunc_end1-_Z19__device_stub__initPii
.cfi_endproc
# -- End function
.globl _Z5checkPii # -- Begin function _Z5checkPii
.p2align 4, 0x90
.type _Z5checkPii,@function
_Z5checkPii: # @_Z5checkPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
setle %al
jle .LBB2_6
# %bb.1: # %.lr.ph.preheader
cmpl $0, (%rdi)
je .LBB2_2
.LBB2_6: # %._crit_edge
retq
.LBB2_2: # %.lr.ph14.preheader
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_3: # %.lr.ph14
# =>This Inner Loop Header: Depth=1
incq %rcx
cmpq %rax, %rcx
je .LBB2_5
# %bb.4: # %.lr.ph
# in Loop: Header=BB2_3 Depth=1
movl (%rdi,%rcx,4), %edx
leaq (%rcx,%rcx), %rsi
cmpq %rdx, %rsi
je .LBB2_3
.LBB2_5: # %._crit_edge.loopexit
cmpq %rax, %rcx
setae %al
retq
.Lfunc_end2:
.size _Z5checkPii, .Lfunc_end2-_Z5checkPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 16(%rsp), %rdi
movl $16384, %esi # imm = 0x4000
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
je .LBB3_2
# %bb.1:
movl $.Lstr, %edi
callq puts@PLT
.LBB3_2:
movabsq $4294967300, %r14 # imm = 0x100000004
leaq 1020(%r14), %rbx
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3:
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl $4096, 12(%rsp) # imm = 0x1000
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4initPii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_4:
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5:
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl $4096, 12(%rsp) # imm = 0x1000
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12doublevectorPii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6:
callq hipDeviceSynchronize
movq 16(%rsp), %rax
cmpl $0, (%rax)
jne .LBB3_11
# %bb.7: # %.lr.ph.preheader
xorl %ecx, %ecx
xorl %esi, %esi
.p2align 4, 0x90
.LBB3_8: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %rsi, %rdx
cmpq $4095, %rsi # imm = 0xFFF
je .LBB3_10
# %bb.9: # %.lr.ph.i
# in Loop: Header=BB3_8 Depth=1
movl 4(%rax,%rdx,4), %edi
addq $2, %rcx
leaq 1(%rdx), %rsi
cmpq %rdi, %rcx
je .LBB3_8
.LBB3_10: # %_Z5checkPii.exit
cmpq $4094, %rdx # imm = 0xFFE
ja .LBB3_12
.LBB3_11: # %.critedge
movl $.Lstr.1, %edi
callq puts@PLT
.LBB3_12:
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12doublevectorPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4initPii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12doublevectorPii,@object # @_Z12doublevectorPii
.section .rodata,"a",@progbits
.globl _Z12doublevectorPii
.p2align 3, 0x0
_Z12doublevectorPii:
.quad _Z27__device_stub__doublevectorPii
.size _Z12doublevectorPii, 8
.type _Z4initPii,@object # @_Z4initPii
.globl _Z4initPii
.p2align 3, 0x0
_Z4initPii:
.quad _Z19__device_stub__initPii
.size _Z4initPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12doublevectorPii"
.size .L__unnamed_1, 20
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z4initPii"
.size .L__unnamed_2, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "hipMalloc failed"
.size .Lstr, 17
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "test failed"
.size .Lstr.1, 12
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__doublevectorPii
.addrsig_sym _Z19__device_stub__initPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12doublevectorPii
.addrsig_sym _Z4initPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <sys/time.h>
// Comment out this line to enable debug mode
#define NDEBUG
/* time stamp function in milliseconds */
__host__ double getTimeStamp()
{
struct timeval tv;
gettimeofday(&tv, NULL);
return (double)tv.tv_usec / 1000000 + tv.tv_sec;
}
__host__ void initB(float *B, int nB)
{
for (int i = 0; i < nB; i++)
{
int iIndex = i * nB * nB;
for (int j = 0; j < nB; j++)
{
int ijIndex = iIndex + j * nB;
for (int k = 0; k < nB; k++)
{
int ijkIndex = ijIndex + k;
if (i == 0 || j == 0 || k == 0)
{
B[ijkIndex] = 0;
}
else
{
B[ijkIndex] = ((i - 1 + j - 1 + k - 1) % 10) * (float)1.1;
}
}
}
}
}
#define h_getB(B, nB, i, j, k) B[((i) + 1) * nB * nB + ((j) + 1) * nB + ((k) + 1)]
__host__ void jacobiRelaxationReference(float *A, float *B, int n)
{
int nB = n + 1;
for (int i = 0; i < n; i++)
{
int iIndex = i * n * n;
for (int j = 0; j < n; j++)
{
int ijIndex = iIndex + j * n;
for (int k = 0; k < n; k++)
{
int ijkIndex = ijIndex + k;
if (i >= n - 1 || j >= n - 1 || k >= n - 1)
{
A[ijkIndex] = 0.0;
}
else
{
A[ijkIndex] = (float)0.8 * (h_getB(B, nB, i - 1, j, k) +
h_getB(B, nB, i + 1, j, k) +
h_getB(B, nB, i, j - 1, k) +
h_getB(B, nB, i, j + 1, k) +
h_getB(B, nB, i, j, k - 1) +
h_getB(B, nB, i, j, k + 1));
}
}
}
}
}
__host__ int checkA(float *Expected, float *Actual, int n)
{
for (int i = 0; i < n; i++)
{
int iIndex = i * n * n;
for (int j = 0; j < n; j++)
{
int ijIndex = iIndex + j * n;
for (int k = 0; k < n; k++)
{
int ijkIndex = ijIndex + k;
if (Expected[ijkIndex] != Actual[ijkIndex])
{
#ifndef NDEBUG
printf("(i=%d, j=%d, k=%d) Expected=%f Actual=%f\n", i, j, k, Expected[ijkIndex], Actual[ijkIndex]);
#endif
return 0;
}
}
}
}
return 1;
}
__host__ double sumA(float *A, int n)
{
double sum = 0;
for (int i = 0; i < n; i++)
{
int iIndex = i * n * n;
for (int j = 0; j < n; j++)
{
int ijIndex = iIndex + j * n;
for (int k = 0; k < n; k++)
{
int ijkIndex = ijIndex + k;
sum += A[ijkIndex] * (((i + j + k) % 10) ? 1 : -1);
}
}
}
return sum;
}
__global__ void jacobiRelaxation(float *A, float *B, int n, int startingI)
{
extern __shared__ float s_data[];
/* Global Index */
int globalK = blockDim.x * blockIdx.x + threadIdx.x;
int globalJ = blockDim.y * blockIdx.y + threadIdx.y;
int globalI = blockDim.z * blockIdx.z + threadIdx.z + startingI;
int globalIdx = globalI * n * n + globalJ * n + globalK;
int nB = n + 1;
int sizePerGlobalBI = nB * nB;
int sizePerGlobalBJ = nB;
int globalBIIndex = (globalI + 1) * sizePerGlobalBI;
int globalBIJIndex = globalBIIndex + (globalJ + 1) * sizePerGlobalBJ;
int globalBIdx = globalBIJIndex + (globalK + 1);
if (globalK >= n || globalJ >= n || globalI >= n)
{
return;
}
/* Local Index */
// int sizeI = blockDim.z + 2;
int sizeJ = blockDim.y + 2;
int sizeK = blockDim.x + 2;
int sizePerLocalI = sizeJ * sizeK;
int sizePerLocalJ = sizeK;
int localIIndex = (threadIdx.z + 1) * sizePerLocalI;
int localIJIndex = localIIndex + (threadIdx.y + 1) * sizePerLocalJ;
int localIdx = localIJIndex + (threadIdx.x + 1);
s_data[localIdx] = B[globalBIdx];
if (threadIdx.z == 0)
{
s_data[localIdx - sizePerLocalI] = B[globalBIdx - sizePerGlobalBI];
s_data[localIdx + blockDim.z * sizePerLocalI] = B[globalBIdx + blockDim.z * sizePerGlobalBI];
}
if (threadIdx.y == 0)
{
s_data[localIdx - sizePerLocalJ] = B[globalBIdx - sizePerGlobalBJ];
s_data[localIdx + blockDim.y * sizePerLocalJ] = B[globalBIdx + blockDim.y * sizePerGlobalBJ];
}
if (threadIdx.x == 0)
{
s_data[localIdx - 1] = B[globalBIdx - 1];
s_data[localIdx + blockDim.x] = B[globalBIdx + blockDim.x];
}
__syncthreads();
if (globalK == n - 1 || globalJ == n - 1 || globalI == n - 1)
{
A[globalIdx] = 0;
}
else
{
A[globalIdx] = (float)0.8 * (s_data[localIdx - sizePerLocalI] +
s_data[localIdx + sizePerLocalI] +
s_data[localIdx - sizePerLocalJ] +
s_data[localIdx + sizePerLocalJ] +
s_data[localIdx - 1] +
s_data[localIdx + 1]);
}
}
int main(int argc, char *argv[])
{
int error = 0;
/* Get Dimension */
if (argc != 2)
{
printf("Error: The number of arguments is not exactly 1\n");
return 0;
}
int n = atoi(argv[1]);
size_t numElem = n * n * n;
size_t numBytes = numElem * sizeof(float);
int nB = n + 1;
size_t numElemB = nB * nB * nB;
size_t numBytesB = numElemB * sizeof(float);
#ifndef NDEBUG
printf("n=%d, numElem=%ld, numBytes=%ld\n", n, numElem, numBytes);
printf("nB=%d, numElemB=%ld, numBytesB=%ld\n", nB, numElemB, numBytesB);
#endif
/* Allocate Host Memory */
float *h_B = NULL;
error = error || cudaHostAlloc((void **)&h_B, numBytesB, 0);
#ifndef NDEBUG
float *h_hA = (float *)malloc(numBytes);
#endif
float *h_dA = NULL;
error = error || cudaHostAlloc((void **)&h_dA, numBytes, 0);
if (error)
{
printf("Error: cudaHostAlloc returns error\n");
return 0;
}
/* Initialize Host Memory */
initB(h_B, nB);
#ifndef NDEBUG
double timestampPreCpuKernel = getTimeStamp();
jacobiRelaxationReference(h_hA, h_B, n);
double timestampPostCpuKernel = getTimeStamp();
printf("CPU: %lf %ld\n", sumA(h_hA, n), (long)ceil(1000*(timestampPostCpuKernel - timestampPreCpuKernel)));
#endif
/* Allocate Device Memory */
float *d_B = NULL;
error = error || cudaMalloc((void **)&d_B, numBytesB);
float *d_A = NULL;
error = error || cudaMalloc((void **)&d_A, numBytes);
if (error)
{
printf("Error: cudaMalloc returns error\n");
return 0;
}
/* Configuration */
#define NUM_STREAM 2
int nIStreams[NUM_STREAM];
for (int i = 0; i < NUM_STREAM; i++)
{
nIStreams[i] = n / NUM_STREAM;
}
nIStreams[NUM_STREAM - 1] += n % NUM_STREAM;
dim3 d_blockDim;
d_blockDim.x = 32;
d_blockDim.y = 32;
d_blockDim.z = 1; // must be 1
dim3 d_gridDimStreams[NUM_STREAM];
for (int i = 0; i < NUM_STREAM; i++)
{
d_gridDimStreams[i].x = (n - 1) / d_blockDim.x + 1;
d_gridDimStreams[i].y = (n - 1) / d_blockDim.y + 1;
d_gridDimStreams[i].z = (nIStreams[i] - 1) / d_blockDim.z + 1;
}
/* Create NUM_STREAM Streams */
cudaStream_t d_streams[NUM_STREAM];
for (int i = 0; i < NUM_STREAM; i++)
{
error = error || cudaStreamCreate(&d_streams[i]);
}
if (error)
{
printf("Error: cudaStreamCreate returns error\n");
return 0;
}
// TIMER BEGIN
/* Copy Host Memory to Device Memory */
double timestampPreCpuGpuTransfer = getTimeStamp();
size_t numElemBStream1 = 0;
if (NUM_STREAM != 1)
{
numElemBStream1 = (nIStreams[0] + 1 + 1) * nB * nB;
}
else
{
numElemBStream1 = (nIStreams[0] + 1) * nB * nB;
}
error = error || cudaMemcpyAsync(d_B, h_B, numElemBStream1 * sizeof(float), cudaMemcpyHostToDevice, d_streams[0]);
if (NUM_STREAM != 1)
{
cudaStreamSynchronize(d_streams[0]);
}
int numElemBStreams = numElemBStream1;
for (int i = 1; i < NUM_STREAM; i++)
{
int nBIStreami = nIStreams[i];
size_t numElemBStreami = ((i == NUM_STREAM - 1) ? nBIStreami - 1 : nBIStreami) * nB * nB;
error = error || cudaMemcpyAsync(d_B + numElemBStreams, h_B + numElemBStreams, numElemBStreami * sizeof(float), cudaMemcpyHostToDevice, d_streams[i]);
numElemBStreams += numElemBStreami;
if (i != NUM_STREAM - 1)
{
// Synchronize between cudaMemcpyAsync
cudaStreamSynchronize(d_streams[i]);
}
}
if (numElemBStreams != numElemB)
{
printf("Error: cudaMemcpyAsync does not cover entire B (%ld != %ld)\n", numElemBStreams, numElemB);
return 0;
}
if (error)
{
printf("Error: cudaMemcpyAsync B returns error %d\n", error);
return 0;
}
/* Run Kernel */
int d_smemNumElem = (d_blockDim.x + 2) * (d_blockDim.y + 2) * (d_blockDim.z + 2);
size_t d_smemNumBytes = d_smemNumElem * sizeof(float);
size_t d_startingI = 0;
for (int i = 0; i < NUM_STREAM; i++)
{
jacobiRelaxation<<<d_gridDimStreams[i], d_blockDim, d_smemNumBytes, d_streams[i]>>>(d_A, d_B, n, d_startingI);
d_startingI += nIStreams[i];
}
/* Copy Device Memory to Host Memory */
size_t numElemAStreams = 0;
for (int i = 0; i < NUM_STREAM; i++)
{
size_t numElemAStreami = nIStreams[i] * n * n;
error = error || cudaMemcpyAsync(h_dA + numElemAStreams, d_A + numElemAStreams, numElemAStreami * sizeof(float), cudaMemcpyDeviceToHost, d_streams[i]);
numElemAStreams += numElemAStreami;
}
if (numElemAStreams != numElem)
{
printf("Error: cudaMemcpyAsync does not cover entire A\n");
return 0;
}
if (error)
{
printf("Error: cudaMemcpyAsync A returns error %d\n", error);
return 0;
}
/* Synchronize Streams */
for (int i = 0; i < NUM_STREAM; i++)
{
cudaStreamSynchronize(d_streams[i]);
}
double timestampPostGpuCpuTransfer = getTimeStamp();
// TIMER END
/* Free Device Memory */
cudaFree(d_A);
d_A = NULL;
cudaFree(d_B);
d_B = NULL;
/* Output */
double aValue = sumA(h_dA, n);
long totalGpuElapased = (long)ceil(1000*(timestampPostGpuCpuTransfer - timestampPreCpuGpuTransfer));
printf("%lf %ld\n", aValue, totalGpuElapased);
#ifndef NDEBUG
for (int i = 0; i < NUM_STREAM; i++)
{
printf("d_gridDimStream%d=(%d, %d, %d), d_blockDim=(%d, %d, %d), d_smemNumBytes=%ld\n", i, d_gridDimStreams[i].x, d_gridDimStreams[i].y, d_gridDimStreams[i].z, d_blockDim.x, d_blockDim.y, d_blockDim.z, d_smemNumBytes);
}
/* Verify Device Result with Host Result */
error = error || !checkA(h_hA, h_dA, n);
if(error)
{
printf("Error: GPU result does not with CPU result\n");
}
#endif
/* Free Host Memory */
cudaFreeHost(h_dA);
h_dA = NULL;
#ifndef NDEBUG
free(h_hA);
h_hA = NULL;
#endif
cudaFreeHost(h_B);
h_B = NULL;
/* Clean Up Device Resource */
cudaDeviceReset();
} | code for sm_80
Function : _Z16jacobiRelaxationPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R10, SR_TID.X ; /* 0x00000000000a7919 */
/* 0x000e280000002100 */
/*0030*/ S2R R14, SR_CTAID.Z ; /* 0x00000000000e7919 */
/* 0x000e680000002700 */
/*0040*/ S2R R11, SR_TID.Z ; /* 0x00000000000b7919 */
/* 0x000e680000002300 */
/*0050*/ S2R R13, SR_CTAID.Y ; /* 0x00000000000d7919 */
/* 0x000ea80000002600 */
/*0060*/ S2R R12, SR_TID.Y ; /* 0x00000000000c7919 */
/* 0x000ea20000002200 */
/*0070*/ IMAD R0, R3, c[0x0][0x0], R10 ; /* 0x0000000003007a24 */
/* 0x001fe200078e020a */
/*0080*/ HFMA2.MMA R3, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff037435 */
/* 0x000fc800000001ff */
/*0090*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f06270 */
/*00a0*/ IMAD R14, R14, c[0x0][0x8], R11 ; /* 0x000002000e0e7a24 */
/* 0x002fca00078e020b */
/*00b0*/ IADD3 R3, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007ffe0ff */
/*00c0*/ IADD3 R14, R14, c[0x0][0x174], RZ ; /* 0x00005d000e0e7a10 */
/* 0x000fe20007ffe0ff */
/*00d0*/ IMAD R13, R13, c[0x0][0x4], R12 ; /* 0x000001000d0d7a24 */
/* 0x004fc600078e020c */
/*00e0*/ IADD3 R2, R14.reuse, 0x1, RZ ; /* 0x000000010e027810 */
/* 0x040fe40007ffe0ff */
/*00f0*/ ISETP.GE.OR P0, PT, R13.reuse, c[0x0][0x170], P0 ; /* 0x00005c000d007a0c */
/* 0x040fe40000706670 */
/*0100*/ IADD3 R4, R13, 0x1, RZ ; /* 0x000000010d047810 */
/* 0x000fe40007ffe0ff */
/*0110*/ ISETP.GE.OR P0, PT, R14, c[0x0][0x170], P0 ; /* 0x00005c000e007a0c */
/* 0x000fc60000706670 */
/*0120*/ IMAD R4, R3, R2, R4 ; /* 0x0000000203047224 */
/* 0x000fd400078e0204 */
/*0130*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0140*/ ISETP.NE.AND P3, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003f65270 */
/*0150*/ IMAD R4, R3.reuse, R4, R0 ; /* 0x0000000403047224 */
/* 0x040fe200078e0200 */
/*0160*/ ISETP.NE.AND P2, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f45270 */
/*0170*/ IMAD R2, R3, R3, RZ ; /* 0x0000000303027224 */
/* 0x000fe200078e02ff */
/*0180*/ ISETP.NE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f25270 */
/*0190*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*01a0*/ IADD3 R6, R4, 0x1, RZ ; /* 0x0000000104067810 */
/* 0x000fe40007ffe0ff */
/*01b0*/ MOV R15, 0x4 ; /* 0x00000004000f7802 */
/* 0x000fca0000000f00 */
/*01c0*/ @!P3 IADD3 R20, -R2.reuse, R6.reuse, RZ ; /* 0x000000060214b210 */
/* 0x0c0fe20007ffe1ff */
/*01d0*/ @!P3 IMAD R18, R2, c[0x0][0x8], R6.reuse ; /* 0x000002000212ba24 */
/* 0x100fe200078e0206 */
/*01e0*/ @!P2 IADD3 R8, -R3.reuse, R6, RZ ; /* 0x000000060308a210 */
/* 0x040fe20007ffe1ff */
/*01f0*/ @!P2 IMAD R2, R3, c[0x0][0x4], R6 ; /* 0x000001000302aa24 */
/* 0x000fe200078e0206 */
/*0200*/ @!P1 IADD3 R22, R6.reuse, c[0x0][0x0], RZ ; /* 0x0000000006169a10 */
/* 0x040fe20007ffe0ff */
/*0210*/ IMAD.WIDE R4, R6, R15, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e020f */
/*0220*/ @!P3 IMAD.WIDE R20, R20, R15.reuse, c[0x0][0x168] ; /* 0x00005a001414b625 */
/* 0x080fe200078e020f */
/*0230*/ LDG.E R16, [R4.64] ; /* 0x0000000604107981 */
/* 0x0000a6000c1e1900 */
/*0240*/ @!P3 IMAD.WIDE.U32 R18, R18, R15.reuse, c[0x0][0x168] ; /* 0x00005a001212b625 */
/* 0x080fe200078e000f */
/*0250*/ @!P3 LDG.E R17, [R20.64] ; /* 0x000000061411b981 */
/* 0x0002e6000c1e1900 */
/*0260*/ @!P2 IMAD.WIDE R8, R8, R15.reuse, c[0x0][0x168] ; /* 0x00005a000808a625 */
/* 0x080fe400078e020f */
/*0270*/ @!P3 LDG.E R18, [R18.64] ; /* 0x000000061212b981 */
/* 0x000964000c1e1900 */
/*0280*/ @!P2 IMAD.WIDE.U32 R6, R2, R15, c[0x0][0x168] ; /* 0x00005a000206a625 */
/* 0x000fc400078e000f */
/*0290*/ @!P2 LDG.E R8, [R8.64] ; /* 0x000000060808a981 */
/* 0x000164000c1e1900 */
/*02a0*/ @!P1 IMAD.WIDE.U32 R2, R22, R15, c[0x0][0x168] ; /* 0x00005a0016029625 */
/* 0x000fe400078e000f */
/*02b0*/ @!P2 LDG.E R6, [R6.64] ; /* 0x000000060606a981 */
/* 0x000168000c1e1900 */
/*02c0*/ @!P1 LDG.E R22, [R4.64+-0x4] ; /* 0xfffffc0604169981 */
/* 0x000168000c1e1900 */
/*02d0*/ @!P1 LDG.E R2, [R2.64] ; /* 0x0000000602029981 */
/* 0x000162000c1e1900 */
/*02e0*/ IMAD.MOV.U32 R25, RZ, RZ, 0x2 ; /* 0x00000002ff197424 */
/* 0x000fe200078e00ff */
/*02f0*/ IADD3 R24, R11, 0x1, RZ ; /* 0x000000010b187810 */
/* 0x000fc40007ffe0ff */
/*0300*/ IADD3 R23, R12, 0x1, RZ ; /* 0x000000010c177810 */
/* 0x000fe40007ffe0ff */
/*0310*/ IADD3 R11, R25.reuse, c[0x0][0x4], RZ ; /* 0x00000100190b7a10 */
/* 0x040fe20007ffe0ff */
/*0320*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe20000000000 */
/*0330*/ IADD3 R12, R25, c[0x0][0x0], RZ ; /* 0x00000000190c7a10 */
/* 0x000fe20007ffe0ff */
/*0340*/ ULDC UR5, c[0x0][0x170] ; /* 0x00005c0000057ab9 */
/* 0x000fe40000000800 */
/*0350*/ IMAD R23, R11, R24, R23 ; /* 0x000000180b177224 */
/* 0x000fe200078e0217 */
/*0360*/ UIADD3 UR4, -UR4, UR5, URZ ; /* 0x0000000504047290 */
/* 0x000fc6000fffe13f */
/*0370*/ IMAD R7, R12, R23, RZ ; /* 0x000000170c077224 */
/* 0x001fe400078e02ff */
/*0380*/ IMAD R5, R14, c[0x0][0x170], R13 ; /* 0x00005c000e057a24 */
/* 0x000fe200078e020d */
/*0390*/ ISETP.NE.AND P0, PT, R13, UR4, PT ; /* 0x000000040d007c0c */
/* 0x000fe2000bf05270 */
/*03a0*/ IMAD R11, R11, R12, RZ ; /* 0x0000000c0b0b7224 */
/* 0x000fe200078e02ff */
/*03b0*/ IADD3 R3, R7, R10, RZ ; /* 0x0000000a07037210 */
/* 0x000fe20007ffe0ff */
/*03c0*/ IMAD R4, R5, c[0x0][0x170], R0 ; /* 0x00005c0005047a24 */
/* 0x000fe200078e0200 */
/*03d0*/ ISETP.EQ.OR P0, PT, R0, UR4, !P0 ; /* 0x0000000400007c0c */
/* 0x000fe2000c702670 */
/*03e0*/ @!P3 IMAD R5, R11, c[0x0][0x8], RZ ; /* 0x000002000b05ba24 */
/* 0x000fe200078e02ff */
/*03f0*/ IADD3 R0, R3.reuse, 0x1, RZ ; /* 0x0000000103007810 */
/* 0x040fe40007ffe0ff */
/*0400*/ SHF.L.U32 R10, R3, 0x2, RZ ; /* 0x00000002030a7819 */
/* 0x000fe200000006ff */
/*0410*/ @!P2 IMAD R19, R12, c[0x0][0x4], RZ ; /* 0x000001000c13aa24 */
/* 0x010fe200078e02ff */
/*0420*/ ISETP.EQ.OR P0, PT, R14, UR4, P0 ; /* 0x000000040e007c0c */
/* 0x000fc40008702670 */
/*0430*/ IADD3 R14, -R11, R0.reuse, RZ ; /* 0x000000000b0e7210 */
/* 0x080fe20007ffe1ff */
/*0440*/ @!P3 IMAD R9, R5, 0x4, R10.reuse ; /* 0x000000040509b824 */
/* 0x100fe200078e020a */
/*0450*/ IADD3 R13, -R12, R0, RZ ; /* 0x000000000c0d7210 */
/* 0x000fe40007ffe1ff */
/*0460*/ @!P2 LEA R19, R19, R10, 0x2 ; /* 0x0000000a1313a211 */
/* 0x000fe200078e10ff */
/*0470*/ IMAD R21, R15, c[0x0][0x0], R10 ; /* 0x000000000f157a24 */
/* 0x002fe400078e020a */
/*0480*/ IMAD.WIDE R4, R4, R15, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe200078e020f */
/*0490*/ STS [R3.X4+0x4], R16 ; /* 0x0000041003007388 */
/* 0x0041e80000004800 */
/*04a0*/ @!P3 STS [R14.X4], R17 ; /* 0x000000110e00b388 */
/* 0x0081e80000004800 */
/*04b0*/ @!P3 STS [R9+0x4], R18 ; /* 0x000004120900b388 */
/* 0x0201e80000000800 */
/*04c0*/ @!P2 STS [R13.X4], R8 ; /* 0x000000080d00a388 */
/* 0x0001e80000004800 */
/*04d0*/ @!P2 STS [R19+0x4], R6 ; /* 0x000004061300a388 */
/* 0x0001e80000000800 */
/*04e0*/ @!P1 STS [R7.X4], R22 ; /* 0x0000001607009388 */
/* 0x0001e80000004800 */
/*04f0*/ @!P1 STS [R21+0x4], R2 ; /* 0x0000040215009388 */
/* 0x0001e80000000800 */
/*0500*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0510*/ @P0 BRA 0x610 ; /* 0x000000f000000947 */
/* 0x000fea0003800000 */
/*0520*/ LEA R10, R11, R10, 0x2 ; /* 0x0000000a0b0a7211 */
/* 0x001fe200078e10ff */
/*0530*/ LDS R14, [R14.X4] ; /* 0x000000000e0e7984 */
/* 0x000fe80000004800 */
/*0540*/ LDS R7, [R10+0x4] ; /* 0x000004000a077984 */
/* 0x000e280000000800 */
/*0550*/ LDS R0, [R13.X4] ; /* 0x000000000d007984 */
/* 0x000e680000004800 */
/*0560*/ LDS R21, [R21+0xc] ; /* 0x00000c0015157984 */
/* 0x000ea80000000800 */
/*0570*/ LDS R9, [R3.X4] ; /* 0x0000000003097984 */
/* 0x000ee80000004800 */
/*0580*/ LDS R11, [R3.X4+0x8] ; /* 0x00000800030b7984 */
/* 0x000f220000004800 */
/*0590*/ FADD R7, R14, R7 ; /* 0x000000070e077221 */
/* 0x001fc80000000000 */
/*05a0*/ FADD R0, R7, R0 ; /* 0x0000000007007221 */
/* 0x002fc80000000000 */
/*05b0*/ FADD R0, R0, R21 ; /* 0x0000001500007221 */
/* 0x004fc80000000000 */
/*05c0*/ FADD R0, R0, R9 ; /* 0x0000000900007221 */
/* 0x008fc80000000000 */
/*05d0*/ FADD R0, R0, R11 ; /* 0x0000000b00007221 */
/* 0x010fc80000000000 */
/*05e0*/ FMUL R7, R0, 0.80000001192092895508 ; /* 0x3f4ccccd00077820 */
/* 0x000fca0000400000 */
/*05f0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101906 */
/*0600*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0610*/ STG.E [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x001fe2000c101906 */
/*0620*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0630*/ BRA 0x630; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <sys/time.h>
// Comment out this line to enable debug mode
#define NDEBUG
/* time stamp function in milliseconds */
__host__ double getTimeStamp()
{
struct timeval tv;
gettimeofday(&tv, NULL);
return (double)tv.tv_usec / 1000000 + tv.tv_sec;
}
__host__ void initB(float *B, int nB)
{
for (int i = 0; i < nB; i++)
{
int iIndex = i * nB * nB;
for (int j = 0; j < nB; j++)
{
int ijIndex = iIndex + j * nB;
for (int k = 0; k < nB; k++)
{
int ijkIndex = ijIndex + k;
if (i == 0 || j == 0 || k == 0)
{
B[ijkIndex] = 0;
}
else
{
B[ijkIndex] = ((i - 1 + j - 1 + k - 1) % 10) * (float)1.1;
}
}
}
}
}
#define h_getB(B, nB, i, j, k) B[((i) + 1) * nB * nB + ((j) + 1) * nB + ((k) + 1)]
__host__ void jacobiRelaxationReference(float *A, float *B, int n)
{
int nB = n + 1;
for (int i = 0; i < n; i++)
{
int iIndex = i * n * n;
for (int j = 0; j < n; j++)
{
int ijIndex = iIndex + j * n;
for (int k = 0; k < n; k++)
{
int ijkIndex = ijIndex + k;
if (i >= n - 1 || j >= n - 1 || k >= n - 1)
{
A[ijkIndex] = 0.0;
}
else
{
A[ijkIndex] = (float)0.8 * (h_getB(B, nB, i - 1, j, k) +
h_getB(B, nB, i + 1, j, k) +
h_getB(B, nB, i, j - 1, k) +
h_getB(B, nB, i, j + 1, k) +
h_getB(B, nB, i, j, k - 1) +
h_getB(B, nB, i, j, k + 1));
}
}
}
}
}
__host__ int checkA(float *Expected, float *Actual, int n)
{
for (int i = 0; i < n; i++)
{
int iIndex = i * n * n;
for (int j = 0; j < n; j++)
{
int ijIndex = iIndex + j * n;
for (int k = 0; k < n; k++)
{
int ijkIndex = ijIndex + k;
if (Expected[ijkIndex] != Actual[ijkIndex])
{
#ifndef NDEBUG
printf("(i=%d, j=%d, k=%d) Expected=%f Actual=%f\n", i, j, k, Expected[ijkIndex], Actual[ijkIndex]);
#endif
return 0;
}
}
}
}
return 1;
}
__host__ double sumA(float *A, int n)
{
double sum = 0;
for (int i = 0; i < n; i++)
{
int iIndex = i * n * n;
for (int j = 0; j < n; j++)
{
int ijIndex = iIndex + j * n;
for (int k = 0; k < n; k++)
{
int ijkIndex = ijIndex + k;
sum += A[ijkIndex] * (((i + j + k) % 10) ? 1 : -1);
}
}
}
return sum;
}
__global__ void jacobiRelaxation(float *A, float *B, int n, int startingI)
{
extern __shared__ float s_data[];
/* Global Index */
int globalK = blockDim.x * blockIdx.x + threadIdx.x;
int globalJ = blockDim.y * blockIdx.y + threadIdx.y;
int globalI = blockDim.z * blockIdx.z + threadIdx.z + startingI;
int globalIdx = globalI * n * n + globalJ * n + globalK;
int nB = n + 1;
int sizePerGlobalBI = nB * nB;
int sizePerGlobalBJ = nB;
int globalBIIndex = (globalI + 1) * sizePerGlobalBI;
int globalBIJIndex = globalBIIndex + (globalJ + 1) * sizePerGlobalBJ;
int globalBIdx = globalBIJIndex + (globalK + 1);
if (globalK >= n || globalJ >= n || globalI >= n)
{
return;
}
/* Local Index */
// int sizeI = blockDim.z + 2;
int sizeJ = blockDim.y + 2;
int sizeK = blockDim.x + 2;
int sizePerLocalI = sizeJ * sizeK;
int sizePerLocalJ = sizeK;
int localIIndex = (threadIdx.z + 1) * sizePerLocalI;
int localIJIndex = localIIndex + (threadIdx.y + 1) * sizePerLocalJ;
int localIdx = localIJIndex + (threadIdx.x + 1);
s_data[localIdx] = B[globalBIdx];
if (threadIdx.z == 0)
{
s_data[localIdx - sizePerLocalI] = B[globalBIdx - sizePerGlobalBI];
s_data[localIdx + blockDim.z * sizePerLocalI] = B[globalBIdx + blockDim.z * sizePerGlobalBI];
}
if (threadIdx.y == 0)
{
s_data[localIdx - sizePerLocalJ] = B[globalBIdx - sizePerGlobalBJ];
s_data[localIdx + blockDim.y * sizePerLocalJ] = B[globalBIdx + blockDim.y * sizePerGlobalBJ];
}
if (threadIdx.x == 0)
{
s_data[localIdx - 1] = B[globalBIdx - 1];
s_data[localIdx + blockDim.x] = B[globalBIdx + blockDim.x];
}
__syncthreads();
if (globalK == n - 1 || globalJ == n - 1 || globalI == n - 1)
{
A[globalIdx] = 0;
}
else
{
A[globalIdx] = (float)0.8 * (s_data[localIdx - sizePerLocalI] +
s_data[localIdx + sizePerLocalI] +
s_data[localIdx - sizePerLocalJ] +
s_data[localIdx + sizePerLocalJ] +
s_data[localIdx - 1] +
s_data[localIdx + 1]);
}
}
int main(int argc, char *argv[])
{
int error = 0;
/* Get Dimension */
if (argc != 2)
{
printf("Error: The number of arguments is not exactly 1\n");
return 0;
}
int n = atoi(argv[1]);
size_t numElem = n * n * n;
size_t numBytes = numElem * sizeof(float);
int nB = n + 1;
size_t numElemB = nB * nB * nB;
size_t numBytesB = numElemB * sizeof(float);
#ifndef NDEBUG
printf("n=%d, numElem=%ld, numBytes=%ld\n", n, numElem, numBytes);
printf("nB=%d, numElemB=%ld, numBytesB=%ld\n", nB, numElemB, numBytesB);
#endif
/* Allocate Host Memory */
float *h_B = NULL;
error = error || cudaHostAlloc((void **)&h_B, numBytesB, 0);
#ifndef NDEBUG
float *h_hA = (float *)malloc(numBytes);
#endif
float *h_dA = NULL;
error = error || cudaHostAlloc((void **)&h_dA, numBytes, 0);
if (error)
{
printf("Error: cudaHostAlloc returns error\n");
return 0;
}
/* Initialize Host Memory */
initB(h_B, nB);
#ifndef NDEBUG
double timestampPreCpuKernel = getTimeStamp();
jacobiRelaxationReference(h_hA, h_B, n);
double timestampPostCpuKernel = getTimeStamp();
printf("CPU: %lf %ld\n", sumA(h_hA, n), (long)ceil(1000*(timestampPostCpuKernel - timestampPreCpuKernel)));
#endif
/* Allocate Device Memory */
float *d_B = NULL;
error = error || cudaMalloc((void **)&d_B, numBytesB);
float *d_A = NULL;
error = error || cudaMalloc((void **)&d_A, numBytes);
if (error)
{
printf("Error: cudaMalloc returns error\n");
return 0;
}
/* Configuration */
#define NUM_STREAM 2
int nIStreams[NUM_STREAM];
for (int i = 0; i < NUM_STREAM; i++)
{
nIStreams[i] = n / NUM_STREAM;
}
nIStreams[NUM_STREAM - 1] += n % NUM_STREAM;
dim3 d_blockDim;
d_blockDim.x = 32;
d_blockDim.y = 32;
d_blockDim.z = 1; // must be 1
dim3 d_gridDimStreams[NUM_STREAM];
for (int i = 0; i < NUM_STREAM; i++)
{
d_gridDimStreams[i].x = (n - 1) / d_blockDim.x + 1;
d_gridDimStreams[i].y = (n - 1) / d_blockDim.y + 1;
d_gridDimStreams[i].z = (nIStreams[i] - 1) / d_blockDim.z + 1;
}
/* Create NUM_STREAM Streams */
cudaStream_t d_streams[NUM_STREAM];
for (int i = 0; i < NUM_STREAM; i++)
{
error = error || cudaStreamCreate(&d_streams[i]);
}
if (error)
{
printf("Error: cudaStreamCreate returns error\n");
return 0;
}
// TIMER BEGIN
/* Copy Host Memory to Device Memory */
double timestampPreCpuGpuTransfer = getTimeStamp();
size_t numElemBStream1 = 0;
if (NUM_STREAM != 1)
{
numElemBStream1 = (nIStreams[0] + 1 + 1) * nB * nB;
}
else
{
numElemBStream1 = (nIStreams[0] + 1) * nB * nB;
}
error = error || cudaMemcpyAsync(d_B, h_B, numElemBStream1 * sizeof(float), cudaMemcpyHostToDevice, d_streams[0]);
if (NUM_STREAM != 1)
{
cudaStreamSynchronize(d_streams[0]);
}
int numElemBStreams = numElemBStream1;
for (int i = 1; i < NUM_STREAM; i++)
{
int nBIStreami = nIStreams[i];
size_t numElemBStreami = ((i == NUM_STREAM - 1) ? nBIStreami - 1 : nBIStreami) * nB * nB;
error = error || cudaMemcpyAsync(d_B + numElemBStreams, h_B + numElemBStreams, numElemBStreami * sizeof(float), cudaMemcpyHostToDevice, d_streams[i]);
numElemBStreams += numElemBStreami;
if (i != NUM_STREAM - 1)
{
// Synchronize between cudaMemcpyAsync
cudaStreamSynchronize(d_streams[i]);
}
}
if (numElemBStreams != numElemB)
{
printf("Error: cudaMemcpyAsync does not cover entire B (%ld != %ld)\n", numElemBStreams, numElemB);
return 0;
}
if (error)
{
printf("Error: cudaMemcpyAsync B returns error %d\n", error);
return 0;
}
/* Run Kernel */
int d_smemNumElem = (d_blockDim.x + 2) * (d_blockDim.y + 2) * (d_blockDim.z + 2);
size_t d_smemNumBytes = d_smemNumElem * sizeof(float);
size_t d_startingI = 0;
for (int i = 0; i < NUM_STREAM; i++)
{
jacobiRelaxation<<<d_gridDimStreams[i], d_blockDim, d_smemNumBytes, d_streams[i]>>>(d_A, d_B, n, d_startingI);
d_startingI += nIStreams[i];
}
/* Copy Device Memory to Host Memory */
size_t numElemAStreams = 0;
for (int i = 0; i < NUM_STREAM; i++)
{
size_t numElemAStreami = nIStreams[i] * n * n;
error = error || cudaMemcpyAsync(h_dA + numElemAStreams, d_A + numElemAStreams, numElemAStreami * sizeof(float), cudaMemcpyDeviceToHost, d_streams[i]);
numElemAStreams += numElemAStreami;
}
if (numElemAStreams != numElem)
{
printf("Error: cudaMemcpyAsync does not cover entire A\n");
return 0;
}
if (error)
{
printf("Error: cudaMemcpyAsync A returns error %d\n", error);
return 0;
}
/* Synchronize Streams */
for (int i = 0; i < NUM_STREAM; i++)
{
cudaStreamSynchronize(d_streams[i]);
}
double timestampPostGpuCpuTransfer = getTimeStamp();
// TIMER END
/* Free Device Memory */
cudaFree(d_A);
d_A = NULL;
cudaFree(d_B);
d_B = NULL;
/* Output */
double aValue = sumA(h_dA, n);
long totalGpuElapased = (long)ceil(1000*(timestampPostGpuCpuTransfer - timestampPreCpuGpuTransfer));
printf("%lf %ld\n", aValue, totalGpuElapased);
#ifndef NDEBUG
for (int i = 0; i < NUM_STREAM; i++)
{
printf("d_gridDimStream%d=(%d, %d, %d), d_blockDim=(%d, %d, %d), d_smemNumBytes=%ld\n", i, d_gridDimStreams[i].x, d_gridDimStreams[i].y, d_gridDimStreams[i].z, d_blockDim.x, d_blockDim.y, d_blockDim.z, d_smemNumBytes);
}
/* Verify Device Result with Host Result */
error = error || !checkA(h_hA, h_dA, n);
if(error)
{
printf("Error: GPU result does not with CPU result\n");
}
#endif
/* Free Host Memory */
cudaFreeHost(h_dA);
h_dA = NULL;
#ifndef NDEBUG
free(h_hA);
h_hA = NULL;
#endif
cudaFreeHost(h_B);
h_B = NULL;
/* Clean Up Device Resource */
cudaDeviceReset();
} | .file "tmpxft_00084f7d_00000000-6_1001721498.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12getTimeStampv
.type _Z12getTimeStampv, @function
_Z12getTimeStampv:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
divsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z12getTimeStampv, .-_Z12getTimeStampv
.globl _Z5initBPfi
.type _Z5initBPfi, @function
_Z5initBPfi:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L20
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rdi, %rbp
movl %esi, %r11d
movl %esi, %r12d
imull %esi, %r12d
movslq %r12d, %r12
salq $2, %r12
movslq %esi, %r8
leaq 0(,%r8,4), %rbx
movl $0, %edi
movl $0, %r13d
movss .LC2(%rip), %xmm1
jmp .L14
.L17:
movl $0x00000000, (%rsi,%rax,4)
.L11:
addq $1, %rax
cmpq %r8, %rax
je .L23
.L12:
testl %edi, %edi
sete %dl
testl %ecx, %ecx
sete %r14b
orb %r14b, %dl
jne .L17
testl %eax, %eax
je .L17
leal (%r9,%rax), %r14d
movslq %r14d, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %r14d, %r15d
sarl $31, %r15d
subl %r15d, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %r14d
pxor %xmm0, %xmm0
cvtsi2ssl %r14d, %xmm0
mulss %xmm1, %xmm0
movss %xmm0, (%rsi,%rax,4)
jmp .L11
.L23:
leal 1(%rcx), %eax
addq %rbx, %rsi
addl $1, %r10d
cmpl %eax, %r11d
je .L24
movl %eax, %ecx
.L13:
movl $0, %eax
leal -3(%r10), %r9d
jmp .L12
.L24:
leal 1(%rdi), %eax
addq %r12, %rbp
cmpl %ecx, %edi
je .L25
movl %eax, %edi
.L14:
movl %edi, %r10d
movq %rbp, %rsi
movl %r13d, %ecx
jmp .L13
.L25:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2058:
.size _Z5initBPfi, .-_Z5initBPfi
.globl _Z25jacobiRelaxationReferencePfS_i
.type _Z25jacobiRelaxationReferencePfS_i, @function
_Z25jacobiRelaxationReferencePfS_i:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rdi, %rax
movl %edx, -24(%rsp)
leal 1(%rdx), %edi
movl %edi, -40(%rsp)
testl %edx, %edx
jle .L26
movl %edx, %ebx
imull %edx, %edx
movslq %edx, %rdx
leaq 0(,%rdx,4), %r12
movq %rax, %r8
movl %edi, %ebp
imull %edi, %ebp
leal (%rdi,%rbp,2), %ecx
movl %ebx, %eax
imull %edi, %ebx
movl %ebx, -56(%rsp)
movl %eax, %ebx
movslq %eax, %r10
leaq 0(,%r10,4), %rax
movq %rax, -48(%rsp)
leal (%rdi,%rdi), %eax
movl %eax, -36(%rsp)
movl %edi, %eax
movl $0, %r9d
leal -1(%rbx), %r15d
movss .LC3(%rip), %xmm1
movq %r12, -8(%rsp)
jmp .L32
.L28:
leal 0(%r13,%rax), %r9d
movslq %r9d, %r9
leal (%r12,%rax), %r8d
movslq %r8d, %r8
movss (%rsi,%r9,4), %xmm0
addss (%rsi,%r8,4), %xmm0
leal 0(%rbp,%rax), %r8d
movslq %r8d, %r8
addss (%rsi,%r8,4), %xmm0
leal (%rbx,%rax), %r8d
movslq %r8d, %r8
addss (%rsi,%r8,4), %xmm0
movslq %edx, %r8
addss (%rsi,%r8,4), %xmm0
leal 2(%rdx), %r8d
movslq %r8d, %r8
addss (%rsi,%r8,4), %xmm0
mulss %xmm1, %xmm0
movss %xmm0, (%rdi,%rax,4)
.L29:
addq $1, %rax
addl $1, %edx
cmpq %r10, %rax
je .L37
.L30:
movl %eax, %r8d
cmpl %eax, %ecx
cmovge %ecx, %r8d
cmpl %r8d, %r15d
jg .L28
movl $0x00000000, (%rdi,%rax,4)
jmp .L29
.L37:
movl -60(%rsp), %r9d
leal 1(%r14), %eax
movq -48(%rsp), %rbx
addq %rbx, %rdi
cmpl %eax, -24(%rsp)
je .L38
movl %eax, %r14d
.L31:
movl %r11d, %r13d
movl -56(%rsp), %eax
subl %eax, %r13d
movl -52(%rsp), %eax
leal (%rax,%r11), %r12d
movl -36(%rsp), %eax
leal (%r11,%rax), %ebx
movl %r11d, %ebp
movl -40(%rsp), %eax
addl %eax, %r11d
movl %r11d, %edx
movl $0, %eax
cmpl %r14d, %r9d
movl %r14d, %ecx
cmovge %r9d, %ecx
addl $1, %r13d
addl $1, %r12d
addl $1, %ebp
addl $1, %ebx
movl %r9d, -60(%rsp)
jmp .L30
.L38:
movq -32(%rsp), %r8
movl -20(%rsp), %eax
movl -16(%rsp), %ebp
movl -12(%rsp), %ecx
leal 1(%r9), %edx
movq -8(%rsp), %rbx
addq %rbx, %r8
addl %ebp, %eax
addl %ebp, %ecx
cmpl %r14d, %r9d
je .L26
movl %edx, %r9d
.L32:
movl -56(%rsp), %ebx
leal (%rax,%rbx), %edx
movl %edx, %r11d
movq %r8, %rdi
movl $0, %r14d
movl %ecx, %ebx
subl %edx, %ebx
movl %ebx, -52(%rsp)
movq %r8, -32(%rsp)
movl %eax, -20(%rsp)
movl %ebp, -16(%rsp)
movl %ecx, -12(%rsp)
jmp .L31
.L26:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z25jacobiRelaxationReferencePfS_i, .-_Z25jacobiRelaxationReferencePfS_i
.globl _Z6checkAPfS_i
.type _Z6checkAPfS_i, @function
_Z6checkAPfS_i:
.LFB2060:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L45
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rcx
movl %edx, %edi
movl %edx, %eax
imull %edx, %eax
cltq
leaq 0(,%rax,4), %r9
movslq %edx, %r8
leaq 0(,%r8,4), %r11
negq %r8
salq $2, %r8
movq %r11, %rbx
movl $0, %r12d
movl $0, %ebp
.L44:
movq %rbx, %rdx
movl %ebp, %r10d
.L43:
leaq (%rdx,%r8), %rax
.L42:
movss (%rcx,%rax), %xmm0
ucomiss (%rsi,%rax), %xmm0
jp .L46
jne .L46
addq $4, %rax
cmpq %rdx, %rax
jne .L42
leal 1(%r10), %eax
addq %r11, %rdx
cmpl %eax, %edi
je .L55
movl %eax, %r10d
jmp .L43
.L55:
leal 1(%r12), %eax
addq %r9, %rbx
cmpl %r10d, %r12d
je .L56
movl %eax, %r12d
jmp .L44
.L56:
movl $1, %eax
jmp .L39
.L45:
.cfi_def_cfa_offset 8
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
movl $1, %eax
ret
.L46:
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
.cfi_offset 6, -24
.cfi_offset 12, -16
movl $0, %eax
.L39:
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z6checkAPfS_i, .-_Z6checkAPfS_i
.globl _Z4sumAPfi
.type _Z4sumAPfi, @function
_Z4sumAPfi:
.LFB2061:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L63
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
movq %rdi, %rbx
movl %esi, %ebp
leal (%rsi,%rsi), %r9d
movl %esi, %r12d
imull %esi, %r12d
movslq %r12d, %r12
salq $2, %r12
movslq %esi, %r10
salq $2, %r10
movl $0, %r11d
pxor %xmm2, %xmm2
movss .LC6(%rip), %xmm3
movss .LC5(%rip), %xmm4
jmp .L62
.L59:
mulss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
addsd %xmm0, %xmm2
addq $4, %rcx
addl $1, %edx
cmpl %esi, %edx
je .L72
.L60:
movss (%rcx), %xmm0
movslq %edx, %rax
imulq $1717986919, %rax, %rax
sarq $34, %rax
movl %edx, %r13d
sarl $31, %r13d
subl %r13d, %eax
leal (%rax,%rax,4), %eax
addl %eax, %eax
movaps %xmm3, %xmm1
cmpl %eax, %edx
je .L59
movaps %xmm4, %xmm1
jmp .L59
.L72:
addl $1, %esi
addq %r10, %rdi
addl $1, %r8d
cmpl %r9d, %esi
je .L73
.L61:
movl %r8d, %edx
movq %rdi, %rcx
jmp .L60
.L73:
addl $1, %r11d
addl $1, %r9d
addq %r12, %rbx
cmpl %r11d, %ebp
je .L74
.L62:
movl %r11d, %r8d
leal 0(%rbp,%r11), %esi
movq %rbx, %rdi
jmp .L61
.L63:
.cfi_def_cfa_offset 8
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
pxor %xmm2, %xmm2
movapd %xmm2, %xmm0
ret
.L74:
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
.cfi_offset 6, -32
.cfi_offset 12, -24
.cfi_offset 13, -16
movapd %xmm2, %xmm0
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z4sumAPfi, .-_Z4sumAPfi
.globl _Z40__device_stub__Z16jacobiRelaxationPfS_iiPfS_ii
.type _Z40__device_stub__Z16jacobiRelaxationPfS_iiPfS_ii, @function
_Z40__device_stub__Z16jacobiRelaxationPfS_iiPfS_ii:
.LFB2087:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L79
.L75:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L80
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L79:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16jacobiRelaxationPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L75
.L80:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z40__device_stub__Z16jacobiRelaxationPfS_iiPfS_ii, .-_Z40__device_stub__Z16jacobiRelaxationPfS_iiPfS_ii
.globl _Z16jacobiRelaxationPfS_ii
.type _Z16jacobiRelaxationPfS_ii, @function
_Z16jacobiRelaxationPfS_ii:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z16jacobiRelaxationPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z16jacobiRelaxationPfS_ii, .-_Z16jacobiRelaxationPfS_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "Error: The number of arguments is not exactly 1\n"
.align 8
.LC8:
.string "Error: cudaHostAlloc returns error\n"
.align 8
.LC9:
.string "Error: cudaMalloc returns error\n"
.align 8
.LC10:
.string "Error: cudaStreamCreate returns error\n"
.align 8
.LC11:
.string "Error: cudaMemcpyAsync does not cover entire B (%ld != %ld)\n"
.align 8
.LC12:
.string "Error: cudaMemcpyAsync B returns error %d\n"
.align 8
.LC13:
.string "Error: cudaMemcpyAsync does not cover entire A\n"
.align 8
.LC14:
.string "Error: cudaMemcpyAsync A returns error %d\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC16:
.string "%lf %ld\n"
.text
.globl main
.type main, @function
main:
.LFB2062:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $168, %rsp
.cfi_def_cfa_offset 224
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
cmpl $2, %edi
je .L84
leaq .LC7(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
.L85:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L114
movl $0, %eax
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L84:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, 8(%rsp)
leal 1(%rax), %ebp
movl %ebp, %r12d
imull %ebp, %r12d
imull %ebp, %r12d
movslq %r12d, %r15
leaq 0(,%r15,4), %r14
movq $0, 56(%rsp)
leaq 56(%rsp), %rdi
movl $0, %edx
movq %r14, %rsi
call cudaHostAlloc@PLT
testl %eax, %eax
je .L86
movq $0, 64(%rsp)
.L87:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L85
.L86:
movl %ebx, %r13d
imull %ebx, %r13d
imull %ebx, %r13d
movslq %r13d, %r13
leaq 0(,%r13,4), %rax
movq %rax, 16(%rsp)
movq $0, 64(%rsp)
leaq 64(%rsp), %rdi
movl $0, %edx
movq %rax, %rsi
call cudaHostAlloc@PLT
testl %eax, %eax
jne .L87
movl %ebp, %esi
movq 56(%rsp), %rdi
call _Z5initBPfi
movq $0, 72(%rsp)
leaq 72(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
testl %eax, %eax
je .L115
movq $0, 80(%rsp)
.L90:
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L85
.L115:
movq $0, 80(%rsp)
leaq 80(%rsp), %rdi
movq 16(%rsp), %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L90
movl $2, %ecx
movl 8(%rsp), %eax
cltd
idivl %ecx
movl %eax, %r14d
movl %eax, 104(%rsp)
leal (%rdx,%rax), %ecx
movl %ecx, 16(%rsp)
movl %ecx, 108(%rsp)
subl $1, %ebx
shrl $5, %ebx
leal 1(%rbx), %eax
movl %eax, 128(%rsp)
movl %eax, 132(%rsp)
movl %r14d, 136(%rsp)
movl %eax, 140(%rsp)
movl %eax, 144(%rsp)
movl %ecx, 148(%rsp)
leaq 112(%rsp), %rdi
call cudaStreamCreate@PLT
testl %eax, %eax
je .L116
.L92:
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L85
.L116:
leaq 120(%rsp), %rdi
call cudaStreamCreate@PLT
testl %eax, %eax
jne .L92
call _Z12getTimeStampv
movsd %xmm0, 40(%rsp)
addl $2, %r14d
imull %ebp, %r14d
imull %ebp, %r14d
movslq %r14d, %rax
salq $2, %rax
movq %rax, 32(%rsp)
movq 112(%rsp), %r8
movl $1, %ecx
movq %rax, %rdx
movq 56(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpyAsync@PLT
movl %eax, 28(%rsp)
movq 112(%rsp), %rdi
call cudaStreamSynchronize@PLT
movl 16(%rsp), %ebx
subl $1, %ebx
imull %ebp, %ebx
imull %ebp, %ebx
movslq %ebx, %rax
cmpl $0, 28(%rsp)
je .L117
leal (%r14,%rbx), %edx
cmpl %edx, %r12d
je .L103
.L102:
movq %r15, %rcx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L85
.L117:
leaq 0(,%rax,4), %rdx
movq 32(%rsp), %rax
movq %rax, %rsi
addq 56(%rsp), %rsi
addq 72(%rsp), %rax
movq %rax, %rdi
movq 120(%rsp), %r8
movl $1, %ecx
call cudaMemcpyAsync@PLT
leal (%r14,%rbx), %edx
cmpl %edx, %r12d
jne .L102
movl $0, %ebx
movl $0, %ebp
testl %eax, %eax
jne .L103
.L96:
movl $32, 92(%rsp)
movl $32, 96(%rsp)
movl $1, 100(%rsp)
movslq %ebx, %rax
imulq $12, %rax, %rax
movq 128(%rsp,%rax), %rdi
movl 136(%rsp,%rax), %esi
movq 112(%rsp,%rbx,8), %r9
movl $13872, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L118
.L97:
movslq 104(%rsp,%rbx,4), %rax
addq %rax, %rbp
addq $1, %rbx
cmpq $2, %rbx
jne .L96
movl $0, %ebp
movl $0, %r12d
movl $0, %edx
leaq 104(%rsp), %r14
.L99:
movl 8(%rsp), %eax
movl %eax, %ebx
imull (%r14,%rbp,4), %ebx
imull %eax, %ebx
movslq %ebx, %rbx
movl $1, %eax
testl %edx, %edx
je .L119
.L98:
movzbl %al, %edx
addq %rbx, %r12
addq $1, %rbp
cmpq $2, %rbp
jne .L99
cmpq %r12, %r13
jne .L120
testb %al, %al
jne .L121
movq 112(%rsp), %rdi
call cudaStreamSynchronize@PLT
movq 120(%rsp), %rdi
call cudaStreamSynchronize@PLT
call _Z12getTimeStampv
movsd %xmm0, 16(%rsp)
movq 80(%rsp), %rdi
call cudaFree@PLT
movq $0, 80(%rsp)
movq 72(%rsp), %rdi
call cudaFree@PLT
movq $0, 72(%rsp)
movl 8(%rsp), %esi
movq 64(%rsp), %rdi
call _Z4sumAPfi
movsd %xmm0, 8(%rsp)
movsd 16(%rsp), %xmm1
subsd 40(%rsp), %xmm1
movapd %xmm1, %xmm0
mulsd .LC15(%rip), %xmm0
call ceil@PLT
cvttsd2siq %xmm0, %rdx
movsd 8(%rsp), %xmm0
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 64(%rsp), %rdi
call cudaFreeHost@PLT
movq $0, 64(%rsp)
movq 56(%rsp), %rdi
call cudaFreeHost@PLT
movq $0, 56(%rsp)
call cudaDeviceReset@PLT
jmp .L85
.L103:
movl $1, %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L85
.L118:
movl %ebp, %ecx
movl 8(%rsp), %edx
movq 72(%rsp), %rsi
movq 80(%rsp), %rdi
call _Z40__device_stub__Z16jacobiRelaxationPfS_iiPfS_ii
jmp .L97
.L119:
leaq 0(,%r12,4), %rdi
leaq 0(,%rbx,4), %rdx
movq %rdi, %rsi
addq 80(%rsp), %rsi
addq 64(%rsp), %rdi
movq 112(%rsp,%rbp,8), %r8
movl $2, %ecx
call cudaMemcpyAsync@PLT
testl %eax, %eax
setne %al
jmp .L98
.L120:
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L85
.L121:
movl $1, %edx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L85
.L114:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size main, .-main
.section .rodata.str1.1
.LC17:
.string "_Z16jacobiRelaxationPfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _Z16jacobiRelaxationPfS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1066192077
.align 4
.LC3:
.long 1061997773
.align 4
.LC5:
.long 1065353216
.align 4
.LC6:
.long -1082130432
.section .rodata.cst8
.align 8
.LC15:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <sys/time.h>
// Comment out this line to enable debug mode
#define NDEBUG
/* time stamp function in milliseconds */
__host__ double getTimeStamp()
{
struct timeval tv;
gettimeofday(&tv, NULL);
return (double)tv.tv_usec / 1000000 + tv.tv_sec;
}
__host__ void initB(float *B, int nB)
{
for (int i = 0; i < nB; i++)
{
int iIndex = i * nB * nB;
for (int j = 0; j < nB; j++)
{
int ijIndex = iIndex + j * nB;
for (int k = 0; k < nB; k++)
{
int ijkIndex = ijIndex + k;
if (i == 0 || j == 0 || k == 0)
{
B[ijkIndex] = 0;
}
else
{
B[ijkIndex] = ((i - 1 + j - 1 + k - 1) % 10) * (float)1.1;
}
}
}
}
}
#define h_getB(B, nB, i, j, k) B[((i) + 1) * nB * nB + ((j) + 1) * nB + ((k) + 1)]
__host__ void jacobiRelaxationReference(float *A, float *B, int n)
{
int nB = n + 1;
for (int i = 0; i < n; i++)
{
int iIndex = i * n * n;
for (int j = 0; j < n; j++)
{
int ijIndex = iIndex + j * n;
for (int k = 0; k < n; k++)
{
int ijkIndex = ijIndex + k;
if (i >= n - 1 || j >= n - 1 || k >= n - 1)
{
A[ijkIndex] = 0.0;
}
else
{
A[ijkIndex] = (float)0.8 * (h_getB(B, nB, i - 1, j, k) +
h_getB(B, nB, i + 1, j, k) +
h_getB(B, nB, i, j - 1, k) +
h_getB(B, nB, i, j + 1, k) +
h_getB(B, nB, i, j, k - 1) +
h_getB(B, nB, i, j, k + 1));
}
}
}
}
}
__host__ int checkA(float *Expected, float *Actual, int n)
{
for (int i = 0; i < n; i++)
{
int iIndex = i * n * n;
for (int j = 0; j < n; j++)
{
int ijIndex = iIndex + j * n;
for (int k = 0; k < n; k++)
{
int ijkIndex = ijIndex + k;
if (Expected[ijkIndex] != Actual[ijkIndex])
{
#ifndef NDEBUG
printf("(i=%d, j=%d, k=%d) Expected=%f Actual=%f\n", i, j, k, Expected[ijkIndex], Actual[ijkIndex]);
#endif
return 0;
}
}
}
}
return 1;
}
__host__ double sumA(float *A, int n)
{
double sum = 0;
for (int i = 0; i < n; i++)
{
int iIndex = i * n * n;
for (int j = 0; j < n; j++)
{
int ijIndex = iIndex + j * n;
for (int k = 0; k < n; k++)
{
int ijkIndex = ijIndex + k;
sum += A[ijkIndex] * (((i + j + k) % 10) ? 1 : -1);
}
}
}
return sum;
}
__global__ void jacobiRelaxation(float *A, float *B, int n, int startingI)
{
extern __shared__ float s_data[];
/* Global Index */
int globalK = blockDim.x * blockIdx.x + threadIdx.x;
int globalJ = blockDim.y * blockIdx.y + threadIdx.y;
int globalI = blockDim.z * blockIdx.z + threadIdx.z + startingI;
int globalIdx = globalI * n * n + globalJ * n + globalK;
int nB = n + 1;
int sizePerGlobalBI = nB * nB;
int sizePerGlobalBJ = nB;
int globalBIIndex = (globalI + 1) * sizePerGlobalBI;
int globalBIJIndex = globalBIIndex + (globalJ + 1) * sizePerGlobalBJ;
int globalBIdx = globalBIJIndex + (globalK + 1);
if (globalK >= n || globalJ >= n || globalI >= n)
{
return;
}
/* Local Index */
// int sizeI = blockDim.z + 2;
int sizeJ = blockDim.y + 2;
int sizeK = blockDim.x + 2;
int sizePerLocalI = sizeJ * sizeK;
int sizePerLocalJ = sizeK;
int localIIndex = (threadIdx.z + 1) * sizePerLocalI;
int localIJIndex = localIIndex + (threadIdx.y + 1) * sizePerLocalJ;
int localIdx = localIJIndex + (threadIdx.x + 1);
s_data[localIdx] = B[globalBIdx];
if (threadIdx.z == 0)
{
s_data[localIdx - sizePerLocalI] = B[globalBIdx - sizePerGlobalBI];
s_data[localIdx + blockDim.z * sizePerLocalI] = B[globalBIdx + blockDim.z * sizePerGlobalBI];
}
if (threadIdx.y == 0)
{
s_data[localIdx - sizePerLocalJ] = B[globalBIdx - sizePerGlobalBJ];
s_data[localIdx + blockDim.y * sizePerLocalJ] = B[globalBIdx + blockDim.y * sizePerGlobalBJ];
}
if (threadIdx.x == 0)
{
s_data[localIdx - 1] = B[globalBIdx - 1];
s_data[localIdx + blockDim.x] = B[globalBIdx + blockDim.x];
}
__syncthreads();
if (globalK == n - 1 || globalJ == n - 1 || globalI == n - 1)
{
A[globalIdx] = 0;
}
else
{
A[globalIdx] = (float)0.8 * (s_data[localIdx - sizePerLocalI] +
s_data[localIdx + sizePerLocalI] +
s_data[localIdx - sizePerLocalJ] +
s_data[localIdx + sizePerLocalJ] +
s_data[localIdx - 1] +
s_data[localIdx + 1]);
}
}
int main(int argc, char *argv[])
{
int error = 0;
/* Get Dimension */
if (argc != 2)
{
printf("Error: The number of arguments is not exactly 1\n");
return 0;
}
int n = atoi(argv[1]);
size_t numElem = n * n * n;
size_t numBytes = numElem * sizeof(float);
int nB = n + 1;
size_t numElemB = nB * nB * nB;
size_t numBytesB = numElemB * sizeof(float);
#ifndef NDEBUG
printf("n=%d, numElem=%ld, numBytes=%ld\n", n, numElem, numBytes);
printf("nB=%d, numElemB=%ld, numBytesB=%ld\n", nB, numElemB, numBytesB);
#endif
/* Allocate Host Memory */
float *h_B = NULL;
error = error || cudaHostAlloc((void **)&h_B, numBytesB, 0);
#ifndef NDEBUG
float *h_hA = (float *)malloc(numBytes);
#endif
float *h_dA = NULL;
error = error || cudaHostAlloc((void **)&h_dA, numBytes, 0);
if (error)
{
printf("Error: cudaHostAlloc returns error\n");
return 0;
}
/* Initialize Host Memory */
initB(h_B, nB);
#ifndef NDEBUG
double timestampPreCpuKernel = getTimeStamp();
jacobiRelaxationReference(h_hA, h_B, n);
double timestampPostCpuKernel = getTimeStamp();
printf("CPU: %lf %ld\n", sumA(h_hA, n), (long)ceil(1000*(timestampPostCpuKernel - timestampPreCpuKernel)));
#endif
/* Allocate Device Memory */
float *d_B = NULL;
error = error || cudaMalloc((void **)&d_B, numBytesB);
float *d_A = NULL;
error = error || cudaMalloc((void **)&d_A, numBytes);
if (error)
{
printf("Error: cudaMalloc returns error\n");
return 0;
}
/* Configuration */
#define NUM_STREAM 2
int nIStreams[NUM_STREAM];
for (int i = 0; i < NUM_STREAM; i++)
{
nIStreams[i] = n / NUM_STREAM;
}
nIStreams[NUM_STREAM - 1] += n % NUM_STREAM;
dim3 d_blockDim;
d_blockDim.x = 32;
d_blockDim.y = 32;
d_blockDim.z = 1; // must be 1
dim3 d_gridDimStreams[NUM_STREAM];
for (int i = 0; i < NUM_STREAM; i++)
{
d_gridDimStreams[i].x = (n - 1) / d_blockDim.x + 1;
d_gridDimStreams[i].y = (n - 1) / d_blockDim.y + 1;
d_gridDimStreams[i].z = (nIStreams[i] - 1) / d_blockDim.z + 1;
}
/* Create NUM_STREAM Streams */
cudaStream_t d_streams[NUM_STREAM];
for (int i = 0; i < NUM_STREAM; i++)
{
error = error || cudaStreamCreate(&d_streams[i]);
}
if (error)
{
printf("Error: cudaStreamCreate returns error\n");
return 0;
}
// TIMER BEGIN
/* Copy Host Memory to Device Memory */
double timestampPreCpuGpuTransfer = getTimeStamp();
size_t numElemBStream1 = 0;
if (NUM_STREAM != 1)
{
numElemBStream1 = (nIStreams[0] + 1 + 1) * nB * nB;
}
else
{
numElemBStream1 = (nIStreams[0] + 1) * nB * nB;
}
error = error || cudaMemcpyAsync(d_B, h_B, numElemBStream1 * sizeof(float), cudaMemcpyHostToDevice, d_streams[0]);
if (NUM_STREAM != 1)
{
cudaStreamSynchronize(d_streams[0]);
}
int numElemBStreams = numElemBStream1;
for (int i = 1; i < NUM_STREAM; i++)
{
int nBIStreami = nIStreams[i];
size_t numElemBStreami = ((i == NUM_STREAM - 1) ? nBIStreami - 1 : nBIStreami) * nB * nB;
error = error || cudaMemcpyAsync(d_B + numElemBStreams, h_B + numElemBStreams, numElemBStreami * sizeof(float), cudaMemcpyHostToDevice, d_streams[i]);
numElemBStreams += numElemBStreami;
if (i != NUM_STREAM - 1)
{
// Synchronize between cudaMemcpyAsync
cudaStreamSynchronize(d_streams[i]);
}
}
if (numElemBStreams != numElemB)
{
printf("Error: cudaMemcpyAsync does not cover entire B (%ld != %ld)\n", numElemBStreams, numElemB);
return 0;
}
if (error)
{
printf("Error: cudaMemcpyAsync B returns error %d\n", error);
return 0;
}
/* Run Kernel */
int d_smemNumElem = (d_blockDim.x + 2) * (d_blockDim.y + 2) * (d_blockDim.z + 2);
size_t d_smemNumBytes = d_smemNumElem * sizeof(float);
size_t d_startingI = 0;
for (int i = 0; i < NUM_STREAM; i++)
{
jacobiRelaxation<<<d_gridDimStreams[i], d_blockDim, d_smemNumBytes, d_streams[i]>>>(d_A, d_B, n, d_startingI);
d_startingI += nIStreams[i];
}
/* Copy Device Memory to Host Memory */
size_t numElemAStreams = 0;
for (int i = 0; i < NUM_STREAM; i++)
{
size_t numElemAStreami = nIStreams[i] * n * n;
error = error || cudaMemcpyAsync(h_dA + numElemAStreams, d_A + numElemAStreams, numElemAStreami * sizeof(float), cudaMemcpyDeviceToHost, d_streams[i]);
numElemAStreams += numElemAStreami;
}
if (numElemAStreams != numElem)
{
printf("Error: cudaMemcpyAsync does not cover entire A\n");
return 0;
}
if (error)
{
printf("Error: cudaMemcpyAsync A returns error %d\n", error);
return 0;
}
/* Synchronize Streams */
for (int i = 0; i < NUM_STREAM; i++)
{
cudaStreamSynchronize(d_streams[i]);
}
double timestampPostGpuCpuTransfer = getTimeStamp();
// TIMER END
/* Free Device Memory */
cudaFree(d_A);
d_A = NULL;
cudaFree(d_B);
d_B = NULL;
/* Output */
double aValue = sumA(h_dA, n);
long totalGpuElapased = (long)ceil(1000*(timestampPostGpuCpuTransfer - timestampPreCpuGpuTransfer));
printf("%lf %ld\n", aValue, totalGpuElapased);
#ifndef NDEBUG
for (int i = 0; i < NUM_STREAM; i++)
{
printf("d_gridDimStream%d=(%d, %d, %d), d_blockDim=(%d, %d, %d), d_smemNumBytes=%ld\n", i, d_gridDimStreams[i].x, d_gridDimStreams[i].y, d_gridDimStreams[i].z, d_blockDim.x, d_blockDim.y, d_blockDim.z, d_smemNumBytes);
}
/* Verify Device Result with Host Result */
error = error || !checkA(h_hA, h_dA, n);
if(error)
{
printf("Error: GPU result does not with CPU result\n");
}
#endif
/* Free Host Memory */
cudaFreeHost(h_dA);
h_dA = NULL;
#ifndef NDEBUG
free(h_hA);
h_hA = NULL;
#endif
cudaFreeHost(h_B);
h_B = NULL;
/* Clean Up Device Resource */
cudaDeviceReset();
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <sys/time.h>
// Comment out this line to enable debug mode
#define NDEBUG
/* time stamp function in milliseconds */
__host__ double getTimeStamp()
{
struct timeval tv;
gettimeofday(&tv, NULL);
return (double)tv.tv_usec / 1000000 + tv.tv_sec;
}
__host__ void initB(float *B, int nB)
{
for (int i = 0; i < nB; i++)
{
int iIndex = i * nB * nB;
for (int j = 0; j < nB; j++)
{
int ijIndex = iIndex + j * nB;
for (int k = 0; k < nB; k++)
{
int ijkIndex = ijIndex + k;
if (i == 0 || j == 0 || k == 0)
{
B[ijkIndex] = 0;
}
else
{
B[ijkIndex] = ((i - 1 + j - 1 + k - 1) % 10) * (float)1.1;
}
}
}
}
}
#define h_getB(B, nB, i, j, k) B[((i) + 1) * nB * nB + ((j) + 1) * nB + ((k) + 1)]
__host__ void jacobiRelaxationReference(float *A, float *B, int n)
{
int nB = n + 1;
for (int i = 0; i < n; i++)
{
int iIndex = i * n * n;
for (int j = 0; j < n; j++)
{
int ijIndex = iIndex + j * n;
for (int k = 0; k < n; k++)
{
int ijkIndex = ijIndex + k;
if (i >= n - 1 || j >= n - 1 || k >= n - 1)
{
A[ijkIndex] = 0.0;
}
else
{
A[ijkIndex] = (float)0.8 * (h_getB(B, nB, i - 1, j, k) +
h_getB(B, nB, i + 1, j, k) +
h_getB(B, nB, i, j - 1, k) +
h_getB(B, nB, i, j + 1, k) +
h_getB(B, nB, i, j, k - 1) +
h_getB(B, nB, i, j, k + 1));
}
}
}
}
}
__host__ int checkA(float *Expected, float *Actual, int n)
{
for (int i = 0; i < n; i++)
{
int iIndex = i * n * n;
for (int j = 0; j < n; j++)
{
int ijIndex = iIndex + j * n;
for (int k = 0; k < n; k++)
{
int ijkIndex = ijIndex + k;
if (Expected[ijkIndex] != Actual[ijkIndex])
{
#ifndef NDEBUG
printf("(i=%d, j=%d, k=%d) Expected=%f Actual=%f\n", i, j, k, Expected[ijkIndex], Actual[ijkIndex]);
#endif
return 0;
}
}
}
}
return 1;
}
__host__ double sumA(float *A, int n)
{
double sum = 0;
for (int i = 0; i < n; i++)
{
int iIndex = i * n * n;
for (int j = 0; j < n; j++)
{
int ijIndex = iIndex + j * n;
for (int k = 0; k < n; k++)
{
int ijkIndex = ijIndex + k;
sum += A[ijkIndex] * (((i + j + k) % 10) ? 1 : -1);
}
}
}
return sum;
}
__global__ void jacobiRelaxation(float *A, float *B, int n, int startingI)
{
extern __shared__ float s_data[];
/* Global Index */
int globalK = blockDim.x * blockIdx.x + threadIdx.x;
int globalJ = blockDim.y * blockIdx.y + threadIdx.y;
int globalI = blockDim.z * blockIdx.z + threadIdx.z + startingI;
int globalIdx = globalI * n * n + globalJ * n + globalK;
int nB = n + 1;
int sizePerGlobalBI = nB * nB;
int sizePerGlobalBJ = nB;
int globalBIIndex = (globalI + 1) * sizePerGlobalBI;
int globalBIJIndex = globalBIIndex + (globalJ + 1) * sizePerGlobalBJ;
int globalBIdx = globalBIJIndex + (globalK + 1);
if (globalK >= n || globalJ >= n || globalI >= n)
{
return;
}
/* Local Index */
// int sizeI = blockDim.z + 2;
int sizeJ = blockDim.y + 2;
int sizeK = blockDim.x + 2;
int sizePerLocalI = sizeJ * sizeK;
int sizePerLocalJ = sizeK;
int localIIndex = (threadIdx.z + 1) * sizePerLocalI;
int localIJIndex = localIIndex + (threadIdx.y + 1) * sizePerLocalJ;
int localIdx = localIJIndex + (threadIdx.x + 1);
s_data[localIdx] = B[globalBIdx];
if (threadIdx.z == 0)
{
s_data[localIdx - sizePerLocalI] = B[globalBIdx - sizePerGlobalBI];
s_data[localIdx + blockDim.z * sizePerLocalI] = B[globalBIdx + blockDim.z * sizePerGlobalBI];
}
if (threadIdx.y == 0)
{
s_data[localIdx - sizePerLocalJ] = B[globalBIdx - sizePerGlobalBJ];
s_data[localIdx + blockDim.y * sizePerLocalJ] = B[globalBIdx + blockDim.y * sizePerGlobalBJ];
}
if (threadIdx.x == 0)
{
s_data[localIdx - 1] = B[globalBIdx - 1];
s_data[localIdx + blockDim.x] = B[globalBIdx + blockDim.x];
}
__syncthreads();
if (globalK == n - 1 || globalJ == n - 1 || globalI == n - 1)
{
A[globalIdx] = 0;
}
else
{
A[globalIdx] = (float)0.8 * (s_data[localIdx - sizePerLocalI] +
s_data[localIdx + sizePerLocalI] +
s_data[localIdx - sizePerLocalJ] +
s_data[localIdx + sizePerLocalJ] +
s_data[localIdx - 1] +
s_data[localIdx + 1]);
}
}
int main(int argc, char *argv[])
{
int error = 0;
/* Get Dimension */
if (argc != 2)
{
printf("Error: The number of arguments is not exactly 1\n");
return 0;
}
int n = atoi(argv[1]);
size_t numElem = n * n * n;
size_t numBytes = numElem * sizeof(float);
int nB = n + 1;
size_t numElemB = nB * nB * nB;
size_t numBytesB = numElemB * sizeof(float);
#ifndef NDEBUG
printf("n=%d, numElem=%ld, numBytes=%ld\n", n, numElem, numBytes);
printf("nB=%d, numElemB=%ld, numBytesB=%ld\n", nB, numElemB, numBytesB);
#endif
/* Allocate Host Memory */
float *h_B = NULL;
error = error || hipHostAlloc((void **)&h_B, numBytesB, 0);
#ifndef NDEBUG
float *h_hA = (float *)malloc(numBytes);
#endif
float *h_dA = NULL;
error = error || hipHostAlloc((void **)&h_dA, numBytes, 0);
if (error)
{
printf("Error: hipHostAlloc returns error\n");
return 0;
}
/* Initialize Host Memory */
initB(h_B, nB);
#ifndef NDEBUG
double timestampPreCpuKernel = getTimeStamp();
jacobiRelaxationReference(h_hA, h_B, n);
double timestampPostCpuKernel = getTimeStamp();
printf("CPU: %lf %ld\n", sumA(h_hA, n), (long)ceil(1000*(timestampPostCpuKernel - timestampPreCpuKernel)));
#endif
/* Allocate Device Memory */
float *d_B = NULL;
error = error || hipMalloc((void **)&d_B, numBytesB);
float *d_A = NULL;
error = error || hipMalloc((void **)&d_A, numBytes);
if (error)
{
printf("Error: hipMalloc returns error\n");
return 0;
}
/* Configuration */
#define NUM_STREAM 2
int nIStreams[NUM_STREAM];
for (int i = 0; i < NUM_STREAM; i++)
{
nIStreams[i] = n / NUM_STREAM;
}
nIStreams[NUM_STREAM - 1] += n % NUM_STREAM;
dim3 d_blockDim;
d_blockDim.x = 32;
d_blockDim.y = 32;
d_blockDim.z = 1; // must be 1
dim3 d_gridDimStreams[NUM_STREAM];
for (int i = 0; i < NUM_STREAM; i++)
{
d_gridDimStreams[i].x = (n - 1) / d_blockDim.x + 1;
d_gridDimStreams[i].y = (n - 1) / d_blockDim.y + 1;
d_gridDimStreams[i].z = (nIStreams[i] - 1) / d_blockDim.z + 1;
}
/* Create NUM_STREAM Streams */
hipStream_t d_streams[NUM_STREAM];
for (int i = 0; i < NUM_STREAM; i++)
{
error = error || hipStreamCreate(&d_streams[i]);
}
if (error)
{
printf("Error: hipStreamCreate returns error\n");
return 0;
}
// TIMER BEGIN
/* Copy Host Memory to Device Memory */
double timestampPreCpuGpuTransfer = getTimeStamp();
size_t numElemBStream1 = 0;
if (NUM_STREAM != 1)
{
numElemBStream1 = (nIStreams[0] + 1 + 1) * nB * nB;
}
else
{
numElemBStream1 = (nIStreams[0] + 1) * nB * nB;
}
error = error || hipMemcpyAsync(d_B, h_B, numElemBStream1 * sizeof(float), hipMemcpyHostToDevice, d_streams[0]);
if (NUM_STREAM != 1)
{
hipStreamSynchronize(d_streams[0]);
}
int numElemBStreams = numElemBStream1;
for (int i = 1; i < NUM_STREAM; i++)
{
int nBIStreami = nIStreams[i];
size_t numElemBStreami = ((i == NUM_STREAM - 1) ? nBIStreami - 1 : nBIStreami) * nB * nB;
error = error || hipMemcpyAsync(d_B + numElemBStreams, h_B + numElemBStreams, numElemBStreami * sizeof(float), hipMemcpyHostToDevice, d_streams[i]);
numElemBStreams += numElemBStreami;
if (i != NUM_STREAM - 1)
{
// Synchronize between cudaMemcpyAsync
hipStreamSynchronize(d_streams[i]);
}
}
if (numElemBStreams != numElemB)
{
printf("Error: hipMemcpyAsync does not cover entire B (%ld != %ld)\n", numElemBStreams, numElemB);
return 0;
}
if (error)
{
printf("Error: hipMemcpyAsync B returns error %d\n", error);
return 0;
}
/* Run Kernel */
int d_smemNumElem = (d_blockDim.x + 2) * (d_blockDim.y + 2) * (d_blockDim.z + 2);
size_t d_smemNumBytes = d_smemNumElem * sizeof(float);
size_t d_startingI = 0;
for (int i = 0; i < NUM_STREAM; i++)
{
jacobiRelaxation<<<d_gridDimStreams[i], d_blockDim, d_smemNumBytes, d_streams[i]>>>(d_A, d_B, n, d_startingI);
d_startingI += nIStreams[i];
}
/* Copy Device Memory to Host Memory */
size_t numElemAStreams = 0;
for (int i = 0; i < NUM_STREAM; i++)
{
size_t numElemAStreami = nIStreams[i] * n * n;
error = error || hipMemcpyAsync(h_dA + numElemAStreams, d_A + numElemAStreams, numElemAStreami * sizeof(float), hipMemcpyDeviceToHost, d_streams[i]);
numElemAStreams += numElemAStreami;
}
if (numElemAStreams != numElem)
{
printf("Error: hipMemcpyAsync does not cover entire A\n");
return 0;
}
if (error)
{
printf("Error: hipMemcpyAsync A returns error %d\n", error);
return 0;
}
/* Synchronize Streams */
for (int i = 0; i < NUM_STREAM; i++)
{
hipStreamSynchronize(d_streams[i]);
}
double timestampPostGpuCpuTransfer = getTimeStamp();
// TIMER END
/* Free Device Memory */
hipFree(d_A);
d_A = NULL;
hipFree(d_B);
d_B = NULL;
/* Output */
double aValue = sumA(h_dA, n);
long totalGpuElapased = (long)ceil(1000*(timestampPostGpuCpuTransfer - timestampPreCpuGpuTransfer));
printf("%lf %ld\n", aValue, totalGpuElapased);
#ifndef NDEBUG
for (int i = 0; i < NUM_STREAM; i++)
{
printf("d_gridDimStream%d=(%d, %d, %d), d_blockDim=(%d, %d, %d), d_smemNumBytes=%ld\n", i, d_gridDimStreams[i].x, d_gridDimStreams[i].y, d_gridDimStreams[i].z, d_blockDim.x, d_blockDim.y, d_blockDim.z, d_smemNumBytes);
}
/* Verify Device Result with Host Result */
error = error || !checkA(h_hA, h_dA, n);
if(error)
{
printf("Error: GPU result does not with CPU result\n");
}
#endif
/* Free Host Memory */
hipHostFree(h_dA);
h_dA = NULL;
#ifndef NDEBUG
free(h_hA);
h_hA = NULL;
#endif
hipHostFree(h_B);
h_B = NULL;
/* Clean Up Device Resource */
hipDeviceReset();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <sys/time.h>
// Comment out this line to enable debug mode
#define NDEBUG
/* time stamp function in milliseconds */
__host__ double getTimeStamp()
{
struct timeval tv;
gettimeofday(&tv, NULL);
return (double)tv.tv_usec / 1000000 + tv.tv_sec;
}
__host__ void initB(float *B, int nB)
{
for (int i = 0; i < nB; i++)
{
int iIndex = i * nB * nB;
for (int j = 0; j < nB; j++)
{
int ijIndex = iIndex + j * nB;
for (int k = 0; k < nB; k++)
{
int ijkIndex = ijIndex + k;
if (i == 0 || j == 0 || k == 0)
{
B[ijkIndex] = 0;
}
else
{
B[ijkIndex] = ((i - 1 + j - 1 + k - 1) % 10) * (float)1.1;
}
}
}
}
}
#define h_getB(B, nB, i, j, k) B[((i) + 1) * nB * nB + ((j) + 1) * nB + ((k) + 1)]
__host__ void jacobiRelaxationReference(float *A, float *B, int n)
{
int nB = n + 1;
for (int i = 0; i < n; i++)
{
int iIndex = i * n * n;
for (int j = 0; j < n; j++)
{
int ijIndex = iIndex + j * n;
for (int k = 0; k < n; k++)
{
int ijkIndex = ijIndex + k;
if (i >= n - 1 || j >= n - 1 || k >= n - 1)
{
A[ijkIndex] = 0.0;
}
else
{
A[ijkIndex] = (float)0.8 * (h_getB(B, nB, i - 1, j, k) +
h_getB(B, nB, i + 1, j, k) +
h_getB(B, nB, i, j - 1, k) +
h_getB(B, nB, i, j + 1, k) +
h_getB(B, nB, i, j, k - 1) +
h_getB(B, nB, i, j, k + 1));
}
}
}
}
}
__host__ int checkA(float *Expected, float *Actual, int n)
{
for (int i = 0; i < n; i++)
{
int iIndex = i * n * n;
for (int j = 0; j < n; j++)
{
int ijIndex = iIndex + j * n;
for (int k = 0; k < n; k++)
{
int ijkIndex = ijIndex + k;
if (Expected[ijkIndex] != Actual[ijkIndex])
{
#ifndef NDEBUG
printf("(i=%d, j=%d, k=%d) Expected=%f Actual=%f\n", i, j, k, Expected[ijkIndex], Actual[ijkIndex]);
#endif
return 0;
}
}
}
}
return 1;
}
__host__ double sumA(float *A, int n)
{
double sum = 0;
for (int i = 0; i < n; i++)
{
int iIndex = i * n * n;
for (int j = 0; j < n; j++)
{
int ijIndex = iIndex + j * n;
for (int k = 0; k < n; k++)
{
int ijkIndex = ijIndex + k;
sum += A[ijkIndex] * (((i + j + k) % 10) ? 1 : -1);
}
}
}
return sum;
}
__global__ void jacobiRelaxation(float *A, float *B, int n, int startingI)
{
extern __shared__ float s_data[];
/* Global Index */
int globalK = blockDim.x * blockIdx.x + threadIdx.x;
int globalJ = blockDim.y * blockIdx.y + threadIdx.y;
int globalI = blockDim.z * blockIdx.z + threadIdx.z + startingI;
int globalIdx = globalI * n * n + globalJ * n + globalK;
int nB = n + 1;
int sizePerGlobalBI = nB * nB;
int sizePerGlobalBJ = nB;
int globalBIIndex = (globalI + 1) * sizePerGlobalBI;
int globalBIJIndex = globalBIIndex + (globalJ + 1) * sizePerGlobalBJ;
int globalBIdx = globalBIJIndex + (globalK + 1);
if (globalK >= n || globalJ >= n || globalI >= n)
{
return;
}
/* Local Index */
// int sizeI = blockDim.z + 2;
int sizeJ = blockDim.y + 2;
int sizeK = blockDim.x + 2;
int sizePerLocalI = sizeJ * sizeK;
int sizePerLocalJ = sizeK;
int localIIndex = (threadIdx.z + 1) * sizePerLocalI;
int localIJIndex = localIIndex + (threadIdx.y + 1) * sizePerLocalJ;
int localIdx = localIJIndex + (threadIdx.x + 1);
s_data[localIdx] = B[globalBIdx];
if (threadIdx.z == 0)
{
s_data[localIdx - sizePerLocalI] = B[globalBIdx - sizePerGlobalBI];
s_data[localIdx + blockDim.z * sizePerLocalI] = B[globalBIdx + blockDim.z * sizePerGlobalBI];
}
if (threadIdx.y == 0)
{
s_data[localIdx - sizePerLocalJ] = B[globalBIdx - sizePerGlobalBJ];
s_data[localIdx + blockDim.y * sizePerLocalJ] = B[globalBIdx + blockDim.y * sizePerGlobalBJ];
}
if (threadIdx.x == 0)
{
s_data[localIdx - 1] = B[globalBIdx - 1];
s_data[localIdx + blockDim.x] = B[globalBIdx + blockDim.x];
}
__syncthreads();
if (globalK == n - 1 || globalJ == n - 1 || globalI == n - 1)
{
A[globalIdx] = 0;
}
else
{
A[globalIdx] = (float)0.8 * (s_data[localIdx - sizePerLocalI] +
s_data[localIdx + sizePerLocalI] +
s_data[localIdx - sizePerLocalJ] +
s_data[localIdx + sizePerLocalJ] +
s_data[localIdx - 1] +
s_data[localIdx + 1]);
}
}
int main(int argc, char *argv[])
{
int error = 0;
/* Get Dimension */
if (argc != 2)
{
printf("Error: The number of arguments is not exactly 1\n");
return 0;
}
int n = atoi(argv[1]);
size_t numElem = n * n * n;
size_t numBytes = numElem * sizeof(float);
int nB = n + 1;
size_t numElemB = nB * nB * nB;
size_t numBytesB = numElemB * sizeof(float);
#ifndef NDEBUG
printf("n=%d, numElem=%ld, numBytes=%ld\n", n, numElem, numBytes);
printf("nB=%d, numElemB=%ld, numBytesB=%ld\n", nB, numElemB, numBytesB);
#endif
/* Allocate Host Memory */
float *h_B = NULL;
error = error || hipHostAlloc((void **)&h_B, numBytesB, 0);
#ifndef NDEBUG
float *h_hA = (float *)malloc(numBytes);
#endif
float *h_dA = NULL;
error = error || hipHostAlloc((void **)&h_dA, numBytes, 0);
if (error)
{
printf("Error: hipHostAlloc returns error\n");
return 0;
}
/* Initialize Host Memory */
initB(h_B, nB);
#ifndef NDEBUG
double timestampPreCpuKernel = getTimeStamp();
jacobiRelaxationReference(h_hA, h_B, n);
double timestampPostCpuKernel = getTimeStamp();
printf("CPU: %lf %ld\n", sumA(h_hA, n), (long)ceil(1000*(timestampPostCpuKernel - timestampPreCpuKernel)));
#endif
/* Allocate Device Memory */
float *d_B = NULL;
error = error || hipMalloc((void **)&d_B, numBytesB);
float *d_A = NULL;
error = error || hipMalloc((void **)&d_A, numBytes);
if (error)
{
printf("Error: hipMalloc returns error\n");
return 0;
}
/* Configuration */
#define NUM_STREAM 2
int nIStreams[NUM_STREAM];
for (int i = 0; i < NUM_STREAM; i++)
{
nIStreams[i] = n / NUM_STREAM;
}
nIStreams[NUM_STREAM - 1] += n % NUM_STREAM;
dim3 d_blockDim;
d_blockDim.x = 32;
d_blockDim.y = 32;
d_blockDim.z = 1; // must be 1
dim3 d_gridDimStreams[NUM_STREAM];
for (int i = 0; i < NUM_STREAM; i++)
{
d_gridDimStreams[i].x = (n - 1) / d_blockDim.x + 1;
d_gridDimStreams[i].y = (n - 1) / d_blockDim.y + 1;
d_gridDimStreams[i].z = (nIStreams[i] - 1) / d_blockDim.z + 1;
}
/* Create NUM_STREAM Streams */
hipStream_t d_streams[NUM_STREAM];
for (int i = 0; i < NUM_STREAM; i++)
{
error = error || hipStreamCreate(&d_streams[i]);
}
if (error)
{
printf("Error: hipStreamCreate returns error\n");
return 0;
}
// TIMER BEGIN
/* Copy Host Memory to Device Memory */
double timestampPreCpuGpuTransfer = getTimeStamp();
size_t numElemBStream1 = 0;
if (NUM_STREAM != 1)
{
numElemBStream1 = (nIStreams[0] + 1 + 1) * nB * nB;
}
else
{
numElemBStream1 = (nIStreams[0] + 1) * nB * nB;
}
error = error || hipMemcpyAsync(d_B, h_B, numElemBStream1 * sizeof(float), hipMemcpyHostToDevice, d_streams[0]);
if (NUM_STREAM != 1)
{
hipStreamSynchronize(d_streams[0]);
}
int numElemBStreams = numElemBStream1;
for (int i = 1; i < NUM_STREAM; i++)
{
int nBIStreami = nIStreams[i];
size_t numElemBStreami = ((i == NUM_STREAM - 1) ? nBIStreami - 1 : nBIStreami) * nB * nB;
error = error || hipMemcpyAsync(d_B + numElemBStreams, h_B + numElemBStreams, numElemBStreami * sizeof(float), hipMemcpyHostToDevice, d_streams[i]);
numElemBStreams += numElemBStreami;
if (i != NUM_STREAM - 1)
{
// Synchronize between cudaMemcpyAsync
hipStreamSynchronize(d_streams[i]);
}
}
if (numElemBStreams != numElemB)
{
printf("Error: hipMemcpyAsync does not cover entire B (%ld != %ld)\n", numElemBStreams, numElemB);
return 0;
}
if (error)
{
printf("Error: hipMemcpyAsync B returns error %d\n", error);
return 0;
}
/* Run Kernel */
int d_smemNumElem = (d_blockDim.x + 2) * (d_blockDim.y + 2) * (d_blockDim.z + 2);
size_t d_smemNumBytes = d_smemNumElem * sizeof(float);
size_t d_startingI = 0;
for (int i = 0; i < NUM_STREAM; i++)
{
jacobiRelaxation<<<d_gridDimStreams[i], d_blockDim, d_smemNumBytes, d_streams[i]>>>(d_A, d_B, n, d_startingI);
d_startingI += nIStreams[i];
}
/* Copy Device Memory to Host Memory */
size_t numElemAStreams = 0;
for (int i = 0; i < NUM_STREAM; i++)
{
size_t numElemAStreami = nIStreams[i] * n * n;
error = error || hipMemcpyAsync(h_dA + numElemAStreams, d_A + numElemAStreams, numElemAStreami * sizeof(float), hipMemcpyDeviceToHost, d_streams[i]);
numElemAStreams += numElemAStreami;
}
if (numElemAStreams != numElem)
{
printf("Error: hipMemcpyAsync does not cover entire A\n");
return 0;
}
if (error)
{
printf("Error: hipMemcpyAsync A returns error %d\n", error);
return 0;
}
/* Synchronize Streams */
for (int i = 0; i < NUM_STREAM; i++)
{
hipStreamSynchronize(d_streams[i]);
}
double timestampPostGpuCpuTransfer = getTimeStamp();
// TIMER END
/* Free Device Memory */
hipFree(d_A);
d_A = NULL;
hipFree(d_B);
d_B = NULL;
/* Output */
double aValue = sumA(h_dA, n);
long totalGpuElapased = (long)ceil(1000*(timestampPostGpuCpuTransfer - timestampPreCpuGpuTransfer));
printf("%lf %ld\n", aValue, totalGpuElapased);
#ifndef NDEBUG
for (int i = 0; i < NUM_STREAM; i++)
{
printf("d_gridDimStream%d=(%d, %d, %d), d_blockDim=(%d, %d, %d), d_smemNumBytes=%ld\n", i, d_gridDimStreams[i].x, d_gridDimStreams[i].y, d_gridDimStreams[i].z, d_blockDim.x, d_blockDim.y, d_blockDim.z, d_smemNumBytes);
}
/* Verify Device Result with Host Result */
error = error || !checkA(h_hA, h_dA, n);
if(error)
{
printf("Error: GPU result does not with CPU result\n");
}
#endif
/* Free Host Memory */
hipHostFree(h_dA);
h_dA = NULL;
#ifndef NDEBUG
free(h_hA);
h_hA = NULL;
#endif
hipHostFree(h_B);
h_B = NULL;
/* Clean Up Device Resource */
hipDeviceReset();
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16jacobiRelaxationPfS_ii
.globl _Z16jacobiRelaxationPfS_ii
.p2align 8
.type _Z16jacobiRelaxationPfS_ii,@function
_Z16jacobiRelaxationPfS_ii:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v3, 0x3ff, v0
v_bfe_u32 v5, v0, 10, 10
v_bfe_u32 v9, v0, 20, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s2, 0xffff
s_lshr_b32 s9, s2, 16
s_and_b32 s10, s3, 0xffff
v_mad_u64_u32 v[0:1], null, s13, s7, v[3:4]
v_mad_u64_u32 v[1:2], null, s14, s9, v[5:6]
s_mul_i32 s15, s15, s10
s_mov_b32 s2, exec_lo
v_add3_u32 v8, s15, s5, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max3_i32 v2, v0, v1, v8
v_cmpx_gt_i32_e64 s4, v2
s_cbranch_execz .LBB0_10
s_add_i32 s6, s4, 1
s_load_b64 s[2:3], s[0:1], 0x8
s_mul_i32 s11, s6, s6
v_mad_u64_u32 v[6:7], null, s6, v1, s[6:7]
v_mul_lo_u32 v2, s11, v8
s_add_i32 s8, s9, 2
s_add_i32 s5, s7, 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_i32 s8, s8, s5
v_add3_u32 v2, v2, s11, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, v2, v0
v_add_nc_u32_e32 v2, 1, v5
v_add_nc_u32_e32 v6, 1, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_u32_u24_e32 v2, s5, v2
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[10:11], 2, v[6:7]
v_mul_lo_u32 v7, s8, v9
s_waitcnt lgkmcnt(0)
v_add_co_u32 v10, vcc_lo, s2, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v11, vcc_lo, s3, v11, vcc_lo
v_add3_u32 v7, v7, s8, v2
v_cmp_eq_u32_e32 vcc_lo, 0, v9
global_load_b32 v10, v[10:11], off
v_add3_u32 v2, v3, v7, 1
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v11, v2, 2, 0
v_subrev_nc_u32_e32 v9, s8, v2
s_waitcnt vmcnt(0)
ds_store_b32 v11, v10
s_and_saveexec_b32 s12, vcc_lo
s_cbranch_execz .LBB0_3
v_subrev_nc_u32_e32 v10, s11, v6
v_mad_u64_u32 v[12:13], null, s11, s10, v[6:7]
v_mov_b32_e32 v13, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], 2, v[10:11]
v_add_co_u32 v10, vcc_lo, s2, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v11, vcc_lo, s3, v11, vcc_lo
v_add_co_u32 v12, vcc_lo, s2, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s3, v13, vcc_lo
s_clause 0x1
global_load_b32 v14, v[10:11], off
global_load_b32 v12, v[12:13], off
v_mad_u64_u32 v[10:11], null, s8, s10, v[2:3]
v_lshl_add_u32 v11, v9, 2, 0
s_delay_alu instid0(VALU_DEP_2)
v_lshl_add_u32 v10, v10, 2, 0
s_waitcnt vmcnt(1)
ds_store_b32 v11, v14
s_waitcnt vmcnt(0)
ds_store_b32 v10, v12
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s12
v_subrev_nc_u32_e32 v10, s5, v2
s_mov_b32 s10, exec_lo
v_cmpx_eq_u32_e32 0, v5
s_cbranch_execz .LBB0_5
v_subrev_nc_u32_e32 v11, s4, v4
v_mad_u64_u32 v[13:14], null, s6, s9, v[6:7]
v_mov_b32_e32 v14, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v12, 31, v11
v_lshlrev_b64 v[13:14], 2, v[13:14]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_add_co_u32 v11, vcc_lo, s2, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v12, vcc_lo
v_add_co_u32 v13, vcc_lo, s2, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s3, v14, vcc_lo
s_clause 0x1
global_load_b32 v5, v[11:12], off
global_load_b32 v13, v[13:14], off
v_mad_u64_u32 v[11:12], null, s5, s9, v[2:3]
v_lshl_add_u32 v12, v10, 2, 0
s_delay_alu instid0(VALU_DEP_2)
v_lshl_add_u32 v11, v11, 2, 0
s_waitcnt vmcnt(1)
ds_store_b32 v12, v5
s_waitcnt vmcnt(0)
ds_store_b32 v11, v13
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s6, exec_lo
v_cmpx_eq_u32_e32 0, v3
s_cbranch_execz .LBB0_7
v_ashrrev_i32_e32 v5, 31, v4
v_dual_mov_b32 v12, 0 :: v_dual_add_nc_u32 v11, s7, v6
v_add_nc_u32_e32 v6, s7, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshl_add_u32 v6, v6, 2, 0
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_add_co_u32 v11, vcc_lo, s2, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v12, vcc_lo
s_clause 0x1
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[11:12], off
v_lshl_add_u32 v11, v7, 2, 0
s_waitcnt vmcnt(1)
ds_store_b32 v11, v4
s_waitcnt vmcnt(0)
ds_store_b32 v6, v5
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s6
s_add_i32 s3, s4, -1
v_mov_b32_e32 v4, 0
v_cmp_ne_u32_e32 vcc_lo, s3, v0
v_cmp_ne_u32_e64 s2, s3, v1
v_cmp_ne_u32_e64 s3, s3, v8
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s2, s3
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_9
v_add_nc_u32_e32 v4, s8, v2
v_lshl_add_u32 v5, v9, 2, 0
v_lshl_add_u32 v6, v10, 2, 0
s_delay_alu instid0(VALU_DEP_3)
v_lshl_add_u32 v4, v4, 2, 0
ds_load_b32 v5, v5
ds_load_b32 v4, v4
ds_load_b32 v6, v6
v_add_nc_u32_e32 v9, s5, v2
v_lshl_add_u32 v2, v2, 2, 0
s_waitcnt lgkmcnt(1)
v_add_f32_e32 v4, v5, v4
s_delay_alu instid0(VALU_DEP_3)
v_lshl_add_u32 v9, v9, 2, 0
v_add_nc_u32_e32 v3, v7, v3
ds_load_b32 v7, v9
s_waitcnt lgkmcnt(1)
v_add_f32_e32 v4, v4, v6
v_lshl_add_u32 v3, v3, 2, 0
ds_load_b32 v3, v3
ds_load_b32 v2, v2 offset:4
s_waitcnt lgkmcnt(2)
v_add_f32_e32 v4, v4, v7
s_waitcnt lgkmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v4, v3
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v4, 0x3f4ccccd, v2
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s2
v_mad_u64_u32 v[2:3], null, v8, s4, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v2, s4, v[0:1]
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16jacobiRelaxationPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16jacobiRelaxationPfS_ii, .Lfunc_end0-_Z16jacobiRelaxationPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16jacobiRelaxationPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16jacobiRelaxationPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <sys/time.h>
// Comment out this line to enable debug mode
#define NDEBUG
/* time stamp function in milliseconds */
__host__ double getTimeStamp()
{
struct timeval tv;
gettimeofday(&tv, NULL);
return (double)tv.tv_usec / 1000000 + tv.tv_sec;
}
__host__ void initB(float *B, int nB)
{
for (int i = 0; i < nB; i++)
{
int iIndex = i * nB * nB;
for (int j = 0; j < nB; j++)
{
int ijIndex = iIndex + j * nB;
for (int k = 0; k < nB; k++)
{
int ijkIndex = ijIndex + k;
if (i == 0 || j == 0 || k == 0)
{
B[ijkIndex] = 0;
}
else
{
B[ijkIndex] = ((i - 1 + j - 1 + k - 1) % 10) * (float)1.1;
}
}
}
}
}
#define h_getB(B, nB, i, j, k) B[((i) + 1) * nB * nB + ((j) + 1) * nB + ((k) + 1)]
__host__ void jacobiRelaxationReference(float *A, float *B, int n)
{
int nB = n + 1;
for (int i = 0; i < n; i++)
{
int iIndex = i * n * n;
for (int j = 0; j < n; j++)
{
int ijIndex = iIndex + j * n;
for (int k = 0; k < n; k++)
{
int ijkIndex = ijIndex + k;
if (i >= n - 1 || j >= n - 1 || k >= n - 1)
{
A[ijkIndex] = 0.0;
}
else
{
A[ijkIndex] = (float)0.8 * (h_getB(B, nB, i - 1, j, k) +
h_getB(B, nB, i + 1, j, k) +
h_getB(B, nB, i, j - 1, k) +
h_getB(B, nB, i, j + 1, k) +
h_getB(B, nB, i, j, k - 1) +
h_getB(B, nB, i, j, k + 1));
}
}
}
}
}
__host__ int checkA(float *Expected, float *Actual, int n)
{
for (int i = 0; i < n; i++)
{
int iIndex = i * n * n;
for (int j = 0; j < n; j++)
{
int ijIndex = iIndex + j * n;
for (int k = 0; k < n; k++)
{
int ijkIndex = ijIndex + k;
if (Expected[ijkIndex] != Actual[ijkIndex])
{
#ifndef NDEBUG
printf("(i=%d, j=%d, k=%d) Expected=%f Actual=%f\n", i, j, k, Expected[ijkIndex], Actual[ijkIndex]);
#endif
return 0;
}
}
}
}
return 1;
}
__host__ double sumA(float *A, int n)
{
double sum = 0;
for (int i = 0; i < n; i++)
{
int iIndex = i * n * n;
for (int j = 0; j < n; j++)
{
int ijIndex = iIndex + j * n;
for (int k = 0; k < n; k++)
{
int ijkIndex = ijIndex + k;
sum += A[ijkIndex] * (((i + j + k) % 10) ? 1 : -1);
}
}
}
return sum;
}
__global__ void jacobiRelaxation(float *A, float *B, int n, int startingI)
{
extern __shared__ float s_data[];
/* Global Index */
int globalK = blockDim.x * blockIdx.x + threadIdx.x;
int globalJ = blockDim.y * blockIdx.y + threadIdx.y;
int globalI = blockDim.z * blockIdx.z + threadIdx.z + startingI;
int globalIdx = globalI * n * n + globalJ * n + globalK;
int nB = n + 1;
int sizePerGlobalBI = nB * nB;
int sizePerGlobalBJ = nB;
int globalBIIndex = (globalI + 1) * sizePerGlobalBI;
int globalBIJIndex = globalBIIndex + (globalJ + 1) * sizePerGlobalBJ;
int globalBIdx = globalBIJIndex + (globalK + 1);
if (globalK >= n || globalJ >= n || globalI >= n)
{
return;
}
/* Local Index */
// int sizeI = blockDim.z + 2;
int sizeJ = blockDim.y + 2;
int sizeK = blockDim.x + 2;
int sizePerLocalI = sizeJ * sizeK;
int sizePerLocalJ = sizeK;
int localIIndex = (threadIdx.z + 1) * sizePerLocalI;
int localIJIndex = localIIndex + (threadIdx.y + 1) * sizePerLocalJ;
int localIdx = localIJIndex + (threadIdx.x + 1);
s_data[localIdx] = B[globalBIdx];
if (threadIdx.z == 0)
{
s_data[localIdx - sizePerLocalI] = B[globalBIdx - sizePerGlobalBI];
s_data[localIdx + blockDim.z * sizePerLocalI] = B[globalBIdx + blockDim.z * sizePerGlobalBI];
}
if (threadIdx.y == 0)
{
s_data[localIdx - sizePerLocalJ] = B[globalBIdx - sizePerGlobalBJ];
s_data[localIdx + blockDim.y * sizePerLocalJ] = B[globalBIdx + blockDim.y * sizePerGlobalBJ];
}
if (threadIdx.x == 0)
{
s_data[localIdx - 1] = B[globalBIdx - 1];
s_data[localIdx + blockDim.x] = B[globalBIdx + blockDim.x];
}
__syncthreads();
if (globalK == n - 1 || globalJ == n - 1 || globalI == n - 1)
{
A[globalIdx] = 0;
}
else
{
A[globalIdx] = (float)0.8 * (s_data[localIdx - sizePerLocalI] +
s_data[localIdx + sizePerLocalI] +
s_data[localIdx - sizePerLocalJ] +
s_data[localIdx + sizePerLocalJ] +
s_data[localIdx - 1] +
s_data[localIdx + 1]);
}
}
int main(int argc, char *argv[])
{
int error = 0;
/* Get Dimension */
if (argc != 2)
{
printf("Error: The number of arguments is not exactly 1\n");
return 0;
}
int n = atoi(argv[1]);
size_t numElem = n * n * n;
size_t numBytes = numElem * sizeof(float);
int nB = n + 1;
size_t numElemB = nB * nB * nB;
size_t numBytesB = numElemB * sizeof(float);
#ifndef NDEBUG
printf("n=%d, numElem=%ld, numBytes=%ld\n", n, numElem, numBytes);
printf("nB=%d, numElemB=%ld, numBytesB=%ld\n", nB, numElemB, numBytesB);
#endif
/* Allocate Host Memory */
float *h_B = NULL;
error = error || hipHostAlloc((void **)&h_B, numBytesB, 0);
#ifndef NDEBUG
float *h_hA = (float *)malloc(numBytes);
#endif
float *h_dA = NULL;
error = error || hipHostAlloc((void **)&h_dA, numBytes, 0);
if (error)
{
printf("Error: hipHostAlloc returns error\n");
return 0;
}
/* Initialize Host Memory */
initB(h_B, nB);
#ifndef NDEBUG
double timestampPreCpuKernel = getTimeStamp();
jacobiRelaxationReference(h_hA, h_B, n);
double timestampPostCpuKernel = getTimeStamp();
printf("CPU: %lf %ld\n", sumA(h_hA, n), (long)ceil(1000*(timestampPostCpuKernel - timestampPreCpuKernel)));
#endif
/* Allocate Device Memory */
float *d_B = NULL;
error = error || hipMalloc((void **)&d_B, numBytesB);
float *d_A = NULL;
error = error || hipMalloc((void **)&d_A, numBytes);
if (error)
{
printf("Error: hipMalloc returns error\n");
return 0;
}
/* Configuration */
#define NUM_STREAM 2
int nIStreams[NUM_STREAM];
for (int i = 0; i < NUM_STREAM; i++)
{
nIStreams[i] = n / NUM_STREAM;
}
nIStreams[NUM_STREAM - 1] += n % NUM_STREAM;
dim3 d_blockDim;
d_blockDim.x = 32;
d_blockDim.y = 32;
d_blockDim.z = 1; // must be 1
dim3 d_gridDimStreams[NUM_STREAM];
for (int i = 0; i < NUM_STREAM; i++)
{
d_gridDimStreams[i].x = (n - 1) / d_blockDim.x + 1;
d_gridDimStreams[i].y = (n - 1) / d_blockDim.y + 1;
d_gridDimStreams[i].z = (nIStreams[i] - 1) / d_blockDim.z + 1;
}
/* Create NUM_STREAM Streams */
hipStream_t d_streams[NUM_STREAM];
for (int i = 0; i < NUM_STREAM; i++)
{
error = error || hipStreamCreate(&d_streams[i]);
}
if (error)
{
printf("Error: hipStreamCreate returns error\n");
return 0;
}
// TIMER BEGIN
/* Copy Host Memory to Device Memory */
double timestampPreCpuGpuTransfer = getTimeStamp();
size_t numElemBStream1 = 0;
if (NUM_STREAM != 1)
{
numElemBStream1 = (nIStreams[0] + 1 + 1) * nB * nB;
}
else
{
numElemBStream1 = (nIStreams[0] + 1) * nB * nB;
}
error = error || hipMemcpyAsync(d_B, h_B, numElemBStream1 * sizeof(float), hipMemcpyHostToDevice, d_streams[0]);
if (NUM_STREAM != 1)
{
hipStreamSynchronize(d_streams[0]);
}
int numElemBStreams = numElemBStream1;
for (int i = 1; i < NUM_STREAM; i++)
{
int nBIStreami = nIStreams[i];
size_t numElemBStreami = ((i == NUM_STREAM - 1) ? nBIStreami - 1 : nBIStreami) * nB * nB;
error = error || hipMemcpyAsync(d_B + numElemBStreams, h_B + numElemBStreams, numElemBStreami * sizeof(float), hipMemcpyHostToDevice, d_streams[i]);
numElemBStreams += numElemBStreami;
if (i != NUM_STREAM - 1)
{
// Synchronize between cudaMemcpyAsync
hipStreamSynchronize(d_streams[i]);
}
}
if (numElemBStreams != numElemB)
{
printf("Error: hipMemcpyAsync does not cover entire B (%ld != %ld)\n", numElemBStreams, numElemB);
return 0;
}
if (error)
{
printf("Error: hipMemcpyAsync B returns error %d\n", error);
return 0;
}
/* Run Kernel */
int d_smemNumElem = (d_blockDim.x + 2) * (d_blockDim.y + 2) * (d_blockDim.z + 2);
size_t d_smemNumBytes = d_smemNumElem * sizeof(float);
size_t d_startingI = 0;
for (int i = 0; i < NUM_STREAM; i++)
{
jacobiRelaxation<<<d_gridDimStreams[i], d_blockDim, d_smemNumBytes, d_streams[i]>>>(d_A, d_B, n, d_startingI);
d_startingI += nIStreams[i];
}
/* Copy Device Memory to Host Memory */
size_t numElemAStreams = 0;
for (int i = 0; i < NUM_STREAM; i++)
{
size_t numElemAStreami = nIStreams[i] * n * n;
error = error || hipMemcpyAsync(h_dA + numElemAStreams, d_A + numElemAStreams, numElemAStreami * sizeof(float), hipMemcpyDeviceToHost, d_streams[i]);
numElemAStreams += numElemAStreami;
}
if (numElemAStreams != numElem)
{
printf("Error: hipMemcpyAsync does not cover entire A\n");
return 0;
}
if (error)
{
printf("Error: hipMemcpyAsync A returns error %d\n", error);
return 0;
}
/* Synchronize Streams */
for (int i = 0; i < NUM_STREAM; i++)
{
hipStreamSynchronize(d_streams[i]);
}
double timestampPostGpuCpuTransfer = getTimeStamp();
// TIMER END
/* Free Device Memory */
hipFree(d_A);
d_A = NULL;
hipFree(d_B);
d_B = NULL;
/* Output */
double aValue = sumA(h_dA, n);
long totalGpuElapased = (long)ceil(1000*(timestampPostGpuCpuTransfer - timestampPreCpuGpuTransfer));
printf("%lf %ld\n", aValue, totalGpuElapased);
#ifndef NDEBUG
for (int i = 0; i < NUM_STREAM; i++)
{
printf("d_gridDimStream%d=(%d, %d, %d), d_blockDim=(%d, %d, %d), d_smemNumBytes=%ld\n", i, d_gridDimStreams[i].x, d_gridDimStreams[i].y, d_gridDimStreams[i].z, d_blockDim.x, d_blockDim.y, d_blockDim.z, d_smemNumBytes);
}
/* Verify Device Result with Host Result */
error = error || !checkA(h_hA, h_dA, n);
if(error)
{
printf("Error: GPU result does not with CPU result\n");
}
#endif
/* Free Host Memory */
hipHostFree(h_dA);
h_dA = NULL;
#ifndef NDEBUG
free(h_hA);
h_hA = NULL;
#endif
hipHostFree(h_B);
h_B = NULL;
/* Clean Up Device Resource */
hipDeviceReset();
} | .text
.file "1001721498.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z12getTimeStampv
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z12getTimeStampv
.p2align 4, 0x90
.type _Z12getTimeStampv,@function
_Z12getTimeStampv: # @_Z12getTimeStampv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 16(%rsp), %xmm1
divsd .LCPI0_0(%rip), %xmm1
cvtsi2sdq 8(%rsp), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z12getTimeStampv, .Lfunc_end0-_Z12getTimeStampv
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z5initBPfi
.LCPI1_0:
.long 0x3f8ccccd # float 1.10000002
.text
.globl _Z5initBPfi
.p2align 4, 0x90
.type _Z5initBPfi,@function
_Z5initBPfi: # @_Z5initBPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_10
# %bb.1: # %.lr.ph39
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %eax
movl %esi, %ecx
imull %esi, %ecx
movl %ecx, -4(%rsp) # 4-byte Spill
xorl %edx, %edx
movq $-3, %r8
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorl %r9d, %r9d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_8: # %._crit_edge36
# in Loop: Header=BB1_2 Depth=1
incq %r9
addl -4(%rsp), %edx # 4-byte Folded Reload
incq %r8
cmpq %rax, %r9
je .LBB1_9
.LBB1_2: # %.lr.ph35
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
# Child Loop BB1_4 Depth 3
movq %r8, %r10
movl %edx, %r11d
xorl %ebx, %ebx
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_7: # %._crit_edge
# in Loop: Header=BB1_3 Depth=2
incq %rbx
addl %esi, %r11d
incq %r10
cmpq %rax, %rbx
je .LBB1_8
.LBB1_3: # %.lr.ph
# Parent Loop BB1_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_4 Depth 3
testq %r9, %r9
sete %r15b
movslq %r11d, %r14
leaq (%rdi,%r14,4), %r14
testq %rbx, %rbx
sete %bpl
orb %r15b, %bpl
xorl %r15d, %r15d
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_6: # in Loop: Header=BB1_4 Depth=3
movss %xmm1, (%r14,%r15,4)
incq %r15
cmpq %r15, %rax
je .LBB1_7
.LBB1_4: # Parent Loop BB1_2 Depth=1
# Parent Loop BB1_3 Depth=2
# => This Inner Loop Header: Depth=3
testq %r15, %r15
sete %r12b
orb %bpl, %r12b
xorps %xmm1, %xmm1
jne .LBB1_6
# %bb.5: # in Loop: Header=BB1_4 Depth=3
leal (%r10,%r15), %r12d
movslq %r12d, %r12
imulq $1717986919, %r12, %r13 # imm = 0x66666667
movq %r13, %rcx
shrq $63, %rcx
sarq $34, %r13
addl %ecx, %r13d
addl %r13d, %r13d
leal (%r13,%r13,4), %ecx
subl %ecx, %r12d
xorps %xmm1, %xmm1
cvtsi2ss %r12d, %xmm1
mulss %xmm0, %xmm1
jmp .LBB1_6
.LBB1_9:
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB1_10: # %._crit_edge40
retq
.Lfunc_end1:
.size _Z5initBPfi, .Lfunc_end1-_Z5initBPfi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z25jacobiRelaxationReferencePfS_i
.LCPI2_0:
.long 0x3f4ccccd # float 0.800000011
.text
.globl _Z25jacobiRelaxationReferencePfS_i
.p2align 4, 0x90
.type _Z25jacobiRelaxationReferencePfS_i,@function
_Z25jacobiRelaxationReferencePfS_i: # @_Z25jacobiRelaxationReferencePfS_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
# kill: def $edx killed $edx def $rdx
movq %rdi, -16(%rsp) # 8-byte Spill
movq %rdx, -72(%rsp) # 8-byte Spill
testl %edx, %edx
jle .LBB2_10
# %bb.1: # %.lr.ph83
movq -72(%rsp), %rdx # 8-byte Reload
leal 1(%rdx), %edi
leal -1(%rdx), %eax
movslq %eax, %rcx
movl %edi, %eax
movq %rax, -24(%rsp) # 8-byte Spill
movl %edx, %r9d
movl %edx, %eax
imull %edx, %eax
movl %eax, -116(%rsp) # 4-byte Spill
leal 2(%rdx), %eax
imull %edi, %eax
movl %edi, %r8d
imull %r8d, %r8d
leaq 4(%rsi), %r10
movq %r10, -32(%rsp) # 8-byte Spill
leal 3(%rdx), %r15d
imull %edi, %r15d
leal 3(,%rdx,2), %r10d
imull %edi, %r10d
leal 2(%rax), %r12d
xorl %r11d, %r11d
movss .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movl %edi, -96(%rsp) # 4-byte Spill
movq %r8, -64(%rsp) # 8-byte Spill
# kill: def $r8d killed $r8d killed $r8
xorl %edx, %edx
movq %rdx, -128(%rsp) # 8-byte Spill
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_9: # %._crit_edge80
# in Loop: Header=BB2_2 Depth=1
movq -128(%rsp), %rbx # 8-byte Reload
incq %rbx
movq -56(%rsp), %r11 # 8-byte Reload
addl -116(%rsp), %r11d # 4-byte Folded Reload
movq -40(%rsp), %rax # 8-byte Reload
movq -64(%rsp), %rdx # 8-byte Reload
addl %edx, %eax
movl -100(%rsp), %r15d # 4-byte Reload
addl %edx, %r15d
movl -112(%rsp), %r8d # 4-byte Reload
addl %edx, %r8d
movl -104(%rsp), %r10d # 4-byte Reload
addl %edx, %r10d
movl -108(%rsp), %edi # 4-byte Reload
addl %edx, %edi
movq -48(%rsp), %r12 # 8-byte Reload
addq %rdx, %r12
movq %rbx, %rdx
movq %rbx, -128(%rsp) # 8-byte Spill
cmpq %r9, %rbx
je .LBB2_10
.LBB2_2: # %.lr.ph79
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
# Child Loop BB2_4 Depth 3
movq %r12, -48(%rsp) # 8-byte Spill
movl %edi, -108(%rsp) # 4-byte Spill
movl %edi, %ebp
movl %r10d, -104(%rsp) # 4-byte Spill
movl %r8d, -112(%rsp) # 4-byte Spill
movl %r8d, %edx
movl %r15d, -100(%rsp) # 4-byte Spill
movl %r15d, %r14d
movq %rax, -40(%rsp) # 8-byte Spill
movl %eax, %ebx
movq %r11, -56(%rsp) # 8-byte Spill
movl %r11d, %r8d
xorl %r15d, %r15d
jmp .LBB2_3
.p2align 4, 0x90
.LBB2_8: # %._crit_edge
# in Loop: Header=BB2_3 Depth=2
addl -72(%rsp), %r8d # 4-byte Folded Reload
movl -96(%rsp), %eax # 4-byte Reload
movl -88(%rsp), %ebx # 4-byte Reload
addl %eax, %ebx
movl -92(%rsp), %r14d # 4-byte Reload
addl %eax, %r14d
movl -84(%rsp), %edx # 4-byte Reload
addl %eax, %edx
movl -80(%rsp), %r10d # 4-byte Reload
addl %eax, %r10d
movl -76(%rsp), %ebp # 4-byte Reload
addl %eax, %ebp
addq -24(%rsp), %r12 # 8-byte Folded Reload
movq -8(%rsp), %r15 # 8-byte Reload
cmpq %r9, %r15
je .LBB2_9
.LBB2_3: # %.lr.ph
# Parent Loop BB2_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_4 Depth 3
movslq %r8d, %rax
movl %edx, %r13d
movq -16(%rsp), %rdx # 8-byte Reload
leaq (%rdx,%rax,4), %rdi
movl %ebx, -88(%rsp) # 4-byte Spill
movslq %ebx, %rax
leaq (%rsi,%rax,4), %r11
movl %r14d, -92(%rsp) # 4-byte Spill
movslq %r14d, %rax
movq -32(%rsp), %rbx # 8-byte Reload
leaq (%rbx,%rax,4), %r14
movl %r13d, -84(%rsp) # 4-byte Spill
movslq %r13d, %rax
leaq (%rbx,%rax,4), %rax
movl %r10d, -80(%rsp) # 4-byte Spill
movslq %r10d, %rdx
leaq (%rbx,%rdx,4), %rdx
movl %ebp, -76(%rsp) # 4-byte Spill
movslq %ebp, %r10
leaq (%rbx,%r10,4), %r10
movq -128(%rsp), %rbx # 8-byte Reload
cmpl %r15d, %ebx
movl %r15d, %ebp
cmovgl %ebx, %ebp
incq %r15
movq %r15, -8(%rsp) # 8-byte Spill
xorl %ebx, %ebx
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_7: # in Loop: Header=BB2_4 Depth=3
movss %xmm1, (%rdi,%rbx,4)
incq %rbx
cmpq %rbx, %r9
je .LBB2_8
.LBB2_4: # Parent Loop BB2_2 Depth=1
# Parent Loop BB2_3 Depth=2
# => This Inner Loop Header: Depth=3
xorps %xmm1, %xmm1
cmpl %ebp, %ecx
jle .LBB2_7
# %bb.5: # in Loop: Header=BB2_4 Depth=3
cmpq %rcx, %rbx
jge .LBB2_7
# %bb.6: # in Loop: Header=BB2_4 Depth=3
movss (%r10,%rbx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
addss (%rdx,%rbx,4), %xmm1
addss (%rax,%rbx,4), %xmm1
addss (%r14,%rbx,4), %xmm1
addss (%r11,%rbx,4), %xmm1
leal (%r12,%rbx), %r13d
movslq %r13d, %r13
addss (%rsi,%r13,4), %xmm1
mulss %xmm0, %xmm1
jmp .LBB2_7
.LBB2_10: # %._crit_edge84
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z25jacobiRelaxationReferencePfS_i, .Lfunc_end2-_Z25jacobiRelaxationReferencePfS_i
.cfi_endproc
# -- End function
.globl _Z6checkAPfS_i # -- Begin function _Z6checkAPfS_i
.p2align 4, 0x90
.type _Z6checkAPfS_i,@function
_Z6checkAPfS_i: # @_Z6checkAPfS_i
.cfi_startproc
# %bb.0:
testl %edx, %edx
setle %al
jle .LBB3_18
# %bb.1: # %.lr.ph60
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ecx
movl %edx, %r8d
imull %edx, %r8d
xorl %r9d, %r9d
xorl %r10d, %r10d
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_16: # in Loop: Header=BB3_2 Depth=1
incq %r10
cmpq %rcx, %r10
setae %al
addl %r8d, %r9d
cmpq %rcx, %r10
je .LBB3_17
.LBB3_2: # %.lr.ph51.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_3 Depth 2
# Child Loop BB3_8 Depth 3
movl %r10d, %r11d
imull %edx, %r11d
movl %r9d, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_3: # %.lr.ph51
# Parent Loop BB3_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_8 Depth 3
leal (%r11,%r14), %ebp
imull %edx, %ebp
movslq %ebp, %r15
movss (%rdi,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss (%rsi,%r15,4), %xmm0
jne .LBB3_4
jp .LBB3_4
# %bb.7: # %.lr.ph.preheader
# in Loop: Header=BB3_3 Depth=2
movslq %ebx, %r15
leaq (%rdi,%r15,4), %r12
leaq (%rsi,%r15,4), %r13
movl $1, %ebp
.p2align 4, 0x90
.LBB3_8: # %.lr.ph
# Parent Loop BB3_2 Depth=1
# Parent Loop BB3_3 Depth=2
# => This Inner Loop Header: Depth=3
movq %rbp, %r15
cmpq %rbp, %rcx
je .LBB3_9
# %bb.10: # in Loop: Header=BB3_8 Depth=3
movss (%r12,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
leaq 1(%r15), %rbp
ucomiss (%r13,%r15,4), %xmm0
jne .LBB3_11
jnp .LBB3_8
.LBB3_11: # in Loop: Header=BB3_3 Depth=2
movl $1, %ebp
jmp .LBB3_12
.p2align 4, 0x90
.LBB3_4: # in Loop: Header=BB3_3 Depth=2
movl $1, %ebp
movb $1, %r15b
testb %r15b, %r15b
je .LBB3_5
jmp .LBB3_14
.p2align 4, 0x90
.LBB3_9: # in Loop: Header=BB3_3 Depth=2
xorl %ebp, %ebp
.LBB3_12: # %._crit_edge.loopexit
# in Loop: Header=BB3_3 Depth=2
cmpq %rcx, %r15
setb %r15b
testb %r15b, %r15b
jne .LBB3_14
.LBB3_5: # in Loop: Header=BB3_3 Depth=2
incq %r14
addl %edx, %ebx
cmpq %rcx, %r14
jne .LBB3_3
# %bb.6: # in Loop: Header=BB3_2 Depth=1
movl $5, %ebp
.LBB3_14: # %._crit_edge52
# in Loop: Header=BB3_2 Depth=1
cmpl $5, %ebp
je .LBB3_16
# %bb.15: # %._crit_edge52
# in Loop: Header=BB3_2 Depth=1
testl %ebp, %ebp
je .LBB3_16
.LBB3_17:
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB3_18: # %._crit_edge61
movzbl %al, %eax
andl $1, %eax
retq
.Lfunc_end3:
.size _Z6checkAPfS_i, .Lfunc_end3-_Z6checkAPfS_i
.cfi_endproc
# -- End function
.globl _Z4sumAPfi # -- Begin function _Z4sumAPfi
.p2align 4, 0x90
.type _Z4sumAPfi,@function
_Z4sumAPfi: # @_Z4sumAPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB4_1
# %bb.3: # %.lr.ph38
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %eax
movl %esi, %ecx
imull %esi, %ecx
movl %ecx, -12(%rsp) # 4-byte Spill
xorpd %xmm0, %xmm0
xorl %ebx, %ebx
movl $3435973837, %r8d # imm = 0xCCCCCCCD
xorl %r9d, %r9d
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB4_4: # %.lr.ph32.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_5 Depth 2
# Child Loop BB4_6 Depth 3
movl %r10d, %r11d
movq %rbx, -8(%rsp) # 8-byte Spill
# kill: def $ebx killed $ebx killed $rbx def $rbx
movl %r9d, %ebp
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_5: # %.lr.ph32
# Parent Loop BB4_4 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_6 Depth 3
movslq %ebp, %r15
leaq (%rdi,%r15,4), %r15
movl %r11d, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_6: # Parent Loop BB4_4 Depth=1
# Parent Loop BB4_5 Depth=2
# => This Inner Loop Header: Depth=3
movl %r12d, %ecx
imulq %r8, %rcx
shrq $35, %rcx
leal (%rcx,%rcx,4), %ecx
leal (%rbx,%rcx,2), %ecx
xorl %edx, %edx
cmpl %r13d, %ecx
setne %dl
leal -1(,%rdx,2), %ecx
xorps %xmm1, %xmm1
cvtsi2ss %ecx, %xmm1
mulss (%r15,%r13,4), %xmm1
cvtss2sd %xmm1, %xmm1
addsd %xmm1, %xmm0
incq %r13
incl %r12d
cmpq %r13, %rax
jne .LBB4_6
# %bb.7: # %._crit_edge
# in Loop: Header=BB4_5 Depth=2
incq %r14
addl %esi, %ebp
decl %ebx
incl %r11d
cmpq %rax, %r14
jne .LBB4_5
# %bb.8: # %._crit_edge33
# in Loop: Header=BB4_4 Depth=1
incq %r10
addl -12(%rsp), %r9d # 4-byte Folded Reload
movq -8(%rsp), %rbx # 8-byte Reload
decl %ebx
cmpq %rax, %r10
jne .LBB4_4
# %bb.9:
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
retq
.LBB4_1:
xorps %xmm0, %xmm0
retq
.Lfunc_end4:
.size _Z4sumAPfi, .Lfunc_end4-_Z4sumAPfi
.cfi_endproc
# -- End function
.globl _Z31__device_stub__jacobiRelaxationPfS_ii # -- Begin function _Z31__device_stub__jacobiRelaxationPfS_ii
.p2align 4, 0x90
.type _Z31__device_stub__jacobiRelaxationPfS_ii,@function
_Z31__device_stub__jacobiRelaxationPfS_ii: # @_Z31__device_stub__jacobiRelaxationPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16jacobiRelaxationPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end5:
.size _Z31__device_stub__jacobiRelaxationPfS_ii, .Lfunc_end5-_Z31__device_stub__jacobiRelaxationPfS_ii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI6_0:
.long 0x3f8ccccd # float 1.10000002
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI6_1:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 320
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB6_4
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
leal 1(%rax), %r13d
movl %r13d, %r12d
imull %r13d, %r12d
movl %r12d, 56(%rsp) # 4-byte Spill
imull %r13d, %r12d
movslq %r12d, %r15
leaq (,%r15,4), %rsi
movq $0, 24(%rsp)
leaq 24(%rsp), %rdi
movq %rsi, 72(%rsp) # 8-byte Spill
xorl %edx, %edx
callq hipHostAlloc
movq $0, 48(%rsp)
testl %eax, %eax
jne .LBB6_3
# %bb.2:
movl %ebx, %ebp
imull %ebx, %ebp
movl %ebp, %eax
imull %ebx, %eax
movslq %eax, %r14
leaq (,%r14,4), %rsi
leaq 48(%rsp), %rdi
movq %rsi, 8(%rsp) # 8-byte Spill
xorl %edx, %edx
callq hipHostAlloc
testl %eax, %eax
je .LBB6_7
.LBB6_3: # %.critedge
movl $.Lstr.3, %edi
jmp .LBB6_5
.LBB6_4:
movl $.Lstr.4, %edi
.LBB6_5:
callq puts@PLT
.LBB6_6:
xorl %eax, %eax
addq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB6_7:
.cfi_def_cfa_offset 320
movl %r12d, 84(%rsp) # 4-byte Spill
movq %r15, 120(%rsp) # 8-byte Spill
movq %r14, 112(%rsp) # 8-byte Spill
movl %ebp, 80(%rsp) # 4-byte Spill
movq %rbx, 64(%rsp) # 8-byte Spill
testl %ebx, %ebx
movq 8(%rsp), %r15 # 8-byte Reload
js .LBB6_16
# %bb.8: # %.lr.ph39.i
movq 24(%rsp), %rax
movl %r13d, %ecx
xorl %edx, %edx
movq $-3, %rsi
movss .LCPI6_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorl %edi, %edi
jmp .LBB6_10
.p2align 4, 0x90
.LBB6_9: # %._crit_edge36.i
# in Loop: Header=BB6_10 Depth=1
incq %rdi
movq 8(%rsp), %rdx # 8-byte Reload
addl 56(%rsp), %edx # 4-byte Folded Reload
incq %rsi
cmpq %rcx, %rdi
je .LBB6_16
.LBB6_10: # %.lr.ph35.i
# =>This Loop Header: Depth=1
# Child Loop BB6_12 Depth 2
# Child Loop BB6_14 Depth 3
movq %rsi, %r8
movq %rdx, 8(%rsp) # 8-byte Spill
movl %edx, %r9d
xorl %r10d, %r10d
jmp .LBB6_12
.p2align 4, 0x90
.LBB6_11: # %._crit_edge.i
# in Loop: Header=BB6_12 Depth=2
incq %r10
addl %r13d, %r9d
incq %r8
cmpq %rcx, %r10
je .LBB6_9
.LBB6_12: # %.lr.ph.i
# Parent Loop BB6_10 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB6_14 Depth 3
testq %rdi, %rdi
sete %bl
movslq %r9d, %r11
leaq (%rax,%r11,4), %r11
testq %r10, %r10
sete %r14b
orb %bl, %r14b
xorl %ebx, %ebx
jmp .LBB6_14
.p2align 4, 0x90
.LBB6_13: # in Loop: Header=BB6_14 Depth=3
movss %xmm1, (%r11,%rbx,4)
incq %rbx
cmpq %rbx, %rcx
je .LBB6_11
.LBB6_14: # Parent Loop BB6_10 Depth=1
# Parent Loop BB6_12 Depth=2
# => This Inner Loop Header: Depth=3
testq %rbx, %rbx
sete %r12b
orb %r14b, %r12b
xorps %xmm1, %xmm1
jne .LBB6_13
# %bb.15: # in Loop: Header=BB6_14 Depth=3
leal (%r8,%rbx), %r12d
movslq %r12d, %r12
movq %r15, %rdx
imulq $1717986919, %r12, %r15 # imm = 0x66666667
movq %r15, %rbp
shrq $63, %rbp
sarq $34, %r15
addl %ebp, %r15d
addl %r15d, %r15d
leal (%r15,%r15,4), %ebp
movq %rdx, %r15
subl %ebp, %r12d
xorps %xmm1, %xmm1
cvtsi2ss %r12d, %xmm1
mulss %xmm0, %xmm1
jmp .LBB6_13
.LBB6_16: # %_Z5initBPfi.exit
movq $0, 16(%rsp)
leaq 16(%rsp), %rdi
movq 72(%rsp), %rsi # 8-byte Reload
callq hipMalloc
movq $0, 40(%rsp)
movb $1, %cl
testl %eax, %eax
jne .LBB6_18
# %bb.17:
leaq 40(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
setne %cl
.LBB6_18:
testb %cl, %cl
movq 64(%rsp), %rsi # 8-byte Reload
movq 120(%rsp), %r14 # 8-byte Reload
movl 84(%rsp), %ebp # 4-byte Reload
je .LBB6_20
# %bb.19:
movl $.Lstr.2, %edi
jmp .LBB6_5
.LBB6_20:
movl %esi, %edx
shrl $31, %edx
addl %esi, %edx
movl %edx, %eax
sarl %eax
andl $-2, %edx
movl %esi, %r15d
subl %edx, %r15d
xorl %edx, %edx
.p2align 4, 0x90
.LBB6_21: # =>This Inner Loop Header: Depth=1
movl %eax, 32(%rsp,%rdx,4)
incq %rdx
cmpq $1, %rdx
je .LBB6_21
# %bb.22:
addl 36(%rsp), %r15d
movl %r15d, 36(%rsp)
movl $8, %eax
movabsq $4294967297, %rdx # imm = 0x100000001
.p2align 4, 0x90
.LBB6_23: # =>This Inner Loop Header: Depth=1
movq %rdx, 184(%rsp,%rax)
movl $1, 192(%rsp,%rax)
addq $12, %rax
cmpq $32, %rax
jne .LBB6_23
# %bb.24: # %.preheader151
leal -1(%rsi), %eax
shrl $5, %eax
incl %eax
leaq 200(%rsp), %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB6_25: # =>This Inner Loop Header: Depth=1
movl %eax, -8(%rdx)
movl %eax, -4(%rdx)
movl 32(%rsp,%rsi,4), %edi
movl %edi, (%rdx)
incq %rsi
addq $12, %rdx
cmpq $1, %rsi
je .LBB6_25
# %bb.26:
xorl %ebx, %ebx
jmp .LBB6_28
.p2align 4, 0x90
.LBB6_27: # in Loop: Header=BB6_28 Depth=1
addq $8, %rbx
cmpq $8, %rbx
jne .LBB6_30
.LBB6_28: # =>This Inner Loop Header: Depth=1
testb $1, %cl
movb $1, %cl
jne .LBB6_27
# %bb.29: # in Loop: Header=BB6_28 Depth=1
leaq (%rsp,%rbx), %rdi
addq $96, %rdi
callq hipStreamCreate
testl %eax, %eax
setne %cl
jmp .LBB6_27
.LBB6_30:
testb %cl, %cl
je .LBB6_32
# %bb.31:
movl $.Lstr.1, %edi
jmp .LBB6_5
.LBB6_32:
callq _Z12getTimeStampv
movsd %xmm0, 72(%rsp) # 8-byte Spill
movl 32(%rsp), %r13d
addl $2, %r13d
movl 56(%rsp), %ebx # 4-byte Reload
imull %ebx, %r13d
movslq %r13d, %r12
movq 16(%rsp), %rdi
movq 24(%rsp), %rsi
shlq $2, %r12
movq 96(%rsp), %r8
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpyAsync
movl %eax, 8(%rsp) # 4-byte Spill
movq 96(%rsp), %rdi
callq hipStreamSynchronize
decl %r15d
imull %ebx, %r15d
movb $1, %al
cmpl $0, 8(%rsp) # 4-byte Folded Reload
jne .LBB6_34
# %bb.33:
movslq %r15d, %rdx
shlq $2, %rdx
movq 16(%rsp), %rdi
addq %r12, %rdi
addq 24(%rsp), %r12
movq 104(%rsp), %r8
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpyAsync
testl %eax, %eax
setne %al
.LBB6_34:
addl %r15d, %r13d
cmpl %ebp, %r13d
movq 64(%rsp), %rbx # 8-byte Reload
jne .LBB6_38
# %bb.35:
testb %al, %al
je .LBB6_39
# %bb.36:
movl $.L.str.5, %edi
.LBB6_37:
movl $1, %esi
xorl %eax, %eax
callq printf
jmp .LBB6_6
.LBB6_38:
movl $.L.str.4, %edi
movl %r13d, %esi
movq %r14, %rdx
xorl %eax, %eax
callq printf
jmp .LBB6_6
.LBB6_39: # %.preheader150
leaq 200(%rsp), %r13
xorl %r12d, %r12d
movabsq $137438953504, %r14 # imm = 0x2000000020
leaq 224(%rsp), %r15
xorl %ebp, %ebp
jmp .LBB6_41
.LBB6_40: # in Loop: Header=BB6_41 Depth=1
movl 32(%rsp,%r12,4), %eax
addq %rax, %rbp
incq %r12
addq $12, %r13
cmpq $1, %r12
jne .LBB6_43
.LBB6_41: # =>This Inner Loop Header: Depth=1
movq -8(%r13), %rdi
movl (%r13), %esi
movq 96(%rsp,%r12,8), %r9
movl $13872, %r8d # imm = 0x3630
movq %r14, %rdx
movl $1, %ecx
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_40
# %bb.42: # in Loop: Header=BB6_41 Depth=1
movq 40(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 184(%rsp)
movq %rcx, 176(%rsp)
movl %ebx, 92(%rsp)
movl %ebp, 88(%rsp)
leaq 184(%rsp), %rax
movq %rax, 224(%rsp)
leaq 176(%rsp), %rax
movq %rax, 232(%rsp)
leaq 92(%rsp), %rax
movq %rax, 240(%rsp)
leaq 88(%rsp), %rax
movq %rax, 248(%rsp)
leaq 160(%rsp), %rdi
leaq 144(%rsp), %rsi
leaq 136(%rsp), %rdx
leaq 128(%rsp), %rcx
callq __hipPopCallConfiguration
movq 160(%rsp), %rsi
movl 168(%rsp), %edx
movq 144(%rsp), %rcx
movl 152(%rsp), %r8d
movl $_Z16jacobiRelaxationPfS_ii, %edi
movq %r15, %r9
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB6_40
.LBB6_43: # %.preheader149
xorl %r14d, %r14d
xorl %eax, %eax
xorl %r15d, %r15d
movl 80(%rsp), %ebp # 4-byte Reload
jmp .LBB6_45
.LBB6_44: # in Loop: Header=BB6_45 Depth=1
movzbl %cl, %eax
addq %rbx, %r15
incq %r14
cmpq $1, %r14
jne .LBB6_47
.LBB6_45: # =>This Inner Loop Header: Depth=1
movl 32(%rsp,%r14,4), %ecx
imull %ebp, %ecx
movslq %ecx, %rbx
movb $1, %cl
testl %eax, %eax
jne .LBB6_44
# %bb.46: # in Loop: Header=BB6_45 Depth=1
leaq (,%r15,4), %rsi
movq 48(%rsp), %rdi
addq %rsi, %rdi
addq 40(%rsp), %rsi
leaq (,%rbx,4), %rdx
movq 96(%rsp,%r14,8), %r8
movl $2, %ecx
callq hipMemcpyAsync
testl %eax, %eax
setne %cl
jmp .LBB6_44
.LBB6_47:
cmpq 112(%rsp), %r15 # 8-byte Folded Reload
jne .LBB6_50
# %bb.48:
testl %eax, %eax
je .LBB6_51
# %bb.49:
movl $.L.str.7, %edi
jmp .LBB6_37
.LBB6_50:
movl $.Lstr, %edi
jmp .LBB6_5
.LBB6_51: # %.preheader.preheader
xorl %ebx, %ebx
.LBB6_52: # %.preheader
# =>This Inner Loop Header: Depth=1
movq 96(%rsp,%rbx,8), %rdi
callq hipStreamSynchronize
incq %rbx
cmpq $1, %rbx
je .LBB6_52
# %bb.53:
callq _Z12getTimeStampv
movsd %xmm0, 8(%rsp) # 8-byte Spill
movq 40(%rsp), %rdi
callq hipFree
movq $0, 40(%rsp)
movq 16(%rsp), %rdi
callq hipFree
movq $0, 16(%rsp)
movq 48(%rsp), %rdi
movq 64(%rsp), %rsi # 8-byte Reload
# kill: def $esi killed $esi killed $rsi
callq _Z4sumAPfi
movsd %xmm0, 56(%rsp) # 8-byte Spill
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
subsd 72(%rsp), %xmm0 # 8-byte Folded Reload
mulsd .LCPI6_1(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %rsi
movl $.L.str.8, %edi
movsd 56(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movq 48(%rsp), %rdi
callq hipHostFree
movq $0, 48(%rsp)
movq 24(%rsp), %rdi
callq hipHostFree
movq $0, 24(%rsp)
callq hipDeviceReset
jmp .LBB6_6
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16jacobiRelaxationPfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16jacobiRelaxationPfS_ii,@object # @_Z16jacobiRelaxationPfS_ii
.section .rodata,"a",@progbits
.globl _Z16jacobiRelaxationPfS_ii
.p2align 3, 0x0
_Z16jacobiRelaxationPfS_ii:
.quad _Z31__device_stub__jacobiRelaxationPfS_ii
.size _Z16jacobiRelaxationPfS_ii, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "Error: hipMemcpyAsync does not cover entire B (%ld != %ld)\n"
.size .L.str.4, 60
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Error: hipMemcpyAsync B returns error %d\n"
.size .L.str.5, 42
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Error: hipMemcpyAsync A returns error %d\n"
.size .L.str.7, 42
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%lf %ld\n"
.size .L.str.8, 9
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16jacobiRelaxationPfS_ii"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Error: hipMemcpyAsync does not cover entire A"
.size .Lstr, 46
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Error: hipStreamCreate returns error"
.size .Lstr.1, 37
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Error: hipMalloc returns error"
.size .Lstr.2, 31
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Error: hipHostAlloc returns error"
.size .Lstr.3, 34
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Error: The number of arguments is not exactly 1"
.size .Lstr.4, 48
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__jacobiRelaxationPfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16jacobiRelaxationPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16jacobiRelaxationPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R10, SR_TID.X ; /* 0x00000000000a7919 */
/* 0x000e280000002100 */
/*0030*/ S2R R14, SR_CTAID.Z ; /* 0x00000000000e7919 */
/* 0x000e680000002700 */
/*0040*/ S2R R11, SR_TID.Z ; /* 0x00000000000b7919 */
/* 0x000e680000002300 */
/*0050*/ S2R R13, SR_CTAID.Y ; /* 0x00000000000d7919 */
/* 0x000ea80000002600 */
/*0060*/ S2R R12, SR_TID.Y ; /* 0x00000000000c7919 */
/* 0x000ea20000002200 */
/*0070*/ IMAD R0, R3, c[0x0][0x0], R10 ; /* 0x0000000003007a24 */
/* 0x001fe200078e020a */
/*0080*/ HFMA2.MMA R3, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff037435 */
/* 0x000fc800000001ff */
/*0090*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f06270 */
/*00a0*/ IMAD R14, R14, c[0x0][0x8], R11 ; /* 0x000002000e0e7a24 */
/* 0x002fca00078e020b */
/*00b0*/ IADD3 R3, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007ffe0ff */
/*00c0*/ IADD3 R14, R14, c[0x0][0x174], RZ ; /* 0x00005d000e0e7a10 */
/* 0x000fe20007ffe0ff */
/*00d0*/ IMAD R13, R13, c[0x0][0x4], R12 ; /* 0x000001000d0d7a24 */
/* 0x004fc600078e020c */
/*00e0*/ IADD3 R2, R14.reuse, 0x1, RZ ; /* 0x000000010e027810 */
/* 0x040fe40007ffe0ff */
/*00f0*/ ISETP.GE.OR P0, PT, R13.reuse, c[0x0][0x170], P0 ; /* 0x00005c000d007a0c */
/* 0x040fe40000706670 */
/*0100*/ IADD3 R4, R13, 0x1, RZ ; /* 0x000000010d047810 */
/* 0x000fe40007ffe0ff */
/*0110*/ ISETP.GE.OR P0, PT, R14, c[0x0][0x170], P0 ; /* 0x00005c000e007a0c */
/* 0x000fc60000706670 */
/*0120*/ IMAD R4, R3, R2, R4 ; /* 0x0000000203047224 */
/* 0x000fd400078e0204 */
/*0130*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0140*/ ISETP.NE.AND P3, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003f65270 */
/*0150*/ IMAD R4, R3.reuse, R4, R0 ; /* 0x0000000403047224 */
/* 0x040fe200078e0200 */
/*0160*/ ISETP.NE.AND P2, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f45270 */
/*0170*/ IMAD R2, R3, R3, RZ ; /* 0x0000000303027224 */
/* 0x000fe200078e02ff */
/*0180*/ ISETP.NE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f25270 */
/*0190*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*01a0*/ IADD3 R6, R4, 0x1, RZ ; /* 0x0000000104067810 */
/* 0x000fe40007ffe0ff */
/*01b0*/ MOV R15, 0x4 ; /* 0x00000004000f7802 */
/* 0x000fca0000000f00 */
/*01c0*/ @!P3 IADD3 R20, -R2.reuse, R6.reuse, RZ ; /* 0x000000060214b210 */
/* 0x0c0fe20007ffe1ff */
/*01d0*/ @!P3 IMAD R18, R2, c[0x0][0x8], R6.reuse ; /* 0x000002000212ba24 */
/* 0x100fe200078e0206 */
/*01e0*/ @!P2 IADD3 R8, -R3.reuse, R6, RZ ; /* 0x000000060308a210 */
/* 0x040fe20007ffe1ff */
/*01f0*/ @!P2 IMAD R2, R3, c[0x0][0x4], R6 ; /* 0x000001000302aa24 */
/* 0x000fe200078e0206 */
/*0200*/ @!P1 IADD3 R22, R6.reuse, c[0x0][0x0], RZ ; /* 0x0000000006169a10 */
/* 0x040fe20007ffe0ff */
/*0210*/ IMAD.WIDE R4, R6, R15, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e020f */
/*0220*/ @!P3 IMAD.WIDE R20, R20, R15.reuse, c[0x0][0x168] ; /* 0x00005a001414b625 */
/* 0x080fe200078e020f */
/*0230*/ LDG.E R16, [R4.64] ; /* 0x0000000604107981 */
/* 0x0000a6000c1e1900 */
/*0240*/ @!P3 IMAD.WIDE.U32 R18, R18, R15.reuse, c[0x0][0x168] ; /* 0x00005a001212b625 */
/* 0x080fe200078e000f */
/*0250*/ @!P3 LDG.E R17, [R20.64] ; /* 0x000000061411b981 */
/* 0x0002e6000c1e1900 */
/*0260*/ @!P2 IMAD.WIDE R8, R8, R15.reuse, c[0x0][0x168] ; /* 0x00005a000808a625 */
/* 0x080fe400078e020f */
/*0270*/ @!P3 LDG.E R18, [R18.64] ; /* 0x000000061212b981 */
/* 0x000964000c1e1900 */
/*0280*/ @!P2 IMAD.WIDE.U32 R6, R2, R15, c[0x0][0x168] ; /* 0x00005a000206a625 */
/* 0x000fc400078e000f */
/*0290*/ @!P2 LDG.E R8, [R8.64] ; /* 0x000000060808a981 */
/* 0x000164000c1e1900 */
/*02a0*/ @!P1 IMAD.WIDE.U32 R2, R22, R15, c[0x0][0x168] ; /* 0x00005a0016029625 */
/* 0x000fe400078e000f */
/*02b0*/ @!P2 LDG.E R6, [R6.64] ; /* 0x000000060606a981 */
/* 0x000168000c1e1900 */
/*02c0*/ @!P1 LDG.E R22, [R4.64+-0x4] ; /* 0xfffffc0604169981 */
/* 0x000168000c1e1900 */
/*02d0*/ @!P1 LDG.E R2, [R2.64] ; /* 0x0000000602029981 */
/* 0x000162000c1e1900 */
/*02e0*/ IMAD.MOV.U32 R25, RZ, RZ, 0x2 ; /* 0x00000002ff197424 */
/* 0x000fe200078e00ff */
/*02f0*/ IADD3 R24, R11, 0x1, RZ ; /* 0x000000010b187810 */
/* 0x000fc40007ffe0ff */
/*0300*/ IADD3 R23, R12, 0x1, RZ ; /* 0x000000010c177810 */
/* 0x000fe40007ffe0ff */
/*0310*/ IADD3 R11, R25.reuse, c[0x0][0x4], RZ ; /* 0x00000100190b7a10 */
/* 0x040fe20007ffe0ff */
/*0320*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe20000000000 */
/*0330*/ IADD3 R12, R25, c[0x0][0x0], RZ ; /* 0x00000000190c7a10 */
/* 0x000fe20007ffe0ff */
/*0340*/ ULDC UR5, c[0x0][0x170] ; /* 0x00005c0000057ab9 */
/* 0x000fe40000000800 */
/*0350*/ IMAD R23, R11, R24, R23 ; /* 0x000000180b177224 */
/* 0x000fe200078e0217 */
/*0360*/ UIADD3 UR4, -UR4, UR5, URZ ; /* 0x0000000504047290 */
/* 0x000fc6000fffe13f */
/*0370*/ IMAD R7, R12, R23, RZ ; /* 0x000000170c077224 */
/* 0x001fe400078e02ff */
/*0380*/ IMAD R5, R14, c[0x0][0x170], R13 ; /* 0x00005c000e057a24 */
/* 0x000fe200078e020d */
/*0390*/ ISETP.NE.AND P0, PT, R13, UR4, PT ; /* 0x000000040d007c0c */
/* 0x000fe2000bf05270 */
/*03a0*/ IMAD R11, R11, R12, RZ ; /* 0x0000000c0b0b7224 */
/* 0x000fe200078e02ff */
/*03b0*/ IADD3 R3, R7, R10, RZ ; /* 0x0000000a07037210 */
/* 0x000fe20007ffe0ff */
/*03c0*/ IMAD R4, R5, c[0x0][0x170], R0 ; /* 0x00005c0005047a24 */
/* 0x000fe200078e0200 */
/*03d0*/ ISETP.EQ.OR P0, PT, R0, UR4, !P0 ; /* 0x0000000400007c0c */
/* 0x000fe2000c702670 */
/*03e0*/ @!P3 IMAD R5, R11, c[0x0][0x8], RZ ; /* 0x000002000b05ba24 */
/* 0x000fe200078e02ff */
/*03f0*/ IADD3 R0, R3.reuse, 0x1, RZ ; /* 0x0000000103007810 */
/* 0x040fe40007ffe0ff */
/*0400*/ SHF.L.U32 R10, R3, 0x2, RZ ; /* 0x00000002030a7819 */
/* 0x000fe200000006ff */
/*0410*/ @!P2 IMAD R19, R12, c[0x0][0x4], RZ ; /* 0x000001000c13aa24 */
/* 0x010fe200078e02ff */
/*0420*/ ISETP.EQ.OR P0, PT, R14, UR4, P0 ; /* 0x000000040e007c0c */
/* 0x000fc40008702670 */
/*0430*/ IADD3 R14, -R11, R0.reuse, RZ ; /* 0x000000000b0e7210 */
/* 0x080fe20007ffe1ff */
/*0440*/ @!P3 IMAD R9, R5, 0x4, R10.reuse ; /* 0x000000040509b824 */
/* 0x100fe200078e020a */
/*0450*/ IADD3 R13, -R12, R0, RZ ; /* 0x000000000c0d7210 */
/* 0x000fe40007ffe1ff */
/*0460*/ @!P2 LEA R19, R19, R10, 0x2 ; /* 0x0000000a1313a211 */
/* 0x000fe200078e10ff */
/*0470*/ IMAD R21, R15, c[0x0][0x0], R10 ; /* 0x000000000f157a24 */
/* 0x002fe400078e020a */
/*0480*/ IMAD.WIDE R4, R4, R15, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe200078e020f */
/*0490*/ STS [R3.X4+0x4], R16 ; /* 0x0000041003007388 */
/* 0x0041e80000004800 */
/*04a0*/ @!P3 STS [R14.X4], R17 ; /* 0x000000110e00b388 */
/* 0x0081e80000004800 */
/*04b0*/ @!P3 STS [R9+0x4], R18 ; /* 0x000004120900b388 */
/* 0x0201e80000000800 */
/*04c0*/ @!P2 STS [R13.X4], R8 ; /* 0x000000080d00a388 */
/* 0x0001e80000004800 */
/*04d0*/ @!P2 STS [R19+0x4], R6 ; /* 0x000004061300a388 */
/* 0x0001e80000000800 */
/*04e0*/ @!P1 STS [R7.X4], R22 ; /* 0x0000001607009388 */
/* 0x0001e80000004800 */
/*04f0*/ @!P1 STS [R21+0x4], R2 ; /* 0x0000040215009388 */
/* 0x0001e80000000800 */
/*0500*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0510*/ @P0 BRA 0x610 ; /* 0x000000f000000947 */
/* 0x000fea0003800000 */
/*0520*/ LEA R10, R11, R10, 0x2 ; /* 0x0000000a0b0a7211 */
/* 0x001fe200078e10ff */
/*0530*/ LDS R14, [R14.X4] ; /* 0x000000000e0e7984 */
/* 0x000fe80000004800 */
/*0540*/ LDS R7, [R10+0x4] ; /* 0x000004000a077984 */
/* 0x000e280000000800 */
/*0550*/ LDS R0, [R13.X4] ; /* 0x000000000d007984 */
/* 0x000e680000004800 */
/*0560*/ LDS R21, [R21+0xc] ; /* 0x00000c0015157984 */
/* 0x000ea80000000800 */
/*0570*/ LDS R9, [R3.X4] ; /* 0x0000000003097984 */
/* 0x000ee80000004800 */
/*0580*/ LDS R11, [R3.X4+0x8] ; /* 0x00000800030b7984 */
/* 0x000f220000004800 */
/*0590*/ FADD R7, R14, R7 ; /* 0x000000070e077221 */
/* 0x001fc80000000000 */
/*05a0*/ FADD R0, R7, R0 ; /* 0x0000000007007221 */
/* 0x002fc80000000000 */
/*05b0*/ FADD R0, R0, R21 ; /* 0x0000001500007221 */
/* 0x004fc80000000000 */
/*05c0*/ FADD R0, R0, R9 ; /* 0x0000000900007221 */
/* 0x008fc80000000000 */
/*05d0*/ FADD R0, R0, R11 ; /* 0x0000000b00007221 */
/* 0x010fc80000000000 */
/*05e0*/ FMUL R7, R0, 0.80000001192092895508 ; /* 0x3f4ccccd00077820 */
/* 0x000fca0000400000 */
/*05f0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101906 */
/*0600*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0610*/ STG.E [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x001fe2000c101906 */
/*0620*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0630*/ BRA 0x630; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16jacobiRelaxationPfS_ii
.globl _Z16jacobiRelaxationPfS_ii
.p2align 8
.type _Z16jacobiRelaxationPfS_ii,@function
_Z16jacobiRelaxationPfS_ii:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v3, 0x3ff, v0
v_bfe_u32 v5, v0, 10, 10
v_bfe_u32 v9, v0, 20, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s2, 0xffff
s_lshr_b32 s9, s2, 16
s_and_b32 s10, s3, 0xffff
v_mad_u64_u32 v[0:1], null, s13, s7, v[3:4]
v_mad_u64_u32 v[1:2], null, s14, s9, v[5:6]
s_mul_i32 s15, s15, s10
s_mov_b32 s2, exec_lo
v_add3_u32 v8, s15, s5, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max3_i32 v2, v0, v1, v8
v_cmpx_gt_i32_e64 s4, v2
s_cbranch_execz .LBB0_10
s_add_i32 s6, s4, 1
s_load_b64 s[2:3], s[0:1], 0x8
s_mul_i32 s11, s6, s6
v_mad_u64_u32 v[6:7], null, s6, v1, s[6:7]
v_mul_lo_u32 v2, s11, v8
s_add_i32 s8, s9, 2
s_add_i32 s5, s7, 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_i32 s8, s8, s5
v_add3_u32 v2, v2, s11, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, v2, v0
v_add_nc_u32_e32 v2, 1, v5
v_add_nc_u32_e32 v6, 1, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_u32_u24_e32 v2, s5, v2
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[10:11], 2, v[6:7]
v_mul_lo_u32 v7, s8, v9
s_waitcnt lgkmcnt(0)
v_add_co_u32 v10, vcc_lo, s2, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v11, vcc_lo, s3, v11, vcc_lo
v_add3_u32 v7, v7, s8, v2
v_cmp_eq_u32_e32 vcc_lo, 0, v9
global_load_b32 v10, v[10:11], off
v_add3_u32 v2, v3, v7, 1
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v11, v2, 2, 0
v_subrev_nc_u32_e32 v9, s8, v2
s_waitcnt vmcnt(0)
ds_store_b32 v11, v10
s_and_saveexec_b32 s12, vcc_lo
s_cbranch_execz .LBB0_3
v_subrev_nc_u32_e32 v10, s11, v6
v_mad_u64_u32 v[12:13], null, s11, s10, v[6:7]
v_mov_b32_e32 v13, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], 2, v[10:11]
v_add_co_u32 v10, vcc_lo, s2, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v11, vcc_lo, s3, v11, vcc_lo
v_add_co_u32 v12, vcc_lo, s2, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s3, v13, vcc_lo
s_clause 0x1
global_load_b32 v14, v[10:11], off
global_load_b32 v12, v[12:13], off
v_mad_u64_u32 v[10:11], null, s8, s10, v[2:3]
v_lshl_add_u32 v11, v9, 2, 0
s_delay_alu instid0(VALU_DEP_2)
v_lshl_add_u32 v10, v10, 2, 0
s_waitcnt vmcnt(1)
ds_store_b32 v11, v14
s_waitcnt vmcnt(0)
ds_store_b32 v10, v12
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s12
v_subrev_nc_u32_e32 v10, s5, v2
s_mov_b32 s10, exec_lo
v_cmpx_eq_u32_e32 0, v5
s_cbranch_execz .LBB0_5
v_subrev_nc_u32_e32 v11, s4, v4
v_mad_u64_u32 v[13:14], null, s6, s9, v[6:7]
v_mov_b32_e32 v14, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v12, 31, v11
v_lshlrev_b64 v[13:14], 2, v[13:14]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_add_co_u32 v11, vcc_lo, s2, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v12, vcc_lo
v_add_co_u32 v13, vcc_lo, s2, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s3, v14, vcc_lo
s_clause 0x1
global_load_b32 v5, v[11:12], off
global_load_b32 v13, v[13:14], off
v_mad_u64_u32 v[11:12], null, s5, s9, v[2:3]
v_lshl_add_u32 v12, v10, 2, 0
s_delay_alu instid0(VALU_DEP_2)
v_lshl_add_u32 v11, v11, 2, 0
s_waitcnt vmcnt(1)
ds_store_b32 v12, v5
s_waitcnt vmcnt(0)
ds_store_b32 v11, v13
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s6, exec_lo
v_cmpx_eq_u32_e32 0, v3
s_cbranch_execz .LBB0_7
v_ashrrev_i32_e32 v5, 31, v4
v_dual_mov_b32 v12, 0 :: v_dual_add_nc_u32 v11, s7, v6
v_add_nc_u32_e32 v6, s7, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshl_add_u32 v6, v6, 2, 0
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_add_co_u32 v11, vcc_lo, s2, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v12, vcc_lo
s_clause 0x1
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[11:12], off
v_lshl_add_u32 v11, v7, 2, 0
s_waitcnt vmcnt(1)
ds_store_b32 v11, v4
s_waitcnt vmcnt(0)
ds_store_b32 v6, v5
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s6
s_add_i32 s3, s4, -1
v_mov_b32_e32 v4, 0
v_cmp_ne_u32_e32 vcc_lo, s3, v0
v_cmp_ne_u32_e64 s2, s3, v1
v_cmp_ne_u32_e64 s3, s3, v8
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s2, s3
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_9
v_add_nc_u32_e32 v4, s8, v2
v_lshl_add_u32 v5, v9, 2, 0
v_lshl_add_u32 v6, v10, 2, 0
s_delay_alu instid0(VALU_DEP_3)
v_lshl_add_u32 v4, v4, 2, 0
ds_load_b32 v5, v5
ds_load_b32 v4, v4
ds_load_b32 v6, v6
v_add_nc_u32_e32 v9, s5, v2
v_lshl_add_u32 v2, v2, 2, 0
s_waitcnt lgkmcnt(1)
v_add_f32_e32 v4, v5, v4
s_delay_alu instid0(VALU_DEP_3)
v_lshl_add_u32 v9, v9, 2, 0
v_add_nc_u32_e32 v3, v7, v3
ds_load_b32 v7, v9
s_waitcnt lgkmcnt(1)
v_add_f32_e32 v4, v4, v6
v_lshl_add_u32 v3, v3, 2, 0
ds_load_b32 v3, v3
ds_load_b32 v2, v2 offset:4
s_waitcnt lgkmcnt(2)
v_add_f32_e32 v4, v4, v7
s_waitcnt lgkmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v4, v3
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v4, 0x3f4ccccd, v2
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s2
v_mad_u64_u32 v[2:3], null, v8, s4, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v2, s4, v[0:1]
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16jacobiRelaxationPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16jacobiRelaxationPfS_ii, .Lfunc_end0-_Z16jacobiRelaxationPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16jacobiRelaxationPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16jacobiRelaxationPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include "cuda.h"
#define max(x,y) ((x) > (y)? (x) : (y))
#define min(x,y) ((x) < (y)? (x) : (y))
#define ceil(a,b) ((a) % (b) == 0 ? (a) / (b) : ((a) / (b)) + 1)
void check_error (const char* message) {
cudaError_t error = cudaGetLastError ();
if (error != cudaSuccess) {
printf ("CUDA error : %s, %s\n", message, cudaGetErrorString (error));
exit(-1);
}
}
__global__ void sw4 (float * __restrict__ uacc_0, float * __restrict__ uacc_1, float * __restrict__ uacc_2, float * __restrict__ u_0, float * __restrict__ u_1, float * __restrict__ u_2, float * __restrict__ mu, float * __restrict__ la, float * __restrict__ strx, float * __restrict__ stry, float * __restrict__ strz, int N) {
//Determing the block's indices
int blockdim_i= (int)(blockDim.x);
int i0 = (int)(blockIdx.x)*(blockdim_i);
int i = max (i0, 0) + (int)(threadIdx.x);
int blockdim_j= (int)(blockDim.y);
int j0 = (int)(blockIdx.y)*(blockdim_j);
int j = max (j0, 0) + (int)(threadIdx.y);
int blockdim_k= (int)(blockDim.z);
int k0 = (int)(blockIdx.z)*(blockdim_k);
int k = max (k0, 0) + (int)(threadIdx.z);
// Assumptions
int a1 = 1;
float h = 3.7;
float cof = 1e0 / ( h * h);
if (i>=2 & j>=2 & k>=2 & i<=N-3 & j<=N-3 & k<=N-3) {
/* 28 * 3 = 84 flops */
float mux1 = mu[k*N*N+j*N+i-1] * strx[i-1] - 3e0 / 4 * (mu[k*N*N+j*N+i] * strx[i] + mu[k*N*N+j*N+i-2] * strx[i-2]);
float mux2 = mu[k*N*N+j*N+i-2] * strx[i-2] + mu[k*N*N+j*N+i+1] * strx[i+1] + 3 * (mu[k*N*N+j*N+i] * strx[i] + mu[k*N*N+j*N+i-1] * strx[i-1]);
float mux3 = mu[k*N*N+j*N+i-1] * strx[i-1] + mu[k*N*N+j*N+i+2] * strx[i+2] + 3 * (mu[k*N*N+j*N+i+1] * strx[i+1] + mu[k*N*N+j*N+i] * strx[i]);
float mux4 = mu[k*N*N+j*N+i+1] * strx[i+1] - 3e0 / 4 * (mu[k*N*N+j*N+i] * strx[i] + mu[k*N*N+j*N+i+2] * strx[i+2]);
float muy1 = mu[k*N*N+(j-1)*N+i] * stry[j-1] - 3e0 / 4 * (mu[k*N*N+j*N+i] * stry[j] + mu[k*N*N+(j-2)*N+i] * stry[j-2]);
float muy2 = mu[k*N*N+(j-2)*N+i] * stry[j-2] + mu[k*N*N+(j+1)*N+i] * stry[j+1] + 3 * (mu[k*N*N+j*N+i] * stry[j] + mu[k*N*N+(j-1)*N+i] * stry[j-1]);
float muy3 = mu[k*N*N+(j-1)*N+i] * stry[j-1] + mu[k*N*N+(j+2)*N+i] * stry[j+2] + 3 * (mu[k*N*N+(j+1)*N+i] * stry[j+1] + mu[k*N*N+j*N+i] * stry[j]);
float muy4 = mu[k*N*N+(j+1)*N+i] * stry[j+1] - 3e0 / 4 * (mu[k*N*N+j*N+i] * stry[j] + mu[k*N*N+(j+2)*N+i] * stry[j+2]);
float muz1 = mu[(k-1)*N*N+j*N+i] * strz[k-1] - 3e0 / 4 * (mu[k*N*N+j*N+i] * strz[k] + mu[(k-2)*N*N+j*N+i] * strz[k-2]);
float muz2 = mu[(k-2)*N*N+j*N+i] * strz[k-2] + mu[(k+1)*N*N+j*N+i] * strz[k+1] + 3 * (mu[k*N*N+j*N+i] * strz[k] + mu[(k-1)*N*N+j*N+i] * strz[k-1]);
float muz3 = mu[(k-1)*N*N+j*N+i] * strz[k-1] + mu[(k+2)*N*N+j*N+i] * strz[k+2] + 3 * (mu[(k+1)*N*N+j*N+i] * strz[k+1] + mu[k*N*N+j*N+i] * strz[k]);
float muz4 = mu[(k+1)*N*N+j*N+i] * strz[k+1] - 3e0 / 4 * (mu[k*N*N+j*N+i] * strz[k] + mu[(k+2)*N*N+j*N+i] * strz[k+2]);
/* 78 * 3 = 234 flops */
float r1 = 1e0 / 6 * (strx[i] * ((2 * mux1 + la[k*N*N+j*N+i-1] * strx[i-1] - 3e0 / 4 * (la[k*N*N+j*N+i] * strx[i] + la[k*N*N+j*N+i-2] * strx[i-2])) * (u_0[k*N*N+j*N+i-2] - u_0[k*N*N+j*N+i]) + (2 * mux2 + la[k*N*N+j*N+i-2] * strx[i-2] + la[k*N*N+j*N+i+1] * strx[i+1] + 3 * (la[k*N*N+j*N+i] * strx[i] + la[k*N*N+j*N+i-1] * strx[i-1])) * (u_0[k*N*N+j*N+i-1] - u_0[k*N*N+j*N+i]) + (2 * mux3 + la[k*N*N+j*N+i-1] * strx[i-1] + la[k*N*N+j*N+i+2] * strx[i+2] + 3 * (la[k*N*N+j*N+i+1] * strx[i+1] + la[k*N*N+j*N+i] * strx[i])) * (u_0[k*N*N+j*N+i+1] - u_0[k*N*N+j*N+i]) + (2 * mux4 + la[k*N*N+j*N+i+1] * strx[i+1] - 3e0 / 4 * (la[k*N*N+j*N+i] * strx[i] + la[k*N*N+j*N+i+2] * strx[i+2])) * (u_0[k*N*N+j*N+i+2] - u_0[k*N*N+j*N+i])) + stry[j] * (muy1 * (u_0[k*N*N+(j-2)*N+i] - u_0[k*N*N+j*N+i]) + muy2 * (u_0[k*N*N+(j-1)*N+i] - u_0[k*N*N+j*N+i]) + muy3 * (u_0[k*N*N+(j+1)*N+i] - u_0[k*N*N+j*N+i]) + muy4 * (u_0[k*N*N+(j+2)*N+i] - u_0[k*N*N+j*N+i])) + strz[k] * (muz1 * (u_0[(k-2)*N*N+j*N+i] - u_0[k*N*N+j*N+i]) + muz2 * (u_0[(k-1)*N*N+j*N+i] - u_0[k*N*N+j*N+i]) + muz3 * (u_0[(k+1)*N*N+j*N+i] - u_0[k*N*N+j*N+i]) + muz4 * (u_0[(k+2)*N*N+j*N+i] - u_0[k*N*N+j*N+i])));
float r2 = 1e0 / 6 * (strx[i] * (mux1 * (u_1[k*N*N+j*N+i-2] - u_1[k*N*N+j*N+i]) + mux2 * (u_1[k*N*N+j*N+i-1] - u_1[k*N*N+j*N+i]) + mux3 * (u_1[k*N*N+j*N+i+1] - u_1[k*N*N+j*N+i]) + mux4 * (u_1[k*N*N+j*N+i+2] - u_1[k*N*N+j*N+i])) + stry[j] * ((2 * muy1 + la[k*N*N+(j-1)*N+i] * stry[j-1] - 3e0 / 4 * (la[k*N*N+j*N+i] * stry[j] + la[k*N*N+(j-2)*N+i] * stry[j-2])) * (u_1[k*N*N+(j-2)*N+i] - u_1[k*N*N+j*N+i]) + (2 * muy2 + la[k*N*N+(j-2)*N+i] * stry[j-2] + la[k*N*N+(j+1)*N+i] * stry[j+1] + 3 * (la[k*N*N+j*N+i] * stry[j] + la[k*N*N+(j-1)*N+i] * stry[j-1])) * (u_1[k*N*N+(j-1)*N+i] - u_1[k*N*N+j*N+i]) + (2 * muy3 + la[k*N*N+(j-1)*N+i] * stry[j-1] + la[k*N*N+(j+2)*N+i] * stry[j+2] + 3 * (la[k*N*N+(j+1)*N+i] * stry[j+1] + la[k*N*N+j*N+i] * stry[j])) * (u_1[k*N*N+(j+1)*N+i] - u_1[k*N*N+j*N+i]) + (2 * muy4 + la[k*N*N+(j+1)*N+i] * stry[j+1] - 3e0 / 4 * (la[k*N*N+j*N+i] * stry[j] + la[k*N*N+(j+2)*N+i] * stry[j+2])) * (u_1[k*N*N+(j+2)*N+i] - u_1[k*N*N+j*N+i])) + strz[k] * (muz1 * (u_1[(k-2)*N*N+j*N+i] - u_1[k*N*N+j*N+i]) + muz2 * (u_1[(k-1)*N*N+j*N+i] - u_1[k*N*N+j*N+i]) + muz3 * (u_1[(k+1)*N*N+j*N+i] - u_1[k*N*N+j*N+i]) + muz4 * (u_1[(k+2)*N*N+j*N+i] - u_1[k*N*N+j*N+i])));
float r3 = 1e0 / 6 * (strx[i] * (mux1 * (u_2[k*N*N+j*N+i-2] - u_2[k*N*N+j*N+i]) + mux2 * (u_2[k*N*N+j*N+i-1] - u_2[k*N*N+j*N+i]) + mux3 * (u_2[k*N*N+j*N+i+1] - u_2[k*N*N+j*N+i]) + mux4 * (u_2[k*N*N+j*N+i+2] - u_2[k*N*N+j*N+i])) + stry[j] * (muy1 * (u_2[k*N*N+(j-2)*N+i] - u_2[k*N*N+j*N+i]) + muy2 * (u_2[k*N*N+(j-1)*N+i] - u_2[k*N*N+j*N+i]) + muy3 * (u_2[k*N*N+(j+1)*N+i] - u_2[k*N*N+j*N+i]) + muy4 * (u_2[k*N*N+(j+2)*N+i] - u_2[k*N*N+j*N+i])) + strz[k] * ((2 * muz1 + la[(k-1)*N*N+j*N+i] * strz[k-1] - 3e0 / 4 * (la[k*N*N+j*N+i] * strz[k] + la[(k-2)*N*N+j*N+i] * strz[k-2])) * (u_2[(k-2)*N*N+j*N+i] - u_2[k*N*N+j*N+i]) + (2 * muz2 + la[(k-2)*N*N+j*N+i] * strz[k-2] + la[(k+1)*N*N+j*N+i] * strz[k+1] + 3 * (la[k*N*N+j*N+i] * strz[k] + la[(k-1)*N*N+j*N+i] * strz[k-1])) * (u_2[(k-1)*N*N+j*N+i] - u_2[k*N*N+j*N+i]) + (2 * muz3 + la[(k-1)*N*N+j*N+i] * strz[k-1] + la[(k+2)*N*N+j*N+i] * strz[k+2] + 3 * (la[(k+1)*N*N+j*N+i] * strz[k+1] + la[k*N*N+j*N+i] * strz[k])) * (u_2[(k+1)*N*N+j*N+i] - u_2[k*N*N+j*N+i]) + (2 * muz4 + la[(k+1)*N*N+j*N+i] * strz[k+1] - 3e0 / 4 * (la[k*N*N+j*N+i] * strz[k] + la[(k+2)*N*N+j*N+i] * strz[k+2])) * (u_2[(k+2)*N*N+j*N+i] - u_2[k*N*N+j*N+i])));
/* 120 * 3 = 360 flops */
r1 = r1 + strx[i] * stry[j] * (1e0 / 144) * (la[k*N*N+j*N+i-2] * (u_1[k*N*N+(j-2)*N+i-2] - u_1[k*N*N+(j+2)*N+i-2] + 8 * (-u_1[k*N*N+(j-1)*N+i-2] + u_1[k*N*N+(j+1)*N+i-2])) - 8 * (la[k*N*N+j*N+i-1] * (u_1[k*N*N+(j-2)*N+i-1] - u_1[k*N*N+(j+2)*N+i-1] + 8 * (-u_1[k*N*N+(j-1)*N+i-1] + u_1[k*N*N+(j+1)*N+i-1]))) + 8 * (la[k*N*N+j*N+i+1] * (u_1[k*N*N+(j-2)*N+i+1] - u_1[k*N*N+(j+2)*N+i+1] + 8 * (-u_1[k*N*N+(j-1)*N+i+1] + u_1[k*N*N+(j+1)*N+i+1]))) - (la[k*N*N+j*N+i+2] * (u_1[k*N*N+(j-2)*N+i+2] - u_1[k*N*N+(j+2)*N+i+2] + 8 * (-u_1[k*N*N+(j-1)*N+i+2] + u_1[k*N*N+(j+1)*N+i+2])))) + strx[i] * strz[k] * (1e0 / 144) * (la[k*N*N+j*N+i-2] * (u_2[(k-2)*N*N+j*N+i-2] - u_2[(k+2)*N*N+j*N+i-2] + 8 * (-u_2[(k-1)*N*N+j*N+i-2] + u_2[(k+1)*N*N+j*N+i-2])) - 8 * (la[k*N*N+j*N+i-1] * (u_2[(k-2)*N*N+j*N+i-1] - u_2[(k+2)*N*N+j*N+i-1] + 8 * (-u_2[(k-1)*N*N+j*N+i-1] + u_2[(k+1)*N*N+j*N+i-1]))) + 8 * (la[k*N*N+j*N+i+1] * (u_2[(k-2)*N*N+j*N+i+1] - u_2[(k+2)*N*N+j*N+i+1] + 8 * (-u_2[(k-1)*N*N+j*N+i+1] + u_2[(k+1)*N*N+j*N+i+1]))) - (la[k*N*N+j*N+i+2] * (u_2[(k-2)*N*N+j*N+i+2] - u_2[(k+2)*N*N+j*N+i+2] + 8 * (-u_2[(k-1)*N*N+j*N+i+2] + u_2[(k+1)*N*N+j*N+i+2])))) + strx[i] * stry[j] * (1e0 / 144) * (mu[k*N*N+(j-2)*N+i] * (u_1[k*N*N+(j-2)*N+i-2] - u_1[k*N*N+(j-2)*N+i+2] + 8 * (-u_1[k*N*N+(j-2)*N+i-1] + u_1[k*N*N+(j-2)*N+i+1])) - 8 * (mu[k*N*N+(j-1)*N+i] * (u_1[k*N*N+(j-1)*N+i-2] - u_1[k*N*N+(j-1)*N+i+2] + 8 * (-u_1[k*N*N+(j-1)*N+i-1] + u_1[k*N*N+(j-1)*N+i+1]))) + 8 * (mu[k*N*N+(j+1)*N+i] * (u_1[k*N*N+(j+1)*N+i-2] - u_1[k*N*N+(j+1)*N+i+2] + 8 * (-u_1[k*N*N+(j+1)*N+i-1] + u_1[k*N*N+(j+1)*N+i+1]))) - (mu[k*N*N+(j+2)*N+i] * (u_1[k*N*N+(j+2)*N+i-2] - u_1[k*N*N+(j+2)*N+i+2] + 8 * (-u_1[k*N*N+(j+2)*N+i-1] + u_1[k*N*N+(j+2)*N+i+1])))) + strx[i] * strz[k] * (1e0 / 144) * (mu[(k-2)*N*N+j*N+i] * (u_2[(k-2)*N*N+j*N+i-2] - u_2[(k-2)*N*N+j*N+i+2] + 8 * (-u_2[(k-2)*N*N+j*N+i-1] + u_2[(k-2)*N*N+j*N+i+1])) - 8 * (mu[(k-1)*N*N+j*N+i] * (u_2[(k-1)*N*N+j*N+i-2] - u_2[(k-1)*N*N+j*N+i+2] + 8 * (-u_2[(k-1)*N*N+j*N+i-1] + u_2[(k-1)*N*N+j*N+i+1]))) + 8 * (mu[(k+1)*N*N+j*N+i] * (u_2[(k+1)*N*N+j*N+i-2] - u_2[(k+1)*N*N+j*N+i+2] + 8 * (-u_2[(k+1)*N*N+j*N+i-1] + u_2[(k+1)*N*N+j*N+i+1]))) - (mu[(k+2)*N*N+j*N+i] * (u_2[(k+2)*N*N+j*N+i-2] - u_2[(k+2)*N*N+j*N+i+2] + 8 * (-u_2[(k+2)*N*N+j*N+i-1] + u_2[(k+2)*N*N+j*N+i+1]))));
r2 = r2 + strx[i] * stry[j] * (1e0 / 144) * (mu[k*N*N+j*N+i-2] * (u_0[k*N*N+(j-2)*N+i-2] - u_0[k*N*N+(j+2)*N+i-2] + 8 * (-u_0[k*N*N+(j-1)*N+i-2] + u_0[k*N*N+(j+1)*N+i-2])) - 8 * (mu[k*N*N+j*N+i-1] * (u_0[k*N*N+(j-2)*N+i-1] - u_0[k*N*N+(j+2)*N+i-1] + 8 * (-u_0[k*N*N+(j-1)*N+i-1] + u_0[k*N*N+(j+1)*N+i-1]))) + 8 * (mu[k*N*N+j*N+i+1] * (u_0[k*N*N+(j-2)*N+i+1] - u_0[k*N*N+(j+2)*N+i+1] + 8 * (-u_0[k*N*N+(j-1)*N+i+1] + u_0[k*N*N+(j+1)*N+i+1]))) - (mu[k*N*N+j*N+i+2] * (u_0[k*N*N+(j-2)*N+i+2] - u_0[k*N*N+(j+2)*N+i+2] + 8 * (-u_0[k*N*N+(j-1)*N+i+2] + u_0[k*N*N+(j+1)*N+i+2])))) + strx[i] * stry[j] * (1e0 / 144) * (la[k*N*N+(j-2)*N+i] * (u_0[k*N*N+(j-2)*N+i-2] - u_0[k*N*N+(j-2)*N+i+2] + 8 * (-u_0[k*N*N+(j-2)*N+i-1] + u_0[k*N*N+(j-2)*N+i+1])) - 8 * (la[k*N*N+(j-1)*N+i] * (u_0[k*N*N+(j-1)*N+i-2] - u_0[k*N*N+(j-1)*N+i+2] + 8 * (-u_0[k*N*N+(j-1)*N+i-1] + u_0[k*N*N+(j-1)*N+i+1]))) + 8 * (la[k*N*N+(j+1)*N+i] * (u_0[k*N*N+(j+1)*N+i-2] - u_0[k*N*N+(j+1)*N+i+2] + 8 * (-u_0[k*N*N+(j+1)*N+i-1] + u_0[k*N*N+(j+1)*N+i+1]))) - (la[k*N*N+(j+2)*N+i] * (u_0[k*N*N+(j+2)*N+i-2] - u_0[k*N*N+(j+2)*N+i+2] + 8 * (-u_0[k*N*N+(j+2)*N+i-1] + u_0[k*N*N+(j+2)*N+i+1])))) + stry[j] * strz[k] * (1e0 / 144) * (la[k*N*N+(j-2)*N+i] * (u_2[(k-2)*N*N+(j-2)*N+i] - u_2[(k+2)*N*N+(j-2)*N+i] + 8 * (-u_2[(k-1)*N*N+(j-2)*N+i] + u_2[(k+1)*N*N+(j-2)*N+i])) - 8 * (la[k*N*N+(j-1)*N+i] * (u_2[(k-2)*N*N+(j-1)*N+i] - u_2[(k+2)*N*N+(j-1)*N+i] + 8 * (-u_2[(k-1)*N*N+(j-1)*N+i] + u_2[(k+1)*N*N+(j-1)*N+i]))) + 8 * (la[k*N*N+(j+1)*N+i] * (u_2[(k-2)*N*N+(j+1)*N+i] - u_2[(k+2)*N*N+(j+1)*N+i] + 8 * (-u_2[(k-1)*N*N+(j+1)*N+i] + u_2[(k+1)*N*N+(j+1)*N+i]))) - (la[k*N*N+(j+2)*N+i] * (u_2[(k-2)*N*N+(j+2)*N+i] - u_2[(k+2)*N*N+(j+2)*N+i] + 8 * (-u_2[(k-1)*N*N+(j+2)*N+i] + u_2[(k+1)*N*N+(j+2)*N+i])))) + stry[j] * strz[k] * (1e0 / 144) * (mu[(k-2)*N*N+j*N+i] * (u_2[(k-2)*N*N+(j-2)*N+i] - u_2[(k-2)*N*N+(j+2)*N+i] + 8 * (-u_2[(k-2)*N*N+(j-1)*N+i] + u_2[(k-2)*N*N+(j+1)*N+i])) - 8 * (mu[(k-1)*N*N+j*N+i] * (u_2[(k-1)*N*N+(j-2)*N+i] - u_2[(k-1)*N*N+(j+2)*N+i] + 8 * (-u_2[(k-1)*N*N+(j-1)*N+i] + u_2[(k-1)*N*N+(j+1)*N+i]))) + 8 * (mu[(k+1)*N*N+j*N+i] * (u_2[(k+1)*N*N+(j-2)*N+i] - u_2[(k+1)*N*N+(j+2)*N+i] + 8 * (-u_2[(k+1)*N*N+(j-1)*N+i] + u_2[(k+1)*N*N+(j+1)*N+i]))) - (mu[(k+2)*N*N+j*N+i] * (u_2[(k+2)*N*N+(j-2)*N+i] - u_2[(k+2)*N*N+(j+2)*N+i] + 8 * (-u_2[(k+2)*N*N+(j-1)*N+i] + u_2[(k+2)*N*N+(j+1)*N+i]))));
r3 = r3 + strx[i] * strz[k] * (1e0 / 144) * (mu[k*N*N+j*N+i-2] * (u_0[(k-2)*N*N+j*N+i-2] - u_0[(k+2)*N*N+j*N+i-2] + 8 * (-u_0[(k-1)*N*N+j*N+i-2] + u_0[(k+1)*N*N+j*N+i-2])) - 8 * (mu[k*N*N+j*N+i-1] * (u_0[(k-2)*N*N+j*N+i-1] - u_0[(k+2)*N*N+j*N+i-1] + 8 * (-u_0[(k-1)*N*N+j*N+i-1] + u_0[(k+1)*N*N+j*N+i-1]))) + 8 * (mu[k*N*N+j*N+i+1] * (u_0[(k-2)*N*N+j*N+i+1] - u_0[(k+2)*N*N+j*N+i+1] + 8 * (-u_0[(k-1)*N*N+j*N+i+1] + u_0[(k+1)*N*N+j*N+i+1]))) - (mu[k*N*N+j*N+i+2] * (u_0[(k-2)*N*N+j*N+i+2] - u_0[(k+2)*N*N+j*N+i+2] + 8 * (-u_0[(k-1)*N*N+j*N+i+2] + u_0[(k+1)*N*N+j*N+i+2])))) + stry[j] * strz[k] * (1e0 / 144) * (mu[k*N*N+(j-2)*N+i] * (u_1[(k-2)*N*N+(j-2)*N+i] - u_1[(k+2)*N*N+(j-2)*N+i] + 8 * (-u_1[(k-1)*N*N+(j-2)*N+i] + u_1[(k+1)*N*N+(j-2)*N+i])) - 8 * (mu[k*N*N+(j-1)*N+i] * (u_1[(k-2)*N*N+(j-1)*N+i] - u_1[(k+2)*N*N+(j-1)*N+i] + 8 * (-u_1[(k-1)*N*N+(j-1)*N+i] + u_1[(k+1)*N*N+(j-1)*N+i]))) + 8 * (mu[k*N*N+(j+1)*N+i] * (u_1[(k-2)*N*N+(j+1)*N+i] - u_1[(k+2)*N*N+(j+1)*N+i] + 8 * (-u_1[(k-1)*N*N+(j+1)*N+i] + u_1[(k+1)*N*N+(j+1)*N+i]))) - (mu[k*N*N+(j+2)*N+i] * (u_1[(k-2)*N*N+(j+2)*N+i] - u_1[(k+2)*N*N+(j+2)*N+i] + 8 * (-u_1[(k-1)*N*N+(j+2)*N+i] + u_1[(k+1)*N*N+(j+2)*N+i])))) + strx[i] * strz[k] * (1e0 / 144) * (la[(k-2)*N*N+j*N+i] * (u_0[(k-2)*N*N+j*N+i-2] - u_0[(k-2)*N*N+j*N+i+2] + 8 * (-u_0[(k-2)*N*N+j*N+i-1] + u_0[(k-2)*N*N+j*N+i+1])) - 8 * (la[(k-1)*N*N+j*N+i] * (u_0[(k-1)*N*N+j*N+i-2] - u_0[(k-1)*N*N+j*N+i+2] + 8 * (-u_0[(k-1)*N*N+j*N+i-1] + u_0[(k-1)*N*N+j*N+i+1]))) + 8 * (la[(k+1)*N*N+j*N+i] * (u_0[(k+1)*N*N+j*N+i-2] - u_0[(k+1)*N*N+j*N+i+2] + 8 * (-u_0[(k+1)*N*N+j*N+i-1] + u_0[(k+1)*N*N+j*N+i+1]))) - (la[(k+2)*N*N+j*N+i] * (u_0[(k+2)*N*N+j*N+i-2] - u_0[(k+2)*N*N+j*N+i+2] + 8 * (-u_0[(k+2)*N*N+j*N+i-1] + u_0[(k+2)*N*N+j*N+i+1])))) + stry[j] * strz[k] * (1e0 / 144) * (la[(k-2)*N*N+j*N+i] * (u_1[(k-2)*N*N+(j-2)*N+i] - u_1[(k-2)*N*N+(j+2)*N+i] + 8 * (-u_1[(k-2)*N*N+(j-1)*N+i] + u_1[(k-2)*N*N+(j+1)*N+i])) - 8 * (la[(k-1)*N*N+j*N+i] * (u_1[(k-1)*N*N+(j-2)*N+i] - u_1[(k-1)*N*N+(j+2)*N+i] + 8 * (-u_1[(k-1)*N*N+(j-1)*N+i] + u_1[(k-1)*N*N+(j+1)*N+i]))) + 8 * (la[(k+1)*N*N+j*N+i] * (u_1[(k+1)*N*N+(j-2)*N+i] - u_1[(k+1)*N*N+(j+2)*N+i] + 8 * (-u_1[(k+1)*N*N+(j-1)*N+i] + u_1[(k+1)*N*N+(j+1)*N+i]))) - (la[(k+2)*N*N+j*N+i] * (u_1[(k+2)*N*N+(j-2)*N+i] - u_1[(k+2)*N*N+(j+2)*N+i] + 8 * (-u_1[(k+2)*N*N+(j-1)*N+i] + u_1[(k+2)*N*N+(j+1)*N+i]))));
/* 3 * 3 = 9 flops */
uacc_0[k*N*N+j*N+i] = a1 * uacc_0[k*N*N+j*N+i] + cof * r1;
uacc_1[k*N*N+j*N+i] = a1 * uacc_1[k*N*N+j*N+i] + cof * r2;
uacc_2[k*N*N+j*N+i] = a1 * uacc_2[k*N*N+j*N+i] + cof * r3;
}
}
extern "C" void host_code (float *h_uacc_0, float *h_uacc_1, float *h_uacc_2, float *h_u_0, float *h_u_1, float *h_u_2, float *h_mu, float *h_la, float *h_strx, float *h_stry, float *h_strz, int N) {
float *uacc_0;
cudaMalloc (&uacc_0, sizeof(float)*N*N*N);
check_error ("Failed to allocate device memory for uacc_0\n");
cudaMemcpy (uacc_0, h_uacc_0, sizeof(float)*N*N*N, cudaMemcpyHostToDevice);
float *uacc_1;
cudaMalloc (&uacc_1, sizeof(float)*N*N*N);
check_error ("Failed to allocate device memory for uacc_1\n");
cudaMemcpy (uacc_1, h_uacc_1, sizeof(float)*N*N*N, cudaMemcpyHostToDevice);
float *uacc_2;
cudaMalloc (&uacc_2, sizeof(float)*N*N*N);
check_error ("Failed to allocate device memory for uacc_2\n");
cudaMemcpy (uacc_2, h_uacc_2, sizeof(float)*N*N*N, cudaMemcpyHostToDevice);
float *u_0;
cudaMalloc (&u_0, sizeof(float)*N*N*N);
check_error ("Failed to allocate device memory for u_0\n");
cudaMemcpy (u_0, h_u_0, sizeof(float)*N*N*N, cudaMemcpyHostToDevice);
float *u_1;
cudaMalloc (&u_1, sizeof(float)*N*N*N);
check_error ("Failed to allocate device memory for u_1\n");
cudaMemcpy (u_1, h_u_1, sizeof(float)*N*N*N, cudaMemcpyHostToDevice);
float *u_2;
cudaMalloc (&u_2, sizeof(float)*N*N*N);
check_error ("Failed to allocate device memory for u_2\n");
cudaMemcpy (u_2, h_u_2, sizeof(float)*N*N*N, cudaMemcpyHostToDevice);
float *mu;
cudaMalloc (&mu, sizeof(float)*N*N*N);
check_error ("Failed to allocate device memory for mu\n");
cudaMemcpy (mu, h_mu, sizeof(float)*N*N*N, cudaMemcpyHostToDevice);
float *la;
cudaMalloc (&la, sizeof(float)*N*N*N);
check_error ("Failed to allocate device memory for la\n");
cudaMemcpy (la, h_la, sizeof(float)*N*N*N, cudaMemcpyHostToDevice);
float *strx;
cudaMalloc (&strx, sizeof(float)*N);
check_error ("Failed to allocate device memory for strx\n");
cudaMemcpy (strx, h_strx, sizeof(float)*N, cudaMemcpyHostToDevice);
float *stry;
cudaMalloc (&stry, sizeof(float)*N);
check_error ("Failed to allocate device memory for stry\n");
cudaMemcpy (stry, h_stry, sizeof(float)*N, cudaMemcpyHostToDevice);
float *strz;
cudaMalloc (&strz, sizeof(float)*N);
check_error ("Failed to allocate device memory for strz\n");
cudaMemcpy (strz, h_strz, sizeof(float)*N, cudaMemcpyHostToDevice);
dim3 blockconfig (32, 4, 2);
dim3 gridconfig (ceil(N, blockconfig.x), ceil(N, blockconfig.y), ceil(N, blockconfig.z));
sw4 <<<gridconfig, blockconfig>>> (uacc_0, uacc_1, uacc_2, u_0, u_1, u_2, mu, la, strx, stry, strz, N);
cudaMemcpy (h_uacc_0, uacc_0, sizeof(float)*N*N*N, cudaMemcpyDeviceToHost);
cudaMemcpy (h_uacc_1, uacc_1, sizeof(float)*N*N*N, cudaMemcpyDeviceToHost);
cudaMemcpy (h_uacc_2, uacc_2, sizeof(float)*N*N*N, cudaMemcpyDeviceToHost);
cudaFree (uacc_0);
cudaFree (uacc_1);
cudaFree (uacc_2);
cudaFree (u_0);
cudaFree (u_1);
cudaFree (u_2);
cudaFree (mu);
cudaFree (la);
cudaFree (strx);
cudaFree (stry);
cudaFree (strz);
} | .file "tmpxft_000619c4_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA error : %s, %s\n"
.text
.globl _Z11check_errorPKc
.type _Z11check_errorPKc, @function
_Z11check_errorPKc:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movq %rbx, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z11check_errorPKc, .-_Z11check_errorPKc
.globl _Z43__device_stub__Z3sw4PfS_S_S_S_S_S_S_S_S_S_iPfS_S_S_S_S_S_S_S_S_S_i
.type _Z43__device_stub__Z3sw4PfS_S_S_S_S_S_S_S_S_S_iPfS_S_S_S_S_S_S_S_S_S_i, @function
_Z43__device_stub__Z3sw4PfS_S_S_S_S_S_S_S_S_S_iPfS_S_S_S_S_S_S_S_S_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $280, %rsp
.cfi_def_cfa_offset 288
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
movq %rdi, 8(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movq %rsi, 16(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
movq %rdx, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 176(%rsp)
movq %rcx, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
movq %r8, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 192(%rsp)
movq %r9, 48(%rsp)
leaq 48(%rsp), %rax
movq %rax, 200(%rsp)
movq 288(%rsp), %rax
movq %rax, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 208(%rsp)
movq 296(%rsp), %rax
movq %rax, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, 216(%rsp)
movq 304(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 224(%rsp)
movq 312(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 232(%rsp)
movq 320(%rsp), %rax
movq %rax, 88(%rsp)
leaq 88(%rsp), %rax
movq %rax, 240(%rsp)
leaq 328(%rsp), %rax
movq %rax, 248(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
leaq 104(%rsp), %rcx
leaq 96(%rsp), %rdx
leaq 124(%rsp), %rsi
leaq 112(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 104(%rsp)
.cfi_def_cfa_offset 296
pushq 104(%rsp)
.cfi_def_cfa_offset 304
leaq 176(%rsp), %r9
movq 140(%rsp), %rcx
movl 148(%rsp), %r8d
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
leaq _Z3sw4PfS_S_S_S_S_S_S_S_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 288
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z43__device_stub__Z3sw4PfS_S_S_S_S_S_S_S_S_S_iPfS_S_S_S_S_S_S_S_S_S_i, .-_Z43__device_stub__Z3sw4PfS_S_S_S_S_S_S_S_S_S_iPfS_S_S_S_S_S_S_S_S_S_i
.globl _Z3sw4PfS_S_S_S_S_S_S_S_S_S_i
.type _Z3sw4PfS_S_S_S_S_S_S_S_S_S_i, @function
_Z3sw4PfS_S_S_S_S_S_S_S_S_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 56(%rsp)
.cfi_def_cfa_offset 32
pushq 56(%rsp)
.cfi_def_cfa_offset 40
pushq 56(%rsp)
.cfi_def_cfa_offset 48
pushq 56(%rsp)
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z43__device_stub__Z3sw4PfS_S_S_S_S_S_S_S_S_S_iPfS_S_S_S_S_S_S_S_S_S_i
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z3sw4PfS_S_S_S_S_S_S_S_S_S_i, .-_Z3sw4PfS_S_S_S_S_S_S_S_S_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Failed to allocate device memory for uacc_0\n"
.align 8
.LC2:
.string "Failed to allocate device memory for uacc_1\n"
.align 8
.LC3:
.string "Failed to allocate device memory for uacc_2\n"
.align 8
.LC4:
.string "Failed to allocate device memory for u_0\n"
.align 8
.LC5:
.string "Failed to allocate device memory for u_1\n"
.align 8
.LC6:
.string "Failed to allocate device memory for u_2\n"
.align 8
.LC7:
.string "Failed to allocate device memory for mu\n"
.align 8
.LC8:
.string "Failed to allocate device memory for la\n"
.align 8
.LC9:
.string "Failed to allocate device memory for strx\n"
.align 8
.LC10:
.string "Failed to allocate device memory for stry\n"
.align 8
.LC11:
.string "Failed to allocate device memory for strz\n"
.text
.globl host_code
.type host_code, @function
host_code:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $200, %rsp
.cfi_def_cfa_offset 256
movq %rdi, (%rsp)
movq %rsi, 8(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 32(%rsp)
movq %r9, 40(%rsp)
movq 256(%rsp), %r15
movq 264(%rsp), %r14
movq 272(%rsp), %r13
movq 280(%rsp), %rax
movq %rax, 48(%rsp)
movq 288(%rsp), %rbx
movq %rbx, 56(%rsp)
movl 296(%rsp), %r12d
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
movslq %r12d, %rbp
movq %rbp, %rbx
imulq %rbp, %rbx
imulq %rbp, %rbx
salq $2, %rbx
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC1(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbx, %rdx
movq (%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
leaq 80(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC2(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
leaq 88(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC3(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
leaq 96(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC4(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq 96(%rsp), %rdi
call cudaMemcpy@PLT
leaq 104(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC5(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbx, %rdx
movq 32(%rsp), %rsi
movq 104(%rsp), %rdi
call cudaMemcpy@PLT
leaq 112(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC6(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq 112(%rsp), %rdi
call cudaMemcpy@PLT
leaq 120(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC7(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbx, %rdx
movq %r15, %rsi
movq 120(%rsp), %rdi
call cudaMemcpy@PLT
leaq 128(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC8(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 128(%rsp), %rdi
call cudaMemcpy@PLT
salq $2, %rbp
leaq 136(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq .LC9(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbp, %rdx
movq %r13, %rsi
movq 136(%rsp), %rdi
call cudaMemcpy@PLT
leaq 144(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq .LC10(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbp, %rdx
movq 48(%rsp), %rsi
movq 144(%rsp), %rdi
call cudaMemcpy@PLT
leaq 152(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq .LC11(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbp, %rdx
movq 56(%rsp), %rsi
movq 152(%rsp), %rdi
call cudaMemcpy@PLT
movl %r12d, %eax
shrl %eax
movl %eax, %esi
addl $1, %esi
testb $1, %r12b
cmove %eax, %esi
movl %r12d, %edx
shrl $2, %edx
movl %edx, %eax
addl $1, %eax
testb $3, %r12b
cmove %edx, %eax
movl %r12d, %ecx
shrl $5, %ecx
movl %ecx, %edx
addl $1, %edx
testb $31, %r12b
cmove %ecx, %edx
movl %edx, 172(%rsp)
movl %eax, 176(%rsp)
movl $32, 160(%rsp)
movl $4, 164(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 160(%rsp), %rdx
movl $2, %ecx
movq 172(%rsp), %rdi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L22:
movl $2, %ecx
movq %rbx, %rdx
movq 72(%rsp), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 80(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 88(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 112(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rdi
call cudaFree@PLT
movq 128(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rdi
call cudaFree@PLT
movq 144(%rsp), %rdi
call cudaFree@PLT
movq 152(%rsp), %rdi
call cudaFree@PLT
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq %r12
.cfi_def_cfa_offset 264
pushq 160(%rsp)
.cfi_def_cfa_offset 272
pushq 160(%rsp)
.cfi_def_cfa_offset 280
pushq 160(%rsp)
.cfi_def_cfa_offset 288
pushq 160(%rsp)
.cfi_def_cfa_offset 296
pushq 160(%rsp)
.cfi_def_cfa_offset 304
movq 160(%rsp), %r9
movq 152(%rsp), %r8
movq 144(%rsp), %rcx
movq 136(%rsp), %rdx
movq 128(%rsp), %rsi
movq 120(%rsp), %rdi
call _Z43__device_stub__Z3sw4PfS_S_S_S_S_S_S_S_S_S_iPfS_S_S_S_S_S_S_S_S_S_i
addq $48, %rsp
.cfi_def_cfa_offset 256
jmp .L22
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size host_code, .-host_code
.section .rodata.str1.1
.LC12:
.string "_Z3sw4PfS_S_S_S_S_S_S_S_S_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z3sw4PfS_S_S_S_S_S_S_S_S_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include "cuda.h"
#define max(x,y) ((x) > (y)? (x) : (y))
#define min(x,y) ((x) < (y)? (x) : (y))
#define ceil(a,b) ((a) % (b) == 0 ? (a) / (b) : ((a) / (b)) + 1)
void check_error (const char* message) {
cudaError_t error = cudaGetLastError ();
if (error != cudaSuccess) {
printf ("CUDA error : %s, %s\n", message, cudaGetErrorString (error));
exit(-1);
}
}
__global__ void sw4 (float * __restrict__ uacc_0, float * __restrict__ uacc_1, float * __restrict__ uacc_2, float * __restrict__ u_0, float * __restrict__ u_1, float * __restrict__ u_2, float * __restrict__ mu, float * __restrict__ la, float * __restrict__ strx, float * __restrict__ stry, float * __restrict__ strz, int N) {
//Determing the block's indices
int blockdim_i= (int)(blockDim.x);
int i0 = (int)(blockIdx.x)*(blockdim_i);
int i = max (i0, 0) + (int)(threadIdx.x);
int blockdim_j= (int)(blockDim.y);
int j0 = (int)(blockIdx.y)*(blockdim_j);
int j = max (j0, 0) + (int)(threadIdx.y);
int blockdim_k= (int)(blockDim.z);
int k0 = (int)(blockIdx.z)*(blockdim_k);
int k = max (k0, 0) + (int)(threadIdx.z);
// Assumptions
int a1 = 1;
float h = 3.7;
float cof = 1e0 / ( h * h);
if (i>=2 & j>=2 & k>=2 & i<=N-3 & j<=N-3 & k<=N-3) {
/* 28 * 3 = 84 flops */
float mux1 = mu[k*N*N+j*N+i-1] * strx[i-1] - 3e0 / 4 * (mu[k*N*N+j*N+i] * strx[i] + mu[k*N*N+j*N+i-2] * strx[i-2]);
float mux2 = mu[k*N*N+j*N+i-2] * strx[i-2] + mu[k*N*N+j*N+i+1] * strx[i+1] + 3 * (mu[k*N*N+j*N+i] * strx[i] + mu[k*N*N+j*N+i-1] * strx[i-1]);
float mux3 = mu[k*N*N+j*N+i-1] * strx[i-1] + mu[k*N*N+j*N+i+2] * strx[i+2] + 3 * (mu[k*N*N+j*N+i+1] * strx[i+1] + mu[k*N*N+j*N+i] * strx[i]);
float mux4 = mu[k*N*N+j*N+i+1] * strx[i+1] - 3e0 / 4 * (mu[k*N*N+j*N+i] * strx[i] + mu[k*N*N+j*N+i+2] * strx[i+2]);
float muy1 = mu[k*N*N+(j-1)*N+i] * stry[j-1] - 3e0 / 4 * (mu[k*N*N+j*N+i] * stry[j] + mu[k*N*N+(j-2)*N+i] * stry[j-2]);
float muy2 = mu[k*N*N+(j-2)*N+i] * stry[j-2] + mu[k*N*N+(j+1)*N+i] * stry[j+1] + 3 * (mu[k*N*N+j*N+i] * stry[j] + mu[k*N*N+(j-1)*N+i] * stry[j-1]);
float muy3 = mu[k*N*N+(j-1)*N+i] * stry[j-1] + mu[k*N*N+(j+2)*N+i] * stry[j+2] + 3 * (mu[k*N*N+(j+1)*N+i] * stry[j+1] + mu[k*N*N+j*N+i] * stry[j]);
float muy4 = mu[k*N*N+(j+1)*N+i] * stry[j+1] - 3e0 / 4 * (mu[k*N*N+j*N+i] * stry[j] + mu[k*N*N+(j+2)*N+i] * stry[j+2]);
float muz1 = mu[(k-1)*N*N+j*N+i] * strz[k-1] - 3e0 / 4 * (mu[k*N*N+j*N+i] * strz[k] + mu[(k-2)*N*N+j*N+i] * strz[k-2]);
float muz2 = mu[(k-2)*N*N+j*N+i] * strz[k-2] + mu[(k+1)*N*N+j*N+i] * strz[k+1] + 3 * (mu[k*N*N+j*N+i] * strz[k] + mu[(k-1)*N*N+j*N+i] * strz[k-1]);
float muz3 = mu[(k-1)*N*N+j*N+i] * strz[k-1] + mu[(k+2)*N*N+j*N+i] * strz[k+2] + 3 * (mu[(k+1)*N*N+j*N+i] * strz[k+1] + mu[k*N*N+j*N+i] * strz[k]);
float muz4 = mu[(k+1)*N*N+j*N+i] * strz[k+1] - 3e0 / 4 * (mu[k*N*N+j*N+i] * strz[k] + mu[(k+2)*N*N+j*N+i] * strz[k+2]);
/* 78 * 3 = 234 flops */
float r1 = 1e0 / 6 * (strx[i] * ((2 * mux1 + la[k*N*N+j*N+i-1] * strx[i-1] - 3e0 / 4 * (la[k*N*N+j*N+i] * strx[i] + la[k*N*N+j*N+i-2] * strx[i-2])) * (u_0[k*N*N+j*N+i-2] - u_0[k*N*N+j*N+i]) + (2 * mux2 + la[k*N*N+j*N+i-2] * strx[i-2] + la[k*N*N+j*N+i+1] * strx[i+1] + 3 * (la[k*N*N+j*N+i] * strx[i] + la[k*N*N+j*N+i-1] * strx[i-1])) * (u_0[k*N*N+j*N+i-1] - u_0[k*N*N+j*N+i]) + (2 * mux3 + la[k*N*N+j*N+i-1] * strx[i-1] + la[k*N*N+j*N+i+2] * strx[i+2] + 3 * (la[k*N*N+j*N+i+1] * strx[i+1] + la[k*N*N+j*N+i] * strx[i])) * (u_0[k*N*N+j*N+i+1] - u_0[k*N*N+j*N+i]) + (2 * mux4 + la[k*N*N+j*N+i+1] * strx[i+1] - 3e0 / 4 * (la[k*N*N+j*N+i] * strx[i] + la[k*N*N+j*N+i+2] * strx[i+2])) * (u_0[k*N*N+j*N+i+2] - u_0[k*N*N+j*N+i])) + stry[j] * (muy1 * (u_0[k*N*N+(j-2)*N+i] - u_0[k*N*N+j*N+i]) + muy2 * (u_0[k*N*N+(j-1)*N+i] - u_0[k*N*N+j*N+i]) + muy3 * (u_0[k*N*N+(j+1)*N+i] - u_0[k*N*N+j*N+i]) + muy4 * (u_0[k*N*N+(j+2)*N+i] - u_0[k*N*N+j*N+i])) + strz[k] * (muz1 * (u_0[(k-2)*N*N+j*N+i] - u_0[k*N*N+j*N+i]) + muz2 * (u_0[(k-1)*N*N+j*N+i] - u_0[k*N*N+j*N+i]) + muz3 * (u_0[(k+1)*N*N+j*N+i] - u_0[k*N*N+j*N+i]) + muz4 * (u_0[(k+2)*N*N+j*N+i] - u_0[k*N*N+j*N+i])));
float r2 = 1e0 / 6 * (strx[i] * (mux1 * (u_1[k*N*N+j*N+i-2] - u_1[k*N*N+j*N+i]) + mux2 * (u_1[k*N*N+j*N+i-1] - u_1[k*N*N+j*N+i]) + mux3 * (u_1[k*N*N+j*N+i+1] - u_1[k*N*N+j*N+i]) + mux4 * (u_1[k*N*N+j*N+i+2] - u_1[k*N*N+j*N+i])) + stry[j] * ((2 * muy1 + la[k*N*N+(j-1)*N+i] * stry[j-1] - 3e0 / 4 * (la[k*N*N+j*N+i] * stry[j] + la[k*N*N+(j-2)*N+i] * stry[j-2])) * (u_1[k*N*N+(j-2)*N+i] - u_1[k*N*N+j*N+i]) + (2 * muy2 + la[k*N*N+(j-2)*N+i] * stry[j-2] + la[k*N*N+(j+1)*N+i] * stry[j+1] + 3 * (la[k*N*N+j*N+i] * stry[j] + la[k*N*N+(j-1)*N+i] * stry[j-1])) * (u_1[k*N*N+(j-1)*N+i] - u_1[k*N*N+j*N+i]) + (2 * muy3 + la[k*N*N+(j-1)*N+i] * stry[j-1] + la[k*N*N+(j+2)*N+i] * stry[j+2] + 3 * (la[k*N*N+(j+1)*N+i] * stry[j+1] + la[k*N*N+j*N+i] * stry[j])) * (u_1[k*N*N+(j+1)*N+i] - u_1[k*N*N+j*N+i]) + (2 * muy4 + la[k*N*N+(j+1)*N+i] * stry[j+1] - 3e0 / 4 * (la[k*N*N+j*N+i] * stry[j] + la[k*N*N+(j+2)*N+i] * stry[j+2])) * (u_1[k*N*N+(j+2)*N+i] - u_1[k*N*N+j*N+i])) + strz[k] * (muz1 * (u_1[(k-2)*N*N+j*N+i] - u_1[k*N*N+j*N+i]) + muz2 * (u_1[(k-1)*N*N+j*N+i] - u_1[k*N*N+j*N+i]) + muz3 * (u_1[(k+1)*N*N+j*N+i] - u_1[k*N*N+j*N+i]) + muz4 * (u_1[(k+2)*N*N+j*N+i] - u_1[k*N*N+j*N+i])));
float r3 = 1e0 / 6 * (strx[i] * (mux1 * (u_2[k*N*N+j*N+i-2] - u_2[k*N*N+j*N+i]) + mux2 * (u_2[k*N*N+j*N+i-1] - u_2[k*N*N+j*N+i]) + mux3 * (u_2[k*N*N+j*N+i+1] - u_2[k*N*N+j*N+i]) + mux4 * (u_2[k*N*N+j*N+i+2] - u_2[k*N*N+j*N+i])) + stry[j] * (muy1 * (u_2[k*N*N+(j-2)*N+i] - u_2[k*N*N+j*N+i]) + muy2 * (u_2[k*N*N+(j-1)*N+i] - u_2[k*N*N+j*N+i]) + muy3 * (u_2[k*N*N+(j+1)*N+i] - u_2[k*N*N+j*N+i]) + muy4 * (u_2[k*N*N+(j+2)*N+i] - u_2[k*N*N+j*N+i])) + strz[k] * ((2 * muz1 + la[(k-1)*N*N+j*N+i] * strz[k-1] - 3e0 / 4 * (la[k*N*N+j*N+i] * strz[k] + la[(k-2)*N*N+j*N+i] * strz[k-2])) * (u_2[(k-2)*N*N+j*N+i] - u_2[k*N*N+j*N+i]) + (2 * muz2 + la[(k-2)*N*N+j*N+i] * strz[k-2] + la[(k+1)*N*N+j*N+i] * strz[k+1] + 3 * (la[k*N*N+j*N+i] * strz[k] + la[(k-1)*N*N+j*N+i] * strz[k-1])) * (u_2[(k-1)*N*N+j*N+i] - u_2[k*N*N+j*N+i]) + (2 * muz3 + la[(k-1)*N*N+j*N+i] * strz[k-1] + la[(k+2)*N*N+j*N+i] * strz[k+2] + 3 * (la[(k+1)*N*N+j*N+i] * strz[k+1] + la[k*N*N+j*N+i] * strz[k])) * (u_2[(k+1)*N*N+j*N+i] - u_2[k*N*N+j*N+i]) + (2 * muz4 + la[(k+1)*N*N+j*N+i] * strz[k+1] - 3e0 / 4 * (la[k*N*N+j*N+i] * strz[k] + la[(k+2)*N*N+j*N+i] * strz[k+2])) * (u_2[(k+2)*N*N+j*N+i] - u_2[k*N*N+j*N+i])));
/* 120 * 3 = 360 flops */
r1 = r1 + strx[i] * stry[j] * (1e0 / 144) * (la[k*N*N+j*N+i-2] * (u_1[k*N*N+(j-2)*N+i-2] - u_1[k*N*N+(j+2)*N+i-2] + 8 * (-u_1[k*N*N+(j-1)*N+i-2] + u_1[k*N*N+(j+1)*N+i-2])) - 8 * (la[k*N*N+j*N+i-1] * (u_1[k*N*N+(j-2)*N+i-1] - u_1[k*N*N+(j+2)*N+i-1] + 8 * (-u_1[k*N*N+(j-1)*N+i-1] + u_1[k*N*N+(j+1)*N+i-1]))) + 8 * (la[k*N*N+j*N+i+1] * (u_1[k*N*N+(j-2)*N+i+1] - u_1[k*N*N+(j+2)*N+i+1] + 8 * (-u_1[k*N*N+(j-1)*N+i+1] + u_1[k*N*N+(j+1)*N+i+1]))) - (la[k*N*N+j*N+i+2] * (u_1[k*N*N+(j-2)*N+i+2] - u_1[k*N*N+(j+2)*N+i+2] + 8 * (-u_1[k*N*N+(j-1)*N+i+2] + u_1[k*N*N+(j+1)*N+i+2])))) + strx[i] * strz[k] * (1e0 / 144) * (la[k*N*N+j*N+i-2] * (u_2[(k-2)*N*N+j*N+i-2] - u_2[(k+2)*N*N+j*N+i-2] + 8 * (-u_2[(k-1)*N*N+j*N+i-2] + u_2[(k+1)*N*N+j*N+i-2])) - 8 * (la[k*N*N+j*N+i-1] * (u_2[(k-2)*N*N+j*N+i-1] - u_2[(k+2)*N*N+j*N+i-1] + 8 * (-u_2[(k-1)*N*N+j*N+i-1] + u_2[(k+1)*N*N+j*N+i-1]))) + 8 * (la[k*N*N+j*N+i+1] * (u_2[(k-2)*N*N+j*N+i+1] - u_2[(k+2)*N*N+j*N+i+1] + 8 * (-u_2[(k-1)*N*N+j*N+i+1] + u_2[(k+1)*N*N+j*N+i+1]))) - (la[k*N*N+j*N+i+2] * (u_2[(k-2)*N*N+j*N+i+2] - u_2[(k+2)*N*N+j*N+i+2] + 8 * (-u_2[(k-1)*N*N+j*N+i+2] + u_2[(k+1)*N*N+j*N+i+2])))) + strx[i] * stry[j] * (1e0 / 144) * (mu[k*N*N+(j-2)*N+i] * (u_1[k*N*N+(j-2)*N+i-2] - u_1[k*N*N+(j-2)*N+i+2] + 8 * (-u_1[k*N*N+(j-2)*N+i-1] + u_1[k*N*N+(j-2)*N+i+1])) - 8 * (mu[k*N*N+(j-1)*N+i] * (u_1[k*N*N+(j-1)*N+i-2] - u_1[k*N*N+(j-1)*N+i+2] + 8 * (-u_1[k*N*N+(j-1)*N+i-1] + u_1[k*N*N+(j-1)*N+i+1]))) + 8 * (mu[k*N*N+(j+1)*N+i] * (u_1[k*N*N+(j+1)*N+i-2] - u_1[k*N*N+(j+1)*N+i+2] + 8 * (-u_1[k*N*N+(j+1)*N+i-1] + u_1[k*N*N+(j+1)*N+i+1]))) - (mu[k*N*N+(j+2)*N+i] * (u_1[k*N*N+(j+2)*N+i-2] - u_1[k*N*N+(j+2)*N+i+2] + 8 * (-u_1[k*N*N+(j+2)*N+i-1] + u_1[k*N*N+(j+2)*N+i+1])))) + strx[i] * strz[k] * (1e0 / 144) * (mu[(k-2)*N*N+j*N+i] * (u_2[(k-2)*N*N+j*N+i-2] - u_2[(k-2)*N*N+j*N+i+2] + 8 * (-u_2[(k-2)*N*N+j*N+i-1] + u_2[(k-2)*N*N+j*N+i+1])) - 8 * (mu[(k-1)*N*N+j*N+i] * (u_2[(k-1)*N*N+j*N+i-2] - u_2[(k-1)*N*N+j*N+i+2] + 8 * (-u_2[(k-1)*N*N+j*N+i-1] + u_2[(k-1)*N*N+j*N+i+1]))) + 8 * (mu[(k+1)*N*N+j*N+i] * (u_2[(k+1)*N*N+j*N+i-2] - u_2[(k+1)*N*N+j*N+i+2] + 8 * (-u_2[(k+1)*N*N+j*N+i-1] + u_2[(k+1)*N*N+j*N+i+1]))) - (mu[(k+2)*N*N+j*N+i] * (u_2[(k+2)*N*N+j*N+i-2] - u_2[(k+2)*N*N+j*N+i+2] + 8 * (-u_2[(k+2)*N*N+j*N+i-1] + u_2[(k+2)*N*N+j*N+i+1]))));
r2 = r2 + strx[i] * stry[j] * (1e0 / 144) * (mu[k*N*N+j*N+i-2] * (u_0[k*N*N+(j-2)*N+i-2] - u_0[k*N*N+(j+2)*N+i-2] + 8 * (-u_0[k*N*N+(j-1)*N+i-2] + u_0[k*N*N+(j+1)*N+i-2])) - 8 * (mu[k*N*N+j*N+i-1] * (u_0[k*N*N+(j-2)*N+i-1] - u_0[k*N*N+(j+2)*N+i-1] + 8 * (-u_0[k*N*N+(j-1)*N+i-1] + u_0[k*N*N+(j+1)*N+i-1]))) + 8 * (mu[k*N*N+j*N+i+1] * (u_0[k*N*N+(j-2)*N+i+1] - u_0[k*N*N+(j+2)*N+i+1] + 8 * (-u_0[k*N*N+(j-1)*N+i+1] + u_0[k*N*N+(j+1)*N+i+1]))) - (mu[k*N*N+j*N+i+2] * (u_0[k*N*N+(j-2)*N+i+2] - u_0[k*N*N+(j+2)*N+i+2] + 8 * (-u_0[k*N*N+(j-1)*N+i+2] + u_0[k*N*N+(j+1)*N+i+2])))) + strx[i] * stry[j] * (1e0 / 144) * (la[k*N*N+(j-2)*N+i] * (u_0[k*N*N+(j-2)*N+i-2] - u_0[k*N*N+(j-2)*N+i+2] + 8 * (-u_0[k*N*N+(j-2)*N+i-1] + u_0[k*N*N+(j-2)*N+i+1])) - 8 * (la[k*N*N+(j-1)*N+i] * (u_0[k*N*N+(j-1)*N+i-2] - u_0[k*N*N+(j-1)*N+i+2] + 8 * (-u_0[k*N*N+(j-1)*N+i-1] + u_0[k*N*N+(j-1)*N+i+1]))) + 8 * (la[k*N*N+(j+1)*N+i] * (u_0[k*N*N+(j+1)*N+i-2] - u_0[k*N*N+(j+1)*N+i+2] + 8 * (-u_0[k*N*N+(j+1)*N+i-1] + u_0[k*N*N+(j+1)*N+i+1]))) - (la[k*N*N+(j+2)*N+i] * (u_0[k*N*N+(j+2)*N+i-2] - u_0[k*N*N+(j+2)*N+i+2] + 8 * (-u_0[k*N*N+(j+2)*N+i-1] + u_0[k*N*N+(j+2)*N+i+1])))) + stry[j] * strz[k] * (1e0 / 144) * (la[k*N*N+(j-2)*N+i] * (u_2[(k-2)*N*N+(j-2)*N+i] - u_2[(k+2)*N*N+(j-2)*N+i] + 8 * (-u_2[(k-1)*N*N+(j-2)*N+i] + u_2[(k+1)*N*N+(j-2)*N+i])) - 8 * (la[k*N*N+(j-1)*N+i] * (u_2[(k-2)*N*N+(j-1)*N+i] - u_2[(k+2)*N*N+(j-1)*N+i] + 8 * (-u_2[(k-1)*N*N+(j-1)*N+i] + u_2[(k+1)*N*N+(j-1)*N+i]))) + 8 * (la[k*N*N+(j+1)*N+i] * (u_2[(k-2)*N*N+(j+1)*N+i] - u_2[(k+2)*N*N+(j+1)*N+i] + 8 * (-u_2[(k-1)*N*N+(j+1)*N+i] + u_2[(k+1)*N*N+(j+1)*N+i]))) - (la[k*N*N+(j+2)*N+i] * (u_2[(k-2)*N*N+(j+2)*N+i] - u_2[(k+2)*N*N+(j+2)*N+i] + 8 * (-u_2[(k-1)*N*N+(j+2)*N+i] + u_2[(k+1)*N*N+(j+2)*N+i])))) + stry[j] * strz[k] * (1e0 / 144) * (mu[(k-2)*N*N+j*N+i] * (u_2[(k-2)*N*N+(j-2)*N+i] - u_2[(k-2)*N*N+(j+2)*N+i] + 8 * (-u_2[(k-2)*N*N+(j-1)*N+i] + u_2[(k-2)*N*N+(j+1)*N+i])) - 8 * (mu[(k-1)*N*N+j*N+i] * (u_2[(k-1)*N*N+(j-2)*N+i] - u_2[(k-1)*N*N+(j+2)*N+i] + 8 * (-u_2[(k-1)*N*N+(j-1)*N+i] + u_2[(k-1)*N*N+(j+1)*N+i]))) + 8 * (mu[(k+1)*N*N+j*N+i] * (u_2[(k+1)*N*N+(j-2)*N+i] - u_2[(k+1)*N*N+(j+2)*N+i] + 8 * (-u_2[(k+1)*N*N+(j-1)*N+i] + u_2[(k+1)*N*N+(j+1)*N+i]))) - (mu[(k+2)*N*N+j*N+i] * (u_2[(k+2)*N*N+(j-2)*N+i] - u_2[(k+2)*N*N+(j+2)*N+i] + 8 * (-u_2[(k+2)*N*N+(j-1)*N+i] + u_2[(k+2)*N*N+(j+1)*N+i]))));
r3 = r3 + strx[i] * strz[k] * (1e0 / 144) * (mu[k*N*N+j*N+i-2] * (u_0[(k-2)*N*N+j*N+i-2] - u_0[(k+2)*N*N+j*N+i-2] + 8 * (-u_0[(k-1)*N*N+j*N+i-2] + u_0[(k+1)*N*N+j*N+i-2])) - 8 * (mu[k*N*N+j*N+i-1] * (u_0[(k-2)*N*N+j*N+i-1] - u_0[(k+2)*N*N+j*N+i-1] + 8 * (-u_0[(k-1)*N*N+j*N+i-1] + u_0[(k+1)*N*N+j*N+i-1]))) + 8 * (mu[k*N*N+j*N+i+1] * (u_0[(k-2)*N*N+j*N+i+1] - u_0[(k+2)*N*N+j*N+i+1] + 8 * (-u_0[(k-1)*N*N+j*N+i+1] + u_0[(k+1)*N*N+j*N+i+1]))) - (mu[k*N*N+j*N+i+2] * (u_0[(k-2)*N*N+j*N+i+2] - u_0[(k+2)*N*N+j*N+i+2] + 8 * (-u_0[(k-1)*N*N+j*N+i+2] + u_0[(k+1)*N*N+j*N+i+2])))) + stry[j] * strz[k] * (1e0 / 144) * (mu[k*N*N+(j-2)*N+i] * (u_1[(k-2)*N*N+(j-2)*N+i] - u_1[(k+2)*N*N+(j-2)*N+i] + 8 * (-u_1[(k-1)*N*N+(j-2)*N+i] + u_1[(k+1)*N*N+(j-2)*N+i])) - 8 * (mu[k*N*N+(j-1)*N+i] * (u_1[(k-2)*N*N+(j-1)*N+i] - u_1[(k+2)*N*N+(j-1)*N+i] + 8 * (-u_1[(k-1)*N*N+(j-1)*N+i] + u_1[(k+1)*N*N+(j-1)*N+i]))) + 8 * (mu[k*N*N+(j+1)*N+i] * (u_1[(k-2)*N*N+(j+1)*N+i] - u_1[(k+2)*N*N+(j+1)*N+i] + 8 * (-u_1[(k-1)*N*N+(j+1)*N+i] + u_1[(k+1)*N*N+(j+1)*N+i]))) - (mu[k*N*N+(j+2)*N+i] * (u_1[(k-2)*N*N+(j+2)*N+i] - u_1[(k+2)*N*N+(j+2)*N+i] + 8 * (-u_1[(k-1)*N*N+(j+2)*N+i] + u_1[(k+1)*N*N+(j+2)*N+i])))) + strx[i] * strz[k] * (1e0 / 144) * (la[(k-2)*N*N+j*N+i] * (u_0[(k-2)*N*N+j*N+i-2] - u_0[(k-2)*N*N+j*N+i+2] + 8 * (-u_0[(k-2)*N*N+j*N+i-1] + u_0[(k-2)*N*N+j*N+i+1])) - 8 * (la[(k-1)*N*N+j*N+i] * (u_0[(k-1)*N*N+j*N+i-2] - u_0[(k-1)*N*N+j*N+i+2] + 8 * (-u_0[(k-1)*N*N+j*N+i-1] + u_0[(k-1)*N*N+j*N+i+1]))) + 8 * (la[(k+1)*N*N+j*N+i] * (u_0[(k+1)*N*N+j*N+i-2] - u_0[(k+1)*N*N+j*N+i+2] + 8 * (-u_0[(k+1)*N*N+j*N+i-1] + u_0[(k+1)*N*N+j*N+i+1]))) - (la[(k+2)*N*N+j*N+i] * (u_0[(k+2)*N*N+j*N+i-2] - u_0[(k+2)*N*N+j*N+i+2] + 8 * (-u_0[(k+2)*N*N+j*N+i-1] + u_0[(k+2)*N*N+j*N+i+1])))) + stry[j] * strz[k] * (1e0 / 144) * (la[(k-2)*N*N+j*N+i] * (u_1[(k-2)*N*N+(j-2)*N+i] - u_1[(k-2)*N*N+(j+2)*N+i] + 8 * (-u_1[(k-2)*N*N+(j-1)*N+i] + u_1[(k-2)*N*N+(j+1)*N+i])) - 8 * (la[(k-1)*N*N+j*N+i] * (u_1[(k-1)*N*N+(j-2)*N+i] - u_1[(k-1)*N*N+(j+2)*N+i] + 8 * (-u_1[(k-1)*N*N+(j-1)*N+i] + u_1[(k-1)*N*N+(j+1)*N+i]))) + 8 * (la[(k+1)*N*N+j*N+i] * (u_1[(k+1)*N*N+(j-2)*N+i] - u_1[(k+1)*N*N+(j+2)*N+i] + 8 * (-u_1[(k+1)*N*N+(j-1)*N+i] + u_1[(k+1)*N*N+(j+1)*N+i]))) - (la[(k+2)*N*N+j*N+i] * (u_1[(k+2)*N*N+(j-2)*N+i] - u_1[(k+2)*N*N+(j+2)*N+i] + 8 * (-u_1[(k+2)*N*N+(j-1)*N+i] + u_1[(k+2)*N*N+(j+1)*N+i]))));
/* 3 * 3 = 9 flops */
uacc_0[k*N*N+j*N+i] = a1 * uacc_0[k*N*N+j*N+i] + cof * r1;
uacc_1[k*N*N+j*N+i] = a1 * uacc_1[k*N*N+j*N+i] + cof * r2;
uacc_2[k*N*N+j*N+i] = a1 * uacc_2[k*N*N+j*N+i] + cof * r3;
}
}
extern "C" void host_code (float *h_uacc_0, float *h_uacc_1, float *h_uacc_2, float *h_u_0, float *h_u_1, float *h_u_2, float *h_mu, float *h_la, float *h_strx, float *h_stry, float *h_strz, int N) {
float *uacc_0;
cudaMalloc (&uacc_0, sizeof(float)*N*N*N);
check_error ("Failed to allocate device memory for uacc_0\n");
cudaMemcpy (uacc_0, h_uacc_0, sizeof(float)*N*N*N, cudaMemcpyHostToDevice);
float *uacc_1;
cudaMalloc (&uacc_1, sizeof(float)*N*N*N);
check_error ("Failed to allocate device memory for uacc_1\n");
cudaMemcpy (uacc_1, h_uacc_1, sizeof(float)*N*N*N, cudaMemcpyHostToDevice);
float *uacc_2;
cudaMalloc (&uacc_2, sizeof(float)*N*N*N);
check_error ("Failed to allocate device memory for uacc_2\n");
cudaMemcpy (uacc_2, h_uacc_2, sizeof(float)*N*N*N, cudaMemcpyHostToDevice);
float *u_0;
cudaMalloc (&u_0, sizeof(float)*N*N*N);
check_error ("Failed to allocate device memory for u_0\n");
cudaMemcpy (u_0, h_u_0, sizeof(float)*N*N*N, cudaMemcpyHostToDevice);
float *u_1;
cudaMalloc (&u_1, sizeof(float)*N*N*N);
check_error ("Failed to allocate device memory for u_1\n");
cudaMemcpy (u_1, h_u_1, sizeof(float)*N*N*N, cudaMemcpyHostToDevice);
float *u_2;
cudaMalloc (&u_2, sizeof(float)*N*N*N);
check_error ("Failed to allocate device memory for u_2\n");
cudaMemcpy (u_2, h_u_2, sizeof(float)*N*N*N, cudaMemcpyHostToDevice);
float *mu;
cudaMalloc (&mu, sizeof(float)*N*N*N);
check_error ("Failed to allocate device memory for mu\n");
cudaMemcpy (mu, h_mu, sizeof(float)*N*N*N, cudaMemcpyHostToDevice);
float *la;
cudaMalloc (&la, sizeof(float)*N*N*N);
check_error ("Failed to allocate device memory for la\n");
cudaMemcpy (la, h_la, sizeof(float)*N*N*N, cudaMemcpyHostToDevice);
float *strx;
cudaMalloc (&strx, sizeof(float)*N);
check_error ("Failed to allocate device memory for strx\n");
cudaMemcpy (strx, h_strx, sizeof(float)*N, cudaMemcpyHostToDevice);
float *stry;
cudaMalloc (&stry, sizeof(float)*N);
check_error ("Failed to allocate device memory for stry\n");
cudaMemcpy (stry, h_stry, sizeof(float)*N, cudaMemcpyHostToDevice);
float *strz;
cudaMalloc (&strz, sizeof(float)*N);
check_error ("Failed to allocate device memory for strz\n");
cudaMemcpy (strz, h_strz, sizeof(float)*N, cudaMemcpyHostToDevice);
dim3 blockconfig (32, 4, 2);
dim3 gridconfig (ceil(N, blockconfig.x), ceil(N, blockconfig.y), ceil(N, blockconfig.z));
sw4 <<<gridconfig, blockconfig>>> (uacc_0, uacc_1, uacc_2, u_0, u_1, u_2, mu, la, strx, stry, strz, N);
cudaMemcpy (h_uacc_0, uacc_0, sizeof(float)*N*N*N, cudaMemcpyDeviceToHost);
cudaMemcpy (h_uacc_1, uacc_1, sizeof(float)*N*N*N, cudaMemcpyDeviceToHost);
cudaMemcpy (h_uacc_2, uacc_2, sizeof(float)*N*N*N, cudaMemcpyDeviceToHost);
cudaFree (uacc_0);
cudaFree (uacc_1);
cudaFree (uacc_2);
cudaFree (u_0);
cudaFree (u_1);
cudaFree (u_2);
cudaFree (mu);
cudaFree (la);
cudaFree (strx);
cudaFree (stry);
cudaFree (strz);
} | #include <stdio.h>
#include "hip/hip_runtime.h"
#define max(x,y) ((x) > (y)? (x) : (y))
#define min(x,y) ((x) < (y)? (x) : (y))
#define ceil(a,b) ((a) % (b) == 0 ? (a) / (b) : ((a) / (b)) + 1)
void check_error (const char* message) {
hipError_t error = hipGetLastError ();
if (error != hipSuccess) {
printf ("CUDA error : %s, %s\n", message, hipGetErrorString (error));
exit(-1);
}
}
__global__ void sw4 (float * __restrict__ uacc_0, float * __restrict__ uacc_1, float * __restrict__ uacc_2, float * __restrict__ u_0, float * __restrict__ u_1, float * __restrict__ u_2, float * __restrict__ mu, float * __restrict__ la, float * __restrict__ strx, float * __restrict__ stry, float * __restrict__ strz, int N) {
//Determing the block's indices
int blockdim_i= (int)(blockDim.x);
int i0 = (int)(blockIdx.x)*(blockdim_i);
int i = max (i0, 0) + (int)(threadIdx.x);
int blockdim_j= (int)(blockDim.y);
int j0 = (int)(blockIdx.y)*(blockdim_j);
int j = max (j0, 0) + (int)(threadIdx.y);
int blockdim_k= (int)(blockDim.z);
int k0 = (int)(blockIdx.z)*(blockdim_k);
int k = max (k0, 0) + (int)(threadIdx.z);
// Assumptions
int a1 = 1;
float h = 3.7;
float cof = 1e0 / ( h * h);
if (i>=2 & j>=2 & k>=2 & i<=N-3 & j<=N-3 & k<=N-3) {
/* 28 * 3 = 84 flops */
float mux1 = mu[k*N*N+j*N+i-1] * strx[i-1] - 3e0 / 4 * (mu[k*N*N+j*N+i] * strx[i] + mu[k*N*N+j*N+i-2] * strx[i-2]);
float mux2 = mu[k*N*N+j*N+i-2] * strx[i-2] + mu[k*N*N+j*N+i+1] * strx[i+1] + 3 * (mu[k*N*N+j*N+i] * strx[i] + mu[k*N*N+j*N+i-1] * strx[i-1]);
float mux3 = mu[k*N*N+j*N+i-1] * strx[i-1] + mu[k*N*N+j*N+i+2] * strx[i+2] + 3 * (mu[k*N*N+j*N+i+1] * strx[i+1] + mu[k*N*N+j*N+i] * strx[i]);
float mux4 = mu[k*N*N+j*N+i+1] * strx[i+1] - 3e0 / 4 * (mu[k*N*N+j*N+i] * strx[i] + mu[k*N*N+j*N+i+2] * strx[i+2]);
float muy1 = mu[k*N*N+(j-1)*N+i] * stry[j-1] - 3e0 / 4 * (mu[k*N*N+j*N+i] * stry[j] + mu[k*N*N+(j-2)*N+i] * stry[j-2]);
float muy2 = mu[k*N*N+(j-2)*N+i] * stry[j-2] + mu[k*N*N+(j+1)*N+i] * stry[j+1] + 3 * (mu[k*N*N+j*N+i] * stry[j] + mu[k*N*N+(j-1)*N+i] * stry[j-1]);
float muy3 = mu[k*N*N+(j-1)*N+i] * stry[j-1] + mu[k*N*N+(j+2)*N+i] * stry[j+2] + 3 * (mu[k*N*N+(j+1)*N+i] * stry[j+1] + mu[k*N*N+j*N+i] * stry[j]);
float muy4 = mu[k*N*N+(j+1)*N+i] * stry[j+1] - 3e0 / 4 * (mu[k*N*N+j*N+i] * stry[j] + mu[k*N*N+(j+2)*N+i] * stry[j+2]);
float muz1 = mu[(k-1)*N*N+j*N+i] * strz[k-1] - 3e0 / 4 * (mu[k*N*N+j*N+i] * strz[k] + mu[(k-2)*N*N+j*N+i] * strz[k-2]);
float muz2 = mu[(k-2)*N*N+j*N+i] * strz[k-2] + mu[(k+1)*N*N+j*N+i] * strz[k+1] + 3 * (mu[k*N*N+j*N+i] * strz[k] + mu[(k-1)*N*N+j*N+i] * strz[k-1]);
float muz3 = mu[(k-1)*N*N+j*N+i] * strz[k-1] + mu[(k+2)*N*N+j*N+i] * strz[k+2] + 3 * (mu[(k+1)*N*N+j*N+i] * strz[k+1] + mu[k*N*N+j*N+i] * strz[k]);
float muz4 = mu[(k+1)*N*N+j*N+i] * strz[k+1] - 3e0 / 4 * (mu[k*N*N+j*N+i] * strz[k] + mu[(k+2)*N*N+j*N+i] * strz[k+2]);
/* 78 * 3 = 234 flops */
float r1 = 1e0 / 6 * (strx[i] * ((2 * mux1 + la[k*N*N+j*N+i-1] * strx[i-1] - 3e0 / 4 * (la[k*N*N+j*N+i] * strx[i] + la[k*N*N+j*N+i-2] * strx[i-2])) * (u_0[k*N*N+j*N+i-2] - u_0[k*N*N+j*N+i]) + (2 * mux2 + la[k*N*N+j*N+i-2] * strx[i-2] + la[k*N*N+j*N+i+1] * strx[i+1] + 3 * (la[k*N*N+j*N+i] * strx[i] + la[k*N*N+j*N+i-1] * strx[i-1])) * (u_0[k*N*N+j*N+i-1] - u_0[k*N*N+j*N+i]) + (2 * mux3 + la[k*N*N+j*N+i-1] * strx[i-1] + la[k*N*N+j*N+i+2] * strx[i+2] + 3 * (la[k*N*N+j*N+i+1] * strx[i+1] + la[k*N*N+j*N+i] * strx[i])) * (u_0[k*N*N+j*N+i+1] - u_0[k*N*N+j*N+i]) + (2 * mux4 + la[k*N*N+j*N+i+1] * strx[i+1] - 3e0 / 4 * (la[k*N*N+j*N+i] * strx[i] + la[k*N*N+j*N+i+2] * strx[i+2])) * (u_0[k*N*N+j*N+i+2] - u_0[k*N*N+j*N+i])) + stry[j] * (muy1 * (u_0[k*N*N+(j-2)*N+i] - u_0[k*N*N+j*N+i]) + muy2 * (u_0[k*N*N+(j-1)*N+i] - u_0[k*N*N+j*N+i]) + muy3 * (u_0[k*N*N+(j+1)*N+i] - u_0[k*N*N+j*N+i]) + muy4 * (u_0[k*N*N+(j+2)*N+i] - u_0[k*N*N+j*N+i])) + strz[k] * (muz1 * (u_0[(k-2)*N*N+j*N+i] - u_0[k*N*N+j*N+i]) + muz2 * (u_0[(k-1)*N*N+j*N+i] - u_0[k*N*N+j*N+i]) + muz3 * (u_0[(k+1)*N*N+j*N+i] - u_0[k*N*N+j*N+i]) + muz4 * (u_0[(k+2)*N*N+j*N+i] - u_0[k*N*N+j*N+i])));
float r2 = 1e0 / 6 * (strx[i] * (mux1 * (u_1[k*N*N+j*N+i-2] - u_1[k*N*N+j*N+i]) + mux2 * (u_1[k*N*N+j*N+i-1] - u_1[k*N*N+j*N+i]) + mux3 * (u_1[k*N*N+j*N+i+1] - u_1[k*N*N+j*N+i]) + mux4 * (u_1[k*N*N+j*N+i+2] - u_1[k*N*N+j*N+i])) + stry[j] * ((2 * muy1 + la[k*N*N+(j-1)*N+i] * stry[j-1] - 3e0 / 4 * (la[k*N*N+j*N+i] * stry[j] + la[k*N*N+(j-2)*N+i] * stry[j-2])) * (u_1[k*N*N+(j-2)*N+i] - u_1[k*N*N+j*N+i]) + (2 * muy2 + la[k*N*N+(j-2)*N+i] * stry[j-2] + la[k*N*N+(j+1)*N+i] * stry[j+1] + 3 * (la[k*N*N+j*N+i] * stry[j] + la[k*N*N+(j-1)*N+i] * stry[j-1])) * (u_1[k*N*N+(j-1)*N+i] - u_1[k*N*N+j*N+i]) + (2 * muy3 + la[k*N*N+(j-1)*N+i] * stry[j-1] + la[k*N*N+(j+2)*N+i] * stry[j+2] + 3 * (la[k*N*N+(j+1)*N+i] * stry[j+1] + la[k*N*N+j*N+i] * stry[j])) * (u_1[k*N*N+(j+1)*N+i] - u_1[k*N*N+j*N+i]) + (2 * muy4 + la[k*N*N+(j+1)*N+i] * stry[j+1] - 3e0 / 4 * (la[k*N*N+j*N+i] * stry[j] + la[k*N*N+(j+2)*N+i] * stry[j+2])) * (u_1[k*N*N+(j+2)*N+i] - u_1[k*N*N+j*N+i])) + strz[k] * (muz1 * (u_1[(k-2)*N*N+j*N+i] - u_1[k*N*N+j*N+i]) + muz2 * (u_1[(k-1)*N*N+j*N+i] - u_1[k*N*N+j*N+i]) + muz3 * (u_1[(k+1)*N*N+j*N+i] - u_1[k*N*N+j*N+i]) + muz4 * (u_1[(k+2)*N*N+j*N+i] - u_1[k*N*N+j*N+i])));
float r3 = 1e0 / 6 * (strx[i] * (mux1 * (u_2[k*N*N+j*N+i-2] - u_2[k*N*N+j*N+i]) + mux2 * (u_2[k*N*N+j*N+i-1] - u_2[k*N*N+j*N+i]) + mux3 * (u_2[k*N*N+j*N+i+1] - u_2[k*N*N+j*N+i]) + mux4 * (u_2[k*N*N+j*N+i+2] - u_2[k*N*N+j*N+i])) + stry[j] * (muy1 * (u_2[k*N*N+(j-2)*N+i] - u_2[k*N*N+j*N+i]) + muy2 * (u_2[k*N*N+(j-1)*N+i] - u_2[k*N*N+j*N+i]) + muy3 * (u_2[k*N*N+(j+1)*N+i] - u_2[k*N*N+j*N+i]) + muy4 * (u_2[k*N*N+(j+2)*N+i] - u_2[k*N*N+j*N+i])) + strz[k] * ((2 * muz1 + la[(k-1)*N*N+j*N+i] * strz[k-1] - 3e0 / 4 * (la[k*N*N+j*N+i] * strz[k] + la[(k-2)*N*N+j*N+i] * strz[k-2])) * (u_2[(k-2)*N*N+j*N+i] - u_2[k*N*N+j*N+i]) + (2 * muz2 + la[(k-2)*N*N+j*N+i] * strz[k-2] + la[(k+1)*N*N+j*N+i] * strz[k+1] + 3 * (la[k*N*N+j*N+i] * strz[k] + la[(k-1)*N*N+j*N+i] * strz[k-1])) * (u_2[(k-1)*N*N+j*N+i] - u_2[k*N*N+j*N+i]) + (2 * muz3 + la[(k-1)*N*N+j*N+i] * strz[k-1] + la[(k+2)*N*N+j*N+i] * strz[k+2] + 3 * (la[(k+1)*N*N+j*N+i] * strz[k+1] + la[k*N*N+j*N+i] * strz[k])) * (u_2[(k+1)*N*N+j*N+i] - u_2[k*N*N+j*N+i]) + (2 * muz4 + la[(k+1)*N*N+j*N+i] * strz[k+1] - 3e0 / 4 * (la[k*N*N+j*N+i] * strz[k] + la[(k+2)*N*N+j*N+i] * strz[k+2])) * (u_2[(k+2)*N*N+j*N+i] - u_2[k*N*N+j*N+i])));
/* 120 * 3 = 360 flops */
r1 = r1 + strx[i] * stry[j] * (1e0 / 144) * (la[k*N*N+j*N+i-2] * (u_1[k*N*N+(j-2)*N+i-2] - u_1[k*N*N+(j+2)*N+i-2] + 8 * (-u_1[k*N*N+(j-1)*N+i-2] + u_1[k*N*N+(j+1)*N+i-2])) - 8 * (la[k*N*N+j*N+i-1] * (u_1[k*N*N+(j-2)*N+i-1] - u_1[k*N*N+(j+2)*N+i-1] + 8 * (-u_1[k*N*N+(j-1)*N+i-1] + u_1[k*N*N+(j+1)*N+i-1]))) + 8 * (la[k*N*N+j*N+i+1] * (u_1[k*N*N+(j-2)*N+i+1] - u_1[k*N*N+(j+2)*N+i+1] + 8 * (-u_1[k*N*N+(j-1)*N+i+1] + u_1[k*N*N+(j+1)*N+i+1]))) - (la[k*N*N+j*N+i+2] * (u_1[k*N*N+(j-2)*N+i+2] - u_1[k*N*N+(j+2)*N+i+2] + 8 * (-u_1[k*N*N+(j-1)*N+i+2] + u_1[k*N*N+(j+1)*N+i+2])))) + strx[i] * strz[k] * (1e0 / 144) * (la[k*N*N+j*N+i-2] * (u_2[(k-2)*N*N+j*N+i-2] - u_2[(k+2)*N*N+j*N+i-2] + 8 * (-u_2[(k-1)*N*N+j*N+i-2] + u_2[(k+1)*N*N+j*N+i-2])) - 8 * (la[k*N*N+j*N+i-1] * (u_2[(k-2)*N*N+j*N+i-1] - u_2[(k+2)*N*N+j*N+i-1] + 8 * (-u_2[(k-1)*N*N+j*N+i-1] + u_2[(k+1)*N*N+j*N+i-1]))) + 8 * (la[k*N*N+j*N+i+1] * (u_2[(k-2)*N*N+j*N+i+1] - u_2[(k+2)*N*N+j*N+i+1] + 8 * (-u_2[(k-1)*N*N+j*N+i+1] + u_2[(k+1)*N*N+j*N+i+1]))) - (la[k*N*N+j*N+i+2] * (u_2[(k-2)*N*N+j*N+i+2] - u_2[(k+2)*N*N+j*N+i+2] + 8 * (-u_2[(k-1)*N*N+j*N+i+2] + u_2[(k+1)*N*N+j*N+i+2])))) + strx[i] * stry[j] * (1e0 / 144) * (mu[k*N*N+(j-2)*N+i] * (u_1[k*N*N+(j-2)*N+i-2] - u_1[k*N*N+(j-2)*N+i+2] + 8 * (-u_1[k*N*N+(j-2)*N+i-1] + u_1[k*N*N+(j-2)*N+i+1])) - 8 * (mu[k*N*N+(j-1)*N+i] * (u_1[k*N*N+(j-1)*N+i-2] - u_1[k*N*N+(j-1)*N+i+2] + 8 * (-u_1[k*N*N+(j-1)*N+i-1] + u_1[k*N*N+(j-1)*N+i+1]))) + 8 * (mu[k*N*N+(j+1)*N+i] * (u_1[k*N*N+(j+1)*N+i-2] - u_1[k*N*N+(j+1)*N+i+2] + 8 * (-u_1[k*N*N+(j+1)*N+i-1] + u_1[k*N*N+(j+1)*N+i+1]))) - (mu[k*N*N+(j+2)*N+i] * (u_1[k*N*N+(j+2)*N+i-2] - u_1[k*N*N+(j+2)*N+i+2] + 8 * (-u_1[k*N*N+(j+2)*N+i-1] + u_1[k*N*N+(j+2)*N+i+1])))) + strx[i] * strz[k] * (1e0 / 144) * (mu[(k-2)*N*N+j*N+i] * (u_2[(k-2)*N*N+j*N+i-2] - u_2[(k-2)*N*N+j*N+i+2] + 8 * (-u_2[(k-2)*N*N+j*N+i-1] + u_2[(k-2)*N*N+j*N+i+1])) - 8 * (mu[(k-1)*N*N+j*N+i] * (u_2[(k-1)*N*N+j*N+i-2] - u_2[(k-1)*N*N+j*N+i+2] + 8 * (-u_2[(k-1)*N*N+j*N+i-1] + u_2[(k-1)*N*N+j*N+i+1]))) + 8 * (mu[(k+1)*N*N+j*N+i] * (u_2[(k+1)*N*N+j*N+i-2] - u_2[(k+1)*N*N+j*N+i+2] + 8 * (-u_2[(k+1)*N*N+j*N+i-1] + u_2[(k+1)*N*N+j*N+i+1]))) - (mu[(k+2)*N*N+j*N+i] * (u_2[(k+2)*N*N+j*N+i-2] - u_2[(k+2)*N*N+j*N+i+2] + 8 * (-u_2[(k+2)*N*N+j*N+i-1] + u_2[(k+2)*N*N+j*N+i+1]))));
r2 = r2 + strx[i] * stry[j] * (1e0 / 144) * (mu[k*N*N+j*N+i-2] * (u_0[k*N*N+(j-2)*N+i-2] - u_0[k*N*N+(j+2)*N+i-2] + 8 * (-u_0[k*N*N+(j-1)*N+i-2] + u_0[k*N*N+(j+1)*N+i-2])) - 8 * (mu[k*N*N+j*N+i-1] * (u_0[k*N*N+(j-2)*N+i-1] - u_0[k*N*N+(j+2)*N+i-1] + 8 * (-u_0[k*N*N+(j-1)*N+i-1] + u_0[k*N*N+(j+1)*N+i-1]))) + 8 * (mu[k*N*N+j*N+i+1] * (u_0[k*N*N+(j-2)*N+i+1] - u_0[k*N*N+(j+2)*N+i+1] + 8 * (-u_0[k*N*N+(j-1)*N+i+1] + u_0[k*N*N+(j+1)*N+i+1]))) - (mu[k*N*N+j*N+i+2] * (u_0[k*N*N+(j-2)*N+i+2] - u_0[k*N*N+(j+2)*N+i+2] + 8 * (-u_0[k*N*N+(j-1)*N+i+2] + u_0[k*N*N+(j+1)*N+i+2])))) + strx[i] * stry[j] * (1e0 / 144) * (la[k*N*N+(j-2)*N+i] * (u_0[k*N*N+(j-2)*N+i-2] - u_0[k*N*N+(j-2)*N+i+2] + 8 * (-u_0[k*N*N+(j-2)*N+i-1] + u_0[k*N*N+(j-2)*N+i+1])) - 8 * (la[k*N*N+(j-1)*N+i] * (u_0[k*N*N+(j-1)*N+i-2] - u_0[k*N*N+(j-1)*N+i+2] + 8 * (-u_0[k*N*N+(j-1)*N+i-1] + u_0[k*N*N+(j-1)*N+i+1]))) + 8 * (la[k*N*N+(j+1)*N+i] * (u_0[k*N*N+(j+1)*N+i-2] - u_0[k*N*N+(j+1)*N+i+2] + 8 * (-u_0[k*N*N+(j+1)*N+i-1] + u_0[k*N*N+(j+1)*N+i+1]))) - (la[k*N*N+(j+2)*N+i] * (u_0[k*N*N+(j+2)*N+i-2] - u_0[k*N*N+(j+2)*N+i+2] + 8 * (-u_0[k*N*N+(j+2)*N+i-1] + u_0[k*N*N+(j+2)*N+i+1])))) + stry[j] * strz[k] * (1e0 / 144) * (la[k*N*N+(j-2)*N+i] * (u_2[(k-2)*N*N+(j-2)*N+i] - u_2[(k+2)*N*N+(j-2)*N+i] + 8 * (-u_2[(k-1)*N*N+(j-2)*N+i] + u_2[(k+1)*N*N+(j-2)*N+i])) - 8 * (la[k*N*N+(j-1)*N+i] * (u_2[(k-2)*N*N+(j-1)*N+i] - u_2[(k+2)*N*N+(j-1)*N+i] + 8 * (-u_2[(k-1)*N*N+(j-1)*N+i] + u_2[(k+1)*N*N+(j-1)*N+i]))) + 8 * (la[k*N*N+(j+1)*N+i] * (u_2[(k-2)*N*N+(j+1)*N+i] - u_2[(k+2)*N*N+(j+1)*N+i] + 8 * (-u_2[(k-1)*N*N+(j+1)*N+i] + u_2[(k+1)*N*N+(j+1)*N+i]))) - (la[k*N*N+(j+2)*N+i] * (u_2[(k-2)*N*N+(j+2)*N+i] - u_2[(k+2)*N*N+(j+2)*N+i] + 8 * (-u_2[(k-1)*N*N+(j+2)*N+i] + u_2[(k+1)*N*N+(j+2)*N+i])))) + stry[j] * strz[k] * (1e0 / 144) * (mu[(k-2)*N*N+j*N+i] * (u_2[(k-2)*N*N+(j-2)*N+i] - u_2[(k-2)*N*N+(j+2)*N+i] + 8 * (-u_2[(k-2)*N*N+(j-1)*N+i] + u_2[(k-2)*N*N+(j+1)*N+i])) - 8 * (mu[(k-1)*N*N+j*N+i] * (u_2[(k-1)*N*N+(j-2)*N+i] - u_2[(k-1)*N*N+(j+2)*N+i] + 8 * (-u_2[(k-1)*N*N+(j-1)*N+i] + u_2[(k-1)*N*N+(j+1)*N+i]))) + 8 * (mu[(k+1)*N*N+j*N+i] * (u_2[(k+1)*N*N+(j-2)*N+i] - u_2[(k+1)*N*N+(j+2)*N+i] + 8 * (-u_2[(k+1)*N*N+(j-1)*N+i] + u_2[(k+1)*N*N+(j+1)*N+i]))) - (mu[(k+2)*N*N+j*N+i] * (u_2[(k+2)*N*N+(j-2)*N+i] - u_2[(k+2)*N*N+(j+2)*N+i] + 8 * (-u_2[(k+2)*N*N+(j-1)*N+i] + u_2[(k+2)*N*N+(j+1)*N+i]))));
r3 = r3 + strx[i] * strz[k] * (1e0 / 144) * (mu[k*N*N+j*N+i-2] * (u_0[(k-2)*N*N+j*N+i-2] - u_0[(k+2)*N*N+j*N+i-2] + 8 * (-u_0[(k-1)*N*N+j*N+i-2] + u_0[(k+1)*N*N+j*N+i-2])) - 8 * (mu[k*N*N+j*N+i-1] * (u_0[(k-2)*N*N+j*N+i-1] - u_0[(k+2)*N*N+j*N+i-1] + 8 * (-u_0[(k-1)*N*N+j*N+i-1] + u_0[(k+1)*N*N+j*N+i-1]))) + 8 * (mu[k*N*N+j*N+i+1] * (u_0[(k-2)*N*N+j*N+i+1] - u_0[(k+2)*N*N+j*N+i+1] + 8 * (-u_0[(k-1)*N*N+j*N+i+1] + u_0[(k+1)*N*N+j*N+i+1]))) - (mu[k*N*N+j*N+i+2] * (u_0[(k-2)*N*N+j*N+i+2] - u_0[(k+2)*N*N+j*N+i+2] + 8 * (-u_0[(k-1)*N*N+j*N+i+2] + u_0[(k+1)*N*N+j*N+i+2])))) + stry[j] * strz[k] * (1e0 / 144) * (mu[k*N*N+(j-2)*N+i] * (u_1[(k-2)*N*N+(j-2)*N+i] - u_1[(k+2)*N*N+(j-2)*N+i] + 8 * (-u_1[(k-1)*N*N+(j-2)*N+i] + u_1[(k+1)*N*N+(j-2)*N+i])) - 8 * (mu[k*N*N+(j-1)*N+i] * (u_1[(k-2)*N*N+(j-1)*N+i] - u_1[(k+2)*N*N+(j-1)*N+i] + 8 * (-u_1[(k-1)*N*N+(j-1)*N+i] + u_1[(k+1)*N*N+(j-1)*N+i]))) + 8 * (mu[k*N*N+(j+1)*N+i] * (u_1[(k-2)*N*N+(j+1)*N+i] - u_1[(k+2)*N*N+(j+1)*N+i] + 8 * (-u_1[(k-1)*N*N+(j+1)*N+i] + u_1[(k+1)*N*N+(j+1)*N+i]))) - (mu[k*N*N+(j+2)*N+i] * (u_1[(k-2)*N*N+(j+2)*N+i] - u_1[(k+2)*N*N+(j+2)*N+i] + 8 * (-u_1[(k-1)*N*N+(j+2)*N+i] + u_1[(k+1)*N*N+(j+2)*N+i])))) + strx[i] * strz[k] * (1e0 / 144) * (la[(k-2)*N*N+j*N+i] * (u_0[(k-2)*N*N+j*N+i-2] - u_0[(k-2)*N*N+j*N+i+2] + 8 * (-u_0[(k-2)*N*N+j*N+i-1] + u_0[(k-2)*N*N+j*N+i+1])) - 8 * (la[(k-1)*N*N+j*N+i] * (u_0[(k-1)*N*N+j*N+i-2] - u_0[(k-1)*N*N+j*N+i+2] + 8 * (-u_0[(k-1)*N*N+j*N+i-1] + u_0[(k-1)*N*N+j*N+i+1]))) + 8 * (la[(k+1)*N*N+j*N+i] * (u_0[(k+1)*N*N+j*N+i-2] - u_0[(k+1)*N*N+j*N+i+2] + 8 * (-u_0[(k+1)*N*N+j*N+i-1] + u_0[(k+1)*N*N+j*N+i+1]))) - (la[(k+2)*N*N+j*N+i] * (u_0[(k+2)*N*N+j*N+i-2] - u_0[(k+2)*N*N+j*N+i+2] + 8 * (-u_0[(k+2)*N*N+j*N+i-1] + u_0[(k+2)*N*N+j*N+i+1])))) + stry[j] * strz[k] * (1e0 / 144) * (la[(k-2)*N*N+j*N+i] * (u_1[(k-2)*N*N+(j-2)*N+i] - u_1[(k-2)*N*N+(j+2)*N+i] + 8 * (-u_1[(k-2)*N*N+(j-1)*N+i] + u_1[(k-2)*N*N+(j+1)*N+i])) - 8 * (la[(k-1)*N*N+j*N+i] * (u_1[(k-1)*N*N+(j-2)*N+i] - u_1[(k-1)*N*N+(j+2)*N+i] + 8 * (-u_1[(k-1)*N*N+(j-1)*N+i] + u_1[(k-1)*N*N+(j+1)*N+i]))) + 8 * (la[(k+1)*N*N+j*N+i] * (u_1[(k+1)*N*N+(j-2)*N+i] - u_1[(k+1)*N*N+(j+2)*N+i] + 8 * (-u_1[(k+1)*N*N+(j-1)*N+i] + u_1[(k+1)*N*N+(j+1)*N+i]))) - (la[(k+2)*N*N+j*N+i] * (u_1[(k+2)*N*N+(j-2)*N+i] - u_1[(k+2)*N*N+(j+2)*N+i] + 8 * (-u_1[(k+2)*N*N+(j-1)*N+i] + u_1[(k+2)*N*N+(j+1)*N+i]))));
/* 3 * 3 = 9 flops */
uacc_0[k*N*N+j*N+i] = a1 * uacc_0[k*N*N+j*N+i] + cof * r1;
uacc_1[k*N*N+j*N+i] = a1 * uacc_1[k*N*N+j*N+i] + cof * r2;
uacc_2[k*N*N+j*N+i] = a1 * uacc_2[k*N*N+j*N+i] + cof * r3;
}
}
extern "C" void host_code (float *h_uacc_0, float *h_uacc_1, float *h_uacc_2, float *h_u_0, float *h_u_1, float *h_u_2, float *h_mu, float *h_la, float *h_strx, float *h_stry, float *h_strz, int N) {
float *uacc_0;
hipMalloc (&uacc_0, sizeof(float)*N*N*N);
check_error ("Failed to allocate device memory for uacc_0\n");
hipMemcpy (uacc_0, h_uacc_0, sizeof(float)*N*N*N, hipMemcpyHostToDevice);
float *uacc_1;
hipMalloc (&uacc_1, sizeof(float)*N*N*N);
check_error ("Failed to allocate device memory for uacc_1\n");
hipMemcpy (uacc_1, h_uacc_1, sizeof(float)*N*N*N, hipMemcpyHostToDevice);
float *uacc_2;
hipMalloc (&uacc_2, sizeof(float)*N*N*N);
check_error ("Failed to allocate device memory for uacc_2\n");
hipMemcpy (uacc_2, h_uacc_2, sizeof(float)*N*N*N, hipMemcpyHostToDevice);
float *u_0;
hipMalloc (&u_0, sizeof(float)*N*N*N);
check_error ("Failed to allocate device memory for u_0\n");
hipMemcpy (u_0, h_u_0, sizeof(float)*N*N*N, hipMemcpyHostToDevice);
float *u_1;
hipMalloc (&u_1, sizeof(float)*N*N*N);
check_error ("Failed to allocate device memory for u_1\n");
hipMemcpy (u_1, h_u_1, sizeof(float)*N*N*N, hipMemcpyHostToDevice);
float *u_2;
hipMalloc (&u_2, sizeof(float)*N*N*N);
check_error ("Failed to allocate device memory for u_2\n");
hipMemcpy (u_2, h_u_2, sizeof(float)*N*N*N, hipMemcpyHostToDevice);
float *mu;
hipMalloc (&mu, sizeof(float)*N*N*N);
check_error ("Failed to allocate device memory for mu\n");
hipMemcpy (mu, h_mu, sizeof(float)*N*N*N, hipMemcpyHostToDevice);
float *la;
hipMalloc (&la, sizeof(float)*N*N*N);
check_error ("Failed to allocate device memory for la\n");
hipMemcpy (la, h_la, sizeof(float)*N*N*N, hipMemcpyHostToDevice);
float *strx;
hipMalloc (&strx, sizeof(float)*N);
check_error ("Failed to allocate device memory for strx\n");
hipMemcpy (strx, h_strx, sizeof(float)*N, hipMemcpyHostToDevice);
float *stry;
hipMalloc (&stry, sizeof(float)*N);
check_error ("Failed to allocate device memory for stry\n");
hipMemcpy (stry, h_stry, sizeof(float)*N, hipMemcpyHostToDevice);
float *strz;
hipMalloc (&strz, sizeof(float)*N);
check_error ("Failed to allocate device memory for strz\n");
hipMemcpy (strz, h_strz, sizeof(float)*N, hipMemcpyHostToDevice);
dim3 blockconfig (32, 4, 2);
dim3 gridconfig (ceil(N, blockconfig.x), ceil(N, blockconfig.y), ceil(N, blockconfig.z));
sw4 <<<gridconfig, blockconfig>>> (uacc_0, uacc_1, uacc_2, u_0, u_1, u_2, mu, la, strx, stry, strz, N);
hipMemcpy (h_uacc_0, uacc_0, sizeof(float)*N*N*N, hipMemcpyDeviceToHost);
hipMemcpy (h_uacc_1, uacc_1, sizeof(float)*N*N*N, hipMemcpyDeviceToHost);
hipMemcpy (h_uacc_2, uacc_2, sizeof(float)*N*N*N, hipMemcpyDeviceToHost);
hipFree (uacc_0);
hipFree (uacc_1);
hipFree (uacc_2);
hipFree (u_0);
hipFree (u_1);
hipFree (u_2);
hipFree (mu);
hipFree (la);
hipFree (strx);
hipFree (stry);
hipFree (strz);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include "hip/hip_runtime.h"
#define max(x,y) ((x) > (y)? (x) : (y))
#define min(x,y) ((x) < (y)? (x) : (y))
#define ceil(a,b) ((a) % (b) == 0 ? (a) / (b) : ((a) / (b)) + 1)
void check_error (const char* message) {
hipError_t error = hipGetLastError ();
if (error != hipSuccess) {
printf ("CUDA error : %s, %s\n", message, hipGetErrorString (error));
exit(-1);
}
}
__global__ void sw4 (float * __restrict__ uacc_0, float * __restrict__ uacc_1, float * __restrict__ uacc_2, float * __restrict__ u_0, float * __restrict__ u_1, float * __restrict__ u_2, float * __restrict__ mu, float * __restrict__ la, float * __restrict__ strx, float * __restrict__ stry, float * __restrict__ strz, int N) {
//Determing the block's indices
int blockdim_i= (int)(blockDim.x);
int i0 = (int)(blockIdx.x)*(blockdim_i);
int i = max (i0, 0) + (int)(threadIdx.x);
int blockdim_j= (int)(blockDim.y);
int j0 = (int)(blockIdx.y)*(blockdim_j);
int j = max (j0, 0) + (int)(threadIdx.y);
int blockdim_k= (int)(blockDim.z);
int k0 = (int)(blockIdx.z)*(blockdim_k);
int k = max (k0, 0) + (int)(threadIdx.z);
// Assumptions
int a1 = 1;
float h = 3.7;
float cof = 1e0 / ( h * h);
if (i>=2 & j>=2 & k>=2 & i<=N-3 & j<=N-3 & k<=N-3) {
/* 28 * 3 = 84 flops */
float mux1 = mu[k*N*N+j*N+i-1] * strx[i-1] - 3e0 / 4 * (mu[k*N*N+j*N+i] * strx[i] + mu[k*N*N+j*N+i-2] * strx[i-2]);
float mux2 = mu[k*N*N+j*N+i-2] * strx[i-2] + mu[k*N*N+j*N+i+1] * strx[i+1] + 3 * (mu[k*N*N+j*N+i] * strx[i] + mu[k*N*N+j*N+i-1] * strx[i-1]);
float mux3 = mu[k*N*N+j*N+i-1] * strx[i-1] + mu[k*N*N+j*N+i+2] * strx[i+2] + 3 * (mu[k*N*N+j*N+i+1] * strx[i+1] + mu[k*N*N+j*N+i] * strx[i]);
float mux4 = mu[k*N*N+j*N+i+1] * strx[i+1] - 3e0 / 4 * (mu[k*N*N+j*N+i] * strx[i] + mu[k*N*N+j*N+i+2] * strx[i+2]);
float muy1 = mu[k*N*N+(j-1)*N+i] * stry[j-1] - 3e0 / 4 * (mu[k*N*N+j*N+i] * stry[j] + mu[k*N*N+(j-2)*N+i] * stry[j-2]);
float muy2 = mu[k*N*N+(j-2)*N+i] * stry[j-2] + mu[k*N*N+(j+1)*N+i] * stry[j+1] + 3 * (mu[k*N*N+j*N+i] * stry[j] + mu[k*N*N+(j-1)*N+i] * stry[j-1]);
float muy3 = mu[k*N*N+(j-1)*N+i] * stry[j-1] + mu[k*N*N+(j+2)*N+i] * stry[j+2] + 3 * (mu[k*N*N+(j+1)*N+i] * stry[j+1] + mu[k*N*N+j*N+i] * stry[j]);
float muy4 = mu[k*N*N+(j+1)*N+i] * stry[j+1] - 3e0 / 4 * (mu[k*N*N+j*N+i] * stry[j] + mu[k*N*N+(j+2)*N+i] * stry[j+2]);
float muz1 = mu[(k-1)*N*N+j*N+i] * strz[k-1] - 3e0 / 4 * (mu[k*N*N+j*N+i] * strz[k] + mu[(k-2)*N*N+j*N+i] * strz[k-2]);
float muz2 = mu[(k-2)*N*N+j*N+i] * strz[k-2] + mu[(k+1)*N*N+j*N+i] * strz[k+1] + 3 * (mu[k*N*N+j*N+i] * strz[k] + mu[(k-1)*N*N+j*N+i] * strz[k-1]);
float muz3 = mu[(k-1)*N*N+j*N+i] * strz[k-1] + mu[(k+2)*N*N+j*N+i] * strz[k+2] + 3 * (mu[(k+1)*N*N+j*N+i] * strz[k+1] + mu[k*N*N+j*N+i] * strz[k]);
float muz4 = mu[(k+1)*N*N+j*N+i] * strz[k+1] - 3e0 / 4 * (mu[k*N*N+j*N+i] * strz[k] + mu[(k+2)*N*N+j*N+i] * strz[k+2]);
/* 78 * 3 = 234 flops */
float r1 = 1e0 / 6 * (strx[i] * ((2 * mux1 + la[k*N*N+j*N+i-1] * strx[i-1] - 3e0 / 4 * (la[k*N*N+j*N+i] * strx[i] + la[k*N*N+j*N+i-2] * strx[i-2])) * (u_0[k*N*N+j*N+i-2] - u_0[k*N*N+j*N+i]) + (2 * mux2 + la[k*N*N+j*N+i-2] * strx[i-2] + la[k*N*N+j*N+i+1] * strx[i+1] + 3 * (la[k*N*N+j*N+i] * strx[i] + la[k*N*N+j*N+i-1] * strx[i-1])) * (u_0[k*N*N+j*N+i-1] - u_0[k*N*N+j*N+i]) + (2 * mux3 + la[k*N*N+j*N+i-1] * strx[i-1] + la[k*N*N+j*N+i+2] * strx[i+2] + 3 * (la[k*N*N+j*N+i+1] * strx[i+1] + la[k*N*N+j*N+i] * strx[i])) * (u_0[k*N*N+j*N+i+1] - u_0[k*N*N+j*N+i]) + (2 * mux4 + la[k*N*N+j*N+i+1] * strx[i+1] - 3e0 / 4 * (la[k*N*N+j*N+i] * strx[i] + la[k*N*N+j*N+i+2] * strx[i+2])) * (u_0[k*N*N+j*N+i+2] - u_0[k*N*N+j*N+i])) + stry[j] * (muy1 * (u_0[k*N*N+(j-2)*N+i] - u_0[k*N*N+j*N+i]) + muy2 * (u_0[k*N*N+(j-1)*N+i] - u_0[k*N*N+j*N+i]) + muy3 * (u_0[k*N*N+(j+1)*N+i] - u_0[k*N*N+j*N+i]) + muy4 * (u_0[k*N*N+(j+2)*N+i] - u_0[k*N*N+j*N+i])) + strz[k] * (muz1 * (u_0[(k-2)*N*N+j*N+i] - u_0[k*N*N+j*N+i]) + muz2 * (u_0[(k-1)*N*N+j*N+i] - u_0[k*N*N+j*N+i]) + muz3 * (u_0[(k+1)*N*N+j*N+i] - u_0[k*N*N+j*N+i]) + muz4 * (u_0[(k+2)*N*N+j*N+i] - u_0[k*N*N+j*N+i])));
float r2 = 1e0 / 6 * (strx[i] * (mux1 * (u_1[k*N*N+j*N+i-2] - u_1[k*N*N+j*N+i]) + mux2 * (u_1[k*N*N+j*N+i-1] - u_1[k*N*N+j*N+i]) + mux3 * (u_1[k*N*N+j*N+i+1] - u_1[k*N*N+j*N+i]) + mux4 * (u_1[k*N*N+j*N+i+2] - u_1[k*N*N+j*N+i])) + stry[j] * ((2 * muy1 + la[k*N*N+(j-1)*N+i] * stry[j-1] - 3e0 / 4 * (la[k*N*N+j*N+i] * stry[j] + la[k*N*N+(j-2)*N+i] * stry[j-2])) * (u_1[k*N*N+(j-2)*N+i] - u_1[k*N*N+j*N+i]) + (2 * muy2 + la[k*N*N+(j-2)*N+i] * stry[j-2] + la[k*N*N+(j+1)*N+i] * stry[j+1] + 3 * (la[k*N*N+j*N+i] * stry[j] + la[k*N*N+(j-1)*N+i] * stry[j-1])) * (u_1[k*N*N+(j-1)*N+i] - u_1[k*N*N+j*N+i]) + (2 * muy3 + la[k*N*N+(j-1)*N+i] * stry[j-1] + la[k*N*N+(j+2)*N+i] * stry[j+2] + 3 * (la[k*N*N+(j+1)*N+i] * stry[j+1] + la[k*N*N+j*N+i] * stry[j])) * (u_1[k*N*N+(j+1)*N+i] - u_1[k*N*N+j*N+i]) + (2 * muy4 + la[k*N*N+(j+1)*N+i] * stry[j+1] - 3e0 / 4 * (la[k*N*N+j*N+i] * stry[j] + la[k*N*N+(j+2)*N+i] * stry[j+2])) * (u_1[k*N*N+(j+2)*N+i] - u_1[k*N*N+j*N+i])) + strz[k] * (muz1 * (u_1[(k-2)*N*N+j*N+i] - u_1[k*N*N+j*N+i]) + muz2 * (u_1[(k-1)*N*N+j*N+i] - u_1[k*N*N+j*N+i]) + muz3 * (u_1[(k+1)*N*N+j*N+i] - u_1[k*N*N+j*N+i]) + muz4 * (u_1[(k+2)*N*N+j*N+i] - u_1[k*N*N+j*N+i])));
float r3 = 1e0 / 6 * (strx[i] * (mux1 * (u_2[k*N*N+j*N+i-2] - u_2[k*N*N+j*N+i]) + mux2 * (u_2[k*N*N+j*N+i-1] - u_2[k*N*N+j*N+i]) + mux3 * (u_2[k*N*N+j*N+i+1] - u_2[k*N*N+j*N+i]) + mux4 * (u_2[k*N*N+j*N+i+2] - u_2[k*N*N+j*N+i])) + stry[j] * (muy1 * (u_2[k*N*N+(j-2)*N+i] - u_2[k*N*N+j*N+i]) + muy2 * (u_2[k*N*N+(j-1)*N+i] - u_2[k*N*N+j*N+i]) + muy3 * (u_2[k*N*N+(j+1)*N+i] - u_2[k*N*N+j*N+i]) + muy4 * (u_2[k*N*N+(j+2)*N+i] - u_2[k*N*N+j*N+i])) + strz[k] * ((2 * muz1 + la[(k-1)*N*N+j*N+i] * strz[k-1] - 3e0 / 4 * (la[k*N*N+j*N+i] * strz[k] + la[(k-2)*N*N+j*N+i] * strz[k-2])) * (u_2[(k-2)*N*N+j*N+i] - u_2[k*N*N+j*N+i]) + (2 * muz2 + la[(k-2)*N*N+j*N+i] * strz[k-2] + la[(k+1)*N*N+j*N+i] * strz[k+1] + 3 * (la[k*N*N+j*N+i] * strz[k] + la[(k-1)*N*N+j*N+i] * strz[k-1])) * (u_2[(k-1)*N*N+j*N+i] - u_2[k*N*N+j*N+i]) + (2 * muz3 + la[(k-1)*N*N+j*N+i] * strz[k-1] + la[(k+2)*N*N+j*N+i] * strz[k+2] + 3 * (la[(k+1)*N*N+j*N+i] * strz[k+1] + la[k*N*N+j*N+i] * strz[k])) * (u_2[(k+1)*N*N+j*N+i] - u_2[k*N*N+j*N+i]) + (2 * muz4 + la[(k+1)*N*N+j*N+i] * strz[k+1] - 3e0 / 4 * (la[k*N*N+j*N+i] * strz[k] + la[(k+2)*N*N+j*N+i] * strz[k+2])) * (u_2[(k+2)*N*N+j*N+i] - u_2[k*N*N+j*N+i])));
/* 120 * 3 = 360 flops */
r1 = r1 + strx[i] * stry[j] * (1e0 / 144) * (la[k*N*N+j*N+i-2] * (u_1[k*N*N+(j-2)*N+i-2] - u_1[k*N*N+(j+2)*N+i-2] + 8 * (-u_1[k*N*N+(j-1)*N+i-2] + u_1[k*N*N+(j+1)*N+i-2])) - 8 * (la[k*N*N+j*N+i-1] * (u_1[k*N*N+(j-2)*N+i-1] - u_1[k*N*N+(j+2)*N+i-1] + 8 * (-u_1[k*N*N+(j-1)*N+i-1] + u_1[k*N*N+(j+1)*N+i-1]))) + 8 * (la[k*N*N+j*N+i+1] * (u_1[k*N*N+(j-2)*N+i+1] - u_1[k*N*N+(j+2)*N+i+1] + 8 * (-u_1[k*N*N+(j-1)*N+i+1] + u_1[k*N*N+(j+1)*N+i+1]))) - (la[k*N*N+j*N+i+2] * (u_1[k*N*N+(j-2)*N+i+2] - u_1[k*N*N+(j+2)*N+i+2] + 8 * (-u_1[k*N*N+(j-1)*N+i+2] + u_1[k*N*N+(j+1)*N+i+2])))) + strx[i] * strz[k] * (1e0 / 144) * (la[k*N*N+j*N+i-2] * (u_2[(k-2)*N*N+j*N+i-2] - u_2[(k+2)*N*N+j*N+i-2] + 8 * (-u_2[(k-1)*N*N+j*N+i-2] + u_2[(k+1)*N*N+j*N+i-2])) - 8 * (la[k*N*N+j*N+i-1] * (u_2[(k-2)*N*N+j*N+i-1] - u_2[(k+2)*N*N+j*N+i-1] + 8 * (-u_2[(k-1)*N*N+j*N+i-1] + u_2[(k+1)*N*N+j*N+i-1]))) + 8 * (la[k*N*N+j*N+i+1] * (u_2[(k-2)*N*N+j*N+i+1] - u_2[(k+2)*N*N+j*N+i+1] + 8 * (-u_2[(k-1)*N*N+j*N+i+1] + u_2[(k+1)*N*N+j*N+i+1]))) - (la[k*N*N+j*N+i+2] * (u_2[(k-2)*N*N+j*N+i+2] - u_2[(k+2)*N*N+j*N+i+2] + 8 * (-u_2[(k-1)*N*N+j*N+i+2] + u_2[(k+1)*N*N+j*N+i+2])))) + strx[i] * stry[j] * (1e0 / 144) * (mu[k*N*N+(j-2)*N+i] * (u_1[k*N*N+(j-2)*N+i-2] - u_1[k*N*N+(j-2)*N+i+2] + 8 * (-u_1[k*N*N+(j-2)*N+i-1] + u_1[k*N*N+(j-2)*N+i+1])) - 8 * (mu[k*N*N+(j-1)*N+i] * (u_1[k*N*N+(j-1)*N+i-2] - u_1[k*N*N+(j-1)*N+i+2] + 8 * (-u_1[k*N*N+(j-1)*N+i-1] + u_1[k*N*N+(j-1)*N+i+1]))) + 8 * (mu[k*N*N+(j+1)*N+i] * (u_1[k*N*N+(j+1)*N+i-2] - u_1[k*N*N+(j+1)*N+i+2] + 8 * (-u_1[k*N*N+(j+1)*N+i-1] + u_1[k*N*N+(j+1)*N+i+1]))) - (mu[k*N*N+(j+2)*N+i] * (u_1[k*N*N+(j+2)*N+i-2] - u_1[k*N*N+(j+2)*N+i+2] + 8 * (-u_1[k*N*N+(j+2)*N+i-1] + u_1[k*N*N+(j+2)*N+i+1])))) + strx[i] * strz[k] * (1e0 / 144) * (mu[(k-2)*N*N+j*N+i] * (u_2[(k-2)*N*N+j*N+i-2] - u_2[(k-2)*N*N+j*N+i+2] + 8 * (-u_2[(k-2)*N*N+j*N+i-1] + u_2[(k-2)*N*N+j*N+i+1])) - 8 * (mu[(k-1)*N*N+j*N+i] * (u_2[(k-1)*N*N+j*N+i-2] - u_2[(k-1)*N*N+j*N+i+2] + 8 * (-u_2[(k-1)*N*N+j*N+i-1] + u_2[(k-1)*N*N+j*N+i+1]))) + 8 * (mu[(k+1)*N*N+j*N+i] * (u_2[(k+1)*N*N+j*N+i-2] - u_2[(k+1)*N*N+j*N+i+2] + 8 * (-u_2[(k+1)*N*N+j*N+i-1] + u_2[(k+1)*N*N+j*N+i+1]))) - (mu[(k+2)*N*N+j*N+i] * (u_2[(k+2)*N*N+j*N+i-2] - u_2[(k+2)*N*N+j*N+i+2] + 8 * (-u_2[(k+2)*N*N+j*N+i-1] + u_2[(k+2)*N*N+j*N+i+1]))));
r2 = r2 + strx[i] * stry[j] * (1e0 / 144) * (mu[k*N*N+j*N+i-2] * (u_0[k*N*N+(j-2)*N+i-2] - u_0[k*N*N+(j+2)*N+i-2] + 8 * (-u_0[k*N*N+(j-1)*N+i-2] + u_0[k*N*N+(j+1)*N+i-2])) - 8 * (mu[k*N*N+j*N+i-1] * (u_0[k*N*N+(j-2)*N+i-1] - u_0[k*N*N+(j+2)*N+i-1] + 8 * (-u_0[k*N*N+(j-1)*N+i-1] + u_0[k*N*N+(j+1)*N+i-1]))) + 8 * (mu[k*N*N+j*N+i+1] * (u_0[k*N*N+(j-2)*N+i+1] - u_0[k*N*N+(j+2)*N+i+1] + 8 * (-u_0[k*N*N+(j-1)*N+i+1] + u_0[k*N*N+(j+1)*N+i+1]))) - (mu[k*N*N+j*N+i+2] * (u_0[k*N*N+(j-2)*N+i+2] - u_0[k*N*N+(j+2)*N+i+2] + 8 * (-u_0[k*N*N+(j-1)*N+i+2] + u_0[k*N*N+(j+1)*N+i+2])))) + strx[i] * stry[j] * (1e0 / 144) * (la[k*N*N+(j-2)*N+i] * (u_0[k*N*N+(j-2)*N+i-2] - u_0[k*N*N+(j-2)*N+i+2] + 8 * (-u_0[k*N*N+(j-2)*N+i-1] + u_0[k*N*N+(j-2)*N+i+1])) - 8 * (la[k*N*N+(j-1)*N+i] * (u_0[k*N*N+(j-1)*N+i-2] - u_0[k*N*N+(j-1)*N+i+2] + 8 * (-u_0[k*N*N+(j-1)*N+i-1] + u_0[k*N*N+(j-1)*N+i+1]))) + 8 * (la[k*N*N+(j+1)*N+i] * (u_0[k*N*N+(j+1)*N+i-2] - u_0[k*N*N+(j+1)*N+i+2] + 8 * (-u_0[k*N*N+(j+1)*N+i-1] + u_0[k*N*N+(j+1)*N+i+1]))) - (la[k*N*N+(j+2)*N+i] * (u_0[k*N*N+(j+2)*N+i-2] - u_0[k*N*N+(j+2)*N+i+2] + 8 * (-u_0[k*N*N+(j+2)*N+i-1] + u_0[k*N*N+(j+2)*N+i+1])))) + stry[j] * strz[k] * (1e0 / 144) * (la[k*N*N+(j-2)*N+i] * (u_2[(k-2)*N*N+(j-2)*N+i] - u_2[(k+2)*N*N+(j-2)*N+i] + 8 * (-u_2[(k-1)*N*N+(j-2)*N+i] + u_2[(k+1)*N*N+(j-2)*N+i])) - 8 * (la[k*N*N+(j-1)*N+i] * (u_2[(k-2)*N*N+(j-1)*N+i] - u_2[(k+2)*N*N+(j-1)*N+i] + 8 * (-u_2[(k-1)*N*N+(j-1)*N+i] + u_2[(k+1)*N*N+(j-1)*N+i]))) + 8 * (la[k*N*N+(j+1)*N+i] * (u_2[(k-2)*N*N+(j+1)*N+i] - u_2[(k+2)*N*N+(j+1)*N+i] + 8 * (-u_2[(k-1)*N*N+(j+1)*N+i] + u_2[(k+1)*N*N+(j+1)*N+i]))) - (la[k*N*N+(j+2)*N+i] * (u_2[(k-2)*N*N+(j+2)*N+i] - u_2[(k+2)*N*N+(j+2)*N+i] + 8 * (-u_2[(k-1)*N*N+(j+2)*N+i] + u_2[(k+1)*N*N+(j+2)*N+i])))) + stry[j] * strz[k] * (1e0 / 144) * (mu[(k-2)*N*N+j*N+i] * (u_2[(k-2)*N*N+(j-2)*N+i] - u_2[(k-2)*N*N+(j+2)*N+i] + 8 * (-u_2[(k-2)*N*N+(j-1)*N+i] + u_2[(k-2)*N*N+(j+1)*N+i])) - 8 * (mu[(k-1)*N*N+j*N+i] * (u_2[(k-1)*N*N+(j-2)*N+i] - u_2[(k-1)*N*N+(j+2)*N+i] + 8 * (-u_2[(k-1)*N*N+(j-1)*N+i] + u_2[(k-1)*N*N+(j+1)*N+i]))) + 8 * (mu[(k+1)*N*N+j*N+i] * (u_2[(k+1)*N*N+(j-2)*N+i] - u_2[(k+1)*N*N+(j+2)*N+i] + 8 * (-u_2[(k+1)*N*N+(j-1)*N+i] + u_2[(k+1)*N*N+(j+1)*N+i]))) - (mu[(k+2)*N*N+j*N+i] * (u_2[(k+2)*N*N+(j-2)*N+i] - u_2[(k+2)*N*N+(j+2)*N+i] + 8 * (-u_2[(k+2)*N*N+(j-1)*N+i] + u_2[(k+2)*N*N+(j+1)*N+i]))));
r3 = r3 + strx[i] * strz[k] * (1e0 / 144) * (mu[k*N*N+j*N+i-2] * (u_0[(k-2)*N*N+j*N+i-2] - u_0[(k+2)*N*N+j*N+i-2] + 8 * (-u_0[(k-1)*N*N+j*N+i-2] + u_0[(k+1)*N*N+j*N+i-2])) - 8 * (mu[k*N*N+j*N+i-1] * (u_0[(k-2)*N*N+j*N+i-1] - u_0[(k+2)*N*N+j*N+i-1] + 8 * (-u_0[(k-1)*N*N+j*N+i-1] + u_0[(k+1)*N*N+j*N+i-1]))) + 8 * (mu[k*N*N+j*N+i+1] * (u_0[(k-2)*N*N+j*N+i+1] - u_0[(k+2)*N*N+j*N+i+1] + 8 * (-u_0[(k-1)*N*N+j*N+i+1] + u_0[(k+1)*N*N+j*N+i+1]))) - (mu[k*N*N+j*N+i+2] * (u_0[(k-2)*N*N+j*N+i+2] - u_0[(k+2)*N*N+j*N+i+2] + 8 * (-u_0[(k-1)*N*N+j*N+i+2] + u_0[(k+1)*N*N+j*N+i+2])))) + stry[j] * strz[k] * (1e0 / 144) * (mu[k*N*N+(j-2)*N+i] * (u_1[(k-2)*N*N+(j-2)*N+i] - u_1[(k+2)*N*N+(j-2)*N+i] + 8 * (-u_1[(k-1)*N*N+(j-2)*N+i] + u_1[(k+1)*N*N+(j-2)*N+i])) - 8 * (mu[k*N*N+(j-1)*N+i] * (u_1[(k-2)*N*N+(j-1)*N+i] - u_1[(k+2)*N*N+(j-1)*N+i] + 8 * (-u_1[(k-1)*N*N+(j-1)*N+i] + u_1[(k+1)*N*N+(j-1)*N+i]))) + 8 * (mu[k*N*N+(j+1)*N+i] * (u_1[(k-2)*N*N+(j+1)*N+i] - u_1[(k+2)*N*N+(j+1)*N+i] + 8 * (-u_1[(k-1)*N*N+(j+1)*N+i] + u_1[(k+1)*N*N+(j+1)*N+i]))) - (mu[k*N*N+(j+2)*N+i] * (u_1[(k-2)*N*N+(j+2)*N+i] - u_1[(k+2)*N*N+(j+2)*N+i] + 8 * (-u_1[(k-1)*N*N+(j+2)*N+i] + u_1[(k+1)*N*N+(j+2)*N+i])))) + strx[i] * strz[k] * (1e0 / 144) * (la[(k-2)*N*N+j*N+i] * (u_0[(k-2)*N*N+j*N+i-2] - u_0[(k-2)*N*N+j*N+i+2] + 8 * (-u_0[(k-2)*N*N+j*N+i-1] + u_0[(k-2)*N*N+j*N+i+1])) - 8 * (la[(k-1)*N*N+j*N+i] * (u_0[(k-1)*N*N+j*N+i-2] - u_0[(k-1)*N*N+j*N+i+2] + 8 * (-u_0[(k-1)*N*N+j*N+i-1] + u_0[(k-1)*N*N+j*N+i+1]))) + 8 * (la[(k+1)*N*N+j*N+i] * (u_0[(k+1)*N*N+j*N+i-2] - u_0[(k+1)*N*N+j*N+i+2] + 8 * (-u_0[(k+1)*N*N+j*N+i-1] + u_0[(k+1)*N*N+j*N+i+1]))) - (la[(k+2)*N*N+j*N+i] * (u_0[(k+2)*N*N+j*N+i-2] - u_0[(k+2)*N*N+j*N+i+2] + 8 * (-u_0[(k+2)*N*N+j*N+i-1] + u_0[(k+2)*N*N+j*N+i+1])))) + stry[j] * strz[k] * (1e0 / 144) * (la[(k-2)*N*N+j*N+i] * (u_1[(k-2)*N*N+(j-2)*N+i] - u_1[(k-2)*N*N+(j+2)*N+i] + 8 * (-u_1[(k-2)*N*N+(j-1)*N+i] + u_1[(k-2)*N*N+(j+1)*N+i])) - 8 * (la[(k-1)*N*N+j*N+i] * (u_1[(k-1)*N*N+(j-2)*N+i] - u_1[(k-1)*N*N+(j+2)*N+i] + 8 * (-u_1[(k-1)*N*N+(j-1)*N+i] + u_1[(k-1)*N*N+(j+1)*N+i]))) + 8 * (la[(k+1)*N*N+j*N+i] * (u_1[(k+1)*N*N+(j-2)*N+i] - u_1[(k+1)*N*N+(j+2)*N+i] + 8 * (-u_1[(k+1)*N*N+(j-1)*N+i] + u_1[(k+1)*N*N+(j+1)*N+i]))) - (la[(k+2)*N*N+j*N+i] * (u_1[(k+2)*N*N+(j-2)*N+i] - u_1[(k+2)*N*N+(j+2)*N+i] + 8 * (-u_1[(k+2)*N*N+(j-1)*N+i] + u_1[(k+2)*N*N+(j+1)*N+i]))));
/* 3 * 3 = 9 flops */
uacc_0[k*N*N+j*N+i] = a1 * uacc_0[k*N*N+j*N+i] + cof * r1;
uacc_1[k*N*N+j*N+i] = a1 * uacc_1[k*N*N+j*N+i] + cof * r2;
uacc_2[k*N*N+j*N+i] = a1 * uacc_2[k*N*N+j*N+i] + cof * r3;
}
}
extern "C" void host_code (float *h_uacc_0, float *h_uacc_1, float *h_uacc_2, float *h_u_0, float *h_u_1, float *h_u_2, float *h_mu, float *h_la, float *h_strx, float *h_stry, float *h_strz, int N) {
float *uacc_0;
hipMalloc (&uacc_0, sizeof(float)*N*N*N);
check_error ("Failed to allocate device memory for uacc_0\n");
hipMemcpy (uacc_0, h_uacc_0, sizeof(float)*N*N*N, hipMemcpyHostToDevice);
float *uacc_1;
hipMalloc (&uacc_1, sizeof(float)*N*N*N);
check_error ("Failed to allocate device memory for uacc_1\n");
hipMemcpy (uacc_1, h_uacc_1, sizeof(float)*N*N*N, hipMemcpyHostToDevice);
float *uacc_2;
hipMalloc (&uacc_2, sizeof(float)*N*N*N);
check_error ("Failed to allocate device memory for uacc_2\n");
hipMemcpy (uacc_2, h_uacc_2, sizeof(float)*N*N*N, hipMemcpyHostToDevice);
float *u_0;
hipMalloc (&u_0, sizeof(float)*N*N*N);
check_error ("Failed to allocate device memory for u_0\n");
hipMemcpy (u_0, h_u_0, sizeof(float)*N*N*N, hipMemcpyHostToDevice);
float *u_1;
hipMalloc (&u_1, sizeof(float)*N*N*N);
check_error ("Failed to allocate device memory for u_1\n");
hipMemcpy (u_1, h_u_1, sizeof(float)*N*N*N, hipMemcpyHostToDevice);
float *u_2;
hipMalloc (&u_2, sizeof(float)*N*N*N);
check_error ("Failed to allocate device memory for u_2\n");
hipMemcpy (u_2, h_u_2, sizeof(float)*N*N*N, hipMemcpyHostToDevice);
float *mu;
hipMalloc (&mu, sizeof(float)*N*N*N);
check_error ("Failed to allocate device memory for mu\n");
hipMemcpy (mu, h_mu, sizeof(float)*N*N*N, hipMemcpyHostToDevice);
float *la;
hipMalloc (&la, sizeof(float)*N*N*N);
check_error ("Failed to allocate device memory for la\n");
hipMemcpy (la, h_la, sizeof(float)*N*N*N, hipMemcpyHostToDevice);
float *strx;
hipMalloc (&strx, sizeof(float)*N);
check_error ("Failed to allocate device memory for strx\n");
hipMemcpy (strx, h_strx, sizeof(float)*N, hipMemcpyHostToDevice);
float *stry;
hipMalloc (&stry, sizeof(float)*N);
check_error ("Failed to allocate device memory for stry\n");
hipMemcpy (stry, h_stry, sizeof(float)*N, hipMemcpyHostToDevice);
float *strz;
hipMalloc (&strz, sizeof(float)*N);
check_error ("Failed to allocate device memory for strz\n");
hipMemcpy (strz, h_strz, sizeof(float)*N, hipMemcpyHostToDevice);
dim3 blockconfig (32, 4, 2);
dim3 gridconfig (ceil(N, blockconfig.x), ceil(N, blockconfig.y), ceil(N, blockconfig.z));
sw4 <<<gridconfig, blockconfig>>> (uacc_0, uacc_1, uacc_2, u_0, u_1, u_2, mu, la, strx, stry, strz, N);
hipMemcpy (h_uacc_0, uacc_0, sizeof(float)*N*N*N, hipMemcpyDeviceToHost);
hipMemcpy (h_uacc_1, uacc_1, sizeof(float)*N*N*N, hipMemcpyDeviceToHost);
hipMemcpy (h_uacc_2, uacc_2, sizeof(float)*N*N*N, hipMemcpyDeviceToHost);
hipFree (uacc_0);
hipFree (uacc_1);
hipFree (uacc_2);
hipFree (u_0);
hipFree (u_1);
hipFree (u_2);
hipFree (mu);
hipFree (la);
hipFree (strx);
hipFree (stry);
hipFree (strz);
} | .text
.file "kernel.hip"
.globl _Z11check_errorPKc # -- Begin function _Z11check_errorPKc
.p2align 4, 0x90
.type _Z11check_errorPKc,@function
_Z11check_errorPKc: # @_Z11check_errorPKc
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
callq hipGetLastError
testl %eax, %eax
jne .LBB0_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 16
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rbx, %rsi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end0:
.size _Z11check_errorPKc, .Lfunc_end0-_Z11check_errorPKc
.cfi_endproc
# -- End function
.globl _Z18__device_stub__sw4PfS_S_S_S_S_S_S_S_S_S_i # -- Begin function _Z18__device_stub__sw4PfS_S_S_S_S_S_S_S_S_S_i
.p2align 4, 0x90
.type _Z18__device_stub__sw4PfS_S_S_S_S_S_S_S_S_S_i,@function
_Z18__device_stub__sw4PfS_S_S_S_S_S_S_S_S_S_i: # @_Z18__device_stub__sw4PfS_S_S_S_S_S_S_S_S_S_i
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3sw4PfS_S_S_S_S_S_S_S_S_S_i, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end1:
.size _Z18__device_stub__sw4PfS_S_S_S_S_S_S_S_S_S_i, .Lfunc_end1-_Z18__device_stub__sw4PfS_S_S_S_S_S_S_S_S_S_i
.cfi_endproc
# -- End function
.globl host_code # -- Begin function host_code
.p2align 4, 0x90
.type host_code,@function
host_code: # @host_code
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $376, %rsp # imm = 0x178
.cfi_def_cfa_offset 432
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, 128(%rsp) # 8-byte Spill
movq %r8, %rbx
movq %rcx, %r15
movq %rdx, 104(%rsp) # 8-byte Spill
movq %rsi, 112(%rsp) # 8-byte Spill
movq %rdi, %rbp
movslq 472(%rsp), %r12
leaq (,%r12,4), %r13
movq %r12, %r14
imulq %r12, %r14
imulq %r13, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB2_1
# %bb.3: # %_Z11check_errorPKc.exit
movq 24(%rsp), %rdi
movq %rbp, 120(%rsp) # 8-byte Spill
movq %rbp, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB2_4
# %bb.5: # %_Z11check_errorPKc.exit93
movq 16(%rsp), %rdi
movq 112(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB2_6
# %bb.7: # %_Z11check_errorPKc.exit95
movq 8(%rsp), %rdi
movq 104(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 88(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB2_8
# %bb.9: # %_Z11check_errorPKc.exit97
movq 88(%rsp), %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 80(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB2_10
# %bb.11: # %_Z11check_errorPKc.exit99
movq 80(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 72(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB2_12
# %bb.13: # %_Z11check_errorPKc.exit101
movq 72(%rsp), %rdi
movq 128(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 64(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB2_14
# %bb.15: # %_Z11check_errorPKc.exit103
movq 432(%rsp), %rsi
movq 64(%rsp), %rdi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 56(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
movq 120(%rsp), %rbp # 8-byte Reload
jne .LBB2_16
# %bb.17: # %_Z11check_errorPKc.exit105
movq 440(%rsp), %rsi
movq 56(%rsp), %rdi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 48(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB2_18
# %bb.19: # %_Z11check_errorPKc.exit107
movq 448(%rsp), %rsi
movq 48(%rsp), %rdi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 40(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB2_20
# %bb.21: # %_Z11check_errorPKc.exit109
movq 456(%rsp), %rsi
movq 40(%rsp), %rdi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 32(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB2_22
# %bb.23: # %_Z11check_errorPKc.exit111
movq 464(%rsp), %rsi
movq 32(%rsp), %rdi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movl %r12d, %eax
shrl $5, %eax
leal 1(%rax), %ecx
testb $31, %r12b
cmovel %eax, %ecx
movl %r12d, %eax
shrl $2, %eax
leal 1(%rax), %edi
testb $3, %r12b
cmovel %eax, %edi
movl %r12d, %eax
shrl %eax
leal 1(%rax), %esi
testb $1, %r12b
cmovel %eax, %esi
shlq $32, %rdi
orq %rcx, %rdi
movabsq $17179869216, %rdx # imm = 0x400000020
movl $2, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_25
# %bb.24:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq 88(%rsp), %rsi
movq 80(%rsp), %rdi
movq 72(%rsp), %r8
movq 64(%rsp), %r9
movq 56(%rsp), %r10
movq 48(%rsp), %r11
movq 40(%rsp), %rbx
movq 32(%rsp), %r15
movq %rax, 264(%rsp)
movq %rcx, 256(%rsp)
movq %rdx, 248(%rsp)
movq %rsi, 240(%rsp)
movq %rdi, 232(%rsp)
movq %r8, 224(%rsp)
movq %r9, 216(%rsp)
movq %r10, 208(%rsp)
movq %r11, 200(%rsp)
movq %rbx, 192(%rsp)
movq %r15, 184(%rsp)
movl %r12d, 100(%rsp)
leaq 264(%rsp), %rax
movq %rax, 272(%rsp)
leaq 256(%rsp), %rax
movq %rax, 280(%rsp)
leaq 248(%rsp), %rax
movq %rax, 288(%rsp)
leaq 240(%rsp), %rax
movq %rax, 296(%rsp)
leaq 232(%rsp), %rax
movq %rax, 304(%rsp)
leaq 224(%rsp), %rax
movq %rax, 312(%rsp)
leaq 216(%rsp), %rax
movq %rax, 320(%rsp)
leaq 208(%rsp), %rax
movq %rax, 328(%rsp)
leaq 200(%rsp), %rax
movq %rax, 336(%rsp)
leaq 192(%rsp), %rax
movq %rax, 344(%rsp)
leaq 184(%rsp), %rax
movq %rax, 352(%rsp)
leaq 100(%rsp), %rax
movq %rax, 360(%rsp)
leaq 168(%rsp), %rdi
leaq 152(%rsp), %rsi
leaq 144(%rsp), %rdx
leaq 136(%rsp), %rcx
callq __hipPopCallConfiguration
movq 168(%rsp), %rsi
movl 176(%rsp), %edx
movq 152(%rsp), %rcx
movl 160(%rsp), %r8d
leaq 272(%rsp), %r9
movl $_Z3sw4PfS_S_S_S_S_S_S_S_S_S_i, %edi
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_25:
movq 24(%rsp), %rsi
movq %rbp, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rsi
movq 112(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rsi
movq 104(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 88(%rsp), %rdi
callq hipFree
movq 80(%rsp), %rdi
callq hipFree
movq 72(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
addq $376, %rsp # imm = 0x178
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_1:
.cfi_def_cfa_offset 432
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
jmp .LBB2_2
.LBB2_4:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.2, %esi
jmp .LBB2_2
.LBB2_6:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.3, %esi
jmp .LBB2_2
.LBB2_8:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.4, %esi
jmp .LBB2_2
.LBB2_10:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.5, %esi
jmp .LBB2_2
.LBB2_12:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.6, %esi
jmp .LBB2_2
.LBB2_14:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.7, %esi
jmp .LBB2_2
.LBB2_16:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.8, %esi
jmp .LBB2_2
.LBB2_18:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.9, %esi
jmp .LBB2_2
.LBB2_20:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.10, %esi
jmp .LBB2_2
.LBB2_22:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.11, %esi
.LBB2_2:
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end2:
.size host_code, .Lfunc_end2-host_code
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3sw4PfS_S_S_S_S_S_S_S_S_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA error : %s, %s\n"
.size .L.str, 21
.type _Z3sw4PfS_S_S_S_S_S_S_S_S_S_i,@object # @_Z3sw4PfS_S_S_S_S_S_S_S_S_S_i
.section .rodata,"a",@progbits
.globl _Z3sw4PfS_S_S_S_S_S_S_S_S_S_i
.p2align 3, 0x0
_Z3sw4PfS_S_S_S_S_S_S_S_S_S_i:
.quad _Z18__device_stub__sw4PfS_S_S_S_S_S_S_S_S_S_i
.size _Z3sw4PfS_S_S_S_S_S_S_S_S_S_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Failed to allocate device memory for uacc_0\n"
.size .L.str.1, 45
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Failed to allocate device memory for uacc_1\n"
.size .L.str.2, 45
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Failed to allocate device memory for uacc_2\n"
.size .L.str.3, 45
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Failed to allocate device memory for u_0\n"
.size .L.str.4, 42
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Failed to allocate device memory for u_1\n"
.size .L.str.5, 42
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Failed to allocate device memory for u_2\n"
.size .L.str.6, 42
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Failed to allocate device memory for mu\n"
.size .L.str.7, 41
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Failed to allocate device memory for la\n"
.size .L.str.8, 41
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Failed to allocate device memory for strx\n"
.size .L.str.9, 43
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Failed to allocate device memory for stry\n"
.size .L.str.10, 43
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Failed to allocate device memory for strz\n"
.size .L.str.11, 43
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3sw4PfS_S_S_S_S_S_S_S_S_S_i"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__sw4PfS_S_S_S_S_S_S_S_S_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3sw4PfS_S_S_S_S_S_S_S_S_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000619c4_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA error : %s, %s\n"
.text
.globl _Z11check_errorPKc
.type _Z11check_errorPKc, @function
_Z11check_errorPKc:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movq %rbx, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z11check_errorPKc, .-_Z11check_errorPKc
.globl _Z43__device_stub__Z3sw4PfS_S_S_S_S_S_S_S_S_S_iPfS_S_S_S_S_S_S_S_S_S_i
.type _Z43__device_stub__Z3sw4PfS_S_S_S_S_S_S_S_S_S_iPfS_S_S_S_S_S_S_S_S_S_i, @function
_Z43__device_stub__Z3sw4PfS_S_S_S_S_S_S_S_S_S_iPfS_S_S_S_S_S_S_S_S_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $280, %rsp
.cfi_def_cfa_offset 288
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
movq %rdi, 8(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movq %rsi, 16(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
movq %rdx, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 176(%rsp)
movq %rcx, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
movq %r8, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 192(%rsp)
movq %r9, 48(%rsp)
leaq 48(%rsp), %rax
movq %rax, 200(%rsp)
movq 288(%rsp), %rax
movq %rax, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 208(%rsp)
movq 296(%rsp), %rax
movq %rax, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, 216(%rsp)
movq 304(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 224(%rsp)
movq 312(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 232(%rsp)
movq 320(%rsp), %rax
movq %rax, 88(%rsp)
leaq 88(%rsp), %rax
movq %rax, 240(%rsp)
leaq 328(%rsp), %rax
movq %rax, 248(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
leaq 104(%rsp), %rcx
leaq 96(%rsp), %rdx
leaq 124(%rsp), %rsi
leaq 112(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 104(%rsp)
.cfi_def_cfa_offset 296
pushq 104(%rsp)
.cfi_def_cfa_offset 304
leaq 176(%rsp), %r9
movq 140(%rsp), %rcx
movl 148(%rsp), %r8d
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
leaq _Z3sw4PfS_S_S_S_S_S_S_S_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 288
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z43__device_stub__Z3sw4PfS_S_S_S_S_S_S_S_S_S_iPfS_S_S_S_S_S_S_S_S_S_i, .-_Z43__device_stub__Z3sw4PfS_S_S_S_S_S_S_S_S_S_iPfS_S_S_S_S_S_S_S_S_S_i
.globl _Z3sw4PfS_S_S_S_S_S_S_S_S_S_i
.type _Z3sw4PfS_S_S_S_S_S_S_S_S_S_i, @function
_Z3sw4PfS_S_S_S_S_S_S_S_S_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 56(%rsp)
.cfi_def_cfa_offset 32
pushq 56(%rsp)
.cfi_def_cfa_offset 40
pushq 56(%rsp)
.cfi_def_cfa_offset 48
pushq 56(%rsp)
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z43__device_stub__Z3sw4PfS_S_S_S_S_S_S_S_S_S_iPfS_S_S_S_S_S_S_S_S_S_i
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z3sw4PfS_S_S_S_S_S_S_S_S_S_i, .-_Z3sw4PfS_S_S_S_S_S_S_S_S_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Failed to allocate device memory for uacc_0\n"
.align 8
.LC2:
.string "Failed to allocate device memory for uacc_1\n"
.align 8
.LC3:
.string "Failed to allocate device memory for uacc_2\n"
.align 8
.LC4:
.string "Failed to allocate device memory for u_0\n"
.align 8
.LC5:
.string "Failed to allocate device memory for u_1\n"
.align 8
.LC6:
.string "Failed to allocate device memory for u_2\n"
.align 8
.LC7:
.string "Failed to allocate device memory for mu\n"
.align 8
.LC8:
.string "Failed to allocate device memory for la\n"
.align 8
.LC9:
.string "Failed to allocate device memory for strx\n"
.align 8
.LC10:
.string "Failed to allocate device memory for stry\n"
.align 8
.LC11:
.string "Failed to allocate device memory for strz\n"
.text
.globl host_code
.type host_code, @function
host_code:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $200, %rsp
.cfi_def_cfa_offset 256
movq %rdi, (%rsp)
movq %rsi, 8(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 32(%rsp)
movq %r9, 40(%rsp)
movq 256(%rsp), %r15
movq 264(%rsp), %r14
movq 272(%rsp), %r13
movq 280(%rsp), %rax
movq %rax, 48(%rsp)
movq 288(%rsp), %rbx
movq %rbx, 56(%rsp)
movl 296(%rsp), %r12d
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
movslq %r12d, %rbp
movq %rbp, %rbx
imulq %rbp, %rbx
imulq %rbp, %rbx
salq $2, %rbx
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC1(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbx, %rdx
movq (%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
leaq 80(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC2(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
leaq 88(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC3(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
leaq 96(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC4(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq 96(%rsp), %rdi
call cudaMemcpy@PLT
leaq 104(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC5(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbx, %rdx
movq 32(%rsp), %rsi
movq 104(%rsp), %rdi
call cudaMemcpy@PLT
leaq 112(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC6(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq 112(%rsp), %rdi
call cudaMemcpy@PLT
leaq 120(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC7(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbx, %rdx
movq %r15, %rsi
movq 120(%rsp), %rdi
call cudaMemcpy@PLT
leaq 128(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC8(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 128(%rsp), %rdi
call cudaMemcpy@PLT
salq $2, %rbp
leaq 136(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq .LC9(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbp, %rdx
movq %r13, %rsi
movq 136(%rsp), %rdi
call cudaMemcpy@PLT
leaq 144(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq .LC10(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbp, %rdx
movq 48(%rsp), %rsi
movq 144(%rsp), %rdi
call cudaMemcpy@PLT
leaq 152(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq .LC11(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbp, %rdx
movq 56(%rsp), %rsi
movq 152(%rsp), %rdi
call cudaMemcpy@PLT
movl %r12d, %eax
shrl %eax
movl %eax, %esi
addl $1, %esi
testb $1, %r12b
cmove %eax, %esi
movl %r12d, %edx
shrl $2, %edx
movl %edx, %eax
addl $1, %eax
testb $3, %r12b
cmove %edx, %eax
movl %r12d, %ecx
shrl $5, %ecx
movl %ecx, %edx
addl $1, %edx
testb $31, %r12b
cmove %ecx, %edx
movl %edx, 172(%rsp)
movl %eax, 176(%rsp)
movl $32, 160(%rsp)
movl $4, 164(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 160(%rsp), %rdx
movl $2, %ecx
movq 172(%rsp), %rdi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L22:
movl $2, %ecx
movq %rbx, %rdx
movq 72(%rsp), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 80(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 88(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 112(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rdi
call cudaFree@PLT
movq 128(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rdi
call cudaFree@PLT
movq 144(%rsp), %rdi
call cudaFree@PLT
movq 152(%rsp), %rdi
call cudaFree@PLT
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq %r12
.cfi_def_cfa_offset 264
pushq 160(%rsp)
.cfi_def_cfa_offset 272
pushq 160(%rsp)
.cfi_def_cfa_offset 280
pushq 160(%rsp)
.cfi_def_cfa_offset 288
pushq 160(%rsp)
.cfi_def_cfa_offset 296
pushq 160(%rsp)
.cfi_def_cfa_offset 304
movq 160(%rsp), %r9
movq 152(%rsp), %r8
movq 144(%rsp), %rcx
movq 136(%rsp), %rdx
movq 128(%rsp), %rsi
movq 120(%rsp), %rdi
call _Z43__device_stub__Z3sw4PfS_S_S_S_S_S_S_S_S_S_iPfS_S_S_S_S_S_S_S_S_S_i
addq $48, %rsp
.cfi_def_cfa_offset 256
jmp .L22
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size host_code, .-host_code
.section .rodata.str1.1
.LC12:
.string "_Z3sw4PfS_S_S_S_S_S_S_S_S_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z3sw4PfS_S_S_S_S_S_S_S_S_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z11check_errorPKc # -- Begin function _Z11check_errorPKc
.p2align 4, 0x90
.type _Z11check_errorPKc,@function
_Z11check_errorPKc: # @_Z11check_errorPKc
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
callq hipGetLastError
testl %eax, %eax
jne .LBB0_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 16
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rbx, %rsi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end0:
.size _Z11check_errorPKc, .Lfunc_end0-_Z11check_errorPKc
.cfi_endproc
# -- End function
.globl _Z18__device_stub__sw4PfS_S_S_S_S_S_S_S_S_S_i # -- Begin function _Z18__device_stub__sw4PfS_S_S_S_S_S_S_S_S_S_i
.p2align 4, 0x90
.type _Z18__device_stub__sw4PfS_S_S_S_S_S_S_S_S_S_i,@function
_Z18__device_stub__sw4PfS_S_S_S_S_S_S_S_S_S_i: # @_Z18__device_stub__sw4PfS_S_S_S_S_S_S_S_S_S_i
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3sw4PfS_S_S_S_S_S_S_S_S_S_i, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end1:
.size _Z18__device_stub__sw4PfS_S_S_S_S_S_S_S_S_S_i, .Lfunc_end1-_Z18__device_stub__sw4PfS_S_S_S_S_S_S_S_S_S_i
.cfi_endproc
# -- End function
.globl host_code # -- Begin function host_code
.p2align 4, 0x90
.type host_code,@function
host_code: # @host_code
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $376, %rsp # imm = 0x178
.cfi_def_cfa_offset 432
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, 128(%rsp) # 8-byte Spill
movq %r8, %rbx
movq %rcx, %r15
movq %rdx, 104(%rsp) # 8-byte Spill
movq %rsi, 112(%rsp) # 8-byte Spill
movq %rdi, %rbp
movslq 472(%rsp), %r12
leaq (,%r12,4), %r13
movq %r12, %r14
imulq %r12, %r14
imulq %r13, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB2_1
# %bb.3: # %_Z11check_errorPKc.exit
movq 24(%rsp), %rdi
movq %rbp, 120(%rsp) # 8-byte Spill
movq %rbp, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB2_4
# %bb.5: # %_Z11check_errorPKc.exit93
movq 16(%rsp), %rdi
movq 112(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB2_6
# %bb.7: # %_Z11check_errorPKc.exit95
movq 8(%rsp), %rdi
movq 104(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 88(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB2_8
# %bb.9: # %_Z11check_errorPKc.exit97
movq 88(%rsp), %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 80(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB2_10
# %bb.11: # %_Z11check_errorPKc.exit99
movq 80(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 72(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB2_12
# %bb.13: # %_Z11check_errorPKc.exit101
movq 72(%rsp), %rdi
movq 128(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 64(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB2_14
# %bb.15: # %_Z11check_errorPKc.exit103
movq 432(%rsp), %rsi
movq 64(%rsp), %rdi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 56(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
movq 120(%rsp), %rbp # 8-byte Reload
jne .LBB2_16
# %bb.17: # %_Z11check_errorPKc.exit105
movq 440(%rsp), %rsi
movq 56(%rsp), %rdi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 48(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB2_18
# %bb.19: # %_Z11check_errorPKc.exit107
movq 448(%rsp), %rsi
movq 48(%rsp), %rdi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 40(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB2_20
# %bb.21: # %_Z11check_errorPKc.exit109
movq 456(%rsp), %rsi
movq 40(%rsp), %rdi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 32(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB2_22
# %bb.23: # %_Z11check_errorPKc.exit111
movq 464(%rsp), %rsi
movq 32(%rsp), %rdi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movl %r12d, %eax
shrl $5, %eax
leal 1(%rax), %ecx
testb $31, %r12b
cmovel %eax, %ecx
movl %r12d, %eax
shrl $2, %eax
leal 1(%rax), %edi
testb $3, %r12b
cmovel %eax, %edi
movl %r12d, %eax
shrl %eax
leal 1(%rax), %esi
testb $1, %r12b
cmovel %eax, %esi
shlq $32, %rdi
orq %rcx, %rdi
movabsq $17179869216, %rdx # imm = 0x400000020
movl $2, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_25
# %bb.24:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq 88(%rsp), %rsi
movq 80(%rsp), %rdi
movq 72(%rsp), %r8
movq 64(%rsp), %r9
movq 56(%rsp), %r10
movq 48(%rsp), %r11
movq 40(%rsp), %rbx
movq 32(%rsp), %r15
movq %rax, 264(%rsp)
movq %rcx, 256(%rsp)
movq %rdx, 248(%rsp)
movq %rsi, 240(%rsp)
movq %rdi, 232(%rsp)
movq %r8, 224(%rsp)
movq %r9, 216(%rsp)
movq %r10, 208(%rsp)
movq %r11, 200(%rsp)
movq %rbx, 192(%rsp)
movq %r15, 184(%rsp)
movl %r12d, 100(%rsp)
leaq 264(%rsp), %rax
movq %rax, 272(%rsp)
leaq 256(%rsp), %rax
movq %rax, 280(%rsp)
leaq 248(%rsp), %rax
movq %rax, 288(%rsp)
leaq 240(%rsp), %rax
movq %rax, 296(%rsp)
leaq 232(%rsp), %rax
movq %rax, 304(%rsp)
leaq 224(%rsp), %rax
movq %rax, 312(%rsp)
leaq 216(%rsp), %rax
movq %rax, 320(%rsp)
leaq 208(%rsp), %rax
movq %rax, 328(%rsp)
leaq 200(%rsp), %rax
movq %rax, 336(%rsp)
leaq 192(%rsp), %rax
movq %rax, 344(%rsp)
leaq 184(%rsp), %rax
movq %rax, 352(%rsp)
leaq 100(%rsp), %rax
movq %rax, 360(%rsp)
leaq 168(%rsp), %rdi
leaq 152(%rsp), %rsi
leaq 144(%rsp), %rdx
leaq 136(%rsp), %rcx
callq __hipPopCallConfiguration
movq 168(%rsp), %rsi
movl 176(%rsp), %edx
movq 152(%rsp), %rcx
movl 160(%rsp), %r8d
leaq 272(%rsp), %r9
movl $_Z3sw4PfS_S_S_S_S_S_S_S_S_S_i, %edi
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_25:
movq 24(%rsp), %rsi
movq %rbp, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rsi
movq 112(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rsi
movq 104(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 88(%rsp), %rdi
callq hipFree
movq 80(%rsp), %rdi
callq hipFree
movq 72(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
addq $376, %rsp # imm = 0x178
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_1:
.cfi_def_cfa_offset 432
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
jmp .LBB2_2
.LBB2_4:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.2, %esi
jmp .LBB2_2
.LBB2_6:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.3, %esi
jmp .LBB2_2
.LBB2_8:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.4, %esi
jmp .LBB2_2
.LBB2_10:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.5, %esi
jmp .LBB2_2
.LBB2_12:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.6, %esi
jmp .LBB2_2
.LBB2_14:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.7, %esi
jmp .LBB2_2
.LBB2_16:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.8, %esi
jmp .LBB2_2
.LBB2_18:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.9, %esi
jmp .LBB2_2
.LBB2_20:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.10, %esi
jmp .LBB2_2
.LBB2_22:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.11, %esi
.LBB2_2:
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end2:
.size host_code, .Lfunc_end2-host_code
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3sw4PfS_S_S_S_S_S_S_S_S_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA error : %s, %s\n"
.size .L.str, 21
.type _Z3sw4PfS_S_S_S_S_S_S_S_S_S_i,@object # @_Z3sw4PfS_S_S_S_S_S_S_S_S_S_i
.section .rodata,"a",@progbits
.globl _Z3sw4PfS_S_S_S_S_S_S_S_S_S_i
.p2align 3, 0x0
_Z3sw4PfS_S_S_S_S_S_S_S_S_S_i:
.quad _Z18__device_stub__sw4PfS_S_S_S_S_S_S_S_S_S_i
.size _Z3sw4PfS_S_S_S_S_S_S_S_S_S_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Failed to allocate device memory for uacc_0\n"
.size .L.str.1, 45
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Failed to allocate device memory for uacc_1\n"
.size .L.str.2, 45
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Failed to allocate device memory for uacc_2\n"
.size .L.str.3, 45
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Failed to allocate device memory for u_0\n"
.size .L.str.4, 42
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Failed to allocate device memory for u_1\n"
.size .L.str.5, 42
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Failed to allocate device memory for u_2\n"
.size .L.str.6, 42
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Failed to allocate device memory for mu\n"
.size .L.str.7, 41
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Failed to allocate device memory for la\n"
.size .L.str.8, 41
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Failed to allocate device memory for strx\n"
.size .L.str.9, 43
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Failed to allocate device memory for stry\n"
.size .L.str.10, 43
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Failed to allocate device memory for strz\n"
.size .L.str.11, 43
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3sw4PfS_S_S_S_S_S_S_S_S_S_i"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__sw4PfS_S_S_S_S_S_S_S_S_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3sw4PfS_S_S_S_S_S_S_S_S_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <stdio.h>
#include <time.h>
#include <iomanip>
using namespace std;
#define PI 3.1415926535897932384
#define mu0 4*PI*1e-7
__global__ void init(double *rod_old, double *rod_new, double imax, double ldr, double rlength, int total_seg){
int i = threadIdx.x;
rod_new[i] = (1-(i*i*ldr*ldr/(3*rlength*rlength)))*3*mu0*imax*i*ldr/(4*PI*rlength*rlength);
if(i==0 || i==total_seg-1){
rod_old[i] = rod_new[i];
}
}
__global__ void run(double *rod_old, double *rod_new, double aug, long int maxSteps, int rod_size){
int i = threadIdx.x + 1;
long int steps = 0;
extern __shared__ double rod_new_s[];
extern __shared__ double rod_old_s[];
rod_new_s[i] = rod_new[i];
__syncthreads();
while(steps<maxSteps){
rod_old_s[i] = rod_new_s[i];
__syncthreads();
if(i==1)
rod_new_s[1]+= aug*(2*rod_old_s[2] - 4*rod_old_s[1]);
else if(i<(rod_size - 1))
rod_new_s[i] += aug*((1+(1/(2*i)))*rod_old_s[i+1] + (-2-(1/(i*i)))*rod_old_s[i] + (1-(1/(2*i)))*rod_old_s[i-1]);
steps++;
__syncthreads();
}
rod_new[i] = rod_new_s[i];
}
int main(){
FILE *myfile;
myfile = fopen("results.txt", "w");
double imax, rlength, eta, tstep, ldr, tottime;
int numseg;
printf("What is your I max? ");
scanf("%lf", &imax);
printf("What is the length of your rod? ");
scanf("%lf", &rlength);
printf("What is eta? ");
scanf("%lf", &eta);
printf("How many segments would you like? ");
scanf("%d", &numseg);
ldr = rlength/(numseg+1);
tstep = 0.25*ldr*ldr*mu0/eta;
printf("How long would you like to run? ");
scanf("%lf", &tottime);
double *h_rod, *d_rod_new, *d_rod_old;
size_t rod_size = (numseg + 2) * sizeof(double);
h_rod = (double*)malloc(rod_size);
cudaMalloc(&d_rod_new, rod_size);
cudaMalloc(&d_rod_old, rod_size);
init<<<1,numseg+2>>>(d_rod_old, d_rod_new, imax, ldr, rlength, numseg + 2);
int out;
//output r values
for(out = 0; out<numseg+1; out++){
fprintf( myfile, "%lf ", out*ldr );
}
fprintf( myfile, "%lf\n", out*ldr );
cudaMemcpy(h_rod, d_rod_new, rod_size, cudaMemcpyDeviceToHost);
for(out = 0; out<numseg+1; out++){
fprintf( myfile, "%lf ", *(h_rod+out) );
}
fprintf( myfile, "%lf\n", *(h_rod+out) );
double aug = eta*tstep/(mu0*ldr*ldr);
long int total_steps = tottime / tstep;
printf("\nSteps: %ld\n", total_steps);
clock_t begin, end;
double time_spent;
begin = clock();
//run
run<<<1,numseg + 2, (numseg+2)*sizeof(double)>>>(d_rod_old, d_rod_new, aug, total_steps, numseg+2);
cudaDeviceSynchronize();
end = clock();
time_spent = (double)(end - begin) / CLOCKS_PER_SEC;
cudaMemcpy(h_rod, d_rod_new, rod_size, cudaMemcpyDeviceToHost);
for(out = 0; out<numseg+1; out++){
fprintf( myfile, "%lf ", *(h_rod+out) );
}
fprintf( myfile, "%lf\n", *(h_rod+out) );
fprintf(myfile, "STOP\n");
fclose(myfile);
cout << "\n------------------------------------\nExecution took: "<< time_spent << " sec\n";
return 0;
} | .file "tmpxft_00022a97_00000000-6_run.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3952:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3952:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z4initPdS_dddiPdS_dddi
.type _Z29__device_stub__Z4initPdS_dddiPdS_dddi, @function
_Z29__device_stub__Z4initPdS_dddiPdS_dddi:
.LFB3974:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movsd %xmm0, 24(%rsp)
movsd %xmm1, 16(%rsp)
movsd %xmm2, 8(%rsp)
movl %edx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z4initPdS_dddi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3974:
.size _Z29__device_stub__Z4initPdS_dddiPdS_dddi, .-_Z29__device_stub__Z4initPdS_dddiPdS_dddi
.globl _Z4initPdS_dddi
.type _Z4initPdS_dddi, @function
_Z4initPdS_dddi:
.LFB3975:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z4initPdS_dddiPdS_dddi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3975:
.size _Z4initPdS_dddi, .-_Z4initPdS_dddi
.globl _Z27__device_stub__Z3runPdS_dliPdS_dli
.type _Z27__device_stub__Z3runPdS_dliPdS_dli, @function
_Z27__device_stub__Z3runPdS_dliPdS_dli:
.LFB3976:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movsd %xmm0, 24(%rsp)
movq %rdx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z3runPdS_dli(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3976:
.size _Z27__device_stub__Z3runPdS_dliPdS_dli, .-_Z27__device_stub__Z3runPdS_dliPdS_dli
.globl _Z3runPdS_dli
.type _Z3runPdS_dli, @function
_Z3runPdS_dli:
.LFB3977:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z3runPdS_dliPdS_dli
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3977:
.size _Z3runPdS_dli, .-_Z3runPdS_dli
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "w"
.LC1:
.string "results.txt"
.LC2:
.string "What is your I max? "
.LC3:
.string "%lf"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "What is the length of your rod? "
.section .rodata.str1.1
.LC5:
.string "What is eta? "
.section .rodata.str1.8
.align 8
.LC6:
.string "How many segments would you like? "
.section .rodata.str1.1
.LC7:
.string "%d"
.section .rodata.str1.8
.align 8
.LC12:
.string "How long would you like to run? "
.section .rodata.str1.1
.LC13:
.string "%lf "
.LC14:
.string "%lf\n"
.LC15:
.string "\nSteps: %ld\n"
.LC18:
.string "STOP\n"
.section .rodata.str1.8
.align 8
.LC19:
.string "\n------------------------------------\nExecution took: "
.section .rodata.str1.1
.LC20:
.string " sec\n"
.text
.globl main
.type main, @function
main:
.LFB3949:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 32(%rsp), %rsi
leaq .LC3(%rip), %rbx
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 40(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 48(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 28(%rsp), %rsi
leaq .LC7(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 28(%rsp), %eax
addl $1, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd 40(%rsp), %xmm1
divsd %xmm0, %xmm1
movsd %xmm1, (%rsp)
movapd %xmm1, %xmm0
mulsd .LC8(%rip), %xmm0
mulsd %xmm1, %xmm0
mulsd .LC9(%rip), %xmm0
mulsd .LC10(%rip), %xmm0
mulsd .LC11(%rip), %xmm0
divsd 48(%rsp), %xmm0
movsd %xmm0, 8(%rsp)
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 56(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 28(%rsp), %eax
leal 2(%rax), %r12d
movslq %r12d, %r12
salq $3, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %r14
leaq 64(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl 28(%rsp), %eax
addl $2, %eax
movl %eax, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L20:
cmpl $0, 28(%rsp)
js .L29
movl $0, %ebx
leaq .LC13(%rip), %r13
.L22:
pxor %xmm0, %xmm0
cvtsi2sdl %ebx, %xmm0
mulsd (%rsp), %xmm0
movq %r13, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addl $1, %ebx
cmpl %ebx, 28(%rsp)
jge .L22
.L21:
pxor %xmm0, %xmm0
cvtsi2sdl %ebx, %xmm0
mulsd (%rsp), %xmm0
leaq .LC14(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
movl $2, %ecx
movq %r12, %rdx
movq 64(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
cmpl $0, 28(%rsp)
js .L30
movq %r14, %r13
movl $0, %ebx
leaq .LC13(%rip), %r15
.L24:
movsd 0(%r13), %xmm0
movq %r15, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addl $1, %ebx
addq $8, %r13
cmpl %ebx, 28(%rsp)
jge .L24
.L23:
movslq %ebx, %rbx
movsd (%r14,%rbx,8), %xmm0
leaq .LC14(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
movq 48(%rsp), %r13
movsd 56(%rsp), %xmm0
divsd 8(%rsp), %xmm0
cvttsd2siq %xmm0, %r15
movq %r15, %rdx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call clock@PLT
movq %rax, %rbx
movl 28(%rsp), %eax
addl $2, %eax
movl %eax, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
cltq
movl $0, %r9d
leaq 0(,%rax,8), %r8
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L25:
call cudaDeviceSynchronize@PLT
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC17(%rip), %xmm0
movq %xmm0, %r13
movl $2, %ecx
movq %r12, %rdx
movq 64(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
cmpl $0, 28(%rsp)
js .L31
movq %r14, %r12
movl $0, %ebx
leaq .LC13(%rip), %r15
.L27:
movsd (%r12), %xmm0
movq %r15, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addl $1, %ebx
addq $8, %r12
cmpl %ebx, 28(%rsp)
jge .L27
.L26:
movslq %ebx, %rbx
movsd (%r14,%rbx,8), %xmm0
leaq .LC14(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
leaq .LC18(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %rbp, %rdi
call fclose@PLT
leaq .LC19(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r13, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC20(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L38
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
movl 28(%rsp), %eax
leal 2(%rax), %edx
movsd 40(%rsp), %xmm2
movsd (%rsp), %xmm1
movsd 32(%rsp), %xmm0
movq 64(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z29__device_stub__Z4initPdS_dddiPdS_dddi
jmp .L20
.L29:
movl $0, %ebx
jmp .L21
.L30:
movl $0, %ebx
jmp .L23
.L37:
movl 28(%rsp), %eax
leal 2(%rax), %ecx
movq %r13, %xmm0
mulsd 8(%rsp), %xmm0
movsd (%rsp), %xmm7
movapd %xmm7, %xmm1
mulsd .LC16(%rip), %xmm1
mulsd %xmm7, %xmm1
divsd %xmm1, %xmm0
movq %r15, %rdx
movq 64(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z27__device_stub__Z3runPdS_dliPdS_dli
jmp .L25
.L31:
movl $0, %ebx
jmp .L26
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3949:
.size main, .-main
.section .rodata.str1.1
.LC21:
.string "_Z3runPdS_dli"
.LC22:
.string "_Z4initPdS_dddi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3979:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _Z3runPdS_dli(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC22(%rip), %rdx
movq %rdx, %rcx
leaq _Z4initPdS_dddi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3979:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC8:
.long 0
.long 1070596096
.align 8
.LC9:
.long 0
.long 1074790400
.align 8
.LC10:
.long 1413754136
.long 1074340347
.align 8
.LC11:
.long -1698910392
.long 1048238066
.align 8
.LC16:
.long 261748427
.long 1052054839
.align 8
.LC17:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <stdio.h>
#include <time.h>
#include <iomanip>
using namespace std;
#define PI 3.1415926535897932384
#define mu0 4*PI*1e-7
__global__ void init(double *rod_old, double *rod_new, double imax, double ldr, double rlength, int total_seg){
int i = threadIdx.x;
rod_new[i] = (1-(i*i*ldr*ldr/(3*rlength*rlength)))*3*mu0*imax*i*ldr/(4*PI*rlength*rlength);
if(i==0 || i==total_seg-1){
rod_old[i] = rod_new[i];
}
}
__global__ void run(double *rod_old, double *rod_new, double aug, long int maxSteps, int rod_size){
int i = threadIdx.x + 1;
long int steps = 0;
extern __shared__ double rod_new_s[];
extern __shared__ double rod_old_s[];
rod_new_s[i] = rod_new[i];
__syncthreads();
while(steps<maxSteps){
rod_old_s[i] = rod_new_s[i];
__syncthreads();
if(i==1)
rod_new_s[1]+= aug*(2*rod_old_s[2] - 4*rod_old_s[1]);
else if(i<(rod_size - 1))
rod_new_s[i] += aug*((1+(1/(2*i)))*rod_old_s[i+1] + (-2-(1/(i*i)))*rod_old_s[i] + (1-(1/(2*i)))*rod_old_s[i-1]);
steps++;
__syncthreads();
}
rod_new[i] = rod_new_s[i];
}
int main(){
FILE *myfile;
myfile = fopen("results.txt", "w");
double imax, rlength, eta, tstep, ldr, tottime;
int numseg;
printf("What is your I max? ");
scanf("%lf", &imax);
printf("What is the length of your rod? ");
scanf("%lf", &rlength);
printf("What is eta? ");
scanf("%lf", &eta);
printf("How many segments would you like? ");
scanf("%d", &numseg);
ldr = rlength/(numseg+1);
tstep = 0.25*ldr*ldr*mu0/eta;
printf("How long would you like to run? ");
scanf("%lf", &tottime);
double *h_rod, *d_rod_new, *d_rod_old;
size_t rod_size = (numseg + 2) * sizeof(double);
h_rod = (double*)malloc(rod_size);
cudaMalloc(&d_rod_new, rod_size);
cudaMalloc(&d_rod_old, rod_size);
init<<<1,numseg+2>>>(d_rod_old, d_rod_new, imax, ldr, rlength, numseg + 2);
int out;
//output r values
for(out = 0; out<numseg+1; out++){
fprintf( myfile, "%lf ", out*ldr );
}
fprintf( myfile, "%lf\n", out*ldr );
cudaMemcpy(h_rod, d_rod_new, rod_size, cudaMemcpyDeviceToHost);
for(out = 0; out<numseg+1; out++){
fprintf( myfile, "%lf ", *(h_rod+out) );
}
fprintf( myfile, "%lf\n", *(h_rod+out) );
double aug = eta*tstep/(mu0*ldr*ldr);
long int total_steps = tottime / tstep;
printf("\nSteps: %ld\n", total_steps);
clock_t begin, end;
double time_spent;
begin = clock();
//run
run<<<1,numseg + 2, (numseg+2)*sizeof(double)>>>(d_rod_old, d_rod_new, aug, total_steps, numseg+2);
cudaDeviceSynchronize();
end = clock();
time_spent = (double)(end - begin) / CLOCKS_PER_SEC;
cudaMemcpy(h_rod, d_rod_new, rod_size, cudaMemcpyDeviceToHost);
for(out = 0; out<numseg+1; out++){
fprintf( myfile, "%lf ", *(h_rod+out) );
}
fprintf( myfile, "%lf\n", *(h_rod+out) );
fprintf(myfile, "STOP\n");
fclose(myfile);
cout << "\n------------------------------------\nExecution took: "<< time_spent << " sec\n";
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <time.h>
#include <iomanip>
using namespace std;
#define PI 3.1415926535897932384
#define mu0 4*PI*1e-7
__global__ void init(double *rod_old, double *rod_new, double imax, double ldr, double rlength, int total_seg){
int i = threadIdx.x;
rod_new[i] = (1-(i*i*ldr*ldr/(3*rlength*rlength)))*3*mu0*imax*i*ldr/(4*PI*rlength*rlength);
if(i==0 || i==total_seg-1){
rod_old[i] = rod_new[i];
}
}
__global__ void run(double *rod_old, double *rod_new, double aug, long int maxSteps, int rod_size){
int i = threadIdx.x + 1;
long int steps = 0;
extern __shared__ double rod_new_s[];
extern __shared__ double rod_old_s[];
rod_new_s[i] = rod_new[i];
__syncthreads();
while(steps<maxSteps){
rod_old_s[i] = rod_new_s[i];
__syncthreads();
if(i==1)
rod_new_s[1]+= aug*(2*rod_old_s[2] - 4*rod_old_s[1]);
else if(i<(rod_size - 1))
rod_new_s[i] += aug*((1+(1/(2*i)))*rod_old_s[i+1] + (-2-(1/(i*i)))*rod_old_s[i] + (1-(1/(2*i)))*rod_old_s[i-1]);
steps++;
__syncthreads();
}
rod_new[i] = rod_new_s[i];
}
int main(){
FILE *myfile;
myfile = fopen("results.txt", "w");
double imax, rlength, eta, tstep, ldr, tottime;
int numseg;
printf("What is your I max? ");
scanf("%lf", &imax);
printf("What is the length of your rod? ");
scanf("%lf", &rlength);
printf("What is eta? ");
scanf("%lf", &eta);
printf("How many segments would you like? ");
scanf("%d", &numseg);
ldr = rlength/(numseg+1);
tstep = 0.25*ldr*ldr*mu0/eta;
printf("How long would you like to run? ");
scanf("%lf", &tottime);
double *h_rod, *d_rod_new, *d_rod_old;
size_t rod_size = (numseg + 2) * sizeof(double);
h_rod = (double*)malloc(rod_size);
hipMalloc(&d_rod_new, rod_size);
hipMalloc(&d_rod_old, rod_size);
init<<<1,numseg+2>>>(d_rod_old, d_rod_new, imax, ldr, rlength, numseg + 2);
int out;
//output r values
for(out = 0; out<numseg+1; out++){
fprintf( myfile, "%lf ", out*ldr );
}
fprintf( myfile, "%lf\n", out*ldr );
hipMemcpy(h_rod, d_rod_new, rod_size, hipMemcpyDeviceToHost);
for(out = 0; out<numseg+1; out++){
fprintf( myfile, "%lf ", *(h_rod+out) );
}
fprintf( myfile, "%lf\n", *(h_rod+out) );
double aug = eta*tstep/(mu0*ldr*ldr);
long int total_steps = tottime / tstep;
printf("\nSteps: %ld\n", total_steps);
clock_t begin, end;
double time_spent;
begin = clock();
//run
run<<<1,numseg + 2, (numseg+2)*sizeof(double)>>>(d_rod_old, d_rod_new, aug, total_steps, numseg+2);
hipDeviceSynchronize();
end = clock();
time_spent = (double)(end - begin) / CLOCKS_PER_SEC;
hipMemcpy(h_rod, d_rod_new, rod_size, hipMemcpyDeviceToHost);
for(out = 0; out<numseg+1; out++){
fprintf( myfile, "%lf ", *(h_rod+out) );
}
fprintf( myfile, "%lf\n", *(h_rod+out) );
fprintf(myfile, "STOP\n");
fclose(myfile);
cout << "\n------------------------------------\nExecution took: "<< time_spent << " sec\n";
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <time.h>
#include <iomanip>
using namespace std;
#define PI 3.1415926535897932384
#define mu0 4*PI*1e-7
__global__ void init(double *rod_old, double *rod_new, double imax, double ldr, double rlength, int total_seg){
int i = threadIdx.x;
rod_new[i] = (1-(i*i*ldr*ldr/(3*rlength*rlength)))*3*mu0*imax*i*ldr/(4*PI*rlength*rlength);
if(i==0 || i==total_seg-1){
rod_old[i] = rod_new[i];
}
}
__global__ void run(double *rod_old, double *rod_new, double aug, long int maxSteps, int rod_size){
int i = threadIdx.x + 1;
long int steps = 0;
extern __shared__ double rod_new_s[];
extern __shared__ double rod_old_s[];
rod_new_s[i] = rod_new[i];
__syncthreads();
while(steps<maxSteps){
rod_old_s[i] = rod_new_s[i];
__syncthreads();
if(i==1)
rod_new_s[1]+= aug*(2*rod_old_s[2] - 4*rod_old_s[1]);
else if(i<(rod_size - 1))
rod_new_s[i] += aug*((1+(1/(2*i)))*rod_old_s[i+1] + (-2-(1/(i*i)))*rod_old_s[i] + (1-(1/(2*i)))*rod_old_s[i-1]);
steps++;
__syncthreads();
}
rod_new[i] = rod_new_s[i];
}
int main(){
FILE *myfile;
myfile = fopen("results.txt", "w");
double imax, rlength, eta, tstep, ldr, tottime;
int numseg;
printf("What is your I max? ");
scanf("%lf", &imax);
printf("What is the length of your rod? ");
scanf("%lf", &rlength);
printf("What is eta? ");
scanf("%lf", &eta);
printf("How many segments would you like? ");
scanf("%d", &numseg);
ldr = rlength/(numseg+1);
tstep = 0.25*ldr*ldr*mu0/eta;
printf("How long would you like to run? ");
scanf("%lf", &tottime);
double *h_rod, *d_rod_new, *d_rod_old;
size_t rod_size = (numseg + 2) * sizeof(double);
h_rod = (double*)malloc(rod_size);
hipMalloc(&d_rod_new, rod_size);
hipMalloc(&d_rod_old, rod_size);
init<<<1,numseg+2>>>(d_rod_old, d_rod_new, imax, ldr, rlength, numseg + 2);
int out;
//output r values
for(out = 0; out<numseg+1; out++){
fprintf( myfile, "%lf ", out*ldr );
}
fprintf( myfile, "%lf\n", out*ldr );
hipMemcpy(h_rod, d_rod_new, rod_size, hipMemcpyDeviceToHost);
for(out = 0; out<numseg+1; out++){
fprintf( myfile, "%lf ", *(h_rod+out) );
}
fprintf( myfile, "%lf\n", *(h_rod+out) );
double aug = eta*tstep/(mu0*ldr*ldr);
long int total_steps = tottime / tstep;
printf("\nSteps: %ld\n", total_steps);
clock_t begin, end;
double time_spent;
begin = clock();
//run
run<<<1,numseg + 2, (numseg+2)*sizeof(double)>>>(d_rod_old, d_rod_new, aug, total_steps, numseg+2);
hipDeviceSynchronize();
end = clock();
time_spent = (double)(end - begin) / CLOCKS_PER_SEC;
hipMemcpy(h_rod, d_rod_new, rod_size, hipMemcpyDeviceToHost);
for(out = 0; out<numseg+1; out++){
fprintf( myfile, "%lf ", *(h_rod+out) );
}
fprintf( myfile, "%lf\n", *(h_rod+out) );
fprintf(myfile, "STOP\n");
fclose(myfile);
cout << "\n------------------------------------\nExecution took: "<< time_spent << " sec\n";
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4initPdS_dddi
.globl _Z4initPdS_dddi
.p2align 8
.type _Z4initPdS_dddi,@function
_Z4initPdS_dddi:
v_mul_u32_u24_e32 v1, v0, v0
s_load_b256 s[4:11], s[0:1], 0x8
s_mov_b32 s3, 0x400921fb
s_mov_b32 s2, 0x54442d18
s_mov_b32 s13, 0x3e7ad7f2
v_cvt_f64_i32_e32 v[1:2], v1
s_mov_b32 s12, 0x9abcaf48
s_waitcnt lgkmcnt(0)
v_mul_f64 v[3:4], s[10:11], 0x40080000
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[1:2], v[1:2], s[8:9]
v_mul_f64 v[3:4], v[3:4], s[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[1:2], v[1:2], s[8:9]
v_div_scale_f64 v[5:6], null, v[3:4], v[3:4], v[1:2]
v_div_scale_f64 v[11:12], vcc_lo, v[1:2], v[3:4], v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[7:8], v[5:6]
s_waitcnt_depctr 0xfff
v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[9:10], v[11:12], v[7:8]
v_fma_f64 v[5:6], -v[5:6], v[9:10], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[5:6], v[5:6], v[7:8], v[9:10]
v_div_fixup_f64 v[1:2], v[5:6], v[3:4], v[1:2]
v_cvt_f64_i32_e32 v[3:4], v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[1:2], -v[1:2], 1.0
v_mul_f64 v[1:2], v[1:2], 0x40080000
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[1:2], v[1:2], 4.0
v_mul_f64 v[1:2], v[1:2], s[2:3]
s_mov_b32 s3, 0x402921fb
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_mul_f64 v[5:6], s[10:11], s[2:3]
s_load_b32 s2, s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s2, -1
v_cmp_eq_u32_e64 s2, s2, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[1:2], v[1:2], s[12:13]
v_mul_f64 v[1:2], v[1:2], s[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f64 v[1:2], v[1:2], v[3:4]
v_mul_f64 v[3:4], v[5:6], s[10:11]
v_mul_f64 v[1:2], v[1:2], s[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[5:6], null, v[3:4], v[3:4], v[1:2]
v_rcp_f64_e32 v[7:8], v[5:6]
s_waitcnt_depctr 0xfff
v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
v_div_scale_f64 v[9:10], vcc_lo, v[1:2], v[3:4], v[1:2]
v_mul_f64 v[11:12], v[9:10], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[5:6], -v[5:6], v[11:12], v[9:10]
v_div_fmas_f64 v[5:6], v[5:6], v[7:8], v[11:12]
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_2)
v_div_fixup_f64 v[1:2], v[5:6], v[3:4], v[1:2]
v_lshlrev_b32_e32 v3, 3, v0
global_store_b64 v3, v[1:2], s[4:5]
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 3, v0
s_waitcnt lgkmcnt(0)
global_store_b64 v0, v[1:2], s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4initPdS_dddi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 44
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 14
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4initPdS_dddi, .Lfunc_end0-_Z4initPdS_dddi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3runPdS_dli
.globl _Z3runPdS_dli
.p2align 8
.type _Z3runPdS_dli,@function
_Z3runPdS_dli:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x18
v_add_nc_u32_e32 v9, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v1, 3, v9
v_add_nc_u32_e32 v11, 0, v1
s_waitcnt lgkmcnt(0)
global_load_b64 v[3:4], v1, s[4:5]
v_cmp_lt_i64_e64 s6, s[2:3], 1
v_add_co_u32 v1, s4, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v2, null, s5, 0, s4
s_and_b32 vcc_lo, exec_lo, s6
s_waitcnt vmcnt(0)
ds_store_b64 v11, v[3:4]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB1_11
v_mul_u32_u24_e32 v4, v9, v9
s_clause 0x1
s_load_b32 s6, s[0:1], 0x20
s_load_b64 s[4:5], s[0:1], 0x10
v_lshl_add_u32 v12, v0, 3, 0
v_lshl_add_u32 v13, v9, 3, 0
s_add_i32 s1, 0, 8
v_add_nc_u32_e32 v6, 1, v4
v_sub_nc_u32_e32 v4, -2, v4
v_lshlrev_b32_e32 v3, 1, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v5, 1, v3
v_cmp_gt_u32_e32 vcc_lo, 3, v5
s_waitcnt lgkmcnt(0)
s_add_i32 s6, s6, -1
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
v_cmp_gt_u32_e32 vcc_lo, 3, v6
v_cmp_gt_i32_e64 s0, s6, v9
s_delay_alu instid0(VALU_DEP_3)
v_or_b32_e32 v5, 1, v3
v_cndmask_b32_e32 v4, -2, v4, vcc_lo
v_sub_nc_u32_e32 v7, 1, v3
v_cmp_ne_u32_e32 vcc_lo, 0, v0
v_add_nc_u32_e32 v0, 16, v12
v_cvt_f64_i32_e32 v[5:6], v5
v_cvt_f64_i32_e32 v[3:4], v4
v_cvt_f64_i32_e32 v[7:8], v7
s_branch .LBB1_3
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s7
s_add_u32 s2, s2, -1
s_addc_u32 s3, s3, -1
s_waitcnt lgkmcnt(0)
s_cmp_lg_u64 s[2:3], 0
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB1_11
.LBB1_3:
ds_load_b64 v[9:10], v11
s_mov_b32 s6, 0
s_waitcnt lgkmcnt(0)
ds_store_b64 v13, v[9:10]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s7, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s7, exec_lo, s7
s_cbranch_execz .LBB1_7
s_and_saveexec_b32 s8, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s8, exec_lo, s8
s_cbranch_execz .LBB1_6
ds_load_b64 v[9:10], v12
ds_load_b64 v[14:15], v13
ds_load_b64 v[16:17], v0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(1)
v_mul_f64 v[14:15], v[14:15], v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], v[16:17], v[5:6], v[14:15]
v_fma_f64 v[9:10], v[9:10], v[7:8], v[14:15]
.LBB1_6:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v14, v11
s_and_b32 s6, s6, exec_lo
.LBB1_7:
s_and_not1_saveexec_b32 s7, s7
s_cbranch_execz .LBB1_9
v_mov_b32_e32 v9, 0
s_or_b32 s6, s6, exec_lo
ds_load_2addr_b64 v[14:17], v9 offset0:1 offset1:2
s_waitcnt lgkmcnt(0)
v_mul_f64 v[9:10], v[14:15], -4.0
v_mov_b32_e32 v14, s1
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[9:10], v[16:17], 2.0, v[9:10]
.LBB1_9:
s_or_b32 exec_lo, exec_lo, s7
s_and_saveexec_b32 s7, s6
s_cbranch_execz .LBB1_2
ds_load_b64 v[15:16], v14
s_waitcnt lgkmcnt(0)
v_fma_f64 v[9:10], v[9:10], s[4:5], v[15:16]
ds_store_b64 v14, v[9:10]
s_branch .LBB1_2
.LBB1_11:
ds_load_b64 v[3:4], v11
s_waitcnt lgkmcnt(0)
global_store_b64 v[1:2], v[3:4], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3runPdS_dli
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 9
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z3runPdS_dli, .Lfunc_end1-_Z3runPdS_dli
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 44
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4initPdS_dddi
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z4initPdS_dddi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3runPdS_dli
.private_segment_fixed_size: 0
.sgpr_count: 11
.sgpr_spill_count: 0
.symbol: _Z3runPdS_dli.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <time.h>
#include <iomanip>
using namespace std;
#define PI 3.1415926535897932384
#define mu0 4*PI*1e-7
__global__ void init(double *rod_old, double *rod_new, double imax, double ldr, double rlength, int total_seg){
int i = threadIdx.x;
rod_new[i] = (1-(i*i*ldr*ldr/(3*rlength*rlength)))*3*mu0*imax*i*ldr/(4*PI*rlength*rlength);
if(i==0 || i==total_seg-1){
rod_old[i] = rod_new[i];
}
}
__global__ void run(double *rod_old, double *rod_new, double aug, long int maxSteps, int rod_size){
int i = threadIdx.x + 1;
long int steps = 0;
extern __shared__ double rod_new_s[];
extern __shared__ double rod_old_s[];
rod_new_s[i] = rod_new[i];
__syncthreads();
while(steps<maxSteps){
rod_old_s[i] = rod_new_s[i];
__syncthreads();
if(i==1)
rod_new_s[1]+= aug*(2*rod_old_s[2] - 4*rod_old_s[1]);
else if(i<(rod_size - 1))
rod_new_s[i] += aug*((1+(1/(2*i)))*rod_old_s[i+1] + (-2-(1/(i*i)))*rod_old_s[i] + (1-(1/(2*i)))*rod_old_s[i-1]);
steps++;
__syncthreads();
}
rod_new[i] = rod_new_s[i];
}
int main(){
FILE *myfile;
myfile = fopen("results.txt", "w");
double imax, rlength, eta, tstep, ldr, tottime;
int numseg;
printf("What is your I max? ");
scanf("%lf", &imax);
printf("What is the length of your rod? ");
scanf("%lf", &rlength);
printf("What is eta? ");
scanf("%lf", &eta);
printf("How many segments would you like? ");
scanf("%d", &numseg);
ldr = rlength/(numseg+1);
tstep = 0.25*ldr*ldr*mu0/eta;
printf("How long would you like to run? ");
scanf("%lf", &tottime);
double *h_rod, *d_rod_new, *d_rod_old;
size_t rod_size = (numseg + 2) * sizeof(double);
h_rod = (double*)malloc(rod_size);
hipMalloc(&d_rod_new, rod_size);
hipMalloc(&d_rod_old, rod_size);
init<<<1,numseg+2>>>(d_rod_old, d_rod_new, imax, ldr, rlength, numseg + 2);
int out;
//output r values
for(out = 0; out<numseg+1; out++){
fprintf( myfile, "%lf ", out*ldr );
}
fprintf( myfile, "%lf\n", out*ldr );
hipMemcpy(h_rod, d_rod_new, rod_size, hipMemcpyDeviceToHost);
for(out = 0; out<numseg+1; out++){
fprintf( myfile, "%lf ", *(h_rod+out) );
}
fprintf( myfile, "%lf\n", *(h_rod+out) );
double aug = eta*tstep/(mu0*ldr*ldr);
long int total_steps = tottime / tstep;
printf("\nSteps: %ld\n", total_steps);
clock_t begin, end;
double time_spent;
begin = clock();
//run
run<<<1,numseg + 2, (numseg+2)*sizeof(double)>>>(d_rod_old, d_rod_new, aug, total_steps, numseg+2);
hipDeviceSynchronize();
end = clock();
time_spent = (double)(end - begin) / CLOCKS_PER_SEC;
hipMemcpy(h_rod, d_rod_new, rod_size, hipMemcpyDeviceToHost);
for(out = 0; out<numseg+1; out++){
fprintf( myfile, "%lf ", *(h_rod+out) );
}
fprintf( myfile, "%lf\n", *(h_rod+out) );
fprintf(myfile, "STOP\n");
fclose(myfile);
cout << "\n------------------------------------\nExecution took: "<< time_spent << " sec\n";
return 0;
} | .text
.file "run.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z19__device_stub__initPdS_dddi # -- Begin function _Z19__device_stub__initPdS_dddi
.p2align 4, 0x90
.type _Z19__device_stub__initPdS_dddi,@function
_Z19__device_stub__initPdS_dddi: # @_Z19__device_stub__initPdS_dddi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movsd %xmm0, 72(%rsp)
movsd %xmm1, 64(%rsp)
movsd %xmm2, 56(%rsp)
movl %edx, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z4initPdS_dddi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z19__device_stub__initPdS_dddi, .Lfunc_end0-_Z19__device_stub__initPdS_dddi
.cfi_endproc
# -- End function
.globl _Z18__device_stub__runPdS_dli # -- Begin function _Z18__device_stub__runPdS_dli
.p2align 4, 0x90
.type _Z18__device_stub__runPdS_dli,@function
_Z18__device_stub__runPdS_dli: # @_Z18__device_stub__runPdS_dli
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movsd %xmm0, 72(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3runPdS_dli, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end1:
.size _Z18__device_stub__runPdS_dli, .Lfunc_end1-_Z18__device_stub__runPdS_dli
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x3fd0000000000000 # double 0.25
.LCPI2_1:
.quad 0x4010000000000000 # double 4
.LCPI2_2:
.quad 0x400921fb54442d18 # double 3.1415926535897931
.LCPI2_3:
.quad 0x3e7ad7f29abcaf48 # double 9.9999999999999995E-8
.LCPI2_4:
.quad 0x3eb515370f99f6cb # double 1.2566370614359173E-6
.LCPI2_5:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967296, %r15 # imm = 0x100000000
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %rbx
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
leaq 224(%rsp), %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
leaq 152(%rsp), %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
leaq 144(%rsp), %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
leaq 12(%rsp), %rsi
movl $.L.str.7, %edi
xorl %eax, %eax
callq __isoc23_scanf
movsd 152(%rsp), %xmm1 # xmm1 = mem[0],zero
movl 12(%rsp), %eax
incl %eax
cvtsi2sd %eax, %xmm0
divsd %xmm0, %xmm1
movsd .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero
mulsd %xmm1, %xmm0
movsd %xmm1, 16(%rsp) # 8-byte Spill
mulsd %xmm1, %xmm0
mulsd .LCPI2_1(%rip), %xmm0
mulsd .LCPI2_2(%rip), %xmm0
mulsd .LCPI2_3(%rip), %xmm0
divsd 144(%rsp), %xmm0
movsd %xmm0, 128(%rsp) # 8-byte Spill
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
leaq 216(%rsp), %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq __isoc23_scanf
movslq 12(%rsp), %rax
leaq 16(,%rax,8), %r12
movq %r12, %rdi
callq malloc
movq %rax, %r14
leaq 24(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 136(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movl 12(%rsp), %edx
addl $2, %edx
orq %r15, %rdx
leaq 1(%r15), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB2_1
# %bb.2:
cmpl $0, 12(%rsp)
js .LBB2_3
.LBB2_4: # %.lr.ph.preheader
movl $-1, %ebp
movsd 16(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB2_5: # %.lr.ph
# =>This Inner Loop Header: Depth=1
incl %ebp
xorps %xmm0, %xmm0
cvtsi2sd %ebp, %xmm0
mulsd %xmm1, %xmm0
movl $.L.str.9, %esi
movq %rbx, %rdi
movb $1, %al
callq fprintf
movsd 16(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
cmpl 12(%rsp), %ebp
jl .LBB2_5
# %bb.6: # %._crit_edge.loopexit
incl %ebp
xorps %xmm0, %xmm0
cvtsi2sd %ebp, %xmm0
jmp .LBB2_7
.LBB2_1:
movq 136(%rsp), %rax
movq 24(%rsp), %rcx
movsd 224(%rsp), %xmm0 # xmm0 = mem[0],zero
movsd 152(%rsp), %xmm1 # xmm1 = mem[0],zero
movl 12(%rsp), %edx
addl $2, %edx
movq %rax, 112(%rsp)
movq %rcx, 104(%rsp)
movsd %xmm0, 96(%rsp)
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 88(%rsp)
movsd %xmm1, 48(%rsp)
movl %edx, 124(%rsp)
leaq 112(%rsp), %rax
movq %rax, 160(%rsp)
leaq 104(%rsp), %rax
movq %rax, 168(%rsp)
leaq 96(%rsp), %rax
movq %rax, 176(%rsp)
leaq 88(%rsp), %rax
movq %rax, 184(%rsp)
leaq 48(%rsp), %rax
movq %rax, 192(%rsp)
leaq 124(%rsp), %rax
movq %rax, 200(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z4initPdS_dddi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
cmpl $0, 12(%rsp)
jns .LBB2_4
.LBB2_3:
xorpd %xmm0, %xmm0
movsd 16(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
.LBB2_7: # %._crit_edge
mulsd %xmm1, %xmm0
movl $.L.str.10, %esi
movq %rbx, %rdi
movb $1, %al
callq fprintf
movq 24(%rsp), %rsi
movq %r14, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
cmpl $0, 12(%rsp)
js .LBB2_8
# %bb.9: # %.lr.ph75.preheader
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_10: # %.lr.ph75
# =>This Inner Loop Header: Depth=1
movsd (%r14,%r13,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.9, %esi
movq %rbx, %rdi
movb $1, %al
callq fprintf
leaq 1(%r13), %rax
movslq 12(%rsp), %rcx
cmpq %rcx, %r13
movq %rax, %r13
jl .LBB2_10
jmp .LBB2_11
.LBB2_8:
xorl %eax, %eax
.LBB2_11: # %._crit_edge76
movsd (%r14,%rax,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.10, %esi
movq %rbx, %rdi
movb $1, %al
callq fprintf
movsd 144(%rsp), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 208(%rsp) # 8-byte Spill
movsd 216(%rsp), %xmm0 # xmm0 = mem[0],zero
divsd 128(%rsp), %xmm0 # 8-byte Folded Reload
cvttsd2si %xmm0, %rbp
movl $.L.str.11, %edi
movq %rbp, %rsi
xorl %eax, %eax
callq printf
callq clock
movq %rax, %r13
movslq 12(%rsp), %rax
leaq 16(,%rax,8), %r8
addq $2, %rax
movl %eax, %edx
orq %r15, %rdx
incq %r15
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_13
# %bb.12:
movsd 128(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
mulsd 208(%rsp), %xmm2 # 8-byte Folded Reload
movsd .LCPI2_4(%rip), %xmm0 # xmm0 = mem[0],zero
movsd 16(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
mulsd %xmm1, %xmm0
divsd %xmm0, %xmm2
movq 136(%rsp), %rax
movq 24(%rsp), %rcx
movl 12(%rsp), %edx
addl $2, %edx
movq %rax, 112(%rsp)
movq %rcx, 104(%rsp)
movsd %xmm2, 96(%rsp)
movq %rbp, 88(%rsp)
movl %edx, 32(%rsp)
leaq 112(%rsp), %rax
movq %rax, 160(%rsp)
leaq 104(%rsp), %rax
movq %rax, 168(%rsp)
leaq 96(%rsp), %rax
movq %rax, 176(%rsp)
leaq 88(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rax
movq %rax, 192(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z3runPdS_dli, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_13:
callq hipDeviceSynchronize
callq clock
movq %rax, %r15
movq 24(%rsp), %rsi
movq %r14, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
cmpl $0, 12(%rsp)
js .LBB2_14
# %bb.15: # %.lr.ph81.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_16: # %.lr.ph81
# =>This Inner Loop Header: Depth=1
movsd (%r14,%r12,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.9, %esi
movq %rbx, %rdi
movb $1, %al
callq fprintf
leaq 1(%r12), %rax
movslq 12(%rsp), %rcx
cmpq %rcx, %r12
movq %rax, %r12
jl .LBB2_16
jmp .LBB2_17
.LBB2_14:
xorl %eax, %eax
.LBB2_17: # %._crit_edge82
subq %r13, %r15
xorps %xmm0, %xmm0
cvtsi2sd %r15, %xmm0
divsd .LCPI2_5(%rip), %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
movsd (%r14,%rax,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.10, %esi
movq %rbx, %rdi
movb $1, %al
callq fprintf
movl $.L.str.12, %edi
movl $5, %esi
movl $1, %edx
movq %rbx, %rcx
callq fwrite@PLT
movq %rbx, %rdi
callq fclose
movl $_ZSt4cout, %edi
movl $.L.str.13, %esi
movl $54, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.14, %esi
movl $5, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %eax, %eax
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4initPdS_dddi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3runPdS_dli, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4initPdS_dddi,@object # @_Z4initPdS_dddi
.section .rodata,"a",@progbits
.globl _Z4initPdS_dddi
.p2align 3, 0x0
_Z4initPdS_dddi:
.quad _Z19__device_stub__initPdS_dddi
.size _Z4initPdS_dddi, 8
.type _Z3runPdS_dli,@object # @_Z3runPdS_dli
.globl _Z3runPdS_dli
.p2align 3, 0x0
_Z3runPdS_dli:
.quad _Z18__device_stub__runPdS_dli
.size _Z3runPdS_dli, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "results.txt"
.size .L.str, 12
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "w"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "What is your I max? "
.size .L.str.2, 21
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%lf"
.size .L.str.3, 4
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "What is the length of your rod? "
.size .L.str.4, 33
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "What is eta? "
.size .L.str.5, 14
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "How many segments would you like? "
.size .L.str.6, 35
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%d"
.size .L.str.7, 3
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "How long would you like to run? "
.size .L.str.8, 33
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%lf "
.size .L.str.9, 5
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "%lf\n"
.size .L.str.10, 5
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "\nSteps: %ld\n"
.size .L.str.11, 13
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "STOP\n"
.size .L.str.12, 6
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "\n------------------------------------\nExecution took: "
.size .L.str.13, 55
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz " sec\n"
.size .L.str.14, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4initPdS_dddi"
.size .L__unnamed_1, 16
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z3runPdS_dli"
.size .L__unnamed_2, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__initPdS_dddi
.addrsig_sym _Z18__device_stub__runPdS_dli
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4initPdS_dddi
.addrsig_sym _Z3runPdS_dli
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00022a97_00000000-6_run.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3952:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3952:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z4initPdS_dddiPdS_dddi
.type _Z29__device_stub__Z4initPdS_dddiPdS_dddi, @function
_Z29__device_stub__Z4initPdS_dddiPdS_dddi:
.LFB3974:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movsd %xmm0, 24(%rsp)
movsd %xmm1, 16(%rsp)
movsd %xmm2, 8(%rsp)
movl %edx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z4initPdS_dddi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3974:
.size _Z29__device_stub__Z4initPdS_dddiPdS_dddi, .-_Z29__device_stub__Z4initPdS_dddiPdS_dddi
.globl _Z4initPdS_dddi
.type _Z4initPdS_dddi, @function
_Z4initPdS_dddi:
.LFB3975:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z4initPdS_dddiPdS_dddi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3975:
.size _Z4initPdS_dddi, .-_Z4initPdS_dddi
.globl _Z27__device_stub__Z3runPdS_dliPdS_dli
.type _Z27__device_stub__Z3runPdS_dliPdS_dli, @function
_Z27__device_stub__Z3runPdS_dliPdS_dli:
.LFB3976:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movsd %xmm0, 24(%rsp)
movq %rdx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z3runPdS_dli(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3976:
.size _Z27__device_stub__Z3runPdS_dliPdS_dli, .-_Z27__device_stub__Z3runPdS_dliPdS_dli
.globl _Z3runPdS_dli
.type _Z3runPdS_dli, @function
_Z3runPdS_dli:
.LFB3977:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z3runPdS_dliPdS_dli
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3977:
.size _Z3runPdS_dli, .-_Z3runPdS_dli
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "w"
.LC1:
.string "results.txt"
.LC2:
.string "What is your I max? "
.LC3:
.string "%lf"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "What is the length of your rod? "
.section .rodata.str1.1
.LC5:
.string "What is eta? "
.section .rodata.str1.8
.align 8
.LC6:
.string "How many segments would you like? "
.section .rodata.str1.1
.LC7:
.string "%d"
.section .rodata.str1.8
.align 8
.LC12:
.string "How long would you like to run? "
.section .rodata.str1.1
.LC13:
.string "%lf "
.LC14:
.string "%lf\n"
.LC15:
.string "\nSteps: %ld\n"
.LC18:
.string "STOP\n"
.section .rodata.str1.8
.align 8
.LC19:
.string "\n------------------------------------\nExecution took: "
.section .rodata.str1.1
.LC20:
.string " sec\n"
.text
.globl main
.type main, @function
main:
.LFB3949:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 32(%rsp), %rsi
leaq .LC3(%rip), %rbx
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 40(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 48(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 28(%rsp), %rsi
leaq .LC7(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 28(%rsp), %eax
addl $1, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd 40(%rsp), %xmm1
divsd %xmm0, %xmm1
movsd %xmm1, (%rsp)
movapd %xmm1, %xmm0
mulsd .LC8(%rip), %xmm0
mulsd %xmm1, %xmm0
mulsd .LC9(%rip), %xmm0
mulsd .LC10(%rip), %xmm0
mulsd .LC11(%rip), %xmm0
divsd 48(%rsp), %xmm0
movsd %xmm0, 8(%rsp)
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 56(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 28(%rsp), %eax
leal 2(%rax), %r12d
movslq %r12d, %r12
salq $3, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %r14
leaq 64(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl 28(%rsp), %eax
addl $2, %eax
movl %eax, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L20:
cmpl $0, 28(%rsp)
js .L29
movl $0, %ebx
leaq .LC13(%rip), %r13
.L22:
pxor %xmm0, %xmm0
cvtsi2sdl %ebx, %xmm0
mulsd (%rsp), %xmm0
movq %r13, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addl $1, %ebx
cmpl %ebx, 28(%rsp)
jge .L22
.L21:
pxor %xmm0, %xmm0
cvtsi2sdl %ebx, %xmm0
mulsd (%rsp), %xmm0
leaq .LC14(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
movl $2, %ecx
movq %r12, %rdx
movq 64(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
cmpl $0, 28(%rsp)
js .L30
movq %r14, %r13
movl $0, %ebx
leaq .LC13(%rip), %r15
.L24:
movsd 0(%r13), %xmm0
movq %r15, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addl $1, %ebx
addq $8, %r13
cmpl %ebx, 28(%rsp)
jge .L24
.L23:
movslq %ebx, %rbx
movsd (%r14,%rbx,8), %xmm0
leaq .LC14(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
movq 48(%rsp), %r13
movsd 56(%rsp), %xmm0
divsd 8(%rsp), %xmm0
cvttsd2siq %xmm0, %r15
movq %r15, %rdx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call clock@PLT
movq %rax, %rbx
movl 28(%rsp), %eax
addl $2, %eax
movl %eax, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
cltq
movl $0, %r9d
leaq 0(,%rax,8), %r8
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L25:
call cudaDeviceSynchronize@PLT
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC17(%rip), %xmm0
movq %xmm0, %r13
movl $2, %ecx
movq %r12, %rdx
movq 64(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
cmpl $0, 28(%rsp)
js .L31
movq %r14, %r12
movl $0, %ebx
leaq .LC13(%rip), %r15
.L27:
movsd (%r12), %xmm0
movq %r15, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addl $1, %ebx
addq $8, %r12
cmpl %ebx, 28(%rsp)
jge .L27
.L26:
movslq %ebx, %rbx
movsd (%r14,%rbx,8), %xmm0
leaq .LC14(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
leaq .LC18(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %rbp, %rdi
call fclose@PLT
leaq .LC19(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r13, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC20(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L38
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
movl 28(%rsp), %eax
leal 2(%rax), %edx
movsd 40(%rsp), %xmm2
movsd (%rsp), %xmm1
movsd 32(%rsp), %xmm0
movq 64(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z29__device_stub__Z4initPdS_dddiPdS_dddi
jmp .L20
.L29:
movl $0, %ebx
jmp .L21
.L30:
movl $0, %ebx
jmp .L23
.L37:
movl 28(%rsp), %eax
leal 2(%rax), %ecx
movq %r13, %xmm0
mulsd 8(%rsp), %xmm0
movsd (%rsp), %xmm7
movapd %xmm7, %xmm1
mulsd .LC16(%rip), %xmm1
mulsd %xmm7, %xmm1
divsd %xmm1, %xmm0
movq %r15, %rdx
movq 64(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z27__device_stub__Z3runPdS_dliPdS_dli
jmp .L25
.L31:
movl $0, %ebx
jmp .L26
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3949:
.size main, .-main
.section .rodata.str1.1
.LC21:
.string "_Z3runPdS_dli"
.LC22:
.string "_Z4initPdS_dddi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3979:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _Z3runPdS_dli(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC22(%rip), %rdx
movq %rdx, %rcx
leaq _Z4initPdS_dddi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3979:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC8:
.long 0
.long 1070596096
.align 8
.LC9:
.long 0
.long 1074790400
.align 8
.LC10:
.long 1413754136
.long 1074340347
.align 8
.LC11:
.long -1698910392
.long 1048238066
.align 8
.LC16:
.long 261748427
.long 1052054839
.align 8
.LC17:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "run.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z19__device_stub__initPdS_dddi # -- Begin function _Z19__device_stub__initPdS_dddi
.p2align 4, 0x90
.type _Z19__device_stub__initPdS_dddi,@function
_Z19__device_stub__initPdS_dddi: # @_Z19__device_stub__initPdS_dddi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movsd %xmm0, 72(%rsp)
movsd %xmm1, 64(%rsp)
movsd %xmm2, 56(%rsp)
movl %edx, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z4initPdS_dddi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z19__device_stub__initPdS_dddi, .Lfunc_end0-_Z19__device_stub__initPdS_dddi
.cfi_endproc
# -- End function
.globl _Z18__device_stub__runPdS_dli # -- Begin function _Z18__device_stub__runPdS_dli
.p2align 4, 0x90
.type _Z18__device_stub__runPdS_dli,@function
_Z18__device_stub__runPdS_dli: # @_Z18__device_stub__runPdS_dli
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movsd %xmm0, 72(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3runPdS_dli, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end1:
.size _Z18__device_stub__runPdS_dli, .Lfunc_end1-_Z18__device_stub__runPdS_dli
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x3fd0000000000000 # double 0.25
.LCPI2_1:
.quad 0x4010000000000000 # double 4
.LCPI2_2:
.quad 0x400921fb54442d18 # double 3.1415926535897931
.LCPI2_3:
.quad 0x3e7ad7f29abcaf48 # double 9.9999999999999995E-8
.LCPI2_4:
.quad 0x3eb515370f99f6cb # double 1.2566370614359173E-6
.LCPI2_5:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967296, %r15 # imm = 0x100000000
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %rbx
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
leaq 224(%rsp), %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
leaq 152(%rsp), %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
leaq 144(%rsp), %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
leaq 12(%rsp), %rsi
movl $.L.str.7, %edi
xorl %eax, %eax
callq __isoc23_scanf
movsd 152(%rsp), %xmm1 # xmm1 = mem[0],zero
movl 12(%rsp), %eax
incl %eax
cvtsi2sd %eax, %xmm0
divsd %xmm0, %xmm1
movsd .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero
mulsd %xmm1, %xmm0
movsd %xmm1, 16(%rsp) # 8-byte Spill
mulsd %xmm1, %xmm0
mulsd .LCPI2_1(%rip), %xmm0
mulsd .LCPI2_2(%rip), %xmm0
mulsd .LCPI2_3(%rip), %xmm0
divsd 144(%rsp), %xmm0
movsd %xmm0, 128(%rsp) # 8-byte Spill
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
leaq 216(%rsp), %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq __isoc23_scanf
movslq 12(%rsp), %rax
leaq 16(,%rax,8), %r12
movq %r12, %rdi
callq malloc
movq %rax, %r14
leaq 24(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 136(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movl 12(%rsp), %edx
addl $2, %edx
orq %r15, %rdx
leaq 1(%r15), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB2_1
# %bb.2:
cmpl $0, 12(%rsp)
js .LBB2_3
.LBB2_4: # %.lr.ph.preheader
movl $-1, %ebp
movsd 16(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB2_5: # %.lr.ph
# =>This Inner Loop Header: Depth=1
incl %ebp
xorps %xmm0, %xmm0
cvtsi2sd %ebp, %xmm0
mulsd %xmm1, %xmm0
movl $.L.str.9, %esi
movq %rbx, %rdi
movb $1, %al
callq fprintf
movsd 16(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
cmpl 12(%rsp), %ebp
jl .LBB2_5
# %bb.6: # %._crit_edge.loopexit
incl %ebp
xorps %xmm0, %xmm0
cvtsi2sd %ebp, %xmm0
jmp .LBB2_7
.LBB2_1:
movq 136(%rsp), %rax
movq 24(%rsp), %rcx
movsd 224(%rsp), %xmm0 # xmm0 = mem[0],zero
movsd 152(%rsp), %xmm1 # xmm1 = mem[0],zero
movl 12(%rsp), %edx
addl $2, %edx
movq %rax, 112(%rsp)
movq %rcx, 104(%rsp)
movsd %xmm0, 96(%rsp)
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 88(%rsp)
movsd %xmm1, 48(%rsp)
movl %edx, 124(%rsp)
leaq 112(%rsp), %rax
movq %rax, 160(%rsp)
leaq 104(%rsp), %rax
movq %rax, 168(%rsp)
leaq 96(%rsp), %rax
movq %rax, 176(%rsp)
leaq 88(%rsp), %rax
movq %rax, 184(%rsp)
leaq 48(%rsp), %rax
movq %rax, 192(%rsp)
leaq 124(%rsp), %rax
movq %rax, 200(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z4initPdS_dddi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
cmpl $0, 12(%rsp)
jns .LBB2_4
.LBB2_3:
xorpd %xmm0, %xmm0
movsd 16(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
.LBB2_7: # %._crit_edge
mulsd %xmm1, %xmm0
movl $.L.str.10, %esi
movq %rbx, %rdi
movb $1, %al
callq fprintf
movq 24(%rsp), %rsi
movq %r14, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
cmpl $0, 12(%rsp)
js .LBB2_8
# %bb.9: # %.lr.ph75.preheader
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_10: # %.lr.ph75
# =>This Inner Loop Header: Depth=1
movsd (%r14,%r13,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.9, %esi
movq %rbx, %rdi
movb $1, %al
callq fprintf
leaq 1(%r13), %rax
movslq 12(%rsp), %rcx
cmpq %rcx, %r13
movq %rax, %r13
jl .LBB2_10
jmp .LBB2_11
.LBB2_8:
xorl %eax, %eax
.LBB2_11: # %._crit_edge76
movsd (%r14,%rax,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.10, %esi
movq %rbx, %rdi
movb $1, %al
callq fprintf
movsd 144(%rsp), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 208(%rsp) # 8-byte Spill
movsd 216(%rsp), %xmm0 # xmm0 = mem[0],zero
divsd 128(%rsp), %xmm0 # 8-byte Folded Reload
cvttsd2si %xmm0, %rbp
movl $.L.str.11, %edi
movq %rbp, %rsi
xorl %eax, %eax
callq printf
callq clock
movq %rax, %r13
movslq 12(%rsp), %rax
leaq 16(,%rax,8), %r8
addq $2, %rax
movl %eax, %edx
orq %r15, %rdx
incq %r15
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_13
# %bb.12:
movsd 128(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
mulsd 208(%rsp), %xmm2 # 8-byte Folded Reload
movsd .LCPI2_4(%rip), %xmm0 # xmm0 = mem[0],zero
movsd 16(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
mulsd %xmm1, %xmm0
divsd %xmm0, %xmm2
movq 136(%rsp), %rax
movq 24(%rsp), %rcx
movl 12(%rsp), %edx
addl $2, %edx
movq %rax, 112(%rsp)
movq %rcx, 104(%rsp)
movsd %xmm2, 96(%rsp)
movq %rbp, 88(%rsp)
movl %edx, 32(%rsp)
leaq 112(%rsp), %rax
movq %rax, 160(%rsp)
leaq 104(%rsp), %rax
movq %rax, 168(%rsp)
leaq 96(%rsp), %rax
movq %rax, 176(%rsp)
leaq 88(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rax
movq %rax, 192(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z3runPdS_dli, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_13:
callq hipDeviceSynchronize
callq clock
movq %rax, %r15
movq 24(%rsp), %rsi
movq %r14, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
cmpl $0, 12(%rsp)
js .LBB2_14
# %bb.15: # %.lr.ph81.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_16: # %.lr.ph81
# =>This Inner Loop Header: Depth=1
movsd (%r14,%r12,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.9, %esi
movq %rbx, %rdi
movb $1, %al
callq fprintf
leaq 1(%r12), %rax
movslq 12(%rsp), %rcx
cmpq %rcx, %r12
movq %rax, %r12
jl .LBB2_16
jmp .LBB2_17
.LBB2_14:
xorl %eax, %eax
.LBB2_17: # %._crit_edge82
subq %r13, %r15
xorps %xmm0, %xmm0
cvtsi2sd %r15, %xmm0
divsd .LCPI2_5(%rip), %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
movsd (%r14,%rax,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.10, %esi
movq %rbx, %rdi
movb $1, %al
callq fprintf
movl $.L.str.12, %edi
movl $5, %esi
movl $1, %edx
movq %rbx, %rcx
callq fwrite@PLT
movq %rbx, %rdi
callq fclose
movl $_ZSt4cout, %edi
movl $.L.str.13, %esi
movl $54, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.14, %esi
movl $5, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %eax, %eax
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4initPdS_dddi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3runPdS_dli, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4initPdS_dddi,@object # @_Z4initPdS_dddi
.section .rodata,"a",@progbits
.globl _Z4initPdS_dddi
.p2align 3, 0x0
_Z4initPdS_dddi:
.quad _Z19__device_stub__initPdS_dddi
.size _Z4initPdS_dddi, 8
.type _Z3runPdS_dli,@object # @_Z3runPdS_dli
.globl _Z3runPdS_dli
.p2align 3, 0x0
_Z3runPdS_dli:
.quad _Z18__device_stub__runPdS_dli
.size _Z3runPdS_dli, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "results.txt"
.size .L.str, 12
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "w"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "What is your I max? "
.size .L.str.2, 21
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%lf"
.size .L.str.3, 4
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "What is the length of your rod? "
.size .L.str.4, 33
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "What is eta? "
.size .L.str.5, 14
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "How many segments would you like? "
.size .L.str.6, 35
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%d"
.size .L.str.7, 3
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "How long would you like to run? "
.size .L.str.8, 33
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%lf "
.size .L.str.9, 5
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "%lf\n"
.size .L.str.10, 5
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "\nSteps: %ld\n"
.size .L.str.11, 13
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "STOP\n"
.size .L.str.12, 6
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "\n------------------------------------\nExecution took: "
.size .L.str.13, 55
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz " sec\n"
.size .L.str.14, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4initPdS_dddi"
.size .L__unnamed_1, 16
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z3runPdS_dli"
.size .L__unnamed_2, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__initPdS_dddi
.addrsig_sym _Z18__device_stub__runPdS_dli
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4initPdS_dddi
.addrsig_sym _Z3runPdS_dli
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#define block_size 32
#define vector_size 100
__global__ void add( int *a, int *b, int *c ) {
int tid = (blockIdx.x*blockDim.x) + threadIdx.x; // this thread handles the data at its thread id
if (tid < vector_size){
c[tid] = a[tid] + b[tid]; // add vectors together
}
}
int main( void ) {
// Set device that we will use for our cuda code
// It will be either 0 or 1
cudaSetDevice(0);
// Time Variables
cudaEvent_t start, stop;
float time;
cudaEventCreate (&start);
cudaEventCreate (&stop);
// Input Arrays and variables
int *a = new int [vector_size];
int *b = new int [vector_size];
int *c_cpu = new int [vector_size];
int *c_gpu = new int [vector_size];
// Pointers in GPU memory
int *dev_a;
int *dev_b;
int *dev_c;
// fill the arrays 'a' and 'b' on the CPU
for (int i = 0; i < vector_size; i++) {
a[i] = rand()%10;
b[i] = rand()%10;
}
//
// CPU Calculation
//////////////////
printf("Running sequential job.\n");
cudaEventRecord(start,0);
// Calculate C in the CPU
for (int i = 0; i < vector_size; i++) {
c_cpu[i] = a[i] + b[i];
}
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
printf("\tSequential Job Time: %.2f ms\n", time);
// allocate the memory on the GPU
// HERE
// copy the arrays 'a' and 'b' to the GPU
// HERE
//
// GPU Calculation
////////////////////////
printf("Running parallel job.\n");
cudaEventRecord(start,0);
// call the kernel
// HERE
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
printf("\tParallel Job Time: %.2f ms\n", time);
// copy the array 'c' back from the GPU to the CPU
// HERE (there's one more at the end, don't miss it!)
// compare the results
int error = 0;
for (int i = 0; i < vector_size; i++) {
if (c_cpu[i] != c_gpu[i]){
error = 1;
printf( "Error starting element %d, %d != %d\n", i, c_gpu[i], c_cpu[i] );
}
if (error) break;
}
if (error == 0){
printf ("Correct result. No errors were found.\n");
}
// free the memory allocated on the GPU
// HERE
return 0;
} | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R6, 0x63, PT ; /* 0x000000630600780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#define block_size 32
#define vector_size 100
__global__ void add( int *a, int *b, int *c ) {
int tid = (blockIdx.x*blockDim.x) + threadIdx.x; // this thread handles the data at its thread id
if (tid < vector_size){
c[tid] = a[tid] + b[tid]; // add vectors together
}
}
int main( void ) {
// Set device that we will use for our cuda code
// It will be either 0 or 1
cudaSetDevice(0);
// Time Variables
cudaEvent_t start, stop;
float time;
cudaEventCreate (&start);
cudaEventCreate (&stop);
// Input Arrays and variables
int *a = new int [vector_size];
int *b = new int [vector_size];
int *c_cpu = new int [vector_size];
int *c_gpu = new int [vector_size];
// Pointers in GPU memory
int *dev_a;
int *dev_b;
int *dev_c;
// fill the arrays 'a' and 'b' on the CPU
for (int i = 0; i < vector_size; i++) {
a[i] = rand()%10;
b[i] = rand()%10;
}
//
// CPU Calculation
//////////////////
printf("Running sequential job.\n");
cudaEventRecord(start,0);
// Calculate C in the CPU
for (int i = 0; i < vector_size; i++) {
c_cpu[i] = a[i] + b[i];
}
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
printf("\tSequential Job Time: %.2f ms\n", time);
// allocate the memory on the GPU
// HERE
// copy the arrays 'a' and 'b' to the GPU
// HERE
//
// GPU Calculation
////////////////////////
printf("Running parallel job.\n");
cudaEventRecord(start,0);
// call the kernel
// HERE
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
printf("\tParallel Job Time: %.2f ms\n", time);
// copy the array 'c' back from the GPU to the CPU
// HERE (there's one more at the end, don't miss it!)
// compare the results
int error = 0;
for (int i = 0; i < vector_size; i++) {
if (c_cpu[i] != c_gpu[i]){
error = 1;
printf( "Error starting element %d, %d != %d\n", i, c_gpu[i], c_cpu[i] );
}
if (error) break;
}
if (error == 0){
printf ("Correct result. No errors were found.\n");
}
// free the memory allocated on the GPU
// HERE
return 0;
} | .file "tmpxft_0019b3c8_00000000-6_VectorAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Running sequential job.\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "\tSequential Job Time: %.2f ms\n"
.section .rodata.str1.1
.LC2:
.string "Running parallel job.\n"
.LC3:
.string "\tParallel Job Time: %.2f ms\n"
.section .rodata.str1.8
.align 8
.LC4:
.string "Error starting element %d, %d != %d\n"
.align 8
.LC5:
.string "Correct result. No errors were found.\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $0, %edi
call cudaSetDevice@PLT
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl $400, %edi
call _Znam@PLT
movq %rax, %rbp
movl $400, %edi
call _Znam@PLT
movq %rax, %r12
movl $400, %edi
call _Znam@PLT
movq %rax, %r13
movl $400, %edi
call _Znam@PLT
movq %rax, %r14
movl $0, %ebx
.L4:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
movl %eax, 0(%rbp,%rbx)
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
movl %eax, (%r12,%rbx)
addq $4, %rbx
cmpq $400, %rbx
jne .L4
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl $0, %eax
.L5:
movl (%r12,%rax), %edx
addl 0(%rbp,%rax), %edx
movl %edx, 0(%r13,%rax)
addq $4, %rax
cmpq $400, %rax
jne .L5
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rbx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %edx
.L8:
movl 0(%r13,%rdx,4), %r8d
movl (%r14,%rdx,4), %ecx
cmpl %ecx, %r8d
jne .L14
addq $1, %rdx
cmpq $100, %rdx
jne .L8
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L7
.L14:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L7:
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L15
movl $0, %eax
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1
.LC6:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#define block_size 32
#define vector_size 100
__global__ void add( int *a, int *b, int *c ) {
int tid = (blockIdx.x*blockDim.x) + threadIdx.x; // this thread handles the data at its thread id
if (tid < vector_size){
c[tid] = a[tid] + b[tid]; // add vectors together
}
}
int main( void ) {
// Set device that we will use for our cuda code
// It will be either 0 or 1
cudaSetDevice(0);
// Time Variables
cudaEvent_t start, stop;
float time;
cudaEventCreate (&start);
cudaEventCreate (&stop);
// Input Arrays and variables
int *a = new int [vector_size];
int *b = new int [vector_size];
int *c_cpu = new int [vector_size];
int *c_gpu = new int [vector_size];
// Pointers in GPU memory
int *dev_a;
int *dev_b;
int *dev_c;
// fill the arrays 'a' and 'b' on the CPU
for (int i = 0; i < vector_size; i++) {
a[i] = rand()%10;
b[i] = rand()%10;
}
//
// CPU Calculation
//////////////////
printf("Running sequential job.\n");
cudaEventRecord(start,0);
// Calculate C in the CPU
for (int i = 0; i < vector_size; i++) {
c_cpu[i] = a[i] + b[i];
}
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
printf("\tSequential Job Time: %.2f ms\n", time);
// allocate the memory on the GPU
// HERE
// copy the arrays 'a' and 'b' to the GPU
// HERE
//
// GPU Calculation
////////////////////////
printf("Running parallel job.\n");
cudaEventRecord(start,0);
// call the kernel
// HERE
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
printf("\tParallel Job Time: %.2f ms\n", time);
// copy the array 'c' back from the GPU to the CPU
// HERE (there's one more at the end, don't miss it!)
// compare the results
int error = 0;
for (int i = 0; i < vector_size; i++) {
if (c_cpu[i] != c_gpu[i]){
error = 1;
printf( "Error starting element %d, %d != %d\n", i, c_gpu[i], c_cpu[i] );
}
if (error) break;
}
if (error == 0){
printf ("Correct result. No errors were found.\n");
}
// free the memory allocated on the GPU
// HERE
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define block_size 32
#define vector_size 100
__global__ void add( int *a, int *b, int *c ) {
int tid = (blockIdx.x*blockDim.x) + threadIdx.x; // this thread handles the data at its thread id
if (tid < vector_size){
c[tid] = a[tid] + b[tid]; // add vectors together
}
}
int main( void ) {
// Set device that we will use for our cuda code
// It will be either 0 or 1
hipSetDevice(0);
// Time Variables
hipEvent_t start, stop;
float time;
hipEventCreate (&start);
hipEventCreate (&stop);
// Input Arrays and variables
int *a = new int [vector_size];
int *b = new int [vector_size];
int *c_cpu = new int [vector_size];
int *c_gpu = new int [vector_size];
// Pointers in GPU memory
int *dev_a;
int *dev_b;
int *dev_c;
// fill the arrays 'a' and 'b' on the CPU
for (int i = 0; i < vector_size; i++) {
a[i] = rand()%10;
b[i] = rand()%10;
}
//
// CPU Calculation
//////////////////
printf("Running sequential job.\n");
hipEventRecord(start,0);
// Calculate C in the CPU
for (int i = 0; i < vector_size; i++) {
c_cpu[i] = a[i] + b[i];
}
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
printf("\tSequential Job Time: %.2f ms\n", time);
// allocate the memory on the GPU
// HERE
// copy the arrays 'a' and 'b' to the GPU
// HERE
//
// GPU Calculation
////////////////////////
printf("Running parallel job.\n");
hipEventRecord(start,0);
// call the kernel
// HERE
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
printf("\tParallel Job Time: %.2f ms\n", time);
// copy the array 'c' back from the GPU to the CPU
// HERE (there's one more at the end, don't miss it!)
// compare the results
int error = 0;
for (int i = 0; i < vector_size; i++) {
if (c_cpu[i] != c_gpu[i]){
error = 1;
printf( "Error starting element %d, %d != %d\n", i, c_gpu[i], c_cpu[i] );
}
if (error) break;
}
if (error == 0){
printf ("Correct result. No errors were found.\n");
}
// free the memory allocated on the GPU
// HERE
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define block_size 32
#define vector_size 100
__global__ void add( int *a, int *b, int *c ) {
int tid = (blockIdx.x*blockDim.x) + threadIdx.x; // this thread handles the data at its thread id
if (tid < vector_size){
c[tid] = a[tid] + b[tid]; // add vectors together
}
}
int main( void ) {
// Set device that we will use for our cuda code
// It will be either 0 or 1
hipSetDevice(0);
// Time Variables
hipEvent_t start, stop;
float time;
hipEventCreate (&start);
hipEventCreate (&stop);
// Input Arrays and variables
int *a = new int [vector_size];
int *b = new int [vector_size];
int *c_cpu = new int [vector_size];
int *c_gpu = new int [vector_size];
// Pointers in GPU memory
int *dev_a;
int *dev_b;
int *dev_c;
// fill the arrays 'a' and 'b' on the CPU
for (int i = 0; i < vector_size; i++) {
a[i] = rand()%10;
b[i] = rand()%10;
}
//
// CPU Calculation
//////////////////
printf("Running sequential job.\n");
hipEventRecord(start,0);
// Calculate C in the CPU
for (int i = 0; i < vector_size; i++) {
c_cpu[i] = a[i] + b[i];
}
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
printf("\tSequential Job Time: %.2f ms\n", time);
// allocate the memory on the GPU
// HERE
// copy the arrays 'a' and 'b' to the GPU
// HERE
//
// GPU Calculation
////////////////////////
printf("Running parallel job.\n");
hipEventRecord(start,0);
// call the kernel
// HERE
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
printf("\tParallel Job Time: %.2f ms\n", time);
// copy the array 'c' back from the GPU to the CPU
// HERE (there's one more at the end, don't miss it!)
// compare the results
int error = 0;
for (int i = 0; i < vector_size; i++) {
if (c_cpu[i] != c_gpu[i]){
error = 1;
printf( "Error starting element %d, %d != %d\n", i, c_gpu[i], c_cpu[i] );
}
if (error) break;
}
if (error == 0){
printf ("Correct result. No errors were found.\n");
}
// free the memory allocated on the GPU
// HERE
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x64, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define block_size 32
#define vector_size 100
__global__ void add( int *a, int *b, int *c ) {
int tid = (blockIdx.x*blockDim.x) + threadIdx.x; // this thread handles the data at its thread id
if (tid < vector_size){
c[tid] = a[tid] + b[tid]; // add vectors together
}
}
int main( void ) {
// Set device that we will use for our cuda code
// It will be either 0 or 1
hipSetDevice(0);
// Time Variables
hipEvent_t start, stop;
float time;
hipEventCreate (&start);
hipEventCreate (&stop);
// Input Arrays and variables
int *a = new int [vector_size];
int *b = new int [vector_size];
int *c_cpu = new int [vector_size];
int *c_gpu = new int [vector_size];
// Pointers in GPU memory
int *dev_a;
int *dev_b;
int *dev_c;
// fill the arrays 'a' and 'b' on the CPU
for (int i = 0; i < vector_size; i++) {
a[i] = rand()%10;
b[i] = rand()%10;
}
//
// CPU Calculation
//////////////////
printf("Running sequential job.\n");
hipEventRecord(start,0);
// Calculate C in the CPU
for (int i = 0; i < vector_size; i++) {
c_cpu[i] = a[i] + b[i];
}
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
printf("\tSequential Job Time: %.2f ms\n", time);
// allocate the memory on the GPU
// HERE
// copy the arrays 'a' and 'b' to the GPU
// HERE
//
// GPU Calculation
////////////////////////
printf("Running parallel job.\n");
hipEventRecord(start,0);
// call the kernel
// HERE
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
printf("\tParallel Job Time: %.2f ms\n", time);
// copy the array 'c' back from the GPU to the CPU
// HERE (there's one more at the end, don't miss it!)
// compare the results
int error = 0;
for (int i = 0; i < vector_size; i++) {
if (c_cpu[i] != c_gpu[i]){
error = 1;
printf( "Error starting element %d, %d != %d\n", i, c_gpu[i], c_cpu[i] );
}
if (error) break;
}
if (error == 0){
printf ("Correct result. No errors were found.\n");
}
// free the memory allocated on the GPU
// HERE
return 0;
} | .text
.file "VectorAdd.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $32, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %r13d, %r13d
xorl %edi, %edi
callq hipSetDevice
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movl $400, %edi # imm = 0x190
callq _Znam
movq %rax, %r15
movl $400, %edi # imm = 0x190
callq _Znam
movq %rax, %r12
movl $400, %edi # imm = 0x190
callq _Znam
movq %rax, %rbx
movl $400, %edi # imm = 0x190
callq _Znam
movq %rax, %r14
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%r15,%r13,4)
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%r12,%r13,4)
incq %r13
cmpq $100, %r13
jne .LBB1_1
# %bb.2:
movl $.Lstr, %edi
callq puts@PLT
movq 24(%rsp), %rdi
xorl %r13d, %r13d
xorl %esi, %esi
callq hipEventRecord
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movl (%r12,%r13,4), %eax
addl (%r15,%r13,4), %eax
movl %eax, (%rbx,%r13,4)
incq %r13
cmpq $100, %r13
jne .LBB1_3
# %bb.4:
movq 8(%rsp), %rdi
xorl %r15d, %r15d
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 20(%rsp), %r12
movq %r12, %rdi
callq hipEventElapsedTime
movss 20(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movl $.Lstr.1, %edi
callq puts@PLT
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
movq %r12, %rdi
callq hipEventElapsedTime
movss 20(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %ecx
movl (%r14,%r15,4), %edx
cmpl %edx, %ecx
jne .LBB1_6
# %bb.7: # %.critedge
# in Loop: Header=BB1_5 Depth=1
incq %r15
cmpq $100, %r15
jne .LBB1_5
# %bb.8: # %.critedge36
movl $.Lstr.2, %edi
callq puts@PLT
jmp .LBB1_9
.LBB1_6:
movl $.L.str.4, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
.LBB1_9:
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "\tSequential Job Time: %.2f ms\n"
.size .L.str.1, 31
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\tParallel Job Time: %.2f ms\n"
.size .L.str.3, 29
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Error starting element %d, %d != %d\n"
.size .L.str.4, 37
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Running sequential job."
.size .Lstr, 24
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Running parallel job."
.size .Lstr.1, 22
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Correct result. No errors were found."
.size .Lstr.2, 38
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R6, 0x63, PT ; /* 0x000000630600780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x64, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0019b3c8_00000000-6_VectorAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Running sequential job.\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "\tSequential Job Time: %.2f ms\n"
.section .rodata.str1.1
.LC2:
.string "Running parallel job.\n"
.LC3:
.string "\tParallel Job Time: %.2f ms\n"
.section .rodata.str1.8
.align 8
.LC4:
.string "Error starting element %d, %d != %d\n"
.align 8
.LC5:
.string "Correct result. No errors were found.\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $0, %edi
call cudaSetDevice@PLT
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl $400, %edi
call _Znam@PLT
movq %rax, %rbp
movl $400, %edi
call _Znam@PLT
movq %rax, %r12
movl $400, %edi
call _Znam@PLT
movq %rax, %r13
movl $400, %edi
call _Znam@PLT
movq %rax, %r14
movl $0, %ebx
.L4:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
movl %eax, 0(%rbp,%rbx)
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
movl %eax, (%r12,%rbx)
addq $4, %rbx
cmpq $400, %rbx
jne .L4
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl $0, %eax
.L5:
movl (%r12,%rax), %edx
addl 0(%rbp,%rax), %edx
movl %edx, 0(%r13,%rax)
addq $4, %rax
cmpq $400, %rax
jne .L5
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rbx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %edx
.L8:
movl 0(%r13,%rdx,4), %r8d
movl (%r14,%rdx,4), %ecx
cmpl %ecx, %r8d
jne .L14
addq $1, %rdx
cmpq $100, %rdx
jne .L8
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L7
.L14:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L7:
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L15
movl $0, %eax
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1
.LC6:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "VectorAdd.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $32, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %r13d, %r13d
xorl %edi, %edi
callq hipSetDevice
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movl $400, %edi # imm = 0x190
callq _Znam
movq %rax, %r15
movl $400, %edi # imm = 0x190
callq _Znam
movq %rax, %r12
movl $400, %edi # imm = 0x190
callq _Znam
movq %rax, %rbx
movl $400, %edi # imm = 0x190
callq _Znam
movq %rax, %r14
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%r15,%r13,4)
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%r12,%r13,4)
incq %r13
cmpq $100, %r13
jne .LBB1_1
# %bb.2:
movl $.Lstr, %edi
callq puts@PLT
movq 24(%rsp), %rdi
xorl %r13d, %r13d
xorl %esi, %esi
callq hipEventRecord
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movl (%r12,%r13,4), %eax
addl (%r15,%r13,4), %eax
movl %eax, (%rbx,%r13,4)
incq %r13
cmpq $100, %r13
jne .LBB1_3
# %bb.4:
movq 8(%rsp), %rdi
xorl %r15d, %r15d
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 20(%rsp), %r12
movq %r12, %rdi
callq hipEventElapsedTime
movss 20(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movl $.Lstr.1, %edi
callq puts@PLT
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
movq %r12, %rdi
callq hipEventElapsedTime
movss 20(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %ecx
movl (%r14,%r15,4), %edx
cmpl %edx, %ecx
jne .LBB1_6
# %bb.7: # %.critedge
# in Loop: Header=BB1_5 Depth=1
incq %r15
cmpq $100, %r15
jne .LBB1_5
# %bb.8: # %.critedge36
movl $.Lstr.2, %edi
callq puts@PLT
jmp .LBB1_9
.LBB1_6:
movl $.L.str.4, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
.LBB1_9:
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "\tSequential Job Time: %.2f ms\n"
.size .L.str.1, 31
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\tParallel Job Time: %.2f ms\n"
.size .L.str.3, 29
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Error starting element %d, %d != %d\n"
.size .L.str.4, 37
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Running sequential job."
.size .Lstr, 24
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Running parallel job."
.size .Lstr.1, 22
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Correct result. No errors were found."
.size .Lstr.2, 38
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void sgemm_kernel(const float *A, const float *B, float *C, int M, int N, int K, float alpha, float beta)
{
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
float element_c = 0.f;
for (int e = 0; e < K; e++)
element_c += A[row * K + e] * B[e * K + col];
C[row * N + col] = alpha * element_c + beta * C[row * N + col];
} | code for sm_80
Function : _Z12sgemm_kernelPKfS0_Pfiiiff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ MOV R0, c[0x0][0x180] ; /* 0x0000600000007a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e680000002600 */
/*0080*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0090*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fe400078e0203 */
/*00a0*/ IMAD R3, R4, c[0x0][0x4], R5 ; /* 0x0000010004037a24 */
/* 0x002fc600078e0205 */
/*00b0*/ @!P0 BRA 0xbd0 ; /* 0x00000b1000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R4, R0.reuse, -0x1, RZ ; /* 0xffffffff00047810 */
/* 0x040fe40007ffe0ff */
/*00d0*/ LOP3.LUT R5, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300057812 */
/* 0x000fe400078ec0ff */
/*00e0*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*00f0*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fe40000000f00 */
/*0100*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*0110*/ @!P0 BRA 0xad0 ; /* 0x000009b000008947 */
/* 0x000fea0003800000 */
/*0120*/ IADD3 R6, -R5, c[0x0][0x180], RZ ; /* 0x0000600005067a10 */
/* 0x000fe20007ffe1ff */
/*0130*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0140*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0150*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*0160*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f04270 */
/*0170*/ IMAD R7, R3, c[0x0][0x180], RZ ; /* 0x0000600003077a24 */
/* 0x000fe200078e02ff */
/*0180*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fca0000000f00 */
/*0190*/ IMAD.WIDE R8, R2, R9, c[0x0][0x168] ; /* 0x00005a0002087625 */
/* 0x000fcc00078e0209 */
/*01a0*/ @!P0 BRA 0x940 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01b0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01d0*/ @!P1 BRA 0x680 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01f0*/ MOV R14, UR6 ; /* 0x00000006000e7c02 */
/* 0x000fe20008000f00 */
/*0200*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a2000c1e1900 */
/*0210*/ MOV R15, UR7 ; /* 0x00000007000f7c02 */
/* 0x000fca0008000f00 */
/*0220*/ IMAD.WIDE R14, R7, 0x4, R14 ; /* 0x00000004070e7825 */
/* 0x000fca00078e020e */
/*0230*/ LDG.E R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x000ea2000c1e1900 */
/*0240*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fc600078e0208 */
/*0250*/ LDG.E R18, [R14.64+0x4] ; /* 0x000004040e127981 */
/* 0x000ee6000c1e1900 */
/*0260*/ IMAD.WIDE R22, R0.reuse, 0x4, R8 ; /* 0x0000000400167825 */
/* 0x040fe200078e0208 */
/*0270*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x0000e8000c1e1900 */
/*0280*/ LDG.E R28, [R22.64] ; /* 0x00000004161c7981 */
/* 0x000322000c1e1900 */
/*0290*/ IMAD.WIDE R26, R0, 0x4, R22 ; /* 0x00000004001a7825 */
/* 0x000fc600078e0216 */
/*02a0*/ LDG.E R29, [R14.64+0x8] ; /* 0x000008040e1d7981 */
/* 0x000f26000c1e1900 */
/*02b0*/ IMAD.WIDE R12, R0.reuse, 0x4, R26 ; /* 0x00000004000c7825 */
/* 0x040fe200078e021a */
/*02c0*/ LDG.E R16, [R26.64] ; /* 0x000000041a107981 */
/* 0x000b28000c1e1900 */
/*02d0*/ LDG.E R17, [R14.64+0xc] ; /* 0x00000c040e117981 */
/* 0x000f28000c1e1900 */
/*02e0*/ LDG.E R20, [R14.64+0x10] ; /* 0x000010040e147981 */
/* 0x000f28000c1e1900 */
/*02f0*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000328000c1e1900 */
/*0300*/ LDG.E R8, [R14.64+0x14] ; /* 0x000014040e087981 */
/* 0x001f28000c1e1900 */
/*0310*/ LDG.E R26, [R14.64+0x1c] ; /* 0x00001c040e1a7981 */
/* 0x020f62000c1e1900 */
/*0320*/ IMAD.WIDE R12, R0, 0x4, R12 ; /* 0x00000004000c7825 */
/* 0x002fca00078e020c */
/*0330*/ LDG.E R9, [R12.64] ; /* 0x000000040c097981 */
/* 0x000562000c1e1900 */
/*0340*/ IMAD.WIDE R22, R0, 0x4, R12 ; /* 0x0000000400167825 */
/* 0x000fc800078e020c */
/*0350*/ FFMA R12, R11, R10, R24 ; /* 0x0000000a0b0c7223 */
/* 0x004fe40000000018 */
/*0360*/ LDG.E R10, [R14.64+0x18] ; /* 0x000018040e0a7981 */
/* 0x000ea2000c1e1900 */
/*0370*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x000fc600078e0216 */
/*0380*/ LDG.E R11, [R22.64] ; /* 0x00000004160b7981 */
/* 0x0000a8000c1e1900 */
/*0390*/ LDG.E R27, [R24.64] ; /* 0x00000004181b7981 */
/* 0x0002a2000c1e1900 */
/*03a0*/ FFMA R12, R19, R18, R12 ; /* 0x00000012130c7223 */
/* 0x008fe4000000000c */
/*03b0*/ IMAD.WIDE R18, R0, 0x4, R24 ; /* 0x0000000400127825 */
/* 0x000fe200078e0218 */
/*03c0*/ LDG.E R23, [R14.64+0x20] ; /* 0x000020040e177981 */
/* 0x001ee6000c1e1900 */
/*03d0*/ FFMA R28, R28, R29, R12 ; /* 0x0000001d1c1c7223 */
/* 0x010fc4000000000c */
/*03e0*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x000fe200078e0212 */
/*03f0*/ LDG.E R25, [R14.64+0x24] ; /* 0x000024040e197981 */
/* 0x002f26000c1e1900 */
/*0400*/ FFMA R28, R16, R17, R28 ; /* 0x00000011101c7223 */
/* 0x000fe2000000001c */
/*0410*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000e2000c1e1900 */
/*0420*/ IMAD.WIDE R16, R0, 0x4, R12 ; /* 0x0000000400107825 */
/* 0x000fc600078e020c */
/*0430*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000322000c1e1900 */
/*0440*/ FFMA R28, R21, R20, R28 ; /* 0x00000014151c7223 */
/* 0x000fc6000000001c */
/*0450*/ LDG.E R22, [R16.64] ; /* 0x0000000410167981 */
/* 0x0002e2000c1e1900 */
/*0460*/ IMAD.WIDE R20, R0, 0x4, R16 ; /* 0x0000000400147825 */
/* 0x000fc600078e0210 */
/*0470*/ LDG.E R29, [R14.64+0x28] ; /* 0x000028040e1d7981 */
/* 0x000f28000c1e1900 */
/*0480*/ LDG.E R19, [R14.64+0x2c] ; /* 0x00002c040e137981 */
/* 0x001f28000c1e1900 */
/*0490*/ LDG.E R24, [R14.64+0x30] ; /* 0x000030040e187981 */
/* 0x000f22000c1e1900 */
/*04a0*/ FFMA R28, R9, R8, R28 ; /* 0x00000008091c7223 */
/* 0x020fe4000000001c */
/*04b0*/ IMAD.WIDE R8, R0, 0x4, R20 ; /* 0x0000000400087825 */
/* 0x000fc400078e0214 */
/*04c0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000168000c1e1900 */
/*04d0*/ LDG.E R21, [R14.64+0x38] ; /* 0x000038040e157981 */
/* 0x001f62000c1e1900 */
/*04e0*/ FFMA R28, R11, R10, R28 ; /* 0x0000000a0b1c7223 */
/* 0x004fe4000000001c */
/*04f0*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fe400078e0208 */
/*0500*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x0000a4000c1e1900 */
/*0510*/ FFMA R13, R27, R26, R28 ; /* 0x0000001a1b0d7223 */
/* 0x002fc4000000001c */
/*0520*/ IMAD.WIDE R26, R0.reuse, 0x4, R10 ; /* 0x00000004001a7825 */
/* 0x040fe400078e020a */
/*0530*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x0002a8000c1e1900 */
/*0540*/ LDG.E R9, [R14.64+0x34] ; /* 0x000034040e097981 */
/* 0x001ea2000c1e1900 */
/*0550*/ IMAD.WIDE R16, R0, 0x4, R26 ; /* 0x0000000400107825 */
/* 0x000fc600078e021a */
/*0560*/ LDG.E R28, [R26.64] ; /* 0x000000041a1c7981 */
/* 0x0000a8000c1e1900 */
/*0570*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x002ea8000c1e1900 */
/*0580*/ LDG.E R26, [R14.64+0x3c] ; /* 0x00003c040e1a7981 */
/* 0x001ea2000c1e1900 */
/*0590*/ FFMA R13, R18, R23, R13 ; /* 0x00000017120d7223 */
/* 0x008fc8000000000d */
/*05a0*/ FFMA R12, R12, R25, R13 ; /* 0x000000190c0c7223 */
/* 0x010fe2000000000d */
/*05b0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc60007ffe0ff */
/*05c0*/ FFMA R12, R22, R29, R12 ; /* 0x0000001d160c7223 */
/* 0x000fe2000000000c */
/*05d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fc60003f24270 */
/*05e0*/ FFMA R19, R20, R19, R12 ; /* 0x0000001314137223 */
/* 0x020fe2000000000c */
/*05f0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0600*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0610*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0620*/ FFMA R8, R8, R24, R19 ; /* 0x0000001808087223 */
/* 0x004fc80000000013 */
/*0630*/ FFMA R8, R10, R9, R8 ; /* 0x000000090a087223 */
/* 0x000fc80000000008 */
/*0640*/ FFMA R8, R28, R21, R8 ; /* 0x000000151c087223 */
/* 0x000fc80000000008 */
/*0650*/ FFMA R24, R11, R26, R8 ; /* 0x0000001a0b187223 */
/* 0x000fe40000000008 */
/*0660*/ IMAD.WIDE R8, R0, 0x4, R16 ; /* 0x0000000400087825 */
/* 0x000fe200078e0210 */
/*0670*/ @P1 BRA 0x1f0 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*0680*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0690*/ @!P1 BRA 0x920 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06a0*/ IMAD.WIDE R16, R0, 0x4, R8 ; /* 0x0000000400107825 */
/* 0x000fe200078e0208 */
/*06b0*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe20008000f00 */
/*06c0*/ LDG.E R23, [R8.64] ; /* 0x0000000408177981 */
/* 0x0000a2000c1e1900 */
/*06d0*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fc60008000f00 */
/*06e0*/ IMAD.WIDE R12, R0.reuse, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x040fe400078e0210 */
/*06f0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0002e4000c1e1900 */
/*0700*/ IMAD.WIDE R10, R7, 0x4, R10 ; /* 0x00000004070a7825 */
/* 0x000fe400078e020a */
/*0710*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000964000c1e1900 */
/*0720*/ IMAD.WIDE R14, R0.reuse, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x040fe400078e020c */
/*0730*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x000ea8000c1e1900 */
/*0740*/ LDG.E R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000ee2000c1e1900 */
/*0750*/ IMAD.WIDE R18, R0, 0x4, R14 ; /* 0x0000000400127825 */
/* 0x000fc600078e020e */
/*0760*/ LDG.E R27, [R10.64+0x8] ; /* 0x000008040a1b7981 */
/* 0x000f66000c1e1900 */
/*0770*/ IMAD.WIDE R20, R0.reuse, 0x4, R18 ; /* 0x0000000400147825 */
/* 0x040fe200078e0212 */
/*0780*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*0790*/ LDG.E R29, [R10.64+0xc] ; /* 0x00000c040a1d7981 */
/* 0x000f62000c1e1900 */
/*07a0*/ IMAD.WIDE R8, R0, 0x4, R20 ; /* 0x0000000400087825 */
/* 0x001fc600078e0214 */
/*07b0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000168000c1e1900 */
/*07c0*/ LDG.E R28, [R10.64+0x10] ; /* 0x000010040a1c7981 */
/* 0x000f62000c1e1900 */
/*07d0*/ IMAD.WIDE R12, R0, 0x4, R8 ; /* 0x00000004000c7825 */
/* 0x010fc600078e0208 */
/*07e0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000f28000c1e1900 */
/*07f0*/ LDG.E R15, [R10.64+0x14] ; /* 0x000014040a0f7981 */
/* 0x002f28000c1e1900 */
/*0800*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000328000c1e1900 */
/*0810*/ LDG.E R19, [R10.64+0x1c] ; /* 0x00001c040a137981 */
/* 0x001f28000c1e1900 */
/*0820*/ LDG.E R8, [R10.64+0x18] ; /* 0x000018040a087981 */
/* 0x002f28000c1e1900 */
/*0830*/ LDG.E R9, [R12.64] ; /* 0x000000040c097981 */
/* 0x000f22000c1e1900 */
/*0840*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0850*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0860*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*0870*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0880*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0890*/ FFMA R22, R23, R22, R24 ; /* 0x0000001617167223 */
/* 0x004fc80000000018 */
/*08a0*/ FFMA R16, R16, R25, R22 ; /* 0x0000001910107223 */
/* 0x008fc80000000016 */
/*08b0*/ FFMA R16, R26, R27, R16 ; /* 0x0000001b1a107223 */
/* 0x020fc80000000010 */
/*08c0*/ FFMA R29, R14, R29, R16 ; /* 0x0000001d0e1d7223 */
/* 0x000fc80000000010 */
/*08d0*/ FFMA R18, R18, R28, R29 ; /* 0x0000001c12127223 */
/* 0x000fc8000000001d */
/*08e0*/ FFMA R15, R20, R15, R18 ; /* 0x0000000f140f7223 */
/* 0x010fc80000000012 */
/*08f0*/ FFMA R8, R17, R8, R15 ; /* 0x0000000811087223 */
/* 0x000fc8000000000f */
/*0900*/ FFMA R24, R9, R19, R8 ; /* 0x0000001309187223 */
/* 0x000fe40000000008 */
/*0910*/ IMAD.WIDE R8, R0, 0x4, R12 ; /* 0x0000000400087825 */
/* 0x000fc800078e020c */
/*0920*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0930*/ @!P0 BRA 0xad0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0940*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0950*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fe200078e0208 */
/*0960*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fe20008000f00 */
/*0970*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea8000c1e1900 */
/*0980*/ IMAD.WIDE R12, R7, 0x4, R12 ; /* 0x00000004070c7825 */
/* 0x000fc800078e020c */
/*0990*/ IMAD.WIDE R14, R0.reuse, 0x4, R10 ; /* 0x00000004000e7825 */
/* 0x040fe200078e020a */
/*09a0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000ee2000c1e1900 */
/*09c0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*09d0*/ LDG.E R19, [R12.64+0x4] ; /* 0x000004040c137981 */
/* 0x000ee8000c1e1900 */
/*09e0*/ LDG.E R21, [R14.64] ; /* 0x000000040e157981 */
/* 0x000f28000c1e1900 */
/*09f0*/ LDG.E R20, [R12.64+0x8] ; /* 0x000008040c147981 */
/* 0x000f28000c1e1900 */
/*0a00*/ LDG.E R22, [R12.64+0xc] ; /* 0x00000c040c167981 */
/* 0x000f68000c1e1900 */
/*0a10*/ LDG.E R23, [R16.64] ; /* 0x0000000410177981 */
/* 0x000f62000c1e1900 */
/*0a20*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a30*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a40*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a50*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a60*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a70*/ FFMA R18, R9, R18, R24 ; /* 0x0000001209127223 */
/* 0x004fc80000000018 */
/*0a80*/ FFMA R18, R11, R19, R18 ; /* 0x000000130b127223 */
/* 0x008fe40000000012 */
/*0a90*/ IMAD.WIDE R8, R0, 0x4, R16 ; /* 0x0000000400087825 */
/* 0x000fc800078e0210 */
/*0aa0*/ FFMA R18, R21, R20, R18 ; /* 0x0000001415127223 */
/* 0x010fc80000000012 */
/*0ab0*/ FFMA R24, R23, R22, R18 ; /* 0x0000001617187223 */
/* 0x020fe20000000012 */
/*0ac0*/ @P0 BRA 0x940 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0ad0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0ae0*/ @!P0 BRA 0xbd0 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0af0*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b00*/ IMAD R6, R3, c[0x0][0x180], R4 ; /* 0x0000600003067a24 */
/* 0x000fe400078e0204 */
/*0b10*/ IMAD R4, R4, c[0x0][0x180], R2 ; /* 0x0000600004047a24 */
/* 0x000fce00078e0202 */
/*0b20*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b30*/ IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fca00078e0209 */
/*0b40*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a8000c1e1900 */
/*0b50*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002a2000c1e1900 */
/*0b60*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0b70*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0b80*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fe200078e0208 */
/*0b90*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0ba0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0bb0*/ FFMA R24, R11, R4, R24 ; /* 0x000000040b187223 */
/* 0x004fcc0000000018 */
/*0bc0*/ @P0 BRA 0xb40 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0bd0*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fe20000000f00 */
/*0be0*/ IMAD R2, R3, c[0x0][0x17c], R2 ; /* 0x00005f0003027a24 */
/* 0x000fc800078e0202 */
/*0bf0*/ IMAD.WIDE R2, R2, R5, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0205 */
/*0c00*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0c10*/ FMUL R5, R0, c[0x0][0x188] ; /* 0x0000620000057a20 */
/* 0x004fc80000400000 */
/*0c20*/ FFMA R5, R24, c[0x0][0x184], R5 ; /* 0x0000610018057a23 */
/* 0x000fca0000000005 */
/*0c30*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0c40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c50*/ BRA 0xc50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void sgemm_kernel(const float *A, const float *B, float *C, int M, int N, int K, float alpha, float beta)
{
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
float element_c = 0.f;
for (int e = 0; e < K; e++)
element_c += A[row * K + e] * B[e * K + col];
C[row * N + col] = alpha * element_c + beta * C[row * N + col];
} | .file "tmpxft_001167a8_00000000-6_sgemm_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z12sgemm_kernelPKfS0_PfiiiffPKfS0_Pfiiiff
.type _Z43__device_stub__Z12sgemm_kernelPKfS0_PfiiiffPKfS0_Pfiiiff, @function
_Z43__device_stub__Z12sgemm_kernelPKfS0_PfiiiffPKfS0_Pfiiiff:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm1, 4(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
leaq 4(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12sgemm_kernelPKfS0_Pfiiiff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z12sgemm_kernelPKfS0_PfiiiffPKfS0_Pfiiiff, .-_Z43__device_stub__Z12sgemm_kernelPKfS0_PfiiiffPKfS0_Pfiiiff
.globl _Z12sgemm_kernelPKfS0_Pfiiiff
.type _Z12sgemm_kernelPKfS0_Pfiiiff, @function
_Z12sgemm_kernelPKfS0_Pfiiiff:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z12sgemm_kernelPKfS0_PfiiiffPKfS0_Pfiiiff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12sgemm_kernelPKfS0_Pfiiiff, .-_Z12sgemm_kernelPKfS0_Pfiiiff
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12sgemm_kernelPKfS0_Pfiiiff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12sgemm_kernelPKfS0_Pfiiiff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void sgemm_kernel(const float *A, const float *B, float *C, int M, int N, int K, float alpha, float beta)
{
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
float element_c = 0.f;
for (int e = 0; e < K; e++)
element_c += A[row * K + e] * B[e * K + col];
C[row * N + col] = alpha * element_c + beta * C[row * N + col];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sgemm_kernel(const float *A, const float *B, float *C, int M, int N, int K, float alpha, float beta)
{
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
float element_c = 0.f;
for (int e = 0; e < K; e++)
element_c += A[row * K + e] * B[e * K + col];
C[row * N + col] = alpha * element_c + beta * C[row * N + col];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sgemm_kernel(const float *A, const float *B, float *C, int M, int N, int K, float alpha, float beta)
{
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
float element_c = 0.f;
for (int e = 0; e < K; e++)
element_c += A[row * K + e] * B[e * K + col];
C[row * N + col] = alpha * element_c + beta * C[row * N + col];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12sgemm_kernelPKfS0_Pfiiiff
.globl _Z12sgemm_kernelPKfS0_Pfiiiff
.p2align 8
.type _Z12sgemm_kernelPKfS0_Pfiiiff,@function
_Z12sgemm_kernelPKfS0_Pfiiiff:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x3c
s_load_b32 s2, s[0:1], 0x20
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_mul_lo_u32 v2, v1, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v0
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x24
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, s1, v2
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v2, s0, v6
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12sgemm_kernelPKfS0_Pfiiiff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12sgemm_kernelPKfS0_Pfiiiff, .Lfunc_end0-_Z12sgemm_kernelPKfS0_Pfiiiff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12sgemm_kernelPKfS0_Pfiiiff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12sgemm_kernelPKfS0_Pfiiiff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sgemm_kernel(const float *A, const float *B, float *C, int M, int N, int K, float alpha, float beta)
{
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
float element_c = 0.f;
for (int e = 0; e < K; e++)
element_c += A[row * K + e] * B[e * K + col];
C[row * N + col] = alpha * element_c + beta * C[row * N + col];
} | .text
.file "sgemm_kernel.hip"
.globl _Z27__device_stub__sgemm_kernelPKfS0_Pfiiiff # -- Begin function _Z27__device_stub__sgemm_kernelPKfS0_Pfiiiff
.p2align 4, 0x90
.type _Z27__device_stub__sgemm_kernelPKfS0_Pfiiiff,@function
_Z27__device_stub__sgemm_kernelPKfS0_Pfiiiff: # @_Z27__device_stub__sgemm_kernelPKfS0_Pfiiiff
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm1, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12sgemm_kernelPKfS0_Pfiiiff, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z27__device_stub__sgemm_kernelPKfS0_Pfiiiff, .Lfunc_end0-_Z27__device_stub__sgemm_kernelPKfS0_Pfiiiff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12sgemm_kernelPKfS0_Pfiiiff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12sgemm_kernelPKfS0_Pfiiiff,@object # @_Z12sgemm_kernelPKfS0_Pfiiiff
.section .rodata,"a",@progbits
.globl _Z12sgemm_kernelPKfS0_Pfiiiff
.p2align 3, 0x0
_Z12sgemm_kernelPKfS0_Pfiiiff:
.quad _Z27__device_stub__sgemm_kernelPKfS0_Pfiiiff
.size _Z12sgemm_kernelPKfS0_Pfiiiff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12sgemm_kernelPKfS0_Pfiiiff"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__sgemm_kernelPKfS0_Pfiiiff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12sgemm_kernelPKfS0_Pfiiiff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12sgemm_kernelPKfS0_Pfiiiff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ MOV R0, c[0x0][0x180] ; /* 0x0000600000007a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e680000002600 */
/*0080*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0090*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fe400078e0203 */
/*00a0*/ IMAD R3, R4, c[0x0][0x4], R5 ; /* 0x0000010004037a24 */
/* 0x002fc600078e0205 */
/*00b0*/ @!P0 BRA 0xbd0 ; /* 0x00000b1000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R4, R0.reuse, -0x1, RZ ; /* 0xffffffff00047810 */
/* 0x040fe40007ffe0ff */
/*00d0*/ LOP3.LUT R5, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300057812 */
/* 0x000fe400078ec0ff */
/*00e0*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*00f0*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fe40000000f00 */
/*0100*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*0110*/ @!P0 BRA 0xad0 ; /* 0x000009b000008947 */
/* 0x000fea0003800000 */
/*0120*/ IADD3 R6, -R5, c[0x0][0x180], RZ ; /* 0x0000600005067a10 */
/* 0x000fe20007ffe1ff */
/*0130*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0140*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0150*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*0160*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f04270 */
/*0170*/ IMAD R7, R3, c[0x0][0x180], RZ ; /* 0x0000600003077a24 */
/* 0x000fe200078e02ff */
/*0180*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fca0000000f00 */
/*0190*/ IMAD.WIDE R8, R2, R9, c[0x0][0x168] ; /* 0x00005a0002087625 */
/* 0x000fcc00078e0209 */
/*01a0*/ @!P0 BRA 0x940 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01b0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01d0*/ @!P1 BRA 0x680 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01f0*/ MOV R14, UR6 ; /* 0x00000006000e7c02 */
/* 0x000fe20008000f00 */
/*0200*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a2000c1e1900 */
/*0210*/ MOV R15, UR7 ; /* 0x00000007000f7c02 */
/* 0x000fca0008000f00 */
/*0220*/ IMAD.WIDE R14, R7, 0x4, R14 ; /* 0x00000004070e7825 */
/* 0x000fca00078e020e */
/*0230*/ LDG.E R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x000ea2000c1e1900 */
/*0240*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fc600078e0208 */
/*0250*/ LDG.E R18, [R14.64+0x4] ; /* 0x000004040e127981 */
/* 0x000ee6000c1e1900 */
/*0260*/ IMAD.WIDE R22, R0.reuse, 0x4, R8 ; /* 0x0000000400167825 */
/* 0x040fe200078e0208 */
/*0270*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x0000e8000c1e1900 */
/*0280*/ LDG.E R28, [R22.64] ; /* 0x00000004161c7981 */
/* 0x000322000c1e1900 */
/*0290*/ IMAD.WIDE R26, R0, 0x4, R22 ; /* 0x00000004001a7825 */
/* 0x000fc600078e0216 */
/*02a0*/ LDG.E R29, [R14.64+0x8] ; /* 0x000008040e1d7981 */
/* 0x000f26000c1e1900 */
/*02b0*/ IMAD.WIDE R12, R0.reuse, 0x4, R26 ; /* 0x00000004000c7825 */
/* 0x040fe200078e021a */
/*02c0*/ LDG.E R16, [R26.64] ; /* 0x000000041a107981 */
/* 0x000b28000c1e1900 */
/*02d0*/ LDG.E R17, [R14.64+0xc] ; /* 0x00000c040e117981 */
/* 0x000f28000c1e1900 */
/*02e0*/ LDG.E R20, [R14.64+0x10] ; /* 0x000010040e147981 */
/* 0x000f28000c1e1900 */
/*02f0*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000328000c1e1900 */
/*0300*/ LDG.E R8, [R14.64+0x14] ; /* 0x000014040e087981 */
/* 0x001f28000c1e1900 */
/*0310*/ LDG.E R26, [R14.64+0x1c] ; /* 0x00001c040e1a7981 */
/* 0x020f62000c1e1900 */
/*0320*/ IMAD.WIDE R12, R0, 0x4, R12 ; /* 0x00000004000c7825 */
/* 0x002fca00078e020c */
/*0330*/ LDG.E R9, [R12.64] ; /* 0x000000040c097981 */
/* 0x000562000c1e1900 */
/*0340*/ IMAD.WIDE R22, R0, 0x4, R12 ; /* 0x0000000400167825 */
/* 0x000fc800078e020c */
/*0350*/ FFMA R12, R11, R10, R24 ; /* 0x0000000a0b0c7223 */
/* 0x004fe40000000018 */
/*0360*/ LDG.E R10, [R14.64+0x18] ; /* 0x000018040e0a7981 */
/* 0x000ea2000c1e1900 */
/*0370*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x000fc600078e0216 */
/*0380*/ LDG.E R11, [R22.64] ; /* 0x00000004160b7981 */
/* 0x0000a8000c1e1900 */
/*0390*/ LDG.E R27, [R24.64] ; /* 0x00000004181b7981 */
/* 0x0002a2000c1e1900 */
/*03a0*/ FFMA R12, R19, R18, R12 ; /* 0x00000012130c7223 */
/* 0x008fe4000000000c */
/*03b0*/ IMAD.WIDE R18, R0, 0x4, R24 ; /* 0x0000000400127825 */
/* 0x000fe200078e0218 */
/*03c0*/ LDG.E R23, [R14.64+0x20] ; /* 0x000020040e177981 */
/* 0x001ee6000c1e1900 */
/*03d0*/ FFMA R28, R28, R29, R12 ; /* 0x0000001d1c1c7223 */
/* 0x010fc4000000000c */
/*03e0*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x000fe200078e0212 */
/*03f0*/ LDG.E R25, [R14.64+0x24] ; /* 0x000024040e197981 */
/* 0x002f26000c1e1900 */
/*0400*/ FFMA R28, R16, R17, R28 ; /* 0x00000011101c7223 */
/* 0x000fe2000000001c */
/*0410*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000e2000c1e1900 */
/*0420*/ IMAD.WIDE R16, R0, 0x4, R12 ; /* 0x0000000400107825 */
/* 0x000fc600078e020c */
/*0430*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000322000c1e1900 */
/*0440*/ FFMA R28, R21, R20, R28 ; /* 0x00000014151c7223 */
/* 0x000fc6000000001c */
/*0450*/ LDG.E R22, [R16.64] ; /* 0x0000000410167981 */
/* 0x0002e2000c1e1900 */
/*0460*/ IMAD.WIDE R20, R0, 0x4, R16 ; /* 0x0000000400147825 */
/* 0x000fc600078e0210 */
/*0470*/ LDG.E R29, [R14.64+0x28] ; /* 0x000028040e1d7981 */
/* 0x000f28000c1e1900 */
/*0480*/ LDG.E R19, [R14.64+0x2c] ; /* 0x00002c040e137981 */
/* 0x001f28000c1e1900 */
/*0490*/ LDG.E R24, [R14.64+0x30] ; /* 0x000030040e187981 */
/* 0x000f22000c1e1900 */
/*04a0*/ FFMA R28, R9, R8, R28 ; /* 0x00000008091c7223 */
/* 0x020fe4000000001c */
/*04b0*/ IMAD.WIDE R8, R0, 0x4, R20 ; /* 0x0000000400087825 */
/* 0x000fc400078e0214 */
/*04c0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000168000c1e1900 */
/*04d0*/ LDG.E R21, [R14.64+0x38] ; /* 0x000038040e157981 */
/* 0x001f62000c1e1900 */
/*04e0*/ FFMA R28, R11, R10, R28 ; /* 0x0000000a0b1c7223 */
/* 0x004fe4000000001c */
/*04f0*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fe400078e0208 */
/*0500*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x0000a4000c1e1900 */
/*0510*/ FFMA R13, R27, R26, R28 ; /* 0x0000001a1b0d7223 */
/* 0x002fc4000000001c */
/*0520*/ IMAD.WIDE R26, R0.reuse, 0x4, R10 ; /* 0x00000004001a7825 */
/* 0x040fe400078e020a */
/*0530*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x0002a8000c1e1900 */
/*0540*/ LDG.E R9, [R14.64+0x34] ; /* 0x000034040e097981 */
/* 0x001ea2000c1e1900 */
/*0550*/ IMAD.WIDE R16, R0, 0x4, R26 ; /* 0x0000000400107825 */
/* 0x000fc600078e021a */
/*0560*/ LDG.E R28, [R26.64] ; /* 0x000000041a1c7981 */
/* 0x0000a8000c1e1900 */
/*0570*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x002ea8000c1e1900 */
/*0580*/ LDG.E R26, [R14.64+0x3c] ; /* 0x00003c040e1a7981 */
/* 0x001ea2000c1e1900 */
/*0590*/ FFMA R13, R18, R23, R13 ; /* 0x00000017120d7223 */
/* 0x008fc8000000000d */
/*05a0*/ FFMA R12, R12, R25, R13 ; /* 0x000000190c0c7223 */
/* 0x010fe2000000000d */
/*05b0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc60007ffe0ff */
/*05c0*/ FFMA R12, R22, R29, R12 ; /* 0x0000001d160c7223 */
/* 0x000fe2000000000c */
/*05d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fc60003f24270 */
/*05e0*/ FFMA R19, R20, R19, R12 ; /* 0x0000001314137223 */
/* 0x020fe2000000000c */
/*05f0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0600*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0610*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0620*/ FFMA R8, R8, R24, R19 ; /* 0x0000001808087223 */
/* 0x004fc80000000013 */
/*0630*/ FFMA R8, R10, R9, R8 ; /* 0x000000090a087223 */
/* 0x000fc80000000008 */
/*0640*/ FFMA R8, R28, R21, R8 ; /* 0x000000151c087223 */
/* 0x000fc80000000008 */
/*0650*/ FFMA R24, R11, R26, R8 ; /* 0x0000001a0b187223 */
/* 0x000fe40000000008 */
/*0660*/ IMAD.WIDE R8, R0, 0x4, R16 ; /* 0x0000000400087825 */
/* 0x000fe200078e0210 */
/*0670*/ @P1 BRA 0x1f0 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*0680*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0690*/ @!P1 BRA 0x920 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06a0*/ IMAD.WIDE R16, R0, 0x4, R8 ; /* 0x0000000400107825 */
/* 0x000fe200078e0208 */
/*06b0*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe20008000f00 */
/*06c0*/ LDG.E R23, [R8.64] ; /* 0x0000000408177981 */
/* 0x0000a2000c1e1900 */
/*06d0*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fc60008000f00 */
/*06e0*/ IMAD.WIDE R12, R0.reuse, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x040fe400078e0210 */
/*06f0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0002e4000c1e1900 */
/*0700*/ IMAD.WIDE R10, R7, 0x4, R10 ; /* 0x00000004070a7825 */
/* 0x000fe400078e020a */
/*0710*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000964000c1e1900 */
/*0720*/ IMAD.WIDE R14, R0.reuse, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x040fe400078e020c */
/*0730*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x000ea8000c1e1900 */
/*0740*/ LDG.E R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000ee2000c1e1900 */
/*0750*/ IMAD.WIDE R18, R0, 0x4, R14 ; /* 0x0000000400127825 */
/* 0x000fc600078e020e */
/*0760*/ LDG.E R27, [R10.64+0x8] ; /* 0x000008040a1b7981 */
/* 0x000f66000c1e1900 */
/*0770*/ IMAD.WIDE R20, R0.reuse, 0x4, R18 ; /* 0x0000000400147825 */
/* 0x040fe200078e0212 */
/*0780*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*0790*/ LDG.E R29, [R10.64+0xc] ; /* 0x00000c040a1d7981 */
/* 0x000f62000c1e1900 */
/*07a0*/ IMAD.WIDE R8, R0, 0x4, R20 ; /* 0x0000000400087825 */
/* 0x001fc600078e0214 */
/*07b0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000168000c1e1900 */
/*07c0*/ LDG.E R28, [R10.64+0x10] ; /* 0x000010040a1c7981 */
/* 0x000f62000c1e1900 */
/*07d0*/ IMAD.WIDE R12, R0, 0x4, R8 ; /* 0x00000004000c7825 */
/* 0x010fc600078e0208 */
/*07e0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000f28000c1e1900 */
/*07f0*/ LDG.E R15, [R10.64+0x14] ; /* 0x000014040a0f7981 */
/* 0x002f28000c1e1900 */
/*0800*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000328000c1e1900 */
/*0810*/ LDG.E R19, [R10.64+0x1c] ; /* 0x00001c040a137981 */
/* 0x001f28000c1e1900 */
/*0820*/ LDG.E R8, [R10.64+0x18] ; /* 0x000018040a087981 */
/* 0x002f28000c1e1900 */
/*0830*/ LDG.E R9, [R12.64] ; /* 0x000000040c097981 */
/* 0x000f22000c1e1900 */
/*0840*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0850*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0860*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*0870*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0880*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0890*/ FFMA R22, R23, R22, R24 ; /* 0x0000001617167223 */
/* 0x004fc80000000018 */
/*08a0*/ FFMA R16, R16, R25, R22 ; /* 0x0000001910107223 */
/* 0x008fc80000000016 */
/*08b0*/ FFMA R16, R26, R27, R16 ; /* 0x0000001b1a107223 */
/* 0x020fc80000000010 */
/*08c0*/ FFMA R29, R14, R29, R16 ; /* 0x0000001d0e1d7223 */
/* 0x000fc80000000010 */
/*08d0*/ FFMA R18, R18, R28, R29 ; /* 0x0000001c12127223 */
/* 0x000fc8000000001d */
/*08e0*/ FFMA R15, R20, R15, R18 ; /* 0x0000000f140f7223 */
/* 0x010fc80000000012 */
/*08f0*/ FFMA R8, R17, R8, R15 ; /* 0x0000000811087223 */
/* 0x000fc8000000000f */
/*0900*/ FFMA R24, R9, R19, R8 ; /* 0x0000001309187223 */
/* 0x000fe40000000008 */
/*0910*/ IMAD.WIDE R8, R0, 0x4, R12 ; /* 0x0000000400087825 */
/* 0x000fc800078e020c */
/*0920*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0930*/ @!P0 BRA 0xad0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0940*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0950*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fe200078e0208 */
/*0960*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fe20008000f00 */
/*0970*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea8000c1e1900 */
/*0980*/ IMAD.WIDE R12, R7, 0x4, R12 ; /* 0x00000004070c7825 */
/* 0x000fc800078e020c */
/*0990*/ IMAD.WIDE R14, R0.reuse, 0x4, R10 ; /* 0x00000004000e7825 */
/* 0x040fe200078e020a */
/*09a0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000ee2000c1e1900 */
/*09c0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*09d0*/ LDG.E R19, [R12.64+0x4] ; /* 0x000004040c137981 */
/* 0x000ee8000c1e1900 */
/*09e0*/ LDG.E R21, [R14.64] ; /* 0x000000040e157981 */
/* 0x000f28000c1e1900 */
/*09f0*/ LDG.E R20, [R12.64+0x8] ; /* 0x000008040c147981 */
/* 0x000f28000c1e1900 */
/*0a00*/ LDG.E R22, [R12.64+0xc] ; /* 0x00000c040c167981 */
/* 0x000f68000c1e1900 */
/*0a10*/ LDG.E R23, [R16.64] ; /* 0x0000000410177981 */
/* 0x000f62000c1e1900 */
/*0a20*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a30*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a40*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a50*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a60*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a70*/ FFMA R18, R9, R18, R24 ; /* 0x0000001209127223 */
/* 0x004fc80000000018 */
/*0a80*/ FFMA R18, R11, R19, R18 ; /* 0x000000130b127223 */
/* 0x008fe40000000012 */
/*0a90*/ IMAD.WIDE R8, R0, 0x4, R16 ; /* 0x0000000400087825 */
/* 0x000fc800078e0210 */
/*0aa0*/ FFMA R18, R21, R20, R18 ; /* 0x0000001415127223 */
/* 0x010fc80000000012 */
/*0ab0*/ FFMA R24, R23, R22, R18 ; /* 0x0000001617187223 */
/* 0x020fe20000000012 */
/*0ac0*/ @P0 BRA 0x940 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0ad0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0ae0*/ @!P0 BRA 0xbd0 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0af0*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b00*/ IMAD R6, R3, c[0x0][0x180], R4 ; /* 0x0000600003067a24 */
/* 0x000fe400078e0204 */
/*0b10*/ IMAD R4, R4, c[0x0][0x180], R2 ; /* 0x0000600004047a24 */
/* 0x000fce00078e0202 */
/*0b20*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b30*/ IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fca00078e0209 */
/*0b40*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a8000c1e1900 */
/*0b50*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002a2000c1e1900 */
/*0b60*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0b70*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0b80*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fe200078e0208 */
/*0b90*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0ba0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0bb0*/ FFMA R24, R11, R4, R24 ; /* 0x000000040b187223 */
/* 0x004fcc0000000018 */
/*0bc0*/ @P0 BRA 0xb40 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0bd0*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fe20000000f00 */
/*0be0*/ IMAD R2, R3, c[0x0][0x17c], R2 ; /* 0x00005f0003027a24 */
/* 0x000fc800078e0202 */
/*0bf0*/ IMAD.WIDE R2, R2, R5, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0205 */
/*0c00*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0c10*/ FMUL R5, R0, c[0x0][0x188] ; /* 0x0000620000057a20 */
/* 0x004fc80000400000 */
/*0c20*/ FFMA R5, R24, c[0x0][0x184], R5 ; /* 0x0000610018057a23 */
/* 0x000fca0000000005 */
/*0c30*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0c40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c50*/ BRA 0xc50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12sgemm_kernelPKfS0_Pfiiiff
.globl _Z12sgemm_kernelPKfS0_Pfiiiff
.p2align 8
.type _Z12sgemm_kernelPKfS0_Pfiiiff,@function
_Z12sgemm_kernelPKfS0_Pfiiiff:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x3c
s_load_b32 s2, s[0:1], 0x20
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_mul_lo_u32 v2, v1, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v0
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x24
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, s1, v2
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v2, s0, v6
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12sgemm_kernelPKfS0_Pfiiiff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12sgemm_kernelPKfS0_Pfiiiff, .Lfunc_end0-_Z12sgemm_kernelPKfS0_Pfiiiff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12sgemm_kernelPKfS0_Pfiiiff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12sgemm_kernelPKfS0_Pfiiiff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001167a8_00000000-6_sgemm_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z12sgemm_kernelPKfS0_PfiiiffPKfS0_Pfiiiff
.type _Z43__device_stub__Z12sgemm_kernelPKfS0_PfiiiffPKfS0_Pfiiiff, @function
_Z43__device_stub__Z12sgemm_kernelPKfS0_PfiiiffPKfS0_Pfiiiff:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm1, 4(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
leaq 4(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12sgemm_kernelPKfS0_Pfiiiff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z12sgemm_kernelPKfS0_PfiiiffPKfS0_Pfiiiff, .-_Z43__device_stub__Z12sgemm_kernelPKfS0_PfiiiffPKfS0_Pfiiiff
.globl _Z12sgemm_kernelPKfS0_Pfiiiff
.type _Z12sgemm_kernelPKfS0_Pfiiiff, @function
_Z12sgemm_kernelPKfS0_Pfiiiff:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z12sgemm_kernelPKfS0_PfiiiffPKfS0_Pfiiiff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12sgemm_kernelPKfS0_Pfiiiff, .-_Z12sgemm_kernelPKfS0_Pfiiiff
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12sgemm_kernelPKfS0_Pfiiiff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12sgemm_kernelPKfS0_Pfiiiff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sgemm_kernel.hip"
.globl _Z27__device_stub__sgemm_kernelPKfS0_Pfiiiff # -- Begin function _Z27__device_stub__sgemm_kernelPKfS0_Pfiiiff
.p2align 4, 0x90
.type _Z27__device_stub__sgemm_kernelPKfS0_Pfiiiff,@function
_Z27__device_stub__sgemm_kernelPKfS0_Pfiiiff: # @_Z27__device_stub__sgemm_kernelPKfS0_Pfiiiff
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm1, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12sgemm_kernelPKfS0_Pfiiiff, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z27__device_stub__sgemm_kernelPKfS0_Pfiiiff, .Lfunc_end0-_Z27__device_stub__sgemm_kernelPKfS0_Pfiiiff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12sgemm_kernelPKfS0_Pfiiiff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12sgemm_kernelPKfS0_Pfiiiff,@object # @_Z12sgemm_kernelPKfS0_Pfiiiff
.section .rodata,"a",@progbits
.globl _Z12sgemm_kernelPKfS0_Pfiiiff
.p2align 3, 0x0
_Z12sgemm_kernelPKfS0_Pfiiiff:
.quad _Z27__device_stub__sgemm_kernelPKfS0_Pfiiiff
.size _Z12sgemm_kernelPKfS0_Pfiiiff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12sgemm_kernelPKfS0_Pfiiiff"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__sgemm_kernelPKfS0_Pfiiiff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12sgemm_kernelPKfS0_Pfiiiff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void find_all_sums_hub_kernel(int* hub, int nhub, float *node_weight, int *neighbor, int *neighbor_start, float *neighbor_accum_weight_result, float *sum_weight_result){
int x = blockIdx.x * blockDim.x + threadIdx.x;
if (x < nhub) {
int nid = hub[x];
float sum = 0.0;
for (int eid = neighbor_start[nid]; eid < neighbor_start[nid+1]; eid++) { // this eid is just index of the neighbor in the neighbor array
sum += node_weight[neighbor[eid]];
neighbor_accum_weight_result[eid] = sum;
}
sum_weight_result[nid] = sum;
}
} | code for sm_80
Function : _Z24find_all_sums_hub_kernelPiiPfS_S_S0_S0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R7, R7, c[0x0][0x0], R0 ; /* 0x0000000007077a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x168], PT ; /* 0x00005a0007007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R0, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff007435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R6, R7, R0, c[0x0][0x160] ; /* 0x0000580007067625 */
/* 0x000fcc00078e0200 */
/*0090*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ IMAD.WIDE R2, R7, R0, c[0x0][0x180] ; /* 0x0000600007027625 */
/* 0x004fca00078e0200 */
/*00b0*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ LDG.E R5, [R2.64+0x4] ; /* 0x0000040402057981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ SHF.R.S32.HI R10, RZ, 0x1f, R7 ; /* 0x0000001fff0a7819 */
/* 0x000fe20000011407 */
/*00e0*/ BSSY B0, 0x2a0 ; /* 0x000001b000007945 */
/* 0x000fe20003800000 */
/*00f0*/ LEA R4, P1, R7.reuse, c[0x0][0x190], 0x2 ; /* 0x0000640007047a11 */
/* 0x040fe200078210ff */
/*0100*/ IMAD.MOV.U32 R13, RZ, RZ, RZ ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e00ff */
/*0110*/ ISETP.GE.AND P0, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x004fe40003f06270 */
/*0120*/ LEA.HI.X R5, R7, c[0x0][0x194], R10, 0x2, P1 ; /* 0x0000650007057a11 */
/* 0x000fd600008f140a */
/*0130*/ @P0 BRA 0x290 ; /* 0x0000015000000947 */
/* 0x000fea0003800000 */
/*0140*/ MOV R11, R8 ; /* 0x00000008000b7202 */
/* 0x000fe20000000f00 */
/*0150*/ IMAD.MOV.U32 R13, RZ, RZ, RZ ; /* 0x000000ffff0d7224 */
/* 0x000fc800078e00ff */
/*0160*/ IMAD.WIDE R6, R11, R0, c[0x0][0x188] ; /* 0x000062000b067625 */
/* 0x000fc800078e0200 */
/*0170*/ IMAD.WIDE R8, R11, R0, c[0x0][0x178] ; /* 0x00005e000b087625 */
/* 0x000fe200078e0200 */
/*0180*/ MOV R15, R7 ; /* 0x00000007000f7202 */
/* 0x000fc60000000f00 */
/*0190*/ IMAD.MOV.U32 R12, RZ, RZ, R6 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0006 */
/*01a0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea4000c1e1900 */
/*01b0*/ IMAD.WIDE R6, R7, R0, c[0x0][0x170] ; /* 0x00005c0007067625 */
/* 0x004fcc00078e0200 */
/*01c0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x0000a4000c1e1900 */
/*01d0*/ IMAD.MOV.U32 R7, RZ, RZ, R15 ; /* 0x000000ffff077224 */
/* 0x001fe400078e000f */
/*01e0*/ FADD R13, R6, R13 ; /* 0x0000000d060d7221 */
/* 0x004fe20000000000 */
/*01f0*/ MOV R6, R12 ; /* 0x0000000c00067202 */
/* 0x000fca0000000f00 */
/*0200*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0001e8000c101904 */
/*0210*/ LDG.E R10, [R2.64+0x4] ; /* 0x00000404020a7981 */
/* 0x000ea2000c1e1900 */
/*0220*/ IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b7810 */
/* 0x000fe40007ffe0ff */
/*0230*/ IADD3 R12, P1, R12, 0x4, RZ ; /* 0x000000040c0c7810 */
/* 0x000fe40007f3e0ff */
/*0240*/ IADD3 R8, P2, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fc60007f5e0ff */
/*0250*/ IMAD.X R15, RZ, RZ, R15, P1 ; /* 0x000000ffff0f7224 */
/* 0x000fe200008e060f */
/*0260*/ IADD3.X R9, RZ, R9, RZ, P2, !PT ; /* 0x00000009ff097210 */
/* 0x000fe400017fe4ff */
/*0270*/ ISETP.GE.AND P0, PT, R11, R10, PT ; /* 0x0000000a0b00720c */
/* 0x004fda0003f06270 */
/*0280*/ @!P0 BRA 0x1a0 ; /* 0xffffff1000008947 */
/* 0x001fea000383ffff */
/*0290*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02a0*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x000fe2000c101904 */
/*02b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02c0*/ BRA 0x2c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void find_all_sums_hub_kernel(int* hub, int nhub, float *node_weight, int *neighbor, int *neighbor_start, float *neighbor_accum_weight_result, float *sum_weight_result){
int x = blockIdx.x * blockDim.x + threadIdx.x;
if (x < nhub) {
int nid = hub[x];
float sum = 0.0;
for (int eid = neighbor_start[nid]; eid < neighbor_start[nid+1]; eid++) { // this eid is just index of the neighbor in the neighbor array
sum += node_weight[neighbor[eid]];
neighbor_accum_weight_result[eid] = sum;
}
sum_weight_result[nid] = sum;
}
} | .file "tmpxft_000c06c5_00000000-6_find_all_sums_hub_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z57__device_stub__Z24find_all_sums_hub_kernelPiiPfS_S_S0_S0_PiiPfS_S_S0_S0_
.type _Z57__device_stub__Z24find_all_sums_hub_kernelPiiPfS_S_S0_S0_PiiPfS_S_S0_S0_, @function
_Z57__device_stub__Z24find_all_sums_hub_kernelPiiPfS_S_S0_S0_PiiPfS_S_S0_S0_:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 56(%rsp)
movl %esi, 52(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 52(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z24find_all_sums_hub_kernelPiiPfS_S_S0_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z57__device_stub__Z24find_all_sums_hub_kernelPiiPfS_S_S0_S0_PiiPfS_S_S0_S0_, .-_Z57__device_stub__Z24find_all_sums_hub_kernelPiiPfS_S_S0_S0_PiiPfS_S_S0_S0_
.globl _Z24find_all_sums_hub_kernelPiiPfS_S_S0_S0_
.type _Z24find_all_sums_hub_kernelPiiPfS_S_S0_S0_, @function
_Z24find_all_sums_hub_kernelPiiPfS_S_S0_S0_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z57__device_stub__Z24find_all_sums_hub_kernelPiiPfS_S_S0_S0_PiiPfS_S_S0_S0_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z24find_all_sums_hub_kernelPiiPfS_S_S0_S0_, .-_Z24find_all_sums_hub_kernelPiiPfS_S_S0_S0_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24find_all_sums_hub_kernelPiiPfS_S_S0_S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24find_all_sums_hub_kernelPiiPfS_S_S0_S0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void find_all_sums_hub_kernel(int* hub, int nhub, float *node_weight, int *neighbor, int *neighbor_start, float *neighbor_accum_weight_result, float *sum_weight_result){
int x = blockIdx.x * blockDim.x + threadIdx.x;
if (x < nhub) {
int nid = hub[x];
float sum = 0.0;
for (int eid = neighbor_start[nid]; eid < neighbor_start[nid+1]; eid++) { // this eid is just index of the neighbor in the neighbor array
sum += node_weight[neighbor[eid]];
neighbor_accum_weight_result[eid] = sum;
}
sum_weight_result[nid] = sum;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void find_all_sums_hub_kernel(int* hub, int nhub, float *node_weight, int *neighbor, int *neighbor_start, float *neighbor_accum_weight_result, float *sum_weight_result){
int x = blockIdx.x * blockDim.x + threadIdx.x;
if (x < nhub) {
int nid = hub[x];
float sum = 0.0;
for (int eid = neighbor_start[nid]; eid < neighbor_start[nid+1]; eid++) { // this eid is just index of the neighbor in the neighbor array
sum += node_weight[neighbor[eid]];
neighbor_accum_weight_result[eid] = sum;
}
sum_weight_result[nid] = sum;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void find_all_sums_hub_kernel(int* hub, int nhub, float *node_weight, int *neighbor, int *neighbor_start, float *neighbor_accum_weight_result, float *sum_weight_result){
int x = blockIdx.x * blockDim.x + threadIdx.x;
if (x < nhub) {
int nid = hub[x];
float sum = 0.0;
for (int eid = neighbor_start[nid]; eid < neighbor_start[nid+1]; eid++) { // this eid is just index of the neighbor in the neighbor array
sum += node_weight[neighbor[eid]];
neighbor_accum_weight_result[eid] = sum;
}
sum_weight_result[nid] = sum;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24find_all_sums_hub_kernelPiiPfS_S_S0_S0_
.globl _Z24find_all_sums_hub_kernelPiiPfS_S_S0_S0_
.p2align 8
.type _Z24find_all_sums_hub_kernelPiiPfS_S_S0_S0_,@function
_Z24find_all_sums_hub_kernelPiiPfS_S_S0_S0_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x44
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_6
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x20
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v8, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_mov_b32 s3, exec_lo
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e64 v2, v3
s_cbranch_execz .LBB0_5
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x10
s_load_b64 s[8:9], s[0:1], 0x28
v_ashrrev_i32_e32 v5, 31, v2
v_mov_b32_e32 v4, v2
v_mov_b32_e32 v8, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v7, vcc_lo
v_add_co_u32 v6, vcc_lo, s8, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
s_mov_b32 s6, 0
.p2align 6
.LBB0_3:
global_load_b32 v9, v[4:5], off
v_add_nc_u32_e32 v2, 1, v2
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_add_co_u32 v9, vcc_lo, s4, v9
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
global_load_b32 v9, v[9:10], off
v_cmp_ge_i32_e32 vcc_lo, v2, v3
s_or_b32 s6, vcc_lo, s6
s_waitcnt vmcnt(0)
v_add_f32_e32 v8, v8, v9
global_store_b32 v[6:7], v8, off
v_add_co_u32 v6, s2, v6, 4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v7, s2, 0, v7, s2
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s6
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x30
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v8, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24find_all_sums_hub_kernelPiiPfS_S_S0_S0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24find_all_sums_hub_kernelPiiPfS_S_S0_S0_, .Lfunc_end0-_Z24find_all_sums_hub_kernelPiiPfS_S_S0_S0_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24find_all_sums_hub_kernelPiiPfS_S_S0_S0_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z24find_all_sums_hub_kernelPiiPfS_S_S0_S0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void find_all_sums_hub_kernel(int* hub, int nhub, float *node_weight, int *neighbor, int *neighbor_start, float *neighbor_accum_weight_result, float *sum_weight_result){
int x = blockIdx.x * blockDim.x + threadIdx.x;
if (x < nhub) {
int nid = hub[x];
float sum = 0.0;
for (int eid = neighbor_start[nid]; eid < neighbor_start[nid+1]; eid++) { // this eid is just index of the neighbor in the neighbor array
sum += node_weight[neighbor[eid]];
neighbor_accum_weight_result[eid] = sum;
}
sum_weight_result[nid] = sum;
}
} | .text
.file "find_all_sums_hub_kernel.hip"
.globl _Z39__device_stub__find_all_sums_hub_kernelPiiPfS_S_S0_S0_ # -- Begin function _Z39__device_stub__find_all_sums_hub_kernelPiiPfS_S_S0_S0_
.p2align 4, 0x90
.type _Z39__device_stub__find_all_sums_hub_kernelPiiPfS_S_S0_S0_,@function
_Z39__device_stub__find_all_sums_hub_kernelPiiPfS_S_S0_S0_: # @_Z39__device_stub__find_all_sums_hub_kernelPiiPfS_S_S0_S0_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 4(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z24find_all_sums_hub_kernelPiiPfS_S_S0_S0_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z39__device_stub__find_all_sums_hub_kernelPiiPfS_S_S0_S0_, .Lfunc_end0-_Z39__device_stub__find_all_sums_hub_kernelPiiPfS_S_S0_S0_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24find_all_sums_hub_kernelPiiPfS_S_S0_S0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24find_all_sums_hub_kernelPiiPfS_S_S0_S0_,@object # @_Z24find_all_sums_hub_kernelPiiPfS_S_S0_S0_
.section .rodata,"a",@progbits
.globl _Z24find_all_sums_hub_kernelPiiPfS_S_S0_S0_
.p2align 3, 0x0
_Z24find_all_sums_hub_kernelPiiPfS_S_S0_S0_:
.quad _Z39__device_stub__find_all_sums_hub_kernelPiiPfS_S_S0_S0_
.size _Z24find_all_sums_hub_kernelPiiPfS_S_S0_S0_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24find_all_sums_hub_kernelPiiPfS_S_S0_S0_"
.size .L__unnamed_1, 44
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__find_all_sums_hub_kernelPiiPfS_S_S0_S0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24find_all_sums_hub_kernelPiiPfS_S_S0_S0_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z24find_all_sums_hub_kernelPiiPfS_S_S0_S0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R7, R7, c[0x0][0x0], R0 ; /* 0x0000000007077a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x168], PT ; /* 0x00005a0007007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R0, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff007435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R6, R7, R0, c[0x0][0x160] ; /* 0x0000580007067625 */
/* 0x000fcc00078e0200 */
/*0090*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ IMAD.WIDE R2, R7, R0, c[0x0][0x180] ; /* 0x0000600007027625 */
/* 0x004fca00078e0200 */
/*00b0*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ LDG.E R5, [R2.64+0x4] ; /* 0x0000040402057981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ SHF.R.S32.HI R10, RZ, 0x1f, R7 ; /* 0x0000001fff0a7819 */
/* 0x000fe20000011407 */
/*00e0*/ BSSY B0, 0x2a0 ; /* 0x000001b000007945 */
/* 0x000fe20003800000 */
/*00f0*/ LEA R4, P1, R7.reuse, c[0x0][0x190], 0x2 ; /* 0x0000640007047a11 */
/* 0x040fe200078210ff */
/*0100*/ IMAD.MOV.U32 R13, RZ, RZ, RZ ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e00ff */
/*0110*/ ISETP.GE.AND P0, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x004fe40003f06270 */
/*0120*/ LEA.HI.X R5, R7, c[0x0][0x194], R10, 0x2, P1 ; /* 0x0000650007057a11 */
/* 0x000fd600008f140a */
/*0130*/ @P0 BRA 0x290 ; /* 0x0000015000000947 */
/* 0x000fea0003800000 */
/*0140*/ MOV R11, R8 ; /* 0x00000008000b7202 */
/* 0x000fe20000000f00 */
/*0150*/ IMAD.MOV.U32 R13, RZ, RZ, RZ ; /* 0x000000ffff0d7224 */
/* 0x000fc800078e00ff */
/*0160*/ IMAD.WIDE R6, R11, R0, c[0x0][0x188] ; /* 0x000062000b067625 */
/* 0x000fc800078e0200 */
/*0170*/ IMAD.WIDE R8, R11, R0, c[0x0][0x178] ; /* 0x00005e000b087625 */
/* 0x000fe200078e0200 */
/*0180*/ MOV R15, R7 ; /* 0x00000007000f7202 */
/* 0x000fc60000000f00 */
/*0190*/ IMAD.MOV.U32 R12, RZ, RZ, R6 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0006 */
/*01a0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea4000c1e1900 */
/*01b0*/ IMAD.WIDE R6, R7, R0, c[0x0][0x170] ; /* 0x00005c0007067625 */
/* 0x004fcc00078e0200 */
/*01c0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x0000a4000c1e1900 */
/*01d0*/ IMAD.MOV.U32 R7, RZ, RZ, R15 ; /* 0x000000ffff077224 */
/* 0x001fe400078e000f */
/*01e0*/ FADD R13, R6, R13 ; /* 0x0000000d060d7221 */
/* 0x004fe20000000000 */
/*01f0*/ MOV R6, R12 ; /* 0x0000000c00067202 */
/* 0x000fca0000000f00 */
/*0200*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0001e8000c101904 */
/*0210*/ LDG.E R10, [R2.64+0x4] ; /* 0x00000404020a7981 */
/* 0x000ea2000c1e1900 */
/*0220*/ IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b7810 */
/* 0x000fe40007ffe0ff */
/*0230*/ IADD3 R12, P1, R12, 0x4, RZ ; /* 0x000000040c0c7810 */
/* 0x000fe40007f3e0ff */
/*0240*/ IADD3 R8, P2, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fc60007f5e0ff */
/*0250*/ IMAD.X R15, RZ, RZ, R15, P1 ; /* 0x000000ffff0f7224 */
/* 0x000fe200008e060f */
/*0260*/ IADD3.X R9, RZ, R9, RZ, P2, !PT ; /* 0x00000009ff097210 */
/* 0x000fe400017fe4ff */
/*0270*/ ISETP.GE.AND P0, PT, R11, R10, PT ; /* 0x0000000a0b00720c */
/* 0x004fda0003f06270 */
/*0280*/ @!P0 BRA 0x1a0 ; /* 0xffffff1000008947 */
/* 0x001fea000383ffff */
/*0290*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02a0*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x000fe2000c101904 */
/*02b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02c0*/ BRA 0x2c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24find_all_sums_hub_kernelPiiPfS_S_S0_S0_
.globl _Z24find_all_sums_hub_kernelPiiPfS_S_S0_S0_
.p2align 8
.type _Z24find_all_sums_hub_kernelPiiPfS_S_S0_S0_,@function
_Z24find_all_sums_hub_kernelPiiPfS_S_S0_S0_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x44
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_6
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x20
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v8, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_mov_b32 s3, exec_lo
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e64 v2, v3
s_cbranch_execz .LBB0_5
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x10
s_load_b64 s[8:9], s[0:1], 0x28
v_ashrrev_i32_e32 v5, 31, v2
v_mov_b32_e32 v4, v2
v_mov_b32_e32 v8, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v7, vcc_lo
v_add_co_u32 v6, vcc_lo, s8, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
s_mov_b32 s6, 0
.p2align 6
.LBB0_3:
global_load_b32 v9, v[4:5], off
v_add_nc_u32_e32 v2, 1, v2
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_add_co_u32 v9, vcc_lo, s4, v9
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
global_load_b32 v9, v[9:10], off
v_cmp_ge_i32_e32 vcc_lo, v2, v3
s_or_b32 s6, vcc_lo, s6
s_waitcnt vmcnt(0)
v_add_f32_e32 v8, v8, v9
global_store_b32 v[6:7], v8, off
v_add_co_u32 v6, s2, v6, 4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v7, s2, 0, v7, s2
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s6
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x30
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v8, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24find_all_sums_hub_kernelPiiPfS_S_S0_S0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24find_all_sums_hub_kernelPiiPfS_S_S0_S0_, .Lfunc_end0-_Z24find_all_sums_hub_kernelPiiPfS_S_S0_S0_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24find_all_sums_hub_kernelPiiPfS_S_S0_S0_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z24find_all_sums_hub_kernelPiiPfS_S_S0_S0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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