system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
// Define your kernels in this file you may use more than one kernel if you
// need to
#define BLOCK_SIZE 512
#define NUM_BINS 40
#define SPACE_INDEX 36
#define PERIOD_INDEX 37
#define COMMA_INDEX 38
#define NEW_LINE 39
// INSERT KERNEL(S) HERE
/*
* This function calculates the frequency of each character in the character buffer. It does so by creating local
* histograms and finally merging them with global histogram.
*/
__global__ void calculateFrequency(char* input, unsigned int* bins, unsigned int num_elements)
{
__shared__ unsigned int private_histogram[NUM_BINS];
//Computation of private histogram
int i = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
if (threadIdx.x < NUM_BINS) {
private_histogram[threadIdx.x] = 0;
}
__syncthreads();
while(i < num_elements) {
if(input[i] >= 97 && input[i] <= 122) { //if the character is small alphabet from a to z
atomicAdd(&private_histogram[input[i]-97], 1);
} else if(input[i] >= 48 && input[i] <= 57) { //if the character is a digit from 0 to 9
atomicAdd(&private_histogram[input[i]-22], 1);
} else if(input[i] == 32) { //if the character is a space
atomicAdd(&private_histogram[SPACE_INDEX], 1);
} else if(input[i] == 46) { //if the character is a fullstop
atomicAdd(&private_histogram[PERIOD_INDEX], 1);
} else if(input[i] == 44) { //if the character is a comma
atomicAdd(&private_histogram[COMMA_INDEX], 1);
} else if(input[i] == 10) { //if the character is a new line character
atomicAdd(&private_histogram[NEW_LINE], 1);
}
i += stride;
}
__syncthreads();
if (threadIdx.x < NUM_BINS) {
atomicAdd(&bins[threadIdx.x], private_histogram[threadIdx.x]);
}
__syncthreads();
}
/*
* This function reads input character and converts that character into its corresponding string code from the char**
* array passed. The code is written to output array with each character code taking as much space as is the length
* of the code.
*/
__global__ void encodeDataKernel(char* input, unsigned int num_elements, char** characterCodes, int* codeLengths, int maxLength, char* output) {
//__shared__ char* sharedOutput[outSize];
int i = blockIdx.x * blockDim.x + threadIdx.x;
char ch;
char* code;
int codeLen = 0;
if(threadIdx.x < num_elements) {
ch = input[threadIdx.x];
if(ch >= 97 && ch <= 122) { //if the character is small alphabet from a to z
code = characterCodes[ch - 97];
codeLen = codeLengths[ch - 97];
} else if(ch >= 48 && ch <= 57) { //if the character is a digit from 0 to 9
code = characterCodes[ch - 22];
codeLen = codeLengths[ch - 22];
} else if(ch == 32) { //if the character is a space
code = characterCodes[SPACE_INDEX];
codeLen = codeLengths[SPACE_INDEX];
} else if(ch == 46) { //if the character is a fullstop
code = characterCodes[PERIOD_INDEX];
codeLen = codeLengths[PERIOD_INDEX];
} else if(ch == 44) { //if the character is a comma
code = characterCodes[COMMA_INDEX];
codeLen = codeLengths[COMMA_INDEX];
} else if(ch == 10) { //if the character is a new line character
code = characterCodes[NEW_LINE];
codeLen = codeLengths[NEW_LINE];
}
}
__syncthreads();
int j = i * maxLength, k, m;
for(m = 0, k = 0; m < maxLength && k < codeLen; j++, k++, m++) {
//sharedOutput[j] = code[k];
output[j] = code[k];
}
if(k == codeLen && m < maxLength) {
for(; m < maxLength; m++, j++) {
//sharedOutput[j] = '2'; //padding with '2'
output[j] = '2'; //padding with '2'
}
}
__syncthreads();
}
/******************************************************************************
Setup and invoke your kernel(s) in this function. You may also allocate more
GPU memory if you need to
*******************************************************************************/
void histogram(char* input, unsigned int* bins, unsigned int num_elements)
{
// INSERT CODE HERE
dim3 dimGrid((num_elements - 1)/BLOCK_SIZE + 1, 1, 1);
dim3 dimBlock(BLOCK_SIZE, 1, 1);
calculateFrequency<<<dimGrid, dimBlock>>>(input, bins, num_elements);
}
void encodeData(char* input, unsigned int num_elements, char** characterCodes, int* codeLengths, int maxLength, char* output) {
dim3 dimGrid((num_elements - 1)/BLOCK_SIZE + 1, 1, 1);
dim3 dimBlock(BLOCK_SIZE, 1, 1);
encodeDataKernel<<<dimGrid, dimBlock>>>(input, num_elements, characterCodes, codeLengths, maxLength, output);
} | .file "tmpxft_00106e70_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z18calculateFrequencyPcPjjPcPjj
.type _Z41__device_stub__Z18calculateFrequencyPcPjjPcPjj, @function
_Z41__device_stub__Z18calculateFrequencyPcPjjPcPjj:
.LFB2053:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18calculateFrequencyPcPjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z41__device_stub__Z18calculateFrequencyPcPjjPcPjj, .-_Z41__device_stub__Z18calculateFrequencyPcPjjPcPjj
.globl _Z18calculateFrequencyPcPjj
.type _Z18calculateFrequencyPcPjj, @function
_Z18calculateFrequencyPcPjj:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z18calculateFrequencyPcPjjPcPjj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z18calculateFrequencyPcPjj, .-_Z18calculateFrequencyPcPjj
.globl _Z9histogramPcPjj
.type _Z9histogramPcPjj, @function
_Z9histogramPcPjj:
.LFB2027:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movq %rsi, %r12
movl %edx, %ebx
leal -1(%rdx), %eax
shrl $9, %eax
addl $1, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl %ebx, %edx
movq %r12, %rsi
movq %rbp, %rdi
call _Z41__device_stub__Z18calculateFrequencyPcPjjPcPjj
jmp .L11
.cfi_endproc
.LFE2027:
.size _Z9histogramPcPjj, .-_Z9histogramPcPjj
.globl _Z45__device_stub__Z16encodeDataKernelPcjPS_PiiS_PcjPS_PiiS_
.type _Z45__device_stub__Z16encodeDataKernelPcjPS_PiiS_PcjPS_PiiS_, @function
_Z45__device_stub__Z16encodeDataKernelPcjPS_PiiS_PcjPS_PiiS_:
.LFB2055:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 32(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16encodeDataKernelPcjPS_PiiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z45__device_stub__Z16encodeDataKernelPcjPS_PiiS_PcjPS_PiiS_, .-_Z45__device_stub__Z16encodeDataKernelPcjPS_PiiS_PcjPS_PiiS_
.globl _Z16encodeDataKernelPcjPS_PiiS_
.type _Z16encodeDataKernelPcjPS_PiiS_, @function
_Z16encodeDataKernelPcjPS_PiiS_:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z16encodeDataKernelPcjPS_PiiS_PcjPS_PiiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z16encodeDataKernelPcjPS_PiiS_, .-_Z16encodeDataKernelPcjPS_PiiS_
.globl _Z10encodeDataPcjPS_PiiS_
.type _Z10encodeDataPcjPS_PiiS_, @function
_Z10encodeDataPcjPS_PiiS_:
.LFB2028:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbp
movl %esi, %ebx
movq %rdx, %r12
movq %rcx, %r13
movl %r8d, %r14d
movq %r9, %r15
leal -1(%rsi), %eax
shrl $9, %eax
addl $1, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L23:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movq %r15, %r9
movl %r14d, %r8d
movq %r13, %rcx
movq %r12, %rdx
movl %ebx, %esi
movq %rbp, %rdi
call _Z45__device_stub__Z16encodeDataKernelPcjPS_PiiS_PcjPS_PiiS_
jmp .L23
.cfi_endproc
.LFE2028:
.size _Z10encodeDataPcjPS_PiiS_, .-_Z10encodeDataPcjPS_PiiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z16encodeDataKernelPcjPS_PiiS_"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z18calculateFrequencyPcPjj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16encodeDataKernelPcjPS_PiiS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z18calculateFrequencyPcPjj(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
// Define your kernels in this file you may use more than one kernel if you
// need to
#define BLOCK_SIZE 512
#define NUM_BINS 40
#define SPACE_INDEX 36
#define PERIOD_INDEX 37
#define COMMA_INDEX 38
#define NEW_LINE 39
// INSERT KERNEL(S) HERE
/*
* This function calculates the frequency of each character in the character buffer. It does so by creating local
* histograms and finally merging them with global histogram.
*/
__global__ void calculateFrequency(char* input, unsigned int* bins, unsigned int num_elements)
{
__shared__ unsigned int private_histogram[NUM_BINS];
//Computation of private histogram
int i = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
if (threadIdx.x < NUM_BINS) {
private_histogram[threadIdx.x] = 0;
}
__syncthreads();
while(i < num_elements) {
if(input[i] >= 97 && input[i] <= 122) { //if the character is small alphabet from a to z
atomicAdd(&private_histogram[input[i]-97], 1);
} else if(input[i] >= 48 && input[i] <= 57) { //if the character is a digit from 0 to 9
atomicAdd(&private_histogram[input[i]-22], 1);
} else if(input[i] == 32) { //if the character is a space
atomicAdd(&private_histogram[SPACE_INDEX], 1);
} else if(input[i] == 46) { //if the character is a fullstop
atomicAdd(&private_histogram[PERIOD_INDEX], 1);
} else if(input[i] == 44) { //if the character is a comma
atomicAdd(&private_histogram[COMMA_INDEX], 1);
} else if(input[i] == 10) { //if the character is a new line character
atomicAdd(&private_histogram[NEW_LINE], 1);
}
i += stride;
}
__syncthreads();
if (threadIdx.x < NUM_BINS) {
atomicAdd(&bins[threadIdx.x], private_histogram[threadIdx.x]);
}
__syncthreads();
}
/*
* This function reads input character and converts that character into its corresponding string code from the char**
* array passed. The code is written to output array with each character code taking as much space as is the length
* of the code.
*/
__global__ void encodeDataKernel(char* input, unsigned int num_elements, char** characterCodes, int* codeLengths, int maxLength, char* output) {
//__shared__ char* sharedOutput[outSize];
int i = blockIdx.x * blockDim.x + threadIdx.x;
char ch;
char* code;
int codeLen = 0;
if(threadIdx.x < num_elements) {
ch = input[threadIdx.x];
if(ch >= 97 && ch <= 122) { //if the character is small alphabet from a to z
code = characterCodes[ch - 97];
codeLen = codeLengths[ch - 97];
} else if(ch >= 48 && ch <= 57) { //if the character is a digit from 0 to 9
code = characterCodes[ch - 22];
codeLen = codeLengths[ch - 22];
} else if(ch == 32) { //if the character is a space
code = characterCodes[SPACE_INDEX];
codeLen = codeLengths[SPACE_INDEX];
} else if(ch == 46) { //if the character is a fullstop
code = characterCodes[PERIOD_INDEX];
codeLen = codeLengths[PERIOD_INDEX];
} else if(ch == 44) { //if the character is a comma
code = characterCodes[COMMA_INDEX];
codeLen = codeLengths[COMMA_INDEX];
} else if(ch == 10) { //if the character is a new line character
code = characterCodes[NEW_LINE];
codeLen = codeLengths[NEW_LINE];
}
}
__syncthreads();
int j = i * maxLength, k, m;
for(m = 0, k = 0; m < maxLength && k < codeLen; j++, k++, m++) {
//sharedOutput[j] = code[k];
output[j] = code[k];
}
if(k == codeLen && m < maxLength) {
for(; m < maxLength; m++, j++) {
//sharedOutput[j] = '2'; //padding with '2'
output[j] = '2'; //padding with '2'
}
}
__syncthreads();
}
/******************************************************************************
Setup and invoke your kernel(s) in this function. You may also allocate more
GPU memory if you need to
*******************************************************************************/
void histogram(char* input, unsigned int* bins, unsigned int num_elements)
{
// INSERT CODE HERE
dim3 dimGrid((num_elements - 1)/BLOCK_SIZE + 1, 1, 1);
dim3 dimBlock(BLOCK_SIZE, 1, 1);
calculateFrequency<<<dimGrid, dimBlock>>>(input, bins, num_elements);
}
void encodeData(char* input, unsigned int num_elements, char** characterCodes, int* codeLengths, int maxLength, char* output) {
dim3 dimGrid((num_elements - 1)/BLOCK_SIZE + 1, 1, 1);
dim3 dimBlock(BLOCK_SIZE, 1, 1);
encodeDataKernel<<<dimGrid, dimBlock>>>(input, num_elements, characterCodes, codeLengths, maxLength, output);
} | #include <hip/hip_runtime.h>
/******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
// Define your kernels in this file you may use more than one kernel if you
// need to
#define BLOCK_SIZE 512
#define NUM_BINS 40
#define SPACE_INDEX 36
#define PERIOD_INDEX 37
#define COMMA_INDEX 38
#define NEW_LINE 39
// INSERT KERNEL(S) HERE
/*
* This function calculates the frequency of each character in the character buffer. It does so by creating local
* histograms and finally merging them with global histogram.
*/
__global__ void calculateFrequency(char* input, unsigned int* bins, unsigned int num_elements)
{
__shared__ unsigned int private_histogram[NUM_BINS];
//Computation of private histogram
int i = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
if (threadIdx.x < NUM_BINS) {
private_histogram[threadIdx.x] = 0;
}
__syncthreads();
while(i < num_elements) {
if(input[i] >= 97 && input[i] <= 122) { //if the character is small alphabet from a to z
atomicAdd(&private_histogram[input[i]-97], 1);
} else if(input[i] >= 48 && input[i] <= 57) { //if the character is a digit from 0 to 9
atomicAdd(&private_histogram[input[i]-22], 1);
} else if(input[i] == 32) { //if the character is a space
atomicAdd(&private_histogram[SPACE_INDEX], 1);
} else if(input[i] == 46) { //if the character is a fullstop
atomicAdd(&private_histogram[PERIOD_INDEX], 1);
} else if(input[i] == 44) { //if the character is a comma
atomicAdd(&private_histogram[COMMA_INDEX], 1);
} else if(input[i] == 10) { //if the character is a new line character
atomicAdd(&private_histogram[NEW_LINE], 1);
}
i += stride;
}
__syncthreads();
if (threadIdx.x < NUM_BINS) {
atomicAdd(&bins[threadIdx.x], private_histogram[threadIdx.x]);
}
__syncthreads();
}
/*
* This function reads input character and converts that character into its corresponding string code from the char**
* array passed. The code is written to output array with each character code taking as much space as is the length
* of the code.
*/
__global__ void encodeDataKernel(char* input, unsigned int num_elements, char** characterCodes, int* codeLengths, int maxLength, char* output) {
//__shared__ char* sharedOutput[outSize];
int i = blockIdx.x * blockDim.x + threadIdx.x;
char ch;
char* code;
int codeLen = 0;
if(threadIdx.x < num_elements) {
ch = input[threadIdx.x];
if(ch >= 97 && ch <= 122) { //if the character is small alphabet from a to z
code = characterCodes[ch - 97];
codeLen = codeLengths[ch - 97];
} else if(ch >= 48 && ch <= 57) { //if the character is a digit from 0 to 9
code = characterCodes[ch - 22];
codeLen = codeLengths[ch - 22];
} else if(ch == 32) { //if the character is a space
code = characterCodes[SPACE_INDEX];
codeLen = codeLengths[SPACE_INDEX];
} else if(ch == 46) { //if the character is a fullstop
code = characterCodes[PERIOD_INDEX];
codeLen = codeLengths[PERIOD_INDEX];
} else if(ch == 44) { //if the character is a comma
code = characterCodes[COMMA_INDEX];
codeLen = codeLengths[COMMA_INDEX];
} else if(ch == 10) { //if the character is a new line character
code = characterCodes[NEW_LINE];
codeLen = codeLengths[NEW_LINE];
}
}
__syncthreads();
int j = i * maxLength, k, m;
for(m = 0, k = 0; m < maxLength && k < codeLen; j++, k++, m++) {
//sharedOutput[j] = code[k];
output[j] = code[k];
}
if(k == codeLen && m < maxLength) {
for(; m < maxLength; m++, j++) {
//sharedOutput[j] = '2'; //padding with '2'
output[j] = '2'; //padding with '2'
}
}
__syncthreads();
}
/******************************************************************************
Setup and invoke your kernel(s) in this function. You may also allocate more
GPU memory if you need to
*******************************************************************************/
void histogram(char* input, unsigned int* bins, unsigned int num_elements)
{
// INSERT CODE HERE
dim3 dimGrid((num_elements - 1)/BLOCK_SIZE + 1, 1, 1);
dim3 dimBlock(BLOCK_SIZE, 1, 1);
calculateFrequency<<<dimGrid, dimBlock>>>(input, bins, num_elements);
}
void encodeData(char* input, unsigned int num_elements, char** characterCodes, int* codeLengths, int maxLength, char* output) {
dim3 dimGrid((num_elements - 1)/BLOCK_SIZE + 1, 1, 1);
dim3 dimBlock(BLOCK_SIZE, 1, 1);
encodeDataKernel<<<dimGrid, dimBlock>>>(input, num_elements, characterCodes, codeLengths, maxLength, output);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
// Define your kernels in this file you may use more than one kernel if you
// need to
#define BLOCK_SIZE 512
#define NUM_BINS 40
#define SPACE_INDEX 36
#define PERIOD_INDEX 37
#define COMMA_INDEX 38
#define NEW_LINE 39
// INSERT KERNEL(S) HERE
/*
* This function calculates the frequency of each character in the character buffer. It does so by creating local
* histograms and finally merging them with global histogram.
*/
__global__ void calculateFrequency(char* input, unsigned int* bins, unsigned int num_elements)
{
__shared__ unsigned int private_histogram[NUM_BINS];
//Computation of private histogram
int i = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
if (threadIdx.x < NUM_BINS) {
private_histogram[threadIdx.x] = 0;
}
__syncthreads();
while(i < num_elements) {
if(input[i] >= 97 && input[i] <= 122) { //if the character is small alphabet from a to z
atomicAdd(&private_histogram[input[i]-97], 1);
} else if(input[i] >= 48 && input[i] <= 57) { //if the character is a digit from 0 to 9
atomicAdd(&private_histogram[input[i]-22], 1);
} else if(input[i] == 32) { //if the character is a space
atomicAdd(&private_histogram[SPACE_INDEX], 1);
} else if(input[i] == 46) { //if the character is a fullstop
atomicAdd(&private_histogram[PERIOD_INDEX], 1);
} else if(input[i] == 44) { //if the character is a comma
atomicAdd(&private_histogram[COMMA_INDEX], 1);
} else if(input[i] == 10) { //if the character is a new line character
atomicAdd(&private_histogram[NEW_LINE], 1);
}
i += stride;
}
__syncthreads();
if (threadIdx.x < NUM_BINS) {
atomicAdd(&bins[threadIdx.x], private_histogram[threadIdx.x]);
}
__syncthreads();
}
/*
* This function reads input character and converts that character into its corresponding string code from the char**
* array passed. The code is written to output array with each character code taking as much space as is the length
* of the code.
*/
__global__ void encodeDataKernel(char* input, unsigned int num_elements, char** characterCodes, int* codeLengths, int maxLength, char* output) {
//__shared__ char* sharedOutput[outSize];
int i = blockIdx.x * blockDim.x + threadIdx.x;
char ch;
char* code;
int codeLen = 0;
if(threadIdx.x < num_elements) {
ch = input[threadIdx.x];
if(ch >= 97 && ch <= 122) { //if the character is small alphabet from a to z
code = characterCodes[ch - 97];
codeLen = codeLengths[ch - 97];
} else if(ch >= 48 && ch <= 57) { //if the character is a digit from 0 to 9
code = characterCodes[ch - 22];
codeLen = codeLengths[ch - 22];
} else if(ch == 32) { //if the character is a space
code = characterCodes[SPACE_INDEX];
codeLen = codeLengths[SPACE_INDEX];
} else if(ch == 46) { //if the character is a fullstop
code = characterCodes[PERIOD_INDEX];
codeLen = codeLengths[PERIOD_INDEX];
} else if(ch == 44) { //if the character is a comma
code = characterCodes[COMMA_INDEX];
codeLen = codeLengths[COMMA_INDEX];
} else if(ch == 10) { //if the character is a new line character
code = characterCodes[NEW_LINE];
codeLen = codeLengths[NEW_LINE];
}
}
__syncthreads();
int j = i * maxLength, k, m;
for(m = 0, k = 0; m < maxLength && k < codeLen; j++, k++, m++) {
//sharedOutput[j] = code[k];
output[j] = code[k];
}
if(k == codeLen && m < maxLength) {
for(; m < maxLength; m++, j++) {
//sharedOutput[j] = '2'; //padding with '2'
output[j] = '2'; //padding with '2'
}
}
__syncthreads();
}
/******************************************************************************
Setup and invoke your kernel(s) in this function. You may also allocate more
GPU memory if you need to
*******************************************************************************/
void histogram(char* input, unsigned int* bins, unsigned int num_elements)
{
// INSERT CODE HERE
dim3 dimGrid((num_elements - 1)/BLOCK_SIZE + 1, 1, 1);
dim3 dimBlock(BLOCK_SIZE, 1, 1);
calculateFrequency<<<dimGrid, dimBlock>>>(input, bins, num_elements);
}
void encodeData(char* input, unsigned int num_elements, char** characterCodes, int* codeLengths, int maxLength, char* output) {
dim3 dimGrid((num_elements - 1)/BLOCK_SIZE + 1, 1, 1);
dim3 dimBlock(BLOCK_SIZE, 1, 1);
encodeDataKernel<<<dimGrid, dimBlock>>>(input, num_elements, characterCodes, codeLengths, maxLength, output);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18calculateFrequencyPcPjj
.globl _Z18calculateFrequencyPcPjj
.p2align 8
.type _Z18calculateFrequencyPcPjj,@function
_Z18calculateFrequencyPcPjj:
s_load_b32 s2, s[0:1], 0x24
v_cmp_gt_u32_e32 vcc_lo, 40, v0
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_2
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 2, v0
ds_store_b32 v1, v2
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
s_load_b32 s4, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, 0xffff, s2
s_mov_b32 s5, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s4, v1
s_cbranch_execz .LBB0_33
s_clause 0x1
s_load_b32 s2, s[0:1], 0x18
s_load_b64 s[8:9], s[0:1], 0x0
v_ashrrev_i32_e32 v3, 31, v1
v_mov_b32_e32 v4, 1
s_waitcnt lgkmcnt(0)
s_mul_i32 s6, s2, s3
v_add_co_u32 v2, s2, s8, v1
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s2, s9, v3, s2
s_ashr_i32 s7, s6, 31
s_mov_b32 s8, 0
s_branch .LBB0_5
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v1, s6, v1
v_add_co_u32 v2, s3, v2, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v3, s3, s7, v3, s3
v_cmp_le_u32_e64 s2, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s8, s2, s8
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execz .LBB0_33
.LBB0_5:
global_load_u8 v6, v[2:3], off
s_mov_b32 s9, 0
s_waitcnt vmcnt(0)
v_add_nc_u16 v5, v6, 0xff9f
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v5, 0xff, v5
v_cmp_lt_u16_e64 s2, 25, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB0_29
v_sub_nc_u16 v5, v6, 48
s_mov_b32 s10, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v5, 0xff, v5
v_cmp_lt_u16_e64 s2, 9, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s9, s2
s_xor_b32 s9, exec_lo, s9
s_cbranch_execz .LBB0_26
v_and_b32_e32 v6, 0xff, v6
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i16_e32 43, v6
s_xor_b32 s11, exec_lo, s11
s_cbranch_execz .LBB0_17
s_mov_b32 s12, exec_lo
v_cmpx_lt_i16_e32 45, v6
s_xor_b32 s12, exec_lo, s12
s_cbranch_execz .LBB0_12
s_mov_b32 s14, exec_lo
v_cmpx_eq_u16_e32 46, v6
s_mov_b32 s10, exec_lo
s_movk_i32 s13, 0x94
s_or_b32 exec_lo, exec_lo, s14
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s10, s10, exec_lo
.LBB0_12:
s_or_saveexec_b32 s12, s12
v_mov_b32_e32 v5, s13
s_xor_b32 exec_lo, exec_lo, s12
s_cbranch_execz .LBB0_16
s_mov_b32 s13, s10
s_mov_b32 s15, exec_lo
v_cmpx_eq_u16_e32 44, v6
s_movk_i32 s14, 0x98
s_or_b32 s13, s10, exec_lo
s_or_b32 exec_lo, exec_lo, s15
v_mov_b32_e32 v5, s14
s_and_not1_b32 s2, s10, exec_lo
s_and_b32 s10, s13, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s10, s2, s10
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s12
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s10, s10, exec_lo
.LBB0_17:
s_and_not1_saveexec_b32 s11, s11
s_cbranch_execz .LBB0_25
s_mov_b32 s12, s10
s_mov_b32 s13, exec_lo
v_cmpx_lt_i16_e32 31, v6
s_xor_b32 s13, exec_lo, s13
v_cmp_eq_u16_e64 s2, 32, v6
s_and_not1_b32 s12, s10, exec_lo
s_movk_i32 s14, 0x90
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, exec_lo
s_or_b32 s12, s12, s2
s_or_saveexec_b32 s13, s13
v_mov_b32_e32 v5, s14
s_xor_b32 exec_lo, exec_lo, s13
s_cbranch_execz .LBB0_24
v_cmp_eq_u16_e64 s2, 10, v6
s_mov_b32 s14, s12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s16, s2
s_xor_b32 s2, exec_lo, s16
s_movk_i32 s15, 0x9c
s_or_b32 s14, s12, exec_lo
s_or_b32 exec_lo, exec_lo, s2
v_mov_b32_e32 v5, s15
s_and_not1_b32 s2, s12, exec_lo
s_and_b32 s12, s14, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s12, s2, s12
.LBB0_24:
s_or_b32 exec_lo, exec_lo, s13
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s2, s10, exec_lo
s_and_b32 s10, s12, exec_lo
s_or_b32 s10, s2, s10
.LBB0_25:
s_or_b32 exec_lo, exec_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s10, s10, exec_lo
.LBB0_26:
s_and_not1_saveexec_b32 s2, s9
v_sub_nc_u16 v5, v6, 22
s_or_b32 s10, s10, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v5, 0xff, v5
v_lshlrev_b32_e32 v5, 2, v5
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s9, s10, exec_lo
.LBB0_29:
s_and_not1_saveexec_b32 s2, s3
v_bfe_i32 v5, v6, 0, 8
s_or_b32 s9, s9, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v5, v5, 2, 0xfffffe7c
s_or_b32 exec_lo, exec_lo, s2
s_and_saveexec_b32 s2, s9
s_cbranch_execz .LBB0_4
ds_add_u32 v5, v4
s_branch .LBB0_4
.LBB0_33:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_35
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x8
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
.LBB0_35:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18calculateFrequencyPcPjj
.amdhsa_group_segment_fixed_size 160
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18calculateFrequencyPcPjj, .Lfunc_end0-_Z18calculateFrequencyPcPjj
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z16encodeDataKernelPcjPS_PiiS_
.globl _Z16encodeDataKernelPcjPS_PiiS_
.p2align 8
.type _Z16encodeDataKernelPcjPS_PiiS_,@function
_Z16encodeDataKernelPcjPS_PiiS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x8
s_load_b32 s4, s[0:1], 0x3c
v_mov_b32_e32 v4, 0
s_waitcnt lgkmcnt(0)
v_cmp_gt_u32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_30
s_load_b64 s[6:7], s[0:1], 0x0
s_mov_b32 s5, 0
s_waitcnt lgkmcnt(0)
global_load_u8 v3, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u16 v1, v3, 0xff9f
v_bfe_i32 v2, v3, 0, 8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, 0xff, v1
v_cmp_lt_u16_e32 vcc_lo, 25, v1
s_and_saveexec_b32 s3, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB1_25
v_sub_nc_u16 v1, v3, 48
s_mov_b32 s6, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, 0xff, v1
v_cmp_lt_u16_e32 vcc_lo, 9, v1
s_and_saveexec_b32 s5, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s5, exec_lo, s5
s_cbranch_execz .LBB1_22
v_and_b32_e32 v2, 0xff, v3
s_mov_b32 s7, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i16_e32 43, v2
s_xor_b32 s7, exec_lo, s7
s_cbranch_execz .LBB1_13
s_mov_b32 s8, exec_lo
v_cmpx_lt_i16_e32 45, v2
s_xor_b32 s8, exec_lo, s8
s_cbranch_execz .LBB1_8
s_mov_b32 s9, 0
s_mov_b32 s11, exec_lo
v_cmpx_eq_u16_e32 46, v2
s_mov_b32 s6, exec_lo
s_mov_b32 s10, 37
s_or_b32 exec_lo, exec_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s6, s6, exec_lo
.LBB1_8:
s_or_saveexec_b32 s8, s8
v_dual_mov_b32 v4, s9 :: v_dual_mov_b32 v1, s10
s_xor_b32 exec_lo, exec_lo, s8
s_cbranch_execz .LBB1_12
s_mov_b32 s9, s6
s_mov_b32 s11, exec_lo
v_cmpx_eq_u16_e32 44, v2
s_mov_b32 s10, 38
s_or_b32 s9, s6, exec_lo
s_or_b32 exec_lo, exec_lo, s11
v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s10
s_and_not1_b32 s6, s6, exec_lo
s_and_b32 s9, s9, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s6, s6, s9
.LBB1_12:
s_or_b32 exec_lo, exec_lo, s8
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s6, s6, exec_lo
.LBB1_13:
s_and_not1_saveexec_b32 s7, s7
s_cbranch_execz .LBB1_21
s_mov_b32 s8, s6
s_mov_b32 s9, exec_lo
v_cmpx_lt_i16_e32 31, v2
s_xor_b32 s9, exec_lo, s9
v_cmp_eq_u16_e32 vcc_lo, 32, v2
s_and_not1_b32 s8, s6, exec_lo
s_mov_b32 s10, 36
s_mov_b32 s11, 0
s_and_b32 s12, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s8, s8, s12
s_or_saveexec_b32 s9, s9
v_dual_mov_b32 v4, s11 :: v_dual_mov_b32 v1, s10
s_xor_b32 exec_lo, exec_lo, s9
s_cbranch_execz .LBB1_20
s_mov_b32 s10, s8
s_mov_b32 s12, exec_lo
v_cmpx_eq_u16_e32 10, v2
s_xor_b32 s12, exec_lo, s12
s_mov_b32 s11, 39
s_or_b32 s10, s8, exec_lo
s_or_b32 exec_lo, exec_lo, s12
v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s11
s_and_not1_b32 s8, s8, exec_lo
s_and_b32 s10, s10, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s8, s8, s10
.LBB1_20:
s_or_b32 exec_lo, exec_lo, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s6, s6, exec_lo
s_and_b32 s8, s8, exec_lo
s_or_b32 s6, s6, s8
.LBB1_21:
s_or_b32 exec_lo, exec_lo, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s6, s6, exec_lo
.LBB1_22:
s_and_not1_saveexec_b32 s5, s5
v_subrev_nc_u32_e32 v1, 22, v2
s_or_b32 s6, s6, exec_lo
s_or_b32 exec_lo, exec_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s5, s6, exec_lo
.LBB1_25:
s_and_not1_saveexec_b32 s3, s3
v_add_nc_u32_e32 v1, 0xffffff9f, v2
s_or_b32 s5, s5, exec_lo
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s3, s5
s_cbranch_execz .LBB1_29
s_load_b128 s[8:11], s[0:1], 0x10
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 3, v[1:2]
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s8, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
v_add_co_u32 v5, vcc_lo, s10, v1
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, s11, v2, vcc_lo
global_load_b64 v[2:3], v[3:4], off
global_load_b32 v4, v[5:6], off
.LBB1_29:
s_or_b32 exec_lo, exec_lo, s3
.LBB1_30:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s2
s_clause 0x1
s_load_b32 s5, s[0:1], 0x20
s_load_b64 s[2:3], s[0:1], 0x28
s_and_b32 s0, 0xffff, s4
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, 0, v4
v_mad_u64_u32 v[5:6], null, s15, s0, v[0:1]
v_mov_b32_e32 v0, 0
s_mov_b32 s7, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_mul_lo_u32 v5, v5, s5
s_cmp_gt_i32 s5, 0
s_cselect_b32 s4, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s4, vcc_lo
s_and_saveexec_b32 s6, s0
s_cbranch_execz .LBB1_34
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v0, 31, v5
v_add_co_u32 v6, vcc_lo, s2, v5
v_min_i32_e32 v8, s5, v4
s_mov_b64 s[0:1], 0
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v0, vcc_lo
.p2align 6
.LBB1_32:
v_add_co_u32 v0, vcc_lo, v2, s0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v9, vcc_lo, v6, s0
s_add_u32 s0, s0, 1
flat_load_u8 v11, v[0:1]
v_add_co_ci_u32_e32 v10, vcc_lo, s1, v7, vcc_lo
v_cmp_ge_i32_e32 vcc_lo, s0, v8
s_addc_u32 s1, s1, 0
s_cmp_lt_i32 s0, s5
v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
s_cselect_b32 s9, -1, 0
s_or_b32 s7, vcc_lo, s7
s_and_not1_b32 s8, s8, exec_lo
s_and_b32 s9, s9, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s8, s8, s9
s_waitcnt vmcnt(0) lgkmcnt(0)
global_store_b8 v[9:10], v11, off
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB1_32
s_or_b32 exec_lo, exec_lo, s7
v_add_nc_u32_e32 v5, v5, v0
s_and_not1_b32 s0, s4, exec_lo
s_and_b32 s1, s8, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s4, s0, s1
.LBB1_34:
s_or_b32 exec_lo, exec_lo, s6
v_cmp_eq_u32_e32 vcc_lo, v0, v4
v_cmp_gt_i32_e64 s0, s5, v0
s_and_b32 s1, vcc_lo, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB1_37
v_ashrrev_i32_e32 v2, 31, v5
v_add_co_u32 v1, vcc_lo, s2, v5
v_mov_b32_e32 v3, 50
s_mov_b32 s2, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
.LBB1_36:
v_add_nc_u32_e32 v0, 1, v0
global_store_b8 v[1:2], v3, off
v_add_co_u32 v1, s0, v1, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v2, s0, 0, v2, s0
v_cmp_le_i32_e32 vcc_lo, s5, v0
s_or_b32 s2, vcc_lo, s2
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB1_36
.LBB1_37:
s_or_b32 exec_lo, exec_lo, s1
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16encodeDataKernelPcjPS_PiiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z16encodeDataKernelPcjPS_PiiS_, .Lfunc_end1-_Z16encodeDataKernelPcjPS_PiiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 160
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18calculateFrequencyPcPjj
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: _Z18calculateFrequencyPcPjj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16encodeDataKernelPcjPS_PiiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16encodeDataKernelPcjPS_PiiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
// Define your kernels in this file you may use more than one kernel if you
// need to
#define BLOCK_SIZE 512
#define NUM_BINS 40
#define SPACE_INDEX 36
#define PERIOD_INDEX 37
#define COMMA_INDEX 38
#define NEW_LINE 39
// INSERT KERNEL(S) HERE
/*
* This function calculates the frequency of each character in the character buffer. It does so by creating local
* histograms and finally merging them with global histogram.
*/
__global__ void calculateFrequency(char* input, unsigned int* bins, unsigned int num_elements)
{
__shared__ unsigned int private_histogram[NUM_BINS];
//Computation of private histogram
int i = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
if (threadIdx.x < NUM_BINS) {
private_histogram[threadIdx.x] = 0;
}
__syncthreads();
while(i < num_elements) {
if(input[i] >= 97 && input[i] <= 122) { //if the character is small alphabet from a to z
atomicAdd(&private_histogram[input[i]-97], 1);
} else if(input[i] >= 48 && input[i] <= 57) { //if the character is a digit from 0 to 9
atomicAdd(&private_histogram[input[i]-22], 1);
} else if(input[i] == 32) { //if the character is a space
atomicAdd(&private_histogram[SPACE_INDEX], 1);
} else if(input[i] == 46) { //if the character is a fullstop
atomicAdd(&private_histogram[PERIOD_INDEX], 1);
} else if(input[i] == 44) { //if the character is a comma
atomicAdd(&private_histogram[COMMA_INDEX], 1);
} else if(input[i] == 10) { //if the character is a new line character
atomicAdd(&private_histogram[NEW_LINE], 1);
}
i += stride;
}
__syncthreads();
if (threadIdx.x < NUM_BINS) {
atomicAdd(&bins[threadIdx.x], private_histogram[threadIdx.x]);
}
__syncthreads();
}
/*
* This function reads input character and converts that character into its corresponding string code from the char**
* array passed. The code is written to output array with each character code taking as much space as is the length
* of the code.
*/
__global__ void encodeDataKernel(char* input, unsigned int num_elements, char** characterCodes, int* codeLengths, int maxLength, char* output) {
//__shared__ char* sharedOutput[outSize];
int i = blockIdx.x * blockDim.x + threadIdx.x;
char ch;
char* code;
int codeLen = 0;
if(threadIdx.x < num_elements) {
ch = input[threadIdx.x];
if(ch >= 97 && ch <= 122) { //if the character is small alphabet from a to z
code = characterCodes[ch - 97];
codeLen = codeLengths[ch - 97];
} else if(ch >= 48 && ch <= 57) { //if the character is a digit from 0 to 9
code = characterCodes[ch - 22];
codeLen = codeLengths[ch - 22];
} else if(ch == 32) { //if the character is a space
code = characterCodes[SPACE_INDEX];
codeLen = codeLengths[SPACE_INDEX];
} else if(ch == 46) { //if the character is a fullstop
code = characterCodes[PERIOD_INDEX];
codeLen = codeLengths[PERIOD_INDEX];
} else if(ch == 44) { //if the character is a comma
code = characterCodes[COMMA_INDEX];
codeLen = codeLengths[COMMA_INDEX];
} else if(ch == 10) { //if the character is a new line character
code = characterCodes[NEW_LINE];
codeLen = codeLengths[NEW_LINE];
}
}
__syncthreads();
int j = i * maxLength, k, m;
for(m = 0, k = 0; m < maxLength && k < codeLen; j++, k++, m++) {
//sharedOutput[j] = code[k];
output[j] = code[k];
}
if(k == codeLen && m < maxLength) {
for(; m < maxLength; m++, j++) {
//sharedOutput[j] = '2'; //padding with '2'
output[j] = '2'; //padding with '2'
}
}
__syncthreads();
}
/******************************************************************************
Setup and invoke your kernel(s) in this function. You may also allocate more
GPU memory if you need to
*******************************************************************************/
void histogram(char* input, unsigned int* bins, unsigned int num_elements)
{
// INSERT CODE HERE
dim3 dimGrid((num_elements - 1)/BLOCK_SIZE + 1, 1, 1);
dim3 dimBlock(BLOCK_SIZE, 1, 1);
calculateFrequency<<<dimGrid, dimBlock>>>(input, bins, num_elements);
}
void encodeData(char* input, unsigned int num_elements, char** characterCodes, int* codeLengths, int maxLength, char* output) {
dim3 dimGrid((num_elements - 1)/BLOCK_SIZE + 1, 1, 1);
dim3 dimBlock(BLOCK_SIZE, 1, 1);
encodeDataKernel<<<dimGrid, dimBlock>>>(input, num_elements, characterCodes, codeLengths, maxLength, output);
} | .text
.file "kernel.hip"
.globl _Z33__device_stub__calculateFrequencyPcPjj # -- Begin function _Z33__device_stub__calculateFrequencyPcPjj
.p2align 4, 0x90
.type _Z33__device_stub__calculateFrequencyPcPjj,@function
_Z33__device_stub__calculateFrequencyPcPjj: # @_Z33__device_stub__calculateFrequencyPcPjj
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18calculateFrequencyPcPjj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z33__device_stub__calculateFrequencyPcPjj, .Lfunc_end0-_Z33__device_stub__calculateFrequencyPcPjj
.cfi_endproc
# -- End function
.globl _Z31__device_stub__encodeDataKernelPcjPS_PiiS_ # -- Begin function _Z31__device_stub__encodeDataKernelPcjPS_PiiS_
.p2align 4, 0x90
.type _Z31__device_stub__encodeDataKernelPcjPS_PiiS_,@function
_Z31__device_stub__encodeDataKernelPcjPS_PiiS_: # @_Z31__device_stub__encodeDataKernelPcjPS_PiiS_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movl %r8d, 8(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16encodeDataKernelPcjPS_PiiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z31__device_stub__encodeDataKernelPcjPS_PiiS_, .Lfunc_end1-_Z31__device_stub__encodeDataKernelPcjPS_PiiS_
.cfi_endproc
# -- End function
.globl _Z9histogramPcPjj # -- Begin function _Z9histogramPcPjj
.p2align 4, 0x90
.type _Z9histogramPcPjj,@function
_Z9histogramPcPjj: # @_Z9histogramPcPjj
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %edx, %ebx
movq %rsi, %r14
movq %rdi, %r15
leal -1(%rbx), %eax
shrl $9, %eax
movabsq $4294967296, %rdx # imm = 0x100000000
leaq (%rdx,%rax), %rdi
incq %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq %r15, 72(%rsp)
movq %r14, 64(%rsp)
movl %ebx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18calculateFrequencyPcPjj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z9histogramPcPjj, .Lfunc_end2-_Z9histogramPcPjj
.cfi_endproc
# -- End function
.globl _Z10encodeDataPcjPS_PiiS_ # -- Begin function _Z10encodeDataPcjPS_PiiS_
.p2align 4, 0x90
.type _Z10encodeDataPcjPS_PiiS_,@function
_Z10encodeDataPcjPS_PiiS_: # @_Z10encodeDataPcjPS_PiiS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movl %r8d, %ebp
movq %rcx, %r14
movq %rdx, %r15
movl %esi, %r12d
movq %rdi, %r13
leal -1(%r12), %eax
shrl $9, %eax
movabsq $4294967296, %rdx # imm = 0x100000000
leaq (%rdx,%rax), %rdi
incq %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq %r13, 88(%rsp)
movl %r12d, 12(%rsp)
movq %r15, 80(%rsp)
movq %r14, 72(%rsp)
movl %ebp, 8(%rsp)
movq %rbx, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16encodeDataKernelPcjPS_PiiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z10encodeDataPcjPS_PiiS_, .Lfunc_end3-_Z10encodeDataPcjPS_PiiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18calculateFrequencyPcPjj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16encodeDataKernelPcjPS_PiiS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18calculateFrequencyPcPjj,@object # @_Z18calculateFrequencyPcPjj
.section .rodata,"a",@progbits
.globl _Z18calculateFrequencyPcPjj
.p2align 3, 0x0
_Z18calculateFrequencyPcPjj:
.quad _Z33__device_stub__calculateFrequencyPcPjj
.size _Z18calculateFrequencyPcPjj, 8
.type _Z16encodeDataKernelPcjPS_PiiS_,@object # @_Z16encodeDataKernelPcjPS_PiiS_
.globl _Z16encodeDataKernelPcjPS_PiiS_
.p2align 3, 0x0
_Z16encodeDataKernelPcjPS_PiiS_:
.quad _Z31__device_stub__encodeDataKernelPcjPS_PiiS_
.size _Z16encodeDataKernelPcjPS_PiiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18calculateFrequencyPcPjj"
.size .L__unnamed_1, 28
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z16encodeDataKernelPcjPS_PiiS_"
.size .L__unnamed_2, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__calculateFrequencyPcPjj
.addrsig_sym _Z31__device_stub__encodeDataKernelPcjPS_PiiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18calculateFrequencyPcPjj
.addrsig_sym _Z16encodeDataKernelPcjPS_PiiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00106e70_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z18calculateFrequencyPcPjjPcPjj
.type _Z41__device_stub__Z18calculateFrequencyPcPjjPcPjj, @function
_Z41__device_stub__Z18calculateFrequencyPcPjjPcPjj:
.LFB2053:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18calculateFrequencyPcPjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z41__device_stub__Z18calculateFrequencyPcPjjPcPjj, .-_Z41__device_stub__Z18calculateFrequencyPcPjjPcPjj
.globl _Z18calculateFrequencyPcPjj
.type _Z18calculateFrequencyPcPjj, @function
_Z18calculateFrequencyPcPjj:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z18calculateFrequencyPcPjjPcPjj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z18calculateFrequencyPcPjj, .-_Z18calculateFrequencyPcPjj
.globl _Z9histogramPcPjj
.type _Z9histogramPcPjj, @function
_Z9histogramPcPjj:
.LFB2027:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movq %rsi, %r12
movl %edx, %ebx
leal -1(%rdx), %eax
shrl $9, %eax
addl $1, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl %ebx, %edx
movq %r12, %rsi
movq %rbp, %rdi
call _Z41__device_stub__Z18calculateFrequencyPcPjjPcPjj
jmp .L11
.cfi_endproc
.LFE2027:
.size _Z9histogramPcPjj, .-_Z9histogramPcPjj
.globl _Z45__device_stub__Z16encodeDataKernelPcjPS_PiiS_PcjPS_PiiS_
.type _Z45__device_stub__Z16encodeDataKernelPcjPS_PiiS_PcjPS_PiiS_, @function
_Z45__device_stub__Z16encodeDataKernelPcjPS_PiiS_PcjPS_PiiS_:
.LFB2055:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 32(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16encodeDataKernelPcjPS_PiiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z45__device_stub__Z16encodeDataKernelPcjPS_PiiS_PcjPS_PiiS_, .-_Z45__device_stub__Z16encodeDataKernelPcjPS_PiiS_PcjPS_PiiS_
.globl _Z16encodeDataKernelPcjPS_PiiS_
.type _Z16encodeDataKernelPcjPS_PiiS_, @function
_Z16encodeDataKernelPcjPS_PiiS_:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z16encodeDataKernelPcjPS_PiiS_PcjPS_PiiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z16encodeDataKernelPcjPS_PiiS_, .-_Z16encodeDataKernelPcjPS_PiiS_
.globl _Z10encodeDataPcjPS_PiiS_
.type _Z10encodeDataPcjPS_PiiS_, @function
_Z10encodeDataPcjPS_PiiS_:
.LFB2028:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbp
movl %esi, %ebx
movq %rdx, %r12
movq %rcx, %r13
movl %r8d, %r14d
movq %r9, %r15
leal -1(%rsi), %eax
shrl $9, %eax
addl $1, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L23:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movq %r15, %r9
movl %r14d, %r8d
movq %r13, %rcx
movq %r12, %rdx
movl %ebx, %esi
movq %rbp, %rdi
call _Z45__device_stub__Z16encodeDataKernelPcjPS_PiiS_PcjPS_PiiS_
jmp .L23
.cfi_endproc
.LFE2028:
.size _Z10encodeDataPcjPS_PiiS_, .-_Z10encodeDataPcjPS_PiiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z16encodeDataKernelPcjPS_PiiS_"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z18calculateFrequencyPcPjj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16encodeDataKernelPcjPS_PiiS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z18calculateFrequencyPcPjj(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z33__device_stub__calculateFrequencyPcPjj # -- Begin function _Z33__device_stub__calculateFrequencyPcPjj
.p2align 4, 0x90
.type _Z33__device_stub__calculateFrequencyPcPjj,@function
_Z33__device_stub__calculateFrequencyPcPjj: # @_Z33__device_stub__calculateFrequencyPcPjj
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18calculateFrequencyPcPjj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z33__device_stub__calculateFrequencyPcPjj, .Lfunc_end0-_Z33__device_stub__calculateFrequencyPcPjj
.cfi_endproc
# -- End function
.globl _Z31__device_stub__encodeDataKernelPcjPS_PiiS_ # -- Begin function _Z31__device_stub__encodeDataKernelPcjPS_PiiS_
.p2align 4, 0x90
.type _Z31__device_stub__encodeDataKernelPcjPS_PiiS_,@function
_Z31__device_stub__encodeDataKernelPcjPS_PiiS_: # @_Z31__device_stub__encodeDataKernelPcjPS_PiiS_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movl %r8d, 8(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16encodeDataKernelPcjPS_PiiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z31__device_stub__encodeDataKernelPcjPS_PiiS_, .Lfunc_end1-_Z31__device_stub__encodeDataKernelPcjPS_PiiS_
.cfi_endproc
# -- End function
.globl _Z9histogramPcPjj # -- Begin function _Z9histogramPcPjj
.p2align 4, 0x90
.type _Z9histogramPcPjj,@function
_Z9histogramPcPjj: # @_Z9histogramPcPjj
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %edx, %ebx
movq %rsi, %r14
movq %rdi, %r15
leal -1(%rbx), %eax
shrl $9, %eax
movabsq $4294967296, %rdx # imm = 0x100000000
leaq (%rdx,%rax), %rdi
incq %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq %r15, 72(%rsp)
movq %r14, 64(%rsp)
movl %ebx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18calculateFrequencyPcPjj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z9histogramPcPjj, .Lfunc_end2-_Z9histogramPcPjj
.cfi_endproc
# -- End function
.globl _Z10encodeDataPcjPS_PiiS_ # -- Begin function _Z10encodeDataPcjPS_PiiS_
.p2align 4, 0x90
.type _Z10encodeDataPcjPS_PiiS_,@function
_Z10encodeDataPcjPS_PiiS_: # @_Z10encodeDataPcjPS_PiiS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movl %r8d, %ebp
movq %rcx, %r14
movq %rdx, %r15
movl %esi, %r12d
movq %rdi, %r13
leal -1(%r12), %eax
shrl $9, %eax
movabsq $4294967296, %rdx # imm = 0x100000000
leaq (%rdx,%rax), %rdi
incq %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq %r13, 88(%rsp)
movl %r12d, 12(%rsp)
movq %r15, 80(%rsp)
movq %r14, 72(%rsp)
movl %ebp, 8(%rsp)
movq %rbx, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16encodeDataKernelPcjPS_PiiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z10encodeDataPcjPS_PiiS_, .Lfunc_end3-_Z10encodeDataPcjPS_PiiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18calculateFrequencyPcPjj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16encodeDataKernelPcjPS_PiiS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18calculateFrequencyPcPjj,@object # @_Z18calculateFrequencyPcPjj
.section .rodata,"a",@progbits
.globl _Z18calculateFrequencyPcPjj
.p2align 3, 0x0
_Z18calculateFrequencyPcPjj:
.quad _Z33__device_stub__calculateFrequencyPcPjj
.size _Z18calculateFrequencyPcPjj, 8
.type _Z16encodeDataKernelPcjPS_PiiS_,@object # @_Z16encodeDataKernelPcjPS_PiiS_
.globl _Z16encodeDataKernelPcjPS_PiiS_
.p2align 3, 0x0
_Z16encodeDataKernelPcjPS_PiiS_:
.quad _Z31__device_stub__encodeDataKernelPcjPS_PiiS_
.size _Z16encodeDataKernelPcjPS_PiiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18calculateFrequencyPcPjj"
.size .L__unnamed_1, 28
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z16encodeDataKernelPcjPS_PiiS_"
.size .L__unnamed_2, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__calculateFrequencyPcPjj
.addrsig_sym _Z31__device_stub__encodeDataKernelPcjPS_PiiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18calculateFrequencyPcPjj
.addrsig_sym _Z16encodeDataKernelPcjPS_PiiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //pass
//--blockDim=32 --gridDim=2
#include "../common.h"
__global__ void Pathcalc_Portfolio_KernelGPU2(float *d_v)
{
const int tid = blockDim.x * blockIdx.x + threadIdx.x;
const int threadN = blockDim.x * gridDim.x;
int i, path;
float L[NN], z[NN];
/* Monte Carlo LIBOR path calculation*/
for(path = tid; path < NPATH; path += threadN){
// initialise the data for current thread
for (i=0; i<N; i++) {
// for real application, z should be randomly generated
z[i] = 0.3;
L[i] = 0.05;
}
path_calc(L, z);
d_v[path] = portfolio(L);
}
} | .file "tmpxft_000fb4af_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2034:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2034:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z29Pathcalc_Portfolio_KernelGPU2PfPf
.type _Z49__device_stub__Z29Pathcalc_Portfolio_KernelGPU2PfPf, @function
_Z49__device_stub__Z29Pathcalc_Portfolio_KernelGPU2PfPf:
.LFB2056:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z29Pathcalc_Portfolio_KernelGPU2Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2056:
.size _Z49__device_stub__Z29Pathcalc_Portfolio_KernelGPU2PfPf, .-_Z49__device_stub__Z29Pathcalc_Portfolio_KernelGPU2PfPf
.globl _Z29Pathcalc_Portfolio_KernelGPU2Pf
.type _Z29Pathcalc_Portfolio_KernelGPU2Pf, @function
_Z29Pathcalc_Portfolio_KernelGPU2Pf:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z29Pathcalc_Portfolio_KernelGPU2PfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z29Pathcalc_Portfolio_KernelGPU2Pf, .-_Z29Pathcalc_Portfolio_KernelGPU2Pf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z29Pathcalc_Portfolio_KernelGPU2Pf"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "N"
.LC2:
.string "Nmat"
.LC3:
.string "Nopt"
.LC4:
.string "maturities"
.LC5:
.string "delta"
.LC6:
.string "swaprates"
.LC7:
.string "lambda"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z29Pathcalc_Portfolio_KernelGPU2Pf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1N(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL4Nmat(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL4Nopt(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $60, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10maturities(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5delta(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $60, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL9swaprates(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $320, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6lambda(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL6lambda
.comm _ZL6lambda,320,32
.local _ZL9swaprates
.comm _ZL9swaprates,60,32
.local _ZL5delta
.comm _ZL5delta,4,4
.local _ZL10maturities
.comm _ZL10maturities,60,32
.local _ZL4Nopt
.comm _ZL4Nopt,4,4
.local _ZL4Nmat
.comm _ZL4Nmat,4,4
.local _ZL1N
.comm _ZL1N,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //pass
//--blockDim=32 --gridDim=2
#include "../common.h"
__global__ void Pathcalc_Portfolio_KernelGPU2(float *d_v)
{
const int tid = blockDim.x * blockIdx.x + threadIdx.x;
const int threadN = blockDim.x * gridDim.x;
int i, path;
float L[NN], z[NN];
/* Monte Carlo LIBOR path calculation*/
for(path = tid; path < NPATH; path += threadN){
// initialise the data for current thread
for (i=0; i<N; i++) {
// for real application, z should be randomly generated
z[i] = 0.3;
L[i] = 0.05;
}
path_calc(L, z);
d_v[path] = portfolio(L);
}
} | //pass
//--blockDim=32 --gridDim=2
#include <hip/hip_runtime.h>
#include "../common.h"
__global__ void Pathcalc_Portfolio_KernelGPU2(float *d_v)
{
const int tid = blockDim.x * blockIdx.x + threadIdx.x;
const int threadN = blockDim.x * gridDim.x;
int i, path;
float L[NN], z[NN];
/* Monte Carlo LIBOR path calculation*/
for(path = tid; path < NPATH; path += threadN){
// initialise the data for current thread
for (i=0; i<N; i++) {
// for real application, z should be randomly generated
z[i] = 0.3;
L[i] = 0.05;
}
path_calc(L, z);
d_v[path] = portfolio(L);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //pass
//--blockDim=32 --gridDim=2
#include <hip/hip_runtime.h>
#include "../common.h"
__global__ void Pathcalc_Portfolio_KernelGPU2(float *d_v)
{
const int tid = blockDim.x * blockIdx.x + threadIdx.x;
const int threadN = blockDim.x * gridDim.x;
int i, path;
float L[NN], z[NN];
/* Monte Carlo LIBOR path calculation*/
for(path = tid; path < NPATH; path += threadN){
// initialise the data for current thread
for (i=0; i<N; i++) {
// for real application, z should be randomly generated
z[i] = 0.3;
L[i] = 0.05;
}
path_calc(L, z);
d_v[path] = portfolio(L);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z29Pathcalc_Portfolio_KernelGPU2Pf
.globl _Z29Pathcalc_Portfolio_KernelGPU2Pf
.p2align 8
.type _Z29Pathcalc_Portfolio_KernelGPU2Pf,@function
_Z29Pathcalc_Portfolio_KernelGPU2Pf:
s_load_b32 s2, s[0:1], 0x14
s_add_u32 s4, s0, 8
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s14, s2, 0xffff
s_mov_b32 s2, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s14, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x1000, v1
s_cbranch_execz .LBB0_25
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, N@rel32@lo+4
s_addc_u32 s3, s3, N@rel32@hi+12
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s6, s[2:3], 0x0
s_mov_b32 s15, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s14, s4, s14
s_cmp_gt_i32 s6, 0
s_cselect_b32 s7, -1, 0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, Nmat@rel32@lo+4
s_addc_u32 s3, s3, Nmat@rel32@hi+12
s_load_b32 s8, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_gt_i32 s8, 0
s_cselect_b32 s9, -1, 0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, delta@rel32@lo+4
s_addc_u32 s3, s3, delta@rel32@hi+12
s_cmp_lt_i32 s8, s6
s_load_b32 s10, s[2:3], 0x0
s_cselect_b32 s11, -1, 0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, Nopt@rel32@lo+4
s_addc_u32 s3, s3, Nopt@rel32@hi+12
s_load_b32 s12, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_mul_f32_e64 v0, 0x4f800000, s10
v_cmp_gt_f32_e64 vcc_lo, 0xf800000, s10
s_cmp_gt_i32 s12, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, s10, v0, vcc_lo
s_cselect_b32 s13, -1, 0
v_sqrt_f32_e32 v0, v2
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v3, -1, v0
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v5, -v3, v0, v2
v_cmp_ge_f32_e64 s2, 0, v5
v_mov_b32_e32 v5, 0x3d4ccccd
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v6, -v4, v0, v2
v_cndmask_b32_e64 v0, v0, v3, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s2, 0, v6
v_cndmask_b32_e64 v3, v0, v4, s2
s_load_b64 s[2:3], s[0:1], 0x0
s_lshl_b32 s0, s8, 2
v_or_b32_e64 v0, 0x150, 4
v_mov_b32_e32 v4, 0x3e99999a
v_mul_f32_e32 v6, 0x37800000, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v3, v3, v6, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v2, 0x260
v_add_nc_u32_e64 v6, 0x150, s0
v_cndmask_b32_e32 v7, v3, v2, vcc_lo
s_branch .LBB0_4
.LBB0_2:
v_mov_b32_e32 v8, 1.0
.LBB0_3:
s_set_inst_prefetch_distance 0x2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v8, v3, v8
v_lshlrev_b64 v[9:10], 2, v[1:2]
v_add_nc_u32_e32 v1, s14, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_lt_i32_e32 vcc_lo, 0xfff, v1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, s0, s2, v9
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s3, v10, s0
s_or_b32 s15, vcc_lo, s15
global_store_b32 v[2:3], v8, off
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execz .LBB0_25
.LBB0_4:
s_and_not1_b32 vcc_lo, exec_lo, s7
s_cbranch_vccnz .LBB0_7
v_mov_b32_e32 v2, 0x290
v_mov_b32_e32 v3, 0x150
s_mov_b32 s0, s6
.LBB0_6:
scratch_store_b32 v2, v4, off
scratch_store_b32 v3, v5, off
v_add_nc_u32_e32 v2, 4, v2
v_add_nc_u32_e32 v3, 4, v3
s_add_i32 s0, s0, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s0, 0
s_cbranch_scc1 .LBB0_6
.LBB0_7:
s_and_not1_b32 vcc_lo, exec_lo, s9
s_cbranch_vccnz .LBB0_13
v_mov_b32_e32 v8, v0
s_mov_b32 s4, 0
s_branch .LBB0_10
.LBB0_9:
v_add_nc_u32_e32 v8, 4, v8
s_cmp_eq_u32 s4, s8
s_cbranch_scc1 .LBB0_13
.LBB0_10:
s_mov_b32 s0, s4
s_add_i32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s4, s6
s_cbranch_scc1 .LBB0_9
s_lshl_b32 s0, s0, 2
v_mov_b32_e32 v10, v8
s_addk_i32 s0, 0x290
s_mov_b32 s5, s4
scratch_load_b32 v2, off, s0
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, lambda@rel32@lo+4
s_addc_u32 s1, s1, lambda@rel32@hi+12
s_waitcnt vmcnt(0)
v_dual_mov_b32 v9, 0 :: v_dual_mul_f32 v2, v7, v2
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f64_f32_e32 v[2:3], v2
.LBB0_12:
scratch_load_b32 v17, v10, off
s_load_b32 s16, s[0:1], 0x0
s_add_i32 s5, s5, 1
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_ge_i32 s5, s6
s_waitcnt lgkmcnt(0)
v_mul_f32_e64 v13, s10, s16
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f32_e32 v14, v13, v17
v_fma_f32 v15, s10, v17, 1.0
v_div_scale_f32 v16, null, v15, v15, v14
v_div_scale_f32 v19, vcc_lo, v14, v15, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v18, v16
s_waitcnt_depctr 0xfff
v_fma_f32 v11, -v16, v18, 1.0
v_fmac_f32_e32 v18, v11, v18
v_cvt_f64_f32_e32 v[11:12], v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v20, v19, v18
v_fma_f32 v21, -v16, v20, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v20, v21, v18
v_fma_f32 v16, -v16, v20, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v16, v16, v18, v20
v_div_fixup_f32 v14, v16, v15, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v9, v9, v14
v_fma_f64 v[11:12], v[11:12], -0.5, v[2:3]
v_mul_f32_e32 v15, v13, v9
v_cvt_f64_f32_e32 v[13:14], s16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[15:16], v15
v_fma_f64 v[11:12], v[11:12], v[13:14], v[15:16]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_f64_e32 v11, v[11:12]
v_mul_f32_e32 v11, 0x3fb8aa3b, v11
s_delay_alu instid0(VALU_DEP_1)
v_exp_f32_e32 v11, v11
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v11, v17, v11
scratch_store_b32 v10, v11, off
v_add_nc_u32_e32 v10, 4, v10
s_cbranch_scc0 .LBB0_12
s_branch .LBB0_9
.LBB0_13:
s_and_not1_b32 vcc_lo, exec_lo, s11
s_cbranch_vccnz .LBB0_16
v_dual_mov_b32 v2, 0xb0 :: v_dual_mov_b32 v3, 16
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, v6
v_mov_b32_e32 v10, 1.0
s_mov_b32 s0, s8
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_15:
scratch_load_b32 v11, v9, off
v_cvt_f64_f32_e32 v[13:14], v10
v_add_nc_u32_e32 v9, 4, v9
s_add_i32 s0, s0, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_cmp_ge_i32 s0, s6
s_waitcnt vmcnt(0)
v_mul_f32_e32 v11, s10, v11
v_cvt_f64_f32_e32 v[11:12], v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[10:11], v[11:12], 1.0
v_div_scale_f64 v[15:16], null, v[10:11], v[10:11], v[13:14]
v_div_scale_f64 v[21:22], vcc_lo, v[13:14], v[10:11], v[13:14]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[17:18], v[15:16]
s_waitcnt_depctr 0xfff
v_fma_f64 v[19:20], -v[15:16], v[17:18], 1.0
v_fma_f64 v[17:18], v[17:18], v[19:20], v[17:18]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[19:20], -v[15:16], v[17:18], 1.0
v_fma_f64 v[17:18], v[17:18], v[19:20], v[17:18]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[19:20], v[21:22], v[17:18]
v_fma_f64 v[15:16], -v[15:16], v[19:20], v[21:22]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[15:16], v[15:16], v[17:18], v[19:20]
v_div_fixup_f64 v[10:11], v[15:16], v[10:11], v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_f64_e32 v10, v[10:11]
v_fmac_f32_e32 v8, s10, v10
scratch_store_b32 v3, v10, off
v_add_nc_u32_e32 v3, 4, v3
scratch_store_b32 v2, v8, off
v_add_nc_u32_e32 v2, 4, v2
s_cbranch_scc0 .LBB0_15
.LBB0_16:
s_set_inst_prefetch_distance 0x2
s_and_not1_b32 vcc_lo, exec_lo, s13
s_cbranch_vccnz .LBB0_21
v_mov_b32_e32 v3, 0
s_mov_b32 s16, s12
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, swaprates@rel32@lo+4
s_addc_u32 s1, s1, swaprates@rel32@hi+12
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, maturities@rel32@lo+4
s_addc_u32 s5, s5, maturities@rel32@hi+12
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_19
.p2align 6
.LBB0_18:
s_or_b32 exec_lo, exec_lo, s17
s_add_i32 s16, s16, -1
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s16, 0
s_cbranch_scc1 .LBB0_22
.LBB0_19:
s_load_b32 s17, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
s_lshl_b32 s17, s17, 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s17, s17, -4
s_add_i32 s18, s17, 16
s_addk_i32 s17, 0xb0
scratch_load_b32 v2, off, s18
scratch_load_b32 v8, off, s17
s_load_b32 s17, s[0:1], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v2, s17, v8
s_mov_b32 s17, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, -1.0, v2
v_cmpx_gt_f32_e32 0, v2
s_cbranch_execz .LBB0_18
v_cvt_f64_f32_e32 v[8:9], v2
v_cvt_f64_f32_e32 v[2:3], v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], v[8:9], 0xc0590000, v[2:3]
v_cvt_f32_f64_e32 v3, v[2:3]
s_branch .LBB0_18
.LBB0_21:
v_mov_b32_e32 v3, 0
.LBB0_22:
s_set_inst_prefetch_distance 0x2
s_and_not1_b32 vcc_lo, exec_lo, s9
s_cbranch_vccnz .LBB0_2
v_mov_b32_e32 v2, 0x150
v_mov_b32_e32 v8, 1.0
s_mov_b32 s0, s8
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_24:
scratch_load_b32 v9, v2, off
v_cvt_f64_f32_e32 v[11:12], v8
s_add_i32 s0, s0, -1
v_add_nc_u32_e32 v2, 4, v2
s_cmp_lg_u32 s0, 0
s_waitcnt vmcnt(0)
v_mul_f32_e32 v9, s10, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[9:10], v9
v_add_f64 v[8:9], v[9:10], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f64 v[13:14], null, v[8:9], v[8:9], v[11:12]
v_div_scale_f64 v[19:20], vcc_lo, v[11:12], v[8:9], v[11:12]
v_rcp_f64_e32 v[15:16], v[13:14]
s_waitcnt_depctr 0xfff
v_fma_f64 v[17:18], -v[13:14], v[15:16], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16]
v_fma_f64 v[17:18], -v[13:14], v[15:16], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16]
v_mul_f64 v[17:18], v[19:20], v[15:16]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], -v[13:14], v[17:18], v[19:20]
v_div_fmas_f64 v[13:14], v[13:14], v[15:16], v[17:18]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[8:9], v[13:14], v[8:9], v[11:12]
v_cvt_f32_f64_e32 v8, v[8:9]
s_cbranch_scc1 .LBB0_24
s_branch .LBB0_3
.LBB0_25:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z29Pathcalc_Portfolio_KernelGPU2Pf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 976
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 1
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 23
.amdhsa_next_free_sgpr 19
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z29Pathcalc_Portfolio_KernelGPU2Pf, .Lfunc_end0-_Z29Pathcalc_Portfolio_KernelGPU2Pf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected N
.type N,@object
.section .bss,"aw",@nobits
.globl N
.p2align 2, 0x0
N:
.long 0
.size N, 4
.protected Nmat
.type Nmat,@object
.globl Nmat
.p2align 2, 0x0
Nmat:
.long 0
.size Nmat, 4
.protected Nopt
.type Nopt,@object
.globl Nopt
.p2align 2, 0x0
Nopt:
.long 0
.size Nopt, 4
.protected maturities
.type maturities,@object
.globl maturities
.p2align 4, 0x0
maturities:
.zero 60
.size maturities, 60
.protected delta
.type delta,@object
.globl delta
.p2align 2, 0x0
delta:
.long 0x00000000
.size delta, 4
.protected swaprates
.type swaprates,@object
.globl swaprates
.p2align 4, 0x0
swaprates:
.zero 60
.size swaprates, 60
.protected lambda
.type lambda,@object
.globl lambda
.p2align 4, 0x0
lambda:
.zero 320
.size lambda, 320
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym N
.addrsig_sym Nmat
.addrsig_sym Nopt
.addrsig_sym maturities
.addrsig_sym delta
.addrsig_sym swaprates
.addrsig_sym lambda
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z29Pathcalc_Portfolio_KernelGPU2Pf
.private_segment_fixed_size: 976
.sgpr_count: 21
.sgpr_spill_count: 0
.symbol: _Z29Pathcalc_Portfolio_KernelGPU2Pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 23
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //pass
//--blockDim=32 --gridDim=2
#include <hip/hip_runtime.h>
#include "../common.h"
__global__ void Pathcalc_Portfolio_KernelGPU2(float *d_v)
{
const int tid = blockDim.x * blockIdx.x + threadIdx.x;
const int threadN = blockDim.x * gridDim.x;
int i, path;
float L[NN], z[NN];
/* Monte Carlo LIBOR path calculation*/
for(path = tid; path < NPATH; path += threadN){
// initialise the data for current thread
for (i=0; i<N; i++) {
// for real application, z should be randomly generated
z[i] = 0.3;
L[i] = 0.05;
}
path_calc(L, z);
d_v[path] = portfolio(L);
}
} | .text
.file "kernel.hip"
.globl _Z44__device_stub__Pathcalc_Portfolio_KernelGPU2Pf # -- Begin function _Z44__device_stub__Pathcalc_Portfolio_KernelGPU2Pf
.p2align 4, 0x90
.type _Z44__device_stub__Pathcalc_Portfolio_KernelGPU2Pf,@function
_Z44__device_stub__Pathcalc_Portfolio_KernelGPU2Pf: # @_Z44__device_stub__Pathcalc_Portfolio_KernelGPU2Pf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z29Pathcalc_Portfolio_KernelGPU2Pf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z44__device_stub__Pathcalc_Portfolio_KernelGPU2Pf, .Lfunc_end0-_Z44__device_stub__Pathcalc_Portfolio_KernelGPU2Pf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z29Pathcalc_Portfolio_KernelGPU2Pf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $N, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $Nmat, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $Nopt, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $maturities, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movl $60, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $delta, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $swaprates, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movl $60, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $lambda, %esi
movl $.L__unnamed_8, %edx
movl $.L__unnamed_8, %ecx
movl $320, %r9d # imm = 0x140
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type N,@object # @N
.local N
.comm N,4,4
.type Nmat,@object # @Nmat
.local Nmat
.comm Nmat,4,4
.type Nopt,@object # @Nopt
.local Nopt
.comm Nopt,4,4
.type maturities,@object # @maturities
.local maturities
.comm maturities,60,16
.type delta,@object # @delta
.local delta
.comm delta,4,4
.type swaprates,@object # @swaprates
.local swaprates
.comm swaprates,60,16
.type lambda,@object # @lambda
.local lambda
.comm lambda,320,16
.type _Z29Pathcalc_Portfolio_KernelGPU2Pf,@object # @_Z29Pathcalc_Portfolio_KernelGPU2Pf
.section .rodata,"a",@progbits
.globl _Z29Pathcalc_Portfolio_KernelGPU2Pf
.p2align 3, 0x0
_Z29Pathcalc_Portfolio_KernelGPU2Pf:
.quad _Z44__device_stub__Pathcalc_Portfolio_KernelGPU2Pf
.size _Z29Pathcalc_Portfolio_KernelGPU2Pf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z29Pathcalc_Portfolio_KernelGPU2Pf"
.size .L__unnamed_1, 36
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "N"
.size .L__unnamed_2, 2
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "Nmat"
.size .L__unnamed_3, 5
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "Nopt"
.size .L__unnamed_4, 5
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "maturities"
.size .L__unnamed_5, 11
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "delta"
.size .L__unnamed_6, 6
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "swaprates"
.size .L__unnamed_7, 10
.type .L__unnamed_8,@object # @7
.L__unnamed_8:
.asciz "lambda"
.size .L__unnamed_8, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z44__device_stub__Pathcalc_Portfolio_KernelGPU2Pf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym N
.addrsig_sym Nmat
.addrsig_sym Nopt
.addrsig_sym maturities
.addrsig_sym delta
.addrsig_sym swaprates
.addrsig_sym lambda
.addrsig_sym _Z29Pathcalc_Portfolio_KernelGPU2Pf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000fb4af_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2034:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2034:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z29Pathcalc_Portfolio_KernelGPU2PfPf
.type _Z49__device_stub__Z29Pathcalc_Portfolio_KernelGPU2PfPf, @function
_Z49__device_stub__Z29Pathcalc_Portfolio_KernelGPU2PfPf:
.LFB2056:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z29Pathcalc_Portfolio_KernelGPU2Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2056:
.size _Z49__device_stub__Z29Pathcalc_Portfolio_KernelGPU2PfPf, .-_Z49__device_stub__Z29Pathcalc_Portfolio_KernelGPU2PfPf
.globl _Z29Pathcalc_Portfolio_KernelGPU2Pf
.type _Z29Pathcalc_Portfolio_KernelGPU2Pf, @function
_Z29Pathcalc_Portfolio_KernelGPU2Pf:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z29Pathcalc_Portfolio_KernelGPU2PfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z29Pathcalc_Portfolio_KernelGPU2Pf, .-_Z29Pathcalc_Portfolio_KernelGPU2Pf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z29Pathcalc_Portfolio_KernelGPU2Pf"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "N"
.LC2:
.string "Nmat"
.LC3:
.string "Nopt"
.LC4:
.string "maturities"
.LC5:
.string "delta"
.LC6:
.string "swaprates"
.LC7:
.string "lambda"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z29Pathcalc_Portfolio_KernelGPU2Pf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1N(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL4Nmat(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL4Nopt(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $60, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10maturities(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5delta(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $60, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL9swaprates(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $320, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6lambda(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL6lambda
.comm _ZL6lambda,320,32
.local _ZL9swaprates
.comm _ZL9swaprates,60,32
.local _ZL5delta
.comm _ZL5delta,4,4
.local _ZL10maturities
.comm _ZL10maturities,60,32
.local _ZL4Nopt
.comm _ZL4Nopt,4,4
.local _ZL4Nmat
.comm _ZL4Nmat,4,4
.local _ZL1N
.comm _ZL1N,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z44__device_stub__Pathcalc_Portfolio_KernelGPU2Pf # -- Begin function _Z44__device_stub__Pathcalc_Portfolio_KernelGPU2Pf
.p2align 4, 0x90
.type _Z44__device_stub__Pathcalc_Portfolio_KernelGPU2Pf,@function
_Z44__device_stub__Pathcalc_Portfolio_KernelGPU2Pf: # @_Z44__device_stub__Pathcalc_Portfolio_KernelGPU2Pf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z29Pathcalc_Portfolio_KernelGPU2Pf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z44__device_stub__Pathcalc_Portfolio_KernelGPU2Pf, .Lfunc_end0-_Z44__device_stub__Pathcalc_Portfolio_KernelGPU2Pf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z29Pathcalc_Portfolio_KernelGPU2Pf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $N, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $Nmat, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $Nopt, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $maturities, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movl $60, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $delta, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $swaprates, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movl $60, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $lambda, %esi
movl $.L__unnamed_8, %edx
movl $.L__unnamed_8, %ecx
movl $320, %r9d # imm = 0x140
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type N,@object # @N
.local N
.comm N,4,4
.type Nmat,@object # @Nmat
.local Nmat
.comm Nmat,4,4
.type Nopt,@object # @Nopt
.local Nopt
.comm Nopt,4,4
.type maturities,@object # @maturities
.local maturities
.comm maturities,60,16
.type delta,@object # @delta
.local delta
.comm delta,4,4
.type swaprates,@object # @swaprates
.local swaprates
.comm swaprates,60,16
.type lambda,@object # @lambda
.local lambda
.comm lambda,320,16
.type _Z29Pathcalc_Portfolio_KernelGPU2Pf,@object # @_Z29Pathcalc_Portfolio_KernelGPU2Pf
.section .rodata,"a",@progbits
.globl _Z29Pathcalc_Portfolio_KernelGPU2Pf
.p2align 3, 0x0
_Z29Pathcalc_Portfolio_KernelGPU2Pf:
.quad _Z44__device_stub__Pathcalc_Portfolio_KernelGPU2Pf
.size _Z29Pathcalc_Portfolio_KernelGPU2Pf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z29Pathcalc_Portfolio_KernelGPU2Pf"
.size .L__unnamed_1, 36
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "N"
.size .L__unnamed_2, 2
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "Nmat"
.size .L__unnamed_3, 5
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "Nopt"
.size .L__unnamed_4, 5
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "maturities"
.size .L__unnamed_5, 11
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "delta"
.size .L__unnamed_6, 6
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "swaprates"
.size .L__unnamed_7, 10
.type .L__unnamed_8,@object # @7
.L__unnamed_8:
.asciz "lambda"
.size .L__unnamed_8, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z44__device_stub__Pathcalc_Portfolio_KernelGPU2Pf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym N
.addrsig_sym Nmat
.addrsig_sym Nopt
.addrsig_sym maturities
.addrsig_sym delta
.addrsig_sym swaprates
.addrsig_sym lambda
.addrsig_sym _Z29Pathcalc_Portfolio_KernelGPU2Pf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /**
* jrc3_cuda_delta.cu
* block loading delta calculation. should be much faster
* system('nvcc -ptx -m 64 -arch sm_35 jrc3_cuda_rho.cu')
* iA is multiple of CHUNK (16)
* J. James Jun, Vidrio Technologies, LLC., 2017 Jun 11
*/
#include <cuda_runtime.h>
// #include "cublas_v2.h"
#include <math.h>
#define ABS(my_val) ((my_val) < 0) ? (-1*(my_val)) : (my_val)
#define MIN(A,B) ((A)<(B)) ? (A) : (B)
#define MAX(A,B) ((A)>(B)) ? (A) : (B)
#define NTHREADS 128
#define NC 45 // number of Channels
#define CHUNK 16 //previously defined as CHUNK
#define SINGLE_INF (3.402E+38)
/** Main entry point.
* Works out where the current thread should read/write to global memory
* and calls doIterations to do the actual work.
* Step through one B at a time
* 7/13/17: fDc_spk option added, which uses spike-specific distance cut-off (dc)
*/
// % Matlab syntax
// mrDist12_ = eucl2_dist_(mrFet12, mrFet12(:,1:n1)); %not sqrt
// mlRemove12_ = bsxfun(@ge, viiRho12_ord, viiRho12_ord(1:n1)') ...
// | abs(bsxfun(@minus, viiSpk12_ord_, viiSpk12_ord_(1:n1)')) > dn_max;
// mrDist12_(mlRemove12_) = nan;
// [vrDelta1, viNneigh1] = min(mrDist12_);
__global__ void jrc3_cuda_delta(float * vrDelta1, unsigned int * viNneigh1, const float * mrFet12, const int * viiSpk12_ord, const int * viiRho12_ord, const int * vnConst, const float dc2){
// int iA = blockIdx.x * CHUNK;
int i1 = (blockIdx.x + blockIdx.y * gridDim.x) * CHUNK; // base index of i1
int tx = threadIdx.x;
int i1_tx = i1 + tx;
int n1 = vnConst[0];
int n12 = vnConst[1];
int nC = vnConst[2];
int dn_max = vnConst[3];
int fDc_spk = vnConst[4];
__shared__ int viiSpk1_ord_[CHUNK];
__shared__ int viiRho1_ord_[CHUNK];
__shared__ float mrFet1_[NC][CHUNK];
__shared__ float mrDelta1_[NTHREADS][CHUNK];
__shared__ unsigned int miNneigh1_[NTHREADS][CHUNK];
__shared__ float vrDc1_[CHUNK]; // use if fDc_spk=1
// cache shared memory
if (tx < nC){ //use tx as iC
for (int i_c = 0; i_c < CHUNK; ++i_c){
int i1_c = i_c + i1;
if (i1_c < n1){
mrFet1_[tx][i_c] = mrFet12[tx + i1_c * nC];
}else{
mrFet1_[tx][i_c] = 0.0f;
}
}
}
if (tx < CHUNK && i1_tx < n1){
viiSpk1_ord_[tx] = viiSpk12_ord[i1_tx];
viiRho1_ord_[tx] = viiRho12_ord[i1_tx];
}
float vr_minDist1[CHUNK];
unsigned int vi_minIdx1[CHUNK];
for (int i_c = 0; i_c < CHUNK; ++i_c){
vr_minDist1[i_c] = SINGLE_INF;
vi_minIdx1[i_c] = i1 + i_c; // self
}
// calculate spike-specific distance cut-off vrDc1_ only if fDc_spk==1
if (tx < CHUNK && fDc_spk==1){
vrDc1_[tx] = 0.0f; //init
//for (int iC = 0; iC < 1; ++iC){ //center only scale
for (int iC = 0; iC < nC; ++iC){
float temp_ = mrFet1_[iC][tx];
vrDc1_[tx] += (temp_ * temp_);
}
vrDc1_[tx] *= dc2;
}
__syncthreads();
// fill in the shared memory A
for (int i12_tx = tx; i12_tx < n12; i12_tx += blockDim.x){
//for (int i12_tx = 1; i12_tx < n12; ++i12_tx){
// compute time difference
char vlDist_c[CHUNK];
int iiSpk12_ord_tx = viiSpk12_ord[i12_tx];
int iiRho12_ord_tx = viiRho12_ord[i12_tx];
for (int i_c = 0; i_c < CHUNK; ++i_c){
char di_rho_ = (iiRho12_ord_tx < viiRho1_ord_[i_c]);
int di_spk_ = ABS(viiSpk1_ord_[i_c] - iiSpk12_ord_tx);
vlDist_c[i_c] = (di_spk_ <= dn_max) && di_rho_;
}
// compute distance
float vrDist_c[CHUNK];
for (int i_c = 0; i_c < CHUNK; ++i_c) vrDist_c[i_c] = 0.0f;
for (int iC = 0; iC < nC; ++iC){
float fet12_tx = mrFet12[iC + i12_tx * nC];
for (int i_c = 0; i_c < CHUNK; ++i_c){
float temp = fet12_tx - mrFet1_[iC][i_c];
vrDist_c[i_c] += temp * temp;
}
}
// Compare the index and distance
for (int i_c = 0; i_c < CHUNK; ++i_c){
if (vrDist_c[i_c] < vr_minDist1[i_c]){
if (vlDist_c[i_c] == 1){
vr_minDist1[i_c] = vrDist_c[i_c];
vi_minIdx1[i_c] = i12_tx;
}
}
}
} // while
// collect result from each thread
for (int i_c = 0; i_c < CHUNK; ++i_c){
mrDelta1_[tx][i_c] = vr_minDist1[i_c];
miNneigh1_[tx][i_c] = vi_minIdx1[i_c];
}
__syncthreads();
// final count
//if (tx < CHUNK && i1_tx < n1){
if (tx < CHUNK){
float minDist1 = SINGLE_INF;
unsigned int minIdx1 = i1_tx;
for (int tx1=0; tx1<blockDim.x; ++tx1){
if (mrDelta1_[tx1][tx] < minDist1){
minDist1 = mrDelta1_[tx1][tx];
minIdx1 = miNneigh1_[tx1][tx];
}
}
//vrDelta1[i1_tx] = sqrtf(minDist1);
if (i1_tx < n1){
// vrDelta_ = sqrt(abs(single(vrDelta_) / vrDc2_site(iSite))); %normalize and convert dist
if (fDc_spk==0){
vrDelta1[i1_tx] = sqrtf(ABS(minDist1) / dc2);
}else{
vrDelta1[i1_tx] = sqrtf(ABS(minDist1) / vrDc1_[tx]);
//vrDelta1[i1_tx] = sqrtf(ABS(minDist1));
}
viNneigh1[i1_tx] = minIdx1 + 1; //Matlab index output
}
}
} // func | .file "tmpxft_000ebeb9_00000000-6_irc_cuda_delta.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_fPfPjPKfPKiS4_S4_f
.type _Z50__device_stub__Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_fPfPjPKfPKiS4_S4_f, @function
_Z50__device_stub__Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_fPfPjPKfPKiS4_S4_f:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_f(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_fPfPjPKfPKiS4_S4_f, .-_Z50__device_stub__Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_fPfPjPKfPKiS4_S4_f
.globl _Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_f
.type _Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_f, @function
_Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_f:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_fPfPjPKfPKiS4_S4_f
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_f, .-_Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_f
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_f"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_f(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
* jrc3_cuda_delta.cu
* block loading delta calculation. should be much faster
* system('nvcc -ptx -m 64 -arch sm_35 jrc3_cuda_rho.cu')
* iA is multiple of CHUNK (16)
* J. James Jun, Vidrio Technologies, LLC., 2017 Jun 11
*/
#include <cuda_runtime.h>
// #include "cublas_v2.h"
#include <math.h>
#define ABS(my_val) ((my_val) < 0) ? (-1*(my_val)) : (my_val)
#define MIN(A,B) ((A)<(B)) ? (A) : (B)
#define MAX(A,B) ((A)>(B)) ? (A) : (B)
#define NTHREADS 128
#define NC 45 // number of Channels
#define CHUNK 16 //previously defined as CHUNK
#define SINGLE_INF (3.402E+38)
/** Main entry point.
* Works out where the current thread should read/write to global memory
* and calls doIterations to do the actual work.
* Step through one B at a time
* 7/13/17: fDc_spk option added, which uses spike-specific distance cut-off (dc)
*/
// % Matlab syntax
// mrDist12_ = eucl2_dist_(mrFet12, mrFet12(:,1:n1)); %not sqrt
// mlRemove12_ = bsxfun(@ge, viiRho12_ord, viiRho12_ord(1:n1)') ...
// | abs(bsxfun(@minus, viiSpk12_ord_, viiSpk12_ord_(1:n1)')) > dn_max;
// mrDist12_(mlRemove12_) = nan;
// [vrDelta1, viNneigh1] = min(mrDist12_);
__global__ void jrc3_cuda_delta(float * vrDelta1, unsigned int * viNneigh1, const float * mrFet12, const int * viiSpk12_ord, const int * viiRho12_ord, const int * vnConst, const float dc2){
// int iA = blockIdx.x * CHUNK;
int i1 = (blockIdx.x + blockIdx.y * gridDim.x) * CHUNK; // base index of i1
int tx = threadIdx.x;
int i1_tx = i1 + tx;
int n1 = vnConst[0];
int n12 = vnConst[1];
int nC = vnConst[2];
int dn_max = vnConst[3];
int fDc_spk = vnConst[4];
__shared__ int viiSpk1_ord_[CHUNK];
__shared__ int viiRho1_ord_[CHUNK];
__shared__ float mrFet1_[NC][CHUNK];
__shared__ float mrDelta1_[NTHREADS][CHUNK];
__shared__ unsigned int miNneigh1_[NTHREADS][CHUNK];
__shared__ float vrDc1_[CHUNK]; // use if fDc_spk=1
// cache shared memory
if (tx < nC){ //use tx as iC
for (int i_c = 0; i_c < CHUNK; ++i_c){
int i1_c = i_c + i1;
if (i1_c < n1){
mrFet1_[tx][i_c] = mrFet12[tx + i1_c * nC];
}else{
mrFet1_[tx][i_c] = 0.0f;
}
}
}
if (tx < CHUNK && i1_tx < n1){
viiSpk1_ord_[tx] = viiSpk12_ord[i1_tx];
viiRho1_ord_[tx] = viiRho12_ord[i1_tx];
}
float vr_minDist1[CHUNK];
unsigned int vi_minIdx1[CHUNK];
for (int i_c = 0; i_c < CHUNK; ++i_c){
vr_minDist1[i_c] = SINGLE_INF;
vi_minIdx1[i_c] = i1 + i_c; // self
}
// calculate spike-specific distance cut-off vrDc1_ only if fDc_spk==1
if (tx < CHUNK && fDc_spk==1){
vrDc1_[tx] = 0.0f; //init
//for (int iC = 0; iC < 1; ++iC){ //center only scale
for (int iC = 0; iC < nC; ++iC){
float temp_ = mrFet1_[iC][tx];
vrDc1_[tx] += (temp_ * temp_);
}
vrDc1_[tx] *= dc2;
}
__syncthreads();
// fill in the shared memory A
for (int i12_tx = tx; i12_tx < n12; i12_tx += blockDim.x){
//for (int i12_tx = 1; i12_tx < n12; ++i12_tx){
// compute time difference
char vlDist_c[CHUNK];
int iiSpk12_ord_tx = viiSpk12_ord[i12_tx];
int iiRho12_ord_tx = viiRho12_ord[i12_tx];
for (int i_c = 0; i_c < CHUNK; ++i_c){
char di_rho_ = (iiRho12_ord_tx < viiRho1_ord_[i_c]);
int di_spk_ = ABS(viiSpk1_ord_[i_c] - iiSpk12_ord_tx);
vlDist_c[i_c] = (di_spk_ <= dn_max) && di_rho_;
}
// compute distance
float vrDist_c[CHUNK];
for (int i_c = 0; i_c < CHUNK; ++i_c) vrDist_c[i_c] = 0.0f;
for (int iC = 0; iC < nC; ++iC){
float fet12_tx = mrFet12[iC + i12_tx * nC];
for (int i_c = 0; i_c < CHUNK; ++i_c){
float temp = fet12_tx - mrFet1_[iC][i_c];
vrDist_c[i_c] += temp * temp;
}
}
// Compare the index and distance
for (int i_c = 0; i_c < CHUNK; ++i_c){
if (vrDist_c[i_c] < vr_minDist1[i_c]){
if (vlDist_c[i_c] == 1){
vr_minDist1[i_c] = vrDist_c[i_c];
vi_minIdx1[i_c] = i12_tx;
}
}
}
} // while
// collect result from each thread
for (int i_c = 0; i_c < CHUNK; ++i_c){
mrDelta1_[tx][i_c] = vr_minDist1[i_c];
miNneigh1_[tx][i_c] = vi_minIdx1[i_c];
}
__syncthreads();
// final count
//if (tx < CHUNK && i1_tx < n1){
if (tx < CHUNK){
float minDist1 = SINGLE_INF;
unsigned int minIdx1 = i1_tx;
for (int tx1=0; tx1<blockDim.x; ++tx1){
if (mrDelta1_[tx1][tx] < minDist1){
minDist1 = mrDelta1_[tx1][tx];
minIdx1 = miNneigh1_[tx1][tx];
}
}
//vrDelta1[i1_tx] = sqrtf(minDist1);
if (i1_tx < n1){
// vrDelta_ = sqrt(abs(single(vrDelta_) / vrDc2_site(iSite))); %normalize and convert dist
if (fDc_spk==0){
vrDelta1[i1_tx] = sqrtf(ABS(minDist1) / dc2);
}else{
vrDelta1[i1_tx] = sqrtf(ABS(minDist1) / vrDc1_[tx]);
//vrDelta1[i1_tx] = sqrtf(ABS(minDist1));
}
viNneigh1[i1_tx] = minIdx1 + 1; //Matlab index output
}
}
} // func | /**
* jrc3_cuda_delta.cu
* block loading delta calculation. should be much faster
* system('nvcc -ptx -m 64 -arch sm_35 jrc3_cuda_rho.cu')
* iA is multiple of CHUNK (16)
* J. James Jun, Vidrio Technologies, LLC., 2017 Jun 11
*/
#include <hip/hip_runtime.h>
// #include "cublas_v2.h"
#include <math.h>
#define ABS(my_val) ((my_val) < 0) ? (-1*(my_val)) : (my_val)
#define MIN(A,B) ((A)<(B)) ? (A) : (B)
#define MAX(A,B) ((A)>(B)) ? (A) : (B)
#define NTHREADS 128
#define NC 45 // number of Channels
#define CHUNK 16 //previously defined as CHUNK
#define SINGLE_INF (3.402E+38)
/** Main entry point.
* Works out where the current thread should read/write to global memory
* and calls doIterations to do the actual work.
* Step through one B at a time
* 7/13/17: fDc_spk option added, which uses spike-specific distance cut-off (dc)
*/
// % Matlab syntax
// mrDist12_ = eucl2_dist_(mrFet12, mrFet12(:,1:n1)); %not sqrt
// mlRemove12_ = bsxfun(@ge, viiRho12_ord, viiRho12_ord(1:n1)') ...
// | abs(bsxfun(@minus, viiSpk12_ord_, viiSpk12_ord_(1:n1)')) > dn_max;
// mrDist12_(mlRemove12_) = nan;
// [vrDelta1, viNneigh1] = min(mrDist12_);
__global__ void jrc3_cuda_delta(float * vrDelta1, unsigned int * viNneigh1, const float * mrFet12, const int * viiSpk12_ord, const int * viiRho12_ord, const int * vnConst, const float dc2){
// int iA = blockIdx.x * CHUNK;
int i1 = (blockIdx.x + blockIdx.y * gridDim.x) * CHUNK; // base index of i1
int tx = threadIdx.x;
int i1_tx = i1 + tx;
int n1 = vnConst[0];
int n12 = vnConst[1];
int nC = vnConst[2];
int dn_max = vnConst[3];
int fDc_spk = vnConst[4];
__shared__ int viiSpk1_ord_[CHUNK];
__shared__ int viiRho1_ord_[CHUNK];
__shared__ float mrFet1_[NC][CHUNK];
__shared__ float mrDelta1_[NTHREADS][CHUNK];
__shared__ unsigned int miNneigh1_[NTHREADS][CHUNK];
__shared__ float vrDc1_[CHUNK]; // use if fDc_spk=1
// cache shared memory
if (tx < nC){ //use tx as iC
for (int i_c = 0; i_c < CHUNK; ++i_c){
int i1_c = i_c + i1;
if (i1_c < n1){
mrFet1_[tx][i_c] = mrFet12[tx + i1_c * nC];
}else{
mrFet1_[tx][i_c] = 0.0f;
}
}
}
if (tx < CHUNK && i1_tx < n1){
viiSpk1_ord_[tx] = viiSpk12_ord[i1_tx];
viiRho1_ord_[tx] = viiRho12_ord[i1_tx];
}
float vr_minDist1[CHUNK];
unsigned int vi_minIdx1[CHUNK];
for (int i_c = 0; i_c < CHUNK; ++i_c){
vr_minDist1[i_c] = SINGLE_INF;
vi_minIdx1[i_c] = i1 + i_c; // self
}
// calculate spike-specific distance cut-off vrDc1_ only if fDc_spk==1
if (tx < CHUNK && fDc_spk==1){
vrDc1_[tx] = 0.0f; //init
//for (int iC = 0; iC < 1; ++iC){ //center only scale
for (int iC = 0; iC < nC; ++iC){
float temp_ = mrFet1_[iC][tx];
vrDc1_[tx] += (temp_ * temp_);
}
vrDc1_[tx] *= dc2;
}
__syncthreads();
// fill in the shared memory A
for (int i12_tx = tx; i12_tx < n12; i12_tx += blockDim.x){
//for (int i12_tx = 1; i12_tx < n12; ++i12_tx){
// compute time difference
char vlDist_c[CHUNK];
int iiSpk12_ord_tx = viiSpk12_ord[i12_tx];
int iiRho12_ord_tx = viiRho12_ord[i12_tx];
for (int i_c = 0; i_c < CHUNK; ++i_c){
char di_rho_ = (iiRho12_ord_tx < viiRho1_ord_[i_c]);
int di_spk_ = ABS(viiSpk1_ord_[i_c] - iiSpk12_ord_tx);
vlDist_c[i_c] = (di_spk_ <= dn_max) && di_rho_;
}
// compute distance
float vrDist_c[CHUNK];
for (int i_c = 0; i_c < CHUNK; ++i_c) vrDist_c[i_c] = 0.0f;
for (int iC = 0; iC < nC; ++iC){
float fet12_tx = mrFet12[iC + i12_tx * nC];
for (int i_c = 0; i_c < CHUNK; ++i_c){
float temp = fet12_tx - mrFet1_[iC][i_c];
vrDist_c[i_c] += temp * temp;
}
}
// Compare the index and distance
for (int i_c = 0; i_c < CHUNK; ++i_c){
if (vrDist_c[i_c] < vr_minDist1[i_c]){
if (vlDist_c[i_c] == 1){
vr_minDist1[i_c] = vrDist_c[i_c];
vi_minIdx1[i_c] = i12_tx;
}
}
}
} // while
// collect result from each thread
for (int i_c = 0; i_c < CHUNK; ++i_c){
mrDelta1_[tx][i_c] = vr_minDist1[i_c];
miNneigh1_[tx][i_c] = vi_minIdx1[i_c];
}
__syncthreads();
// final count
//if (tx < CHUNK && i1_tx < n1){
if (tx < CHUNK){
float minDist1 = SINGLE_INF;
unsigned int minIdx1 = i1_tx;
for (int tx1=0; tx1<blockDim.x; ++tx1){
if (mrDelta1_[tx1][tx] < minDist1){
minDist1 = mrDelta1_[tx1][tx];
minIdx1 = miNneigh1_[tx1][tx];
}
}
//vrDelta1[i1_tx] = sqrtf(minDist1);
if (i1_tx < n1){
// vrDelta_ = sqrt(abs(single(vrDelta_) / vrDc2_site(iSite))); %normalize and convert dist
if (fDc_spk==0){
vrDelta1[i1_tx] = sqrtf(ABS(minDist1) / dc2);
}else{
vrDelta1[i1_tx] = sqrtf(ABS(minDist1) / vrDc1_[tx]);
//vrDelta1[i1_tx] = sqrtf(ABS(minDist1));
}
viNneigh1[i1_tx] = minIdx1 + 1; //Matlab index output
}
}
} // func |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /**
* jrc3_cuda_delta.cu
* block loading delta calculation. should be much faster
* system('nvcc -ptx -m 64 -arch sm_35 jrc3_cuda_rho.cu')
* iA is multiple of CHUNK (16)
* J. James Jun, Vidrio Technologies, LLC., 2017 Jun 11
*/
#include <hip/hip_runtime.h>
// #include "cublas_v2.h"
#include <math.h>
#define ABS(my_val) ((my_val) < 0) ? (-1*(my_val)) : (my_val)
#define MIN(A,B) ((A)<(B)) ? (A) : (B)
#define MAX(A,B) ((A)>(B)) ? (A) : (B)
#define NTHREADS 128
#define NC 45 // number of Channels
#define CHUNK 16 //previously defined as CHUNK
#define SINGLE_INF (3.402E+38)
/** Main entry point.
* Works out where the current thread should read/write to global memory
* and calls doIterations to do the actual work.
* Step through one B at a time
* 7/13/17: fDc_spk option added, which uses spike-specific distance cut-off (dc)
*/
// % Matlab syntax
// mrDist12_ = eucl2_dist_(mrFet12, mrFet12(:,1:n1)); %not sqrt
// mlRemove12_ = bsxfun(@ge, viiRho12_ord, viiRho12_ord(1:n1)') ...
// | abs(bsxfun(@minus, viiSpk12_ord_, viiSpk12_ord_(1:n1)')) > dn_max;
// mrDist12_(mlRemove12_) = nan;
// [vrDelta1, viNneigh1] = min(mrDist12_);
__global__ void jrc3_cuda_delta(float * vrDelta1, unsigned int * viNneigh1, const float * mrFet12, const int * viiSpk12_ord, const int * viiRho12_ord, const int * vnConst, const float dc2){
// int iA = blockIdx.x * CHUNK;
int i1 = (blockIdx.x + blockIdx.y * gridDim.x) * CHUNK; // base index of i1
int tx = threadIdx.x;
int i1_tx = i1 + tx;
int n1 = vnConst[0];
int n12 = vnConst[1];
int nC = vnConst[2];
int dn_max = vnConst[3];
int fDc_spk = vnConst[4];
__shared__ int viiSpk1_ord_[CHUNK];
__shared__ int viiRho1_ord_[CHUNK];
__shared__ float mrFet1_[NC][CHUNK];
__shared__ float mrDelta1_[NTHREADS][CHUNK];
__shared__ unsigned int miNneigh1_[NTHREADS][CHUNK];
__shared__ float vrDc1_[CHUNK]; // use if fDc_spk=1
// cache shared memory
if (tx < nC){ //use tx as iC
for (int i_c = 0; i_c < CHUNK; ++i_c){
int i1_c = i_c + i1;
if (i1_c < n1){
mrFet1_[tx][i_c] = mrFet12[tx + i1_c * nC];
}else{
mrFet1_[tx][i_c] = 0.0f;
}
}
}
if (tx < CHUNK && i1_tx < n1){
viiSpk1_ord_[tx] = viiSpk12_ord[i1_tx];
viiRho1_ord_[tx] = viiRho12_ord[i1_tx];
}
float vr_minDist1[CHUNK];
unsigned int vi_minIdx1[CHUNK];
for (int i_c = 0; i_c < CHUNK; ++i_c){
vr_minDist1[i_c] = SINGLE_INF;
vi_minIdx1[i_c] = i1 + i_c; // self
}
// calculate spike-specific distance cut-off vrDc1_ only if fDc_spk==1
if (tx < CHUNK && fDc_spk==1){
vrDc1_[tx] = 0.0f; //init
//for (int iC = 0; iC < 1; ++iC){ //center only scale
for (int iC = 0; iC < nC; ++iC){
float temp_ = mrFet1_[iC][tx];
vrDc1_[tx] += (temp_ * temp_);
}
vrDc1_[tx] *= dc2;
}
__syncthreads();
// fill in the shared memory A
for (int i12_tx = tx; i12_tx < n12; i12_tx += blockDim.x){
//for (int i12_tx = 1; i12_tx < n12; ++i12_tx){
// compute time difference
char vlDist_c[CHUNK];
int iiSpk12_ord_tx = viiSpk12_ord[i12_tx];
int iiRho12_ord_tx = viiRho12_ord[i12_tx];
for (int i_c = 0; i_c < CHUNK; ++i_c){
char di_rho_ = (iiRho12_ord_tx < viiRho1_ord_[i_c]);
int di_spk_ = ABS(viiSpk1_ord_[i_c] - iiSpk12_ord_tx);
vlDist_c[i_c] = (di_spk_ <= dn_max) && di_rho_;
}
// compute distance
float vrDist_c[CHUNK];
for (int i_c = 0; i_c < CHUNK; ++i_c) vrDist_c[i_c] = 0.0f;
for (int iC = 0; iC < nC; ++iC){
float fet12_tx = mrFet12[iC + i12_tx * nC];
for (int i_c = 0; i_c < CHUNK; ++i_c){
float temp = fet12_tx - mrFet1_[iC][i_c];
vrDist_c[i_c] += temp * temp;
}
}
// Compare the index and distance
for (int i_c = 0; i_c < CHUNK; ++i_c){
if (vrDist_c[i_c] < vr_minDist1[i_c]){
if (vlDist_c[i_c] == 1){
vr_minDist1[i_c] = vrDist_c[i_c];
vi_minIdx1[i_c] = i12_tx;
}
}
}
} // while
// collect result from each thread
for (int i_c = 0; i_c < CHUNK; ++i_c){
mrDelta1_[tx][i_c] = vr_minDist1[i_c];
miNneigh1_[tx][i_c] = vi_minIdx1[i_c];
}
__syncthreads();
// final count
//if (tx < CHUNK && i1_tx < n1){
if (tx < CHUNK){
float minDist1 = SINGLE_INF;
unsigned int minIdx1 = i1_tx;
for (int tx1=0; tx1<blockDim.x; ++tx1){
if (mrDelta1_[tx1][tx] < minDist1){
minDist1 = mrDelta1_[tx1][tx];
minIdx1 = miNneigh1_[tx1][tx];
}
}
//vrDelta1[i1_tx] = sqrtf(minDist1);
if (i1_tx < n1){
// vrDelta_ = sqrt(abs(single(vrDelta_) / vrDc2_site(iSite))); %normalize and convert dist
if (fDc_spk==0){
vrDelta1[i1_tx] = sqrtf(ABS(minDist1) / dc2);
}else{
vrDelta1[i1_tx] = sqrtf(ABS(minDist1) / vrDc1_[tx]);
//vrDelta1[i1_tx] = sqrtf(ABS(minDist1));
}
viNneigh1[i1_tx] = minIdx1 + 1; //Matlab index output
}
}
} // func | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_f
.globl _Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_f
.p2align 8
.type _Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_f,@function
_Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_f:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x28
s_load_b32 s4, s[0:1], 0x38
s_add_u32 s12, s0, 56
s_addc_u32 s13, s1, 0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_load_b32 s18, s[2:3], 0x8
s_load_b64 s[16:17], s[0:1], 0x10
s_load_b32 s5, s[2:3], 0x0
s_mul_i32 s4, s4, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s4, s14
s_lshl_b32 s15, s7, 4
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s18, v0
s_cbranch_execz .LBB0_5
s_mul_i32 s7, s18, s7
v_lshl_add_u32 v3, v0, 6, 0x4000
v_lshl_add_u32 v1, s7, 4, v0
s_mov_b32 s7, 0
s_mov_b32 s8, s15
s_branch .LBB0_3
.p2align 6
.LBB0_2:
v_add_nc_u32_e32 v4, s7, v3
v_add_nc_u32_e32 v1, s18, v1
s_add_i32 s7, s7, 4
s_add_i32 s8, s8, 1
s_cmp_lg_u32 s7, 64
s_waitcnt vmcnt(0)
ds_store_b32 v4, v2
s_cbranch_scc0 .LBB0_5
.LBB0_3:
v_mov_b32_e32 v2, 0
s_cmp_ge_i32 s8, s5
s_cbranch_scc1 .LBB0_2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s16, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s17, v5, vcc_lo
global_load_b32 v2, v[4:5], off
s_branch .LBB0_2
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s6
s_clause 0x1
s_load_b32 s19, s[2:3], 0x4
s_load_b64 s[6:7], s[2:3], 0xc
s_load_b128 s[8:11], s[0:1], 0x18
v_add_nc_u32_e32 v81, s15, v0
v_cmp_gt_u32_e64 s3, 16, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v81
s_and_b32 s15, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s15
s_cbranch_execz .LBB0_7
v_ashrrev_i32_e32 v82, 31, v81
s_movk_i32 s15, 0x4800
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[81:82]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s8, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, s10, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s11, v2, vcc_lo
global_load_b32 v3, v[3:4], off
global_load_b32 v1, v[1:2], off
v_lshlrev_b32_e32 v2, 2, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v2, s15, v2
s_waitcnt vmcnt(0)
ds_store_2addr_b32 v2, v1, v3 offset0:208 offset1:224
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s5
s_lshl_b32 s4, s4, 4
s_lshl_b32 s5, s14, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s14, s4, s5
s_mov_b64 s[4:5], 0
.LBB0_8:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s15, s14, s4
s_mov_b32 m0, s4
s_add_u32 s4, s4, 1
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s4, 16
v_movreld_b32_e32 v1, 0x7f7ff023
v_movreld_b32_e32 v17, s15
s_cbranch_scc0 .LBB0_8
s_load_b32 s20, s[0:1], 0x30
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s7, 1
s_cselect_b32 s4, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s5, s3, s4
s_and_saveexec_b32 s4, s5
s_cbranch_execz .LBB0_15
v_dual_mov_b32 v35, 0 :: v_dual_lshlrev_b32 v34, 2, v0
s_cmp_lt_i32 s18, 1
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v33, 0x4bc0, v34
ds_store_b32 v34, v35 offset:19392
s_cbranch_scc1 .LBB0_14
ds_load_b32 v34, v33
v_lshl_or_b32 v35, v0, 2, 0x4000
s_mov_b32 s5, s18
.LBB0_12:
ds_load_b32 v36, v35
v_add_nc_u32_e32 v35, 64, v35
s_add_i32 s5, s5, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s5, 0
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v34, v36, v36
s_cbranch_scc0 .LBB0_12
ds_store_b32 v33, v34
.LBB0_14:
ds_load_b32 v34, v33
s_waitcnt lgkmcnt(0)
v_mul_f32_e32 v34, s20, v34
ds_store_b32 v33, v34
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s21, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_i32_e64 s19, v0
s_cbranch_execz .LBB0_30
s_load_b32 s4, s[12:13], 0xc
v_mov_b32_e32 v82, v0
s_cmp_gt_i32 s18, 0
s_mov_b32 s22, 0
s_cselect_b32 s23, -1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s24, s4, 0xffff
.LBB0_17:
v_ashrrev_i32_e32 v83, 31, v82
s_mov_b64 s[14:15], 0
s_movk_i32 s5, 0x4b40
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[49:50], 2, v[82:83]
v_add_co_u32 v51, vcc_lo, s8, v49
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v52, vcc_lo, s9, v50, vcc_lo
v_add_co_u32 v53, vcc_lo, s10, v49
v_add_co_ci_u32_e32 v54, vcc_lo, s11, v50, vcc_lo
global_load_b32 v49, v[51:52], off
global_load_b32 v50, v[53:54], off
.LBB0_18:
v_mov_b32_e32 v51, s5
ds_load_2addr_b32 v[51:52], v51 offset1:16
s_waitcnt vmcnt(1) lgkmcnt(0)
v_sub_nc_u32_e32 v52, v52, v49
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v50, v51
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v51, 0, v52
v_max_i32_e32 v51, v52, v51
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_i32_e64 s4, s6, v51
s_and_b32 s4, s4, vcc_lo
s_cmp_eq_u32 s14, 7
v_cndmask_b32_e64 v51, 0, 1, s4
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s14, 6
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e32 v91, v91, v51, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s14, 5
v_cndmask_b32_e32 v90, v90, v51, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s14, 4
v_cndmask_b32_e32 v89, v89, v51, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s14, 3
v_cndmask_b32_e32 v88, v88, v51, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s14, 2
v_cndmask_b32_e32 v87, v87, v51, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s14, 1
v_cndmask_b32_e32 v86, v86, v51, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s14, 0
v_cndmask_b32_e32 v85, v85, v51, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s14, 8
v_cndmask_b32_e32 v84, v84, v51, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s14, 9
v_cndmask_b32_e32 v92, v92, v51, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s14, 10
v_cndmask_b32_e32 v93, v93, v51, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s14, 11
v_cndmask_b32_e32 v94, v94, v51, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s14, 12
v_cndmask_b32_e32 v95, v95, v51, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s14, 13
v_cndmask_b32_e32 v96, v96, v51, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s14, 14
v_cndmask_b32_e32 v97, v97, v51, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s14, 15
v_cndmask_b32_e32 v98, v98, v51, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_add_u32 s14, s14, 1
v_cndmask_b32_e32 v99, v99, v51, vcc_lo
s_addc_u32 s15, s15, 0
s_add_i32 s5, s5, 4
s_cmp_lg_u32 s14, 16
s_cbranch_scc1 .LBB0_18
s_mov_b64 s[4:5], 0
.LBB0_20:
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 m0, s4
s_add_u32 s4, s4, 1
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s4, 16
v_movreld_b32_e32 v33, 0
s_cbranch_scc0 .LBB0_20
s_and_not1_b32 vcc_lo, exec_lo, s23
s_cbranch_vccnz .LBB0_26
v_mul_lo_u32 v49, v82, s18
s_mov_b32 s14, 0
s_movk_i32 s15, 0x4000
.p2align 6
.LBB0_23:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v50, s14, v49
s_mov_b64 s[4:5], 0
s_mov_b32 s25, s15
v_ashrrev_i32_e32 v51, 31, v50
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[50:51], 2, v[50:51]
v_add_co_u32 v50, vcc_lo, s16, v50
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v51, vcc_lo, s17, v51, vcc_lo
global_load_b32 v50, v[50:51], off
.LBB0_24:
v_mov_b32_e32 v51, s25
s_mov_b32 m0, s4
s_add_u32 s4, s4, 1
v_movrels_b32_e32 v52, v33
s_addc_u32 s5, s5, 0
ds_load_b32 v51, v51
s_add_i32 s25, s25, 4
s_cmp_eq_u32 s4, 16
s_waitcnt vmcnt(0) lgkmcnt(0)
v_sub_f32_e32 v51, v50, v51
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v52, v51, v51
v_movreld_b32_e32 v33, v52
s_cbranch_scc0 .LBB0_24
s_add_i32 s14, s14, 1
s_add_i32 s15, s15, 64
s_cmp_eq_u32 s14, s18
s_cbranch_scc0 .LBB0_23
.LBB0_26:
s_mov_b64 s[14:15], 0
.LBB0_27:
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s14, 1
s_mov_b32 m0, s14
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s14, 2
v_cndmask_b32_e32 v100, v84, v85, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
v_dual_mov_b32 v64, v16 :: v_dual_mov_b32 v63, v15
v_dual_mov_b32 v80, v32 :: v_dual_mov_b32 v79, v31
v_dual_mov_b32 v50, v2 :: v_dual_mov_b32 v49, v1
v_dual_mov_b32 v66, v18 :: v_dual_mov_b32 v65, v17
v_movrels_b32_e32 v83, v33
v_movrels_b32_e32 v101, v1
v_cndmask_b32_e32 v100, v100, v86, vcc_lo
s_cmp_eq_u32 s14, 3
v_dual_mov_b32 v62, v14 :: v_dual_mov_b32 v61, v13
s_cselect_b32 vcc_lo, -1, 0
v_dual_mov_b32 v60, v12 :: v_dual_mov_b32 v59, v11
v_dual_mov_b32 v58, v10 :: v_dual_mov_b32 v57, v9
v_dual_mov_b32 v56, v8 :: v_dual_mov_b32 v55, v7
v_dual_mov_b32 v54, v6 :: v_dual_mov_b32 v53, v5
v_dual_mov_b32 v52, v4 :: v_dual_mov_b32 v51, v3
v_dual_mov_b32 v78, v30 :: v_dual_mov_b32 v77, v29
v_dual_mov_b32 v76, v28 :: v_dual_mov_b32 v75, v27
v_dual_mov_b32 v74, v26 :: v_dual_mov_b32 v73, v25
v_dual_mov_b32 v72, v24 :: v_dual_mov_b32 v71, v23
v_dual_mov_b32 v70, v22 :: v_dual_mov_b32 v69, v21
v_dual_mov_b32 v68, v20 :: v_dual_mov_b32 v67, v19
v_cmp_lt_f32_e64 s4, v83, v101
v_movreld_b32_e32 v49, v83
v_movreld_b32_e32 v65, v82
v_cndmask_b32_e32 v83, v100, v87, vcc_lo
s_cmp_eq_u32 s14, 4
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s14, 5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v83, v83, v88, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s14, 6
v_cndmask_b32_e32 v83, v83, v89, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s14, 7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v83, v83, v90, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s14, 8
v_cndmask_b32_e32 v83, v83, v91, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s14, 9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v83, v83, v92, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s14, 10
v_cndmask_b32_e32 v83, v83, v93, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s14, 11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v83, v83, v94, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s14, 12
v_cndmask_b32_e32 v83, v83, v95, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s14, 13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v83, v83, v96, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s14, 14
v_cndmask_b32_e32 v83, v83, v97, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s14, 15
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v83, v83, v98, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
v_cndmask_b32_e32 v83, v83, v99, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v83, 0xff, v83
v_cmp_eq_u16_e32 vcc_lo, 1, v83
s_and_b32 vcc_lo, s4, vcc_lo
s_add_u32 s14, s14, 1
v_cndmask_b32_e32 v10, v10, v58, vcc_lo
v_dual_cndmask_b32 v32, v32, v80 :: v_dual_cndmask_b32 v31, v31, v79
v_cndmask_b32_e32 v8, v8, v56, vcc_lo
v_dual_cndmask_b32 v30, v30, v78 :: v_dual_cndmask_b32 v29, v29, v77
v_cndmask_b32_e32 v6, v6, v54, vcc_lo
v_dual_cndmask_b32 v28, v28, v76 :: v_dual_cndmask_b32 v27, v27, v75
v_cndmask_b32_e32 v4, v4, v52, vcc_lo
v_dual_cndmask_b32 v26, v26, v74 :: v_dual_cndmask_b32 v25, v25, v73
v_cndmask_b32_e32 v2, v2, v50, vcc_lo
v_dual_cndmask_b32 v24, v24, v72 :: v_dual_cndmask_b32 v23, v23, v71
v_dual_cndmask_b32 v22, v22, v70 :: v_dual_cndmask_b32 v21, v21, v69
v_dual_cndmask_b32 v20, v20, v68 :: v_dual_cndmask_b32 v19, v19, v67
v_dual_cndmask_b32 v18, v18, v66 :: v_dual_cndmask_b32 v17, v17, v65
v_dual_cndmask_b32 v16, v16, v64 :: v_dual_cndmask_b32 v15, v15, v63
v_dual_cndmask_b32 v14, v14, v62 :: v_dual_cndmask_b32 v13, v13, v61
v_dual_cndmask_b32 v12, v12, v60 :: v_dual_cndmask_b32 v11, v11, v59
v_cndmask_b32_e32 v9, v9, v57, vcc_lo
v_cndmask_b32_e32 v7, v7, v55, vcc_lo
v_cndmask_b32_e32 v5, v5, v53, vcc_lo
v_cndmask_b32_e32 v3, v3, v51, vcc_lo
v_cndmask_b32_e32 v1, v1, v49, vcc_lo
s_addc_u32 s15, s15, 0
s_cmp_eq_u32 s14, 16
s_cbranch_scc0 .LBB0_27
v_add_nc_u32_e32 v82, s24, v82
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s19, v82
s_or_b32 s22, vcc_lo, s22
s_and_not1_b32 exec_lo, exec_lo, s22
s_cbranch_execnz .LBB0_17
s_or_b32 exec_lo, exec_lo, s22
.LBB0_30:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s21
v_lshlrev_b32_e32 v33, 6, v0
s_mov_b64 s[4:5], 0
.LBB0_31:
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 m0, s4
s_add_u32 s4, s4, 1
v_movrels_b32_e32 v34, v1
v_movrels_b32_e32 v35, v17
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s4, 16
ds_store_2addr_stride64_b32 v33, v35, v34 offset1:32
v_add_nc_u32_e32 v33, 4, v33
s_cbranch_scc0 .LBB0_31
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s4, s3
s_cbranch_execz .LBB0_53
s_load_b32 s3, s[12:13], 0xc
s_waitcnt lgkmcnt(0)
v_cmp_eq_u16_e64 s4, s3, 0
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s4
s_cbranch_vccnz .LBB0_38
v_dual_mov_b32 v2, 0x7f7ff023 :: v_dual_lshlrev_b32 v3, 2, v0
v_mov_b32_e32 v1, v81
s_and_b32 s3, 0xffff, s3
s_branch .LBB0_36
.LBB0_35:
s_or_b32 exec_lo, exec_lo, s4
v_add_nc_u32_e32 v3, 64, v3
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s3, 0
s_cbranch_scc1 .LBB0_39
.LBB0_36:
ds_load_b32 v4, v3 offset:8192
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_lt_f32_e32 v4, v2
s_cbranch_execz .LBB0_35
ds_load_b32 v1, v3
v_mov_b32_e32 v2, v4
s_branch .LBB0_35
.LBB0_38:
v_dual_mov_b32 v2, 0x7f7ff023 :: v_dual_mov_b32 v1, v81
.LBB0_39:
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_53
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ngt_f32_e64 s2, 0, v2
s_cmp_lg_u32 s7, 0
s_cbranch_scc0 .LBB0_46
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB0_43
v_lshlrev_b32_e32 v0, 2, v0
ds_load_b32 v0, v0 offset:19392
s_waitcnt lgkmcnt(0)
v_div_scale_f32 v3, null, v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
v_fmac_f32_e32 v4, v5, v4
v_div_scale_f32 v5, vcc_lo, v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, v5, v4
v_fma_f32 v7, -v3, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v7, v4
v_fma_f32 v3, -v3, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v3, v3, v4, v6
v_div_fixup_f32 v3, v3, v0, v2
.LBB0_43:
s_and_not1_saveexec_b32 s3, s3
v_xor_b32_e32 v3, 0x80000000, v2
s_or_b32 exec_lo, exec_lo, s3
s_cbranch_execz .LBB0_47
s_branch .LBB0_52
.LBB0_46:
.LBB0_47:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_xor_b32 s2, exec_lo, s3
v_div_scale_f32 v0, null, s20, s20, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v3, v0
s_waitcnt_depctr 0xfff
v_fma_f32 v4, -v0, v3, 1.0
v_fmac_f32_e32 v3, v4, v3
v_div_scale_f32 v4, vcc_lo, v2, s20, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, v4, v3
v_fma_f32 v6, -v0, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v3
v_fma_f32 v0, -v0, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v0, v0, v3, v5
v_div_fixup_f32 v3, v0, s20, v2
s_and_not1_saveexec_b32 s2, s2
v_xor_b32_e32 v3, 0x80000000, v2
s_or_b32 exec_lo, exec_lo, s2
.LBB0_52:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_mul_f32_e32 v0, 0x4f800000, v3
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v3
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v82, 31, v81
v_cndmask_b32_e32 v4, v3, v0, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v0, v4
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v2, -1, v0
v_add_nc_u32_e32 v3, 1, v0
v_fma_f32 v5, -v2, v0, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v6, -v3, v0, v4
v_cmp_ge_f32_e64 s0, 0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v0, v0, v2, s0
v_cmp_lt_f32_e64 s0, 0, v6
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v6, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v0, v0, v3, s0
v_lshlrev_b64 v[2:3], 2, v[81:82]
v_mul_f32_e32 v5, 0x37800000, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v5, v0, v5, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v3, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v4, 0x260
v_cndmask_b32_e32 v4, v5, v4, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_store_b32 v[0:1], v4, off
global_store_b32 v[2:3], v6, off
.LBB0_53:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_f
.amdhsa_group_segment_fixed_size 19456
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 102
.amdhsa_next_free_sgpr 26
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_f, .Lfunc_end0-_Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_f
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 19456
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_f
.private_segment_fixed_size: 0
.sgpr_count: 28
.sgpr_spill_count: 0
.symbol: _Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_f.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 102
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /**
* jrc3_cuda_delta.cu
* block loading delta calculation. should be much faster
* system('nvcc -ptx -m 64 -arch sm_35 jrc3_cuda_rho.cu')
* iA is multiple of CHUNK (16)
* J. James Jun, Vidrio Technologies, LLC., 2017 Jun 11
*/
#include <hip/hip_runtime.h>
// #include "cublas_v2.h"
#include <math.h>
#define ABS(my_val) ((my_val) < 0) ? (-1*(my_val)) : (my_val)
#define MIN(A,B) ((A)<(B)) ? (A) : (B)
#define MAX(A,B) ((A)>(B)) ? (A) : (B)
#define NTHREADS 128
#define NC 45 // number of Channels
#define CHUNK 16 //previously defined as CHUNK
#define SINGLE_INF (3.402E+38)
/** Main entry point.
* Works out where the current thread should read/write to global memory
* and calls doIterations to do the actual work.
* Step through one B at a time
* 7/13/17: fDc_spk option added, which uses spike-specific distance cut-off (dc)
*/
// % Matlab syntax
// mrDist12_ = eucl2_dist_(mrFet12, mrFet12(:,1:n1)); %not sqrt
// mlRemove12_ = bsxfun(@ge, viiRho12_ord, viiRho12_ord(1:n1)') ...
// | abs(bsxfun(@minus, viiSpk12_ord_, viiSpk12_ord_(1:n1)')) > dn_max;
// mrDist12_(mlRemove12_) = nan;
// [vrDelta1, viNneigh1] = min(mrDist12_);
__global__ void jrc3_cuda_delta(float * vrDelta1, unsigned int * viNneigh1, const float * mrFet12, const int * viiSpk12_ord, const int * viiRho12_ord, const int * vnConst, const float dc2){
// int iA = blockIdx.x * CHUNK;
int i1 = (blockIdx.x + blockIdx.y * gridDim.x) * CHUNK; // base index of i1
int tx = threadIdx.x;
int i1_tx = i1 + tx;
int n1 = vnConst[0];
int n12 = vnConst[1];
int nC = vnConst[2];
int dn_max = vnConst[3];
int fDc_spk = vnConst[4];
__shared__ int viiSpk1_ord_[CHUNK];
__shared__ int viiRho1_ord_[CHUNK];
__shared__ float mrFet1_[NC][CHUNK];
__shared__ float mrDelta1_[NTHREADS][CHUNK];
__shared__ unsigned int miNneigh1_[NTHREADS][CHUNK];
__shared__ float vrDc1_[CHUNK]; // use if fDc_spk=1
// cache shared memory
if (tx < nC){ //use tx as iC
for (int i_c = 0; i_c < CHUNK; ++i_c){
int i1_c = i_c + i1;
if (i1_c < n1){
mrFet1_[tx][i_c] = mrFet12[tx + i1_c * nC];
}else{
mrFet1_[tx][i_c] = 0.0f;
}
}
}
if (tx < CHUNK && i1_tx < n1){
viiSpk1_ord_[tx] = viiSpk12_ord[i1_tx];
viiRho1_ord_[tx] = viiRho12_ord[i1_tx];
}
float vr_minDist1[CHUNK];
unsigned int vi_minIdx1[CHUNK];
for (int i_c = 0; i_c < CHUNK; ++i_c){
vr_minDist1[i_c] = SINGLE_INF;
vi_minIdx1[i_c] = i1 + i_c; // self
}
// calculate spike-specific distance cut-off vrDc1_ only if fDc_spk==1
if (tx < CHUNK && fDc_spk==1){
vrDc1_[tx] = 0.0f; //init
//for (int iC = 0; iC < 1; ++iC){ //center only scale
for (int iC = 0; iC < nC; ++iC){
float temp_ = mrFet1_[iC][tx];
vrDc1_[tx] += (temp_ * temp_);
}
vrDc1_[tx] *= dc2;
}
__syncthreads();
// fill in the shared memory A
for (int i12_tx = tx; i12_tx < n12; i12_tx += blockDim.x){
//for (int i12_tx = 1; i12_tx < n12; ++i12_tx){
// compute time difference
char vlDist_c[CHUNK];
int iiSpk12_ord_tx = viiSpk12_ord[i12_tx];
int iiRho12_ord_tx = viiRho12_ord[i12_tx];
for (int i_c = 0; i_c < CHUNK; ++i_c){
char di_rho_ = (iiRho12_ord_tx < viiRho1_ord_[i_c]);
int di_spk_ = ABS(viiSpk1_ord_[i_c] - iiSpk12_ord_tx);
vlDist_c[i_c] = (di_spk_ <= dn_max) && di_rho_;
}
// compute distance
float vrDist_c[CHUNK];
for (int i_c = 0; i_c < CHUNK; ++i_c) vrDist_c[i_c] = 0.0f;
for (int iC = 0; iC < nC; ++iC){
float fet12_tx = mrFet12[iC + i12_tx * nC];
for (int i_c = 0; i_c < CHUNK; ++i_c){
float temp = fet12_tx - mrFet1_[iC][i_c];
vrDist_c[i_c] += temp * temp;
}
}
// Compare the index and distance
for (int i_c = 0; i_c < CHUNK; ++i_c){
if (vrDist_c[i_c] < vr_minDist1[i_c]){
if (vlDist_c[i_c] == 1){
vr_minDist1[i_c] = vrDist_c[i_c];
vi_minIdx1[i_c] = i12_tx;
}
}
}
} // while
// collect result from each thread
for (int i_c = 0; i_c < CHUNK; ++i_c){
mrDelta1_[tx][i_c] = vr_minDist1[i_c];
miNneigh1_[tx][i_c] = vi_minIdx1[i_c];
}
__syncthreads();
// final count
//if (tx < CHUNK && i1_tx < n1){
if (tx < CHUNK){
float minDist1 = SINGLE_INF;
unsigned int minIdx1 = i1_tx;
for (int tx1=0; tx1<blockDim.x; ++tx1){
if (mrDelta1_[tx1][tx] < minDist1){
minDist1 = mrDelta1_[tx1][tx];
minIdx1 = miNneigh1_[tx1][tx];
}
}
//vrDelta1[i1_tx] = sqrtf(minDist1);
if (i1_tx < n1){
// vrDelta_ = sqrt(abs(single(vrDelta_) / vrDc2_site(iSite))); %normalize and convert dist
if (fDc_spk==0){
vrDelta1[i1_tx] = sqrtf(ABS(minDist1) / dc2);
}else{
vrDelta1[i1_tx] = sqrtf(ABS(minDist1) / vrDc1_[tx]);
//vrDelta1[i1_tx] = sqrtf(ABS(minDist1));
}
viNneigh1[i1_tx] = minIdx1 + 1; //Matlab index output
}
}
} // func | .text
.file "irc_cuda_delta.hip"
.globl _Z30__device_stub__jrc3_cuda_deltaPfPjPKfPKiS4_S4_f # -- Begin function _Z30__device_stub__jrc3_cuda_deltaPfPjPKfPKiS4_S4_f
.p2align 4, 0x90
.type _Z30__device_stub__jrc3_cuda_deltaPfPjPKfPKiS4_S4_f,@function
_Z30__device_stub__jrc3_cuda_deltaPfPjPKfPKiS4_S4_f: # @_Z30__device_stub__jrc3_cuda_deltaPfPjPKfPKiS4_S4_f
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movss %xmm0, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_f, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z30__device_stub__jrc3_cuda_deltaPfPjPKfPKiS4_S4_f, .Lfunc_end0-_Z30__device_stub__jrc3_cuda_deltaPfPjPKfPKiS4_S4_f
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_f, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_f,@object # @_Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_f
.section .rodata,"a",@progbits
.globl _Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_f
.p2align 3, 0x0
_Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_f:
.quad _Z30__device_stub__jrc3_cuda_deltaPfPjPKfPKiS4_S4_f
.size _Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_f, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_f"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__jrc3_cuda_deltaPfPjPKfPKiS4_S4_f
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_f
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ebeb9_00000000-6_irc_cuda_delta.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_fPfPjPKfPKiS4_S4_f
.type _Z50__device_stub__Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_fPfPjPKfPKiS4_S4_f, @function
_Z50__device_stub__Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_fPfPjPKfPKiS4_S4_f:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_f(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_fPfPjPKfPKiS4_S4_f, .-_Z50__device_stub__Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_fPfPjPKfPKiS4_S4_f
.globl _Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_f
.type _Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_f, @function
_Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_f:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_fPfPjPKfPKiS4_S4_f
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_f, .-_Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_f
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_f"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_f(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "irc_cuda_delta.hip"
.globl _Z30__device_stub__jrc3_cuda_deltaPfPjPKfPKiS4_S4_f # -- Begin function _Z30__device_stub__jrc3_cuda_deltaPfPjPKfPKiS4_S4_f
.p2align 4, 0x90
.type _Z30__device_stub__jrc3_cuda_deltaPfPjPKfPKiS4_S4_f,@function
_Z30__device_stub__jrc3_cuda_deltaPfPjPKfPKiS4_S4_f: # @_Z30__device_stub__jrc3_cuda_deltaPfPjPKfPKiS4_S4_f
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movss %xmm0, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_f, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z30__device_stub__jrc3_cuda_deltaPfPjPKfPKiS4_S4_f, .Lfunc_end0-_Z30__device_stub__jrc3_cuda_deltaPfPjPKfPKiS4_S4_f
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_f, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_f,@object # @_Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_f
.section .rodata,"a",@progbits
.globl _Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_f
.p2align 3, 0x0
_Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_f:
.quad _Z30__device_stub__jrc3_cuda_deltaPfPjPKfPKiS4_S4_f
.size _Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_f, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_f"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__jrc3_cuda_deltaPfPjPKfPKiS4_S4_f
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15jrc3_cuda_deltaPfPjPKfPKiS4_S4_f
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* Just how many cuda enabled devices on this machine?
* Also, what are their properties?
*
* Note - EVERY cuda call returns an error value. While
* this is vital in real code, it gets in the way of
* tutorial code. I'm showing it here for cudaGetDeviceCount
* but will omit it for the rest of the tutorial.
*/
#include <stdio.h>
#include <stdlib.h>
int main(int argc, char** argv) {
int numberOfDevices;
cudaError_t err;
err = cudaGetDeviceCount(&numberOfDevices);
if (err != cudaSuccess) {
fprintf(stderr,"fail - cudaGetDeviceCount %d\n",err);
exit(1);
}
printf("Number of cuda devices = %d\n",numberOfDevices);
/* the cudaDeviceProp struct is fairly large - read about it in the
docs. */
for (int dev = 0; dev < numberOfDevices; dev++) {
cudaDeviceProp props;
cudaGetDeviceProperties(&props,dev);
printf("Device # %d\n",dev);
printf(" name = %s\n",props.name);
printf(" version = %d.%d\n",props.major,props.minor);
printf(" total global memory = %ld\n",props.totalGlobalMem);
printf(" shared Memory/Block = %ld\n",props.sharedMemPerBlock);
printf(" registers/block = %d\n",props.regsPerBlock);
printf(" warp size = %d\n",props.warpSize);
printf(" Max threads/block = %d\n",props.maxThreadsPerBlock);
printf(" Max Threads Dim = %d x %d x %d\n",props.maxThreadsDim[0],
props.maxThreadsDim[1],props.maxThreadsDim[2]);
printf(" Max Grid Size = %d x %d x %d\n",props.maxGridSize[0],
props.maxGridSize[1],props.maxGridSize[2]);
printf(" Multi-processor count = %d\n",props.multiProcessorCount);
printf(" Max Threads/multiprocessor = %d\n",props.maxThreadsPerMultiProcessor);
}
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* Just how many cuda enabled devices on this machine?
* Also, what are their properties?
*
* Note - EVERY cuda call returns an error value. While
* this is vital in real code, it gets in the way of
* tutorial code. I'm showing it here for cudaGetDeviceCount
* but will omit it for the rest of the tutorial.
*/
#include <stdio.h>
#include <stdlib.h>
int main(int argc, char** argv) {
int numberOfDevices;
cudaError_t err;
err = cudaGetDeviceCount(&numberOfDevices);
if (err != cudaSuccess) {
fprintf(stderr,"fail - cudaGetDeviceCount %d\n",err);
exit(1);
}
printf("Number of cuda devices = %d\n",numberOfDevices);
/* the cudaDeviceProp struct is fairly large - read about it in the
docs. */
for (int dev = 0; dev < numberOfDevices; dev++) {
cudaDeviceProp props;
cudaGetDeviceProperties(&props,dev);
printf("Device # %d\n",dev);
printf(" name = %s\n",props.name);
printf(" version = %d.%d\n",props.major,props.minor);
printf(" total global memory = %ld\n",props.totalGlobalMem);
printf(" shared Memory/Block = %ld\n",props.sharedMemPerBlock);
printf(" registers/block = %d\n",props.regsPerBlock);
printf(" warp size = %d\n",props.warpSize);
printf(" Max threads/block = %d\n",props.maxThreadsPerBlock);
printf(" Max Threads Dim = %d x %d x %d\n",props.maxThreadsDim[0],
props.maxThreadsDim[1],props.maxThreadsDim[2]);
printf(" Max Grid Size = %d x %d x %d\n",props.maxGridSize[0],
props.maxGridSize[1],props.maxGridSize[2]);
printf(" Multi-processor count = %d\n",props.multiProcessorCount);
printf(" Max Threads/multiprocessor = %d\n",props.maxThreadsPerMultiProcessor);
}
return 0;
} | .file "tmpxft_0016021d_00000000-6_cuda-devices.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "fail - cudaGetDeviceCount %d\n"
.LC1:
.string "Number of cuda devices = %d\n"
.LC2:
.string "Device # %d\n"
.LC3:
.string " name = %s\n"
.LC4:
.string " version = %d.%d\n"
.LC5:
.string " total global memory = %ld\n"
.LC6:
.string " shared Memory/Block = %ld\n"
.LC7:
.string " registers/block = %d\n"
.LC8:
.string " warp size = %d\n"
.LC9:
.string " Max threads/block = %d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC10:
.string " Max Threads Dim = %d x %d x %d\n"
.align 8
.LC11:
.string " Max Grid Size = %d x %d x %d\n"
.section .rodata.str1.1
.LC12:
.string " Multi-processor count = %d\n"
.section .rodata.str1.8
.align 8
.LC13:
.string " Max Threads/multiprocessor = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1064, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
testl %eax, %eax
jne .L10
movl 12(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 12(%rsp)
jle .L5
movl $0, %ebx
leaq .LC2(%rip), %r15
leaq .LC3(%rip), %r14
leaq .LC4(%rip), %r13
leaq .LC5(%rip), %r12
.L6:
leaq 16(%rsp), %rbp
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
movl %ebx, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 380(%rsp), %ecx
movl 376(%rsp), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 304(%rsp), %rdx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 312(%rsp), %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 320(%rsp), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 324(%rsp), %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 348(%rsp), %r8d
movl 344(%rsp), %ecx
movl 340(%rsp), %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 360(%rsp), %r8d
movl 356(%rsp), %ecx
movl 352(%rsp), %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 404(%rsp), %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 640(%rsp), %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jg .L6
.L5:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L11
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %eax, %ecx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L11:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* Just how many cuda enabled devices on this machine?
* Also, what are their properties?
*
* Note - EVERY cuda call returns an error value. While
* this is vital in real code, it gets in the way of
* tutorial code. I'm showing it here for cudaGetDeviceCount
* but will omit it for the rest of the tutorial.
*/
#include <stdio.h>
#include <stdlib.h>
int main(int argc, char** argv) {
int numberOfDevices;
cudaError_t err;
err = cudaGetDeviceCount(&numberOfDevices);
if (err != cudaSuccess) {
fprintf(stderr,"fail - cudaGetDeviceCount %d\n",err);
exit(1);
}
printf("Number of cuda devices = %d\n",numberOfDevices);
/* the cudaDeviceProp struct is fairly large - read about it in the
docs. */
for (int dev = 0; dev < numberOfDevices; dev++) {
cudaDeviceProp props;
cudaGetDeviceProperties(&props,dev);
printf("Device # %d\n",dev);
printf(" name = %s\n",props.name);
printf(" version = %d.%d\n",props.major,props.minor);
printf(" total global memory = %ld\n",props.totalGlobalMem);
printf(" shared Memory/Block = %ld\n",props.sharedMemPerBlock);
printf(" registers/block = %d\n",props.regsPerBlock);
printf(" warp size = %d\n",props.warpSize);
printf(" Max threads/block = %d\n",props.maxThreadsPerBlock);
printf(" Max Threads Dim = %d x %d x %d\n",props.maxThreadsDim[0],
props.maxThreadsDim[1],props.maxThreadsDim[2]);
printf(" Max Grid Size = %d x %d x %d\n",props.maxGridSize[0],
props.maxGridSize[1],props.maxGridSize[2]);
printf(" Multi-processor count = %d\n",props.multiProcessorCount);
printf(" Max Threads/multiprocessor = %d\n",props.maxThreadsPerMultiProcessor);
}
return 0;
} | /*
* Just how many cuda enabled devices on this machine?
* Also, what are their properties?
*
* Note - EVERY cuda call returns an error value. While
* this is vital in real code, it gets in the way of
* tutorial code. I'm showing it here for cudaGetDeviceCount
* but will omit it for the rest of the tutorial.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
int main(int argc, char** argv) {
int numberOfDevices;
hipError_t err;
err = hipGetDeviceCount(&numberOfDevices);
if (err != hipSuccess) {
fprintf(stderr,"fail - hipGetDeviceCount %d\n",err);
exit(1);
}
printf("Number of cuda devices = %d\n",numberOfDevices);
/* the cudaDeviceProp struct is fairly large - read about it in the
docs. */
for (int dev = 0; dev < numberOfDevices; dev++) {
hipDeviceProp_t props;
hipGetDeviceProperties(&props,dev);
printf("Device # %d\n",dev);
printf(" name = %s\n",props.name);
printf(" version = %d.%d\n",props.major,props.minor);
printf(" total global memory = %ld\n",props.totalGlobalMem);
printf(" shared Memory/Block = %ld\n",props.sharedMemPerBlock);
printf(" registers/block = %d\n",props.regsPerBlock);
printf(" warp size = %d\n",props.warpSize);
printf(" Max threads/block = %d\n",props.maxThreadsPerBlock);
printf(" Max Threads Dim = %d x %d x %d\n",props.maxThreadsDim[0],
props.maxThreadsDim[1],props.maxThreadsDim[2]);
printf(" Max Grid Size = %d x %d x %d\n",props.maxGridSize[0],
props.maxGridSize[1],props.maxGridSize[2]);
printf(" Multi-processor count = %d\n",props.multiProcessorCount);
printf(" Max Threads/multiprocessor = %d\n",props.maxThreadsPerMultiProcessor);
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* Just how many cuda enabled devices on this machine?
* Also, what are their properties?
*
* Note - EVERY cuda call returns an error value. While
* this is vital in real code, it gets in the way of
* tutorial code. I'm showing it here for cudaGetDeviceCount
* but will omit it for the rest of the tutorial.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
int main(int argc, char** argv) {
int numberOfDevices;
hipError_t err;
err = hipGetDeviceCount(&numberOfDevices);
if (err != hipSuccess) {
fprintf(stderr,"fail - hipGetDeviceCount %d\n",err);
exit(1);
}
printf("Number of cuda devices = %d\n",numberOfDevices);
/* the cudaDeviceProp struct is fairly large - read about it in the
docs. */
for (int dev = 0; dev < numberOfDevices; dev++) {
hipDeviceProp_t props;
hipGetDeviceProperties(&props,dev);
printf("Device # %d\n",dev);
printf(" name = %s\n",props.name);
printf(" version = %d.%d\n",props.major,props.minor);
printf(" total global memory = %ld\n",props.totalGlobalMem);
printf(" shared Memory/Block = %ld\n",props.sharedMemPerBlock);
printf(" registers/block = %d\n",props.regsPerBlock);
printf(" warp size = %d\n",props.warpSize);
printf(" Max threads/block = %d\n",props.maxThreadsPerBlock);
printf(" Max Threads Dim = %d x %d x %d\n",props.maxThreadsDim[0],
props.maxThreadsDim[1],props.maxThreadsDim[2]);
printf(" Max Grid Size = %d x %d x %d\n",props.maxGridSize[0],
props.maxGridSize[1],props.maxGridSize[2]);
printf(" Multi-processor count = %d\n",props.multiProcessorCount);
printf(" Max Threads/multiprocessor = %d\n",props.maxThreadsPerMultiProcessor);
}
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* Just how many cuda enabled devices on this machine?
* Also, what are their properties?
*
* Note - EVERY cuda call returns an error value. While
* this is vital in real code, it gets in the way of
* tutorial code. I'm showing it here for cudaGetDeviceCount
* but will omit it for the rest of the tutorial.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
int main(int argc, char** argv) {
int numberOfDevices;
hipError_t err;
err = hipGetDeviceCount(&numberOfDevices);
if (err != hipSuccess) {
fprintf(stderr,"fail - hipGetDeviceCount %d\n",err);
exit(1);
}
printf("Number of cuda devices = %d\n",numberOfDevices);
/* the cudaDeviceProp struct is fairly large - read about it in the
docs. */
for (int dev = 0; dev < numberOfDevices; dev++) {
hipDeviceProp_t props;
hipGetDeviceProperties(&props,dev);
printf("Device # %d\n",dev);
printf(" name = %s\n",props.name);
printf(" version = %d.%d\n",props.major,props.minor);
printf(" total global memory = %ld\n",props.totalGlobalMem);
printf(" shared Memory/Block = %ld\n",props.sharedMemPerBlock);
printf(" registers/block = %d\n",props.regsPerBlock);
printf(" warp size = %d\n",props.warpSize);
printf(" Max threads/block = %d\n",props.maxThreadsPerBlock);
printf(" Max Threads Dim = %d x %d x %d\n",props.maxThreadsDim[0],
props.maxThreadsDim[1],props.maxThreadsDim[2]);
printf(" Max Grid Size = %d x %d x %d\n",props.maxGridSize[0],
props.maxGridSize[1],props.maxGridSize[2]);
printf(" Multi-processor count = %d\n",props.multiProcessorCount);
printf(" Max Threads/multiprocessor = %d\n",props.maxThreadsPerMultiProcessor);
}
return 0;
} | .text
.file "cuda-devices.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
testl %eax, %eax
jne .LBB0_5
# %bb.1:
movl 4(%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
cmpl $0, 4(%rsp)
jle .LBB0_4
# %bb.2: # %.lr.ph
leaq 8(%rsp), %rbx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_3: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.2, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl 368(%rsp), %esi
movl 372(%rsp), %edx
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movq 296(%rsp), %rsi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movq 304(%rsp), %rsi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movl 312(%rsp), %esi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl 316(%rsp), %esi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movl 328(%rsp), %esi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl 332(%rsp), %esi
movl 336(%rsp), %edx
movl 340(%rsp), %ecx
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movl 344(%rsp), %esi
movl 348(%rsp), %edx
movl 352(%rsp), %ecx
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movl 396(%rsp), %esi
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
movl 632(%rsp), %esi
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
incl %ebp
cmpl 4(%rsp), %ebp
jl .LBB0_3
.LBB0_4: # %._crit_edge
xorl %eax, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_5:
.cfi_def_cfa_offset 1504
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl %eax, %edx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "fail - hipGetDeviceCount %d\n"
.size .L.str, 29
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Number of cuda devices = %d\n"
.size .L.str.1, 29
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Device # %d\n"
.size .L.str.2, 13
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " name = %s\n"
.size .L.str.3, 12
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " version = %d.%d\n"
.size .L.str.4, 18
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " total global memory = %ld\n"
.size .L.str.5, 28
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " shared Memory/Block = %ld\n"
.size .L.str.6, 28
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz " registers/block = %d\n"
.size .L.str.7, 23
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz " warp size = %d\n"
.size .L.str.8, 17
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz " Max threads/block = %d\n"
.size .L.str.9, 25
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz " Max Threads Dim = %d x %d x %d\n"
.size .L.str.10, 33
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz " Max Grid Size = %d x %d x %d\n"
.size .L.str.11, 31
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz " Multi-processor count = %d\n"
.size .L.str.12, 29
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz " Max Threads/multiprocessor = %d\n"
.size .L.str.13, 34
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016021d_00000000-6_cuda-devices.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "fail - cudaGetDeviceCount %d\n"
.LC1:
.string "Number of cuda devices = %d\n"
.LC2:
.string "Device # %d\n"
.LC3:
.string " name = %s\n"
.LC4:
.string " version = %d.%d\n"
.LC5:
.string " total global memory = %ld\n"
.LC6:
.string " shared Memory/Block = %ld\n"
.LC7:
.string " registers/block = %d\n"
.LC8:
.string " warp size = %d\n"
.LC9:
.string " Max threads/block = %d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC10:
.string " Max Threads Dim = %d x %d x %d\n"
.align 8
.LC11:
.string " Max Grid Size = %d x %d x %d\n"
.section .rodata.str1.1
.LC12:
.string " Multi-processor count = %d\n"
.section .rodata.str1.8
.align 8
.LC13:
.string " Max Threads/multiprocessor = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1064, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
testl %eax, %eax
jne .L10
movl 12(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 12(%rsp)
jle .L5
movl $0, %ebx
leaq .LC2(%rip), %r15
leaq .LC3(%rip), %r14
leaq .LC4(%rip), %r13
leaq .LC5(%rip), %r12
.L6:
leaq 16(%rsp), %rbp
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
movl %ebx, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 380(%rsp), %ecx
movl 376(%rsp), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 304(%rsp), %rdx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 312(%rsp), %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 320(%rsp), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 324(%rsp), %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 348(%rsp), %r8d
movl 344(%rsp), %ecx
movl 340(%rsp), %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 360(%rsp), %r8d
movl 356(%rsp), %ecx
movl 352(%rsp), %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 404(%rsp), %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 640(%rsp), %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jg .L6
.L5:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L11
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %eax, %ecx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L11:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda-devices.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
testl %eax, %eax
jne .LBB0_5
# %bb.1:
movl 4(%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
cmpl $0, 4(%rsp)
jle .LBB0_4
# %bb.2: # %.lr.ph
leaq 8(%rsp), %rbx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_3: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.2, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl 368(%rsp), %esi
movl 372(%rsp), %edx
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movq 296(%rsp), %rsi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movq 304(%rsp), %rsi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movl 312(%rsp), %esi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl 316(%rsp), %esi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movl 328(%rsp), %esi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl 332(%rsp), %esi
movl 336(%rsp), %edx
movl 340(%rsp), %ecx
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movl 344(%rsp), %esi
movl 348(%rsp), %edx
movl 352(%rsp), %ecx
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movl 396(%rsp), %esi
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
movl 632(%rsp), %esi
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
incl %ebp
cmpl 4(%rsp), %ebp
jl .LBB0_3
.LBB0_4: # %._crit_edge
xorl %eax, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_5:
.cfi_def_cfa_offset 1504
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl %eax, %edx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "fail - hipGetDeviceCount %d\n"
.size .L.str, 29
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Number of cuda devices = %d\n"
.size .L.str.1, 29
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Device # %d\n"
.size .L.str.2, 13
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " name = %s\n"
.size .L.str.3, 12
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " version = %d.%d\n"
.size .L.str.4, 18
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " total global memory = %ld\n"
.size .L.str.5, 28
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " shared Memory/Block = %ld\n"
.size .L.str.6, 28
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz " registers/block = %d\n"
.size .L.str.7, 23
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz " warp size = %d\n"
.size .L.str.8, 17
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz " Max threads/block = %d\n"
.size .L.str.9, 25
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz " Max Threads Dim = %d x %d x %d\n"
.size .L.str.10, 33
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz " Max Grid Size = %d x %d x %d\n"
.size .L.str.11, 31
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz " Multi-processor count = %d\n"
.size .L.str.12, 29
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz " Max Threads/multiprocessor = %d\n"
.size .L.str.13, 34
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<cuda.h>
#include<cuda_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<cmath>
#define TILE_SIZE 2 // Tile size and block size, both are taken as 32
__device__ void store_full_row(float*,float*,int,int, int, int);
__device__ void load_full_row(float*,float*,int,int, int, int);
__device__ void store_full(float*,float*,int,int,int, int, int);
__device__ void load_full(float*,float*,int,int,int, int, int);
__device__ void store_lower(float*,float*,int,int,int, int, int);
__device__ void load_lower(float*,float*,int,int,int, int, int);
__device__ void potrf_tile(float*);
__device__ void trsm_tile(float*,int,int,int);
__device__ void syrk_tile(float*,float*,int,int,int);
__global__ void right_looking_launch_kernel(float*,int);
__device__ void store_full_row(float* read_data,float* write_data,int i,int N, int M, int shared_size_single_matrix)
{
int global_y;
int global_x = i*blockDim.y + threadIdx.y;
for(int j=0;j<N/TILE_SIZE;j++)
{
global_y = j*blockDim.z + threadIdx.z;
write_data[global_y*N*M + global_x*M + threadIdx.x] = read_data[threadIdx.y + (TILE_SIZE+1)*global_y + threadIdx.x*shared_size_single_matrix];
}
__syncthreads();
}
__device__ void load_full_row(float* read_data,float* write_data,int i,int N, int M, int shared_size_single_matrix)
{
int global_y;
int global_x = i*blockDim.y + threadIdx.y;
for(int j=0;j<N/TILE_SIZE;j++)
{
global_y = j*blockDim.z + threadIdx.z;
write_data[threadIdx.y + (TILE_SIZE+1)*global_y + threadIdx.x*shared_size_single_matrix] = read_data[global_y*N*M + global_x*M + threadIdx.x];
printf("%d, %d\n", threadIdx.y + (TILE_SIZE+1)*global_y + threadIdx.x*shared_size_single_matrix, global_y*N*M + global_x*M + threadIdx.x);
}
__syncthreads();
}
__device__ void store_full(float* read_data,float* write_data,int i,int j,int N, int M, int shared_size_single_matrix)
{
int global_y = j*blockDim.z + threadIdx.z;
int global_x = i*blockDim.y + threadIdx.y;
write_data[global_y*N*M + global_x*M + threadIdx.x] = read_data[threadIdx.y + (TILE_SIZE+1)*threadIdx.z + threadIdx.x*shared_size_single_matrix];
__syncthreads();
}
__device__ void load_full(float* read_data,float* write_data,int i,int j,int N, int M, int shared_size_single_matrix)
{
int global_y = j*blockDim.z + threadIdx.z;
int global_x = i*blockDim.y + threadIdx.y;
write_data[threadIdx.y + (TILE_SIZE+1)*threadIdx.z + threadIdx.x*shared_size_single_matrix] = read_data[global_y*N*M + global_x*M + threadIdx.x];
__syncthreads();
}
__device__ void store_lower(float* read_data,float* write_data,int i,int j,int N, int M, int shared_size_single_matrix)
{
int global_y = j*blockDim.z + threadIdx.z;
int global_x = i*blockDim.y + threadIdx.y;
// printf("%f is at %d\n", read_data[threadIdx.y + (TILE_SIZE+1)*threadIdx.z + threadIdx.x*shared_size_single_matrix], threadIdx.y + (TILE_SIZE+1)*threadIdx.z + threadIdx.x*shared_size_single_matrix);
if(threadIdx.z >= threadIdx.y)
write_data[global_y*N*M + global_x*M + threadIdx.x] = read_data[threadIdx.y + (TILE_SIZE+1)*threadIdx.z + threadIdx.x*shared_size_single_matrix];
else
write_data[global_y*N*M + global_x*M + threadIdx.x] = 0.0;
__syncthreads();
}
__device__ void load_lower(float* read_data,float* write_data,int i,int j,int N, int M, int shared_size_single_matrix)
{
int global_y = j*blockDim.z + threadIdx.z;
int global_x = i*blockDim.y + threadIdx.y;
if(threadIdx.z >= threadIdx.y)
write_data[threadIdx.y + (TILE_SIZE+1)*threadIdx.z + threadIdx.x*shared_size_single_matrix] = read_data[global_y*N*M + global_x*M + threadIdx.x];
else
write_data[threadIdx.y + (TILE_SIZE+1)*threadIdx.z + threadIdx.x*shared_size_single_matrix] = 0.0;
__syncthreads();
}
__device__ void potrf_tile(float* t_A)
{
int t_x = threadIdx.y;
int t_y = threadIdx.z;
__shared__ float temp2;
for(int k=0;k<TILE_SIZE;k++)
{
if(t_x==t_y && t_x==k)
{
t_A[k*(TILE_SIZE+1) + k] = sqrtf(t_A[k*(TILE_SIZE+1) + k]);
temp2 = t_A[k*(TILE_SIZE+1) + k];
}
__syncthreads();
if(t_x<t_y && t_x == k)
{
t_A[t_y*(TILE_SIZE+1) + k]/= temp2;
}
__syncthreads();
if(k<t_y && k<t_x && t_x<=t_y)
{
t_A[t_y*(TILE_SIZE+1) + t_x]-= t_A[t_x*(TILE_SIZE+1) + k]*t_A[t_y*(TILE_SIZE+1) + k];
}
__syncthreads();
}
}
__device__ void trsm_tile(float *row_data,int i,int j,int N)
{
int global_y = j*blockDim.z + threadIdx.z;
int global_x = i*blockDim.y + threadIdx.y;
int t_x = threadIdx.y;
int t_y = threadIdx.z;
for(int s=0;s<TILE_SIZE;s++)
{
if(t_x==s)
{
row_data[global_y*(TILE_SIZE+1) + t_x]/= row_data[global_x*(TILE_SIZE+1) + t_x];
}
__syncthreads();
if(t_x > s)
{
row_data[global_y*(TILE_SIZE+1) + t_x]-= row_data[global_x*(TILE_SIZE+1) + s]*row_data[global_y*(TILE_SIZE+1) + s];
}
__syncthreads();
}
}
__device__ void syrk_tile(float* row_data,float* edit_data,int i,int j,int N)
{
int global_y = j*blockDim.z + threadIdx.z;
int global_x = i*blockDim.y + threadIdx.y;
int t_y = threadIdx.z;
int t_x = threadIdx.y;
float valueToSubtract = 0.0;
for(int r=0;r<TILE_SIZE;r++)
{
valueToSubtract+= row_data[r + global_y*(TILE_SIZE+1)]*row_data[r + global_x*(TILE_SIZE+1)];
}
edit_data[t_y*(TILE_SIZE+1) + t_x]-= valueToSubtract;
__syncthreads();
}
__global__ void right_looking_launch_kernel(float* read_data,int N, int M , int num_of_matrices_per_block, int shared_size_single_matrix) // N -> dim, M -> num of matrices per block
{
int no_of_tiles = (N / TILE_SIZE) + (N % TILE_SIZE != 0);
int tx = threadIdx.x;
float *rA1 = NULL;
extern __shared__ float row_data[];
// __shared__ float tile_data[TILE_SIZE*(TILE_SIZE+1)]; // Using TILE_SIZE+1 to avoid Band-conflict in Shared Memory
int tile_data_index = M * (N*(TILE_SIZE+1) + TILE_SIZE*(TILE_SIZE+1) + 1);
// __shared__ float* tile_data = &row_data[M * (N*(TILE_SIZE+1) + TILE_SIZE*(TILE_SIZE+1) + 1)];
int shared_size_single_matrix_tile_data = TILE_SIZE * (TILE_SIZE + 1);
int i,j,k;
for(i=0;i<N/TILE_SIZE;i++)
{
load_lower(read_data,&row_data[tile_data_index],i,i,N, M, shared_size_single_matrix_tile_data);
// printf("%d \n", tile_data_index + shared_size_single_matrix_tile_data * M);
// if (threadIdx.x == 0 && threadIdx.y == 0 && threadIdx.z == 0) {
// for (int z = tile_data_index; z < tile_data_index + shared_size_single_matrix_tile_data * M; z++) {
// printf("%f is at %d\n", row_data[z], z);
// }
// }
rA1 = &row_data[tile_data_index + tx*shared_size_single_matrix_tile_data];
// printf("%d\n", tx*shared_size_single_matrix_tile_data);
// potrf_tile(tile_data);
potrf_tile(rA1);
store_lower(&row_data[tile_data_index],read_data,i,i,N, M, shared_size_single_matrix_tile_data);
load_full_row(read_data,row_data,i,N, M, shared_size_single_matrix);
for(j=i+1;j<N/TILE_SIZE;j++)
{
trsm_tile(&row_data[tx*shared_size_single_matrix],i,j,N);
for(k=i+1;k<j;k++)
{
load_full(read_data,&row_data[tile_data_index],k,j,N, M, shared_size_single_matrix_tile_data);
rA1 = &row_data[tile_data_index + tx*shared_size_single_matrix_tile_data];
// syrk_tile(row_data,tile_data,k,j,N);
syrk_tile(&row_data[tx*shared_size_single_matrix],rA1,k,j,N);
store_full(&row_data[tile_data_index],read_data,k,j,N, M, shared_size_single_matrix_tile_data);
}
load_full(read_data,&row_data[tile_data_index],k,j,N, M, shared_size_single_matrix_tile_data);
syrk_tile(&row_data[tx*shared_size_single_matrix],&row_data[tile_data_index + tx*shared_size_single_matrix_tile_data],k,j,N);
store_full(&row_data[tile_data_index],read_data,k,j,N, M, shared_size_single_matrix_tile_data);
}
store_full_row(row_data,read_data,i,N, M, shared_size_single_matrix);
}
}
int main()
{
// int n,N;
// printf("Enter dimension (N) : ");
// scanf("%d",&n);
// if((n%TILE_SIZE)==0)
// N = n;
// else
// N = (((int) (n/TILE_SIZE)) + 1)*TILE_SIZE;
// size_t size = N*N*sizeof(float);
// float *M = (float *)malloc(size);
// if(M == NULL)
// {
// fprintf(stderr,"Failed to allocate host vectors!\n");
// exit(EXIT_FAILURE);
// }
// int i,j;
// printf("Enter input matrix: \n");
// for(i=0;i<N;i++)
// {
// for(j=0;j<N;j++)
// {
// if(i>=n || j>=n)
// M[i*N + j] = 1; //Padding the matrix with 1
// else
// scanf("%f",&M[i*N + j]);
// }
// }
FILE *fptr;
fptr = fopen("./dim2_256matrices.txt", "r");
int num_of_matrices, dim_of_matrix;
fscanf(fptr, "%d", &num_of_matrices);
fscanf(fptr, "%d", &dim_of_matrix);
float read_element;
float* h_A = NULL;
int numElements = num_of_matrices * dim_of_matrix * dim_of_matrix;
size_t size = numElements * sizeof(float);
cudaDeviceProp devp;
cudaGetDeviceProperties(&devp, 0);
h_A = (float *)malloc(size);
int global_id = 0;
for (int matrix_index = 0; matrix_index < num_of_matrices; matrix_index++)
{
for (int row = 0; row < dim_of_matrix; row++)
{
for (int column = 0; column < dim_of_matrix; column++)
{
fscanf(fptr, "%f", &read_element);
global_id = row * dim_of_matrix * num_of_matrices + column * num_of_matrices + matrix_index;
h_A[global_id] = read_element;
// printf("At pos %d we get %0.2f\n", global_id, h_A[global_id]);
// printf("%0.2f \n ", h_A[global_id]);
}
}
}
printf("\nRead from the input file successfully!\n");
fclose(fptr);
printf("\nPrinting the host-side input array read from the input file:\n");
for (int i = 0; i < numElements; i++) {
printf("%f ", h_A[i]);
}
printf("\n\n");
// cudaError_t err = cudaSuccess;
// float *read_data = NULL;
// err = cudaMalloc((void **)&read_data,N*N*sizeof(float));
// if(err != cudaSuccess)
// {
// fprintf(stderr,"Failed to allocate matrix on the CUDA device! (error code %s)\n",cudaGetErrorString(err));
// exit(EXIT_FAILURE);
// }
// printf("Coping the matrix from host memory to device memory\n");
// err = cudaMemcpy(read_data,M,size,cudaMemcpyHostToDevice);
// if(err != cudaSuccess)
// {
// fprintf(stderr,"Failed to copy matrix from host to device (error code %s)\n",cudaGetErrorString(err));
// exit(EXIT_FAILURE);
// }
// printf("Testing for matrix M [%dx%d]\n",N,N);
cudaError_t err = cudaSuccess;
float *d_A = NULL;
err = cudaMalloc((void **)&d_A, size);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device vector A (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy vector A from host to device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
else {
printf("Copied the h_A to device side successfully!\n\n");
}
// dim3 grid(1,1,1);
// dim3 block(TILE_SIZE,TILE_SIZE,1);
// size_t shared_size = (N*(TILE_SIZE+1) + TILE_SIZE*(TILE_SIZE+1) + 1)*sizeof(float);
// right_looking_launch_kernel<<<grid,block,shared_size>>>(read_data,N);
// err = cudaMemcpy(M,read_data,size,cudaMemcpyDeviceToHost);
// if(err != cudaSuccess)
// {
// fprintf(stderr, "Failed to copy the output matrix M from device to Host (error code %s)\n", cudaGetErrorString(err));
// exit(EXIT_FAILURE);
// }
int num_of_matrices_per_block = num_of_matrices;
dim3 grid(1, 1, 1);
dim3 block(num_of_matrices, TILE_SIZE, TILE_SIZE);
// no of tiles in a column
// int INPUT_SIZE = dim_of_matrix;
// int no_of_tiles = (INPUT_SIZE / TILE_SIZE) + (INPUT_SIZE % TILE_SIZE != 0); // ceil of (INPUT_SIZE / TILE_SIZE)
int N = dim_of_matrix;
size_t shared_size = num_of_matrices * (N*(TILE_SIZE+1) + TILE_SIZE*(TILE_SIZE+1) + 1)*sizeof(float) + num_of_matrices_per_block * TILE_SIZE*(TILE_SIZE+1) * sizeof(float);
right_looking_launch_kernel<<<grid,block,shared_size>>>(d_A, dim_of_matrix, num_of_matrices, num_of_matrices ,(num_of_matrices * (N*(TILE_SIZE+1) + TILE_SIZE*(TILE_SIZE+1) + 1))/num_of_matrices);
//left_looking_kernel<<<grid, block, num_of_matrices_per_block * 1 * TILE_SIZE * TILE_SIZE * sizeof(float)>>>(d_A, dim_of_matrix, num_of_matrices ,1 * TILE_SIZE * TILE_SIZE);
cudaError_t cudaerr = cudaDeviceSynchronize();
if (cudaerr != cudaSuccess) {
printf("kernel launch failed with error \"%s\".\n",
cudaGetErrorString(cudaerr));
}
// if(TILE_SIZE == INPUT_SIZE)
// {
// // printf("The if statement works.\n");
// left_looking_kernel<<<grid, block, num_of_matrices * 1 * TILE_SIZE * TILE_SIZE * sizeof(float)>>>(d_A, dim_of_matrix, num_of_matrices ,1 * TILE_SIZE * TILE_SIZE);
// }
// else if((no_of_tiles + 2) * TILE_SIZE * TILE_SIZE * sizeof(float) < devp.sharedMemPerBlock)
// {
// //printf("The if statement works.\n");
// left_looking_kernel_less_mem<<<grid, block, num_of_matrices * 4 * TILE_SIZE * TILE_SIZE * sizeof(float)>>>(d_A, dim_of_matrix, num_of_matrices ,4 * TILE_SIZE * TILE_SIZE);
// // left_looking_kernel<<<grid, block,num_of_matrices * (no_of_tiles + 2) * TILE_SIZE * TILE_SIZE * sizeof(float)>>>(d_A, dim_of_matrix, num_of_matrices ,(no_of_tiles + 2) * TILE_SIZE * TILE_SIZE);
// }
// else
// {
// left_looking_kernel_less_mem<<<grid, block, num_of_matrices * 4 * TILE_SIZE * TILE_SIZE * sizeof(float)>>>(d_A, dim_of_matrix, num_of_matrices ,4 * TILE_SIZE * TILE_SIZE);
// }
// printf("Printing output matrix\n");
// for(i=0;i<n;i++)
// {
// for(j=0;j<n;j++)
// {
// if(j<=i)
// printf("%f\t",M[i*N + j]);
// else
// printf("%f\t",0.0);
// }
// printf("\n");
// }
// err = cudaFree(read_data);
// if(err != cudaSuccess)
// {
// fprintf(stderr, "Failed to free device matrix M (error code %s)\n", cudaGetErrorString(err));
// exit(EXIT_FAILURE);
// }
// err = cudaDeviceReset();
// if(err != cudaSuccess)
// {
// fprintf(stderr, "Failed to deinitialize the CUDA device (error code %s)\n", cudaGetErrorString(err));
// exit(EXIT_FAILURE);
// }
// free(M);
// printf("DONE!\n");
err = cudaMemcpy(h_A, d_A, size, cudaMemcpyDeviceToHost);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy vector A from device to host (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
else {
printf("\nCopied d_A to host side successfully!\n");
}
printf("\nPrinting the output of cudememcopyDeviceToHost, i.e. the host-side array returned from device side:\n");
for (int i = 0; i < numElements; i++) {
printf("%f ", h_A[i]);
}
err = cudaFree(d_A);
if(err != cudaSuccess)
{
fprintf(stderr, "\nFailed to free device matrix M (error code %s)\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaDeviceReset();
if(err != cudaSuccess)
{
fprintf(stderr, "Failed to deinitialize the CUDA device (error code %s)\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
FILE *fptr1;
fptr1 = fopen("./output.txt", "w+");
float write_element;
fprintf(fptr1, "%d\n", num_of_matrices);
fprintf(fptr1, "%d\n", dim_of_matrix);
for (int matrix_index = 0; matrix_index < num_of_matrices; matrix_index++)
{
for (int row = 0; row < dim_of_matrix; row++)
{
for (int column = 0; column < dim_of_matrix; column++)
{
//write_element = h_A[matrix_index * dim_of_matrix * dim_of_matrix + row * dim_of_matrix + column];
global_id = row * dim_of_matrix * num_of_matrices + column * num_of_matrices + matrix_index;
write_element = h_A[global_id] ;
fprintf(fptr1, "%0.2f ", write_element);
}
fprintf(fptr1,"\n");
}
}
fclose(fptr1);
free(h_A);
printf("\n\nAll tasks completed successfully!\n\n");
return 0;
} | .file "tmpxft_0001f6b6_00000000-6_right_looking_interleaved_latest.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2069:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2069:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14store_full_rowPfS_iiii
.type _Z14store_full_rowPfS_iiii, @function
_Z14store_full_rowPfS_iiii:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z14store_full_rowPfS_iiii, .-_Z14store_full_rowPfS_iiii
.globl _Z13load_full_rowPfS_iiii
.type _Z13load_full_rowPfS_iiii, @function
_Z13load_full_rowPfS_iiii:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z13load_full_rowPfS_iiii, .-_Z13load_full_rowPfS_iiii
.globl _Z10store_fullPfS_iiiii
.type _Z10store_fullPfS_iiiii, @function
_Z10store_fullPfS_iiiii:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z10store_fullPfS_iiiii, .-_Z10store_fullPfS_iiiii
.globl _Z9load_fullPfS_iiiii
.type _Z9load_fullPfS_iiiii, @function
_Z9load_fullPfS_iiiii:
.LFB2060:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size _Z9load_fullPfS_iiiii, .-_Z9load_fullPfS_iiiii
.globl _Z11store_lowerPfS_iiiii
.type _Z11store_lowerPfS_iiiii, @function
_Z11store_lowerPfS_iiiii:
.LFB2061:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2061:
.size _Z11store_lowerPfS_iiiii, .-_Z11store_lowerPfS_iiiii
.globl _Z10load_lowerPfS_iiiii
.type _Z10load_lowerPfS_iiiii, @function
_Z10load_lowerPfS_iiiii:
.LFB2062:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2062:
.size _Z10load_lowerPfS_iiiii, .-_Z10load_lowerPfS_iiiii
.globl _Z10potrf_tilePf
.type _Z10potrf_tilePf, @function
_Z10potrf_tilePf:
.LFB2063:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2063:
.size _Z10potrf_tilePf, .-_Z10potrf_tilePf
.globl _Z9trsm_tilePfiii
.type _Z9trsm_tilePfiii, @function
_Z9trsm_tilePfiii:
.LFB2064:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2064:
.size _Z9trsm_tilePfiii, .-_Z9trsm_tilePfiii
.globl _Z9syrk_tilePfS_iii
.type _Z9syrk_tilePfS_iii, @function
_Z9syrk_tilePfS_iii:
.LFB2065:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2065:
.size _Z9syrk_tilePfS_iii, .-_Z9syrk_tilePfS_iii
.globl _Z51__device_stub__Z27right_looking_launch_kernelPfiiiiPfiiii
.type _Z51__device_stub__Z27right_looking_launch_kernelPfiiiiPfiiii, @function
_Z51__device_stub__Z27right_looking_launch_kernelPfiiiiPfiiii:
.LFB2091:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z27right_looking_launch_kernelPfiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2091:
.size _Z51__device_stub__Z27right_looking_launch_kernelPfiiiiPfiiii, .-_Z51__device_stub__Z27right_looking_launch_kernelPfiiiiPfiiii
.globl _Z27right_looking_launch_kernelPfiiii
.type _Z27right_looking_launch_kernelPfiiii, @function
_Z27right_looking_launch_kernelPfiiii:
.LFB2092:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z27right_looking_launch_kernelPfiiiiPfiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _Z27right_looking_launch_kernelPfiiii, .-_Z27right_looking_launch_kernelPfiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "./dim2_256matrices.txt"
.LC2:
.string "%d"
.LC3:
.string "%f"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "\nRead from the input file successfully!\n"
.align 8
.LC5:
.string "\nPrinting the host-side input array read from the input file:\n"
.section .rodata.str1.1
.LC6:
.string "%f "
.LC7:
.string "\n\n"
.section .rodata.str1.8
.align 8
.LC8:
.string "Failed to allocate device vector A (error code %s)!\n"
.align 8
.LC9:
.string "Failed to copy vector A from host to device (error code %s)!\n"
.align 8
.LC10:
.string "Copied the h_A to device side successfully!\n\n"
.align 8
.LC11:
.string "kernel launch failed with error \"%s\".\n"
.align 8
.LC12:
.string "Failed to copy vector A from device to host (error code %s)!\n"
.align 8
.LC13:
.string "\nCopied d_A to host side successfully!\n"
.align 8
.LC14:
.string "\nPrinting the output of cudememcopyDeviceToHost, i.e. the host-side array returned from device side:\n"
.align 8
.LC15:
.string "\nFailed to free device matrix M (error code %s)\n"
.align 8
.LC16:
.string "Failed to deinitialize the CUDA device (error code %s)\n"
.section .rodata.str1.1
.LC17:
.string "w+"
.LC18:
.string "./output.txt"
.LC19:
.string "%d\n"
.LC20:
.string "%0.2f "
.LC21:
.string "\n"
.section .rodata.str1.8
.align 8
.LC22:
.string "\n\nAll tasks completed successfully!\n\n"
.text
.globl main
.type main, @function
main:
.LFB2066:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1112, %rsp
.cfi_def_cfa_offset 1168
movq %fs:40, %rax
movq %rax, 1096(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
movq %rax, %r14
leaq 20(%rsp), %rdx
leaq .LC2(%rip), %rbx
movq %rbx, %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
leaq 24(%rsp), %rdx
movq %rbx, %rsi
movq %r14, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 24(%rsp), %eax
movl %eax, %edx
imull 20(%rsp), %edx
imull %eax, %edx
movl %edx, 12(%rsp)
movslq %edx, %rax
salq $2, %rax
movq %rax, %rbx
movq %rax, (%rsp)
leaq 64(%rsp), %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movl $0, %r13d
leaq .LC3(%rip), %r15
cmpl $0, 20(%rsp)
jg .L30
.L31:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r14, %rdi
call fclose@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 12(%rsp)
jle .L36
movq %rbp, %rbx
movq (%rsp), %rax
leaq 0(%rbp,%rax), %r13
leaq .LC6(%rip), %r12
.L37:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbx, %r13
jne .L37
.L36:
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq $0, 32(%rsp)
leaq 32(%rsp), %rdi
movq (%rsp), %rsi
call cudaMalloc@PLT
movl %eax, %edi
testl %eax, %eax
jne .L71
movl $1, %ecx
movq (%rsp), %rdx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
testl %eax, %eax
jne .L72
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 20(%rsp), %edx
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl %edx, 52(%rsp)
movl $2, 56(%rsp)
movl 24(%rsp), %eax
leal 7(%rax,%rax,2), %ebx
movl %ebx, %eax
imull %edx, %eax
cltq
leal (%rdx,%rdx,2), %edx
addl %edx, %edx
movslq %edx, %rdx
addq %rdx, %rax
movl $0, %r9d
leaq 0(,%rax,4), %r8
movq 52(%rsp), %rdx
movl $2, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L73
.L40:
call cudaDeviceSynchronize@PLT
movl %eax, %edi
testl %eax, %eax
jne .L74
.L41:
movl $2, %ecx
movq (%rsp), %rdx
movq 32(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
testl %eax, %eax
jne .L75
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 12(%rsp)
jle .L43
movq %rbp, %rbx
movq (%rsp), %r12
addq %rbp, %r12
leaq .LC6(%rip), %r13
.L44:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbx, %r12
jne .L44
.L43:
movq 32(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
testl %eax, %eax
jne .L76
call cudaDeviceReset@PLT
movl %eax, %edi
testl %eax, %eax
jne .L77
leaq .LC17(%rip), %rsi
leaq .LC18(%rip), %rdi
call fopen@PLT
movq %rax, %r13
movl 20(%rsp), %ecx
leaq .LC19(%rip), %rbx
movq %rbx, %rdx
movl $2, %esi
movq %rax, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 24(%rsp), %ecx
movq %rbx, %rdx
movl $2, %esi
movq %r13, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %r14d
leaq .LC20(%rip), %r15
cmpl $0, 20(%rsp)
jg .L47
.L48:
movq %r13, %rdi
call fclose@PLT
movq %rbp, %rdi
call free@PLT
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 1096(%rsp), %rax
subq %fs:40, %rax
jne .L78
movl $0, %eax
addq $1112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
leaq 28(%rsp), %rdx
movq %r15, %rsi
movq %r14, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 24(%rsp), %edx
movl %edx, %eax
imull %r12d, %eax
leal (%rbx,%rax), %eax
imull 20(%rsp), %eax
addl %r13d, %eax
cltq
movss 28(%rsp), %xmm0
movss %xmm0, 0(%rbp,%rax,4)
addl $1, %ebx
cmpl %ebx, %edx
jg .L32
.L34:
addl $1, %r12d
cmpl %r12d, 24(%rsp)
jle .L33
.L35:
movl $0, %ebx
cmpl $0, 24(%rsp)
jg .L32
jmp .L34
.L33:
addl $1, %r13d
cmpl %r13d, 20(%rsp)
jle .L31
.L30:
movl $0, %r12d
cmpl $0, 24(%rsp)
jg .L35
jmp .L33
.L71:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L72:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L73:
movl 20(%rsp), %edx
movl %ebx, %r8d
movl %edx, %ecx
movl 24(%rsp), %esi
movq 32(%rsp), %rdi
call _Z51__device_stub__Z27right_looking_launch_kernelPfiiiiPfiiii
jmp .L40
.L74:
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L41
.L75:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC12(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L76:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L77:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC16(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L49:
imull %r12d, %eax
leal (%rbx,%rax), %eax
imull 20(%rsp), %eax
addl %r14d, %eax
cltq
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rax,4), %xmm0
movq %r15, %rdx
movl $2, %esi
movq %r13, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addl $1, %ebx
movl 24(%rsp), %eax
cmpl %ebx, %eax
jg .L49
.L51:
leaq .LC21(%rip), %rdx
movl $2, %esi
movq %r13, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addl $1, %r12d
cmpl %r12d, 24(%rsp)
jle .L50
.L52:
movl 24(%rsp), %eax
movl $0, %ebx
testl %eax, %eax
jg .L49
jmp .L51
.L50:
addl $1, %r14d
cmpl %r14d, 20(%rsp)
jle .L48
.L47:
movl $0, %r12d
cmpl $0, 24(%rsp)
jg .L52
jmp .L50
.L78:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2066:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC23:
.string "_Z27right_looking_launch_kernelPfiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2094:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC23(%rip), %rdx
movq %rdx, %rcx
leaq _Z27right_looking_launch_kernelPfiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2094:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<cuda.h>
#include<cuda_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<cmath>
#define TILE_SIZE 2 // Tile size and block size, both are taken as 32
__device__ void store_full_row(float*,float*,int,int, int, int);
__device__ void load_full_row(float*,float*,int,int, int, int);
__device__ void store_full(float*,float*,int,int,int, int, int);
__device__ void load_full(float*,float*,int,int,int, int, int);
__device__ void store_lower(float*,float*,int,int,int, int, int);
__device__ void load_lower(float*,float*,int,int,int, int, int);
__device__ void potrf_tile(float*);
__device__ void trsm_tile(float*,int,int,int);
__device__ void syrk_tile(float*,float*,int,int,int);
__global__ void right_looking_launch_kernel(float*,int);
__device__ void store_full_row(float* read_data,float* write_data,int i,int N, int M, int shared_size_single_matrix)
{
int global_y;
int global_x = i*blockDim.y + threadIdx.y;
for(int j=0;j<N/TILE_SIZE;j++)
{
global_y = j*blockDim.z + threadIdx.z;
write_data[global_y*N*M + global_x*M + threadIdx.x] = read_data[threadIdx.y + (TILE_SIZE+1)*global_y + threadIdx.x*shared_size_single_matrix];
}
__syncthreads();
}
__device__ void load_full_row(float* read_data,float* write_data,int i,int N, int M, int shared_size_single_matrix)
{
int global_y;
int global_x = i*blockDim.y + threadIdx.y;
for(int j=0;j<N/TILE_SIZE;j++)
{
global_y = j*blockDim.z + threadIdx.z;
write_data[threadIdx.y + (TILE_SIZE+1)*global_y + threadIdx.x*shared_size_single_matrix] = read_data[global_y*N*M + global_x*M + threadIdx.x];
printf("%d, %d\n", threadIdx.y + (TILE_SIZE+1)*global_y + threadIdx.x*shared_size_single_matrix, global_y*N*M + global_x*M + threadIdx.x);
}
__syncthreads();
}
__device__ void store_full(float* read_data,float* write_data,int i,int j,int N, int M, int shared_size_single_matrix)
{
int global_y = j*blockDim.z + threadIdx.z;
int global_x = i*blockDim.y + threadIdx.y;
write_data[global_y*N*M + global_x*M + threadIdx.x] = read_data[threadIdx.y + (TILE_SIZE+1)*threadIdx.z + threadIdx.x*shared_size_single_matrix];
__syncthreads();
}
__device__ void load_full(float* read_data,float* write_data,int i,int j,int N, int M, int shared_size_single_matrix)
{
int global_y = j*blockDim.z + threadIdx.z;
int global_x = i*blockDim.y + threadIdx.y;
write_data[threadIdx.y + (TILE_SIZE+1)*threadIdx.z + threadIdx.x*shared_size_single_matrix] = read_data[global_y*N*M + global_x*M + threadIdx.x];
__syncthreads();
}
__device__ void store_lower(float* read_data,float* write_data,int i,int j,int N, int M, int shared_size_single_matrix)
{
int global_y = j*blockDim.z + threadIdx.z;
int global_x = i*blockDim.y + threadIdx.y;
// printf("%f is at %d\n", read_data[threadIdx.y + (TILE_SIZE+1)*threadIdx.z + threadIdx.x*shared_size_single_matrix], threadIdx.y + (TILE_SIZE+1)*threadIdx.z + threadIdx.x*shared_size_single_matrix);
if(threadIdx.z >= threadIdx.y)
write_data[global_y*N*M + global_x*M + threadIdx.x] = read_data[threadIdx.y + (TILE_SIZE+1)*threadIdx.z + threadIdx.x*shared_size_single_matrix];
else
write_data[global_y*N*M + global_x*M + threadIdx.x] = 0.0;
__syncthreads();
}
__device__ void load_lower(float* read_data,float* write_data,int i,int j,int N, int M, int shared_size_single_matrix)
{
int global_y = j*blockDim.z + threadIdx.z;
int global_x = i*blockDim.y + threadIdx.y;
if(threadIdx.z >= threadIdx.y)
write_data[threadIdx.y + (TILE_SIZE+1)*threadIdx.z + threadIdx.x*shared_size_single_matrix] = read_data[global_y*N*M + global_x*M + threadIdx.x];
else
write_data[threadIdx.y + (TILE_SIZE+1)*threadIdx.z + threadIdx.x*shared_size_single_matrix] = 0.0;
__syncthreads();
}
__device__ void potrf_tile(float* t_A)
{
int t_x = threadIdx.y;
int t_y = threadIdx.z;
__shared__ float temp2;
for(int k=0;k<TILE_SIZE;k++)
{
if(t_x==t_y && t_x==k)
{
t_A[k*(TILE_SIZE+1) + k] = sqrtf(t_A[k*(TILE_SIZE+1) + k]);
temp2 = t_A[k*(TILE_SIZE+1) + k];
}
__syncthreads();
if(t_x<t_y && t_x == k)
{
t_A[t_y*(TILE_SIZE+1) + k]/= temp2;
}
__syncthreads();
if(k<t_y && k<t_x && t_x<=t_y)
{
t_A[t_y*(TILE_SIZE+1) + t_x]-= t_A[t_x*(TILE_SIZE+1) + k]*t_A[t_y*(TILE_SIZE+1) + k];
}
__syncthreads();
}
}
__device__ void trsm_tile(float *row_data,int i,int j,int N)
{
int global_y = j*blockDim.z + threadIdx.z;
int global_x = i*blockDim.y + threadIdx.y;
int t_x = threadIdx.y;
int t_y = threadIdx.z;
for(int s=0;s<TILE_SIZE;s++)
{
if(t_x==s)
{
row_data[global_y*(TILE_SIZE+1) + t_x]/= row_data[global_x*(TILE_SIZE+1) + t_x];
}
__syncthreads();
if(t_x > s)
{
row_data[global_y*(TILE_SIZE+1) + t_x]-= row_data[global_x*(TILE_SIZE+1) + s]*row_data[global_y*(TILE_SIZE+1) + s];
}
__syncthreads();
}
}
__device__ void syrk_tile(float* row_data,float* edit_data,int i,int j,int N)
{
int global_y = j*blockDim.z + threadIdx.z;
int global_x = i*blockDim.y + threadIdx.y;
int t_y = threadIdx.z;
int t_x = threadIdx.y;
float valueToSubtract = 0.0;
for(int r=0;r<TILE_SIZE;r++)
{
valueToSubtract+= row_data[r + global_y*(TILE_SIZE+1)]*row_data[r + global_x*(TILE_SIZE+1)];
}
edit_data[t_y*(TILE_SIZE+1) + t_x]-= valueToSubtract;
__syncthreads();
}
__global__ void right_looking_launch_kernel(float* read_data,int N, int M , int num_of_matrices_per_block, int shared_size_single_matrix) // N -> dim, M -> num of matrices per block
{
int no_of_tiles = (N / TILE_SIZE) + (N % TILE_SIZE != 0);
int tx = threadIdx.x;
float *rA1 = NULL;
extern __shared__ float row_data[];
// __shared__ float tile_data[TILE_SIZE*(TILE_SIZE+1)]; // Using TILE_SIZE+1 to avoid Band-conflict in Shared Memory
int tile_data_index = M * (N*(TILE_SIZE+1) + TILE_SIZE*(TILE_SIZE+1) + 1);
// __shared__ float* tile_data = &row_data[M * (N*(TILE_SIZE+1) + TILE_SIZE*(TILE_SIZE+1) + 1)];
int shared_size_single_matrix_tile_data = TILE_SIZE * (TILE_SIZE + 1);
int i,j,k;
for(i=0;i<N/TILE_SIZE;i++)
{
load_lower(read_data,&row_data[tile_data_index],i,i,N, M, shared_size_single_matrix_tile_data);
// printf("%d \n", tile_data_index + shared_size_single_matrix_tile_data * M);
// if (threadIdx.x == 0 && threadIdx.y == 0 && threadIdx.z == 0) {
// for (int z = tile_data_index; z < tile_data_index + shared_size_single_matrix_tile_data * M; z++) {
// printf("%f is at %d\n", row_data[z], z);
// }
// }
rA1 = &row_data[tile_data_index + tx*shared_size_single_matrix_tile_data];
// printf("%d\n", tx*shared_size_single_matrix_tile_data);
// potrf_tile(tile_data);
potrf_tile(rA1);
store_lower(&row_data[tile_data_index],read_data,i,i,N, M, shared_size_single_matrix_tile_data);
load_full_row(read_data,row_data,i,N, M, shared_size_single_matrix);
for(j=i+1;j<N/TILE_SIZE;j++)
{
trsm_tile(&row_data[tx*shared_size_single_matrix],i,j,N);
for(k=i+1;k<j;k++)
{
load_full(read_data,&row_data[tile_data_index],k,j,N, M, shared_size_single_matrix_tile_data);
rA1 = &row_data[tile_data_index + tx*shared_size_single_matrix_tile_data];
// syrk_tile(row_data,tile_data,k,j,N);
syrk_tile(&row_data[tx*shared_size_single_matrix],rA1,k,j,N);
store_full(&row_data[tile_data_index],read_data,k,j,N, M, shared_size_single_matrix_tile_data);
}
load_full(read_data,&row_data[tile_data_index],k,j,N, M, shared_size_single_matrix_tile_data);
syrk_tile(&row_data[tx*shared_size_single_matrix],&row_data[tile_data_index + tx*shared_size_single_matrix_tile_data],k,j,N);
store_full(&row_data[tile_data_index],read_data,k,j,N, M, shared_size_single_matrix_tile_data);
}
store_full_row(row_data,read_data,i,N, M, shared_size_single_matrix);
}
}
int main()
{
// int n,N;
// printf("Enter dimension (N) : ");
// scanf("%d",&n);
// if((n%TILE_SIZE)==0)
// N = n;
// else
// N = (((int) (n/TILE_SIZE)) + 1)*TILE_SIZE;
// size_t size = N*N*sizeof(float);
// float *M = (float *)malloc(size);
// if(M == NULL)
// {
// fprintf(stderr,"Failed to allocate host vectors!\n");
// exit(EXIT_FAILURE);
// }
// int i,j;
// printf("Enter input matrix: \n");
// for(i=0;i<N;i++)
// {
// for(j=0;j<N;j++)
// {
// if(i>=n || j>=n)
// M[i*N + j] = 1; //Padding the matrix with 1
// else
// scanf("%f",&M[i*N + j]);
// }
// }
FILE *fptr;
fptr = fopen("./dim2_256matrices.txt", "r");
int num_of_matrices, dim_of_matrix;
fscanf(fptr, "%d", &num_of_matrices);
fscanf(fptr, "%d", &dim_of_matrix);
float read_element;
float* h_A = NULL;
int numElements = num_of_matrices * dim_of_matrix * dim_of_matrix;
size_t size = numElements * sizeof(float);
cudaDeviceProp devp;
cudaGetDeviceProperties(&devp, 0);
h_A = (float *)malloc(size);
int global_id = 0;
for (int matrix_index = 0; matrix_index < num_of_matrices; matrix_index++)
{
for (int row = 0; row < dim_of_matrix; row++)
{
for (int column = 0; column < dim_of_matrix; column++)
{
fscanf(fptr, "%f", &read_element);
global_id = row * dim_of_matrix * num_of_matrices + column * num_of_matrices + matrix_index;
h_A[global_id] = read_element;
// printf("At pos %d we get %0.2f\n", global_id, h_A[global_id]);
// printf("%0.2f \n ", h_A[global_id]);
}
}
}
printf("\nRead from the input file successfully!\n");
fclose(fptr);
printf("\nPrinting the host-side input array read from the input file:\n");
for (int i = 0; i < numElements; i++) {
printf("%f ", h_A[i]);
}
printf("\n\n");
// cudaError_t err = cudaSuccess;
// float *read_data = NULL;
// err = cudaMalloc((void **)&read_data,N*N*sizeof(float));
// if(err != cudaSuccess)
// {
// fprintf(stderr,"Failed to allocate matrix on the CUDA device! (error code %s)\n",cudaGetErrorString(err));
// exit(EXIT_FAILURE);
// }
// printf("Coping the matrix from host memory to device memory\n");
// err = cudaMemcpy(read_data,M,size,cudaMemcpyHostToDevice);
// if(err != cudaSuccess)
// {
// fprintf(stderr,"Failed to copy matrix from host to device (error code %s)\n",cudaGetErrorString(err));
// exit(EXIT_FAILURE);
// }
// printf("Testing for matrix M [%dx%d]\n",N,N);
cudaError_t err = cudaSuccess;
float *d_A = NULL;
err = cudaMalloc((void **)&d_A, size);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device vector A (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy vector A from host to device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
else {
printf("Copied the h_A to device side successfully!\n\n");
}
// dim3 grid(1,1,1);
// dim3 block(TILE_SIZE,TILE_SIZE,1);
// size_t shared_size = (N*(TILE_SIZE+1) + TILE_SIZE*(TILE_SIZE+1) + 1)*sizeof(float);
// right_looking_launch_kernel<<<grid,block,shared_size>>>(read_data,N);
// err = cudaMemcpy(M,read_data,size,cudaMemcpyDeviceToHost);
// if(err != cudaSuccess)
// {
// fprintf(stderr, "Failed to copy the output matrix M from device to Host (error code %s)\n", cudaGetErrorString(err));
// exit(EXIT_FAILURE);
// }
int num_of_matrices_per_block = num_of_matrices;
dim3 grid(1, 1, 1);
dim3 block(num_of_matrices, TILE_SIZE, TILE_SIZE);
// no of tiles in a column
// int INPUT_SIZE = dim_of_matrix;
// int no_of_tiles = (INPUT_SIZE / TILE_SIZE) + (INPUT_SIZE % TILE_SIZE != 0); // ceil of (INPUT_SIZE / TILE_SIZE)
int N = dim_of_matrix;
size_t shared_size = num_of_matrices * (N*(TILE_SIZE+1) + TILE_SIZE*(TILE_SIZE+1) + 1)*sizeof(float) + num_of_matrices_per_block * TILE_SIZE*(TILE_SIZE+1) * sizeof(float);
right_looking_launch_kernel<<<grid,block,shared_size>>>(d_A, dim_of_matrix, num_of_matrices, num_of_matrices ,(num_of_matrices * (N*(TILE_SIZE+1) + TILE_SIZE*(TILE_SIZE+1) + 1))/num_of_matrices);
//left_looking_kernel<<<grid, block, num_of_matrices_per_block * 1 * TILE_SIZE * TILE_SIZE * sizeof(float)>>>(d_A, dim_of_matrix, num_of_matrices ,1 * TILE_SIZE * TILE_SIZE);
cudaError_t cudaerr = cudaDeviceSynchronize();
if (cudaerr != cudaSuccess) {
printf("kernel launch failed with error \"%s\".\n",
cudaGetErrorString(cudaerr));
}
// if(TILE_SIZE == INPUT_SIZE)
// {
// // printf("The if statement works.\n");
// left_looking_kernel<<<grid, block, num_of_matrices * 1 * TILE_SIZE * TILE_SIZE * sizeof(float)>>>(d_A, dim_of_matrix, num_of_matrices ,1 * TILE_SIZE * TILE_SIZE);
// }
// else if((no_of_tiles + 2) * TILE_SIZE * TILE_SIZE * sizeof(float) < devp.sharedMemPerBlock)
// {
// //printf("The if statement works.\n");
// left_looking_kernel_less_mem<<<grid, block, num_of_matrices * 4 * TILE_SIZE * TILE_SIZE * sizeof(float)>>>(d_A, dim_of_matrix, num_of_matrices ,4 * TILE_SIZE * TILE_SIZE);
// // left_looking_kernel<<<grid, block,num_of_matrices * (no_of_tiles + 2) * TILE_SIZE * TILE_SIZE * sizeof(float)>>>(d_A, dim_of_matrix, num_of_matrices ,(no_of_tiles + 2) * TILE_SIZE * TILE_SIZE);
// }
// else
// {
// left_looking_kernel_less_mem<<<grid, block, num_of_matrices * 4 * TILE_SIZE * TILE_SIZE * sizeof(float)>>>(d_A, dim_of_matrix, num_of_matrices ,4 * TILE_SIZE * TILE_SIZE);
// }
// printf("Printing output matrix\n");
// for(i=0;i<n;i++)
// {
// for(j=0;j<n;j++)
// {
// if(j<=i)
// printf("%f\t",M[i*N + j]);
// else
// printf("%f\t",0.0);
// }
// printf("\n");
// }
// err = cudaFree(read_data);
// if(err != cudaSuccess)
// {
// fprintf(stderr, "Failed to free device matrix M (error code %s)\n", cudaGetErrorString(err));
// exit(EXIT_FAILURE);
// }
// err = cudaDeviceReset();
// if(err != cudaSuccess)
// {
// fprintf(stderr, "Failed to deinitialize the CUDA device (error code %s)\n", cudaGetErrorString(err));
// exit(EXIT_FAILURE);
// }
// free(M);
// printf("DONE!\n");
err = cudaMemcpy(h_A, d_A, size, cudaMemcpyDeviceToHost);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy vector A from device to host (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
else {
printf("\nCopied d_A to host side successfully!\n");
}
printf("\nPrinting the output of cudememcopyDeviceToHost, i.e. the host-side array returned from device side:\n");
for (int i = 0; i < numElements; i++) {
printf("%f ", h_A[i]);
}
err = cudaFree(d_A);
if(err != cudaSuccess)
{
fprintf(stderr, "\nFailed to free device matrix M (error code %s)\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaDeviceReset();
if(err != cudaSuccess)
{
fprintf(stderr, "Failed to deinitialize the CUDA device (error code %s)\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
FILE *fptr1;
fptr1 = fopen("./output.txt", "w+");
float write_element;
fprintf(fptr1, "%d\n", num_of_matrices);
fprintf(fptr1, "%d\n", dim_of_matrix);
for (int matrix_index = 0; matrix_index < num_of_matrices; matrix_index++)
{
for (int row = 0; row < dim_of_matrix; row++)
{
for (int column = 0; column < dim_of_matrix; column++)
{
//write_element = h_A[matrix_index * dim_of_matrix * dim_of_matrix + row * dim_of_matrix + column];
global_id = row * dim_of_matrix * num_of_matrices + column * num_of_matrices + matrix_index;
write_element = h_A[global_id] ;
fprintf(fptr1, "%0.2f ", write_element);
}
fprintf(fptr1,"\n");
}
}
fclose(fptr1);
free(h_A);
printf("\n\nAll tasks completed successfully!\n\n");
return 0;
} | #include<hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<cmath>
#define TILE_SIZE 2 // Tile size and block size, both are taken as 32
__device__ void store_full_row(float*,float*,int,int, int, int);
__device__ void load_full_row(float*,float*,int,int, int, int);
__device__ void store_full(float*,float*,int,int,int, int, int);
__device__ void load_full(float*,float*,int,int,int, int, int);
__device__ void store_lower(float*,float*,int,int,int, int, int);
__device__ void load_lower(float*,float*,int,int,int, int, int);
__device__ void potrf_tile(float*);
__device__ void trsm_tile(float*,int,int,int);
__device__ void syrk_tile(float*,float*,int,int,int);
__global__ void right_looking_launch_kernel(float*,int);
__device__ void store_full_row(float* read_data,float* write_data,int i,int N, int M, int shared_size_single_matrix)
{
int global_y;
int global_x = i*blockDim.y + threadIdx.y;
for(int j=0;j<N/TILE_SIZE;j++)
{
global_y = j*blockDim.z + threadIdx.z;
write_data[global_y*N*M + global_x*M + threadIdx.x] = read_data[threadIdx.y + (TILE_SIZE+1)*global_y + threadIdx.x*shared_size_single_matrix];
}
__syncthreads();
}
__device__ void load_full_row(float* read_data,float* write_data,int i,int N, int M, int shared_size_single_matrix)
{
int global_y;
int global_x = i*blockDim.y + threadIdx.y;
for(int j=0;j<N/TILE_SIZE;j++)
{
global_y = j*blockDim.z + threadIdx.z;
write_data[threadIdx.y + (TILE_SIZE+1)*global_y + threadIdx.x*shared_size_single_matrix] = read_data[global_y*N*M + global_x*M + threadIdx.x];
printf("%d, %d\n", threadIdx.y + (TILE_SIZE+1)*global_y + threadIdx.x*shared_size_single_matrix, global_y*N*M + global_x*M + threadIdx.x);
}
__syncthreads();
}
__device__ void store_full(float* read_data,float* write_data,int i,int j,int N, int M, int shared_size_single_matrix)
{
int global_y = j*blockDim.z + threadIdx.z;
int global_x = i*blockDim.y + threadIdx.y;
write_data[global_y*N*M + global_x*M + threadIdx.x] = read_data[threadIdx.y + (TILE_SIZE+1)*threadIdx.z + threadIdx.x*shared_size_single_matrix];
__syncthreads();
}
__device__ void load_full(float* read_data,float* write_data,int i,int j,int N, int M, int shared_size_single_matrix)
{
int global_y = j*blockDim.z + threadIdx.z;
int global_x = i*blockDim.y + threadIdx.y;
write_data[threadIdx.y + (TILE_SIZE+1)*threadIdx.z + threadIdx.x*shared_size_single_matrix] = read_data[global_y*N*M + global_x*M + threadIdx.x];
__syncthreads();
}
__device__ void store_lower(float* read_data,float* write_data,int i,int j,int N, int M, int shared_size_single_matrix)
{
int global_y = j*blockDim.z + threadIdx.z;
int global_x = i*blockDim.y + threadIdx.y;
// printf("%f is at %d\n", read_data[threadIdx.y + (TILE_SIZE+1)*threadIdx.z + threadIdx.x*shared_size_single_matrix], threadIdx.y + (TILE_SIZE+1)*threadIdx.z + threadIdx.x*shared_size_single_matrix);
if(threadIdx.z >= threadIdx.y)
write_data[global_y*N*M + global_x*M + threadIdx.x] = read_data[threadIdx.y + (TILE_SIZE+1)*threadIdx.z + threadIdx.x*shared_size_single_matrix];
else
write_data[global_y*N*M + global_x*M + threadIdx.x] = 0.0;
__syncthreads();
}
__device__ void load_lower(float* read_data,float* write_data,int i,int j,int N, int M, int shared_size_single_matrix)
{
int global_y = j*blockDim.z + threadIdx.z;
int global_x = i*blockDim.y + threadIdx.y;
if(threadIdx.z >= threadIdx.y)
write_data[threadIdx.y + (TILE_SIZE+1)*threadIdx.z + threadIdx.x*shared_size_single_matrix] = read_data[global_y*N*M + global_x*M + threadIdx.x];
else
write_data[threadIdx.y + (TILE_SIZE+1)*threadIdx.z + threadIdx.x*shared_size_single_matrix] = 0.0;
__syncthreads();
}
__device__ void potrf_tile(float* t_A)
{
int t_x = threadIdx.y;
int t_y = threadIdx.z;
__shared__ float temp2;
for(int k=0;k<TILE_SIZE;k++)
{
if(t_x==t_y && t_x==k)
{
t_A[k*(TILE_SIZE+1) + k] = sqrtf(t_A[k*(TILE_SIZE+1) + k]);
temp2 = t_A[k*(TILE_SIZE+1) + k];
}
__syncthreads();
if(t_x<t_y && t_x == k)
{
t_A[t_y*(TILE_SIZE+1) + k]/= temp2;
}
__syncthreads();
if(k<t_y && k<t_x && t_x<=t_y)
{
t_A[t_y*(TILE_SIZE+1) + t_x]-= t_A[t_x*(TILE_SIZE+1) + k]*t_A[t_y*(TILE_SIZE+1) + k];
}
__syncthreads();
}
}
__device__ void trsm_tile(float *row_data,int i,int j,int N)
{
int global_y = j*blockDim.z + threadIdx.z;
int global_x = i*blockDim.y + threadIdx.y;
int t_x = threadIdx.y;
int t_y = threadIdx.z;
for(int s=0;s<TILE_SIZE;s++)
{
if(t_x==s)
{
row_data[global_y*(TILE_SIZE+1) + t_x]/= row_data[global_x*(TILE_SIZE+1) + t_x];
}
__syncthreads();
if(t_x > s)
{
row_data[global_y*(TILE_SIZE+1) + t_x]-= row_data[global_x*(TILE_SIZE+1) + s]*row_data[global_y*(TILE_SIZE+1) + s];
}
__syncthreads();
}
}
__device__ void syrk_tile(float* row_data,float* edit_data,int i,int j,int N)
{
int global_y = j*blockDim.z + threadIdx.z;
int global_x = i*blockDim.y + threadIdx.y;
int t_y = threadIdx.z;
int t_x = threadIdx.y;
float valueToSubtract = 0.0;
for(int r=0;r<TILE_SIZE;r++)
{
valueToSubtract+= row_data[r + global_y*(TILE_SIZE+1)]*row_data[r + global_x*(TILE_SIZE+1)];
}
edit_data[t_y*(TILE_SIZE+1) + t_x]-= valueToSubtract;
__syncthreads();
}
__global__ void right_looking_launch_kernel(float* read_data,int N, int M , int num_of_matrices_per_block, int shared_size_single_matrix) // N -> dim, M -> num of matrices per block
{
int no_of_tiles = (N / TILE_SIZE) + (N % TILE_SIZE != 0);
int tx = threadIdx.x;
float *rA1 = NULL;
extern __shared__ float row_data[];
// __shared__ float tile_data[TILE_SIZE*(TILE_SIZE+1)]; // Using TILE_SIZE+1 to avoid Band-conflict in Shared Memory
int tile_data_index = M * (N*(TILE_SIZE+1) + TILE_SIZE*(TILE_SIZE+1) + 1);
// __shared__ float* tile_data = &row_data[M * (N*(TILE_SIZE+1) + TILE_SIZE*(TILE_SIZE+1) + 1)];
int shared_size_single_matrix_tile_data = TILE_SIZE * (TILE_SIZE + 1);
int i,j,k;
for(i=0;i<N/TILE_SIZE;i++)
{
load_lower(read_data,&row_data[tile_data_index],i,i,N, M, shared_size_single_matrix_tile_data);
// printf("%d \n", tile_data_index + shared_size_single_matrix_tile_data * M);
// if (threadIdx.x == 0 && threadIdx.y == 0 && threadIdx.z == 0) {
// for (int z = tile_data_index; z < tile_data_index + shared_size_single_matrix_tile_data * M; z++) {
// printf("%f is at %d\n", row_data[z], z);
// }
// }
rA1 = &row_data[tile_data_index + tx*shared_size_single_matrix_tile_data];
// printf("%d\n", tx*shared_size_single_matrix_tile_data);
// potrf_tile(tile_data);
potrf_tile(rA1);
store_lower(&row_data[tile_data_index],read_data,i,i,N, M, shared_size_single_matrix_tile_data);
load_full_row(read_data,row_data,i,N, M, shared_size_single_matrix);
for(j=i+1;j<N/TILE_SIZE;j++)
{
trsm_tile(&row_data[tx*shared_size_single_matrix],i,j,N);
for(k=i+1;k<j;k++)
{
load_full(read_data,&row_data[tile_data_index],k,j,N, M, shared_size_single_matrix_tile_data);
rA1 = &row_data[tile_data_index + tx*shared_size_single_matrix_tile_data];
// syrk_tile(row_data,tile_data,k,j,N);
syrk_tile(&row_data[tx*shared_size_single_matrix],rA1,k,j,N);
store_full(&row_data[tile_data_index],read_data,k,j,N, M, shared_size_single_matrix_tile_data);
}
load_full(read_data,&row_data[tile_data_index],k,j,N, M, shared_size_single_matrix_tile_data);
syrk_tile(&row_data[tx*shared_size_single_matrix],&row_data[tile_data_index + tx*shared_size_single_matrix_tile_data],k,j,N);
store_full(&row_data[tile_data_index],read_data,k,j,N, M, shared_size_single_matrix_tile_data);
}
store_full_row(row_data,read_data,i,N, M, shared_size_single_matrix);
}
}
int main()
{
// int n,N;
// printf("Enter dimension (N) : ");
// scanf("%d",&n);
// if((n%TILE_SIZE)==0)
// N = n;
// else
// N = (((int) (n/TILE_SIZE)) + 1)*TILE_SIZE;
// size_t size = N*N*sizeof(float);
// float *M = (float *)malloc(size);
// if(M == NULL)
// {
// fprintf(stderr,"Failed to allocate host vectors!\n");
// exit(EXIT_FAILURE);
// }
// int i,j;
// printf("Enter input matrix: \n");
// for(i=0;i<N;i++)
// {
// for(j=0;j<N;j++)
// {
// if(i>=n || j>=n)
// M[i*N + j] = 1; //Padding the matrix with 1
// else
// scanf("%f",&M[i*N + j]);
// }
// }
FILE *fptr;
fptr = fopen("./dim2_256matrices.txt", "r");
int num_of_matrices, dim_of_matrix;
fscanf(fptr, "%d", &num_of_matrices);
fscanf(fptr, "%d", &dim_of_matrix);
float read_element;
float* h_A = NULL;
int numElements = num_of_matrices * dim_of_matrix * dim_of_matrix;
size_t size = numElements * sizeof(float);
hipDeviceProp_t devp;
hipGetDeviceProperties(&devp, 0);
h_A = (float *)malloc(size);
int global_id = 0;
for (int matrix_index = 0; matrix_index < num_of_matrices; matrix_index++)
{
for (int row = 0; row < dim_of_matrix; row++)
{
for (int column = 0; column < dim_of_matrix; column++)
{
fscanf(fptr, "%f", &read_element);
global_id = row * dim_of_matrix * num_of_matrices + column * num_of_matrices + matrix_index;
h_A[global_id] = read_element;
// printf("At pos %d we get %0.2f\n", global_id, h_A[global_id]);
// printf("%0.2f \n ", h_A[global_id]);
}
}
}
printf("\nRead from the input file successfully!\n");
fclose(fptr);
printf("\nPrinting the host-side input array read from the input file:\n");
for (int i = 0; i < numElements; i++) {
printf("%f ", h_A[i]);
}
printf("\n\n");
// cudaError_t err = cudaSuccess;
// float *read_data = NULL;
// err = cudaMalloc((void **)&read_data,N*N*sizeof(float));
// if(err != cudaSuccess)
// {
// fprintf(stderr,"Failed to allocate matrix on the CUDA device! (error code %s)\n",cudaGetErrorString(err));
// exit(EXIT_FAILURE);
// }
// printf("Coping the matrix from host memory to device memory\n");
// err = cudaMemcpy(read_data,M,size,cudaMemcpyHostToDevice);
// if(err != cudaSuccess)
// {
// fprintf(stderr,"Failed to copy matrix from host to device (error code %s)\n",cudaGetErrorString(err));
// exit(EXIT_FAILURE);
// }
// printf("Testing for matrix M [%dx%d]\n",N,N);
hipError_t err = hipSuccess;
float *d_A = NULL;
err = hipMalloc((void **)&d_A, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device vector A (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy vector A from host to device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
else {
printf("Copied the h_A to device side successfully!\n\n");
}
// dim3 grid(1,1,1);
// dim3 block(TILE_SIZE,TILE_SIZE,1);
// size_t shared_size = (N*(TILE_SIZE+1) + TILE_SIZE*(TILE_SIZE+1) + 1)*sizeof(float);
// right_looking_launch_kernel<<<grid,block,shared_size>>>(read_data,N);
// err = cudaMemcpy(M,read_data,size,cudaMemcpyDeviceToHost);
// if(err != cudaSuccess)
// {
// fprintf(stderr, "Failed to copy the output matrix M from device to Host (error code %s)\n", cudaGetErrorString(err));
// exit(EXIT_FAILURE);
// }
int num_of_matrices_per_block = num_of_matrices;
dim3 grid(1, 1, 1);
dim3 block(num_of_matrices, TILE_SIZE, TILE_SIZE);
// no of tiles in a column
// int INPUT_SIZE = dim_of_matrix;
// int no_of_tiles = (INPUT_SIZE / TILE_SIZE) + (INPUT_SIZE % TILE_SIZE != 0); // ceil of (INPUT_SIZE / TILE_SIZE)
int N = dim_of_matrix;
size_t shared_size = num_of_matrices * (N*(TILE_SIZE+1) + TILE_SIZE*(TILE_SIZE+1) + 1)*sizeof(float) + num_of_matrices_per_block * TILE_SIZE*(TILE_SIZE+1) * sizeof(float);
right_looking_launch_kernel<<<grid,block,shared_size>>>(d_A, dim_of_matrix, num_of_matrices, num_of_matrices ,(num_of_matrices * (N*(TILE_SIZE+1) + TILE_SIZE*(TILE_SIZE+1) + 1))/num_of_matrices);
//left_looking_kernel<<<grid, block, num_of_matrices_per_block * 1 * TILE_SIZE * TILE_SIZE * sizeof(float)>>>(d_A, dim_of_matrix, num_of_matrices ,1 * TILE_SIZE * TILE_SIZE);
hipError_t cudaerr = hipDeviceSynchronize();
if (cudaerr != hipSuccess) {
printf("kernel launch failed with error \"%s\".\n",
hipGetErrorString(cudaerr));
}
// if(TILE_SIZE == INPUT_SIZE)
// {
// // printf("The if statement works.\n");
// left_looking_kernel<<<grid, block, num_of_matrices * 1 * TILE_SIZE * TILE_SIZE * sizeof(float)>>>(d_A, dim_of_matrix, num_of_matrices ,1 * TILE_SIZE * TILE_SIZE);
// }
// else if((no_of_tiles + 2) * TILE_SIZE * TILE_SIZE * sizeof(float) < devp.sharedMemPerBlock)
// {
// //printf("The if statement works.\n");
// left_looking_kernel_less_mem<<<grid, block, num_of_matrices * 4 * TILE_SIZE * TILE_SIZE * sizeof(float)>>>(d_A, dim_of_matrix, num_of_matrices ,4 * TILE_SIZE * TILE_SIZE);
// // left_looking_kernel<<<grid, block,num_of_matrices * (no_of_tiles + 2) * TILE_SIZE * TILE_SIZE * sizeof(float)>>>(d_A, dim_of_matrix, num_of_matrices ,(no_of_tiles + 2) * TILE_SIZE * TILE_SIZE);
// }
// else
// {
// left_looking_kernel_less_mem<<<grid, block, num_of_matrices * 4 * TILE_SIZE * TILE_SIZE * sizeof(float)>>>(d_A, dim_of_matrix, num_of_matrices ,4 * TILE_SIZE * TILE_SIZE);
// }
// printf("Printing output matrix\n");
// for(i=0;i<n;i++)
// {
// for(j=0;j<n;j++)
// {
// if(j<=i)
// printf("%f\t",M[i*N + j]);
// else
// printf("%f\t",0.0);
// }
// printf("\n");
// }
// err = cudaFree(read_data);
// if(err != cudaSuccess)
// {
// fprintf(stderr, "Failed to free device matrix M (error code %s)\n", cudaGetErrorString(err));
// exit(EXIT_FAILURE);
// }
// err = cudaDeviceReset();
// if(err != cudaSuccess)
// {
// fprintf(stderr, "Failed to deinitialize the CUDA device (error code %s)\n", cudaGetErrorString(err));
// exit(EXIT_FAILURE);
// }
// free(M);
// printf("DONE!\n");
err = hipMemcpy(h_A, d_A, size, hipMemcpyDeviceToHost);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy vector A from device to host (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
else {
printf("\nCopied d_A to host side successfully!\n");
}
printf("\nPrinting the output of cudememcopyDeviceToHost, i.e. the host-side array returned from device side:\n");
for (int i = 0; i < numElements; i++) {
printf("%f ", h_A[i]);
}
err = hipFree(d_A);
if(err != hipSuccess)
{
fprintf(stderr, "\nFailed to free device matrix M (error code %s)\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipDeviceReset();
if(err != hipSuccess)
{
fprintf(stderr, "Failed to deinitialize the CUDA device (error code %s)\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
FILE *fptr1;
fptr1 = fopen("./output.txt", "w+");
float write_element;
fprintf(fptr1, "%d\n", num_of_matrices);
fprintf(fptr1, "%d\n", dim_of_matrix);
for (int matrix_index = 0; matrix_index < num_of_matrices; matrix_index++)
{
for (int row = 0; row < dim_of_matrix; row++)
{
for (int column = 0; column < dim_of_matrix; column++)
{
//write_element = h_A[matrix_index * dim_of_matrix * dim_of_matrix + row * dim_of_matrix + column];
global_id = row * dim_of_matrix * num_of_matrices + column * num_of_matrices + matrix_index;
write_element = h_A[global_id] ;
fprintf(fptr1, "%0.2f ", write_element);
}
fprintf(fptr1,"\n");
}
}
fclose(fptr1);
free(h_A);
printf("\n\nAll tasks completed successfully!\n\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<cmath>
#define TILE_SIZE 2 // Tile size and block size, both are taken as 32
__device__ void store_full_row(float*,float*,int,int, int, int);
__device__ void load_full_row(float*,float*,int,int, int, int);
__device__ void store_full(float*,float*,int,int,int, int, int);
__device__ void load_full(float*,float*,int,int,int, int, int);
__device__ void store_lower(float*,float*,int,int,int, int, int);
__device__ void load_lower(float*,float*,int,int,int, int, int);
__device__ void potrf_tile(float*);
__device__ void trsm_tile(float*,int,int,int);
__device__ void syrk_tile(float*,float*,int,int,int);
__global__ void right_looking_launch_kernel(float*,int);
__device__ void store_full_row(float* read_data,float* write_data,int i,int N, int M, int shared_size_single_matrix)
{
int global_y;
int global_x = i*blockDim.y + threadIdx.y;
for(int j=0;j<N/TILE_SIZE;j++)
{
global_y = j*blockDim.z + threadIdx.z;
write_data[global_y*N*M + global_x*M + threadIdx.x] = read_data[threadIdx.y + (TILE_SIZE+1)*global_y + threadIdx.x*shared_size_single_matrix];
}
__syncthreads();
}
__device__ void load_full_row(float* read_data,float* write_data,int i,int N, int M, int shared_size_single_matrix)
{
int global_y;
int global_x = i*blockDim.y + threadIdx.y;
for(int j=0;j<N/TILE_SIZE;j++)
{
global_y = j*blockDim.z + threadIdx.z;
write_data[threadIdx.y + (TILE_SIZE+1)*global_y + threadIdx.x*shared_size_single_matrix] = read_data[global_y*N*M + global_x*M + threadIdx.x];
printf("%d, %d\n", threadIdx.y + (TILE_SIZE+1)*global_y + threadIdx.x*shared_size_single_matrix, global_y*N*M + global_x*M + threadIdx.x);
}
__syncthreads();
}
__device__ void store_full(float* read_data,float* write_data,int i,int j,int N, int M, int shared_size_single_matrix)
{
int global_y = j*blockDim.z + threadIdx.z;
int global_x = i*blockDim.y + threadIdx.y;
write_data[global_y*N*M + global_x*M + threadIdx.x] = read_data[threadIdx.y + (TILE_SIZE+1)*threadIdx.z + threadIdx.x*shared_size_single_matrix];
__syncthreads();
}
__device__ void load_full(float* read_data,float* write_data,int i,int j,int N, int M, int shared_size_single_matrix)
{
int global_y = j*blockDim.z + threadIdx.z;
int global_x = i*blockDim.y + threadIdx.y;
write_data[threadIdx.y + (TILE_SIZE+1)*threadIdx.z + threadIdx.x*shared_size_single_matrix] = read_data[global_y*N*M + global_x*M + threadIdx.x];
__syncthreads();
}
__device__ void store_lower(float* read_data,float* write_data,int i,int j,int N, int M, int shared_size_single_matrix)
{
int global_y = j*blockDim.z + threadIdx.z;
int global_x = i*blockDim.y + threadIdx.y;
// printf("%f is at %d\n", read_data[threadIdx.y + (TILE_SIZE+1)*threadIdx.z + threadIdx.x*shared_size_single_matrix], threadIdx.y + (TILE_SIZE+1)*threadIdx.z + threadIdx.x*shared_size_single_matrix);
if(threadIdx.z >= threadIdx.y)
write_data[global_y*N*M + global_x*M + threadIdx.x] = read_data[threadIdx.y + (TILE_SIZE+1)*threadIdx.z + threadIdx.x*shared_size_single_matrix];
else
write_data[global_y*N*M + global_x*M + threadIdx.x] = 0.0;
__syncthreads();
}
__device__ void load_lower(float* read_data,float* write_data,int i,int j,int N, int M, int shared_size_single_matrix)
{
int global_y = j*blockDim.z + threadIdx.z;
int global_x = i*blockDim.y + threadIdx.y;
if(threadIdx.z >= threadIdx.y)
write_data[threadIdx.y + (TILE_SIZE+1)*threadIdx.z + threadIdx.x*shared_size_single_matrix] = read_data[global_y*N*M + global_x*M + threadIdx.x];
else
write_data[threadIdx.y + (TILE_SIZE+1)*threadIdx.z + threadIdx.x*shared_size_single_matrix] = 0.0;
__syncthreads();
}
__device__ void potrf_tile(float* t_A)
{
int t_x = threadIdx.y;
int t_y = threadIdx.z;
__shared__ float temp2;
for(int k=0;k<TILE_SIZE;k++)
{
if(t_x==t_y && t_x==k)
{
t_A[k*(TILE_SIZE+1) + k] = sqrtf(t_A[k*(TILE_SIZE+1) + k]);
temp2 = t_A[k*(TILE_SIZE+1) + k];
}
__syncthreads();
if(t_x<t_y && t_x == k)
{
t_A[t_y*(TILE_SIZE+1) + k]/= temp2;
}
__syncthreads();
if(k<t_y && k<t_x && t_x<=t_y)
{
t_A[t_y*(TILE_SIZE+1) + t_x]-= t_A[t_x*(TILE_SIZE+1) + k]*t_A[t_y*(TILE_SIZE+1) + k];
}
__syncthreads();
}
}
__device__ void trsm_tile(float *row_data,int i,int j,int N)
{
int global_y = j*blockDim.z + threadIdx.z;
int global_x = i*blockDim.y + threadIdx.y;
int t_x = threadIdx.y;
int t_y = threadIdx.z;
for(int s=0;s<TILE_SIZE;s++)
{
if(t_x==s)
{
row_data[global_y*(TILE_SIZE+1) + t_x]/= row_data[global_x*(TILE_SIZE+1) + t_x];
}
__syncthreads();
if(t_x > s)
{
row_data[global_y*(TILE_SIZE+1) + t_x]-= row_data[global_x*(TILE_SIZE+1) + s]*row_data[global_y*(TILE_SIZE+1) + s];
}
__syncthreads();
}
}
__device__ void syrk_tile(float* row_data,float* edit_data,int i,int j,int N)
{
int global_y = j*blockDim.z + threadIdx.z;
int global_x = i*blockDim.y + threadIdx.y;
int t_y = threadIdx.z;
int t_x = threadIdx.y;
float valueToSubtract = 0.0;
for(int r=0;r<TILE_SIZE;r++)
{
valueToSubtract+= row_data[r + global_y*(TILE_SIZE+1)]*row_data[r + global_x*(TILE_SIZE+1)];
}
edit_data[t_y*(TILE_SIZE+1) + t_x]-= valueToSubtract;
__syncthreads();
}
__global__ void right_looking_launch_kernel(float* read_data,int N, int M , int num_of_matrices_per_block, int shared_size_single_matrix) // N -> dim, M -> num of matrices per block
{
int no_of_tiles = (N / TILE_SIZE) + (N % TILE_SIZE != 0);
int tx = threadIdx.x;
float *rA1 = NULL;
extern __shared__ float row_data[];
// __shared__ float tile_data[TILE_SIZE*(TILE_SIZE+1)]; // Using TILE_SIZE+1 to avoid Band-conflict in Shared Memory
int tile_data_index = M * (N*(TILE_SIZE+1) + TILE_SIZE*(TILE_SIZE+1) + 1);
// __shared__ float* tile_data = &row_data[M * (N*(TILE_SIZE+1) + TILE_SIZE*(TILE_SIZE+1) + 1)];
int shared_size_single_matrix_tile_data = TILE_SIZE * (TILE_SIZE + 1);
int i,j,k;
for(i=0;i<N/TILE_SIZE;i++)
{
load_lower(read_data,&row_data[tile_data_index],i,i,N, M, shared_size_single_matrix_tile_data);
// printf("%d \n", tile_data_index + shared_size_single_matrix_tile_data * M);
// if (threadIdx.x == 0 && threadIdx.y == 0 && threadIdx.z == 0) {
// for (int z = tile_data_index; z < tile_data_index + shared_size_single_matrix_tile_data * M; z++) {
// printf("%f is at %d\n", row_data[z], z);
// }
// }
rA1 = &row_data[tile_data_index + tx*shared_size_single_matrix_tile_data];
// printf("%d\n", tx*shared_size_single_matrix_tile_data);
// potrf_tile(tile_data);
potrf_tile(rA1);
store_lower(&row_data[tile_data_index],read_data,i,i,N, M, shared_size_single_matrix_tile_data);
load_full_row(read_data,row_data,i,N, M, shared_size_single_matrix);
for(j=i+1;j<N/TILE_SIZE;j++)
{
trsm_tile(&row_data[tx*shared_size_single_matrix],i,j,N);
for(k=i+1;k<j;k++)
{
load_full(read_data,&row_data[tile_data_index],k,j,N, M, shared_size_single_matrix_tile_data);
rA1 = &row_data[tile_data_index + tx*shared_size_single_matrix_tile_data];
// syrk_tile(row_data,tile_data,k,j,N);
syrk_tile(&row_data[tx*shared_size_single_matrix],rA1,k,j,N);
store_full(&row_data[tile_data_index],read_data,k,j,N, M, shared_size_single_matrix_tile_data);
}
load_full(read_data,&row_data[tile_data_index],k,j,N, M, shared_size_single_matrix_tile_data);
syrk_tile(&row_data[tx*shared_size_single_matrix],&row_data[tile_data_index + tx*shared_size_single_matrix_tile_data],k,j,N);
store_full(&row_data[tile_data_index],read_data,k,j,N, M, shared_size_single_matrix_tile_data);
}
store_full_row(row_data,read_data,i,N, M, shared_size_single_matrix);
}
}
int main()
{
// int n,N;
// printf("Enter dimension (N) : ");
// scanf("%d",&n);
// if((n%TILE_SIZE)==0)
// N = n;
// else
// N = (((int) (n/TILE_SIZE)) + 1)*TILE_SIZE;
// size_t size = N*N*sizeof(float);
// float *M = (float *)malloc(size);
// if(M == NULL)
// {
// fprintf(stderr,"Failed to allocate host vectors!\n");
// exit(EXIT_FAILURE);
// }
// int i,j;
// printf("Enter input matrix: \n");
// for(i=0;i<N;i++)
// {
// for(j=0;j<N;j++)
// {
// if(i>=n || j>=n)
// M[i*N + j] = 1; //Padding the matrix with 1
// else
// scanf("%f",&M[i*N + j]);
// }
// }
FILE *fptr;
fptr = fopen("./dim2_256matrices.txt", "r");
int num_of_matrices, dim_of_matrix;
fscanf(fptr, "%d", &num_of_matrices);
fscanf(fptr, "%d", &dim_of_matrix);
float read_element;
float* h_A = NULL;
int numElements = num_of_matrices * dim_of_matrix * dim_of_matrix;
size_t size = numElements * sizeof(float);
hipDeviceProp_t devp;
hipGetDeviceProperties(&devp, 0);
h_A = (float *)malloc(size);
int global_id = 0;
for (int matrix_index = 0; matrix_index < num_of_matrices; matrix_index++)
{
for (int row = 0; row < dim_of_matrix; row++)
{
for (int column = 0; column < dim_of_matrix; column++)
{
fscanf(fptr, "%f", &read_element);
global_id = row * dim_of_matrix * num_of_matrices + column * num_of_matrices + matrix_index;
h_A[global_id] = read_element;
// printf("At pos %d we get %0.2f\n", global_id, h_A[global_id]);
// printf("%0.2f \n ", h_A[global_id]);
}
}
}
printf("\nRead from the input file successfully!\n");
fclose(fptr);
printf("\nPrinting the host-side input array read from the input file:\n");
for (int i = 0; i < numElements; i++) {
printf("%f ", h_A[i]);
}
printf("\n\n");
// cudaError_t err = cudaSuccess;
// float *read_data = NULL;
// err = cudaMalloc((void **)&read_data,N*N*sizeof(float));
// if(err != cudaSuccess)
// {
// fprintf(stderr,"Failed to allocate matrix on the CUDA device! (error code %s)\n",cudaGetErrorString(err));
// exit(EXIT_FAILURE);
// }
// printf("Coping the matrix from host memory to device memory\n");
// err = cudaMemcpy(read_data,M,size,cudaMemcpyHostToDevice);
// if(err != cudaSuccess)
// {
// fprintf(stderr,"Failed to copy matrix from host to device (error code %s)\n",cudaGetErrorString(err));
// exit(EXIT_FAILURE);
// }
// printf("Testing for matrix M [%dx%d]\n",N,N);
hipError_t err = hipSuccess;
float *d_A = NULL;
err = hipMalloc((void **)&d_A, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device vector A (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy vector A from host to device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
else {
printf("Copied the h_A to device side successfully!\n\n");
}
// dim3 grid(1,1,1);
// dim3 block(TILE_SIZE,TILE_SIZE,1);
// size_t shared_size = (N*(TILE_SIZE+1) + TILE_SIZE*(TILE_SIZE+1) + 1)*sizeof(float);
// right_looking_launch_kernel<<<grid,block,shared_size>>>(read_data,N);
// err = cudaMemcpy(M,read_data,size,cudaMemcpyDeviceToHost);
// if(err != cudaSuccess)
// {
// fprintf(stderr, "Failed to copy the output matrix M from device to Host (error code %s)\n", cudaGetErrorString(err));
// exit(EXIT_FAILURE);
// }
int num_of_matrices_per_block = num_of_matrices;
dim3 grid(1, 1, 1);
dim3 block(num_of_matrices, TILE_SIZE, TILE_SIZE);
// no of tiles in a column
// int INPUT_SIZE = dim_of_matrix;
// int no_of_tiles = (INPUT_SIZE / TILE_SIZE) + (INPUT_SIZE % TILE_SIZE != 0); // ceil of (INPUT_SIZE / TILE_SIZE)
int N = dim_of_matrix;
size_t shared_size = num_of_matrices * (N*(TILE_SIZE+1) + TILE_SIZE*(TILE_SIZE+1) + 1)*sizeof(float) + num_of_matrices_per_block * TILE_SIZE*(TILE_SIZE+1) * sizeof(float);
right_looking_launch_kernel<<<grid,block,shared_size>>>(d_A, dim_of_matrix, num_of_matrices, num_of_matrices ,(num_of_matrices * (N*(TILE_SIZE+1) + TILE_SIZE*(TILE_SIZE+1) + 1))/num_of_matrices);
//left_looking_kernel<<<grid, block, num_of_matrices_per_block * 1 * TILE_SIZE * TILE_SIZE * sizeof(float)>>>(d_A, dim_of_matrix, num_of_matrices ,1 * TILE_SIZE * TILE_SIZE);
hipError_t cudaerr = hipDeviceSynchronize();
if (cudaerr != hipSuccess) {
printf("kernel launch failed with error \"%s\".\n",
hipGetErrorString(cudaerr));
}
// if(TILE_SIZE == INPUT_SIZE)
// {
// // printf("The if statement works.\n");
// left_looking_kernel<<<grid, block, num_of_matrices * 1 * TILE_SIZE * TILE_SIZE * sizeof(float)>>>(d_A, dim_of_matrix, num_of_matrices ,1 * TILE_SIZE * TILE_SIZE);
// }
// else if((no_of_tiles + 2) * TILE_SIZE * TILE_SIZE * sizeof(float) < devp.sharedMemPerBlock)
// {
// //printf("The if statement works.\n");
// left_looking_kernel_less_mem<<<grid, block, num_of_matrices * 4 * TILE_SIZE * TILE_SIZE * sizeof(float)>>>(d_A, dim_of_matrix, num_of_matrices ,4 * TILE_SIZE * TILE_SIZE);
// // left_looking_kernel<<<grid, block,num_of_matrices * (no_of_tiles + 2) * TILE_SIZE * TILE_SIZE * sizeof(float)>>>(d_A, dim_of_matrix, num_of_matrices ,(no_of_tiles + 2) * TILE_SIZE * TILE_SIZE);
// }
// else
// {
// left_looking_kernel_less_mem<<<grid, block, num_of_matrices * 4 * TILE_SIZE * TILE_SIZE * sizeof(float)>>>(d_A, dim_of_matrix, num_of_matrices ,4 * TILE_SIZE * TILE_SIZE);
// }
// printf("Printing output matrix\n");
// for(i=0;i<n;i++)
// {
// for(j=0;j<n;j++)
// {
// if(j<=i)
// printf("%f\t",M[i*N + j]);
// else
// printf("%f\t",0.0);
// }
// printf("\n");
// }
// err = cudaFree(read_data);
// if(err != cudaSuccess)
// {
// fprintf(stderr, "Failed to free device matrix M (error code %s)\n", cudaGetErrorString(err));
// exit(EXIT_FAILURE);
// }
// err = cudaDeviceReset();
// if(err != cudaSuccess)
// {
// fprintf(stderr, "Failed to deinitialize the CUDA device (error code %s)\n", cudaGetErrorString(err));
// exit(EXIT_FAILURE);
// }
// free(M);
// printf("DONE!\n");
err = hipMemcpy(h_A, d_A, size, hipMemcpyDeviceToHost);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy vector A from device to host (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
else {
printf("\nCopied d_A to host side successfully!\n");
}
printf("\nPrinting the output of cudememcopyDeviceToHost, i.e. the host-side array returned from device side:\n");
for (int i = 0; i < numElements; i++) {
printf("%f ", h_A[i]);
}
err = hipFree(d_A);
if(err != hipSuccess)
{
fprintf(stderr, "\nFailed to free device matrix M (error code %s)\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipDeviceReset();
if(err != hipSuccess)
{
fprintf(stderr, "Failed to deinitialize the CUDA device (error code %s)\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
FILE *fptr1;
fptr1 = fopen("./output.txt", "w+");
float write_element;
fprintf(fptr1, "%d\n", num_of_matrices);
fprintf(fptr1, "%d\n", dim_of_matrix);
for (int matrix_index = 0; matrix_index < num_of_matrices; matrix_index++)
{
for (int row = 0; row < dim_of_matrix; row++)
{
for (int column = 0; column < dim_of_matrix; column++)
{
//write_element = h_A[matrix_index * dim_of_matrix * dim_of_matrix + row * dim_of_matrix + column];
global_id = row * dim_of_matrix * num_of_matrices + column * num_of_matrices + matrix_index;
write_element = h_A[global_id] ;
fprintf(fptr1, "%0.2f ", write_element);
}
fprintf(fptr1,"\n");
}
}
fclose(fptr1);
free(h_A);
printf("\n\nAll tasks completed successfully!\n\n");
return 0;
} | .text
.file "right_looking_interleaved_latest.hip"
.globl _Z42__device_stub__right_looking_launch_kernelPfiiii # -- Begin function _Z42__device_stub__right_looking_launch_kernelPfiiii
.p2align 4, 0x90
.type _Z42__device_stub__right_looking_launch_kernelPfiiii,@function
_Z42__device_stub__right_looking_launch_kernelPfiiii: # @_Z42__device_stub__right_looking_launch_kernelPfiiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z27right_looking_launch_kernelPfiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z42__device_stub__right_looking_launch_kernelPfiiii, .Lfunc_end0-_Z42__device_stub__right_looking_launch_kernelPfiiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1624, %rsp # imm = 0x658
.cfi_def_cfa_offset 1680
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %r15
leaq 12(%rsp), %rdx
movl $.L.str.2, %esi
movq %rax, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
leaq 8(%rsp), %rdx
movl $.L.str.2, %esi
movq %r15, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movl 8(%rsp), %eax
movl 12(%rsp), %ecx
imull %eax, %ecx
imull %eax, %ecx
movl %ecx, 24(%rsp) # 4-byte Spill
movslq %ecx, %rbx
shlq $2, %rbx
leaq 152(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movq %rbx, 48(%rsp) # 8-byte Spill
movq %rbx, %rdi
callq malloc
movq %rax, %rbx
cmpl $0, 12(%rsp)
jle .LBB1_9
# %bb.1: # %.preheader103.preheader
leaq 28(%rsp), %r12
xorl %r13d, %r13d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_8: # %._crit_edge106
# in Loop: Header=BB1_2 Depth=1
incl %r13d
cmpl 12(%rsp), %r13d
jge .LBB1_9
.LBB1_2: # %.preheader103
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
# Child Loop BB1_6 Depth 3
cmpl $0, 8(%rsp)
jle .LBB1_8
# %bb.3: # %.preheader102.preheader
# in Loop: Header=BB1_2 Depth=1
xorl %r14d, %r14d
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_7: # %._crit_edge
# in Loop: Header=BB1_4 Depth=2
incl %r14d
cmpl 8(%rsp), %r14d
jge .LBB1_8
.LBB1_4: # %.preheader102
# Parent Loop BB1_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_6 Depth 3
cmpl $0, 8(%rsp)
jle .LBB1_7
# %bb.5: # %.lr.ph.preheader
# in Loop: Header=BB1_4 Depth=2
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_6: # %.lr.ph
# Parent Loop BB1_2 Depth=1
# Parent Loop BB1_4 Depth=2
# => This Inner Loop Header: Depth=3
movl $.L.str.3, %esi
movq %r15, %rdi
movq %r12, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movl 8(%rsp), %eax
imull %r14d, %eax
addl %ebp, %eax
imull 12(%rsp), %eax
addl %r13d, %eax
movss 28(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cltq
movss %xmm0, (%rbx,%rax,4)
incl %ebp
cmpl 8(%rsp), %ebp
jl .LBB1_6
jmp .LBB1_7
.LBB1_9: # %._crit_edge108
movl $.Lstr, %edi
callq puts@PLT
movq %r15, %rdi
callq fclose
movl $.Lstr.1, %edi
callq puts@PLT
movl 24(%rsp), %ebp # 4-byte Reload
movl %ebp, %r15d
testl %ebp, %ebp
jle .LBB1_12
# %bb.10: # %.lr.ph111.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_11: # %.lr.ph111
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
incq %r14
cmpq %r14, %r15
jne .LBB1_11
.LBB1_12: # %._crit_edge112
movl $.Lstr.2, %edi
callq puts@PLT
movq $0, 16(%rsp)
leaq 16(%rsp), %rdi
movq 48(%rsp), %r12 # 8-byte Reload
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_13
# %bb.15:
movq 16(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_16
# %bb.17:
movl $.Lstr.3, %edi
callq puts@PLT
movl 12(%rsp), %eax
movslq %eax, %rcx
movabsq $8589934592, %rdx # imm = 0x200000000
orq %rax, %rdx
movslq 8(%rsp), %rax
leaq (%rax,%rax,2), %r14
addq $7, %r14
movq %r14, %rax
imulq %rcx, %rax
leaq (%rcx,%rcx,2), %rcx
leaq (%rax,%rcx,2), %r8
shlq $2, %r8
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movl $2, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_19
# %bb.18:
movq 16(%rsp), %rax
movl 8(%rsp), %ecx
movl 12(%rsp), %edx
movq %rax, 104(%rsp)
movl %ecx, 44(%rsp)
movl %edx, 40(%rsp)
movl %edx, 36(%rsp)
movl %r14d, 32(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 44(%rsp), %rax
movq %rax, 120(%rsp)
leaq 40(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z27right_looking_launch_kernelPfiiii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_19:
callq hipDeviceSynchronize
testl %eax, %eax
je .LBB1_21
# %bb.20:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.11, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB1_21:
movq 16(%rsp), %rsi
movq %rbx, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_22
# %bb.23:
movl $.Lstr.4, %edi
callq puts@PLT
movl $.Lstr.5, %edi
callq puts@PLT
testl %ebp, %ebp
jle .LBB1_26
# %bb.24: # %.lr.ph115.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_25: # %.lr.ph115
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
incq %r14
cmpq %r14, %r15
jne .LBB1_25
.LBB1_26: # %._crit_edge116
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_27
# %bb.28:
callq hipDeviceReset
testl %eax, %eax
jne .LBB1_29
# %bb.30:
movl $.L.str.17, %edi
movl $.L.str.18, %esi
callq fopen
movq %rax, %r14
movl 12(%rsp), %edx
xorl %ebp, %ebp
movl $.L.str.19, %esi
movq %rax, %rdi
xorl %eax, %eax
callq fprintf
movl 8(%rsp), %edx
movl $.L.str.19, %esi
movq %r14, %rdi
xorl %eax, %eax
callq fprintf
cmpl $0, 12(%rsp)
jg .LBB1_31
.LBB1_38: # %._crit_edge123
movq %r14, %rdi
callq fclose
movq %rbx, %rdi
callq free
movl $.Lstr.6, %edi
callq puts@PLT
xorl %eax, %eax
addq $1624, %rsp # imm = 0x658
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.p2align 4, 0x90
.LBB1_37: # %._crit_edge121
# in Loop: Header=BB1_31 Depth=1
.cfi_def_cfa_offset 1680
incl %ebp
cmpl 12(%rsp), %ebp
jge .LBB1_38
.LBB1_31: # %.preheader101
# =>This Loop Header: Depth=1
# Child Loop BB1_33 Depth 2
# Child Loop BB1_35 Depth 3
cmpl $0, 8(%rsp)
jle .LBB1_37
# %bb.32: # %.preheader.preheader
# in Loop: Header=BB1_31 Depth=1
xorl %r15d, %r15d
jmp .LBB1_33
.p2align 4, 0x90
.LBB1_36: # %._crit_edge119
# in Loop: Header=BB1_33 Depth=2
movl $10, %edi
movq %r14, %rsi
callq fputc@PLT
incl %r15d
cmpl 8(%rsp), %r15d
jge .LBB1_37
.LBB1_33: # %.preheader
# Parent Loop BB1_31 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_35 Depth 3
movl 8(%rsp), %eax
testl %eax, %eax
jle .LBB1_36
# %bb.34: # %.lr.ph118.preheader
# in Loop: Header=BB1_33 Depth=2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_35: # %.lr.ph118
# Parent Loop BB1_31 Depth=1
# Parent Loop BB1_33 Depth=2
# => This Inner Loop Header: Depth=3
imull %r15d, %eax
addl %r12d, %eax
imull 12(%rsp), %eax
addl %ebp, %eax
cltq
movss (%rbx,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.20, %esi
movq %r14, %rdi
movb $1, %al
callq fprintf
incl %r12d
movl 8(%rsp), %eax
cmpl %eax, %r12d
jl .LBB1_35
jmp .LBB1_36
.LBB1_13:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
jmp .LBB1_14
.LBB1_16:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.9, %esi
jmp .LBB1_14
.LBB1_22:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.12, %esi
jmp .LBB1_14
.LBB1_27:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.15, %esi
jmp .LBB1_14
.LBB1_29:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.16, %esi
.LBB1_14:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27right_looking_launch_kernelPfiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z27right_looking_launch_kernelPfiiii,@object # @_Z27right_looking_launch_kernelPfiiii
.section .rodata,"a",@progbits
.globl _Z27right_looking_launch_kernelPfiiii
.p2align 3, 0x0
_Z27right_looking_launch_kernelPfiiii:
.quad _Z42__device_stub__right_looking_launch_kernelPfiiii
.size _Z27right_looking_launch_kernelPfiiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "./dim2_256matrices.txt"
.size .L.str, 23
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "r"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%f"
.size .L.str.3, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%f "
.size .L.str.6, 4
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Failed to allocate device vector A (error code %s)!\n"
.size .L.str.8, 53
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Failed to copy vector A from host to device (error code %s)!\n"
.size .L.str.9, 62
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "kernel launch failed with error \"%s\".\n"
.size .L.str.11, 39
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Failed to copy vector A from device to host (error code %s)!\n"
.size .L.str.12, 62
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "\nFailed to free device matrix M (error code %s)\n"
.size .L.str.15, 49
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "Failed to deinitialize the CUDA device (error code %s)\n"
.size .L.str.16, 56
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "./output.txt"
.size .L.str.17, 13
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "w+"
.size .L.str.18, 3
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "%d\n"
.size .L.str.19, 4
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "%0.2f "
.size .L.str.20, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z27right_looking_launch_kernelPfiiii"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nRead from the input file successfully!"
.size .Lstr, 40
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\nPrinting the host-side input array read from the input file:"
.size .Lstr.1, 62
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\n"
.size .Lstr.2, 2
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Copied the h_A to device side successfully!\n"
.size .Lstr.3, 45
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "\nCopied d_A to host side successfully!"
.size .Lstr.4, 39
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "\nPrinting the output of cudememcopyDeviceToHost, i.e. the host-side array returned from device side:"
.size .Lstr.5, 101
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "\n\nAll tasks completed successfully!\n"
.size .Lstr.6, 37
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z42__device_stub__right_looking_launch_kernelPfiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z27right_looking_launch_kernelPfiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001f6b6_00000000-6_right_looking_interleaved_latest.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2069:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2069:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14store_full_rowPfS_iiii
.type _Z14store_full_rowPfS_iiii, @function
_Z14store_full_rowPfS_iiii:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z14store_full_rowPfS_iiii, .-_Z14store_full_rowPfS_iiii
.globl _Z13load_full_rowPfS_iiii
.type _Z13load_full_rowPfS_iiii, @function
_Z13load_full_rowPfS_iiii:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z13load_full_rowPfS_iiii, .-_Z13load_full_rowPfS_iiii
.globl _Z10store_fullPfS_iiiii
.type _Z10store_fullPfS_iiiii, @function
_Z10store_fullPfS_iiiii:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z10store_fullPfS_iiiii, .-_Z10store_fullPfS_iiiii
.globl _Z9load_fullPfS_iiiii
.type _Z9load_fullPfS_iiiii, @function
_Z9load_fullPfS_iiiii:
.LFB2060:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size _Z9load_fullPfS_iiiii, .-_Z9load_fullPfS_iiiii
.globl _Z11store_lowerPfS_iiiii
.type _Z11store_lowerPfS_iiiii, @function
_Z11store_lowerPfS_iiiii:
.LFB2061:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2061:
.size _Z11store_lowerPfS_iiiii, .-_Z11store_lowerPfS_iiiii
.globl _Z10load_lowerPfS_iiiii
.type _Z10load_lowerPfS_iiiii, @function
_Z10load_lowerPfS_iiiii:
.LFB2062:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2062:
.size _Z10load_lowerPfS_iiiii, .-_Z10load_lowerPfS_iiiii
.globl _Z10potrf_tilePf
.type _Z10potrf_tilePf, @function
_Z10potrf_tilePf:
.LFB2063:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2063:
.size _Z10potrf_tilePf, .-_Z10potrf_tilePf
.globl _Z9trsm_tilePfiii
.type _Z9trsm_tilePfiii, @function
_Z9trsm_tilePfiii:
.LFB2064:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2064:
.size _Z9trsm_tilePfiii, .-_Z9trsm_tilePfiii
.globl _Z9syrk_tilePfS_iii
.type _Z9syrk_tilePfS_iii, @function
_Z9syrk_tilePfS_iii:
.LFB2065:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2065:
.size _Z9syrk_tilePfS_iii, .-_Z9syrk_tilePfS_iii
.globl _Z51__device_stub__Z27right_looking_launch_kernelPfiiiiPfiiii
.type _Z51__device_stub__Z27right_looking_launch_kernelPfiiiiPfiiii, @function
_Z51__device_stub__Z27right_looking_launch_kernelPfiiiiPfiiii:
.LFB2091:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z27right_looking_launch_kernelPfiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2091:
.size _Z51__device_stub__Z27right_looking_launch_kernelPfiiiiPfiiii, .-_Z51__device_stub__Z27right_looking_launch_kernelPfiiiiPfiiii
.globl _Z27right_looking_launch_kernelPfiiii
.type _Z27right_looking_launch_kernelPfiiii, @function
_Z27right_looking_launch_kernelPfiiii:
.LFB2092:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z27right_looking_launch_kernelPfiiiiPfiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _Z27right_looking_launch_kernelPfiiii, .-_Z27right_looking_launch_kernelPfiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "./dim2_256matrices.txt"
.LC2:
.string "%d"
.LC3:
.string "%f"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "\nRead from the input file successfully!\n"
.align 8
.LC5:
.string "\nPrinting the host-side input array read from the input file:\n"
.section .rodata.str1.1
.LC6:
.string "%f "
.LC7:
.string "\n\n"
.section .rodata.str1.8
.align 8
.LC8:
.string "Failed to allocate device vector A (error code %s)!\n"
.align 8
.LC9:
.string "Failed to copy vector A from host to device (error code %s)!\n"
.align 8
.LC10:
.string "Copied the h_A to device side successfully!\n\n"
.align 8
.LC11:
.string "kernel launch failed with error \"%s\".\n"
.align 8
.LC12:
.string "Failed to copy vector A from device to host (error code %s)!\n"
.align 8
.LC13:
.string "\nCopied d_A to host side successfully!\n"
.align 8
.LC14:
.string "\nPrinting the output of cudememcopyDeviceToHost, i.e. the host-side array returned from device side:\n"
.align 8
.LC15:
.string "\nFailed to free device matrix M (error code %s)\n"
.align 8
.LC16:
.string "Failed to deinitialize the CUDA device (error code %s)\n"
.section .rodata.str1.1
.LC17:
.string "w+"
.LC18:
.string "./output.txt"
.LC19:
.string "%d\n"
.LC20:
.string "%0.2f "
.LC21:
.string "\n"
.section .rodata.str1.8
.align 8
.LC22:
.string "\n\nAll tasks completed successfully!\n\n"
.text
.globl main
.type main, @function
main:
.LFB2066:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1112, %rsp
.cfi_def_cfa_offset 1168
movq %fs:40, %rax
movq %rax, 1096(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
movq %rax, %r14
leaq 20(%rsp), %rdx
leaq .LC2(%rip), %rbx
movq %rbx, %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
leaq 24(%rsp), %rdx
movq %rbx, %rsi
movq %r14, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 24(%rsp), %eax
movl %eax, %edx
imull 20(%rsp), %edx
imull %eax, %edx
movl %edx, 12(%rsp)
movslq %edx, %rax
salq $2, %rax
movq %rax, %rbx
movq %rax, (%rsp)
leaq 64(%rsp), %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movl $0, %r13d
leaq .LC3(%rip), %r15
cmpl $0, 20(%rsp)
jg .L30
.L31:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r14, %rdi
call fclose@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 12(%rsp)
jle .L36
movq %rbp, %rbx
movq (%rsp), %rax
leaq 0(%rbp,%rax), %r13
leaq .LC6(%rip), %r12
.L37:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbx, %r13
jne .L37
.L36:
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq $0, 32(%rsp)
leaq 32(%rsp), %rdi
movq (%rsp), %rsi
call cudaMalloc@PLT
movl %eax, %edi
testl %eax, %eax
jne .L71
movl $1, %ecx
movq (%rsp), %rdx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
testl %eax, %eax
jne .L72
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 20(%rsp), %edx
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl %edx, 52(%rsp)
movl $2, 56(%rsp)
movl 24(%rsp), %eax
leal 7(%rax,%rax,2), %ebx
movl %ebx, %eax
imull %edx, %eax
cltq
leal (%rdx,%rdx,2), %edx
addl %edx, %edx
movslq %edx, %rdx
addq %rdx, %rax
movl $0, %r9d
leaq 0(,%rax,4), %r8
movq 52(%rsp), %rdx
movl $2, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L73
.L40:
call cudaDeviceSynchronize@PLT
movl %eax, %edi
testl %eax, %eax
jne .L74
.L41:
movl $2, %ecx
movq (%rsp), %rdx
movq 32(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
testl %eax, %eax
jne .L75
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 12(%rsp)
jle .L43
movq %rbp, %rbx
movq (%rsp), %r12
addq %rbp, %r12
leaq .LC6(%rip), %r13
.L44:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbx, %r12
jne .L44
.L43:
movq 32(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
testl %eax, %eax
jne .L76
call cudaDeviceReset@PLT
movl %eax, %edi
testl %eax, %eax
jne .L77
leaq .LC17(%rip), %rsi
leaq .LC18(%rip), %rdi
call fopen@PLT
movq %rax, %r13
movl 20(%rsp), %ecx
leaq .LC19(%rip), %rbx
movq %rbx, %rdx
movl $2, %esi
movq %rax, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 24(%rsp), %ecx
movq %rbx, %rdx
movl $2, %esi
movq %r13, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %r14d
leaq .LC20(%rip), %r15
cmpl $0, 20(%rsp)
jg .L47
.L48:
movq %r13, %rdi
call fclose@PLT
movq %rbp, %rdi
call free@PLT
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 1096(%rsp), %rax
subq %fs:40, %rax
jne .L78
movl $0, %eax
addq $1112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
leaq 28(%rsp), %rdx
movq %r15, %rsi
movq %r14, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 24(%rsp), %edx
movl %edx, %eax
imull %r12d, %eax
leal (%rbx,%rax), %eax
imull 20(%rsp), %eax
addl %r13d, %eax
cltq
movss 28(%rsp), %xmm0
movss %xmm0, 0(%rbp,%rax,4)
addl $1, %ebx
cmpl %ebx, %edx
jg .L32
.L34:
addl $1, %r12d
cmpl %r12d, 24(%rsp)
jle .L33
.L35:
movl $0, %ebx
cmpl $0, 24(%rsp)
jg .L32
jmp .L34
.L33:
addl $1, %r13d
cmpl %r13d, 20(%rsp)
jle .L31
.L30:
movl $0, %r12d
cmpl $0, 24(%rsp)
jg .L35
jmp .L33
.L71:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L72:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L73:
movl 20(%rsp), %edx
movl %ebx, %r8d
movl %edx, %ecx
movl 24(%rsp), %esi
movq 32(%rsp), %rdi
call _Z51__device_stub__Z27right_looking_launch_kernelPfiiiiPfiiii
jmp .L40
.L74:
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L41
.L75:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC12(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L76:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L77:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC16(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L49:
imull %r12d, %eax
leal (%rbx,%rax), %eax
imull 20(%rsp), %eax
addl %r14d, %eax
cltq
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rax,4), %xmm0
movq %r15, %rdx
movl $2, %esi
movq %r13, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addl $1, %ebx
movl 24(%rsp), %eax
cmpl %ebx, %eax
jg .L49
.L51:
leaq .LC21(%rip), %rdx
movl $2, %esi
movq %r13, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addl $1, %r12d
cmpl %r12d, 24(%rsp)
jle .L50
.L52:
movl 24(%rsp), %eax
movl $0, %ebx
testl %eax, %eax
jg .L49
jmp .L51
.L50:
addl $1, %r14d
cmpl %r14d, 20(%rsp)
jle .L48
.L47:
movl $0, %r12d
cmpl $0, 24(%rsp)
jg .L52
jmp .L50
.L78:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2066:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC23:
.string "_Z27right_looking_launch_kernelPfiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2094:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC23(%rip), %rdx
movq %rdx, %rcx
leaq _Z27right_looking_launch_kernelPfiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2094:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "right_looking_interleaved_latest.hip"
.globl _Z42__device_stub__right_looking_launch_kernelPfiiii # -- Begin function _Z42__device_stub__right_looking_launch_kernelPfiiii
.p2align 4, 0x90
.type _Z42__device_stub__right_looking_launch_kernelPfiiii,@function
_Z42__device_stub__right_looking_launch_kernelPfiiii: # @_Z42__device_stub__right_looking_launch_kernelPfiiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z27right_looking_launch_kernelPfiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z42__device_stub__right_looking_launch_kernelPfiiii, .Lfunc_end0-_Z42__device_stub__right_looking_launch_kernelPfiiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1624, %rsp # imm = 0x658
.cfi_def_cfa_offset 1680
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %r15
leaq 12(%rsp), %rdx
movl $.L.str.2, %esi
movq %rax, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
leaq 8(%rsp), %rdx
movl $.L.str.2, %esi
movq %r15, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movl 8(%rsp), %eax
movl 12(%rsp), %ecx
imull %eax, %ecx
imull %eax, %ecx
movl %ecx, 24(%rsp) # 4-byte Spill
movslq %ecx, %rbx
shlq $2, %rbx
leaq 152(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movq %rbx, 48(%rsp) # 8-byte Spill
movq %rbx, %rdi
callq malloc
movq %rax, %rbx
cmpl $0, 12(%rsp)
jle .LBB1_9
# %bb.1: # %.preheader103.preheader
leaq 28(%rsp), %r12
xorl %r13d, %r13d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_8: # %._crit_edge106
# in Loop: Header=BB1_2 Depth=1
incl %r13d
cmpl 12(%rsp), %r13d
jge .LBB1_9
.LBB1_2: # %.preheader103
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
# Child Loop BB1_6 Depth 3
cmpl $0, 8(%rsp)
jle .LBB1_8
# %bb.3: # %.preheader102.preheader
# in Loop: Header=BB1_2 Depth=1
xorl %r14d, %r14d
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_7: # %._crit_edge
# in Loop: Header=BB1_4 Depth=2
incl %r14d
cmpl 8(%rsp), %r14d
jge .LBB1_8
.LBB1_4: # %.preheader102
# Parent Loop BB1_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_6 Depth 3
cmpl $0, 8(%rsp)
jle .LBB1_7
# %bb.5: # %.lr.ph.preheader
# in Loop: Header=BB1_4 Depth=2
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_6: # %.lr.ph
# Parent Loop BB1_2 Depth=1
# Parent Loop BB1_4 Depth=2
# => This Inner Loop Header: Depth=3
movl $.L.str.3, %esi
movq %r15, %rdi
movq %r12, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movl 8(%rsp), %eax
imull %r14d, %eax
addl %ebp, %eax
imull 12(%rsp), %eax
addl %r13d, %eax
movss 28(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cltq
movss %xmm0, (%rbx,%rax,4)
incl %ebp
cmpl 8(%rsp), %ebp
jl .LBB1_6
jmp .LBB1_7
.LBB1_9: # %._crit_edge108
movl $.Lstr, %edi
callq puts@PLT
movq %r15, %rdi
callq fclose
movl $.Lstr.1, %edi
callq puts@PLT
movl 24(%rsp), %ebp # 4-byte Reload
movl %ebp, %r15d
testl %ebp, %ebp
jle .LBB1_12
# %bb.10: # %.lr.ph111.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_11: # %.lr.ph111
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
incq %r14
cmpq %r14, %r15
jne .LBB1_11
.LBB1_12: # %._crit_edge112
movl $.Lstr.2, %edi
callq puts@PLT
movq $0, 16(%rsp)
leaq 16(%rsp), %rdi
movq 48(%rsp), %r12 # 8-byte Reload
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_13
# %bb.15:
movq 16(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_16
# %bb.17:
movl $.Lstr.3, %edi
callq puts@PLT
movl 12(%rsp), %eax
movslq %eax, %rcx
movabsq $8589934592, %rdx # imm = 0x200000000
orq %rax, %rdx
movslq 8(%rsp), %rax
leaq (%rax,%rax,2), %r14
addq $7, %r14
movq %r14, %rax
imulq %rcx, %rax
leaq (%rcx,%rcx,2), %rcx
leaq (%rax,%rcx,2), %r8
shlq $2, %r8
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movl $2, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_19
# %bb.18:
movq 16(%rsp), %rax
movl 8(%rsp), %ecx
movl 12(%rsp), %edx
movq %rax, 104(%rsp)
movl %ecx, 44(%rsp)
movl %edx, 40(%rsp)
movl %edx, 36(%rsp)
movl %r14d, 32(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 44(%rsp), %rax
movq %rax, 120(%rsp)
leaq 40(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z27right_looking_launch_kernelPfiiii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_19:
callq hipDeviceSynchronize
testl %eax, %eax
je .LBB1_21
# %bb.20:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.11, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB1_21:
movq 16(%rsp), %rsi
movq %rbx, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_22
# %bb.23:
movl $.Lstr.4, %edi
callq puts@PLT
movl $.Lstr.5, %edi
callq puts@PLT
testl %ebp, %ebp
jle .LBB1_26
# %bb.24: # %.lr.ph115.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_25: # %.lr.ph115
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
incq %r14
cmpq %r14, %r15
jne .LBB1_25
.LBB1_26: # %._crit_edge116
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_27
# %bb.28:
callq hipDeviceReset
testl %eax, %eax
jne .LBB1_29
# %bb.30:
movl $.L.str.17, %edi
movl $.L.str.18, %esi
callq fopen
movq %rax, %r14
movl 12(%rsp), %edx
xorl %ebp, %ebp
movl $.L.str.19, %esi
movq %rax, %rdi
xorl %eax, %eax
callq fprintf
movl 8(%rsp), %edx
movl $.L.str.19, %esi
movq %r14, %rdi
xorl %eax, %eax
callq fprintf
cmpl $0, 12(%rsp)
jg .LBB1_31
.LBB1_38: # %._crit_edge123
movq %r14, %rdi
callq fclose
movq %rbx, %rdi
callq free
movl $.Lstr.6, %edi
callq puts@PLT
xorl %eax, %eax
addq $1624, %rsp # imm = 0x658
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.p2align 4, 0x90
.LBB1_37: # %._crit_edge121
# in Loop: Header=BB1_31 Depth=1
.cfi_def_cfa_offset 1680
incl %ebp
cmpl 12(%rsp), %ebp
jge .LBB1_38
.LBB1_31: # %.preheader101
# =>This Loop Header: Depth=1
# Child Loop BB1_33 Depth 2
# Child Loop BB1_35 Depth 3
cmpl $0, 8(%rsp)
jle .LBB1_37
# %bb.32: # %.preheader.preheader
# in Loop: Header=BB1_31 Depth=1
xorl %r15d, %r15d
jmp .LBB1_33
.p2align 4, 0x90
.LBB1_36: # %._crit_edge119
# in Loop: Header=BB1_33 Depth=2
movl $10, %edi
movq %r14, %rsi
callq fputc@PLT
incl %r15d
cmpl 8(%rsp), %r15d
jge .LBB1_37
.LBB1_33: # %.preheader
# Parent Loop BB1_31 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_35 Depth 3
movl 8(%rsp), %eax
testl %eax, %eax
jle .LBB1_36
# %bb.34: # %.lr.ph118.preheader
# in Loop: Header=BB1_33 Depth=2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_35: # %.lr.ph118
# Parent Loop BB1_31 Depth=1
# Parent Loop BB1_33 Depth=2
# => This Inner Loop Header: Depth=3
imull %r15d, %eax
addl %r12d, %eax
imull 12(%rsp), %eax
addl %ebp, %eax
cltq
movss (%rbx,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.20, %esi
movq %r14, %rdi
movb $1, %al
callq fprintf
incl %r12d
movl 8(%rsp), %eax
cmpl %eax, %r12d
jl .LBB1_35
jmp .LBB1_36
.LBB1_13:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
jmp .LBB1_14
.LBB1_16:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.9, %esi
jmp .LBB1_14
.LBB1_22:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.12, %esi
jmp .LBB1_14
.LBB1_27:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.15, %esi
jmp .LBB1_14
.LBB1_29:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.16, %esi
.LBB1_14:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27right_looking_launch_kernelPfiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z27right_looking_launch_kernelPfiiii,@object # @_Z27right_looking_launch_kernelPfiiii
.section .rodata,"a",@progbits
.globl _Z27right_looking_launch_kernelPfiiii
.p2align 3, 0x0
_Z27right_looking_launch_kernelPfiiii:
.quad _Z42__device_stub__right_looking_launch_kernelPfiiii
.size _Z27right_looking_launch_kernelPfiiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "./dim2_256matrices.txt"
.size .L.str, 23
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "r"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%f"
.size .L.str.3, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%f "
.size .L.str.6, 4
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Failed to allocate device vector A (error code %s)!\n"
.size .L.str.8, 53
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Failed to copy vector A from host to device (error code %s)!\n"
.size .L.str.9, 62
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "kernel launch failed with error \"%s\".\n"
.size .L.str.11, 39
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Failed to copy vector A from device to host (error code %s)!\n"
.size .L.str.12, 62
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "\nFailed to free device matrix M (error code %s)\n"
.size .L.str.15, 49
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "Failed to deinitialize the CUDA device (error code %s)\n"
.size .L.str.16, 56
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "./output.txt"
.size .L.str.17, 13
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "w+"
.size .L.str.18, 3
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "%d\n"
.size .L.str.19, 4
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "%0.2f "
.size .L.str.20, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z27right_looking_launch_kernelPfiiii"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nRead from the input file successfully!"
.size .Lstr, 40
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\nPrinting the host-side input array read from the input file:"
.size .Lstr.1, 62
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\n"
.size .Lstr.2, 2
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Copied the h_A to device side successfully!\n"
.size .Lstr.3, 45
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "\nCopied d_A to host side successfully!"
.size .Lstr.4, 39
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "\nPrinting the output of cudememcopyDeviceToHost, i.e. the host-side array returned from device side:"
.size .Lstr.5, 101
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "\n\nAll tasks completed successfully!\n"
.size .Lstr.6, 37
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z42__device_stub__right_looking_launch_kernelPfiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z27right_looking_launch_kernelPfiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // All done in the .cpp file | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // All done in the .cpp file | .file "tmpxft_000dd89d_00000000-6_volumeBoundary.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // All done in the .cpp file | #include <hip/hip_runtime.h>
// All done in the .cpp file |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
// All done in the .cpp file | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
// All done in the .cpp file | .text
.file "volumeBoundary.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000dd89d_00000000-6_volumeBoundary.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "volumeBoundary.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda.h"
#include "cuda_runtime.h"
#include "string.h"
#include "stdio.h"
#include "stdlib.h"
#include <chrono>
#include <iostream>
#include <iomanip>
using namespace std;
#define CUDA_DEBUG { \
cudaError_t err = cudaGetLastError(); \
if (err != cudaSuccess){ \
printf("Error at %s %s: %s\n", __LINE__, __FILE__, cudaGetErrorString(err)); \
exit(1); \
} \
}
__global__ void gpu_mat_mul(float* A, float* B, float* C, long width, long N)
{
const long i = (blockIdx.x * blockDim.x + threadIdx.x);
if(i >= N) return;
float val = 0.0;
float* a = A + (i / width);
float* b = B + (i % width);
for(long j = 0; j < width; j++){
val += *(a + j) * *(b + (width*j));
}
*(C + i) = val;
}
int main(int argc, char **argv){
auto begin = chrono::high_resolution_clock::now();
if(argc < 2){
printf("usage: ./%s <size> \n", argv[0]);
return 1;
}
long size = atol(argv[1]);
long N = size*size;
size_t bytes = sizeof(float) * N;
float* A_h = (float*)malloc(bytes);
float* B_h = (float*)malloc(bytes);
float* C_h = (float*)malloc(bytes);
for(long i = 0; i < N; i++){
*(A_h + i) = (float)i / (float)N;
*(B_h + i) = (float)i / (float)N;
}
float *A_d, *B_d, *C_d;
cudaMalloc((void**)&A_d, bytes);
cudaMalloc((void**)&B_d, bytes);
cudaMalloc((void**)&C_d, bytes);
CUDA_DEBUG
cudaMemcpy(A_d, A_h, bytes, cudaMemcpyHostToDevice);
cudaMemcpy(B_d, B_h, bytes, cudaMemcpyHostToDevice);
cudaDeviceSynchronize();
CUDA_DEBUG
free(A_h);
free(B_h);
long threadsPerBlock = 1024;
long numBlocks = N / threadsPerBlock;
numBlocks += (N % threadsPerBlock > 0) ? 1 : 0;
gpu_mat_mul <<< numBlocks, threadsPerBlock >>> (A_d, B_d, C_d, size, N);
cudaDeviceSynchronize();
CUDA_DEBUG
cudaMemcpy(C_h, C_d, bytes, cudaMemcpyDeviceToHost);
cudaFree(C_d);
cudaFree(B_d);
cudaFree(A_d);
CUDA_DEBUG
free(C_h);
auto end = chrono::high_resolution_clock::now();
auto duration = chrono::duration_cast<chrono::milliseconds>(end - begin);
cout << "Blocksize * Gridsize: " << setw(2) << threadsPerBlock * numBlocks << " Matrix size: " << setw(9) << size;
cout << " Milliseconds taken: " << setw(15) << duration.count() << endl;
return 0;
} | code for sm_80
Function : _Z11gpu_mat_mulPfS_S_ll
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R5 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0205 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x180], PT ; /* 0x0000600004007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.AND.EX P0, PT, RZ, c[0x0][0x184], PT, P0 ; /* 0x00006100ff007a0c */
/* 0x000fda0003f06300 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fda0003f05070 */
/*0080*/ @!P0 BRA 0x160 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0090*/ MOV R0, 0xb0 ; /* 0x000000b000007802 */
/* 0x000fe40000000f00 */
/*00a0*/ CALL.REL.NOINC 0x8d0 ; /* 0x0000082000007944 */
/* 0x000fea0003c00000 */
/*00b0*/ IADD3 R19, P0, RZ, -R6, RZ ; /* 0x80000006ff137210 */
/* 0x000fe20007f1e0ff */
/*00c0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fc800078e00ff */
/*00d0*/ IMAD.X R0, RZ, RZ, ~R7, P0 ; /* 0x000000ffff007224 */
/* 0x000fe400000e0e07 */
/*00e0*/ IMAD.WIDE.U32 R2, R19, c[0x0][0x178], R4 ; /* 0x00005e0013027a25 */
/* 0x000fc800078e0004 */
/*00f0*/ IMAD R0, R0, c[0x0][0x178], RZ ; /* 0x00005e0000007a24 */
/* 0x000fc800078e02ff */
/*0100*/ IMAD R19, R19, c[0x0][0x17c], R0 ; /* 0x00005f0013137a24 */
/* 0x000fe400078e0200 */
/*0110*/ IMAD.MOV.U32 R0, RZ, RZ, R2 ; /* 0x000000ffff007224 */
/* 0x000fe400078e0002 */
/*0120*/ IMAD.IADD R19, R3, 0x1, R19 ; /* 0x0000000103137824 */
/* 0x000fe200078e0213 */
/*0130*/ MOV R3, R7 ; /* 0x0000000700037202 */
/* 0x000fe20000000f00 */
/*0140*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0006 */
/*0150*/ BRA 0x2c0 ; /* 0x0000016000007947 */
/* 0x000fea0003800000 */
/*0160*/ I2F.U32.RP R0, c[0x0][0x178] ; /* 0x00005e0000007b06 */
/* 0x000e220000209000 */
/*0170*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe20003f45070 */
/*0180*/ IMAD.MOV.U32 R19, RZ, RZ, RZ ; /* 0x000000ffff137224 */
/* 0x000fcc00078e00ff */
/*0190*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*01a0*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fcc0007ffe0ff */
/*01b0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*01c0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*01d0*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a03 */
/*01e0*/ IMAD R7, R7, c[0x0][0x178], RZ ; /* 0x00005e0007077a24 */
/* 0x000fc800078e02ff */
/*01f0*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*0200*/ IMAD.HI.U32 R2, R3, R4, RZ ; /* 0x0000000403027227 */
/* 0x000fc800078e00ff */
/*0210*/ IMAD.MOV R3, RZ, RZ, -R2 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a02 */
/*0220*/ IMAD R3, R3, c[0x0][0x178], R4 ; /* 0x00005e0003037a24 */
/* 0x000fca00078e0204 */
/*0230*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fda0003f06070 */
/*0240*/ @P0 IADD3 R3, R3, -c[0x0][0x178], RZ ; /* 0x80005e0003030a10 */
/* 0x000fe40007ffe0ff */
/*0250*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fe40007ffe0ff */
/*0260*/ ISETP.GE.U32.AND P1, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fda0003f26070 */
/*0270*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*0280*/ @!P2 LOP3.LUT R2, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff02aa12 */
/* 0x000fca00078e33ff */
/*0290*/ IMAD.MOV R3, RZ, RZ, -R2 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a02 */
/*02a0*/ IMAD R0, R3, c[0x0][0x178], R4 ; /* 0x00005e0003007a24 */
/* 0x000fe200078e0204 */
/*02b0*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe400000001ff */
/*02c0*/ IMAD.MOV.U32 R18, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff127624 */
/* 0x000fe200078e00ff */
/*02d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*02e0*/ IMAD.MOV.U32 R21, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff157624 */
/* 0x000fe400078e00ff */
/*02f0*/ IMAD.MOV.U32 R24, RZ, RZ, RZ ; /* 0x000000ffff187224 */
/* 0x000fe200078e00ff */
/*0300*/ ISETP.GE.U32.AND P0, PT, R18, 0x1, PT ; /* 0x000000011200780c */
/* 0x000fc80003f06070 */
/*0310*/ ISETP.GE.AND.EX P0, PT, R21, RZ, PT, P0 ; /* 0x000000ff1500720c */
/* 0x000fda0003f06300 */
/*0320*/ @!P0 BRA 0x890 ; /* 0x0000056000008947 */
/* 0x000fea0003800000 */
/*0330*/ IADD3 R6, P0, R18.reuse, -0x1, RZ ; /* 0xffffffff12067810 */
/* 0x040fe20007f1e0ff */
/*0340*/ CS2R R24, SRZ ; /* 0x0000000000187805 */
/* 0x000fe2000001ff00 */
/*0350*/ LOP3.LUT R20, R18, 0x3, RZ, 0xc0, !PT ; /* 0x0000000312147812 */
/* 0x000fe200078ec0ff */
/*0360*/ IMAD.MOV.U32 R23, RZ, RZ, RZ ; /* 0x000000ffff177224 */
/* 0x000fe200078e00ff */
/*0370*/ ISETP.GE.U32.AND P1, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe40003f26070 */
/*0380*/ IADD3.X R6, R21, -0x1, RZ, P0, !PT ; /* 0xffffffff15067810 */
/* 0x000fe400007fe4ff */
/*0390*/ ISETP.NE.U32.AND P0, PT, R20, RZ, PT ; /* 0x000000ff1400720c */
/* 0x000fe40003f05070 */
/*03a0*/ ISETP.GE.U32.AND.EX P1, PT, R6, RZ, PT, P1 ; /* 0x000000ff0600720c */
/* 0x000fc40003f26110 */
/*03b0*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fd60003f05300 */
/*03c0*/ @!P1 BRA 0x690 ; /* 0x000002c000009947 */
/* 0x000fea0003800000 */
/*03d0*/ LEA R8, P3, R2, c[0x0][0x160], 0x2 ; /* 0x0000580002087a11 */
/* 0x000fe200078610ff */
/*03e0*/ IMAD.SHL.U32 R27, R21, 0x4, RZ ; /* 0x00000004151b7824 */
/* 0x000fe200078e00ff */
/*03f0*/ IADD3 R22, P1, R20, -c[0x0][0x178], RZ ; /* 0x80005e0014167a10 */
/* 0x000fe20007f3e0ff */
/*0400*/ IMAD.WIDE.U32 R6, R18, 0x4, RZ ; /* 0x0000000412067825 */
/* 0x000fe200078e00ff */
/*0410*/ IADD3 R8, P4, R8, 0x8, RZ ; /* 0x0000000808087810 */
/* 0x000fe20007f9e0ff */
/*0420*/ CS2R R24, SRZ ; /* 0x0000000000187805 */
/* 0x000fe2000001ff00 */
/*0430*/ LEA.HI.X R9, R2, c[0x0][0x164], R3, 0x2, P3 ; /* 0x0000590002097a11 */
/* 0x000fe200018f1403 */
/*0440*/ IMAD.IADD R27, R7, 0x1, R27 ; /* 0x00000001071b7824 */
/* 0x000fe200078e021b */
/*0450*/ LEA R17, P2, R0.reuse, c[0x0][0x168], 0x2 ; /* 0x00005a0000117a11 */
/* 0x040fe200078410ff */
/*0460*/ IMAD.X R26, RZ, RZ, ~c[0x0][0x17c], P1 ; /* 0x80005f00ff1a7624 */
/* 0x000fe200008e06ff */
/*0470*/ MOV R23, RZ ; /* 0x000000ff00177202 */
/* 0x000fe20000000f00 */
/*0480*/ IMAD.X R9, RZ, RZ, R9, P4 ; /* 0x000000ffff097224 */
/* 0x000fe200020e0609 */
/*0490*/ LEA.HI.X R12, R0, c[0x0][0x16c], R19, 0x2, P2 ; /* 0x00005b00000c7a11 */
/* 0x000fca00010f1413 */
/*04a0*/ IMAD.MOV.U32 R15, RZ, RZ, R12 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e000c */
/*04b0*/ IMAD.MOV.U32 R14, RZ, RZ, R17 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0011 */
/*04c0*/ IADD3 R16, P1, R17, R6, RZ ; /* 0x0000000611107210 */
/* 0x000fe20007f3e0ff */
/*04d0*/ LDG.E R29, [R8.64+-0x4] ; /* 0xfffffc04081d7981 */
/* 0x000ea8000c1e1900 */
/*04e0*/ LDG.E R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x0000e8000c1e1900 */
/*04f0*/ LDG.E R14, [R8.64+-0x8] ; /* 0xfffff804080e7981 */
/* 0x001ee2000c1e1900 */
/*0500*/ IADD3.X R17, R12, R27, RZ, P1, !PT ; /* 0x0000001b0c117210 */
/* 0x000fc40000ffe4ff */
/*0510*/ IADD3 R10, P1, R16, R6, RZ ; /* 0x00000006100a7210 */
/* 0x000fc60007f3e0ff */
/*0520*/ LDG.E R28, [R16.64] ; /* 0x00000004101c7981 */
/* 0x0000a4000c1e1900 */
/*0530*/ IMAD.X R11, R17, 0x1, R27, P1 ; /* 0x00000001110b7824 */
/* 0x000fe200008e061b */
/*0540*/ IADD3 R12, P1, R10, R6, RZ ; /* 0x000000060a0c7210 */
/* 0x000fc80007f3e0ff */
/*0550*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000322000c1e1900 */
/*0560*/ IMAD.X R13, R11, 0x1, R27, P1 ; /* 0x000000010b0d7824 */
/* 0x000fc600008e061b */
/*0570*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x002322000c1e1900 */
/*0580*/ IADD3 R23, P1, R23, 0x4, RZ ; /* 0x0000000417177810 */
/* 0x000fe20007f3e0ff */
/*0590*/ FFMA R14, R15, R14, R24 ; /* 0x0000000e0f0e7223 */
/* 0x008fe40000000018 */
/*05a0*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000768000c1e1900 */
/*05b0*/ LDG.E R24, [R8.64+0x4] ; /* 0x0000040408187981 */
/* 0x000362000c1e1900 */
/*05c0*/ IADD3 R16, P2, R23, R22, RZ ; /* 0x0000001617107210 */
/* 0x001fe20007f5e0ff */
/*05d0*/ IMAD.X R25, RZ, RZ, R25, P1 ; /* 0x000000ffff197224 */
/* 0x000fc600008e0619 */
/*05e0*/ ISETP.NE.U32.AND P1, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe20003f25070 */
/*05f0*/ IMAD.X R16, R25, 0x1, R26, P2 ; /* 0x0000000119107824 */
/* 0x000fca00010e061a */
/*0600*/ ISETP.NE.AND.EX P1, PT, R16, RZ, PT, P1 ; /* 0x000000ff1000720c */
/* 0x000fe20003f25310 */
/*0610*/ FFMA R14, R28, R29, R14 ; /* 0x0000001d1c0e7223 */
/* 0x004fe2000000000e */
/*0620*/ IADD3 R8, P3, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x002fe40007f7e0ff */
/*0630*/ IADD3 R17, P2, R12, R6, RZ ; /* 0x000000060c117210 */
/* 0x000fe20007f5e0ff */
/*0640*/ FFMA R10, R10, R11, R14 ; /* 0x0000000b0a0a7223 */
/* 0x010fe4000000000e */
/*0650*/ IMAD.X R9, RZ, RZ, R9, P3 ; /* 0x000000ffff097224 */
/* 0x000fe200018e0609 */
/*0660*/ IADD3.X R12, R13, R27, RZ, P2, !PT ; /* 0x0000001b0d0c7210 */
/* 0x008fe200017fe4ff */
/*0670*/ FFMA R24, R15, R24, R10 ; /* 0x000000180f187223 */
/* 0x020fc8000000000a */
/*0680*/ @P1 BRA 0x4a0 ; /* 0xfffffe1000001947 */
/* 0x000fea000383ffff */
/*0690*/ @!P0 BRA 0x890 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*06a0*/ IMAD.MOV.U32 R6, RZ, RZ, R0 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0000 */
/*06b0*/ IADD3 R10, P0, R2, R23, RZ ; /* 0x00000017020a7210 */
/* 0x000fe20007f1e0ff */
/*06c0*/ IMAD.MOV.U32 R7, RZ, RZ, R19 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0013 */
/*06d0*/ IADD3 R20, P2, RZ, -R20, RZ ; /* 0x80000014ff147210 */
/* 0x000fe20007f5e0ff */
/*06e0*/ IMAD R8, R25, c[0x0][0x178], RZ ; /* 0x00005e0019087a24 */
/* 0x000fe200078e02ff */
/*06f0*/ LEA R9, P1, R10, c[0x0][0x160], 0x2 ; /* 0x000058000a097a11 */
/* 0x000fe200078210ff */
/*0700*/ IMAD.WIDE.U32 R6, R23, c[0x0][0x178], R6 ; /* 0x00005e0017067a25 */
/* 0x000fe200078e0006 */
/*0710*/ SHF.L.U64.HI R21, R18, 0x2, R21 ; /* 0x0000000212157819 */
/* 0x000fc60000010215 */
/*0720*/ IMAD R23, R23, c[0x0][0x17c], R8 ; /* 0x00005f0017177a24 */
/* 0x000fe400078e0208 */
/*0730*/ IMAD.X R3, R3, 0x1, R25, P0 ; /* 0x0000000103037824 */
/* 0x000fe200000e0619 */
/*0740*/ LEA R11, P0, R6, c[0x0][0x168], 0x2 ; /* 0x00005a00060b7a11 */
/* 0x000fe200078010ff */
/*0750*/ IMAD.IADD R7, R7, 0x1, R23 ; /* 0x0000000107077824 */
/* 0x000fe400078e0217 */
/*0760*/ IMAD.X R8, RZ, RZ, -0x1, P2 ; /* 0xffffffffff087424 */
/* 0x000fe200010e06ff */
/*0770*/ LEA.HI.X R10, R10, c[0x0][0x164], R3, 0x2, P1 ; /* 0x000059000a0a7a11 */
/* 0x000fe400008f1403 */
/*0780*/ LEA.HI.X R12, R6, c[0x0][0x16c], R7, 0x2, P0 ; /* 0x00005b00060c7a11 */
/* 0x000fca00000f1407 */
/*0790*/ IMAD.MOV.U32 R3, RZ, RZ, R12 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000c */
/*07a0*/ MOV R2, R11 ; /* 0x0000000b00027202 */
/* 0x000fe20000000f00 */
/*07b0*/ IMAD.MOV.U32 R6, RZ, RZ, R9 ; /* 0x000000ffff067224 */
/* 0x000fc400078e0009 */
/*07c0*/ IMAD.MOV.U32 R7, RZ, RZ, R10 ; /* 0x000000ffff077224 */
/* 0x000fe400078e000a */
/*07d0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*07e0*/ LDG.E R0, [R6.64] ; /* 0x0000000406007981 */
/* 0x000ea2000c1e1900 */
/*07f0*/ IADD3 R20, P0, R20, 0x1, RZ ; /* 0x0000000114147810 */
/* 0x000fe40007f1e0ff */
/*0800*/ LEA R11, P1, R18, R11, 0x2 ; /* 0x0000000b120b7211 */
/* 0x000fe400078210ff */
/*0810*/ IADD3 R9, P2, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe20007f5e0ff */
/*0820*/ IMAD.X R8, RZ, RZ, R8, P0 ; /* 0x000000ffff087224 */
/* 0x000fe200000e0608 */
/*0830*/ ISETP.NE.U32.AND P0, PT, R20, RZ, PT ; /* 0x000000ff1400720c */
/* 0x000fe20003f05070 */
/*0840*/ IMAD.X R12, R12, 0x1, R21, P1 ; /* 0x000000010c0c7824 */
/* 0x000fe200008e0615 */
/*0850*/ IADD3.X R10, RZ, R10, RZ, P2, !PT ; /* 0x0000000aff0a7210 */
/* 0x000fc400017fe4ff */
/*0860*/ ISETP.NE.AND.EX P0, PT, R8, RZ, PT, P0 ; /* 0x000000ff0800720c */
/* 0x000fe20003f05300 */
/*0870*/ FFMA R24, R3, R0, R24 ; /* 0x0000000003187223 */
/* 0x004fd80000000018 */
/*0880*/ @P0 BRA 0x790 ; /* 0xffffff0000000947 */
/* 0x000fea000383ffff */
/*0890*/ LEA R2, P0, R4, c[0x0][0x170], 0x2 ; /* 0x00005c0004027a11 */
/* 0x000fc800078010ff */
/*08a0*/ LEA.HI.X R3, R4, c[0x0][0x174], RZ, 0x2, P0 ; /* 0x00005d0004037a11 */
/* 0x000fca00000f14ff */
/*08b0*/ STG.E [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x000fe2000c101904 */
/*08c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08d0*/ IADD3 R2, P0, RZ, -c[0x0][0x178], RZ ; /* 0x80005e00ff027a10 */
/* 0x000fe40007f1e0ff */
/*08e0*/ ISETP.LE.AND P1, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fc60003f23270 */
/*08f0*/ IMAD.X R3, RZ, RZ, ~c[0x0][0x17c], P0 ; /* 0x80005f00ff037624 */
/* 0x000fe200000e06ff */
/*0900*/ SEL R2, R2, c[0x0][0x178], !P1 ; /* 0x00005e0002027a07 */
/* 0x000fc80004800000 */
/*0910*/ SEL R3, R3, c[0x0][0x17c], !P1 ; /* 0x00005f0003037a07 */
/* 0x000fc80004800000 */
/*0920*/ I2F.U64.RP R10, R2 ; /* 0x00000002000a7312 */
/* 0x000e300000309000 */
/*0930*/ MUFU.RCP R10, R10 ; /* 0x0000000a000a7308 */
/* 0x001e240000001000 */
/*0940*/ IADD3 R6, R10, 0x1ffffffe, RZ ; /* 0x1ffffffe0a067810 */
/* 0x001fcc0007ffe0ff */
/*0950*/ F2I.U64.TRUNC R6, R6 ; /* 0x0000000600067311 */
/* 0x000e24000020d800 */
/*0960*/ IMAD.WIDE.U32 R8, R6, R2, RZ ; /* 0x0000000206087225 */
/* 0x001fc800078e00ff */
/*0970*/ IMAD R9, R6, R3, R9 ; /* 0x0000000306097224 */
/* 0x000fe200078e0209 */
/*0980*/ IADD3 R11, P0, RZ, -R8, RZ ; /* 0x80000008ff0b7210 */
/* 0x000fc60007f1e0ff */
/*0990*/ IMAD R9, R7, R2, R9 ; /* 0x0000000207097224 */
/* 0x000fe400078e0209 */
/*09a0*/ IMAD.HI.U32 R8, R6, R11, RZ ; /* 0x0000000b06087227 */
/* 0x000fc800078e00ff */
/*09b0*/ IMAD.X R13, RZ, RZ, ~R9, P0 ; /* 0x000000ffff0d7224 */
/* 0x000fe400000e0e09 */
/*09c0*/ IMAD.MOV.U32 R9, RZ, RZ, R6 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0006 */
/*09d0*/ IMAD R15, R7, R13.reuse, RZ ; /* 0x0000000d070f7224 */
/* 0x080fe400078e02ff */
/*09e0*/ IMAD.WIDE.U32 R8, P0, R6, R13, R8 ; /* 0x0000000d06087225 */
/* 0x000fc80007800008 */
/*09f0*/ IMAD.HI.U32 R13, R7, R13, RZ ; /* 0x0000000d070d7227 */
/* 0x000fc800078e00ff */
/*0a00*/ IMAD.HI.U32 R8, P2, R7, R11, R8 ; /* 0x0000000b07087227 */
/* 0x000fca0007840008 */
/*0a10*/ IADD3 R9, P3, R15, R8, RZ ; /* 0x000000080f097210 */
/* 0x000fe20007f7e0ff */
/*0a20*/ IMAD.X R8, R13, 0x1, R7, P0 ; /* 0x000000010d087824 */
/* 0x000fc800000e0607 */
/*0a30*/ IMAD.WIDE.U32 R6, R9, R2, RZ ; /* 0x0000000209067225 */
/* 0x000fe200078e00ff */
/*0a40*/ IADD3.X R11, RZ, RZ, R8, P3, P2 ; /* 0x000000ffff0b7210 */
/* 0x000fc60001fe4408 */
/*0a50*/ IMAD R7, R9, R3, R7 ; /* 0x0000000309077224 */
/* 0x000fe200078e0207 */
/*0a60*/ IADD3 R13, P0, RZ, -R6, RZ ; /* 0x80000006ff0d7210 */
/* 0x000fc60007f1e0ff */
/*0a70*/ IMAD R7, R11, R2, R7 ; /* 0x000000020b077224 */
/* 0x000fe400078e0207 */
/*0a80*/ IMAD.HI.U32 R8, R9, R13, RZ ; /* 0x0000000d09087227 */
/* 0x000fc800078e00ff */
/*0a90*/ IMAD.X R6, RZ, RZ, ~R7, P0 ; /* 0x000000ffff067224 */
/* 0x000fe400000e0e07 */
/*0aa0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe400078e00ff */
/*0ab0*/ IMAD.WIDE.U32 R8, P0, R9, R6, R8 ; /* 0x0000000609087225 */
/* 0x000fc80007800008 */
/*0ac0*/ IMAD R10, R11.reuse, R6, RZ ; /* 0x000000060b0a7224 */
/* 0x040fe400078e02ff */
/*0ad0*/ IMAD.HI.U32 R9, P2, R11, R13, R8 ; /* 0x0000000d0b097227 */
/* 0x000fc80007840008 */
/*0ae0*/ IMAD.HI.U32 R8, R11, R6, RZ ; /* 0x000000060b087227 */
/* 0x000fe200078e00ff */
/*0af0*/ IADD3 R9, P3, R10, R9, RZ ; /* 0x000000090a097210 */
/* 0x000fc80007f7e0ff */
/*0b00*/ IADD3.X R11, R8, R11, RZ, P0, !PT ; /* 0x0000000b080b7210 */
/* 0x000fe200007fe4ff */
/*0b10*/ IMAD.HI.U32 R6, R9, R4, RZ ; /* 0x0000000409067227 */
/* 0x000fc600078e00ff */
/*0b20*/ IADD3.X R11, RZ, RZ, R11, P3, P2 ; /* 0x000000ffff0b7210 */
/* 0x000fc60001fe440b */
/*0b30*/ IMAD.WIDE.U32 R6, RZ, R9, R6 ; /* 0x00000009ff067225 */
/* 0x000fcc00078e0006 */
/*0b40*/ IMAD.HI.U32 R6, P0, R11, R4, R6 ; /* 0x000000040b067227 */
/* 0x000fc80007800006 */
/*0b50*/ IMAD.X R8, RZ, RZ, RZ, P0 ; /* 0x000000ffff087224 */
/* 0x000fe200000e06ff */
/*0b60*/ IADD3 R9, P2, RZ, R6, RZ ; /* 0x00000006ff097210 */
/* 0x000fca0007f5e0ff */
/*0b70*/ IMAD.WIDE.U32 R6, R9, R2, RZ ; /* 0x0000000209067225 */
/* 0x000fc800078e00ff */
/*0b80*/ IMAD.X R11, RZ, RZ, R8, P2 ; /* 0x000000ffff0b7224 */
/* 0x000fe200010e0608 */
/*0b90*/ IADD3 R15, P2, -R6, R4, RZ ; /* 0x00000004060f7210 */
/* 0x000fe20007f5e1ff */
/*0ba0*/ IMAD R7, R9.reuse, R3, R7 ; /* 0x0000000309077224 */
/* 0x040fe200078e0207 */
/*0bb0*/ IADD3 R6, P3, R9, 0x1, RZ ; /* 0x0000000109067810 */
/* 0x000fe40007f7e0ff */
/*0bc0*/ ISETP.GE.U32.AND P0, PT, R15, R2.reuse, PT ; /* 0x000000020f00720c */
/* 0x080fe20003f06070 */
/*0bd0*/ IMAD R7, R11, R2, R7 ; /* 0x000000020b077224 */
/* 0x000fe200078e0207 */
/*0be0*/ IADD3.X R8, RZ, R11, RZ, P3, !PT ; /* 0x0000000bff087210 */
/* 0x000fc60001ffe4ff */
/*0bf0*/ IMAD.X R17, RZ, RZ, ~R7, P2 ; /* 0x000000ffff117224 */
/* 0x000fe200010e0e07 */
/*0c00*/ IADD3 R7, P2, R15, -R2, RZ ; /* 0x800000020f077210 */
/* 0x000fc80007f5e0ff */
/*0c10*/ ISETP.GE.U32.AND.EX P0, PT, R17.reuse, R3, PT, P0 ; /* 0x000000031100720c */
/* 0x040fe20003f06100 */
/*0c20*/ IMAD.X R13, R17, 0x1, ~R3, P2 ; /* 0x00000001110d7824 */
/* 0x000fc600010e0e03 */
/*0c30*/ SEL R7, R7, R15, P0 ; /* 0x0000000f07077207 */
/* 0x000fe40000000000 */
/*0c40*/ SEL R9, R6, R9, P0 ; /* 0x0000000906097207 */
/* 0x000fe40000000000 */
/*0c50*/ SEL R13, R13, R17, P0 ; /* 0x000000110d0d7207 */
/* 0x000fe40000000000 */
/*0c60*/ ISETP.GE.U32.AND P2, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x000fe40003f46070 */
/*0c70*/ SEL R2, R8, R11, P0 ; /* 0x0000000b08027207 */
/* 0x000fe40000000000 */
/*0c80*/ IADD3 R6, P3, R9, 0x1, RZ ; /* 0x0000000109067810 */
/* 0x000fc40007f7e0ff */
/*0c90*/ ISETP.GE.U32.AND.EX P0, PT, R13, R3, PT, P2 ; /* 0x000000030d00720c */
/* 0x000fc60003f06120 */
/*0ca0*/ IMAD.X R7, RZ, RZ, R2, P3 ; /* 0x000000ffff077224 */
/* 0x000fe200018e0602 */
/*0cb0*/ SEL R6, R6, R9, P0 ; /* 0x0000000906067207 */
/* 0x000fc80000000000 */
/*0cc0*/ SEL R7, R7, R2, P0 ; /* 0x0000000207077207 */
/* 0x000fe40000000000 */
/*0cd0*/ IADD3 R3, P2, RZ, -R6.reuse, RZ ; /* 0x80000006ff037210 */
/* 0x080fe40007f5e0ff */
/*0ce0*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe40003f05070 */
/*0cf0*/ SEL R6, R3, R6, !P1 ; /* 0x0000000603067207 */
/* 0x000fe20004800000 */
/*0d00*/ IMAD.X R2, RZ, RZ, ~R7, P2 ; /* 0x000000ffff027224 */
/* 0x000fe200010e0e07 */
/*0d10*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x17c], PT, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fe20003f05300 */
/*0d20*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc600078e00ff */
/*0d30*/ SEL R7, R2, R7, !P1 ; /* 0x0000000702077207 */
/* 0x000fe20004800000 */
/*0d40*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0000 */
/*0d50*/ SEL R6, R6, 0xffffffff, P0 ; /* 0xffffffff06067807 */
/* 0x000fe40000000000 */
/*0d60*/ SEL R7, R7, 0xffffffff, P0 ; /* 0xffffffff07077807 */
/* 0x000fe20000000000 */
/*0d70*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff28002007950 */
/* 0x000fec0003c3ffff */
/*0d80*/ BRA 0xd80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda.h"
#include "cuda_runtime.h"
#include "string.h"
#include "stdio.h"
#include "stdlib.h"
#include <chrono>
#include <iostream>
#include <iomanip>
using namespace std;
#define CUDA_DEBUG { \
cudaError_t err = cudaGetLastError(); \
if (err != cudaSuccess){ \
printf("Error at %s %s: %s\n", __LINE__, __FILE__, cudaGetErrorString(err)); \
exit(1); \
} \
}
__global__ void gpu_mat_mul(float* A, float* B, float* C, long width, long N)
{
const long i = (blockIdx.x * blockDim.x + threadIdx.x);
if(i >= N) return;
float val = 0.0;
float* a = A + (i / width);
float* b = B + (i % width);
for(long j = 0; j < width; j++){
val += *(a + j) * *(b + (width*j));
}
*(C + i) = val;
}
int main(int argc, char **argv){
auto begin = chrono::high_resolution_clock::now();
if(argc < 2){
printf("usage: ./%s <size> \n", argv[0]);
return 1;
}
long size = atol(argv[1]);
long N = size*size;
size_t bytes = sizeof(float) * N;
float* A_h = (float*)malloc(bytes);
float* B_h = (float*)malloc(bytes);
float* C_h = (float*)malloc(bytes);
for(long i = 0; i < N; i++){
*(A_h + i) = (float)i / (float)N;
*(B_h + i) = (float)i / (float)N;
}
float *A_d, *B_d, *C_d;
cudaMalloc((void**)&A_d, bytes);
cudaMalloc((void**)&B_d, bytes);
cudaMalloc((void**)&C_d, bytes);
CUDA_DEBUG
cudaMemcpy(A_d, A_h, bytes, cudaMemcpyHostToDevice);
cudaMemcpy(B_d, B_h, bytes, cudaMemcpyHostToDevice);
cudaDeviceSynchronize();
CUDA_DEBUG
free(A_h);
free(B_h);
long threadsPerBlock = 1024;
long numBlocks = N / threadsPerBlock;
numBlocks += (N % threadsPerBlock > 0) ? 1 : 0;
gpu_mat_mul <<< numBlocks, threadsPerBlock >>> (A_d, B_d, C_d, size, N);
cudaDeviceSynchronize();
CUDA_DEBUG
cudaMemcpy(C_h, C_d, bytes, cudaMemcpyDeviceToHost);
cudaFree(C_d);
cudaFree(B_d);
cudaFree(A_d);
CUDA_DEBUG
free(C_h);
auto end = chrono::high_resolution_clock::now();
auto duration = chrono::duration_cast<chrono::milliseconds>(end - begin);
cout << "Blocksize * Gridsize: " << setw(2) << threadsPerBlock * numBlocks << " Matrix size: " << setw(9) << size;
cout << " Milliseconds taken: " << setw(15) << duration.count() << endl;
return 0;
} | .file "tmpxft_00132069_00000000-6_p6.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4054:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z11gpu_mat_mulPfS_S_llPfS_S_ll
.type _Z37__device_stub__Z11gpu_mat_mulPfS_S_llPfS_S_ll, @function
_Z37__device_stub__Z11gpu_mat_mulPfS_S_llPfS_S_ll:
.LFB4076:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11gpu_mat_mulPfS_S_ll(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4076:
.size _Z37__device_stub__Z11gpu_mat_mulPfS_S_llPfS_S_ll, .-_Z37__device_stub__Z11gpu_mat_mulPfS_S_llPfS_S_ll
.globl _Z11gpu_mat_mulPfS_S_ll
.type _Z11gpu_mat_mulPfS_S_ll, @function
_Z11gpu_mat_mulPfS_S_ll:
.LFB4077:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z11gpu_mat_mulPfS_S_llPfS_S_ll
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4077:
.size _Z11gpu_mat_mulPfS_S_ll, .-_Z11gpu_mat_mulPfS_S_ll
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "usage: ./%s <size> \n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/orb1t-ua/parallel/master/prog6/p6.cu"
.section .rodata.str1.1
.LC2:
.string "Error at %s %s: %s\n"
.LC3:
.string "Blocksize * Gridsize: "
.LC4:
.string " Matrix size: "
.LC5:
.string " Milliseconds taken: "
.text
.globl main
.type main, @function
main:
.LFB4048:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movl %edi, %ebp
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, 8(%rsp)
cmpl $1, %ebp
jle .L24
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r14
movq %rax, %rbx
imulq %rax, %rbx
leaq 0(,%rbx,4), %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %r12
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r13, %rdi
call malloc@PLT
movq %rax, %r15
testq %rbx, %rbx
jle .L14
movl $0, %eax
pxor %xmm1, %xmm1
cvtsi2ssq %rbx, %xmm1
.L15:
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss %xmm1, %xmm0
movss %xmm0, (%r12,%rax,4)
movss %xmm0, 0(%rbp,%rax,4)
addq $1, %rax
cmpq %rax, %rbx
jne .L15
.L14:
leaq 24(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L25
movl $1, %ecx
movq %r13, %rdx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L26
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
leaq 1023(%rbx), %rbp
testq %rbx, %rbx
cmovns %rbx, %rbp
sarq $10, %rbp
movq %rbx, %rax
andl $1023, %eax
cmpq $1, %rax
sbbq $-1, %rbp
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl %ebp, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L18:
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L28
movl $2, %ecx
movq %r13, %rdx
movq 40(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L29
movq %r15, %rdi
call free@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq 8(%rsp), %rcx
subq %rcx, %rax
movq %rax, %rcx
movabsq $4835703278458516699, %rdx
imulq %rdx
sarq $18, %rdx
sarq $63, %rcx
subq %rcx, %rdx
movq %rdx, %rbx
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %r12
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq (%rax), %rax
movq -24(%rax), %rax
movq $2, 16(%rdi,%rax)
movq %rbp, %rsi
salq $10, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq (%rax), %rax
movq -24(%rax), %rax
movq $9, 16(%rdi,%rax)
movq %r14, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
leaq .LC5(%rip), %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq (%rax), %rax
movq -24(%rax), %rax
movq $15, 16(%rdi,%rax)
movq %rbx, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %eax
.L11:
movq 72(%rsp), %rdx
subq %fs:40, %rdx
jne .L30
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movq (%rbx), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L11
.L25:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
leaq .LC1(%rip), %rcx
movl $58, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L26:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
leaq .LC1(%rip), %rcx
movl $65, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L27:
movq %rbx, %r8
movq %r14, %rcx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z37__device_stub__Z11gpu_mat_mulPfS_S_llPfS_S_ll
jmp .L18
.L28:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
leaq .LC1(%rip), %rcx
movl $77, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L29:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
leaq .LC1(%rip), %rcx
movl $85, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4048:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z11gpu_mat_mulPfS_S_ll"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4079:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z11gpu_mat_mulPfS_S_ll(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4079:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda.h"
#include "cuda_runtime.h"
#include "string.h"
#include "stdio.h"
#include "stdlib.h"
#include <chrono>
#include <iostream>
#include <iomanip>
using namespace std;
#define CUDA_DEBUG { \
cudaError_t err = cudaGetLastError(); \
if (err != cudaSuccess){ \
printf("Error at %s %s: %s\n", __LINE__, __FILE__, cudaGetErrorString(err)); \
exit(1); \
} \
}
__global__ void gpu_mat_mul(float* A, float* B, float* C, long width, long N)
{
const long i = (blockIdx.x * blockDim.x + threadIdx.x);
if(i >= N) return;
float val = 0.0;
float* a = A + (i / width);
float* b = B + (i % width);
for(long j = 0; j < width; j++){
val += *(a + j) * *(b + (width*j));
}
*(C + i) = val;
}
int main(int argc, char **argv){
auto begin = chrono::high_resolution_clock::now();
if(argc < 2){
printf("usage: ./%s <size> \n", argv[0]);
return 1;
}
long size = atol(argv[1]);
long N = size*size;
size_t bytes = sizeof(float) * N;
float* A_h = (float*)malloc(bytes);
float* B_h = (float*)malloc(bytes);
float* C_h = (float*)malloc(bytes);
for(long i = 0; i < N; i++){
*(A_h + i) = (float)i / (float)N;
*(B_h + i) = (float)i / (float)N;
}
float *A_d, *B_d, *C_d;
cudaMalloc((void**)&A_d, bytes);
cudaMalloc((void**)&B_d, bytes);
cudaMalloc((void**)&C_d, bytes);
CUDA_DEBUG
cudaMemcpy(A_d, A_h, bytes, cudaMemcpyHostToDevice);
cudaMemcpy(B_d, B_h, bytes, cudaMemcpyHostToDevice);
cudaDeviceSynchronize();
CUDA_DEBUG
free(A_h);
free(B_h);
long threadsPerBlock = 1024;
long numBlocks = N / threadsPerBlock;
numBlocks += (N % threadsPerBlock > 0) ? 1 : 0;
gpu_mat_mul <<< numBlocks, threadsPerBlock >>> (A_d, B_d, C_d, size, N);
cudaDeviceSynchronize();
CUDA_DEBUG
cudaMemcpy(C_h, C_d, bytes, cudaMemcpyDeviceToHost);
cudaFree(C_d);
cudaFree(B_d);
cudaFree(A_d);
CUDA_DEBUG
free(C_h);
auto end = chrono::high_resolution_clock::now();
auto duration = chrono::duration_cast<chrono::milliseconds>(end - begin);
cout << "Blocksize * Gridsize: " << setw(2) << threadsPerBlock * numBlocks << " Matrix size: " << setw(9) << size;
cout << " Milliseconds taken: " << setw(15) << duration.count() << endl;
return 0;
} | #include "hip/hip_runtime.h"
#include "string.h"
#include "stdio.h"
#include "stdlib.h"
#include <chrono>
#include <iostream>
#include <iomanip>
using namespace std;
#define CUDA_DEBUG { \
hipError_t err = hipGetLastError(); \
if (err != hipSuccess){ \
printf("Error at %s %s: %s\n", __LINE__, __FILE__, hipGetErrorString(err)); \
exit(1); \
} \
}
__global__ void gpu_mat_mul(float* A, float* B, float* C, long width, long N)
{
const long i = (blockIdx.x * blockDim.x + threadIdx.x);
if(i >= N) return;
float val = 0.0;
float* a = A + (i / width);
float* b = B + (i % width);
for(long j = 0; j < width; j++){
val += *(a + j) * *(b + (width*j));
}
*(C + i) = val;
}
int main(int argc, char **argv){
auto begin = chrono::high_resolution_clock::now();
if(argc < 2){
printf("usage: ./%s <size> \n", argv[0]);
return 1;
}
long size = atol(argv[1]);
long N = size*size;
size_t bytes = sizeof(float) * N;
float* A_h = (float*)malloc(bytes);
float* B_h = (float*)malloc(bytes);
float* C_h = (float*)malloc(bytes);
for(long i = 0; i < N; i++){
*(A_h + i) = (float)i / (float)N;
*(B_h + i) = (float)i / (float)N;
}
float *A_d, *B_d, *C_d;
hipMalloc((void**)&A_d, bytes);
hipMalloc((void**)&B_d, bytes);
hipMalloc((void**)&C_d, bytes);
CUDA_DEBUG
hipMemcpy(A_d, A_h, bytes, hipMemcpyHostToDevice);
hipMemcpy(B_d, B_h, bytes, hipMemcpyHostToDevice);
hipDeviceSynchronize();
CUDA_DEBUG
free(A_h);
free(B_h);
long threadsPerBlock = 1024;
long numBlocks = N / threadsPerBlock;
numBlocks += (N % threadsPerBlock > 0) ? 1 : 0;
gpu_mat_mul <<< numBlocks, threadsPerBlock >>> (A_d, B_d, C_d, size, N);
hipDeviceSynchronize();
CUDA_DEBUG
hipMemcpy(C_h, C_d, bytes, hipMemcpyDeviceToHost);
hipFree(C_d);
hipFree(B_d);
hipFree(A_d);
CUDA_DEBUG
free(C_h);
auto end = chrono::high_resolution_clock::now();
auto duration = chrono::duration_cast<chrono::milliseconds>(end - begin);
cout << "Blocksize * Gridsize: " << setw(2) << threadsPerBlock * numBlocks << " Matrix size: " << setw(9) << size;
cout << " Milliseconds taken: " << setw(15) << duration.count() << endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include "string.h"
#include "stdio.h"
#include "stdlib.h"
#include <chrono>
#include <iostream>
#include <iomanip>
using namespace std;
#define CUDA_DEBUG { \
hipError_t err = hipGetLastError(); \
if (err != hipSuccess){ \
printf("Error at %s %s: %s\n", __LINE__, __FILE__, hipGetErrorString(err)); \
exit(1); \
} \
}
__global__ void gpu_mat_mul(float* A, float* B, float* C, long width, long N)
{
const long i = (blockIdx.x * blockDim.x + threadIdx.x);
if(i >= N) return;
float val = 0.0;
float* a = A + (i / width);
float* b = B + (i % width);
for(long j = 0; j < width; j++){
val += *(a + j) * *(b + (width*j));
}
*(C + i) = val;
}
int main(int argc, char **argv){
auto begin = chrono::high_resolution_clock::now();
if(argc < 2){
printf("usage: ./%s <size> \n", argv[0]);
return 1;
}
long size = atol(argv[1]);
long N = size*size;
size_t bytes = sizeof(float) * N;
float* A_h = (float*)malloc(bytes);
float* B_h = (float*)malloc(bytes);
float* C_h = (float*)malloc(bytes);
for(long i = 0; i < N; i++){
*(A_h + i) = (float)i / (float)N;
*(B_h + i) = (float)i / (float)N;
}
float *A_d, *B_d, *C_d;
hipMalloc((void**)&A_d, bytes);
hipMalloc((void**)&B_d, bytes);
hipMalloc((void**)&C_d, bytes);
CUDA_DEBUG
hipMemcpy(A_d, A_h, bytes, hipMemcpyHostToDevice);
hipMemcpy(B_d, B_h, bytes, hipMemcpyHostToDevice);
hipDeviceSynchronize();
CUDA_DEBUG
free(A_h);
free(B_h);
long threadsPerBlock = 1024;
long numBlocks = N / threadsPerBlock;
numBlocks += (N % threadsPerBlock > 0) ? 1 : 0;
gpu_mat_mul <<< numBlocks, threadsPerBlock >>> (A_d, B_d, C_d, size, N);
hipDeviceSynchronize();
CUDA_DEBUG
hipMemcpy(C_h, C_d, bytes, hipMemcpyDeviceToHost);
hipFree(C_d);
hipFree(B_d);
hipFree(A_d);
CUDA_DEBUG
free(C_h);
auto end = chrono::high_resolution_clock::now();
auto duration = chrono::duration_cast<chrono::milliseconds>(end - begin);
cout << "Blocksize * Gridsize: " << setw(2) << threadsPerBlock * numBlocks << " Matrix size: " << setw(9) << size;
cout << " Milliseconds taken: " << setw(15) << duration.count() << endl;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11gpu_mat_mulPfS_S_ll
.globl _Z11gpu_mat_mulPfS_S_ll
.p2align 8
.type _Z11gpu_mat_mulPfS_S_ll,@function
_Z11gpu_mat_mulPfS_S_ll:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_10
s_load_b64 s[4:5], s[0:1], 0x18
s_mov_b32 s6, 0
s_waitcnt lgkmcnt(0)
s_mov_b32 s7, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_7
s_ashr_i32 s8, s5, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_u32 s2, s4, s8
s_mov_b32 s9, s8
s_addc_u32 s3, s5, s8
s_xor_b64 s[10:11], s[2:3], s[8:9]
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v0, s10
v_cvt_f32_u32_e32 v3, s11
s_sub_u32 s2, 0, s10
s_subb_u32 s3, 0, s11
v_fmamk_f32 v0, v3, 0x4f800000, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x5f7ffffc, v0
v_mul_f32_e32 v3, 0x2f800000, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_trunc_f32_e32 v3, v3
v_fmamk_f32 v0, v3, 0xcf800000, v0
v_cvt_u32_f32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v4, s2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, s2, v0
v_mul_lo_u32 v6, s3, v0
v_add_nc_u32_e32 v4, v5, v4
v_mul_lo_u32 v5, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, v4, v6
v_mul_hi_u32 v6, v0, v5
s_delay_alu instid0(VALU_DEP_2)
v_mul_lo_u32 v7, v0, v4
v_mul_hi_u32 v8, v0, v4
v_mul_hi_u32 v9, v3, v5
v_mul_lo_u32 v5, v3, v5
v_mul_hi_u32 v10, v3, v4
v_mul_lo_u32 v4, v3, v4
v_add_co_u32 v6, vcc_lo, v6, v7
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, v6, v5
v_add_co_ci_u32_e32 v5, vcc_lo, v7, v9, vcc_lo
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v10, vcc_lo
v_ashrrev_i32_e32 v9, 31, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v5, v4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v4
v_add_co_ci_u32_e32 v3, vcc_lo, v3, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v4, s2, v0
v_mul_lo_u32 v6, s3, v0
v_mul_lo_u32 v5, s2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, v4, v5
v_mul_lo_u32 v5, s2, v0
v_add_nc_u32_e32 v4, v4, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v6, v0, v5
v_mul_lo_u32 v7, v0, v4
v_mul_hi_u32 v8, v0, v4
v_mul_hi_u32 v10, v3, v5
v_mul_lo_u32 v5, v3, v5
v_mul_hi_u32 v11, v3, v4
v_mul_lo_u32 v4, v3, v4
v_add_co_u32 v6, vcc_lo, v6, v7
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, v6, v5
v_add_co_ci_u32_e32 v5, vcc_lo, v7, v10, vcc_lo
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v11, vcc_lo
v_add_co_u32 v7, vcc_lo, v1, v9
v_add_co_ci_u32_e32 v8, vcc_lo, v2, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, v5, v4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v10, v7, v9
v_add_co_u32 v0, vcc_lo, v0, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v11, vcc_lo, v3, v5, vcc_lo
v_xor_b32_e32 v12, v8, v9
v_mul_hi_u32 v13, v10, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[3:4], null, v10, v11, 0
v_mad_u64_u32 v[5:6], null, v12, v0, 0
v_mad_u64_u32 v[7:8], null, v12, v11, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, v13, v3
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v5
v_add_co_ci_u32_e32 v0, vcc_lo, v3, v6, vcc_lo
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v7
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v6, s11, v0
v_mad_u64_u32 v[3:4], null, s10, v0, 0
v_mul_lo_u32 v7, s10, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v3, vcc_lo, v10, v3
v_add3_u32 v4, v4, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v6, v12, v4
v_subrev_co_ci_u32_e64 v6, s2, s11, v6, vcc_lo
v_add_co_u32 v7, s2, v0, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v8, s2, 0, v5, s2
v_sub_co_u32 v10, s2, v3, s10
v_sub_co_ci_u32_e32 v4, vcc_lo, v12, v4, vcc_lo
v_subrev_co_ci_u32_e64 v6, s2, 0, v6, s2
v_cmp_le_u32_e32 vcc_lo, s10, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cmp_eq_u32_e64 s2, s11, v4
v_cndmask_b32_e64 v10, 0, -1, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s11, v6
v_cndmask_b32_e64 v11, 0, -1, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s10, v3
v_cndmask_b32_e64 v3, 0, -1, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s11, v4
v_cndmask_b32_e64 v12, 0, -1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, s11, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v3, v12, v3, s2
v_cndmask_b32_e32 v6, v11, v10, vcc_lo
v_add_co_u32 v10, vcc_lo, v0, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v4, v11, v8, vcc_lo
v_cndmask_b32_e32 v6, v10, v7, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v3
v_xor_b32_e32 v3, s8, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v0, v0, v6, vcc_lo
v_cndmask_b32_e32 v4, v5, v4, vcc_lo
v_xor_b32_e32 v5, s8, v9
v_xor_b32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v4, v4, v5
v_sub_co_u32 v3, vcc_lo, v0, v3
s_delay_alu instid0(VALU_DEP_2)
v_sub_co_ci_u32_e32 v4, vcc_lo, v4, v5, vcc_lo
s_and_not1_b32 vcc_lo, exec_lo, s6
s_cbranch_vccnz .LBB0_4
.LBB0_3:
v_cvt_f32_u32_e32 v0, s4
s_sub_i32 s2, 0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, s2, v0
v_mul_hi_u32 v3, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v3
v_mul_hi_u32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v3, v0, s4
v_add_nc_u32_e32 v4, 1, v0
v_sub_nc_u32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s4, v3
v_cmp_le_u32_e32 vcc_lo, s4, v3
v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s4, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_1)
v_dual_cndmask_b32 v3, v0, v4 :: v_dual_mov_b32 v4, 0
.LBB0_4:
v_cmp_lt_i64_e64 s2, s[4:5], 1
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_8
s_delay_alu instid0(VALU_DEP_2)
v_mul_lo_u32 v0, v4, s4
v_mul_lo_u32 v7, v3, s5
v_mad_u64_u32 v[5:6], null, v3, s4, 0
s_load_b128 s[8:11], s[0:1], 0x0
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_lshl_b64 s[2:3], s[4:5], 2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add3_u32 v0, v6, v7, v0
v_sub_co_u32 v5, vcc_lo, v1, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_co_ci_u32_e32 v6, vcc_lo, v2, v0, vcc_lo
v_mov_b32_e32 v0, 0
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s10, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s11, v6, vcc_lo
.LBB0_6:
global_load_b32 v7, v[3:4], off
global_load_b32 v8, v[5:6], off
v_add_co_u32 v5, vcc_lo, v5, s2
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
v_add_co_u32 v3, vcc_lo, v3, 4
s_add_u32 s4, s4, -1
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_addc_u32 s5, s5, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u64 s[4:5], 0
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v0, v7, v8
s_cbranch_scc0 .LBB0_6
s_branch .LBB0_9
.LBB0_7:
s_branch .LBB0_3
.LBB0_8:
v_mov_b32_e32 v0, 0
.LBB0_9:
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11gpu_mat_mulPfS_S_ll
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11gpu_mat_mulPfS_S_ll, .Lfunc_end0-_Z11gpu_mat_mulPfS_S_ll
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11gpu_mat_mulPfS_S_ll
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11gpu_mat_mulPfS_S_ll.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include "string.h"
#include "stdio.h"
#include "stdlib.h"
#include <chrono>
#include <iostream>
#include <iomanip>
using namespace std;
#define CUDA_DEBUG { \
hipError_t err = hipGetLastError(); \
if (err != hipSuccess){ \
printf("Error at %s %s: %s\n", __LINE__, __FILE__, hipGetErrorString(err)); \
exit(1); \
} \
}
__global__ void gpu_mat_mul(float* A, float* B, float* C, long width, long N)
{
const long i = (blockIdx.x * blockDim.x + threadIdx.x);
if(i >= N) return;
float val = 0.0;
float* a = A + (i / width);
float* b = B + (i % width);
for(long j = 0; j < width; j++){
val += *(a + j) * *(b + (width*j));
}
*(C + i) = val;
}
int main(int argc, char **argv){
auto begin = chrono::high_resolution_clock::now();
if(argc < 2){
printf("usage: ./%s <size> \n", argv[0]);
return 1;
}
long size = atol(argv[1]);
long N = size*size;
size_t bytes = sizeof(float) * N;
float* A_h = (float*)malloc(bytes);
float* B_h = (float*)malloc(bytes);
float* C_h = (float*)malloc(bytes);
for(long i = 0; i < N; i++){
*(A_h + i) = (float)i / (float)N;
*(B_h + i) = (float)i / (float)N;
}
float *A_d, *B_d, *C_d;
hipMalloc((void**)&A_d, bytes);
hipMalloc((void**)&B_d, bytes);
hipMalloc((void**)&C_d, bytes);
CUDA_DEBUG
hipMemcpy(A_d, A_h, bytes, hipMemcpyHostToDevice);
hipMemcpy(B_d, B_h, bytes, hipMemcpyHostToDevice);
hipDeviceSynchronize();
CUDA_DEBUG
free(A_h);
free(B_h);
long threadsPerBlock = 1024;
long numBlocks = N / threadsPerBlock;
numBlocks += (N % threadsPerBlock > 0) ? 1 : 0;
gpu_mat_mul <<< numBlocks, threadsPerBlock >>> (A_d, B_d, C_d, size, N);
hipDeviceSynchronize();
CUDA_DEBUG
hipMemcpy(C_h, C_d, bytes, hipMemcpyDeviceToHost);
hipFree(C_d);
hipFree(B_d);
hipFree(A_d);
CUDA_DEBUG
free(C_h);
auto end = chrono::high_resolution_clock::now();
auto duration = chrono::duration_cast<chrono::milliseconds>(end - begin);
cout << "Blocksize * Gridsize: " << setw(2) << threadsPerBlock * numBlocks << " Matrix size: " << setw(9) << size;
cout << " Milliseconds taken: " << setw(15) << duration.count() << endl;
return 0;
} | .text
.file "p6.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z26__device_stub__gpu_mat_mulPfS_S_ll # -- Begin function _Z26__device_stub__gpu_mat_mulPfS_S_ll
.p2align 4, 0x90
.type _Z26__device_stub__gpu_mat_mulPfS_S_ll,@function
_Z26__device_stub__gpu_mat_mulPfS_S_ll: # @_Z26__device_stub__gpu_mat_mulPfS_S_ll
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11gpu_mat_mulPfS_S_ll, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z26__device_stub__gpu_mat_mulPfS_S_ll, .Lfunc_end0-_Z26__device_stub__gpu_mat_mulPfS_S_ll
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
callq _ZNSt6chrono3_V212system_clock3nowEv
cmpl $1, %ebp
jg .LBB1_2
# %bb.1:
movq (%rbx), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $1, %eax
jmp .LBB1_21
.LBB1_2:
movq %rax, 24(%rsp) # 8-byte Spill
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq %rax, %r14
imulq %rax, %r14
leaq (,%r14,4), %r12
movq %r12, %rdi
callq malloc
movq %rax, %r13
movq %r12, %rdi
callq malloc
movq %rax, %rbp
movq %r12, %rdi
callq malloc
movq %rax, 32(%rsp) # 8-byte Spill
movq %rbx, %r15
testq %rbx, %rbx
je .LBB1_5
# %bb.3: # %.lr.ph
cvtsi2ss %r14, %xmm0
cmpq $1, %r14
movq %r14, %rax
adcq $0, %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_4: # =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2ss %rcx, %xmm1
divss %xmm0, %xmm1
movss %xmm1, (%r13,%rcx,4)
movss %xmm1, (%rbp,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_4
.LBB1_5: # %._crit_edge
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq %rsp, %rdi
movq %r12, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB1_6
# %bb.8:
movq 16(%rsp), %rdi
movq %r13, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq %rbp, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB1_9
# %bb.10:
movq %r13, %rdi
callq free
movq %rbp, %rdi
callq free
movq %r14, %r13
shrq $10, %r13
movl %r14d, %eax
andl $1023, %eax # imm = 0x3FF
cmpq $1, %rax
sbbq $-1, %r13
movl %r13d, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
movq %r15, %rbp
jne .LBB1_12
# %bb.11:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movq %rbp, 96(%rsp)
movq %r14, 88(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 96(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rax
movq %rax, 160(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z11gpu_mat_mulPfS_S_ll, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_12:
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB1_13
# %bb.14:
movq (%rsp), %rsi
movq 32(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
callq hipGetLastError
testl %eax, %eax
jne .LBB1_15
# %bb.16:
movq %rbx, %rdi
callq free
callq _ZNSt6chrono3_V212system_clock3nowEv
subq 24(%rsp), %rax # 8-byte Folded Reload
movabsq $4835703278458516699, %rcx # imm = 0x431BDE82D7B634DB
imulq %rcx
movq %rdx, %r14
shrq $63, %r14
sarq $18, %rdx
addq %rdx, %r14
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $2, _ZSt4cout+16(%rax)
shlq $10, %r13
movl $_ZSt4cout, %edi
movq %r13, %rsi
callq _ZNSo9_M_insertIlEERSoT_
movq %rax, %r15
movl $.L.str.4, %esi
movl $14, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r15), %rax
movq -24(%rax), %rax
movq $9, 16(%r15,%rax)
movq %r15, %rdi
movq %rbp, %rsi
callq _ZNSo9_M_insertIlEERSoT_
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $21, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $15, _ZSt4cout+16(%rax)
movl $_ZSt4cout, %edi
movq %r14, %rsi
callq _ZNSo9_M_insertIlEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_22
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_19
# %bb.18:
movzbl 67(%rbx), %ecx
jmp .LBB1_20
.LBB1_19:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
.LBB1_21:
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_6:
.cfi_def_cfa_offset 224
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %edi
movl $.L.str.2, %edx
movl $58, %esi
jmp .LBB1_7
.LBB1_9:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %edi
movl $.L.str.2, %edx
movl $65, %esi
jmp .LBB1_7
.LBB1_13:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %edi
movl $.L.str.2, %edx
movl $77, %esi
jmp .LBB1_7
.LBB1_15:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %edi
movl $.L.str.2, %edx
movl $85, %esi
.LBB1_7:
movq %rax, %rcx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.LBB1_22:
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11gpu_mat_mulPfS_S_ll, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11gpu_mat_mulPfS_S_ll,@object # @_Z11gpu_mat_mulPfS_S_ll
.section .rodata,"a",@progbits
.globl _Z11gpu_mat_mulPfS_S_ll
.p2align 3, 0x0
_Z11gpu_mat_mulPfS_S_ll:
.quad _Z26__device_stub__gpu_mat_mulPfS_S_ll
.size _Z11gpu_mat_mulPfS_S_ll, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "usage: ./%s <size> \n"
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Error at %s %s: %s\n"
.size .L.str.1, 20
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/orb1t-ua/parallel/master/prog6/p6.hip"
.size .L.str.2, 95
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Blocksize * Gridsize: "
.size .L.str.3, 23
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " Matrix size: "
.size .L.str.4, 15
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " Milliseconds taken: "
.size .L.str.5, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11gpu_mat_mulPfS_S_ll"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__gpu_mat_mulPfS_S_ll
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11gpu_mat_mulPfS_S_ll
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11gpu_mat_mulPfS_S_ll
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R5 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0205 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x180], PT ; /* 0x0000600004007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.AND.EX P0, PT, RZ, c[0x0][0x184], PT, P0 ; /* 0x00006100ff007a0c */
/* 0x000fda0003f06300 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fda0003f05070 */
/*0080*/ @!P0 BRA 0x160 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0090*/ MOV R0, 0xb0 ; /* 0x000000b000007802 */
/* 0x000fe40000000f00 */
/*00a0*/ CALL.REL.NOINC 0x8d0 ; /* 0x0000082000007944 */
/* 0x000fea0003c00000 */
/*00b0*/ IADD3 R19, P0, RZ, -R6, RZ ; /* 0x80000006ff137210 */
/* 0x000fe20007f1e0ff */
/*00c0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fc800078e00ff */
/*00d0*/ IMAD.X R0, RZ, RZ, ~R7, P0 ; /* 0x000000ffff007224 */
/* 0x000fe400000e0e07 */
/*00e0*/ IMAD.WIDE.U32 R2, R19, c[0x0][0x178], R4 ; /* 0x00005e0013027a25 */
/* 0x000fc800078e0004 */
/*00f0*/ IMAD R0, R0, c[0x0][0x178], RZ ; /* 0x00005e0000007a24 */
/* 0x000fc800078e02ff */
/*0100*/ IMAD R19, R19, c[0x0][0x17c], R0 ; /* 0x00005f0013137a24 */
/* 0x000fe400078e0200 */
/*0110*/ IMAD.MOV.U32 R0, RZ, RZ, R2 ; /* 0x000000ffff007224 */
/* 0x000fe400078e0002 */
/*0120*/ IMAD.IADD R19, R3, 0x1, R19 ; /* 0x0000000103137824 */
/* 0x000fe200078e0213 */
/*0130*/ MOV R3, R7 ; /* 0x0000000700037202 */
/* 0x000fe20000000f00 */
/*0140*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0006 */
/*0150*/ BRA 0x2c0 ; /* 0x0000016000007947 */
/* 0x000fea0003800000 */
/*0160*/ I2F.U32.RP R0, c[0x0][0x178] ; /* 0x00005e0000007b06 */
/* 0x000e220000209000 */
/*0170*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe20003f45070 */
/*0180*/ IMAD.MOV.U32 R19, RZ, RZ, RZ ; /* 0x000000ffff137224 */
/* 0x000fcc00078e00ff */
/*0190*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*01a0*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fcc0007ffe0ff */
/*01b0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*01c0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*01d0*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a03 */
/*01e0*/ IMAD R7, R7, c[0x0][0x178], RZ ; /* 0x00005e0007077a24 */
/* 0x000fc800078e02ff */
/*01f0*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*0200*/ IMAD.HI.U32 R2, R3, R4, RZ ; /* 0x0000000403027227 */
/* 0x000fc800078e00ff */
/*0210*/ IMAD.MOV R3, RZ, RZ, -R2 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a02 */
/*0220*/ IMAD R3, R3, c[0x0][0x178], R4 ; /* 0x00005e0003037a24 */
/* 0x000fca00078e0204 */
/*0230*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fda0003f06070 */
/*0240*/ @P0 IADD3 R3, R3, -c[0x0][0x178], RZ ; /* 0x80005e0003030a10 */
/* 0x000fe40007ffe0ff */
/*0250*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fe40007ffe0ff */
/*0260*/ ISETP.GE.U32.AND P1, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fda0003f26070 */
/*0270*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*0280*/ @!P2 LOP3.LUT R2, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff02aa12 */
/* 0x000fca00078e33ff */
/*0290*/ IMAD.MOV R3, RZ, RZ, -R2 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a02 */
/*02a0*/ IMAD R0, R3, c[0x0][0x178], R4 ; /* 0x00005e0003007a24 */
/* 0x000fe200078e0204 */
/*02b0*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe400000001ff */
/*02c0*/ IMAD.MOV.U32 R18, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff127624 */
/* 0x000fe200078e00ff */
/*02d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*02e0*/ IMAD.MOV.U32 R21, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff157624 */
/* 0x000fe400078e00ff */
/*02f0*/ IMAD.MOV.U32 R24, RZ, RZ, RZ ; /* 0x000000ffff187224 */
/* 0x000fe200078e00ff */
/*0300*/ ISETP.GE.U32.AND P0, PT, R18, 0x1, PT ; /* 0x000000011200780c */
/* 0x000fc80003f06070 */
/*0310*/ ISETP.GE.AND.EX P0, PT, R21, RZ, PT, P0 ; /* 0x000000ff1500720c */
/* 0x000fda0003f06300 */
/*0320*/ @!P0 BRA 0x890 ; /* 0x0000056000008947 */
/* 0x000fea0003800000 */
/*0330*/ IADD3 R6, P0, R18.reuse, -0x1, RZ ; /* 0xffffffff12067810 */
/* 0x040fe20007f1e0ff */
/*0340*/ CS2R R24, SRZ ; /* 0x0000000000187805 */
/* 0x000fe2000001ff00 */
/*0350*/ LOP3.LUT R20, R18, 0x3, RZ, 0xc0, !PT ; /* 0x0000000312147812 */
/* 0x000fe200078ec0ff */
/*0360*/ IMAD.MOV.U32 R23, RZ, RZ, RZ ; /* 0x000000ffff177224 */
/* 0x000fe200078e00ff */
/*0370*/ ISETP.GE.U32.AND P1, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe40003f26070 */
/*0380*/ IADD3.X R6, R21, -0x1, RZ, P0, !PT ; /* 0xffffffff15067810 */
/* 0x000fe400007fe4ff */
/*0390*/ ISETP.NE.U32.AND P0, PT, R20, RZ, PT ; /* 0x000000ff1400720c */
/* 0x000fe40003f05070 */
/*03a0*/ ISETP.GE.U32.AND.EX P1, PT, R6, RZ, PT, P1 ; /* 0x000000ff0600720c */
/* 0x000fc40003f26110 */
/*03b0*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fd60003f05300 */
/*03c0*/ @!P1 BRA 0x690 ; /* 0x000002c000009947 */
/* 0x000fea0003800000 */
/*03d0*/ LEA R8, P3, R2, c[0x0][0x160], 0x2 ; /* 0x0000580002087a11 */
/* 0x000fe200078610ff */
/*03e0*/ IMAD.SHL.U32 R27, R21, 0x4, RZ ; /* 0x00000004151b7824 */
/* 0x000fe200078e00ff */
/*03f0*/ IADD3 R22, P1, R20, -c[0x0][0x178], RZ ; /* 0x80005e0014167a10 */
/* 0x000fe20007f3e0ff */
/*0400*/ IMAD.WIDE.U32 R6, R18, 0x4, RZ ; /* 0x0000000412067825 */
/* 0x000fe200078e00ff */
/*0410*/ IADD3 R8, P4, R8, 0x8, RZ ; /* 0x0000000808087810 */
/* 0x000fe20007f9e0ff */
/*0420*/ CS2R R24, SRZ ; /* 0x0000000000187805 */
/* 0x000fe2000001ff00 */
/*0430*/ LEA.HI.X R9, R2, c[0x0][0x164], R3, 0x2, P3 ; /* 0x0000590002097a11 */
/* 0x000fe200018f1403 */
/*0440*/ IMAD.IADD R27, R7, 0x1, R27 ; /* 0x00000001071b7824 */
/* 0x000fe200078e021b */
/*0450*/ LEA R17, P2, R0.reuse, c[0x0][0x168], 0x2 ; /* 0x00005a0000117a11 */
/* 0x040fe200078410ff */
/*0460*/ IMAD.X R26, RZ, RZ, ~c[0x0][0x17c], P1 ; /* 0x80005f00ff1a7624 */
/* 0x000fe200008e06ff */
/*0470*/ MOV R23, RZ ; /* 0x000000ff00177202 */
/* 0x000fe20000000f00 */
/*0480*/ IMAD.X R9, RZ, RZ, R9, P4 ; /* 0x000000ffff097224 */
/* 0x000fe200020e0609 */
/*0490*/ LEA.HI.X R12, R0, c[0x0][0x16c], R19, 0x2, P2 ; /* 0x00005b00000c7a11 */
/* 0x000fca00010f1413 */
/*04a0*/ IMAD.MOV.U32 R15, RZ, RZ, R12 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e000c */
/*04b0*/ IMAD.MOV.U32 R14, RZ, RZ, R17 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0011 */
/*04c0*/ IADD3 R16, P1, R17, R6, RZ ; /* 0x0000000611107210 */
/* 0x000fe20007f3e0ff */
/*04d0*/ LDG.E R29, [R8.64+-0x4] ; /* 0xfffffc04081d7981 */
/* 0x000ea8000c1e1900 */
/*04e0*/ LDG.E R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x0000e8000c1e1900 */
/*04f0*/ LDG.E R14, [R8.64+-0x8] ; /* 0xfffff804080e7981 */
/* 0x001ee2000c1e1900 */
/*0500*/ IADD3.X R17, R12, R27, RZ, P1, !PT ; /* 0x0000001b0c117210 */
/* 0x000fc40000ffe4ff */
/*0510*/ IADD3 R10, P1, R16, R6, RZ ; /* 0x00000006100a7210 */
/* 0x000fc60007f3e0ff */
/*0520*/ LDG.E R28, [R16.64] ; /* 0x00000004101c7981 */
/* 0x0000a4000c1e1900 */
/*0530*/ IMAD.X R11, R17, 0x1, R27, P1 ; /* 0x00000001110b7824 */
/* 0x000fe200008e061b */
/*0540*/ IADD3 R12, P1, R10, R6, RZ ; /* 0x000000060a0c7210 */
/* 0x000fc80007f3e0ff */
/*0550*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000322000c1e1900 */
/*0560*/ IMAD.X R13, R11, 0x1, R27, P1 ; /* 0x000000010b0d7824 */
/* 0x000fc600008e061b */
/*0570*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x002322000c1e1900 */
/*0580*/ IADD3 R23, P1, R23, 0x4, RZ ; /* 0x0000000417177810 */
/* 0x000fe20007f3e0ff */
/*0590*/ FFMA R14, R15, R14, R24 ; /* 0x0000000e0f0e7223 */
/* 0x008fe40000000018 */
/*05a0*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000768000c1e1900 */
/*05b0*/ LDG.E R24, [R8.64+0x4] ; /* 0x0000040408187981 */
/* 0x000362000c1e1900 */
/*05c0*/ IADD3 R16, P2, R23, R22, RZ ; /* 0x0000001617107210 */
/* 0x001fe20007f5e0ff */
/*05d0*/ IMAD.X R25, RZ, RZ, R25, P1 ; /* 0x000000ffff197224 */
/* 0x000fc600008e0619 */
/*05e0*/ ISETP.NE.U32.AND P1, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe20003f25070 */
/*05f0*/ IMAD.X R16, R25, 0x1, R26, P2 ; /* 0x0000000119107824 */
/* 0x000fca00010e061a */
/*0600*/ ISETP.NE.AND.EX P1, PT, R16, RZ, PT, P1 ; /* 0x000000ff1000720c */
/* 0x000fe20003f25310 */
/*0610*/ FFMA R14, R28, R29, R14 ; /* 0x0000001d1c0e7223 */
/* 0x004fe2000000000e */
/*0620*/ IADD3 R8, P3, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x002fe40007f7e0ff */
/*0630*/ IADD3 R17, P2, R12, R6, RZ ; /* 0x000000060c117210 */
/* 0x000fe20007f5e0ff */
/*0640*/ FFMA R10, R10, R11, R14 ; /* 0x0000000b0a0a7223 */
/* 0x010fe4000000000e */
/*0650*/ IMAD.X R9, RZ, RZ, R9, P3 ; /* 0x000000ffff097224 */
/* 0x000fe200018e0609 */
/*0660*/ IADD3.X R12, R13, R27, RZ, P2, !PT ; /* 0x0000001b0d0c7210 */
/* 0x008fe200017fe4ff */
/*0670*/ FFMA R24, R15, R24, R10 ; /* 0x000000180f187223 */
/* 0x020fc8000000000a */
/*0680*/ @P1 BRA 0x4a0 ; /* 0xfffffe1000001947 */
/* 0x000fea000383ffff */
/*0690*/ @!P0 BRA 0x890 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*06a0*/ IMAD.MOV.U32 R6, RZ, RZ, R0 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0000 */
/*06b0*/ IADD3 R10, P0, R2, R23, RZ ; /* 0x00000017020a7210 */
/* 0x000fe20007f1e0ff */
/*06c0*/ IMAD.MOV.U32 R7, RZ, RZ, R19 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0013 */
/*06d0*/ IADD3 R20, P2, RZ, -R20, RZ ; /* 0x80000014ff147210 */
/* 0x000fe20007f5e0ff */
/*06e0*/ IMAD R8, R25, c[0x0][0x178], RZ ; /* 0x00005e0019087a24 */
/* 0x000fe200078e02ff */
/*06f0*/ LEA R9, P1, R10, c[0x0][0x160], 0x2 ; /* 0x000058000a097a11 */
/* 0x000fe200078210ff */
/*0700*/ IMAD.WIDE.U32 R6, R23, c[0x0][0x178], R6 ; /* 0x00005e0017067a25 */
/* 0x000fe200078e0006 */
/*0710*/ SHF.L.U64.HI R21, R18, 0x2, R21 ; /* 0x0000000212157819 */
/* 0x000fc60000010215 */
/*0720*/ IMAD R23, R23, c[0x0][0x17c], R8 ; /* 0x00005f0017177a24 */
/* 0x000fe400078e0208 */
/*0730*/ IMAD.X R3, R3, 0x1, R25, P0 ; /* 0x0000000103037824 */
/* 0x000fe200000e0619 */
/*0740*/ LEA R11, P0, R6, c[0x0][0x168], 0x2 ; /* 0x00005a00060b7a11 */
/* 0x000fe200078010ff */
/*0750*/ IMAD.IADD R7, R7, 0x1, R23 ; /* 0x0000000107077824 */
/* 0x000fe400078e0217 */
/*0760*/ IMAD.X R8, RZ, RZ, -0x1, P2 ; /* 0xffffffffff087424 */
/* 0x000fe200010e06ff */
/*0770*/ LEA.HI.X R10, R10, c[0x0][0x164], R3, 0x2, P1 ; /* 0x000059000a0a7a11 */
/* 0x000fe400008f1403 */
/*0780*/ LEA.HI.X R12, R6, c[0x0][0x16c], R7, 0x2, P0 ; /* 0x00005b00060c7a11 */
/* 0x000fca00000f1407 */
/*0790*/ IMAD.MOV.U32 R3, RZ, RZ, R12 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000c */
/*07a0*/ MOV R2, R11 ; /* 0x0000000b00027202 */
/* 0x000fe20000000f00 */
/*07b0*/ IMAD.MOV.U32 R6, RZ, RZ, R9 ; /* 0x000000ffff067224 */
/* 0x000fc400078e0009 */
/*07c0*/ IMAD.MOV.U32 R7, RZ, RZ, R10 ; /* 0x000000ffff077224 */
/* 0x000fe400078e000a */
/*07d0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*07e0*/ LDG.E R0, [R6.64] ; /* 0x0000000406007981 */
/* 0x000ea2000c1e1900 */
/*07f0*/ IADD3 R20, P0, R20, 0x1, RZ ; /* 0x0000000114147810 */
/* 0x000fe40007f1e0ff */
/*0800*/ LEA R11, P1, R18, R11, 0x2 ; /* 0x0000000b120b7211 */
/* 0x000fe400078210ff */
/*0810*/ IADD3 R9, P2, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe20007f5e0ff */
/*0820*/ IMAD.X R8, RZ, RZ, R8, P0 ; /* 0x000000ffff087224 */
/* 0x000fe200000e0608 */
/*0830*/ ISETP.NE.U32.AND P0, PT, R20, RZ, PT ; /* 0x000000ff1400720c */
/* 0x000fe20003f05070 */
/*0840*/ IMAD.X R12, R12, 0x1, R21, P1 ; /* 0x000000010c0c7824 */
/* 0x000fe200008e0615 */
/*0850*/ IADD3.X R10, RZ, R10, RZ, P2, !PT ; /* 0x0000000aff0a7210 */
/* 0x000fc400017fe4ff */
/*0860*/ ISETP.NE.AND.EX P0, PT, R8, RZ, PT, P0 ; /* 0x000000ff0800720c */
/* 0x000fe20003f05300 */
/*0870*/ FFMA R24, R3, R0, R24 ; /* 0x0000000003187223 */
/* 0x004fd80000000018 */
/*0880*/ @P0 BRA 0x790 ; /* 0xffffff0000000947 */
/* 0x000fea000383ffff */
/*0890*/ LEA R2, P0, R4, c[0x0][0x170], 0x2 ; /* 0x00005c0004027a11 */
/* 0x000fc800078010ff */
/*08a0*/ LEA.HI.X R3, R4, c[0x0][0x174], RZ, 0x2, P0 ; /* 0x00005d0004037a11 */
/* 0x000fca00000f14ff */
/*08b0*/ STG.E [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x000fe2000c101904 */
/*08c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08d0*/ IADD3 R2, P0, RZ, -c[0x0][0x178], RZ ; /* 0x80005e00ff027a10 */
/* 0x000fe40007f1e0ff */
/*08e0*/ ISETP.LE.AND P1, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fc60003f23270 */
/*08f0*/ IMAD.X R3, RZ, RZ, ~c[0x0][0x17c], P0 ; /* 0x80005f00ff037624 */
/* 0x000fe200000e06ff */
/*0900*/ SEL R2, R2, c[0x0][0x178], !P1 ; /* 0x00005e0002027a07 */
/* 0x000fc80004800000 */
/*0910*/ SEL R3, R3, c[0x0][0x17c], !P1 ; /* 0x00005f0003037a07 */
/* 0x000fc80004800000 */
/*0920*/ I2F.U64.RP R10, R2 ; /* 0x00000002000a7312 */
/* 0x000e300000309000 */
/*0930*/ MUFU.RCP R10, R10 ; /* 0x0000000a000a7308 */
/* 0x001e240000001000 */
/*0940*/ IADD3 R6, R10, 0x1ffffffe, RZ ; /* 0x1ffffffe0a067810 */
/* 0x001fcc0007ffe0ff */
/*0950*/ F2I.U64.TRUNC R6, R6 ; /* 0x0000000600067311 */
/* 0x000e24000020d800 */
/*0960*/ IMAD.WIDE.U32 R8, R6, R2, RZ ; /* 0x0000000206087225 */
/* 0x001fc800078e00ff */
/*0970*/ IMAD R9, R6, R3, R9 ; /* 0x0000000306097224 */
/* 0x000fe200078e0209 */
/*0980*/ IADD3 R11, P0, RZ, -R8, RZ ; /* 0x80000008ff0b7210 */
/* 0x000fc60007f1e0ff */
/*0990*/ IMAD R9, R7, R2, R9 ; /* 0x0000000207097224 */
/* 0x000fe400078e0209 */
/*09a0*/ IMAD.HI.U32 R8, R6, R11, RZ ; /* 0x0000000b06087227 */
/* 0x000fc800078e00ff */
/*09b0*/ IMAD.X R13, RZ, RZ, ~R9, P0 ; /* 0x000000ffff0d7224 */
/* 0x000fe400000e0e09 */
/*09c0*/ IMAD.MOV.U32 R9, RZ, RZ, R6 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0006 */
/*09d0*/ IMAD R15, R7, R13.reuse, RZ ; /* 0x0000000d070f7224 */
/* 0x080fe400078e02ff */
/*09e0*/ IMAD.WIDE.U32 R8, P0, R6, R13, R8 ; /* 0x0000000d06087225 */
/* 0x000fc80007800008 */
/*09f0*/ IMAD.HI.U32 R13, R7, R13, RZ ; /* 0x0000000d070d7227 */
/* 0x000fc800078e00ff */
/*0a00*/ IMAD.HI.U32 R8, P2, R7, R11, R8 ; /* 0x0000000b07087227 */
/* 0x000fca0007840008 */
/*0a10*/ IADD3 R9, P3, R15, R8, RZ ; /* 0x000000080f097210 */
/* 0x000fe20007f7e0ff */
/*0a20*/ IMAD.X R8, R13, 0x1, R7, P0 ; /* 0x000000010d087824 */
/* 0x000fc800000e0607 */
/*0a30*/ IMAD.WIDE.U32 R6, R9, R2, RZ ; /* 0x0000000209067225 */
/* 0x000fe200078e00ff */
/*0a40*/ IADD3.X R11, RZ, RZ, R8, P3, P2 ; /* 0x000000ffff0b7210 */
/* 0x000fc60001fe4408 */
/*0a50*/ IMAD R7, R9, R3, R7 ; /* 0x0000000309077224 */
/* 0x000fe200078e0207 */
/*0a60*/ IADD3 R13, P0, RZ, -R6, RZ ; /* 0x80000006ff0d7210 */
/* 0x000fc60007f1e0ff */
/*0a70*/ IMAD R7, R11, R2, R7 ; /* 0x000000020b077224 */
/* 0x000fe400078e0207 */
/*0a80*/ IMAD.HI.U32 R8, R9, R13, RZ ; /* 0x0000000d09087227 */
/* 0x000fc800078e00ff */
/*0a90*/ IMAD.X R6, RZ, RZ, ~R7, P0 ; /* 0x000000ffff067224 */
/* 0x000fe400000e0e07 */
/*0aa0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe400078e00ff */
/*0ab0*/ IMAD.WIDE.U32 R8, P0, R9, R6, R8 ; /* 0x0000000609087225 */
/* 0x000fc80007800008 */
/*0ac0*/ IMAD R10, R11.reuse, R6, RZ ; /* 0x000000060b0a7224 */
/* 0x040fe400078e02ff */
/*0ad0*/ IMAD.HI.U32 R9, P2, R11, R13, R8 ; /* 0x0000000d0b097227 */
/* 0x000fc80007840008 */
/*0ae0*/ IMAD.HI.U32 R8, R11, R6, RZ ; /* 0x000000060b087227 */
/* 0x000fe200078e00ff */
/*0af0*/ IADD3 R9, P3, R10, R9, RZ ; /* 0x000000090a097210 */
/* 0x000fc80007f7e0ff */
/*0b00*/ IADD3.X R11, R8, R11, RZ, P0, !PT ; /* 0x0000000b080b7210 */
/* 0x000fe200007fe4ff */
/*0b10*/ IMAD.HI.U32 R6, R9, R4, RZ ; /* 0x0000000409067227 */
/* 0x000fc600078e00ff */
/*0b20*/ IADD3.X R11, RZ, RZ, R11, P3, P2 ; /* 0x000000ffff0b7210 */
/* 0x000fc60001fe440b */
/*0b30*/ IMAD.WIDE.U32 R6, RZ, R9, R6 ; /* 0x00000009ff067225 */
/* 0x000fcc00078e0006 */
/*0b40*/ IMAD.HI.U32 R6, P0, R11, R4, R6 ; /* 0x000000040b067227 */
/* 0x000fc80007800006 */
/*0b50*/ IMAD.X R8, RZ, RZ, RZ, P0 ; /* 0x000000ffff087224 */
/* 0x000fe200000e06ff */
/*0b60*/ IADD3 R9, P2, RZ, R6, RZ ; /* 0x00000006ff097210 */
/* 0x000fca0007f5e0ff */
/*0b70*/ IMAD.WIDE.U32 R6, R9, R2, RZ ; /* 0x0000000209067225 */
/* 0x000fc800078e00ff */
/*0b80*/ IMAD.X R11, RZ, RZ, R8, P2 ; /* 0x000000ffff0b7224 */
/* 0x000fe200010e0608 */
/*0b90*/ IADD3 R15, P2, -R6, R4, RZ ; /* 0x00000004060f7210 */
/* 0x000fe20007f5e1ff */
/*0ba0*/ IMAD R7, R9.reuse, R3, R7 ; /* 0x0000000309077224 */
/* 0x040fe200078e0207 */
/*0bb0*/ IADD3 R6, P3, R9, 0x1, RZ ; /* 0x0000000109067810 */
/* 0x000fe40007f7e0ff */
/*0bc0*/ ISETP.GE.U32.AND P0, PT, R15, R2.reuse, PT ; /* 0x000000020f00720c */
/* 0x080fe20003f06070 */
/*0bd0*/ IMAD R7, R11, R2, R7 ; /* 0x000000020b077224 */
/* 0x000fe200078e0207 */
/*0be0*/ IADD3.X R8, RZ, R11, RZ, P3, !PT ; /* 0x0000000bff087210 */
/* 0x000fc60001ffe4ff */
/*0bf0*/ IMAD.X R17, RZ, RZ, ~R7, P2 ; /* 0x000000ffff117224 */
/* 0x000fe200010e0e07 */
/*0c00*/ IADD3 R7, P2, R15, -R2, RZ ; /* 0x800000020f077210 */
/* 0x000fc80007f5e0ff */
/*0c10*/ ISETP.GE.U32.AND.EX P0, PT, R17.reuse, R3, PT, P0 ; /* 0x000000031100720c */
/* 0x040fe20003f06100 */
/*0c20*/ IMAD.X R13, R17, 0x1, ~R3, P2 ; /* 0x00000001110d7824 */
/* 0x000fc600010e0e03 */
/*0c30*/ SEL R7, R7, R15, P0 ; /* 0x0000000f07077207 */
/* 0x000fe40000000000 */
/*0c40*/ SEL R9, R6, R9, P0 ; /* 0x0000000906097207 */
/* 0x000fe40000000000 */
/*0c50*/ SEL R13, R13, R17, P0 ; /* 0x000000110d0d7207 */
/* 0x000fe40000000000 */
/*0c60*/ ISETP.GE.U32.AND P2, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x000fe40003f46070 */
/*0c70*/ SEL R2, R8, R11, P0 ; /* 0x0000000b08027207 */
/* 0x000fe40000000000 */
/*0c80*/ IADD3 R6, P3, R9, 0x1, RZ ; /* 0x0000000109067810 */
/* 0x000fc40007f7e0ff */
/*0c90*/ ISETP.GE.U32.AND.EX P0, PT, R13, R3, PT, P2 ; /* 0x000000030d00720c */
/* 0x000fc60003f06120 */
/*0ca0*/ IMAD.X R7, RZ, RZ, R2, P3 ; /* 0x000000ffff077224 */
/* 0x000fe200018e0602 */
/*0cb0*/ SEL R6, R6, R9, P0 ; /* 0x0000000906067207 */
/* 0x000fc80000000000 */
/*0cc0*/ SEL R7, R7, R2, P0 ; /* 0x0000000207077207 */
/* 0x000fe40000000000 */
/*0cd0*/ IADD3 R3, P2, RZ, -R6.reuse, RZ ; /* 0x80000006ff037210 */
/* 0x080fe40007f5e0ff */
/*0ce0*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe40003f05070 */
/*0cf0*/ SEL R6, R3, R6, !P1 ; /* 0x0000000603067207 */
/* 0x000fe20004800000 */
/*0d00*/ IMAD.X R2, RZ, RZ, ~R7, P2 ; /* 0x000000ffff027224 */
/* 0x000fe200010e0e07 */
/*0d10*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x17c], PT, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fe20003f05300 */
/*0d20*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc600078e00ff */
/*0d30*/ SEL R7, R2, R7, !P1 ; /* 0x0000000702077207 */
/* 0x000fe20004800000 */
/*0d40*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0000 */
/*0d50*/ SEL R6, R6, 0xffffffff, P0 ; /* 0xffffffff06067807 */
/* 0x000fe40000000000 */
/*0d60*/ SEL R7, R7, 0xffffffff, P0 ; /* 0xffffffff07077807 */
/* 0x000fe20000000000 */
/*0d70*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff28002007950 */
/* 0x000fec0003c3ffff */
/*0d80*/ BRA 0xd80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11gpu_mat_mulPfS_S_ll
.globl _Z11gpu_mat_mulPfS_S_ll
.p2align 8
.type _Z11gpu_mat_mulPfS_S_ll,@function
_Z11gpu_mat_mulPfS_S_ll:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_10
s_load_b64 s[4:5], s[0:1], 0x18
s_mov_b32 s6, 0
s_waitcnt lgkmcnt(0)
s_mov_b32 s7, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_7
s_ashr_i32 s8, s5, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_u32 s2, s4, s8
s_mov_b32 s9, s8
s_addc_u32 s3, s5, s8
s_xor_b64 s[10:11], s[2:3], s[8:9]
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v0, s10
v_cvt_f32_u32_e32 v3, s11
s_sub_u32 s2, 0, s10
s_subb_u32 s3, 0, s11
v_fmamk_f32 v0, v3, 0x4f800000, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x5f7ffffc, v0
v_mul_f32_e32 v3, 0x2f800000, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_trunc_f32_e32 v3, v3
v_fmamk_f32 v0, v3, 0xcf800000, v0
v_cvt_u32_f32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v4, s2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, s2, v0
v_mul_lo_u32 v6, s3, v0
v_add_nc_u32_e32 v4, v5, v4
v_mul_lo_u32 v5, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, v4, v6
v_mul_hi_u32 v6, v0, v5
s_delay_alu instid0(VALU_DEP_2)
v_mul_lo_u32 v7, v0, v4
v_mul_hi_u32 v8, v0, v4
v_mul_hi_u32 v9, v3, v5
v_mul_lo_u32 v5, v3, v5
v_mul_hi_u32 v10, v3, v4
v_mul_lo_u32 v4, v3, v4
v_add_co_u32 v6, vcc_lo, v6, v7
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, v6, v5
v_add_co_ci_u32_e32 v5, vcc_lo, v7, v9, vcc_lo
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v10, vcc_lo
v_ashrrev_i32_e32 v9, 31, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v5, v4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v4
v_add_co_ci_u32_e32 v3, vcc_lo, v3, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v4, s2, v0
v_mul_lo_u32 v6, s3, v0
v_mul_lo_u32 v5, s2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, v4, v5
v_mul_lo_u32 v5, s2, v0
v_add_nc_u32_e32 v4, v4, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v6, v0, v5
v_mul_lo_u32 v7, v0, v4
v_mul_hi_u32 v8, v0, v4
v_mul_hi_u32 v10, v3, v5
v_mul_lo_u32 v5, v3, v5
v_mul_hi_u32 v11, v3, v4
v_mul_lo_u32 v4, v3, v4
v_add_co_u32 v6, vcc_lo, v6, v7
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, v6, v5
v_add_co_ci_u32_e32 v5, vcc_lo, v7, v10, vcc_lo
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v11, vcc_lo
v_add_co_u32 v7, vcc_lo, v1, v9
v_add_co_ci_u32_e32 v8, vcc_lo, v2, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, v5, v4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v10, v7, v9
v_add_co_u32 v0, vcc_lo, v0, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v11, vcc_lo, v3, v5, vcc_lo
v_xor_b32_e32 v12, v8, v9
v_mul_hi_u32 v13, v10, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[3:4], null, v10, v11, 0
v_mad_u64_u32 v[5:6], null, v12, v0, 0
v_mad_u64_u32 v[7:8], null, v12, v11, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, v13, v3
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v5
v_add_co_ci_u32_e32 v0, vcc_lo, v3, v6, vcc_lo
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v7
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v6, s11, v0
v_mad_u64_u32 v[3:4], null, s10, v0, 0
v_mul_lo_u32 v7, s10, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v3, vcc_lo, v10, v3
v_add3_u32 v4, v4, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v6, v12, v4
v_subrev_co_ci_u32_e64 v6, s2, s11, v6, vcc_lo
v_add_co_u32 v7, s2, v0, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v8, s2, 0, v5, s2
v_sub_co_u32 v10, s2, v3, s10
v_sub_co_ci_u32_e32 v4, vcc_lo, v12, v4, vcc_lo
v_subrev_co_ci_u32_e64 v6, s2, 0, v6, s2
v_cmp_le_u32_e32 vcc_lo, s10, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cmp_eq_u32_e64 s2, s11, v4
v_cndmask_b32_e64 v10, 0, -1, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s11, v6
v_cndmask_b32_e64 v11, 0, -1, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s10, v3
v_cndmask_b32_e64 v3, 0, -1, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s11, v4
v_cndmask_b32_e64 v12, 0, -1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, s11, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v3, v12, v3, s2
v_cndmask_b32_e32 v6, v11, v10, vcc_lo
v_add_co_u32 v10, vcc_lo, v0, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v4, v11, v8, vcc_lo
v_cndmask_b32_e32 v6, v10, v7, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v3
v_xor_b32_e32 v3, s8, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v0, v0, v6, vcc_lo
v_cndmask_b32_e32 v4, v5, v4, vcc_lo
v_xor_b32_e32 v5, s8, v9
v_xor_b32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v4, v4, v5
v_sub_co_u32 v3, vcc_lo, v0, v3
s_delay_alu instid0(VALU_DEP_2)
v_sub_co_ci_u32_e32 v4, vcc_lo, v4, v5, vcc_lo
s_and_not1_b32 vcc_lo, exec_lo, s6
s_cbranch_vccnz .LBB0_4
.LBB0_3:
v_cvt_f32_u32_e32 v0, s4
s_sub_i32 s2, 0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, s2, v0
v_mul_hi_u32 v3, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v3
v_mul_hi_u32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v3, v0, s4
v_add_nc_u32_e32 v4, 1, v0
v_sub_nc_u32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s4, v3
v_cmp_le_u32_e32 vcc_lo, s4, v3
v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s4, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_1)
v_dual_cndmask_b32 v3, v0, v4 :: v_dual_mov_b32 v4, 0
.LBB0_4:
v_cmp_lt_i64_e64 s2, s[4:5], 1
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_8
s_delay_alu instid0(VALU_DEP_2)
v_mul_lo_u32 v0, v4, s4
v_mul_lo_u32 v7, v3, s5
v_mad_u64_u32 v[5:6], null, v3, s4, 0
s_load_b128 s[8:11], s[0:1], 0x0
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_lshl_b64 s[2:3], s[4:5], 2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add3_u32 v0, v6, v7, v0
v_sub_co_u32 v5, vcc_lo, v1, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_co_ci_u32_e32 v6, vcc_lo, v2, v0, vcc_lo
v_mov_b32_e32 v0, 0
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s10, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s11, v6, vcc_lo
.LBB0_6:
global_load_b32 v7, v[3:4], off
global_load_b32 v8, v[5:6], off
v_add_co_u32 v5, vcc_lo, v5, s2
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
v_add_co_u32 v3, vcc_lo, v3, 4
s_add_u32 s4, s4, -1
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_addc_u32 s5, s5, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u64 s[4:5], 0
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v0, v7, v8
s_cbranch_scc0 .LBB0_6
s_branch .LBB0_9
.LBB0_7:
s_branch .LBB0_3
.LBB0_8:
v_mov_b32_e32 v0, 0
.LBB0_9:
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11gpu_mat_mulPfS_S_ll
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11gpu_mat_mulPfS_S_ll, .Lfunc_end0-_Z11gpu_mat_mulPfS_S_ll
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11gpu_mat_mulPfS_S_ll
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11gpu_mat_mulPfS_S_ll.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00132069_00000000-6_p6.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4054:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z11gpu_mat_mulPfS_S_llPfS_S_ll
.type _Z37__device_stub__Z11gpu_mat_mulPfS_S_llPfS_S_ll, @function
_Z37__device_stub__Z11gpu_mat_mulPfS_S_llPfS_S_ll:
.LFB4076:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11gpu_mat_mulPfS_S_ll(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4076:
.size _Z37__device_stub__Z11gpu_mat_mulPfS_S_llPfS_S_ll, .-_Z37__device_stub__Z11gpu_mat_mulPfS_S_llPfS_S_ll
.globl _Z11gpu_mat_mulPfS_S_ll
.type _Z11gpu_mat_mulPfS_S_ll, @function
_Z11gpu_mat_mulPfS_S_ll:
.LFB4077:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z11gpu_mat_mulPfS_S_llPfS_S_ll
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4077:
.size _Z11gpu_mat_mulPfS_S_ll, .-_Z11gpu_mat_mulPfS_S_ll
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "usage: ./%s <size> \n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/orb1t-ua/parallel/master/prog6/p6.cu"
.section .rodata.str1.1
.LC2:
.string "Error at %s %s: %s\n"
.LC3:
.string "Blocksize * Gridsize: "
.LC4:
.string " Matrix size: "
.LC5:
.string " Milliseconds taken: "
.text
.globl main
.type main, @function
main:
.LFB4048:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movl %edi, %ebp
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, 8(%rsp)
cmpl $1, %ebp
jle .L24
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r14
movq %rax, %rbx
imulq %rax, %rbx
leaq 0(,%rbx,4), %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %r12
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r13, %rdi
call malloc@PLT
movq %rax, %r15
testq %rbx, %rbx
jle .L14
movl $0, %eax
pxor %xmm1, %xmm1
cvtsi2ssq %rbx, %xmm1
.L15:
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss %xmm1, %xmm0
movss %xmm0, (%r12,%rax,4)
movss %xmm0, 0(%rbp,%rax,4)
addq $1, %rax
cmpq %rax, %rbx
jne .L15
.L14:
leaq 24(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L25
movl $1, %ecx
movq %r13, %rdx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L26
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
leaq 1023(%rbx), %rbp
testq %rbx, %rbx
cmovns %rbx, %rbp
sarq $10, %rbp
movq %rbx, %rax
andl $1023, %eax
cmpq $1, %rax
sbbq $-1, %rbp
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl %ebp, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L18:
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L28
movl $2, %ecx
movq %r13, %rdx
movq 40(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L29
movq %r15, %rdi
call free@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq 8(%rsp), %rcx
subq %rcx, %rax
movq %rax, %rcx
movabsq $4835703278458516699, %rdx
imulq %rdx
sarq $18, %rdx
sarq $63, %rcx
subq %rcx, %rdx
movq %rdx, %rbx
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %r12
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq (%rax), %rax
movq -24(%rax), %rax
movq $2, 16(%rdi,%rax)
movq %rbp, %rsi
salq $10, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq (%rax), %rax
movq -24(%rax), %rax
movq $9, 16(%rdi,%rax)
movq %r14, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
leaq .LC5(%rip), %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq (%rax), %rax
movq -24(%rax), %rax
movq $15, 16(%rdi,%rax)
movq %rbx, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %eax
.L11:
movq 72(%rsp), %rdx
subq %fs:40, %rdx
jne .L30
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movq (%rbx), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L11
.L25:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
leaq .LC1(%rip), %rcx
movl $58, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L26:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
leaq .LC1(%rip), %rcx
movl $65, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L27:
movq %rbx, %r8
movq %r14, %rcx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z37__device_stub__Z11gpu_mat_mulPfS_S_llPfS_S_ll
jmp .L18
.L28:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
leaq .LC1(%rip), %rcx
movl $77, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L29:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
leaq .LC1(%rip), %rcx
movl $85, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4048:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z11gpu_mat_mulPfS_S_ll"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4079:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z11gpu_mat_mulPfS_S_ll(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4079:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "p6.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z26__device_stub__gpu_mat_mulPfS_S_ll # -- Begin function _Z26__device_stub__gpu_mat_mulPfS_S_ll
.p2align 4, 0x90
.type _Z26__device_stub__gpu_mat_mulPfS_S_ll,@function
_Z26__device_stub__gpu_mat_mulPfS_S_ll: # @_Z26__device_stub__gpu_mat_mulPfS_S_ll
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11gpu_mat_mulPfS_S_ll, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z26__device_stub__gpu_mat_mulPfS_S_ll, .Lfunc_end0-_Z26__device_stub__gpu_mat_mulPfS_S_ll
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
callq _ZNSt6chrono3_V212system_clock3nowEv
cmpl $1, %ebp
jg .LBB1_2
# %bb.1:
movq (%rbx), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $1, %eax
jmp .LBB1_21
.LBB1_2:
movq %rax, 24(%rsp) # 8-byte Spill
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq %rax, %r14
imulq %rax, %r14
leaq (,%r14,4), %r12
movq %r12, %rdi
callq malloc
movq %rax, %r13
movq %r12, %rdi
callq malloc
movq %rax, %rbp
movq %r12, %rdi
callq malloc
movq %rax, 32(%rsp) # 8-byte Spill
movq %rbx, %r15
testq %rbx, %rbx
je .LBB1_5
# %bb.3: # %.lr.ph
cvtsi2ss %r14, %xmm0
cmpq $1, %r14
movq %r14, %rax
adcq $0, %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_4: # =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2ss %rcx, %xmm1
divss %xmm0, %xmm1
movss %xmm1, (%r13,%rcx,4)
movss %xmm1, (%rbp,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_4
.LBB1_5: # %._crit_edge
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq %rsp, %rdi
movq %r12, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB1_6
# %bb.8:
movq 16(%rsp), %rdi
movq %r13, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq %rbp, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB1_9
# %bb.10:
movq %r13, %rdi
callq free
movq %rbp, %rdi
callq free
movq %r14, %r13
shrq $10, %r13
movl %r14d, %eax
andl $1023, %eax # imm = 0x3FF
cmpq $1, %rax
sbbq $-1, %r13
movl %r13d, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
movq %r15, %rbp
jne .LBB1_12
# %bb.11:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movq %rbp, 96(%rsp)
movq %r14, 88(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 96(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rax
movq %rax, 160(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z11gpu_mat_mulPfS_S_ll, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_12:
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB1_13
# %bb.14:
movq (%rsp), %rsi
movq 32(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
callq hipGetLastError
testl %eax, %eax
jne .LBB1_15
# %bb.16:
movq %rbx, %rdi
callq free
callq _ZNSt6chrono3_V212system_clock3nowEv
subq 24(%rsp), %rax # 8-byte Folded Reload
movabsq $4835703278458516699, %rcx # imm = 0x431BDE82D7B634DB
imulq %rcx
movq %rdx, %r14
shrq $63, %r14
sarq $18, %rdx
addq %rdx, %r14
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $2, _ZSt4cout+16(%rax)
shlq $10, %r13
movl $_ZSt4cout, %edi
movq %r13, %rsi
callq _ZNSo9_M_insertIlEERSoT_
movq %rax, %r15
movl $.L.str.4, %esi
movl $14, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r15), %rax
movq -24(%rax), %rax
movq $9, 16(%r15,%rax)
movq %r15, %rdi
movq %rbp, %rsi
callq _ZNSo9_M_insertIlEERSoT_
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $21, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $15, _ZSt4cout+16(%rax)
movl $_ZSt4cout, %edi
movq %r14, %rsi
callq _ZNSo9_M_insertIlEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_22
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_19
# %bb.18:
movzbl 67(%rbx), %ecx
jmp .LBB1_20
.LBB1_19:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
.LBB1_21:
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_6:
.cfi_def_cfa_offset 224
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %edi
movl $.L.str.2, %edx
movl $58, %esi
jmp .LBB1_7
.LBB1_9:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %edi
movl $.L.str.2, %edx
movl $65, %esi
jmp .LBB1_7
.LBB1_13:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %edi
movl $.L.str.2, %edx
movl $77, %esi
jmp .LBB1_7
.LBB1_15:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %edi
movl $.L.str.2, %edx
movl $85, %esi
.LBB1_7:
movq %rax, %rcx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.LBB1_22:
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11gpu_mat_mulPfS_S_ll, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11gpu_mat_mulPfS_S_ll,@object # @_Z11gpu_mat_mulPfS_S_ll
.section .rodata,"a",@progbits
.globl _Z11gpu_mat_mulPfS_S_ll
.p2align 3, 0x0
_Z11gpu_mat_mulPfS_S_ll:
.quad _Z26__device_stub__gpu_mat_mulPfS_S_ll
.size _Z11gpu_mat_mulPfS_S_ll, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "usage: ./%s <size> \n"
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Error at %s %s: %s\n"
.size .L.str.1, 20
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/orb1t-ua/parallel/master/prog6/p6.hip"
.size .L.str.2, 95
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Blocksize * Gridsize: "
.size .L.str.3, 23
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " Matrix size: "
.size .L.str.4, 15
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " Milliseconds taken: "
.size .L.str.5, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11gpu_mat_mulPfS_S_ll"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__gpu_mat_mulPfS_S_ll
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11gpu_mat_mulPfS_S_ll
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
#include <cuda_runtime.h>
__global__ void _erode(char *grayIn, char *grayOut, int width, int height, int kernelSize, int *mask)
{
const unsigned int offset = blockIdx.x * blockDim.x + threadIdx.x;
const int x = offset % width;
const int y = (offset-x) / width;
if( x - kernelSize / 2 < 0 || y - kernelSize / 2 < 0 || x + kernelSize / 2 > width || y + kernelSize / 2 > height ) return;
int intensitySum = 0;
int subImageSize = kernelSize * kernelSize;
for( int i = 0; i < subImageSize; i++ ) {
if( (unsigned char)grayIn[ offset + mask[i] ] > 100 ) intensitySum++;
}
if( intensitySum == subImageSize )
grayOut[ offset ] = (unsigned char)255;
else
grayOut[ offset ] = (unsigned char)0;
}
__global__ void _dilate(char *grayIn, char *grayOut, int width, int height, int kernelSize, int *mask)
{
const unsigned int offset = blockIdx.x * blockDim.x + threadIdx.x;
const int x = offset % width;
const int y = (offset-x) / width;
if( x - kernelSize / 2 < 0 || y - kernelSize / 2 < 0 || x + kernelSize / 2 > width || y + kernelSize / 2 > height ) return;
int intensitySum = 0;
int subImageSize = kernelSize * kernelSize;
for( int i = 0; i < subImageSize; i++ ) {
if( (unsigned char)grayIn[ offset + mask[i] ] > 100 ) intensitySum++;
}
if( intensitySum >= 1 )
grayOut[ offset ] = (unsigned char)255;
else
grayOut[ offset ] = (unsigned char)0;
}
int* _getRangeMask(int kernelSize, int width)
{
int *mask = (int*)malloc(sizeof(int)*kernelSize*kernelSize);
int subImageSize = kernelSize*kernelSize;
int centerPixel = subImageSize / 2;
int centerPixelCol = centerPixel / ( subImageSize / kernelSize );
int centerPixelRow = centerPixel % ( subImageSize / kernelSize );
for( int i = 0; i < subImageSize; i++ ) {
int rowIdx = i / ( subImageSize / kernelSize );
int colIdx = i % ( subImageSize / kernelSize );
mask[i] = ( rowIdx - centerPixelRow ) * width + ( colIdx - centerPixelCol );
}
return mask;
}
void gpu_erode( char *host_src, char *host_dst, int width, int height, int kernelSize = 3 )
{
cudaDeviceProp prop;
int nMaxThreadsPerBlock;
int count = 1;
cudaGetDeviceCount( &count );
for( int i = 0; i < count; i++ ) {
cudaGetDeviceProperties( &prop, i );
nMaxThreadsPerBlock = prop.maxThreadsPerBlock;
}
const int nBlocks = ( width * height + nMaxThreadsPerBlock - 1 ) / nMaxThreadsPerBlock;
char *dev_src, *dev_dst;
cudaMalloc( (void**)&dev_src, sizeof(char)*width*height );
cudaMalloc( (void**)&dev_dst, sizeof(char)*width*height );
cudaMemcpy( dev_src, host_src, sizeof(char)*width*height, cudaMemcpyHostToDevice );
int *host_mask = _getRangeMask( kernelSize, width );
int *dev_mask;
cudaMalloc( (void**)&dev_mask, sizeof(int)*kernelSize*kernelSize);
cudaMemcpy( dev_mask, host_mask, sizeof(int)*kernelSize*kernelSize, cudaMemcpyHostToDevice );
_erode<<< nBlocks, nMaxThreadsPerBlock >>>( dev_src, dev_dst, width, height, kernelSize, dev_mask );
cudaMemcpy( host_dst, dev_dst, sizeof(char)*width*height, cudaMemcpyDeviceToHost );
cudaFree( dev_src );
cudaFree( dev_dst );
cudaFree( dev_mask );
free( host_mask );
}
void gpu_dilate( char *host_src, char *host_dst, int width, int height, int kernelSize = 3 )
{
cudaDeviceProp prop;
int nMaxThreadsPerBlock;
int count = 1;
cudaGetDeviceCount( &count );
for( int i = 0; i < count; i++ ) {
cudaGetDeviceProperties( &prop, i );
nMaxThreadsPerBlock = prop.maxThreadsPerBlock;
}
const int nBlocks = ( width * height + nMaxThreadsPerBlock - 1 ) / nMaxThreadsPerBlock;
char *dev_src, *dev_dst;
cudaMalloc( (void**)&dev_src, sizeof(char)*width*height );
cudaMalloc( (void**)&dev_dst, sizeof(char)*width*height );
cudaMemcpy( dev_src, host_src, sizeof(char)*width*height, cudaMemcpyHostToDevice );
int *host_mask = _getRangeMask( kernelSize, width );
int *dev_mask;
cudaMalloc( (void**)&dev_mask, sizeof(int)*kernelSize*kernelSize);
cudaMemcpy( dev_mask, host_mask, sizeof(int)*kernelSize*kernelSize, cudaMemcpyHostToDevice );
_dilate<<< nBlocks, nMaxThreadsPerBlock >>>( dev_src, dev_dst, width, height, kernelSize, dev_mask );
cudaMemcpy( host_dst, dev_dst, sizeof(char)*width*height, cudaMemcpyDeviceToHost );
cudaFree( dev_src );
cudaFree( dev_dst );
cudaFree( dev_mask );
free( host_mask );
} | .file "tmpxft_00154da5_00000000-6_CudaImageMorphology.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13_getRangeMaskii
.type _Z13_getRangeMaskii, @function
_Z13_getRangeMaskii:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl %edi, %ebx
movl %esi, %ebp
movslq %edi, %rdi
imulq %rdi, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r8
movl %ebx, %edi
imull %ebx, %edi
movl %edi, %eax
shrl $31, %eax
addl %edi, %eax
sarl %eax
cltd
idivl %ebx
testl %edi, %edi
jle .L3
movl %edx, %r9d
movl %eax, %esi
movslq %edi, %rdi
movl $0, %ecx
.L5:
movl %ecx, %eax
cltd
idivl %ebx
subl %r9d, %eax
imull %ebp, %eax
subl %esi, %edx
addl %edx, %eax
movl %eax, (%r8,%rcx,4)
addq $1, %rcx
cmpq %rdi, %rcx
jne .L5
.L3:
movq %r8, %rax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z13_getRangeMaskii, .-_Z13_getRangeMaskii
.globl _Z32__device_stub__Z6_erodePcS_iiiPiPcS_iiiPi
.type _Z32__device_stub__Z6_erodePcS_iiiPiPcS_iiiPi, @function
_Z32__device_stub__Z6_erodePcS_iiiPiPcS_iiiPi:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movl %r8d, 20(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6_erodePcS_iiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z32__device_stub__Z6_erodePcS_iiiPiPcS_iiiPi, .-_Z32__device_stub__Z6_erodePcS_iiiPiPcS_iiiPi
.globl _Z6_erodePcS_iiiPi
.type _Z6_erodePcS_iiiPi, @function
_Z6_erodePcS_iiiPi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6_erodePcS_iiiPiPcS_iiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z6_erodePcS_iiiPi, .-_Z6_erodePcS_iiiPi
.globl _Z9gpu_erodePcS_iii
.type _Z9gpu_erodePcS_iii, @function
_Z9gpu_erodePcS_iii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1144, %rsp
.cfi_def_cfa_offset 1200
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movl %edx, %r13d
movl %ecx, %r14d
movl %r8d, %r15d
movq %fs:40, %rax
movq %rax, 1128(%rsp)
xorl %eax, %eax
movl $1, 44(%rsp)
leaq 44(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 44(%rsp)
jle .L17
movl $0, %ebp
leaq 96(%rsp), %r12
.L18:
movl %ebp, %esi
movq %r12, %rdi
call cudaGetDeviceProperties_v2@PLT
movl 416(%rsp), %ebx
addl $1, %ebp
cmpl %ebp, 44(%rsp)
jg .L18
.L17:
movl %r13d, %eax
imull %r14d, %eax
leal -1(%rbx,%rax), %eax
cltd
idivl %ebx
movl %eax, 28(%rsp)
movslq %r13d, %rbp
movslq %r14d, %rax
imulq %rax, %rbp
leaq 48(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbp, %rdx
movq 8(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl %r13d, %esi
movl %r15d, %edi
call _Z13_getRangeMaskii
movq %rax, 8(%rsp)
movslq %r15d, %r12
imulq %r12, %r12
salq $2, %r12
leaq 64(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq 8(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl %ebx, 84(%rsp)
movl $1, 88(%rsp)
movl 28(%rsp), %eax
movl %eax, 72(%rsp)
movl $1, 76(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 84(%rsp), %rdx
movl $1, %ecx
movq 72(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movl $2, %ecx
movq %rbp, %rdx
movq 56(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 1128(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $1144, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movq 64(%rsp), %r9
movl %r15d, %r8d
movl %r14d, %ecx
movl %r13d, %edx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z32__device_stub__Z6_erodePcS_iiiPiPcS_iiiPi
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z9gpu_erodePcS_iii, .-_Z9gpu_erodePcS_iii
.globl _Z33__device_stub__Z7_dilatePcS_iiiPiPcS_iiiPi
.type _Z33__device_stub__Z7_dilatePcS_iiiPiPcS_iiiPi, @function
_Z33__device_stub__Z7_dilatePcS_iiiPiPcS_iiiPi:
.LFB2086:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movl %r8d, 20(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7_dilatePcS_iiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z33__device_stub__Z7_dilatePcS_iiiPiPcS_iiiPi, .-_Z33__device_stub__Z7_dilatePcS_iiiPiPcS_iiiPi
.globl _Z7_dilatePcS_iiiPi
.type _Z7_dilatePcS_iiiPi, @function
_Z7_dilatePcS_iiiPi:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z7_dilatePcS_iiiPiPcS_iiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z7_dilatePcS_iiiPi, .-_Z7_dilatePcS_iiiPi
.globl _Z10gpu_dilatePcS_iii
.type _Z10gpu_dilatePcS_iii, @function
_Z10gpu_dilatePcS_iii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1144, %rsp
.cfi_def_cfa_offset 1200
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movl %edx, %r13d
movl %ecx, %r14d
movl %r8d, %r15d
movq %fs:40, %rax
movq %rax, 1128(%rsp)
xorl %eax, %eax
movl $1, 44(%rsp)
leaq 44(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 44(%rsp)
jle .L34
movl $0, %ebp
leaq 96(%rsp), %r12
.L35:
movl %ebp, %esi
movq %r12, %rdi
call cudaGetDeviceProperties_v2@PLT
movl 416(%rsp), %ebx
addl $1, %ebp
cmpl %ebp, 44(%rsp)
jg .L35
.L34:
movl %r13d, %eax
imull %r14d, %eax
leal -1(%rbx,%rax), %eax
cltd
idivl %ebx
movl %eax, 28(%rsp)
movslq %r13d, %rbp
movslq %r14d, %rax
imulq %rax, %rbp
leaq 48(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbp, %rdx
movq 8(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl %r13d, %esi
movl %r15d, %edi
call _Z13_getRangeMaskii
movq %rax, 8(%rsp)
movslq %r15d, %r12
imulq %r12, %r12
salq $2, %r12
leaq 64(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq 8(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl %ebx, 84(%rsp)
movl $1, 88(%rsp)
movl 28(%rsp), %eax
movl %eax, 72(%rsp)
movl $1, 76(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 84(%rsp), %rdx
movl $1, %ecx
movq 72(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L40
.L36:
movl $2, %ecx
movq %rbp, %rdx
movq 56(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 1128(%rsp), %rax
subq %fs:40, %rax
jne .L41
addq $1144, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
movq 64(%rsp), %r9
movl %r15d, %r8d
movl %r14d, %ecx
movl %r13d, %edx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z33__device_stub__Z7_dilatePcS_iiiPiPcS_iiiPi
jmp .L36
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z10gpu_dilatePcS_iii, .-_Z10gpu_dilatePcS_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7_dilatePcS_iiiPi"
.LC1:
.string "_Z6_erodePcS_iiiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7_dilatePcS_iiiPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6_erodePcS_iiiPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
#include <cuda_runtime.h>
__global__ void _erode(char *grayIn, char *grayOut, int width, int height, int kernelSize, int *mask)
{
const unsigned int offset = blockIdx.x * blockDim.x + threadIdx.x;
const int x = offset % width;
const int y = (offset-x) / width;
if( x - kernelSize / 2 < 0 || y - kernelSize / 2 < 0 || x + kernelSize / 2 > width || y + kernelSize / 2 > height ) return;
int intensitySum = 0;
int subImageSize = kernelSize * kernelSize;
for( int i = 0; i < subImageSize; i++ ) {
if( (unsigned char)grayIn[ offset + mask[i] ] > 100 ) intensitySum++;
}
if( intensitySum == subImageSize )
grayOut[ offset ] = (unsigned char)255;
else
grayOut[ offset ] = (unsigned char)0;
}
__global__ void _dilate(char *grayIn, char *grayOut, int width, int height, int kernelSize, int *mask)
{
const unsigned int offset = blockIdx.x * blockDim.x + threadIdx.x;
const int x = offset % width;
const int y = (offset-x) / width;
if( x - kernelSize / 2 < 0 || y - kernelSize / 2 < 0 || x + kernelSize / 2 > width || y + kernelSize / 2 > height ) return;
int intensitySum = 0;
int subImageSize = kernelSize * kernelSize;
for( int i = 0; i < subImageSize; i++ ) {
if( (unsigned char)grayIn[ offset + mask[i] ] > 100 ) intensitySum++;
}
if( intensitySum >= 1 )
grayOut[ offset ] = (unsigned char)255;
else
grayOut[ offset ] = (unsigned char)0;
}
int* _getRangeMask(int kernelSize, int width)
{
int *mask = (int*)malloc(sizeof(int)*kernelSize*kernelSize);
int subImageSize = kernelSize*kernelSize;
int centerPixel = subImageSize / 2;
int centerPixelCol = centerPixel / ( subImageSize / kernelSize );
int centerPixelRow = centerPixel % ( subImageSize / kernelSize );
for( int i = 0; i < subImageSize; i++ ) {
int rowIdx = i / ( subImageSize / kernelSize );
int colIdx = i % ( subImageSize / kernelSize );
mask[i] = ( rowIdx - centerPixelRow ) * width + ( colIdx - centerPixelCol );
}
return mask;
}
void gpu_erode( char *host_src, char *host_dst, int width, int height, int kernelSize = 3 )
{
cudaDeviceProp prop;
int nMaxThreadsPerBlock;
int count = 1;
cudaGetDeviceCount( &count );
for( int i = 0; i < count; i++ ) {
cudaGetDeviceProperties( &prop, i );
nMaxThreadsPerBlock = prop.maxThreadsPerBlock;
}
const int nBlocks = ( width * height + nMaxThreadsPerBlock - 1 ) / nMaxThreadsPerBlock;
char *dev_src, *dev_dst;
cudaMalloc( (void**)&dev_src, sizeof(char)*width*height );
cudaMalloc( (void**)&dev_dst, sizeof(char)*width*height );
cudaMemcpy( dev_src, host_src, sizeof(char)*width*height, cudaMemcpyHostToDevice );
int *host_mask = _getRangeMask( kernelSize, width );
int *dev_mask;
cudaMalloc( (void**)&dev_mask, sizeof(int)*kernelSize*kernelSize);
cudaMemcpy( dev_mask, host_mask, sizeof(int)*kernelSize*kernelSize, cudaMemcpyHostToDevice );
_erode<<< nBlocks, nMaxThreadsPerBlock >>>( dev_src, dev_dst, width, height, kernelSize, dev_mask );
cudaMemcpy( host_dst, dev_dst, sizeof(char)*width*height, cudaMemcpyDeviceToHost );
cudaFree( dev_src );
cudaFree( dev_dst );
cudaFree( dev_mask );
free( host_mask );
}
void gpu_dilate( char *host_src, char *host_dst, int width, int height, int kernelSize = 3 )
{
cudaDeviceProp prop;
int nMaxThreadsPerBlock;
int count = 1;
cudaGetDeviceCount( &count );
for( int i = 0; i < count; i++ ) {
cudaGetDeviceProperties( &prop, i );
nMaxThreadsPerBlock = prop.maxThreadsPerBlock;
}
const int nBlocks = ( width * height + nMaxThreadsPerBlock - 1 ) / nMaxThreadsPerBlock;
char *dev_src, *dev_dst;
cudaMalloc( (void**)&dev_src, sizeof(char)*width*height );
cudaMalloc( (void**)&dev_dst, sizeof(char)*width*height );
cudaMemcpy( dev_src, host_src, sizeof(char)*width*height, cudaMemcpyHostToDevice );
int *host_mask = _getRangeMask( kernelSize, width );
int *dev_mask;
cudaMalloc( (void**)&dev_mask, sizeof(int)*kernelSize*kernelSize);
cudaMemcpy( dev_mask, host_mask, sizeof(int)*kernelSize*kernelSize, cudaMemcpyHostToDevice );
_dilate<<< nBlocks, nMaxThreadsPerBlock >>>( dev_src, dev_dst, width, height, kernelSize, dev_mask );
cudaMemcpy( host_dst, dev_dst, sizeof(char)*width*height, cudaMemcpyDeviceToHost );
cudaFree( dev_src );
cudaFree( dev_dst );
cudaFree( dev_mask );
free( host_mask );
} | #include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void _erode(char *grayIn, char *grayOut, int width, int height, int kernelSize, int *mask)
{
const unsigned int offset = blockIdx.x * blockDim.x + threadIdx.x;
const int x = offset % width;
const int y = (offset-x) / width;
if( x - kernelSize / 2 < 0 || y - kernelSize / 2 < 0 || x + kernelSize / 2 > width || y + kernelSize / 2 > height ) return;
int intensitySum = 0;
int subImageSize = kernelSize * kernelSize;
for( int i = 0; i < subImageSize; i++ ) {
if( (unsigned char)grayIn[ offset + mask[i] ] > 100 ) intensitySum++;
}
if( intensitySum == subImageSize )
grayOut[ offset ] = (unsigned char)255;
else
grayOut[ offset ] = (unsigned char)0;
}
__global__ void _dilate(char *grayIn, char *grayOut, int width, int height, int kernelSize, int *mask)
{
const unsigned int offset = blockIdx.x * blockDim.x + threadIdx.x;
const int x = offset % width;
const int y = (offset-x) / width;
if( x - kernelSize / 2 < 0 || y - kernelSize / 2 < 0 || x + kernelSize / 2 > width || y + kernelSize / 2 > height ) return;
int intensitySum = 0;
int subImageSize = kernelSize * kernelSize;
for( int i = 0; i < subImageSize; i++ ) {
if( (unsigned char)grayIn[ offset + mask[i] ] > 100 ) intensitySum++;
}
if( intensitySum >= 1 )
grayOut[ offset ] = (unsigned char)255;
else
grayOut[ offset ] = (unsigned char)0;
}
int* _getRangeMask(int kernelSize, int width)
{
int *mask = (int*)malloc(sizeof(int)*kernelSize*kernelSize);
int subImageSize = kernelSize*kernelSize;
int centerPixel = subImageSize / 2;
int centerPixelCol = centerPixel / ( subImageSize / kernelSize );
int centerPixelRow = centerPixel % ( subImageSize / kernelSize );
for( int i = 0; i < subImageSize; i++ ) {
int rowIdx = i / ( subImageSize / kernelSize );
int colIdx = i % ( subImageSize / kernelSize );
mask[i] = ( rowIdx - centerPixelRow ) * width + ( colIdx - centerPixelCol );
}
return mask;
}
void gpu_erode( char *host_src, char *host_dst, int width, int height, int kernelSize = 3 )
{
hipDeviceProp_t prop;
int nMaxThreadsPerBlock;
int count = 1;
hipGetDeviceCount( &count );
for( int i = 0; i < count; i++ ) {
hipGetDeviceProperties( &prop, i );
nMaxThreadsPerBlock = prop.maxThreadsPerBlock;
}
const int nBlocks = ( width * height + nMaxThreadsPerBlock - 1 ) / nMaxThreadsPerBlock;
char *dev_src, *dev_dst;
hipMalloc( (void**)&dev_src, sizeof(char)*width*height );
hipMalloc( (void**)&dev_dst, sizeof(char)*width*height );
hipMemcpy( dev_src, host_src, sizeof(char)*width*height, hipMemcpyHostToDevice );
int *host_mask = _getRangeMask( kernelSize, width );
int *dev_mask;
hipMalloc( (void**)&dev_mask, sizeof(int)*kernelSize*kernelSize);
hipMemcpy( dev_mask, host_mask, sizeof(int)*kernelSize*kernelSize, hipMemcpyHostToDevice );
_erode<<< nBlocks, nMaxThreadsPerBlock >>>( dev_src, dev_dst, width, height, kernelSize, dev_mask );
hipMemcpy( host_dst, dev_dst, sizeof(char)*width*height, hipMemcpyDeviceToHost );
hipFree( dev_src );
hipFree( dev_dst );
hipFree( dev_mask );
free( host_mask );
}
void gpu_dilate( char *host_src, char *host_dst, int width, int height, int kernelSize = 3 )
{
hipDeviceProp_t prop;
int nMaxThreadsPerBlock;
int count = 1;
hipGetDeviceCount( &count );
for( int i = 0; i < count; i++ ) {
hipGetDeviceProperties( &prop, i );
nMaxThreadsPerBlock = prop.maxThreadsPerBlock;
}
const int nBlocks = ( width * height + nMaxThreadsPerBlock - 1 ) / nMaxThreadsPerBlock;
char *dev_src, *dev_dst;
hipMalloc( (void**)&dev_src, sizeof(char)*width*height );
hipMalloc( (void**)&dev_dst, sizeof(char)*width*height );
hipMemcpy( dev_src, host_src, sizeof(char)*width*height, hipMemcpyHostToDevice );
int *host_mask = _getRangeMask( kernelSize, width );
int *dev_mask;
hipMalloc( (void**)&dev_mask, sizeof(int)*kernelSize*kernelSize);
hipMemcpy( dev_mask, host_mask, sizeof(int)*kernelSize*kernelSize, hipMemcpyHostToDevice );
_dilate<<< nBlocks, nMaxThreadsPerBlock >>>( dev_src, dev_dst, width, height, kernelSize, dev_mask );
hipMemcpy( host_dst, dev_dst, sizeof(char)*width*height, hipMemcpyDeviceToHost );
hipFree( dev_src );
hipFree( dev_dst );
hipFree( dev_mask );
free( host_mask );
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void _erode(char *grayIn, char *grayOut, int width, int height, int kernelSize, int *mask)
{
const unsigned int offset = blockIdx.x * blockDim.x + threadIdx.x;
const int x = offset % width;
const int y = (offset-x) / width;
if( x - kernelSize / 2 < 0 || y - kernelSize / 2 < 0 || x + kernelSize / 2 > width || y + kernelSize / 2 > height ) return;
int intensitySum = 0;
int subImageSize = kernelSize * kernelSize;
for( int i = 0; i < subImageSize; i++ ) {
if( (unsigned char)grayIn[ offset + mask[i] ] > 100 ) intensitySum++;
}
if( intensitySum == subImageSize )
grayOut[ offset ] = (unsigned char)255;
else
grayOut[ offset ] = (unsigned char)0;
}
__global__ void _dilate(char *grayIn, char *grayOut, int width, int height, int kernelSize, int *mask)
{
const unsigned int offset = blockIdx.x * blockDim.x + threadIdx.x;
const int x = offset % width;
const int y = (offset-x) / width;
if( x - kernelSize / 2 < 0 || y - kernelSize / 2 < 0 || x + kernelSize / 2 > width || y + kernelSize / 2 > height ) return;
int intensitySum = 0;
int subImageSize = kernelSize * kernelSize;
for( int i = 0; i < subImageSize; i++ ) {
if( (unsigned char)grayIn[ offset + mask[i] ] > 100 ) intensitySum++;
}
if( intensitySum >= 1 )
grayOut[ offset ] = (unsigned char)255;
else
grayOut[ offset ] = (unsigned char)0;
}
int* _getRangeMask(int kernelSize, int width)
{
int *mask = (int*)malloc(sizeof(int)*kernelSize*kernelSize);
int subImageSize = kernelSize*kernelSize;
int centerPixel = subImageSize / 2;
int centerPixelCol = centerPixel / ( subImageSize / kernelSize );
int centerPixelRow = centerPixel % ( subImageSize / kernelSize );
for( int i = 0; i < subImageSize; i++ ) {
int rowIdx = i / ( subImageSize / kernelSize );
int colIdx = i % ( subImageSize / kernelSize );
mask[i] = ( rowIdx - centerPixelRow ) * width + ( colIdx - centerPixelCol );
}
return mask;
}
void gpu_erode( char *host_src, char *host_dst, int width, int height, int kernelSize = 3 )
{
hipDeviceProp_t prop;
int nMaxThreadsPerBlock;
int count = 1;
hipGetDeviceCount( &count );
for( int i = 0; i < count; i++ ) {
hipGetDeviceProperties( &prop, i );
nMaxThreadsPerBlock = prop.maxThreadsPerBlock;
}
const int nBlocks = ( width * height + nMaxThreadsPerBlock - 1 ) / nMaxThreadsPerBlock;
char *dev_src, *dev_dst;
hipMalloc( (void**)&dev_src, sizeof(char)*width*height );
hipMalloc( (void**)&dev_dst, sizeof(char)*width*height );
hipMemcpy( dev_src, host_src, sizeof(char)*width*height, hipMemcpyHostToDevice );
int *host_mask = _getRangeMask( kernelSize, width );
int *dev_mask;
hipMalloc( (void**)&dev_mask, sizeof(int)*kernelSize*kernelSize);
hipMemcpy( dev_mask, host_mask, sizeof(int)*kernelSize*kernelSize, hipMemcpyHostToDevice );
_erode<<< nBlocks, nMaxThreadsPerBlock >>>( dev_src, dev_dst, width, height, kernelSize, dev_mask );
hipMemcpy( host_dst, dev_dst, sizeof(char)*width*height, hipMemcpyDeviceToHost );
hipFree( dev_src );
hipFree( dev_dst );
hipFree( dev_mask );
free( host_mask );
}
void gpu_dilate( char *host_src, char *host_dst, int width, int height, int kernelSize = 3 )
{
hipDeviceProp_t prop;
int nMaxThreadsPerBlock;
int count = 1;
hipGetDeviceCount( &count );
for( int i = 0; i < count; i++ ) {
hipGetDeviceProperties( &prop, i );
nMaxThreadsPerBlock = prop.maxThreadsPerBlock;
}
const int nBlocks = ( width * height + nMaxThreadsPerBlock - 1 ) / nMaxThreadsPerBlock;
char *dev_src, *dev_dst;
hipMalloc( (void**)&dev_src, sizeof(char)*width*height );
hipMalloc( (void**)&dev_dst, sizeof(char)*width*height );
hipMemcpy( dev_src, host_src, sizeof(char)*width*height, hipMemcpyHostToDevice );
int *host_mask = _getRangeMask( kernelSize, width );
int *dev_mask;
hipMalloc( (void**)&dev_mask, sizeof(int)*kernelSize*kernelSize);
hipMemcpy( dev_mask, host_mask, sizeof(int)*kernelSize*kernelSize, hipMemcpyHostToDevice );
_dilate<<< nBlocks, nMaxThreadsPerBlock >>>( dev_src, dev_dst, width, height, kernelSize, dev_mask );
hipMemcpy( host_dst, dev_dst, sizeof(char)*width*height, hipMemcpyDeviceToHost );
hipFree( dev_src );
hipFree( dev_dst );
hipFree( dev_mask );
free( host_mask );
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6_erodePcS_iiiPi
.globl _Z6_erodePcS_iiiPi
.p2align 8
.type _Z6_erodePcS_iiiPi,@function
_Z6_erodePcS_iiiPi:
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b32 s4, s[0:1], 0x18
s_load_b32 s5, s[0:1], 0x34
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v1, s2
s_sub_i32 s6, 0, s2
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, s6, v3
v_mul_hi_u32 v4, v3, v1
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
s_lshr_b32 s5, s4, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s5, s4, s5
s_ashr_i32 s5, s5, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v3, v4
v_mul_hi_u32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v0, s2
v_add_nc_u32_e32 v3, 1, v0
v_sub_nc_u32_e32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_subrev_nc_u32_e32 v4, s2, v2
v_cmp_le_u32_e32 vcc_lo, s2, v2
v_cndmask_b32_e32 v0, v0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
v_add_nc_u32_e32 v3, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s2, v2
v_cndmask_b32_e32 v0, v0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v0, s2
v_add_nc_u32_e32 v4, s5, v0
v_sub_nc_u32_e32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, s5, v2
v_min_i32_e32 v0, v2, v0
v_cmp_ge_i32_e32 vcc_lo, s2, v3
v_cmp_ge_i32_e64 s2, s3, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_i32_e64 s3, s5, v0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v0, 0
s_cmp_eq_u32 s4, 0
s_mul_i32 s6, s4, s4
s_cbranch_scc1 .LBB0_4
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x20
v_mov_b32_e32 v0, 0
s_max_u32 s7, s6, 1
.LBB0_3:
s_waitcnt lgkmcnt(0)
s_load_b32 s8, s[4:5], 0x0
s_add_i32 s7, s7, -1
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s7, 0
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, s8, v1
global_load_u8 v2, v2, s[2:3]
s_waitcnt vmcnt(0)
v_cmp_lt_u16_e32 vcc_lo, 0x64, v2
v_add_co_ci_u32_e32 v0, vcc_lo, 0, v0, vcc_lo
s_cbranch_scc0 .LBB0_3
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1)
v_cmp_eq_u32_e32 vcc_lo, s6, v0
v_cndmask_b32_e64 v0, 0, -1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b8 v1, v0, s[0:1]
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6_erodePcS_iiiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6_erodePcS_iiiPi, .Lfunc_end0-_Z6_erodePcS_iiiPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7_dilatePcS_iiiPi
.globl _Z7_dilatePcS_iiiPi
.p2align 8
.type _Z7_dilatePcS_iiiPi,@function
_Z7_dilatePcS_iiiPi:
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b32 s6, s[0:1], 0x18
s_load_b32 s4, s[0:1], 0x34
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v1, s2
s_sub_i32 s5, 0, s2
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, s5, v3
v_mul_hi_u32 v4, v3, v1
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_lshr_b32 s4, s6, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s4, s6, s4
s_ashr_i32 s4, s4, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v3, v4
v_mul_hi_u32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v0, s2
v_add_nc_u32_e32 v3, 1, v0
v_sub_nc_u32_e32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_subrev_nc_u32_e32 v4, s2, v2
v_cmp_le_u32_e32 vcc_lo, s2, v2
v_cndmask_b32_e32 v0, v0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
v_add_nc_u32_e32 v3, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s2, v2
v_cndmask_b32_e32 v0, v0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v0, s2
v_add_nc_u32_e32 v4, s4, v0
v_sub_nc_u32_e32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, s4, v2
v_min_i32_e32 v0, v2, v0
v_cmp_ge_i32_e32 vcc_lo, s2, v3
v_cmp_ge_i32_e64 s2, s3, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_i32_e64 s3, s4, v0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_9
s_cmp_eq_u32 s6, 0
s_cbranch_scc1 .LBB1_5
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x20
v_mov_b32_e32 v0, 0
s_mul_i32 s6, s6, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_max_u32 s6, s6, 1
.LBB1_3:
s_waitcnt lgkmcnt(0)
s_load_b32 s7, s[4:5], 0x0
s_add_i32 s6, s6, -1
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s6, 0
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, s7, v1
global_load_u8 v2, v2, s[2:3]
s_waitcnt vmcnt(0)
v_cmp_lt_u16_e32 vcc_lo, 0x64, v2
v_add_co_ci_u32_e32 v0, vcc_lo, 0, v0, vcc_lo
s_cbranch_scc0 .LBB1_3
s_delay_alu instid0(VALU_DEP_1)
v_cmp_eq_u32_e64 s2, 0, v0
s_movk_i32 s3, 0xff
s_branch .LBB1_6
.LBB1_5:
s_mov_b32 s2, -1
.LBB1_6:
v_mov_b32_e32 v0, s3
s_delay_alu instid0(VALU_DEP_2)
s_and_saveexec_b32 s3, s2
v_mov_b32_e32 v0, 0
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
global_store_b8 v1, v0, s[0:1]
.LBB1_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7_dilatePcS_iiiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7_dilatePcS_iiiPi, .Lfunc_end1-_Z7_dilatePcS_iiiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6_erodePcS_iiiPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6_erodePcS_iiiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7_dilatePcS_iiiPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7_dilatePcS_iiiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void _erode(char *grayIn, char *grayOut, int width, int height, int kernelSize, int *mask)
{
const unsigned int offset = blockIdx.x * blockDim.x + threadIdx.x;
const int x = offset % width;
const int y = (offset-x) / width;
if( x - kernelSize / 2 < 0 || y - kernelSize / 2 < 0 || x + kernelSize / 2 > width || y + kernelSize / 2 > height ) return;
int intensitySum = 0;
int subImageSize = kernelSize * kernelSize;
for( int i = 0; i < subImageSize; i++ ) {
if( (unsigned char)grayIn[ offset + mask[i] ] > 100 ) intensitySum++;
}
if( intensitySum == subImageSize )
grayOut[ offset ] = (unsigned char)255;
else
grayOut[ offset ] = (unsigned char)0;
}
__global__ void _dilate(char *grayIn, char *grayOut, int width, int height, int kernelSize, int *mask)
{
const unsigned int offset = blockIdx.x * blockDim.x + threadIdx.x;
const int x = offset % width;
const int y = (offset-x) / width;
if( x - kernelSize / 2 < 0 || y - kernelSize / 2 < 0 || x + kernelSize / 2 > width || y + kernelSize / 2 > height ) return;
int intensitySum = 0;
int subImageSize = kernelSize * kernelSize;
for( int i = 0; i < subImageSize; i++ ) {
if( (unsigned char)grayIn[ offset + mask[i] ] > 100 ) intensitySum++;
}
if( intensitySum >= 1 )
grayOut[ offset ] = (unsigned char)255;
else
grayOut[ offset ] = (unsigned char)0;
}
int* _getRangeMask(int kernelSize, int width)
{
int *mask = (int*)malloc(sizeof(int)*kernelSize*kernelSize);
int subImageSize = kernelSize*kernelSize;
int centerPixel = subImageSize / 2;
int centerPixelCol = centerPixel / ( subImageSize / kernelSize );
int centerPixelRow = centerPixel % ( subImageSize / kernelSize );
for( int i = 0; i < subImageSize; i++ ) {
int rowIdx = i / ( subImageSize / kernelSize );
int colIdx = i % ( subImageSize / kernelSize );
mask[i] = ( rowIdx - centerPixelRow ) * width + ( colIdx - centerPixelCol );
}
return mask;
}
void gpu_erode( char *host_src, char *host_dst, int width, int height, int kernelSize = 3 )
{
hipDeviceProp_t prop;
int nMaxThreadsPerBlock;
int count = 1;
hipGetDeviceCount( &count );
for( int i = 0; i < count; i++ ) {
hipGetDeviceProperties( &prop, i );
nMaxThreadsPerBlock = prop.maxThreadsPerBlock;
}
const int nBlocks = ( width * height + nMaxThreadsPerBlock - 1 ) / nMaxThreadsPerBlock;
char *dev_src, *dev_dst;
hipMalloc( (void**)&dev_src, sizeof(char)*width*height );
hipMalloc( (void**)&dev_dst, sizeof(char)*width*height );
hipMemcpy( dev_src, host_src, sizeof(char)*width*height, hipMemcpyHostToDevice );
int *host_mask = _getRangeMask( kernelSize, width );
int *dev_mask;
hipMalloc( (void**)&dev_mask, sizeof(int)*kernelSize*kernelSize);
hipMemcpy( dev_mask, host_mask, sizeof(int)*kernelSize*kernelSize, hipMemcpyHostToDevice );
_erode<<< nBlocks, nMaxThreadsPerBlock >>>( dev_src, dev_dst, width, height, kernelSize, dev_mask );
hipMemcpy( host_dst, dev_dst, sizeof(char)*width*height, hipMemcpyDeviceToHost );
hipFree( dev_src );
hipFree( dev_dst );
hipFree( dev_mask );
free( host_mask );
}
void gpu_dilate( char *host_src, char *host_dst, int width, int height, int kernelSize = 3 )
{
hipDeviceProp_t prop;
int nMaxThreadsPerBlock;
int count = 1;
hipGetDeviceCount( &count );
for( int i = 0; i < count; i++ ) {
hipGetDeviceProperties( &prop, i );
nMaxThreadsPerBlock = prop.maxThreadsPerBlock;
}
const int nBlocks = ( width * height + nMaxThreadsPerBlock - 1 ) / nMaxThreadsPerBlock;
char *dev_src, *dev_dst;
hipMalloc( (void**)&dev_src, sizeof(char)*width*height );
hipMalloc( (void**)&dev_dst, sizeof(char)*width*height );
hipMemcpy( dev_src, host_src, sizeof(char)*width*height, hipMemcpyHostToDevice );
int *host_mask = _getRangeMask( kernelSize, width );
int *dev_mask;
hipMalloc( (void**)&dev_mask, sizeof(int)*kernelSize*kernelSize);
hipMemcpy( dev_mask, host_mask, sizeof(int)*kernelSize*kernelSize, hipMemcpyHostToDevice );
_dilate<<< nBlocks, nMaxThreadsPerBlock >>>( dev_src, dev_dst, width, height, kernelSize, dev_mask );
hipMemcpy( host_dst, dev_dst, sizeof(char)*width*height, hipMemcpyDeviceToHost );
hipFree( dev_src );
hipFree( dev_dst );
hipFree( dev_mask );
free( host_mask );
} | .text
.file "CudaImageMorphology.hip"
.globl _Z21__device_stub___erodePcS_iiiPi # -- Begin function _Z21__device_stub___erodePcS_iiiPi
.p2align 4, 0x90
.type _Z21__device_stub___erodePcS_iiiPi,@function
_Z21__device_stub___erodePcS_iiiPi: # @_Z21__device_stub___erodePcS_iiiPi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %r9, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6_erodePcS_iiiPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z21__device_stub___erodePcS_iiiPi, .Lfunc_end0-_Z21__device_stub___erodePcS_iiiPi
.cfi_endproc
# -- End function
.globl _Z22__device_stub___dilatePcS_iiiPi # -- Begin function _Z22__device_stub___dilatePcS_iiiPi
.p2align 4, 0x90
.type _Z22__device_stub___dilatePcS_iiiPi,@function
_Z22__device_stub___dilatePcS_iiiPi: # @_Z22__device_stub___dilatePcS_iiiPi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %r9, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7_dilatePcS_iiiPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z22__device_stub___dilatePcS_iiiPi, .Lfunc_end1-_Z22__device_stub___dilatePcS_iiiPi
.cfi_endproc
# -- End function
.globl _Z13_getRangeMaskii # -- Begin function _Z13_getRangeMaskii
.p2align 4, 0x90
.type _Z13_getRangeMaskii,@function
_Z13_getRangeMaskii: # @_Z13_getRangeMaskii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %esi, %ebx
movl %edi, %ebp
movslq %edi, %r14
movq %r14, %rdi
imulq %r14, %rdi
shlq $2, %rdi
callq malloc
movq %rax, %rcx
movl %r14d, %r9d
imull %r9d, %r9d
movl %r9d, %eax
shrl %eax
xorl %edx, %edx
idivl %r14d
movl %eax, %esi
movl %edx, %edi
xorl %r8d, %r8d
cmpl $1, %r9d
adcl $0, %r9d
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl %r8d, %eax
cltd
idivl %ebp
subl %edi, %eax
imull %ebx, %eax
subl %esi, %edx
addl %eax, %edx
movl %edx, (%rcx,%r8,4)
incq %r8
cmpq %r8, %r9
jne .LBB2_1
# %bb.2:
movq %rcx, %rax
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z13_getRangeMaskii, .Lfunc_end2-_Z13_getRangeMaskii
.cfi_endproc
# -- End function
.globl _Z9gpu_erodePcS_iii # -- Begin function _Z9gpu_erodePcS_iii
.p2align 4, 0x90
.type _Z9gpu_erodePcS_iii,@function
_Z9gpu_erodePcS_iii: # @_Z9gpu_erodePcS_iii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1672, %rsp # imm = 0x688
.cfi_def_cfa_offset 1728
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, %ebp
movl %ecx, %r13d
movl %edx, %r12d
movq %rsi, 64(%rsp) # 8-byte Spill
movq %rdi, %r15
movl $1, 4(%rsp)
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 4(%rsp)
jle .LBB3_1
# %bb.8: # %.lr.ph.preheader
xorl %ebx, %ebx
leaq 200(%rsp), %r14
.p2align 4, 0x90
.LBB3_9: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl %ebx, %esi
callq hipGetDevicePropertiesR0600
incl %ebx
cmpl 4(%rsp), %ebx
jl .LBB3_9
# %bb.2: # %._crit_edge
movl 520(%rsp), %ecx
jmp .LBB3_3
.LBB3_1:
# implicit-def: $ecx
.LBB3_3:
movl %r13d, %eax
imull %r12d, %eax
movq %rcx, 48(%rsp) # 8-byte Spill
leal (%rax,%rcx), %ebx
decl %ebx
movslq %r12d, %rax
movl %r13d, 32(%rsp) # 4-byte Spill
movslq %r13d, %r14
imulq %rax, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r15, %rsi
movq %r14, 56(%rsp) # 8-byte Spill
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movslq %ebp, %r15
movq %r15, %r14
imulq %r15, %r14
shlq $2, %r14
movq %r14, %rdi
callq malloc
movq %rax, %r13
movl %r15d, %r8d
imull %r8d, %r8d
movl %r8d, %eax
shrl %eax
xorl %edx, %edx
idivl %r15d
movl %eax, %ecx
movl %edx, %esi
xorl %edi, %edi
cmpl $1, %r8d
adcl $0, %r8d
.p2align 4, 0x90
.LBB3_4: # =>This Inner Loop Header: Depth=1
movl %edi, %eax
cltd
idivl %ebp
subl %esi, %eax
imull %r12d, %eax
subl %ecx, %edx
addl %eax, %edx
movl %edx, (%r13,%rdi,4)
incq %rdi
cmpq %rdi, %r8
jne .LBB3_4
# %bb.5: # %_Z13_getRangeMaskii.exit
movl %ebx, %eax
cltd
movq 48(%rsp), %r15 # 8-byte Reload
idivl %r15d
movl %eax, %ebx
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rbx
movl %r15d, %edx
orq %rax, %rdx
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_7
# %bb.6:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movl %r12d, 44(%rsp)
movl 32(%rsp), %eax # 4-byte Reload
movl %eax, 40(%rsp)
movl %ebp, 36(%rsp)
movq %rdx, 120(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 44(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rax
movq %rax, 168(%rsp)
leaq 36(%rsp), %rax
movq %rax, 176(%rsp)
leaq 120(%rsp), %rax
movq %rax, 184(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z6_erodePcS_iiiPi, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_7:
movq 16(%rsp), %rsi
movq 64(%rsp), %rdi # 8-byte Reload
movq 56(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %r13, %rdi
callq free
addq $1672, %rsp # imm = 0x688
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z9gpu_erodePcS_iii, .Lfunc_end3-_Z9gpu_erodePcS_iii
.cfi_endproc
# -- End function
.globl _Z10gpu_dilatePcS_iii # -- Begin function _Z10gpu_dilatePcS_iii
.p2align 4, 0x90
.type _Z10gpu_dilatePcS_iii,@function
_Z10gpu_dilatePcS_iii: # @_Z10gpu_dilatePcS_iii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1672, %rsp # imm = 0x688
.cfi_def_cfa_offset 1728
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, %ebp
movl %ecx, %r13d
movl %edx, %r12d
movq %rsi, 64(%rsp) # 8-byte Spill
movq %rdi, %r15
movl $1, 4(%rsp)
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 4(%rsp)
jle .LBB4_1
# %bb.8: # %.lr.ph.preheader
xorl %ebx, %ebx
leaq 200(%rsp), %r14
.p2align 4, 0x90
.LBB4_9: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl %ebx, %esi
callq hipGetDevicePropertiesR0600
incl %ebx
cmpl 4(%rsp), %ebx
jl .LBB4_9
# %bb.2: # %._crit_edge
movl 520(%rsp), %ecx
jmp .LBB4_3
.LBB4_1:
# implicit-def: $ecx
.LBB4_3:
movl %r13d, %eax
imull %r12d, %eax
movq %rcx, 48(%rsp) # 8-byte Spill
leal (%rax,%rcx), %ebx
decl %ebx
movslq %r12d, %rax
movl %r13d, 32(%rsp) # 4-byte Spill
movslq %r13d, %r14
imulq %rax, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r15, %rsi
movq %r14, 56(%rsp) # 8-byte Spill
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movslq %ebp, %r15
movq %r15, %r14
imulq %r15, %r14
shlq $2, %r14
movq %r14, %rdi
callq malloc
movq %rax, %r13
movl %r15d, %r8d
imull %r8d, %r8d
movl %r8d, %eax
shrl %eax
xorl %edx, %edx
idivl %r15d
movl %eax, %ecx
movl %edx, %esi
xorl %edi, %edi
cmpl $1, %r8d
adcl $0, %r8d
.p2align 4, 0x90
.LBB4_4: # =>This Inner Loop Header: Depth=1
movl %edi, %eax
cltd
idivl %ebp
subl %esi, %eax
imull %r12d, %eax
subl %ecx, %edx
addl %eax, %edx
movl %edx, (%r13,%rdi,4)
incq %rdi
cmpq %rdi, %r8
jne .LBB4_4
# %bb.5: # %_Z13_getRangeMaskii.exit
movl %ebx, %eax
cltd
movq 48(%rsp), %r15 # 8-byte Reload
idivl %r15d
movl %eax, %ebx
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rbx
movl %r15d, %edx
orq %rax, %rdx
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_7
# %bb.6:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movl %r12d, 44(%rsp)
movl 32(%rsp), %eax # 4-byte Reload
movl %eax, 40(%rsp)
movl %ebp, 36(%rsp)
movq %rdx, 120(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 44(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rax
movq %rax, 168(%rsp)
leaq 36(%rsp), %rax
movq %rax, 176(%rsp)
leaq 120(%rsp), %rax
movq %rax, 184(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z7_dilatePcS_iiiPi, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_7:
movq 16(%rsp), %rsi
movq 64(%rsp), %rdi # 8-byte Reload
movq 56(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %r13, %rdi
callq free
addq $1672, %rsp # imm = 0x688
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z10gpu_dilatePcS_iii, .Lfunc_end4-_Z10gpu_dilatePcS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6_erodePcS_iiiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7_dilatePcS_iiiPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6_erodePcS_iiiPi,@object # @_Z6_erodePcS_iiiPi
.section .rodata,"a",@progbits
.globl _Z6_erodePcS_iiiPi
.p2align 3, 0x0
_Z6_erodePcS_iiiPi:
.quad _Z21__device_stub___erodePcS_iiiPi
.size _Z6_erodePcS_iiiPi, 8
.type _Z7_dilatePcS_iiiPi,@object # @_Z7_dilatePcS_iiiPi
.globl _Z7_dilatePcS_iiiPi
.p2align 3, 0x0
_Z7_dilatePcS_iiiPi:
.quad _Z22__device_stub___dilatePcS_iiiPi
.size _Z7_dilatePcS_iiiPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6_erodePcS_iiiPi"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7_dilatePcS_iiiPi"
.size .L__unnamed_2, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub___erodePcS_iiiPi
.addrsig_sym _Z22__device_stub___dilatePcS_iiiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6_erodePcS_iiiPi
.addrsig_sym _Z7_dilatePcS_iiiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00154da5_00000000-6_CudaImageMorphology.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13_getRangeMaskii
.type _Z13_getRangeMaskii, @function
_Z13_getRangeMaskii:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl %edi, %ebx
movl %esi, %ebp
movslq %edi, %rdi
imulq %rdi, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r8
movl %ebx, %edi
imull %ebx, %edi
movl %edi, %eax
shrl $31, %eax
addl %edi, %eax
sarl %eax
cltd
idivl %ebx
testl %edi, %edi
jle .L3
movl %edx, %r9d
movl %eax, %esi
movslq %edi, %rdi
movl $0, %ecx
.L5:
movl %ecx, %eax
cltd
idivl %ebx
subl %r9d, %eax
imull %ebp, %eax
subl %esi, %edx
addl %edx, %eax
movl %eax, (%r8,%rcx,4)
addq $1, %rcx
cmpq %rdi, %rcx
jne .L5
.L3:
movq %r8, %rax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z13_getRangeMaskii, .-_Z13_getRangeMaskii
.globl _Z32__device_stub__Z6_erodePcS_iiiPiPcS_iiiPi
.type _Z32__device_stub__Z6_erodePcS_iiiPiPcS_iiiPi, @function
_Z32__device_stub__Z6_erodePcS_iiiPiPcS_iiiPi:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movl %r8d, 20(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6_erodePcS_iiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z32__device_stub__Z6_erodePcS_iiiPiPcS_iiiPi, .-_Z32__device_stub__Z6_erodePcS_iiiPiPcS_iiiPi
.globl _Z6_erodePcS_iiiPi
.type _Z6_erodePcS_iiiPi, @function
_Z6_erodePcS_iiiPi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6_erodePcS_iiiPiPcS_iiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z6_erodePcS_iiiPi, .-_Z6_erodePcS_iiiPi
.globl _Z9gpu_erodePcS_iii
.type _Z9gpu_erodePcS_iii, @function
_Z9gpu_erodePcS_iii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1144, %rsp
.cfi_def_cfa_offset 1200
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movl %edx, %r13d
movl %ecx, %r14d
movl %r8d, %r15d
movq %fs:40, %rax
movq %rax, 1128(%rsp)
xorl %eax, %eax
movl $1, 44(%rsp)
leaq 44(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 44(%rsp)
jle .L17
movl $0, %ebp
leaq 96(%rsp), %r12
.L18:
movl %ebp, %esi
movq %r12, %rdi
call cudaGetDeviceProperties_v2@PLT
movl 416(%rsp), %ebx
addl $1, %ebp
cmpl %ebp, 44(%rsp)
jg .L18
.L17:
movl %r13d, %eax
imull %r14d, %eax
leal -1(%rbx,%rax), %eax
cltd
idivl %ebx
movl %eax, 28(%rsp)
movslq %r13d, %rbp
movslq %r14d, %rax
imulq %rax, %rbp
leaq 48(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbp, %rdx
movq 8(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl %r13d, %esi
movl %r15d, %edi
call _Z13_getRangeMaskii
movq %rax, 8(%rsp)
movslq %r15d, %r12
imulq %r12, %r12
salq $2, %r12
leaq 64(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq 8(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl %ebx, 84(%rsp)
movl $1, 88(%rsp)
movl 28(%rsp), %eax
movl %eax, 72(%rsp)
movl $1, 76(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 84(%rsp), %rdx
movl $1, %ecx
movq 72(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movl $2, %ecx
movq %rbp, %rdx
movq 56(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 1128(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $1144, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movq 64(%rsp), %r9
movl %r15d, %r8d
movl %r14d, %ecx
movl %r13d, %edx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z32__device_stub__Z6_erodePcS_iiiPiPcS_iiiPi
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z9gpu_erodePcS_iii, .-_Z9gpu_erodePcS_iii
.globl _Z33__device_stub__Z7_dilatePcS_iiiPiPcS_iiiPi
.type _Z33__device_stub__Z7_dilatePcS_iiiPiPcS_iiiPi, @function
_Z33__device_stub__Z7_dilatePcS_iiiPiPcS_iiiPi:
.LFB2086:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movl %r8d, 20(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7_dilatePcS_iiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z33__device_stub__Z7_dilatePcS_iiiPiPcS_iiiPi, .-_Z33__device_stub__Z7_dilatePcS_iiiPiPcS_iiiPi
.globl _Z7_dilatePcS_iiiPi
.type _Z7_dilatePcS_iiiPi, @function
_Z7_dilatePcS_iiiPi:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z7_dilatePcS_iiiPiPcS_iiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z7_dilatePcS_iiiPi, .-_Z7_dilatePcS_iiiPi
.globl _Z10gpu_dilatePcS_iii
.type _Z10gpu_dilatePcS_iii, @function
_Z10gpu_dilatePcS_iii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1144, %rsp
.cfi_def_cfa_offset 1200
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movl %edx, %r13d
movl %ecx, %r14d
movl %r8d, %r15d
movq %fs:40, %rax
movq %rax, 1128(%rsp)
xorl %eax, %eax
movl $1, 44(%rsp)
leaq 44(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 44(%rsp)
jle .L34
movl $0, %ebp
leaq 96(%rsp), %r12
.L35:
movl %ebp, %esi
movq %r12, %rdi
call cudaGetDeviceProperties_v2@PLT
movl 416(%rsp), %ebx
addl $1, %ebp
cmpl %ebp, 44(%rsp)
jg .L35
.L34:
movl %r13d, %eax
imull %r14d, %eax
leal -1(%rbx,%rax), %eax
cltd
idivl %ebx
movl %eax, 28(%rsp)
movslq %r13d, %rbp
movslq %r14d, %rax
imulq %rax, %rbp
leaq 48(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbp, %rdx
movq 8(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl %r13d, %esi
movl %r15d, %edi
call _Z13_getRangeMaskii
movq %rax, 8(%rsp)
movslq %r15d, %r12
imulq %r12, %r12
salq $2, %r12
leaq 64(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq 8(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl %ebx, 84(%rsp)
movl $1, 88(%rsp)
movl 28(%rsp), %eax
movl %eax, 72(%rsp)
movl $1, 76(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 84(%rsp), %rdx
movl $1, %ecx
movq 72(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L40
.L36:
movl $2, %ecx
movq %rbp, %rdx
movq 56(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 1128(%rsp), %rax
subq %fs:40, %rax
jne .L41
addq $1144, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
movq 64(%rsp), %r9
movl %r15d, %r8d
movl %r14d, %ecx
movl %r13d, %edx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z33__device_stub__Z7_dilatePcS_iiiPiPcS_iiiPi
jmp .L36
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z10gpu_dilatePcS_iii, .-_Z10gpu_dilatePcS_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7_dilatePcS_iiiPi"
.LC1:
.string "_Z6_erodePcS_iiiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7_dilatePcS_iiiPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6_erodePcS_iiiPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "CudaImageMorphology.hip"
.globl _Z21__device_stub___erodePcS_iiiPi # -- Begin function _Z21__device_stub___erodePcS_iiiPi
.p2align 4, 0x90
.type _Z21__device_stub___erodePcS_iiiPi,@function
_Z21__device_stub___erodePcS_iiiPi: # @_Z21__device_stub___erodePcS_iiiPi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %r9, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6_erodePcS_iiiPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z21__device_stub___erodePcS_iiiPi, .Lfunc_end0-_Z21__device_stub___erodePcS_iiiPi
.cfi_endproc
# -- End function
.globl _Z22__device_stub___dilatePcS_iiiPi # -- Begin function _Z22__device_stub___dilatePcS_iiiPi
.p2align 4, 0x90
.type _Z22__device_stub___dilatePcS_iiiPi,@function
_Z22__device_stub___dilatePcS_iiiPi: # @_Z22__device_stub___dilatePcS_iiiPi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %r9, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7_dilatePcS_iiiPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z22__device_stub___dilatePcS_iiiPi, .Lfunc_end1-_Z22__device_stub___dilatePcS_iiiPi
.cfi_endproc
# -- End function
.globl _Z13_getRangeMaskii # -- Begin function _Z13_getRangeMaskii
.p2align 4, 0x90
.type _Z13_getRangeMaskii,@function
_Z13_getRangeMaskii: # @_Z13_getRangeMaskii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %esi, %ebx
movl %edi, %ebp
movslq %edi, %r14
movq %r14, %rdi
imulq %r14, %rdi
shlq $2, %rdi
callq malloc
movq %rax, %rcx
movl %r14d, %r9d
imull %r9d, %r9d
movl %r9d, %eax
shrl %eax
xorl %edx, %edx
idivl %r14d
movl %eax, %esi
movl %edx, %edi
xorl %r8d, %r8d
cmpl $1, %r9d
adcl $0, %r9d
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl %r8d, %eax
cltd
idivl %ebp
subl %edi, %eax
imull %ebx, %eax
subl %esi, %edx
addl %eax, %edx
movl %edx, (%rcx,%r8,4)
incq %r8
cmpq %r8, %r9
jne .LBB2_1
# %bb.2:
movq %rcx, %rax
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z13_getRangeMaskii, .Lfunc_end2-_Z13_getRangeMaskii
.cfi_endproc
# -- End function
.globl _Z9gpu_erodePcS_iii # -- Begin function _Z9gpu_erodePcS_iii
.p2align 4, 0x90
.type _Z9gpu_erodePcS_iii,@function
_Z9gpu_erodePcS_iii: # @_Z9gpu_erodePcS_iii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1672, %rsp # imm = 0x688
.cfi_def_cfa_offset 1728
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, %ebp
movl %ecx, %r13d
movl %edx, %r12d
movq %rsi, 64(%rsp) # 8-byte Spill
movq %rdi, %r15
movl $1, 4(%rsp)
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 4(%rsp)
jle .LBB3_1
# %bb.8: # %.lr.ph.preheader
xorl %ebx, %ebx
leaq 200(%rsp), %r14
.p2align 4, 0x90
.LBB3_9: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl %ebx, %esi
callq hipGetDevicePropertiesR0600
incl %ebx
cmpl 4(%rsp), %ebx
jl .LBB3_9
# %bb.2: # %._crit_edge
movl 520(%rsp), %ecx
jmp .LBB3_3
.LBB3_1:
# implicit-def: $ecx
.LBB3_3:
movl %r13d, %eax
imull %r12d, %eax
movq %rcx, 48(%rsp) # 8-byte Spill
leal (%rax,%rcx), %ebx
decl %ebx
movslq %r12d, %rax
movl %r13d, 32(%rsp) # 4-byte Spill
movslq %r13d, %r14
imulq %rax, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r15, %rsi
movq %r14, 56(%rsp) # 8-byte Spill
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movslq %ebp, %r15
movq %r15, %r14
imulq %r15, %r14
shlq $2, %r14
movq %r14, %rdi
callq malloc
movq %rax, %r13
movl %r15d, %r8d
imull %r8d, %r8d
movl %r8d, %eax
shrl %eax
xorl %edx, %edx
idivl %r15d
movl %eax, %ecx
movl %edx, %esi
xorl %edi, %edi
cmpl $1, %r8d
adcl $0, %r8d
.p2align 4, 0x90
.LBB3_4: # =>This Inner Loop Header: Depth=1
movl %edi, %eax
cltd
idivl %ebp
subl %esi, %eax
imull %r12d, %eax
subl %ecx, %edx
addl %eax, %edx
movl %edx, (%r13,%rdi,4)
incq %rdi
cmpq %rdi, %r8
jne .LBB3_4
# %bb.5: # %_Z13_getRangeMaskii.exit
movl %ebx, %eax
cltd
movq 48(%rsp), %r15 # 8-byte Reload
idivl %r15d
movl %eax, %ebx
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rbx
movl %r15d, %edx
orq %rax, %rdx
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_7
# %bb.6:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movl %r12d, 44(%rsp)
movl 32(%rsp), %eax # 4-byte Reload
movl %eax, 40(%rsp)
movl %ebp, 36(%rsp)
movq %rdx, 120(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 44(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rax
movq %rax, 168(%rsp)
leaq 36(%rsp), %rax
movq %rax, 176(%rsp)
leaq 120(%rsp), %rax
movq %rax, 184(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z6_erodePcS_iiiPi, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_7:
movq 16(%rsp), %rsi
movq 64(%rsp), %rdi # 8-byte Reload
movq 56(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %r13, %rdi
callq free
addq $1672, %rsp # imm = 0x688
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z9gpu_erodePcS_iii, .Lfunc_end3-_Z9gpu_erodePcS_iii
.cfi_endproc
# -- End function
.globl _Z10gpu_dilatePcS_iii # -- Begin function _Z10gpu_dilatePcS_iii
.p2align 4, 0x90
.type _Z10gpu_dilatePcS_iii,@function
_Z10gpu_dilatePcS_iii: # @_Z10gpu_dilatePcS_iii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1672, %rsp # imm = 0x688
.cfi_def_cfa_offset 1728
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, %ebp
movl %ecx, %r13d
movl %edx, %r12d
movq %rsi, 64(%rsp) # 8-byte Spill
movq %rdi, %r15
movl $1, 4(%rsp)
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 4(%rsp)
jle .LBB4_1
# %bb.8: # %.lr.ph.preheader
xorl %ebx, %ebx
leaq 200(%rsp), %r14
.p2align 4, 0x90
.LBB4_9: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl %ebx, %esi
callq hipGetDevicePropertiesR0600
incl %ebx
cmpl 4(%rsp), %ebx
jl .LBB4_9
# %bb.2: # %._crit_edge
movl 520(%rsp), %ecx
jmp .LBB4_3
.LBB4_1:
# implicit-def: $ecx
.LBB4_3:
movl %r13d, %eax
imull %r12d, %eax
movq %rcx, 48(%rsp) # 8-byte Spill
leal (%rax,%rcx), %ebx
decl %ebx
movslq %r12d, %rax
movl %r13d, 32(%rsp) # 4-byte Spill
movslq %r13d, %r14
imulq %rax, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r15, %rsi
movq %r14, 56(%rsp) # 8-byte Spill
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movslq %ebp, %r15
movq %r15, %r14
imulq %r15, %r14
shlq $2, %r14
movq %r14, %rdi
callq malloc
movq %rax, %r13
movl %r15d, %r8d
imull %r8d, %r8d
movl %r8d, %eax
shrl %eax
xorl %edx, %edx
idivl %r15d
movl %eax, %ecx
movl %edx, %esi
xorl %edi, %edi
cmpl $1, %r8d
adcl $0, %r8d
.p2align 4, 0x90
.LBB4_4: # =>This Inner Loop Header: Depth=1
movl %edi, %eax
cltd
idivl %ebp
subl %esi, %eax
imull %r12d, %eax
subl %ecx, %edx
addl %eax, %edx
movl %edx, (%r13,%rdi,4)
incq %rdi
cmpq %rdi, %r8
jne .LBB4_4
# %bb.5: # %_Z13_getRangeMaskii.exit
movl %ebx, %eax
cltd
movq 48(%rsp), %r15 # 8-byte Reload
idivl %r15d
movl %eax, %ebx
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rbx
movl %r15d, %edx
orq %rax, %rdx
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_7
# %bb.6:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movl %r12d, 44(%rsp)
movl 32(%rsp), %eax # 4-byte Reload
movl %eax, 40(%rsp)
movl %ebp, 36(%rsp)
movq %rdx, 120(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 44(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rax
movq %rax, 168(%rsp)
leaq 36(%rsp), %rax
movq %rax, 176(%rsp)
leaq 120(%rsp), %rax
movq %rax, 184(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z7_dilatePcS_iiiPi, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_7:
movq 16(%rsp), %rsi
movq 64(%rsp), %rdi # 8-byte Reload
movq 56(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %r13, %rdi
callq free
addq $1672, %rsp # imm = 0x688
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z10gpu_dilatePcS_iii, .Lfunc_end4-_Z10gpu_dilatePcS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6_erodePcS_iiiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7_dilatePcS_iiiPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6_erodePcS_iiiPi,@object # @_Z6_erodePcS_iiiPi
.section .rodata,"a",@progbits
.globl _Z6_erodePcS_iiiPi
.p2align 3, 0x0
_Z6_erodePcS_iiiPi:
.quad _Z21__device_stub___erodePcS_iiiPi
.size _Z6_erodePcS_iiiPi, 8
.type _Z7_dilatePcS_iiiPi,@object # @_Z7_dilatePcS_iiiPi
.globl _Z7_dilatePcS_iiiPi
.p2align 3, 0x0
_Z7_dilatePcS_iiiPi:
.quad _Z22__device_stub___dilatePcS_iiiPi
.size _Z7_dilatePcS_iiiPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6_erodePcS_iiiPi"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7_dilatePcS_iiiPi"
.size .L__unnamed_2, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub___erodePcS_iiiPi
.addrsig_sym _Z22__device_stub___dilatePcS_iiiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6_erodePcS_iiiPi
.addrsig_sym _Z7_dilatePcS_iiiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
const int W = 40;
const int H = 12;
__global__ void draw(char
*odata)
{
const char tmp_str[H][W] =
{ ":::::::::::::::::::::::::::::::::::::::",
": :",
": :",
": :",
": :",
": #### <| :",
": ###### | :",
": ######## | :",
": ########## | :",
": ############ | :",
": ############## # :",
":::::::::::::::::::::::::::::::::::::::" };
const int x = blockIdx.x * blockDim.x + threadIdx.x;
const int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x < W && y < H) {
char c;
if (x == W - 1 && y != H - 1)
c = '\n';
else
c = tmp_str[y][x];
odata[y * W + x] = c;
}
}
int main(void)
{
char *h_data, *d_data;
const int strlen = W*H;
size_t strsize = strlen * sizeof(char);
h_data = (char *)malloc(strsize);
memset(h_data, 0, strlen);
cudaMalloc((void **)&d_data, strsize);
cudaMemcpy(d_data, h_data, strsize, cudaMemcpyHostToDevice);
dim3 blocksize = dim3(16, 12, 1);
dim3 nblock = dim3((W - 1) / 16 + 1, (H - 1) / 12 + 1, 1);
draw <<<nblock, blocksize>>>(d_data);
cudaMemcpy(h_data, d_data, strlen, cudaMemcpyDeviceToHost);
printf("%s", h_data);
free(h_data);
cudaFree(d_data);
} | code for sm_80
Function : _Z4drawPc
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc600078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*0020*/ HFMA2.MMA R6, -RZ, RZ, 0.008056640625, 0.0082550048828125 ; /* 0x2020203aff067435 */
/* 0x000fe200000001ff */
/*0030*/ IADD3 R1, R1, -0x1e0, RZ ; /* 0xfffffe2001017810 */
/* 0x000fe20007ffe0ff */
/*0040*/ HFMA2.MMA R10, -RZ, RZ, 0.008056640625, 0.008056640625 ; /* 0x20202020ff0a7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R24, SR_TID.Y ; /* 0x0000000000187919 */
/* 0x000e220000002200 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3a3a3a ; /* 0x003a3a3aff057424 */
/* 0x000fe200078e00ff */
/*0070*/ MOV R8, 0x20202020 ; /* 0x2020202000087802 */
/* 0x000fe20000000f00 */
/*0080*/ IMAD.MOV.U32 R7, RZ, RZ, 0x20202020 ; /* 0x20202020ff077424 */
/* 0x000fe200078e00ff */
/*0090*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e620000002500 */
/*00a0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x3a3a3a3a ; /* 0x3a3a3a3aff047424 */
/* 0x000fe200078e00ff */
/*00b0*/ HFMA2.MMA R16, -RZ, RZ, 0.008056640625, 0.008056640625 ; /* 0x20202020ff107435 */
/* 0x000fe200000001ff */
/*00c0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x20202020 ; /* 0x20202020ff097424 */
/* 0x000fe200078e00ff */
/*00d0*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*00e0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x20202020 ; /* 0x20202020ff0b7424 */
/* 0x000fe200078e00ff */
/*00f0*/ HFMA2.MMA R20, -RZ, RZ, 0.008056640625, 0.008056640625 ; /* 0x20202020ff147435 */
/* 0x000fe200000001ff */
/*0100*/ IMAD.MOV.U32 R17, RZ, RZ, 0x20202020 ; /* 0x20202020ff117424 */
/* 0x000fe200078e00ff */
/*0110*/ HFMA2.MMA R13, -RZ, RZ, 0.008056640625, 0.008056640625 ; /* 0x20202020ff0d7435 */
/* 0x000fe200000001ff */
/*0120*/ MOV R18, 0x20202020 ; /* 0x2020202000127802 */
/* 0x000fe20000000f00 */
/*0130*/ IMAD.MOV.U32 R19, RZ, RZ, 0x20202020 ; /* 0x20202020ff137424 */
/* 0x000fe200078e00ff */
/*0140*/ MOV R22, 0x20202020 ; /* 0x2020202000167802 */
/* 0x000fe20000000f00 */
/*0150*/ IMAD.MOV.U32 R21, RZ, RZ, 0x20202020 ; /* 0x20202020ff157424 */
/* 0x000fe200078e00ff */
/*0160*/ MOV R15, 0x3a2020 ; /* 0x003a2020000f7802 */
/* 0x000fe20000000f00 */
/*0170*/ IMAD.MOV.U32 R23, RZ, RZ, 0x3a2020 ; /* 0x003a2020ff177424 */
/* 0x000fe200078e00ff */
/*0180*/ STL.128 [R1+0x20], R4 ; /* 0x0000200401007387 */
/* 0x0005e20000100c00 */
/*0190*/ IMAD.MOV.U32 R12, RZ, RZ, 0x20202020 ; /* 0x20202020ff0c7424 */
/* 0x000fe200078e00ff */
/*01a0*/ HFMA2.MMA R26, -RZ, RZ, 0.7783203125, 0.7783203125 ; /* 0x3a3a3a3aff1a7435 */
/* 0x000fe200000001ff */
/*01b0*/ IMAD.MOV.U32 R14, RZ, RZ, 0x20202020 ; /* 0x20202020ff0e7424 */
/* 0x000fe200078e00ff */
/*01c0*/ STL.128 [R1+0x30], R8 ; /* 0x0000300801007387 */
/* 0x000fe20000100c00 */
/*01d0*/ IMAD R3, R3, c[0x0][0x4], R24 ; /* 0x0000010003037a24 */
/* 0x001fe200078e0218 */
/*01e0*/ MOV R25, 0x3a2023 ; /* 0x003a202300197802 */
/* 0x000fe20000000f00 */
/*01f0*/ IMAD.MOV.U32 R24, RZ, RZ, 0x20202020 ; /* 0x20202020ff187424 */
/* 0x000fe200078e00ff */
/*0200*/ STL.128 [R1+0x60], R8 ; /* 0x0000600801007387 */
/* 0x000fe20000100c00 */
/*0210*/ IMAD.MOV.U32 R27, RZ, RZ, 0x3a3a3a3a ; /* 0x3a3a3a3aff1b7424 */
/* 0x000fe200078e00ff */
/*0220*/ ISETP.GT.AND P0, PT, R3, 0xb, PT ; /* 0x0000000b0300780c */
/* 0x000fc40003f04270 */
/*0230*/ STL.128 [R1+0xb0], R8 ; /* 0x0000b00801007387 */
/* 0x0001e20000100c00 */
/*0240*/ IMAD R2, R2, c[0x0][0x0], R0 ; /* 0x0000000002027a24 */
/* 0x002fe200078e0200 */
/*0250*/ HFMA2.MMA R6, -RZ, RZ, 0.008056640625, 0.008056640625 ; /* 0x20202020ff067435 */
/* 0x004fe400000001ff */
/*0260*/ STL.128 [R1+0x80], R16 ; /* 0x0000801001007387 */
/* 0x0003e20000100c00 */
/*0270*/ MOV R4, 0x2020203a ; /* 0x2020203a00047802 */
/* 0x000fe20000000f00 */
/*0280*/ IMAD.MOV.U32 R5, RZ, RZ, 0x20202020 ; /* 0x20202020ff057424 */
/* 0x000fe200078e00ff */
/*0290*/ ISETP.GT.OR P0, PT, R2, 0x27, P0 ; /* 0x000000270200780c */
/* 0x000fe20000704670 */
/*02a0*/ STL.128 [R1+0x90], R20 ; /* 0x0000901401007387 */
/* 0x0005e80000100c00 */
/*02b0*/ STL.128 [R1+0x40], R12 ; /* 0x0000400c01007387 */
/* 0x0007e20000100c00 */
/*02c0*/ HFMA2.MMA R9, -RZ, RZ, 3.45706939697265625e-06, 0.008758544921875 ; /* 0x003a207cff097435 */
/* 0x001fe200000001ff */
/*02d0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x2020203a ; /* 0x2020203aff0a7424 */
/* 0x000fc400078e00ff */
/*02e0*/ STL.128 [R1+0x50], R4 ; /* 0x0000500401007387 */
/* 0x000fe20000100c00 */
/*02f0*/ HFMA2.MMA R18, -RZ, RZ, 0.01393890380859375, 0.008056640625 ; /* 0x23232020ff127435 */
/* 0x002fe200000001ff */
/*0300*/ IMAD.MOV.U32 R19, RZ, RZ, 0x20202323 ; /* 0x20202323ff137424 */
/* 0x000fe400078e00ff */
/*0310*/ STL.128 [R1+0xa0], R4 ; /* 0x0000a00401007387 */
/* 0x000fe20000100c00 */
/*0320*/ MOV R22, 0x3c202020 ; /* 0x3c20202000167802 */
/* 0x004fe20000000f00 */
/*0330*/ IMAD.MOV.U32 R23, RZ, RZ, 0x3a207c ; /* 0x003a207cff177424 */
/* 0x000fe400078e00ff */
/*0340*/ STL.128 [R1+0xf0], R4 ; /* 0x0000f00401007387 */
/* 0x0001e20000100c00 */
/*0350*/ IMAD.MOV.U32 R13, RZ, RZ, 0x3a2020 ; /* 0x003a2020ff0d7424 */
/* 0x008fe200078e00ff */
/*0360*/ MOV R14, 0x2020203a ; /* 0x2020203a000e7802 */
/* 0x000fe20000000f00 */
/*0370*/ IMAD.MOV.U32 R15, RZ, RZ, 0x20202020 ; /* 0x20202020ff0f7424 */
/* 0x000fe200078e00ff */
/*0380*/ STL.128 [R1+0xe0], R20 ; /* 0x0000e01401007387 */
/* 0x0003e80000100c00 */
/*0390*/ STL.128 [R1+0x110], R8 ; /* 0x0001100801007387 */
/* 0x0005e80000100c00 */
/*03a0*/ STL.128 [R1+0x70], R12 ; /* 0x0000700c01007387 */
/* 0x000fe20000100c00 */
/*03b0*/ HFMA2.MMA R6, -RZ, RZ, 0.008056640625, 0.0082550048828125 ; /* 0x2020203aff067435 */
/* 0x001fc600000001ff */
/*03c0*/ STL.128 [R1+0xc0], R12 ; /* 0x0000c00c01007387 */
/* 0x0001e20000100c00 */
/*03d0*/ MOV R4, 0x20202020 ; /* 0x2020202000047802 */
/* 0x000fe20000000f00 */
/*03e0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3a207c ; /* 0x003a207cff057424 */
/* 0x000fe200078e00ff */
/*03f0*/ HFMA2.MMA R22, -RZ, RZ, 0.008056640625, 0.008056640625 ; /* 0x20202020ff167435 */
/* 0x002fe200000001ff */
/*0400*/ STL.128 [R1+0xd0], R16 ; /* 0x0000d01001007387 */
/* 0x0003e20000100c00 */
/*0410*/ IMAD.MOV.U32 R20, RZ, RZ, 0x2020203a ; /* 0x2020203aff147424 */
/* 0x000fe200078e00ff */
/*0420*/ HFMA2.MMA R11, -RZ, RZ, 0.008056640625, 0.01393890380859375 ; /* 0x20202323ff0b7435 */
/* 0x004fe200000001ff */
/*0430*/ IMAD.MOV.U32 R23, RZ, RZ, 0x23232323 ; /* 0x23232323ff177424 */
/* 0x000fe200078e00ff */
/*0440*/ MOV R9, 0x23232323 ; /* 0x2323232300097802 */
/* 0x000fe20000000f00 */
/*0450*/ IMAD.MOV.U32 R8, RZ, RZ, 0x23232020 ; /* 0x23232020ff087424 */
/* 0x000fe200078e00ff */
/*0460*/ STL.128 [R1+0x160], R4 ; /* 0x0001600401007387 */
/* 0x0005e20000100c00 */
/*0470*/ IMAD.MOV.U32 R10, RZ, RZ, 0x23232323 ; /* 0x23232323ff0a7424 */
/* 0x000fe200078e00ff */
/*0480*/ HFMA2.MMA R15, -RZ, RZ, 0.008056640625, 0.01393890380859375 ; /* 0x20202323ff0f7435 */
/* 0x001fe200000001ff */
/*0490*/ MOV R13, 0x23232020 ; /* 0x23232020000d7802 */
/* 0x000fe20000000f00 */
/*04a0*/ IMAD.MOV.U32 R14, RZ, RZ, 0x23232323 ; /* 0x23232323ff0e7424 */
/* 0x000fe200078e00ff */
/*04b0*/ STL.128 [R1+0x140], R20 ; /* 0x0001401401007387 */
/* 0x0001e20000100c00 */
/*04c0*/ IMAD.MOV.U32 R18, RZ, RZ, 0x20202020 ; /* 0x20202020ff127424 */
/* 0x002fe200078e00ff */
/*04d0*/ MOV R19, 0x3a207c ; /* 0x003a207c00137802 */
/* 0x000fc40000000f00 */
/*04e0*/ STL.128 [R1+0x170], R8 ; /* 0x0001700801007387 */
/* 0x0003e80000100c00 */
/*04f0*/ STL.128 [R1+0x130], R16 ; /* 0x0001301001007387 */
/* 0x0007e20000100c00 */
/*0500*/ HFMA2.MMA R6, -RZ, RZ, 0.7783203125, 0.7783203125 ; /* 0x3a3a3a3aff067435 */
/* 0x004fe200000001ff */
/*0510*/ MOV R4, 0x3a3a3a3a ; /* 0x3a3a3a3a00047802 */
/* 0x000fe20000000f00 */
/*0520*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3a3a3a3a ; /* 0x3a3a3a3aff057424 */
/* 0x000fe200078e00ff */
/*0530*/ STL.128 [R1+0x120], R12 ; /* 0x0001200c01007387 */
/* 0x0005e20000100c00 */
/*0540*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3a3a3a3a ; /* 0x3a3a3a3aff077424 */
/* 0x000fe200078e00ff */
/*0550*/ HFMA2.MMA R21, -RZ, RZ, 0.008056640625, 0.01393890380859375 ; /* 0x20202323ff157435 */
/* 0x001fe200000001ff */
/*0560*/ IMAD.MOV.U32 R20, RZ, RZ, 0x23232323 ; /* 0x23232323ff147424 */
/* 0x000fe200078e00ff */
/*0570*/ STL.128 [R1+0x1b0], R24 ; /* 0x0001b01801007387 */
/* 0x0001e20000100c00 */
/*0580*/ IMAD.MOV.U32 R23, RZ, RZ, 0x20202020 ; /* 0x20202020ff177424 */
/* 0x000fe200078e00ff */
/*0590*/ HFMA2.MMA R10, -RZ, RZ, 0.7783203125, 0.7783203125 ; /* 0x3a3a3a3aff0a7435 */
/* 0x002fe200000001ff */
/*05a0*/ MOV R8, 0x3a3a3a3a ; /* 0x3a3a3a3a00087802 */
/* 0x000fe20000000f00 */
/*05b0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3a3a3a3a ; /* 0x3a3a3a3aff097424 */
/* 0x000fe200078e00ff */
/*05c0*/ STL.128 [R1], R4 ; /* 0x0000000401007387 */
/* 0x0001e20000100c00 */
/*05d0*/ HFMA2.MMA R16, -RZ, RZ, 0.008056640625, 0.0082550048828125 ; /* 0x2020203aff107435 */
/* 0x008fe200000001ff */
/*05e0*/ IMAD.MOV.U32 R18, RZ, RZ, 0x23232323 ; /* 0x23232323ff127424 */
/* 0x000fe200078e00ff */
/*05f0*/ MOV R19, 0x23232323 ; /* 0x2323232300137802 */
/* 0x000fe20000000f00 */
/*0600*/ IMAD.MOV.U32 R11, RZ, RZ, 0x3a3a3a ; /* 0x003a3a3aff0b7424 */
/* 0x000fe200078e00ff */
/*0610*/ MOV R14, 0x20202020 ; /* 0x20202020000e7802 */
/* 0x004fe20000000f00 */
/*0620*/ IMAD.MOV.U32 R13, RZ, RZ, 0x20202020 ; /* 0x20202020ff0d7424 */
/* 0x000fe200078e00ff */
/*0630*/ STL.128 [R1+0x100], R20 ; /* 0x0001001401007387 */
/* 0x0001e20000100c00 */
/*0640*/ IMAD.MOV.U32 R15, RZ, RZ, 0x3a207c ; /* 0x003a207cff0f7424 */
/* 0x000fc600078e00ff */
/*0650*/ STL.128 [R1+0x190], R16 ; /* 0x0001901001007387 */
/* 0x0001e80000100c00 */
/*0660*/ STL.128 [R1+0x180], R12 ; /* 0x0001800c01007387 */
/* 0x0001e80000100c00 */
/*0670*/ STL.128 [R1+0x150], R20 ; /* 0x0001501401007387 */
/* 0x0001e80000100c00 */
/*0680*/ STL.128 [R1+0x1a0], R20 ; /* 0x0001a01401007387 */
/* 0x0001e80000100c00 */
/*0690*/ STL.128 [R1+0x10], R4 ; /* 0x0000100401007387 */
/* 0x0001e80000100c00 */
/*06a0*/ STL.128 [R1+0x1c0], R4 ; /* 0x0001c00401007387 */
/* 0x0001e80000100c00 */
/*06b0*/ STL.128 [R1+0x1d0], R8 ; /* 0x0001d00801007387 */
/* 0x0001e20000100c00 */
/*06c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*06d0*/ ISETP.NE.AND P0, PT, R3, 0xb, PT ; /* 0x0000000b0300780c */
/* 0x000fe20003f05270 */
/*06e0*/ IMAD.MOV.U32 R5, RZ, RZ, 0xa ; /* 0x0000000aff057424 */
/* 0x001fe200078e00ff */
/*06f0*/ MOV R0, R1 ; /* 0x0000000100007202 */
/* 0x000fc40000000f00 */
/*0700*/ ISETP.EQ.AND P0, PT, R2, 0x27, P0 ; /* 0x000000270200780c */
/* 0x000fda0000702270 */
/*0710*/ @!P0 IMAD R4, R3, 0x28, R0.reuse ; /* 0x0000002803048824 */
/* 0x100fe200078e0200 */
/*0720*/ PRMT R0, R5, 0x7610, R0 ; /* 0x0000761005007816 */
/* 0x000fc80000000000 */
/*0730*/ @!P0 IADD3 R4, R2, R4, RZ ; /* 0x0000000402048210 */
/* 0x000fca0007ffe0ff */
/*0740*/ @!P0 LDL.U8 R0, [R4] ; /* 0x0000000004008983 */
/* 0x000ea20000100000 */
/*0750*/ IMAD R3, R3, 0x28, R2 ; /* 0x0000002803037824 */
/* 0x000fe200078e0202 */
/*0760*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0770*/ IADD3 R2, P0, R3, c[0x0][0x160], RZ ; /* 0x0000580003027a10 */
/* 0x000fc80007f1e0ff */
/*0780*/ LEA.HI.X.SX32 R3, R3, c[0x0][0x164], 0x1, P0 ; /* 0x0000590003037a11 */
/* 0x000fca00000f0eff */
/*0790*/ STG.E.U8 [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x004fe2000c101104 */
/*07a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07b0*/ BRA 0x7b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
const int W = 40;
const int H = 12;
__global__ void draw(char
*odata)
{
const char tmp_str[H][W] =
{ ":::::::::::::::::::::::::::::::::::::::",
": :",
": :",
": :",
": :",
": #### <| :",
": ###### | :",
": ######## | :",
": ########## | :",
": ############ | :",
": ############## # :",
":::::::::::::::::::::::::::::::::::::::" };
const int x = blockIdx.x * blockDim.x + threadIdx.x;
const int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x < W && y < H) {
char c;
if (x == W - 1 && y != H - 1)
c = '\n';
else
c = tmp_str[y][x];
odata[y * W + x] = c;
}
}
int main(void)
{
char *h_data, *d_data;
const int strlen = W*H;
size_t strsize = strlen * sizeof(char);
h_data = (char *)malloc(strsize);
memset(h_data, 0, strlen);
cudaMalloc((void **)&d_data, strsize);
cudaMemcpy(d_data, h_data, strsize, cudaMemcpyHostToDevice);
dim3 blocksize = dim3(16, 12, 1);
dim3 nblock = dim3((W - 1) / 16 + 1, (H - 1) / 12 + 1, 1);
draw <<<nblock, blocksize>>>(d_data);
cudaMemcpy(h_data, d_data, strlen, cudaMemcpyDeviceToHost);
printf("%s", h_data);
free(h_data);
cudaFree(d_data);
} | .file "tmpxft_00041820_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z4drawPcPc
.type _Z23__device_stub__Z4drawPcPc, @function
_Z23__device_stub__Z4drawPcPc:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4drawPc(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z23__device_stub__Z4drawPcPc, .-_Z23__device_stub__Z4drawPcPc
.globl _Z4drawPc
.type _Z4drawPc, @function
_Z4drawPc:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z4drawPcPc
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z4drawPc, .-_Z4drawPc
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $480, %edi
call malloc@PLT
movq %rax, %rbx
movl $60, %ecx
movl $0, %eax
movq %rbx, %rdi
rep stosq
leaq 8(%rsp), %rdi
movl $480, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $480, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 16(%rsp)
movl $12, 20(%rsp)
movl $3, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movl $480, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z23__device_stub__Z4drawPcPc
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z4drawPc"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z4drawPc(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
const int W = 40;
const int H = 12;
__global__ void draw(char
*odata)
{
const char tmp_str[H][W] =
{ ":::::::::::::::::::::::::::::::::::::::",
": :",
": :",
": :",
": :",
": #### <| :",
": ###### | :",
": ######## | :",
": ########## | :",
": ############ | :",
": ############## # :",
":::::::::::::::::::::::::::::::::::::::" };
const int x = blockIdx.x * blockDim.x + threadIdx.x;
const int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x < W && y < H) {
char c;
if (x == W - 1 && y != H - 1)
c = '\n';
else
c = tmp_str[y][x];
odata[y * W + x] = c;
}
}
int main(void)
{
char *h_data, *d_data;
const int strlen = W*H;
size_t strsize = strlen * sizeof(char);
h_data = (char *)malloc(strsize);
memset(h_data, 0, strlen);
cudaMalloc((void **)&d_data, strsize);
cudaMemcpy(d_data, h_data, strsize, cudaMemcpyHostToDevice);
dim3 blocksize = dim3(16, 12, 1);
dim3 nblock = dim3((W - 1) / 16 + 1, (H - 1) / 12 + 1, 1);
draw <<<nblock, blocksize>>>(d_data);
cudaMemcpy(h_data, d_data, strlen, cudaMemcpyDeviceToHost);
printf("%s", h_data);
free(h_data);
cudaFree(d_data);
} | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
const int W = 40;
const int H = 12;
__global__ void draw(char
*odata)
{
const char tmp_str[H][W] =
{ ":::::::::::::::::::::::::::::::::::::::",
": :",
": :",
": :",
": :",
": #### <| :",
": ###### | :",
": ######## | :",
": ########## | :",
": ############ | :",
": ############## # :",
":::::::::::::::::::::::::::::::::::::::" };
const int x = blockIdx.x * blockDim.x + threadIdx.x;
const int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x < W && y < H) {
char c;
if (x == W - 1 && y != H - 1)
c = '\n';
else
c = tmp_str[y][x];
odata[y * W + x] = c;
}
}
int main(void)
{
char *h_data, *d_data;
const int strlen = W*H;
size_t strsize = strlen * sizeof(char);
h_data = (char *)malloc(strsize);
memset(h_data, 0, strlen);
hipMalloc((void **)&d_data, strsize);
hipMemcpy(d_data, h_data, strsize, hipMemcpyHostToDevice);
dim3 blocksize = dim3(16, 12, 1);
dim3 nblock = dim3((W - 1) / 16 + 1, (H - 1) / 12 + 1, 1);
draw <<<nblock, blocksize>>>(d_data);
hipMemcpy(h_data, d_data, strlen, hipMemcpyDeviceToHost);
printf("%s", h_data);
free(h_data);
hipFree(d_data);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
const int W = 40;
const int H = 12;
__global__ void draw(char
*odata)
{
const char tmp_str[H][W] =
{ ":::::::::::::::::::::::::::::::::::::::",
": :",
": :",
": :",
": :",
": #### <| :",
": ###### | :",
": ######## | :",
": ########## | :",
": ############ | :",
": ############## # :",
":::::::::::::::::::::::::::::::::::::::" };
const int x = blockIdx.x * blockDim.x + threadIdx.x;
const int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x < W && y < H) {
char c;
if (x == W - 1 && y != H - 1)
c = '\n';
else
c = tmp_str[y][x];
odata[y * W + x] = c;
}
}
int main(void)
{
char *h_data, *d_data;
const int strlen = W*H;
size_t strsize = strlen * sizeof(char);
h_data = (char *)malloc(strsize);
memset(h_data, 0, strlen);
hipMalloc((void **)&d_data, strsize);
hipMemcpy(d_data, h_data, strsize, hipMemcpyHostToDevice);
dim3 blocksize = dim3(16, 12, 1);
dim3 nblock = dim3((W - 1) / 16 + 1, (H - 1) / 12 + 1, 1);
draw <<<nblock, blocksize>>>(d_data);
hipMemcpy(h_data, d_data, strlen, hipMemcpyDeviceToHost);
printf("%s", h_data);
free(h_data);
hipFree(d_data);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4drawPc
.globl _Z4drawPc
.p2align 8
.type _Z4drawPc,@function
_Z4drawPc:
s_load_b32 s2, s[0:1], 0x14
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[2:3], null, s15, s2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, 40, v0
v_cmp_gt_i32_e64 s2, 12, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_4
v_cmp_ne_u32_e32 vcc_lo, 39, v0
v_cmp_eq_u32_e64 s2, 11, v2
v_mov_b32_e32 v1, 10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s3, vcc_lo, s2
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_3
v_ashrrev_i32_e32 v1, 31, v0
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, __const._Z4drawPc.tmp_str@rel32@lo+4
s_addc_u32 s5, s5, __const._Z4drawPc.tmp_str@rel32@hi+12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_i64_i32 v[3:4], null, v2, 40, v[0:1]
v_add_co_u32 v3, vcc_lo, v3, s4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_u8 v1, v[3:4], off
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v2, 40, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v0, 31, v3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v0, vcc_lo
global_store_b8 v[2:3], v1, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4drawPc
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4drawPc, .Lfunc_end0-_Z4drawPc
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __const._Z4drawPc.tmp_str,@object
.section .rodata,"a",@progbits
.p2align 4, 0x0
__const._Z4drawPc.tmp_str:
.asciz ":::::::::::::::::::::::::::::::::::::::"
.asciz ": :"
.asciz ": :"
.asciz ": :"
.asciz ": :"
.asciz ": #### <| :"
.asciz ": ###### | :"
.asciz ": ######## | :"
.asciz ": ########## | :"
.asciz ": ############ | :"
.asciz ": ############## # :"
.asciz ":::::::::::::::::::::::::::::::::::::::"
.size __const._Z4drawPc.tmp_str, 480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4drawPc
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4drawPc.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
const int W = 40;
const int H = 12;
__global__ void draw(char
*odata)
{
const char tmp_str[H][W] =
{ ":::::::::::::::::::::::::::::::::::::::",
": :",
": :",
": :",
": :",
": #### <| :",
": ###### | :",
": ######## | :",
": ########## | :",
": ############ | :",
": ############## # :",
":::::::::::::::::::::::::::::::::::::::" };
const int x = blockIdx.x * blockDim.x + threadIdx.x;
const int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x < W && y < H) {
char c;
if (x == W - 1 && y != H - 1)
c = '\n';
else
c = tmp_str[y][x];
odata[y * W + x] = c;
}
}
int main(void)
{
char *h_data, *d_data;
const int strlen = W*H;
size_t strsize = strlen * sizeof(char);
h_data = (char *)malloc(strsize);
memset(h_data, 0, strlen);
hipMalloc((void **)&d_data, strsize);
hipMemcpy(d_data, h_data, strsize, hipMemcpyHostToDevice);
dim3 blocksize = dim3(16, 12, 1);
dim3 nblock = dim3((W - 1) / 16 + 1, (H - 1) / 12 + 1, 1);
draw <<<nblock, blocksize>>>(d_data);
hipMemcpy(h_data, d_data, strlen, hipMemcpyDeviceToHost);
printf("%s", h_data);
free(h_data);
hipFree(d_data);
} | .text
.file "main.hip"
.globl _Z19__device_stub__drawPc # -- Begin function _Z19__device_stub__drawPc
.p2align 4, 0x90
.type _Z19__device_stub__drawPc,@function
_Z19__device_stub__drawPc: # @_Z19__device_stub__drawPc
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z4drawPc, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z19__device_stub__drawPc, .Lfunc_end0-_Z19__device_stub__drawPc
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $80, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -16
movl $480, %edi # imm = 0x1E0
callq malloc
movq %rax, %rbx
movl $480, %edx # imm = 0x1E0
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
leaq 8(%rsp), %rdi
movl $480, %esi # imm = 0x1E0
callq hipMalloc
movq 8(%rsp), %rdi
movl $480, %edx # imm = 0x1E0
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967299, %rdi # imm = 0x100000003
movabsq $51539607568, %rdx # imm = 0xC00000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z4drawPc, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movl $480, %edx # imm = 0x1E0
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $80, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4drawPc, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4drawPc,@object # @_Z4drawPc
.section .rodata,"a",@progbits
.globl _Z4drawPc
.p2align 3, 0x0
_Z4drawPc:
.quad _Z19__device_stub__drawPc
.size _Z4drawPc, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%s"
.size .L.str, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4drawPc"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__drawPc
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4drawPc
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4drawPc
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc600078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*0020*/ HFMA2.MMA R6, -RZ, RZ, 0.008056640625, 0.0082550048828125 ; /* 0x2020203aff067435 */
/* 0x000fe200000001ff */
/*0030*/ IADD3 R1, R1, -0x1e0, RZ ; /* 0xfffffe2001017810 */
/* 0x000fe20007ffe0ff */
/*0040*/ HFMA2.MMA R10, -RZ, RZ, 0.008056640625, 0.008056640625 ; /* 0x20202020ff0a7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R24, SR_TID.Y ; /* 0x0000000000187919 */
/* 0x000e220000002200 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3a3a3a ; /* 0x003a3a3aff057424 */
/* 0x000fe200078e00ff */
/*0070*/ MOV R8, 0x20202020 ; /* 0x2020202000087802 */
/* 0x000fe20000000f00 */
/*0080*/ IMAD.MOV.U32 R7, RZ, RZ, 0x20202020 ; /* 0x20202020ff077424 */
/* 0x000fe200078e00ff */
/*0090*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e620000002500 */
/*00a0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x3a3a3a3a ; /* 0x3a3a3a3aff047424 */
/* 0x000fe200078e00ff */
/*00b0*/ HFMA2.MMA R16, -RZ, RZ, 0.008056640625, 0.008056640625 ; /* 0x20202020ff107435 */
/* 0x000fe200000001ff */
/*00c0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x20202020 ; /* 0x20202020ff097424 */
/* 0x000fe200078e00ff */
/*00d0*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*00e0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x20202020 ; /* 0x20202020ff0b7424 */
/* 0x000fe200078e00ff */
/*00f0*/ HFMA2.MMA R20, -RZ, RZ, 0.008056640625, 0.008056640625 ; /* 0x20202020ff147435 */
/* 0x000fe200000001ff */
/*0100*/ IMAD.MOV.U32 R17, RZ, RZ, 0x20202020 ; /* 0x20202020ff117424 */
/* 0x000fe200078e00ff */
/*0110*/ HFMA2.MMA R13, -RZ, RZ, 0.008056640625, 0.008056640625 ; /* 0x20202020ff0d7435 */
/* 0x000fe200000001ff */
/*0120*/ MOV R18, 0x20202020 ; /* 0x2020202000127802 */
/* 0x000fe20000000f00 */
/*0130*/ IMAD.MOV.U32 R19, RZ, RZ, 0x20202020 ; /* 0x20202020ff137424 */
/* 0x000fe200078e00ff */
/*0140*/ MOV R22, 0x20202020 ; /* 0x2020202000167802 */
/* 0x000fe20000000f00 */
/*0150*/ IMAD.MOV.U32 R21, RZ, RZ, 0x20202020 ; /* 0x20202020ff157424 */
/* 0x000fe200078e00ff */
/*0160*/ MOV R15, 0x3a2020 ; /* 0x003a2020000f7802 */
/* 0x000fe20000000f00 */
/*0170*/ IMAD.MOV.U32 R23, RZ, RZ, 0x3a2020 ; /* 0x003a2020ff177424 */
/* 0x000fe200078e00ff */
/*0180*/ STL.128 [R1+0x20], R4 ; /* 0x0000200401007387 */
/* 0x0005e20000100c00 */
/*0190*/ IMAD.MOV.U32 R12, RZ, RZ, 0x20202020 ; /* 0x20202020ff0c7424 */
/* 0x000fe200078e00ff */
/*01a0*/ HFMA2.MMA R26, -RZ, RZ, 0.7783203125, 0.7783203125 ; /* 0x3a3a3a3aff1a7435 */
/* 0x000fe200000001ff */
/*01b0*/ IMAD.MOV.U32 R14, RZ, RZ, 0x20202020 ; /* 0x20202020ff0e7424 */
/* 0x000fe200078e00ff */
/*01c0*/ STL.128 [R1+0x30], R8 ; /* 0x0000300801007387 */
/* 0x000fe20000100c00 */
/*01d0*/ IMAD R3, R3, c[0x0][0x4], R24 ; /* 0x0000010003037a24 */
/* 0x001fe200078e0218 */
/*01e0*/ MOV R25, 0x3a2023 ; /* 0x003a202300197802 */
/* 0x000fe20000000f00 */
/*01f0*/ IMAD.MOV.U32 R24, RZ, RZ, 0x20202020 ; /* 0x20202020ff187424 */
/* 0x000fe200078e00ff */
/*0200*/ STL.128 [R1+0x60], R8 ; /* 0x0000600801007387 */
/* 0x000fe20000100c00 */
/*0210*/ IMAD.MOV.U32 R27, RZ, RZ, 0x3a3a3a3a ; /* 0x3a3a3a3aff1b7424 */
/* 0x000fe200078e00ff */
/*0220*/ ISETP.GT.AND P0, PT, R3, 0xb, PT ; /* 0x0000000b0300780c */
/* 0x000fc40003f04270 */
/*0230*/ STL.128 [R1+0xb0], R8 ; /* 0x0000b00801007387 */
/* 0x0001e20000100c00 */
/*0240*/ IMAD R2, R2, c[0x0][0x0], R0 ; /* 0x0000000002027a24 */
/* 0x002fe200078e0200 */
/*0250*/ HFMA2.MMA R6, -RZ, RZ, 0.008056640625, 0.008056640625 ; /* 0x20202020ff067435 */
/* 0x004fe400000001ff */
/*0260*/ STL.128 [R1+0x80], R16 ; /* 0x0000801001007387 */
/* 0x0003e20000100c00 */
/*0270*/ MOV R4, 0x2020203a ; /* 0x2020203a00047802 */
/* 0x000fe20000000f00 */
/*0280*/ IMAD.MOV.U32 R5, RZ, RZ, 0x20202020 ; /* 0x20202020ff057424 */
/* 0x000fe200078e00ff */
/*0290*/ ISETP.GT.OR P0, PT, R2, 0x27, P0 ; /* 0x000000270200780c */
/* 0x000fe20000704670 */
/*02a0*/ STL.128 [R1+0x90], R20 ; /* 0x0000901401007387 */
/* 0x0005e80000100c00 */
/*02b0*/ STL.128 [R1+0x40], R12 ; /* 0x0000400c01007387 */
/* 0x0007e20000100c00 */
/*02c0*/ HFMA2.MMA R9, -RZ, RZ, 3.45706939697265625e-06, 0.008758544921875 ; /* 0x003a207cff097435 */
/* 0x001fe200000001ff */
/*02d0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x2020203a ; /* 0x2020203aff0a7424 */
/* 0x000fc400078e00ff */
/*02e0*/ STL.128 [R1+0x50], R4 ; /* 0x0000500401007387 */
/* 0x000fe20000100c00 */
/*02f0*/ HFMA2.MMA R18, -RZ, RZ, 0.01393890380859375, 0.008056640625 ; /* 0x23232020ff127435 */
/* 0x002fe200000001ff */
/*0300*/ IMAD.MOV.U32 R19, RZ, RZ, 0x20202323 ; /* 0x20202323ff137424 */
/* 0x000fe400078e00ff */
/*0310*/ STL.128 [R1+0xa0], R4 ; /* 0x0000a00401007387 */
/* 0x000fe20000100c00 */
/*0320*/ MOV R22, 0x3c202020 ; /* 0x3c20202000167802 */
/* 0x004fe20000000f00 */
/*0330*/ IMAD.MOV.U32 R23, RZ, RZ, 0x3a207c ; /* 0x003a207cff177424 */
/* 0x000fe400078e00ff */
/*0340*/ STL.128 [R1+0xf0], R4 ; /* 0x0000f00401007387 */
/* 0x0001e20000100c00 */
/*0350*/ IMAD.MOV.U32 R13, RZ, RZ, 0x3a2020 ; /* 0x003a2020ff0d7424 */
/* 0x008fe200078e00ff */
/*0360*/ MOV R14, 0x2020203a ; /* 0x2020203a000e7802 */
/* 0x000fe20000000f00 */
/*0370*/ IMAD.MOV.U32 R15, RZ, RZ, 0x20202020 ; /* 0x20202020ff0f7424 */
/* 0x000fe200078e00ff */
/*0380*/ STL.128 [R1+0xe0], R20 ; /* 0x0000e01401007387 */
/* 0x0003e80000100c00 */
/*0390*/ STL.128 [R1+0x110], R8 ; /* 0x0001100801007387 */
/* 0x0005e80000100c00 */
/*03a0*/ STL.128 [R1+0x70], R12 ; /* 0x0000700c01007387 */
/* 0x000fe20000100c00 */
/*03b0*/ HFMA2.MMA R6, -RZ, RZ, 0.008056640625, 0.0082550048828125 ; /* 0x2020203aff067435 */
/* 0x001fc600000001ff */
/*03c0*/ STL.128 [R1+0xc0], R12 ; /* 0x0000c00c01007387 */
/* 0x0001e20000100c00 */
/*03d0*/ MOV R4, 0x20202020 ; /* 0x2020202000047802 */
/* 0x000fe20000000f00 */
/*03e0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3a207c ; /* 0x003a207cff057424 */
/* 0x000fe200078e00ff */
/*03f0*/ HFMA2.MMA R22, -RZ, RZ, 0.008056640625, 0.008056640625 ; /* 0x20202020ff167435 */
/* 0x002fe200000001ff */
/*0400*/ STL.128 [R1+0xd0], R16 ; /* 0x0000d01001007387 */
/* 0x0003e20000100c00 */
/*0410*/ IMAD.MOV.U32 R20, RZ, RZ, 0x2020203a ; /* 0x2020203aff147424 */
/* 0x000fe200078e00ff */
/*0420*/ HFMA2.MMA R11, -RZ, RZ, 0.008056640625, 0.01393890380859375 ; /* 0x20202323ff0b7435 */
/* 0x004fe200000001ff */
/*0430*/ IMAD.MOV.U32 R23, RZ, RZ, 0x23232323 ; /* 0x23232323ff177424 */
/* 0x000fe200078e00ff */
/*0440*/ MOV R9, 0x23232323 ; /* 0x2323232300097802 */
/* 0x000fe20000000f00 */
/*0450*/ IMAD.MOV.U32 R8, RZ, RZ, 0x23232020 ; /* 0x23232020ff087424 */
/* 0x000fe200078e00ff */
/*0460*/ STL.128 [R1+0x160], R4 ; /* 0x0001600401007387 */
/* 0x0005e20000100c00 */
/*0470*/ IMAD.MOV.U32 R10, RZ, RZ, 0x23232323 ; /* 0x23232323ff0a7424 */
/* 0x000fe200078e00ff */
/*0480*/ HFMA2.MMA R15, -RZ, RZ, 0.008056640625, 0.01393890380859375 ; /* 0x20202323ff0f7435 */
/* 0x001fe200000001ff */
/*0490*/ MOV R13, 0x23232020 ; /* 0x23232020000d7802 */
/* 0x000fe20000000f00 */
/*04a0*/ IMAD.MOV.U32 R14, RZ, RZ, 0x23232323 ; /* 0x23232323ff0e7424 */
/* 0x000fe200078e00ff */
/*04b0*/ STL.128 [R1+0x140], R20 ; /* 0x0001401401007387 */
/* 0x0001e20000100c00 */
/*04c0*/ IMAD.MOV.U32 R18, RZ, RZ, 0x20202020 ; /* 0x20202020ff127424 */
/* 0x002fe200078e00ff */
/*04d0*/ MOV R19, 0x3a207c ; /* 0x003a207c00137802 */
/* 0x000fc40000000f00 */
/*04e0*/ STL.128 [R1+0x170], R8 ; /* 0x0001700801007387 */
/* 0x0003e80000100c00 */
/*04f0*/ STL.128 [R1+0x130], R16 ; /* 0x0001301001007387 */
/* 0x0007e20000100c00 */
/*0500*/ HFMA2.MMA R6, -RZ, RZ, 0.7783203125, 0.7783203125 ; /* 0x3a3a3a3aff067435 */
/* 0x004fe200000001ff */
/*0510*/ MOV R4, 0x3a3a3a3a ; /* 0x3a3a3a3a00047802 */
/* 0x000fe20000000f00 */
/*0520*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3a3a3a3a ; /* 0x3a3a3a3aff057424 */
/* 0x000fe200078e00ff */
/*0530*/ STL.128 [R1+0x120], R12 ; /* 0x0001200c01007387 */
/* 0x0005e20000100c00 */
/*0540*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3a3a3a3a ; /* 0x3a3a3a3aff077424 */
/* 0x000fe200078e00ff */
/*0550*/ HFMA2.MMA R21, -RZ, RZ, 0.008056640625, 0.01393890380859375 ; /* 0x20202323ff157435 */
/* 0x001fe200000001ff */
/*0560*/ IMAD.MOV.U32 R20, RZ, RZ, 0x23232323 ; /* 0x23232323ff147424 */
/* 0x000fe200078e00ff */
/*0570*/ STL.128 [R1+0x1b0], R24 ; /* 0x0001b01801007387 */
/* 0x0001e20000100c00 */
/*0580*/ IMAD.MOV.U32 R23, RZ, RZ, 0x20202020 ; /* 0x20202020ff177424 */
/* 0x000fe200078e00ff */
/*0590*/ HFMA2.MMA R10, -RZ, RZ, 0.7783203125, 0.7783203125 ; /* 0x3a3a3a3aff0a7435 */
/* 0x002fe200000001ff */
/*05a0*/ MOV R8, 0x3a3a3a3a ; /* 0x3a3a3a3a00087802 */
/* 0x000fe20000000f00 */
/*05b0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3a3a3a3a ; /* 0x3a3a3a3aff097424 */
/* 0x000fe200078e00ff */
/*05c0*/ STL.128 [R1], R4 ; /* 0x0000000401007387 */
/* 0x0001e20000100c00 */
/*05d0*/ HFMA2.MMA R16, -RZ, RZ, 0.008056640625, 0.0082550048828125 ; /* 0x2020203aff107435 */
/* 0x008fe200000001ff */
/*05e0*/ IMAD.MOV.U32 R18, RZ, RZ, 0x23232323 ; /* 0x23232323ff127424 */
/* 0x000fe200078e00ff */
/*05f0*/ MOV R19, 0x23232323 ; /* 0x2323232300137802 */
/* 0x000fe20000000f00 */
/*0600*/ IMAD.MOV.U32 R11, RZ, RZ, 0x3a3a3a ; /* 0x003a3a3aff0b7424 */
/* 0x000fe200078e00ff */
/*0610*/ MOV R14, 0x20202020 ; /* 0x20202020000e7802 */
/* 0x004fe20000000f00 */
/*0620*/ IMAD.MOV.U32 R13, RZ, RZ, 0x20202020 ; /* 0x20202020ff0d7424 */
/* 0x000fe200078e00ff */
/*0630*/ STL.128 [R1+0x100], R20 ; /* 0x0001001401007387 */
/* 0x0001e20000100c00 */
/*0640*/ IMAD.MOV.U32 R15, RZ, RZ, 0x3a207c ; /* 0x003a207cff0f7424 */
/* 0x000fc600078e00ff */
/*0650*/ STL.128 [R1+0x190], R16 ; /* 0x0001901001007387 */
/* 0x0001e80000100c00 */
/*0660*/ STL.128 [R1+0x180], R12 ; /* 0x0001800c01007387 */
/* 0x0001e80000100c00 */
/*0670*/ STL.128 [R1+0x150], R20 ; /* 0x0001501401007387 */
/* 0x0001e80000100c00 */
/*0680*/ STL.128 [R1+0x1a0], R20 ; /* 0x0001a01401007387 */
/* 0x0001e80000100c00 */
/*0690*/ STL.128 [R1+0x10], R4 ; /* 0x0000100401007387 */
/* 0x0001e80000100c00 */
/*06a0*/ STL.128 [R1+0x1c0], R4 ; /* 0x0001c00401007387 */
/* 0x0001e80000100c00 */
/*06b0*/ STL.128 [R1+0x1d0], R8 ; /* 0x0001d00801007387 */
/* 0x0001e20000100c00 */
/*06c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*06d0*/ ISETP.NE.AND P0, PT, R3, 0xb, PT ; /* 0x0000000b0300780c */
/* 0x000fe20003f05270 */
/*06e0*/ IMAD.MOV.U32 R5, RZ, RZ, 0xa ; /* 0x0000000aff057424 */
/* 0x001fe200078e00ff */
/*06f0*/ MOV R0, R1 ; /* 0x0000000100007202 */
/* 0x000fc40000000f00 */
/*0700*/ ISETP.EQ.AND P0, PT, R2, 0x27, P0 ; /* 0x000000270200780c */
/* 0x000fda0000702270 */
/*0710*/ @!P0 IMAD R4, R3, 0x28, R0.reuse ; /* 0x0000002803048824 */
/* 0x100fe200078e0200 */
/*0720*/ PRMT R0, R5, 0x7610, R0 ; /* 0x0000761005007816 */
/* 0x000fc80000000000 */
/*0730*/ @!P0 IADD3 R4, R2, R4, RZ ; /* 0x0000000402048210 */
/* 0x000fca0007ffe0ff */
/*0740*/ @!P0 LDL.U8 R0, [R4] ; /* 0x0000000004008983 */
/* 0x000ea20000100000 */
/*0750*/ IMAD R3, R3, 0x28, R2 ; /* 0x0000002803037824 */
/* 0x000fe200078e0202 */
/*0760*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0770*/ IADD3 R2, P0, R3, c[0x0][0x160], RZ ; /* 0x0000580003027a10 */
/* 0x000fc80007f1e0ff */
/*0780*/ LEA.HI.X.SX32 R3, R3, c[0x0][0x164], 0x1, P0 ; /* 0x0000590003037a11 */
/* 0x000fca00000f0eff */
/*0790*/ STG.E.U8 [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x004fe2000c101104 */
/*07a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07b0*/ BRA 0x7b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4drawPc
.globl _Z4drawPc
.p2align 8
.type _Z4drawPc,@function
_Z4drawPc:
s_load_b32 s2, s[0:1], 0x14
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[2:3], null, s15, s2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, 40, v0
v_cmp_gt_i32_e64 s2, 12, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_4
v_cmp_ne_u32_e32 vcc_lo, 39, v0
v_cmp_eq_u32_e64 s2, 11, v2
v_mov_b32_e32 v1, 10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s3, vcc_lo, s2
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_3
v_ashrrev_i32_e32 v1, 31, v0
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, __const._Z4drawPc.tmp_str@rel32@lo+4
s_addc_u32 s5, s5, __const._Z4drawPc.tmp_str@rel32@hi+12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_i64_i32 v[3:4], null, v2, 40, v[0:1]
v_add_co_u32 v3, vcc_lo, v3, s4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_u8 v1, v[3:4], off
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v2, 40, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v0, 31, v3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v0, vcc_lo
global_store_b8 v[2:3], v1, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4drawPc
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4drawPc, .Lfunc_end0-_Z4drawPc
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __const._Z4drawPc.tmp_str,@object
.section .rodata,"a",@progbits
.p2align 4, 0x0
__const._Z4drawPc.tmp_str:
.asciz ":::::::::::::::::::::::::::::::::::::::"
.asciz ": :"
.asciz ": :"
.asciz ": :"
.asciz ": :"
.asciz ": #### <| :"
.asciz ": ###### | :"
.asciz ": ######## | :"
.asciz ": ########## | :"
.asciz ": ############ | :"
.asciz ": ############## # :"
.asciz ":::::::::::::::::::::::::::::::::::::::"
.size __const._Z4drawPc.tmp_str, 480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4drawPc
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4drawPc.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00041820_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z4drawPcPc
.type _Z23__device_stub__Z4drawPcPc, @function
_Z23__device_stub__Z4drawPcPc:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4drawPc(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z23__device_stub__Z4drawPcPc, .-_Z23__device_stub__Z4drawPcPc
.globl _Z4drawPc
.type _Z4drawPc, @function
_Z4drawPc:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z4drawPcPc
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z4drawPc, .-_Z4drawPc
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $480, %edi
call malloc@PLT
movq %rax, %rbx
movl $60, %ecx
movl $0, %eax
movq %rbx, %rdi
rep stosq
leaq 8(%rsp), %rdi
movl $480, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $480, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 16(%rsp)
movl $12, 20(%rsp)
movl $3, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movl $480, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z23__device_stub__Z4drawPcPc
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z4drawPc"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z4drawPc(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z19__device_stub__drawPc # -- Begin function _Z19__device_stub__drawPc
.p2align 4, 0x90
.type _Z19__device_stub__drawPc,@function
_Z19__device_stub__drawPc: # @_Z19__device_stub__drawPc
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z4drawPc, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z19__device_stub__drawPc, .Lfunc_end0-_Z19__device_stub__drawPc
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $80, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -16
movl $480, %edi # imm = 0x1E0
callq malloc
movq %rax, %rbx
movl $480, %edx # imm = 0x1E0
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
leaq 8(%rsp), %rdi
movl $480, %esi # imm = 0x1E0
callq hipMalloc
movq 8(%rsp), %rdi
movl $480, %edx # imm = 0x1E0
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967299, %rdi # imm = 0x100000003
movabsq $51539607568, %rdx # imm = 0xC00000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z4drawPc, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movl $480, %edx # imm = 0x1E0
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $80, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4drawPc, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4drawPc,@object # @_Z4drawPc
.section .rodata,"a",@progbits
.globl _Z4drawPc
.p2align 3, 0x0
_Z4drawPc:
.quad _Z19__device_stub__drawPc
.size _Z4drawPc, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%s"
.size .L.str, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4drawPc"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__drawPc
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4drawPc
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <string>
#include <iostream>
#include <cmath>
#include <climits>
#include <fstream>
//const int N = 512;
using namespace::std;
const int BLOCKS = 19000;
const int DIMENSIONS = 16;
const int TESTLINES = 1000;
unsigned short int testLines[TESTLINES*DIMENSIONS];
unsigned short int trainLines[BLOCKS*DIMENSIONS];
string testFilename = "test.txt";
string trainFilename = "train.txt";
string outputFilename = "myout.txt";
void parseLine(string line, int startIndex, unsigned short int* arr) {
int start=0;
int numIndex = startIndex;
for (size_t i = 0; i < line.length(); i++) {
if (line[i] == ',') {
arr[numIndex] = stoi(line.substr(start, i-start));
numIndex++;
start = i+1;
}
}
arr[numIndex] = stoi(line.substr(start, line.length()-start));
}
void readFile(string filename, unsigned short int* arr){
ifstream inputFile;
inputFile.open(filename.c_str());
int ind = 0;
string line;
while (getline(inputFile, line)) {
parseLine(line, ind*DIMENSIONS, arr);
ind++;
}
}
__global__
void calculateDifference(short int *trainLines,unsigned long long int *diffSquare, short int *testLines, short int id){
__shared__ unsigned int s_diffSquare;
s_diffSquare = 0;
__syncthreads();
short int other = testLines[id*DIMENSIONS + threadIdx.x];
short int self = trainLines[blockIdx.x*DIMENSIONS + threadIdx.x];
int result = other - self;
atomicAdd(&s_diffSquare, result * result);
__syncthreads();
if (threadIdx.x % DIMENSIONS == 0) {
// this will contain min with its index. Since the actual number is on the left side, comparison will be done between
// the mins. Index will have no effect except the case where two distances are equal which will return the lower index.
unsigned long long int min = (((unsigned long long int) s_diffSquare) << 32) | blockIdx.x;
atomicMin(diffSquare, min);
}
}
void getNearestNeighbors(short int *trainLines, short int *testLines,unsigned short int *result){
unsigned long long int *d_diffSquare;
unsigned long long int *diffSquare;
diffSquare = (unsigned long long int *)malloc(sizeof(unsigned long long int));
cudaMalloc((void **)&d_diffSquare, sizeof(unsigned long long int));
unsigned long long int maxLongLong = ULLONG_MAX;
for (size_t i = 0; i < TESTLINES; i++) {
cudaMemcpy(d_diffSquare, &maxLongLong, sizeof(unsigned long long int), cudaMemcpyHostToDevice);
calculateDifference<<<BLOCKS, DIMENSIONS>>>(trainLines, d_diffSquare, testLines, i);
cudaMemcpy(diffSquare, d_diffSquare, sizeof(unsigned long long int), cudaMemcpyDeviceToHost);
result[i] = (unsigned int) *diffSquare;
}
free(diffSquare);
cudaFree(d_diffSquare);
}
int main(int argc, char *argv[]) {
readFile(testFilename, testLines);
readFile(trainFilename, trainLines);
short int* d_testLines;
short int* d_trainLines;
unsigned short int* output;
int lineSize = DIMENSIONS * sizeof(short int);
int trainLinesSize = BLOCKS * lineSize;
int testLinesSize = TESTLINES * lineSize;
output = (unsigned short int *)malloc(TESTLINES * sizeof(unsigned short int));
cudaMalloc((void **)&d_testLines, testLinesSize);
cudaMalloc((void **)&d_trainLines, trainLinesSize);
cudaMemcpy(d_testLines, testLines, testLinesSize, cudaMemcpyHostToDevice);
cudaMemcpy(d_trainLines, trainLines, trainLinesSize, cudaMemcpyHostToDevice);
getNearestNeighbors(d_trainLines, d_testLines, output);
ofstream outputFile;
outputFile.open(outputFilename.c_str());
for (size_t i = 0; i < TESTLINES; i++) {
outputFile << output[i] << endl;
}
free(output);
cudaFree(d_testLines); cudaFree(d_trainLines);
return 1;
} | code for sm_80
Function : _Z19calculateDifferencePsPyS_s
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ LDC.U16 R0, c[0x0][0x178] ; /* 0x00005e00ff007b82 */
/* 0x000e220000000400 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0030*/ IMAD.MOV.U32 R5, RZ, RZ, 0x2 ; /* 0x00000002ff057424 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0050*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0060*/ STS [RZ], RZ ; /* 0x000000ffff007388 */
/* 0x000fe20000000800 */
/*0070*/ PRMT R4, R0, 0x9910, RZ ; /* 0x0000991000047816 */
/* 0x001fc400000000ff */
/*0080*/ LEA R6, R2, R3, 0x4 ; /* 0x0000000302067211 */
/* 0x002fc600078e20ff */
/*0090*/ IMAD R4, R4, 0x10, R3 ; /* 0x0000001004047824 */
/* 0x000fe400078e0203 */
/*00a0*/ IMAD.WIDE.U32 R6, R6, R5.reuse, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x080fe200078e0005 */
/*00b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*00c0*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fc600078e0005 */
/*00d0*/ LDG.E.S16 R7, [R6.64] ; /* 0x0000000606077981 */
/* 0x000ea8000c1e1700 */
/*00e0*/ LDG.E.S16 R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1700 */
/*00f0*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe200038e0100 */
/*0100*/ LOP3.LUT P0, RZ, R3, 0xf, RZ, 0xc0, !PT ; /* 0x0000000f03ff7812 */
/* 0x000fe2000780c0ff */
/*0110*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fe200080e0000 */
/*0120*/ S2R R8, SR_LANEID ; /* 0x0000000000087919 */
/* 0x000e2a0000000000 */
/*0130*/ ISETP.EQ.U32.AND P1, PT, R8, UR4, PT ; /* 0x0000000408007c0c */
/* 0x001fc4000bf22070 */
/*0140*/ IADD3 R0, R4, -R7, RZ ; /* 0x8000000704007210 */
/* 0x004fca0007ffe0ff */
/*0150*/ IMAD R0, R0, R0, RZ ; /* 0x0000000000007224 */
/* 0x000fc800078e02ff */
/*0160*/ REDUX.SUM UR5, R0 ; /* 0x00000000000573c4 */
/* 0x000e24000000c000 */
/*0170*/ IMAD.U32 R8, RZ, RZ, UR5 ; /* 0x00000005ff087e24 */
/* 0x001fca000f8e00ff */
/*0180*/ @P1 ATOMS.ADD RZ, [RZ], R8 ; /* 0x00000008ffff138c */
/* 0x0001e80000000000 */
/*0190*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01b0*/ LDS R3, [RZ] ; /* 0x00000000ff037984 */
/* 0x001e220000000800 */
/*01c0*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fc40000000f00 */
/*01d0*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fca0000000f00 */
/*01e0*/ RED.E.MIN.64.STRONG.GPU [R4.64], R2 ; /* 0x000000020400798e */
/* 0x001fe2000c90e586 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <string>
#include <iostream>
#include <cmath>
#include <climits>
#include <fstream>
//const int N = 512;
using namespace::std;
const int BLOCKS = 19000;
const int DIMENSIONS = 16;
const int TESTLINES = 1000;
unsigned short int testLines[TESTLINES*DIMENSIONS];
unsigned short int trainLines[BLOCKS*DIMENSIONS];
string testFilename = "test.txt";
string trainFilename = "train.txt";
string outputFilename = "myout.txt";
void parseLine(string line, int startIndex, unsigned short int* arr) {
int start=0;
int numIndex = startIndex;
for (size_t i = 0; i < line.length(); i++) {
if (line[i] == ',') {
arr[numIndex] = stoi(line.substr(start, i-start));
numIndex++;
start = i+1;
}
}
arr[numIndex] = stoi(line.substr(start, line.length()-start));
}
void readFile(string filename, unsigned short int* arr){
ifstream inputFile;
inputFile.open(filename.c_str());
int ind = 0;
string line;
while (getline(inputFile, line)) {
parseLine(line, ind*DIMENSIONS, arr);
ind++;
}
}
__global__
void calculateDifference(short int *trainLines,unsigned long long int *diffSquare, short int *testLines, short int id){
__shared__ unsigned int s_diffSquare;
s_diffSquare = 0;
__syncthreads();
short int other = testLines[id*DIMENSIONS + threadIdx.x];
short int self = trainLines[blockIdx.x*DIMENSIONS + threadIdx.x];
int result = other - self;
atomicAdd(&s_diffSquare, result * result);
__syncthreads();
if (threadIdx.x % DIMENSIONS == 0) {
// this will contain min with its index. Since the actual number is on the left side, comparison will be done between
// the mins. Index will have no effect except the case where two distances are equal which will return the lower index.
unsigned long long int min = (((unsigned long long int) s_diffSquare) << 32) | blockIdx.x;
atomicMin(diffSquare, min);
}
}
void getNearestNeighbors(short int *trainLines, short int *testLines,unsigned short int *result){
unsigned long long int *d_diffSquare;
unsigned long long int *diffSquare;
diffSquare = (unsigned long long int *)malloc(sizeof(unsigned long long int));
cudaMalloc((void **)&d_diffSquare, sizeof(unsigned long long int));
unsigned long long int maxLongLong = ULLONG_MAX;
for (size_t i = 0; i < TESTLINES; i++) {
cudaMemcpy(d_diffSquare, &maxLongLong, sizeof(unsigned long long int), cudaMemcpyHostToDevice);
calculateDifference<<<BLOCKS, DIMENSIONS>>>(trainLines, d_diffSquare, testLines, i);
cudaMemcpy(diffSquare, d_diffSquare, sizeof(unsigned long long int), cudaMemcpyDeviceToHost);
result[i] = (unsigned int) *diffSquare;
}
free(diffSquare);
cudaFree(d_diffSquare);
}
int main(int argc, char *argv[]) {
readFile(testFilename, testLines);
readFile(trainFilename, trainLines);
short int* d_testLines;
short int* d_trainLines;
unsigned short int* output;
int lineSize = DIMENSIONS * sizeof(short int);
int trainLinesSize = BLOCKS * lineSize;
int testLinesSize = TESTLINES * lineSize;
output = (unsigned short int *)malloc(TESTLINES * sizeof(unsigned short int));
cudaMalloc((void **)&d_testLines, testLinesSize);
cudaMalloc((void **)&d_trainLines, trainLinesSize);
cudaMemcpy(d_testLines, testLines, testLinesSize, cudaMemcpyHostToDevice);
cudaMemcpy(d_trainLines, trainLines, trainLinesSize, cudaMemcpyHostToDevice);
getNearestNeighbors(d_trainLines, d_testLines, output);
ofstream outputFile;
outputFile.open(outputFilename.c_str());
for (size_t i = 0; i < TESTLINES; i++) {
outputFile << output[i] << endl;
}
free(output);
cudaFree(d_testLines); cudaFree(d_trainLines);
return 1;
} | .file "tmpxft_000cdd2b_00000000-6_bfs.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3807:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3807:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z19calculateDifferencePsPyS_sPsPyS_s
.type _Z44__device_stub__Z19calculateDifferencePsPyS_sPsPyS_s, @function
_Z44__device_stub__Z19calculateDifferencePsPyS_sPsPyS_s:
.LFB3829:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movw %cx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19calculateDifferencePsPyS_s(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3829:
.size _Z44__device_stub__Z19calculateDifferencePsPyS_sPsPyS_s, .-_Z44__device_stub__Z19calculateDifferencePsPyS_sPsPyS_s
.globl _Z19calculateDifferencePsPyS_s
.type _Z19calculateDifferencePsPyS_s, @function
_Z19calculateDifferencePsPyS_s:
.LFB3830:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movswl %cx, %ecx
call _Z44__device_stub__Z19calculateDifferencePsPyS_sPsPyS_s
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3830:
.size _Z19calculateDifferencePsPyS_s, .-_Z19calculateDifferencePsPyS_s
.globl _Z19getNearestNeighborsPsS_Pt
.type _Z19getNearestNeighborsPsS_Pt, @function
_Z19getNearestNeighborsPsS_Pt:
.LFB3803:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r15
movq %rsi, %r14
movq %rdx, %r12
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $8, %edi
call malloc@PLT
movq %rax, %rbp
movq %rsp, %rdi
movl $8, %esi
call cudaMalloc@PLT
movq $-1, 8(%rsp)
movl $0, %ebx
leaq 8(%rsp), %r13
jmp .L13
.L12:
movl $2, %ecx
movl $8, %edx
movq (%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq 0(%rbp), %rax
movw %ax, (%r12,%rbx,2)
addq $1, %rbx
cmpq $1000, %rbx
je .L17
.L13:
movl $1, %ecx
movl $8, %edx
movq %r13, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 28(%rsp)
movl $1, 32(%rsp)
movl $19000, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L12
movl %ebx, %ecx
movq %r14, %rdx
movq (%rsp), %rsi
movq %r15, %rdi
call _Z44__device_stub__Z19calculateDifferencePsPyS_sPsPyS_s
jmp .L12
.L17:
movq %rbp, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3803:
.size _Z19getNearestNeighborsPsS_Pt, .-_Z19getNearestNeighborsPsS_Pt
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19calculateDifferencePsPyS_s"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3832:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19calculateDifferencePsPyS_s(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3832:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,"axG",@progbits,_ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,comdat
.weak _ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.type _ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_, @function
_ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_:
.LFB3906:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3906
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r13
movq %rsi, 8(%rsp)
movq %rdx, %rbp
movq %rcx, %r12
movl %r8d, %r14d
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
call __errno_location@PLT
movq %rax, %rbx
movl (%rax), %r15d
movl $0, (%rax)
leaq 16(%rsp), %rsi
movl %r14d, %edx
movq %rbp, %rdi
.LEHB0:
call *%r13
movq 16(%rsp), %rcx
cmpq %rbp, %rcx
je .L35
cmpl $34, (%rbx)
je .L24
movl $2147483648, %edx
addq %rax, %rdx
shrq $32, %rdx
jne .L24
testq %r12, %r12
je .L27
subq %rbp, %rcx
movq %rcx, (%r12)
.L27:
cmpl $0, (%rbx)
jne .L21
movl %r15d, (%rbx)
.L21:
movq 24(%rsp), %rdx
subq %fs:40, %rdx
jne .L36
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L37
movq 8(%rsp), %rdi
call _ZSt24__throw_invalid_argumentPKc@PLT
.L37:
call __stack_chk_fail@PLT
.L24:
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L38
movq 8(%rsp), %rdi
call _ZSt20__throw_out_of_rangePKc@PLT
.LEHE0:
.L33:
endbr64
movq %rax, %rdi
cmpl $0, (%rbx)
jne .L30
movl %r15d, (%rbx)
.L30:
movq 24(%rsp), %rax
subq %fs:40, %rax
je .L31
call __stack_chk_fail@PLT
.L38:
call __stack_chk_fail@PLT
.L31:
.LEHB1:
call _Unwind_Resume@PLT
.LEHE1:
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3906:
.globl __gxx_personality_v0
.section .gcc_except_table._ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,"aG",@progbits,_ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,comdat
.LLSDA3906:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3906-.LLSDACSB3906
.LLSDACSB3906:
.uleb128 .LEHB0-.LFB3906
.uleb128 .LEHE0-.LEHB0
.uleb128 .L33-.LFB3906
.uleb128 0
.uleb128 .LEHB1-.LFB3906
.uleb128 .LEHE1-.LEHB1
.uleb128 0
.uleb128 0
.LLSDACSE3906:
.section .text._ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,"axG",@progbits,_ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,comdat
.size _ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_, .-_ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag,comdat
.align 2
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag, @function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag:
.LFB4256:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movq %rsi, %r12
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
subq %rsi, %rdx
movq %rdx, %rbp
movq %rdx, (%rsp)
cmpq $15, %rdx
ja .L46
movq (%rdi), %rdi
cmpq $1, %rdx
jne .L42
movzbl (%rsi), %eax
movb %al, (%rdi)
.L43:
movq (%rsp), %rax
movq %rax, 8(%rbx)
movq (%rbx), %rdx
movb $0, (%rdx,%rax)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L47
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
movq %rsp, %rsi
movl $0, %edx
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
movq %rax, %rdi
movq %rax, (%rbx)
movq (%rsp), %rax
movq %rax, 16(%rbx)
.L41:
movq %rbp, %rdx
movq %r12, %rsi
call memcpy@PLT
jmp .L43
.L42:
testq %rdx, %rdx
je .L43
jmp .L41
.L47:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4256:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag, .-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.section .rodata._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "basic_string: construction from null is not valid"
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC5IS3_EEPKcRKS3_,comdat
.align 2
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, @function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_:
.LFB4149:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
leaq 16(%rdi), %rax
movq %rax, (%rdi)
testq %rsi, %rsi
je .L51
movq %rdi, %rbp
movq %rsi, %rbx
movq %rsi, %rdi
call strlen@PLT
leaq (%rbx,%rax), %rdx
movq %rbx, %rsi
movq %rbp, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L51:
.cfi_restore_state
leaq .LC1(%rip), %rdi
call _ZSt19__throw_logic_errorPKc@PLT
.cfi_endproc
.LFE4149:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, .-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.set _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "basic_string::substr"
.section .rodata.str1.8
.align 8
.LC3:
.string "%s: __pos (which is %zu) > this->size() (which is %zu)"
.section .rodata.str1.1
.LC4:
.string "stoi"
.text
.globl _Z9parseLineNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEiPt
.type _Z9parseLineNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEiPt, @function
_Z9parseLineNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEiPt:
.LFB3800:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3800
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbp
movl %esi, %r12d
movq %rdx, %r13
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq 8(%rdi), %rcx
testq %rcx, %rcx
je .L66
movl $0, %ebx
leaq .LC4(%rip), %r14
jmp .L58
.L73:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L71
movq %rax, %rdx
leaq .LC2(%rip), %rsi
leaq .LC3(%rip), %rdi
movl $0, %eax
.LEHB2:
call _ZSt24__throw_out_of_range_fmtPKcz@PLT
.L71:
call __stack_chk_fail@PLT
.L74:
movl %eax, %edx
movslq %r12d, %rax
movw %dx, 0(%r13,%rax,2)
movq (%rsp), %rdi
leaq 16(%rsp), %rax
cmpq %rax, %rdi
je .L57
movq 16(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L57:
addl $1, %r12d
leal 1(%rbx), %eax
.L54:
addq $1, %rbx
movq 8(%rbp), %rcx
cmpq %rcx, %rbx
jnb .L72
.L58:
movq 0(%rbp), %rsi
cmpb $44, (%rsi,%rbx)
jne .L54
cltq
movq %rbx, %rdx
subq %rax, %rdx
cmpq %rax, %rcx
jb .L73
movq %rsp, %rdi
leaq 16(%rsp), %r8
movq %r8, (%rsp)
addq %rax, %rsi
subq %rax, %rcx
cmpq %rdx, %rcx
cmova %rdx, %rcx
leaq (%rsi,%rcx), %rdx
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.LEHE2:
movl $10, %r8d
movl $0, %ecx
movq (%rsp), %rdx
movq %r14, %rsi
movq __isoc23_strtol@GOTPCREL(%rip), %rdi
.LEHB3:
call _ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.LEHE3:
jmp .L74
.L72:
cltq
cmpq %rax, %rcx
jb .L75
.L53:
movq %rsp, %rdi
leaq 16(%rsp), %rdx
movq %rdx, (%rsp)
movq 0(%rbp), %rsi
leaq (%rsi,%rcx), %rdx
addq %rax, %rsi
.LEHB4:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.LEHE4:
movl $10, %r8d
movl $0, %ecx
movq (%rsp), %rdx
leaq .LC4(%rip), %rsi
movq __isoc23_strtol@GOTPCREL(%rip), %rdi
.LEHB5:
call _ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.LEHE5:
jmp .L76
.L75:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L77
movq %rax, %rdx
leaq .LC2(%rip), %rsi
leaq .LC3(%rip), %rdi
movl $0, %eax
.LEHB6:
call _ZSt24__throw_out_of_range_fmtPKcz@PLT
.L77:
call __stack_chk_fail@PLT
.L66:
movq %rcx, %rax
jmp .L53
.L76:
movslq %r12d, %r12
movw %ax, 0(%r13,%r12,2)
movq (%rsp), %rdi
leaq 16(%rsp), %rax
cmpq %rax, %rdi
je .L52
movq 16(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L52:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L78
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L67:
.cfi_restore_state
endbr64
movq %rax, %rbx
movq %rsp, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
je .L62
call __stack_chk_fail@PLT
.L62:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L68:
endbr64
movq %rax, %rbx
movq %rsp, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
je .L64
call __stack_chk_fail@PLT
.L64:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE6:
.L78:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3800:
.section .gcc_except_table,"a",@progbits
.LLSDA3800:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3800-.LLSDACSB3800
.LLSDACSB3800:
.uleb128 .LEHB2-.LFB3800
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB3800
.uleb128 .LEHE3-.LEHB3
.uleb128 .L67-.LFB3800
.uleb128 0
.uleb128 .LEHB4-.LFB3800
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.uleb128 .LEHB5-.LFB3800
.uleb128 .LEHE5-.LEHB5
.uleb128 .L68-.LFB3800
.uleb128 0
.uleb128 .LEHB6-.LFB3800
.uleb128 .LEHE6-.LEHB6
.uleb128 0
.uleb128 0
.LLSDACSE3800:
.text
.size _Z9parseLineNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEiPt, .-_Z9parseLineNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEiPt
.globl _Z8readFileNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPt
.type _Z8readFileNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPt, @function
_Z8readFileNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPt:
.LFB3801:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3801
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $616, %rsp
.cfi_def_cfa_offset 672
movq %rdi, %rbx
movq %rsi, %r14
movq %fs:40, %rax
movq %rax, 600(%rsp)
xorl %eax, %eax
leaq 80(%rsp), %rbp
leaq 336(%rsp), %rdi
call _ZNSt8ios_baseC2Ev@PLT
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 336(%rsp)
movq $0, 552(%rsp)
movb $0, 560(%rsp)
movb $0, 561(%rsp)
movq $0, 568(%rsp)
movq $0, 576(%rsp)
movq $0, 584(%rsp)
movq $0, 592(%rsp)
movq 8+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 80(%rsp)
movq -24(%rax), %rax
movq 16+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rcx
movq %rcx, 80(%rsp,%rax)
movq $0, 88(%rsp)
movq 80(%rsp), %rax
movq %rbp, %rdi
addq -24(%rax), %rdi
movl $0, %esi
.LEHB7:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE7:
leaq 24+_ZTVSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 80(%rsp)
leaq 40(%rax), %rax
movq %rax, 336(%rsp)
leaq 96(%rsp), %rdi
.LEHB8:
call _ZNSt13basic_filebufIcSt11char_traitsIcEEC1Ev@PLT
.LEHE8:
leaq 96(%rsp), %rsi
leaq 336(%rsp), %rdi
.LEHB9:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE9:
jmp .L117
.L111:
endbr64
movq %rax, %rbx
leaq 96(%rsp), %rdi
call _ZNSt13basic_filebufIcSt11char_traitsIcEED1Ev@PLT
.L82:
movq 8+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 80(%rsp)
movq -24(%rax), %rax
movq 16+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rcx
movq %rcx, 80(%rsp,%rax)
movq $0, 88(%rsp)
.L83:
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 336(%rsp)
leaq 336(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 600(%rsp), %rax
subq %fs:40, %rax
je .L84
call __stack_chk_fail@PLT
.L110:
endbr64
movq %rax, %rbx
jmp .L82
.L109:
endbr64
movq %rax, %rbx
jmp .L83
.L84:
movq %rbx, %rdi
.LEHB10:
call _Unwind_Resume@PLT
.LEHE10:
.L117:
movq (%rbx), %rsi
leaq 96(%rsp), %rdi
movl $8, %edx
.LEHB11:
call _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
testq %rax, %rax
je .L118
movq 80(%rsp), %rax
movq -24(%rax), %rax
leaq 80(%rsp,%rax), %rdi
movl $0, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L86
.L118:
movq 80(%rsp), %rax
movq -24(%rax), %rax
leaq 80(%rsp,%rax), %rdi
movl 32(%rdi), %esi
orl $4, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
.LEHE11:
.L86:
leaq 32(%rsp), %rax
movq %rax, 16(%rsp)
movq $0, 24(%rsp)
movb $0, 32(%rsp)
movq 80(%rsp), %rax
movq -24(%rax), %rax
movq 320(%rsp,%rax), %rbx
testq %rbx, %rbx
je .L87
movl $0, %ebp
leaq 16(%rsp), %r15
jmp .L88
.L122:
leaq 8(%rsp), %rsi
leaq 48(%rsp), %rdi
movl $0, %edx
.LEHB12:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
movq %rax, %rdi
movq %rax, 48(%rsp)
movq 8(%rsp), %rax
movq %rax, 64(%rsp)
.L90:
movq %rbx, %rdx
movq %r13, %rsi
call memcpy@PLT
jmp .L92
.L91:
testq %rbx, %rbx
je .L92
leaq 64(%rsp), %rdi
jmp .L90
.L123:
movq 48(%rsp), %rdi
leaq 64(%rsp), %rax
cmpq %rax, %rdi
je .L93
movq 64(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L93:
movq 80(%rsp), %rax
movq -24(%rax), %rax
movq 320(%rsp,%rax), %rbx
addl $16, %ebp
testq %rbx, %rbx
je .L87
.L88:
cmpb $0, 56(%rbx)
je .L95
movzbl 67(%rbx), %edx
.L96:
movsbl %dl, %edx
leaq 80(%rsp), %rdi
movq %r15, %rsi
call _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EES4_@PLT
jmp .L119
.L87:
movq 600(%rsp), %rax
subq %fs:40, %rax
jne .L120
call _ZSt16__throw_bad_castv@PLT
.L108:
endbr64
movq %rax, %rbx
jmp .L102
.L120:
call __stack_chk_fail@PLT
.L95:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
.LEHE12:
movl %eax, %edx
jmp .L96
.L119:
movq (%rax), %rdx
movq -24(%rdx), %rdx
testb $5, 32(%rax,%rdx)
jne .L121
movl %ebp, %r12d
leaq 64(%rsp), %rax
movq %rax, 48(%rsp)
movq 16(%rsp), %r13
movq 24(%rsp), %rbx
movq %rbx, 8(%rsp)
cmpq $15, %rbx
ja .L122
cmpq $1, %rbx
jne .L91
movzbl 0(%r13), %eax
movb %al, 64(%rsp)
.L92:
movq 8(%rsp), %rax
movq %rax, 56(%rsp)
movq 48(%rsp), %rdx
movb $0, (%rdx,%rax)
leaq 48(%rsp), %rdi
movq %r14, %rdx
movl %r12d, %esi
.LEHB13:
call _Z9parseLineNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEiPt
.LEHE13:
jmp .L123
.L121:
movq 16(%rsp), %rdi
leaq 32(%rsp), %rax
cmpq %rax, %rdi
je .L98
movq 32(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L98:
leaq 24+_ZTVSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 80(%rsp)
leaq 40(%rax), %rax
movq %rax, 336(%rsp)
leaq 16+_ZTVSt13basic_filebufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 96(%rsp)
leaq 96(%rsp), %rdi
.LEHB14:
call _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv@PLT
.LEHE14:
jmp .L100
.L112:
endbr64
movq %rax, %rdi
call __cxa_begin_catch@PLT
call __cxa_end_catch@PLT
.L100:
leaq 200(%rsp), %rdi
call _ZNSt12__basic_fileIcED1Ev@PLT
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 96(%rsp)
leaq 152(%rsp), %rdi
call _ZNSt6localeD1Ev@PLT
movq 8+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 80(%rsp)
movq -24(%rax), %rax
movq 16+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rcx
movq %rcx, 80(%rsp,%rax)
movq $0, 88(%rsp)
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 336(%rsp)
leaq 336(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 600(%rsp), %rax
subq %fs:40, %rax
jne .L124
addq $616, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L107:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 48(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L102:
leaq 16(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L103:
leaq 80(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq 600(%rsp), %rax
subq %fs:40, %rax
je .L104
call __stack_chk_fail@PLT
.L106:
endbr64
movq %rax, %rbx
jmp .L103
.L104:
movq %rbx, %rdi
.LEHB15:
call _Unwind_Resume@PLT
.LEHE15:
.L124:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3801:
.section .gcc_except_table
.align 4
.LLSDA3801:
.byte 0xff
.byte 0x9b
.uleb128 .LLSDATT3801-.LLSDATTD3801
.LLSDATTD3801:
.byte 0x1
.uleb128 .LLSDACSE3801-.LLSDACSB3801
.LLSDACSB3801:
.uleb128 .LEHB7-.LFB3801
.uleb128 .LEHE7-.LEHB7
.uleb128 .L109-.LFB3801
.uleb128 0
.uleb128 .LEHB8-.LFB3801
.uleb128 .LEHE8-.LEHB8
.uleb128 .L110-.LFB3801
.uleb128 0
.uleb128 .LEHB9-.LFB3801
.uleb128 .LEHE9-.LEHB9
.uleb128 .L111-.LFB3801
.uleb128 0
.uleb128 .LEHB10-.LFB3801
.uleb128 .LEHE10-.LEHB10
.uleb128 0
.uleb128 0
.uleb128 .LEHB11-.LFB3801
.uleb128 .LEHE11-.LEHB11
.uleb128 .L106-.LFB3801
.uleb128 0
.uleb128 .LEHB12-.LFB3801
.uleb128 .LEHE12-.LEHB12
.uleb128 .L108-.LFB3801
.uleb128 0
.uleb128 .LEHB13-.LFB3801
.uleb128 .LEHE13-.LEHB13
.uleb128 .L107-.LFB3801
.uleb128 0
.uleb128 .LEHB14-.LFB3801
.uleb128 .LEHE14-.LEHB14
.uleb128 .L112-.LFB3801
.uleb128 0x1
.uleb128 .LEHB15-.LFB3801
.uleb128 .LEHE15-.LEHB15
.uleb128 0
.uleb128 0
.LLSDACSE3801:
.byte 0x1
.byte 0
.align 4
.long 0
.LLSDATT3801:
.text
.size _Z8readFileNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPt, .-_Z8readFileNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPt
.globl main
.type main, @function
main:
.LFB3804:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3804
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $552, %rsp
.cfi_def_cfa_offset 608
movq %fs:40, %rax
movq %rax, 536(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rbx
leaq _Z12testFilenameB5cxx11(%rip), %rsi
movq %rbx, %rdi
.LEHB16:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1ERKS4_@PLT
.LEHE16:
leaq testLines(%rip), %rsi
movq %rbx, %rdi
.LEHB17:
call _Z8readFileNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPt
.LEHE17:
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq _Z13trainFilenameB5cxx11(%rip), %rsi
movq %rbx, %rdi
.LEHB18:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1ERKS4_@PLT
.LEHE18:
leaq trainLines(%rip), %rsi
movq %rbx, %rdi
.LEHB19:
call _Z8readFileNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPt
.LEHE19:
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movl $2000, %edi
call malloc@PLT
movq %rax, %r15
movq %rsp, %rdi
movl $32000, %esi
.LEHB20:
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $608000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $32000, %edx
leaq testLines(%rip), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $608000, %edx
leaq trainLines(%rip), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movq %r15, %rdx
movq (%rsp), %rsi
movq 8(%rsp), %rdi
call _Z19getNearestNeighborsPsS_Pt
movq %rbx, %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev@PLT
.LEHE20:
movl $16, %edx
movq _Z14outputFilenameB5cxx11(%rip), %rsi
movq %rbx, %rdi
.LEHB21:
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
movq %r15, %r12
leaq 2000(%r15), %r14
movq %rbx, %r13
jmp .L130
.L148:
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L144
cmpb $0, 56(%rbp)
je .L128
movzbl 67(%rbp), %esi
.L129:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
jmp .L145
.L144:
movq 536(%rsp), %rax
subq %fs:40, %rax
jne .L146
call _ZSt16__throw_bad_castv@PLT
.L140:
endbr64
movq %rax, %rbx
leaq 16(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 536(%rsp), %rax
subq %fs:40, %rax
je .L136
call __stack_chk_fail@PLT
.L146:
call __stack_chk_fail@PLT
.L128:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L129
.L145:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $2, %r12
cmpq %r14, %r12
je .L147
.L130:
movzwl (%r12), %esi
movq %r13, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
jmp .L148
.L147:
movq %r15, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
.LEHE21:
leaq 16(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 536(%rsp), %rax
subq %fs:40, %rax
jne .L149
movl $1, %eax
addq $552, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L138:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 16(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 536(%rsp), %rax
subq %fs:40, %rax
je .L132
call __stack_chk_fail@PLT
.L132:
movq %rbx, %rdi
.LEHB22:
call _Unwind_Resume@PLT
.L139:
endbr64
movq %rax, %rbx
leaq 16(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 536(%rsp), %rax
subq %fs:40, %rax
je .L134
call __stack_chk_fail@PLT
.L134:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L136:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE22:
.L149:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3804:
.section .gcc_except_table
.LLSDA3804:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3804-.LLSDACSB3804
.LLSDACSB3804:
.uleb128 .LEHB16-.LFB3804
.uleb128 .LEHE16-.LEHB16
.uleb128 0
.uleb128 0
.uleb128 .LEHB17-.LFB3804
.uleb128 .LEHE17-.LEHB17
.uleb128 .L138-.LFB3804
.uleb128 0
.uleb128 .LEHB18-.LFB3804
.uleb128 .LEHE18-.LEHB18
.uleb128 0
.uleb128 0
.uleb128 .LEHB19-.LFB3804
.uleb128 .LEHE19-.LEHB19
.uleb128 .L139-.LFB3804
.uleb128 0
.uleb128 .LEHB20-.LFB3804
.uleb128 .LEHE20-.LEHB20
.uleb128 0
.uleb128 0
.uleb128 .LEHB21-.LFB3804
.uleb128 .LEHE21-.LEHB21
.uleb128 .L140-.LFB3804
.uleb128 0
.uleb128 .LEHB22-.LFB3804
.uleb128 .LEHE22-.LEHB22
.uleb128 0
.uleb128 0
.LLSDACSE3804:
.text
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "test.txt"
.LC6:
.string "train.txt"
.LC7:
.string "myout.txt"
.text
.type _GLOBAL__sub_I_testLines, @function
_GLOBAL__sub_I_testLines:
.LFB4542:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 7(%rsp), %r12
movq %r12, %rdx
leaq .LC5(%rip), %rsi
leaq _Z12testFilenameB5cxx11(%rip), %rbx
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
leaq __dso_handle(%rip), %rbp
movq %rbp, %rdx
movq %rbx, %rsi
movq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED1Ev@GOTPCREL(%rip), %rbx
movq %rbx, %rdi
call __cxa_atexit@PLT
movq %r12, %rdx
leaq .LC6(%rip), %rsi
leaq _Z13trainFilenameB5cxx11(%rip), %r13
movq %r13, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
movq %rbp, %rdx
movq %r13, %rsi
movq %rbx, %rdi
call __cxa_atexit@PLT
movq %r12, %rdx
leaq .LC7(%rip), %rsi
leaq _Z14outputFilenameB5cxx11(%rip), %r12
movq %r12, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
movq %rbp, %rdx
movq %r12, %rsi
movq %rbx, %rdi
call __cxa_atexit@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L153
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L153:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4542:
.size _GLOBAL__sub_I_testLines, .-_GLOBAL__sub_I_testLines
.section .init_array
.align 8
.quad _GLOBAL__sub_I_testLines
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl _Z14outputFilenameB5cxx11
.bss
.align 32
.type _Z14outputFilenameB5cxx11, @object
.size _Z14outputFilenameB5cxx11, 32
_Z14outputFilenameB5cxx11:
.zero 32
.globl _Z13trainFilenameB5cxx11
.align 32
.type _Z13trainFilenameB5cxx11, @object
.size _Z13trainFilenameB5cxx11, 32
_Z13trainFilenameB5cxx11:
.zero 32
.globl _Z12testFilenameB5cxx11
.align 32
.type _Z12testFilenameB5cxx11, @object
.size _Z12testFilenameB5cxx11, 32
_Z12testFilenameB5cxx11:
.zero 32
.globl trainLines
.align 32
.type trainLines, @object
.size trainLines, 608000
trainLines:
.zero 608000
.globl testLines
.align 32
.type testLines, @object
.size testLines, 32000
testLines:
.zero 32000
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.hidden __dso_handle
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <string>
#include <iostream>
#include <cmath>
#include <climits>
#include <fstream>
//const int N = 512;
using namespace::std;
const int BLOCKS = 19000;
const int DIMENSIONS = 16;
const int TESTLINES = 1000;
unsigned short int testLines[TESTLINES*DIMENSIONS];
unsigned short int trainLines[BLOCKS*DIMENSIONS];
string testFilename = "test.txt";
string trainFilename = "train.txt";
string outputFilename = "myout.txt";
void parseLine(string line, int startIndex, unsigned short int* arr) {
int start=0;
int numIndex = startIndex;
for (size_t i = 0; i < line.length(); i++) {
if (line[i] == ',') {
arr[numIndex] = stoi(line.substr(start, i-start));
numIndex++;
start = i+1;
}
}
arr[numIndex] = stoi(line.substr(start, line.length()-start));
}
void readFile(string filename, unsigned short int* arr){
ifstream inputFile;
inputFile.open(filename.c_str());
int ind = 0;
string line;
while (getline(inputFile, line)) {
parseLine(line, ind*DIMENSIONS, arr);
ind++;
}
}
__global__
void calculateDifference(short int *trainLines,unsigned long long int *diffSquare, short int *testLines, short int id){
__shared__ unsigned int s_diffSquare;
s_diffSquare = 0;
__syncthreads();
short int other = testLines[id*DIMENSIONS + threadIdx.x];
short int self = trainLines[blockIdx.x*DIMENSIONS + threadIdx.x];
int result = other - self;
atomicAdd(&s_diffSquare, result * result);
__syncthreads();
if (threadIdx.x % DIMENSIONS == 0) {
// this will contain min with its index. Since the actual number is on the left side, comparison will be done between
// the mins. Index will have no effect except the case where two distances are equal which will return the lower index.
unsigned long long int min = (((unsigned long long int) s_diffSquare) << 32) | blockIdx.x;
atomicMin(diffSquare, min);
}
}
void getNearestNeighbors(short int *trainLines, short int *testLines,unsigned short int *result){
unsigned long long int *d_diffSquare;
unsigned long long int *diffSquare;
diffSquare = (unsigned long long int *)malloc(sizeof(unsigned long long int));
cudaMalloc((void **)&d_diffSquare, sizeof(unsigned long long int));
unsigned long long int maxLongLong = ULLONG_MAX;
for (size_t i = 0; i < TESTLINES; i++) {
cudaMemcpy(d_diffSquare, &maxLongLong, sizeof(unsigned long long int), cudaMemcpyHostToDevice);
calculateDifference<<<BLOCKS, DIMENSIONS>>>(trainLines, d_diffSquare, testLines, i);
cudaMemcpy(diffSquare, d_diffSquare, sizeof(unsigned long long int), cudaMemcpyDeviceToHost);
result[i] = (unsigned int) *diffSquare;
}
free(diffSquare);
cudaFree(d_diffSquare);
}
int main(int argc, char *argv[]) {
readFile(testFilename, testLines);
readFile(trainFilename, trainLines);
short int* d_testLines;
short int* d_trainLines;
unsigned short int* output;
int lineSize = DIMENSIONS * sizeof(short int);
int trainLinesSize = BLOCKS * lineSize;
int testLinesSize = TESTLINES * lineSize;
output = (unsigned short int *)malloc(TESTLINES * sizeof(unsigned short int));
cudaMalloc((void **)&d_testLines, testLinesSize);
cudaMalloc((void **)&d_trainLines, trainLinesSize);
cudaMemcpy(d_testLines, testLines, testLinesSize, cudaMemcpyHostToDevice);
cudaMemcpy(d_trainLines, trainLines, trainLinesSize, cudaMemcpyHostToDevice);
getNearestNeighbors(d_trainLines, d_testLines, output);
ofstream outputFile;
outputFile.open(outputFilename.c_str());
for (size_t i = 0; i < TESTLINES; i++) {
outputFile << output[i] << endl;
}
free(output);
cudaFree(d_testLines); cudaFree(d_trainLines);
return 1;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string>
#include <iostream>
#include <cmath>
#include <climits>
#include <fstream>
//const int N = 512;
using namespace::std;
const int BLOCKS = 19000;
const int DIMENSIONS = 16;
const int TESTLINES = 1000;
unsigned short int testLines[TESTLINES*DIMENSIONS];
unsigned short int trainLines[BLOCKS*DIMENSIONS];
string testFilename = "test.txt";
string trainFilename = "train.txt";
string outputFilename = "myout.txt";
void parseLine(string line, int startIndex, unsigned short int* arr) {
int start=0;
int numIndex = startIndex;
for (size_t i = 0; i < line.length(); i++) {
if (line[i] == ',') {
arr[numIndex] = stoi(line.substr(start, i-start));
numIndex++;
start = i+1;
}
}
arr[numIndex] = stoi(line.substr(start, line.length()-start));
}
void readFile(string filename, unsigned short int* arr){
ifstream inputFile;
inputFile.open(filename.c_str());
int ind = 0;
string line;
while (getline(inputFile, line)) {
parseLine(line, ind*DIMENSIONS, arr);
ind++;
}
}
__global__
void calculateDifference(short int *trainLines,unsigned long long int *diffSquare, short int *testLines, short int id){
__shared__ unsigned int s_diffSquare;
s_diffSquare = 0;
__syncthreads();
short int other = testLines[id*DIMENSIONS + threadIdx.x];
short int self = trainLines[blockIdx.x*DIMENSIONS + threadIdx.x];
int result = other - self;
atomicAdd(&s_diffSquare, result * result);
__syncthreads();
if (threadIdx.x % DIMENSIONS == 0) {
// this will contain min with its index. Since the actual number is on the left side, comparison will be done between
// the mins. Index will have no effect except the case where two distances are equal which will return the lower index.
unsigned long long int min = (((unsigned long long int) s_diffSquare) << 32) | blockIdx.x;
atomicMin(diffSquare, min);
}
}
void getNearestNeighbors(short int *trainLines, short int *testLines,unsigned short int *result){
unsigned long long int *d_diffSquare;
unsigned long long int *diffSquare;
diffSquare = (unsigned long long int *)malloc(sizeof(unsigned long long int));
hipMalloc((void **)&d_diffSquare, sizeof(unsigned long long int));
unsigned long long int maxLongLong = ULLONG_MAX;
for (size_t i = 0; i < TESTLINES; i++) {
hipMemcpy(d_diffSquare, &maxLongLong, sizeof(unsigned long long int), hipMemcpyHostToDevice);
calculateDifference<<<BLOCKS, DIMENSIONS>>>(trainLines, d_diffSquare, testLines, i);
hipMemcpy(diffSquare, d_diffSquare, sizeof(unsigned long long int), hipMemcpyDeviceToHost);
result[i] = (unsigned int) *diffSquare;
}
free(diffSquare);
hipFree(d_diffSquare);
}
int main(int argc, char *argv[]) {
readFile(testFilename, testLines);
readFile(trainFilename, trainLines);
short int* d_testLines;
short int* d_trainLines;
unsigned short int* output;
int lineSize = DIMENSIONS * sizeof(short int);
int trainLinesSize = BLOCKS * lineSize;
int testLinesSize = TESTLINES * lineSize;
output = (unsigned short int *)malloc(TESTLINES * sizeof(unsigned short int));
hipMalloc((void **)&d_testLines, testLinesSize);
hipMalloc((void **)&d_trainLines, trainLinesSize);
hipMemcpy(d_testLines, testLines, testLinesSize, hipMemcpyHostToDevice);
hipMemcpy(d_trainLines, trainLines, trainLinesSize, hipMemcpyHostToDevice);
getNearestNeighbors(d_trainLines, d_testLines, output);
ofstream outputFile;
outputFile.open(outputFilename.c_str());
for (size_t i = 0; i < TESTLINES; i++) {
outputFile << output[i] << endl;
}
free(output);
hipFree(d_testLines); hipFree(d_trainLines);
return 1;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string>
#include <iostream>
#include <cmath>
#include <climits>
#include <fstream>
//const int N = 512;
using namespace::std;
const int BLOCKS = 19000;
const int DIMENSIONS = 16;
const int TESTLINES = 1000;
unsigned short int testLines[TESTLINES*DIMENSIONS];
unsigned short int trainLines[BLOCKS*DIMENSIONS];
string testFilename = "test.txt";
string trainFilename = "train.txt";
string outputFilename = "myout.txt";
void parseLine(string line, int startIndex, unsigned short int* arr) {
int start=0;
int numIndex = startIndex;
for (size_t i = 0; i < line.length(); i++) {
if (line[i] == ',') {
arr[numIndex] = stoi(line.substr(start, i-start));
numIndex++;
start = i+1;
}
}
arr[numIndex] = stoi(line.substr(start, line.length()-start));
}
void readFile(string filename, unsigned short int* arr){
ifstream inputFile;
inputFile.open(filename.c_str());
int ind = 0;
string line;
while (getline(inputFile, line)) {
parseLine(line, ind*DIMENSIONS, arr);
ind++;
}
}
__global__
void calculateDifference(short int *trainLines,unsigned long long int *diffSquare, short int *testLines, short int id){
__shared__ unsigned int s_diffSquare;
s_diffSquare = 0;
__syncthreads();
short int other = testLines[id*DIMENSIONS + threadIdx.x];
short int self = trainLines[blockIdx.x*DIMENSIONS + threadIdx.x];
int result = other - self;
atomicAdd(&s_diffSquare, result * result);
__syncthreads();
if (threadIdx.x % DIMENSIONS == 0) {
// this will contain min with its index. Since the actual number is on the left side, comparison will be done between
// the mins. Index will have no effect except the case where two distances are equal which will return the lower index.
unsigned long long int min = (((unsigned long long int) s_diffSquare) << 32) | blockIdx.x;
atomicMin(diffSquare, min);
}
}
void getNearestNeighbors(short int *trainLines, short int *testLines,unsigned short int *result){
unsigned long long int *d_diffSquare;
unsigned long long int *diffSquare;
diffSquare = (unsigned long long int *)malloc(sizeof(unsigned long long int));
hipMalloc((void **)&d_diffSquare, sizeof(unsigned long long int));
unsigned long long int maxLongLong = ULLONG_MAX;
for (size_t i = 0; i < TESTLINES; i++) {
hipMemcpy(d_diffSquare, &maxLongLong, sizeof(unsigned long long int), hipMemcpyHostToDevice);
calculateDifference<<<BLOCKS, DIMENSIONS>>>(trainLines, d_diffSquare, testLines, i);
hipMemcpy(diffSquare, d_diffSquare, sizeof(unsigned long long int), hipMemcpyDeviceToHost);
result[i] = (unsigned int) *diffSquare;
}
free(diffSquare);
hipFree(d_diffSquare);
}
int main(int argc, char *argv[]) {
readFile(testFilename, testLines);
readFile(trainFilename, trainLines);
short int* d_testLines;
short int* d_trainLines;
unsigned short int* output;
int lineSize = DIMENSIONS * sizeof(short int);
int trainLinesSize = BLOCKS * lineSize;
int testLinesSize = TESTLINES * lineSize;
output = (unsigned short int *)malloc(TESTLINES * sizeof(unsigned short int));
hipMalloc((void **)&d_testLines, testLinesSize);
hipMalloc((void **)&d_trainLines, trainLinesSize);
hipMemcpy(d_testLines, testLines, testLinesSize, hipMemcpyHostToDevice);
hipMemcpy(d_trainLines, trainLines, trainLinesSize, hipMemcpyHostToDevice);
getNearestNeighbors(d_trainLines, d_testLines, output);
ofstream outputFile;
outputFile.open(outputFilename.c_str());
for (size_t i = 0; i < TESTLINES; i++) {
outputFile << output[i] << endl;
}
free(output);
hipFree(d_testLines); hipFree(d_trainLines);
return 1;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19calculateDifferencePsPyS_s
.globl _Z19calculateDifferencePsPyS_s
.p2align 8
.type _Z19calculateDifferencePsPyS_s,@function
_Z19calculateDifferencePsPyS_s:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x18
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b64 s[6:7], s[0:1], 0x0
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, 0
s_mov_b32 s2, exec_lo
ds_store_b32 v5, v5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_sext_i32_i16 s3, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshl_add_u32 v1, s3, 4, v0
s_mov_b32 s3, 0
v_lshlrev_b64 v[3:4], 1, v[1:2]
v_lshl_add_u32 v1, s15, 4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[1:2], 1, v[1:2]
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v1, vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_i16 v3, v[3:4], off
global_load_i16 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v1, v3, v1
v_mul_i32_i24_e32 v1, v1, v1
.LBB0_1:
s_ctz_i32_b32 s4, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_readlane_b32 s5, v1, s4
s_lshl_b32 s4, 1, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_not1_b32 s2, s2, s4
s_add_i32 s3, s3, s5
s_cmp_lg_u32 s2, 0
s_cbranch_scc1 .LBB0_1
v_mbcnt_lo_u32_b32 v1, exec_lo, 0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v1
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB0_4
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s3
ds_add_u32 v1, v2
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s2
v_and_b32_e32 v0, 15, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v2, 0
s_load_b64 s[0:1], s[0:1], 0x8
v_mov_b32_e32 v0, s15
ds_load_b32 v1, v2
s_waitcnt lgkmcnt(0)
global_atomic_min_u64 v2, v[0:1], s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19calculateDifferencePsPyS_s
.amdhsa_group_segment_fixed_size 4
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19calculateDifferencePsPyS_s, .Lfunc_end0-_Z19calculateDifferencePsPyS_s
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 2
.value_kind: by_value
.group_segment_fixed_size: 4
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19calculateDifferencePsPyS_s
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19calculateDifferencePsPyS_s.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string>
#include <iostream>
#include <cmath>
#include <climits>
#include <fstream>
//const int N = 512;
using namespace::std;
const int BLOCKS = 19000;
const int DIMENSIONS = 16;
const int TESTLINES = 1000;
unsigned short int testLines[TESTLINES*DIMENSIONS];
unsigned short int trainLines[BLOCKS*DIMENSIONS];
string testFilename = "test.txt";
string trainFilename = "train.txt";
string outputFilename = "myout.txt";
void parseLine(string line, int startIndex, unsigned short int* arr) {
int start=0;
int numIndex = startIndex;
for (size_t i = 0; i < line.length(); i++) {
if (line[i] == ',') {
arr[numIndex] = stoi(line.substr(start, i-start));
numIndex++;
start = i+1;
}
}
arr[numIndex] = stoi(line.substr(start, line.length()-start));
}
void readFile(string filename, unsigned short int* arr){
ifstream inputFile;
inputFile.open(filename.c_str());
int ind = 0;
string line;
while (getline(inputFile, line)) {
parseLine(line, ind*DIMENSIONS, arr);
ind++;
}
}
__global__
void calculateDifference(short int *trainLines,unsigned long long int *diffSquare, short int *testLines, short int id){
__shared__ unsigned int s_diffSquare;
s_diffSquare = 0;
__syncthreads();
short int other = testLines[id*DIMENSIONS + threadIdx.x];
short int self = trainLines[blockIdx.x*DIMENSIONS + threadIdx.x];
int result = other - self;
atomicAdd(&s_diffSquare, result * result);
__syncthreads();
if (threadIdx.x % DIMENSIONS == 0) {
// this will contain min with its index. Since the actual number is on the left side, comparison will be done between
// the mins. Index will have no effect except the case where two distances are equal which will return the lower index.
unsigned long long int min = (((unsigned long long int) s_diffSquare) << 32) | blockIdx.x;
atomicMin(diffSquare, min);
}
}
void getNearestNeighbors(short int *trainLines, short int *testLines,unsigned short int *result){
unsigned long long int *d_diffSquare;
unsigned long long int *diffSquare;
diffSquare = (unsigned long long int *)malloc(sizeof(unsigned long long int));
hipMalloc((void **)&d_diffSquare, sizeof(unsigned long long int));
unsigned long long int maxLongLong = ULLONG_MAX;
for (size_t i = 0; i < TESTLINES; i++) {
hipMemcpy(d_diffSquare, &maxLongLong, sizeof(unsigned long long int), hipMemcpyHostToDevice);
calculateDifference<<<BLOCKS, DIMENSIONS>>>(trainLines, d_diffSquare, testLines, i);
hipMemcpy(diffSquare, d_diffSquare, sizeof(unsigned long long int), hipMemcpyDeviceToHost);
result[i] = (unsigned int) *diffSquare;
}
free(diffSquare);
hipFree(d_diffSquare);
}
int main(int argc, char *argv[]) {
readFile(testFilename, testLines);
readFile(trainFilename, trainLines);
short int* d_testLines;
short int* d_trainLines;
unsigned short int* output;
int lineSize = DIMENSIONS * sizeof(short int);
int trainLinesSize = BLOCKS * lineSize;
int testLinesSize = TESTLINES * lineSize;
output = (unsigned short int *)malloc(TESTLINES * sizeof(unsigned short int));
hipMalloc((void **)&d_testLines, testLinesSize);
hipMalloc((void **)&d_trainLines, trainLinesSize);
hipMemcpy(d_testLines, testLines, testLinesSize, hipMemcpyHostToDevice);
hipMemcpy(d_trainLines, trainLines, trainLinesSize, hipMemcpyHostToDevice);
getNearestNeighbors(d_trainLines, d_testLines, output);
ofstream outputFile;
outputFile.open(outputFilename.c_str());
for (size_t i = 0; i < TESTLINES; i++) {
outputFile << output[i] << endl;
}
free(output);
hipFree(d_testLines); hipFree(d_trainLines);
return 1;
} | .text
.file "bfs.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev,comdat
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev # -- Begin function _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev
.p2align 4, 0x90
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev,@function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev: # @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev
.cfi_startproc
# %bb.0:
movq %rdi, %rax
movq (%rdi), %rdi
addq $16, %rax
cmpq %rax, %rdi
jne _ZdlPv # TAILCALL
# %bb.1: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv.exit
retq
.Lfunc_end0:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev, .Lfunc_end0-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev
.cfi_endproc
# -- End function
.text
.globl _Z9parseLineNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEiPt # -- Begin function _Z9parseLineNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEiPt
.p2align 4, 0x90
.type _Z9parseLineNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEiPt,@function
_Z9parseLineNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEiPt: # @_Z9parseLineNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEiPt
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $56, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, 48(%rsp) # 8-byte Spill
movl %esi, %ebp
movq %rdi, %r14
movq 8(%rdi), %rcx
xorl %r12d, %r12d
testq %rcx, %rcx
je .LBB1_6
# %bb.1: # %.lr.ph
xorl %ebx, %ebx
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_54: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
# in Loop: Header=BB1_2 Depth=1
incl %ebp
leal 1(%rbx), %r12d
.LBB1_55: # in Loop: Header=BB1_2 Depth=1
incq %rbx
movq 8(%r14), %rcx
cmpq %rcx, %rbx
jae .LBB1_5
.LBB1_2: # =>This Inner Loop Header: Depth=1
movq (%r14), %r13
cmpb $44, (%r13,%rbx)
jne .LBB1_55
# %bb.3: # in Loop: Header=BB1_2 Depth=1
movslq %r12d, %r15
movq %rcx, %rax
subq %r15, %rax
jb .LBB1_4
# %bb.30: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6substrEmm.exit22
# in Loop: Header=BB1_2 Depth=1
movq %rbx, %r12
subq %r15, %r12
leaq 24(%rsp), %rcx
movq %rcx, 8(%rsp)
cmpq %r12, %rax
cmovbq %rax, %r12
cmpq $16, %r12
jb .LBB1_34
# %bb.31: # in Loop: Header=BB1_2 Depth=1
testq %r12, %r12
js .LBB1_57
# %bb.32: # in Loop: Header=BB1_2 Depth=1
movq %r12, %rdi
incq %rdi
js .LBB1_58
# %bb.33: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i41
# in Loop: Header=BB1_2 Depth=1
callq _Znwm
movq %rax, 8(%rsp)
movq %r12, 24(%rsp)
.LBB1_34: # in Loop: Header=BB1_2 Depth=1
testq %r12, %r12
je .LBB1_38
# %bb.35: # in Loop: Header=BB1_2 Depth=1
addq %r15, %r13
movq 8(%rsp), %rdi
cmpq $1, %r12
jne .LBB1_37
# %bb.36: # in Loop: Header=BB1_2 Depth=1
movzbl (%r13), %eax
movb %al, (%rdi)
jmp .LBB1_38
.LBB1_37: # in Loop: Header=BB1_2 Depth=1
movq %r13, %rsi
movq %r12, %rdx
callq memcpy@PLT
.LBB1_38: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2ERKS4_mm.exit45
# in Loop: Header=BB1_2 Depth=1
movq %r12, 16(%rsp)
movq 8(%rsp), %rax
movb $0, (%rax,%r12)
movq 8(%rsp), %r15
callq __errno_location
movq %rax, %r12
movl (%rax), %r13d
movl $0, (%rax)
movq %r15, %rdi
leaq 40(%rsp), %rsi
movl $10, %edx
callq __isoc23_strtol
cmpq %r15, 40(%rsp)
je .LBB1_39
# %bb.46: # in Loop: Header=BB1_2 Depth=1
leaq -2147483648(%rax), %rcx
movabsq $-4294967296, %rdx # imm = 0xFFFFFFFF00000000
cmpq %rdx, %rcx
jb .LBB1_48
# %bb.47: # in Loop: Header=BB1_2 Depth=1
movl (%r12), %ecx
cmpl $34, %ecx
je .LBB1_48
# %bb.50: # in Loop: Header=BB1_2 Depth=1
testl %ecx, %ecx
jne .LBB1_52
# %bb.51: # in Loop: Header=BB1_2 Depth=1
movl %r13d, (%r12)
.LBB1_52: # %_ZNSt7__cxx114stoiERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEPmi.exit28
# in Loop: Header=BB1_2 Depth=1
movslq %ebp, %rcx
movq 48(%rsp), %rdx # 8-byte Reload
movw %ax, (%rdx,%rcx,2)
movq 8(%rsp), %rdi
leaq 24(%rsp), %rax
cmpq %rax, %rdi
je .LBB1_54
# %bb.53: # %.critedge.i.i29
# in Loop: Header=BB1_2 Depth=1
callq _ZdlPv
jmp .LBB1_54
.LBB1_5: # %._crit_edge.loopexit
movslq %r12d, %r12
.LBB1_6: # %._crit_edge
movq %rcx, %r15
subq %r12, %r15
jb .LBB1_56
# %bb.7: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6substrEmm.exit
leaq 24(%rsp), %rbx
movq %rbx, 8(%rsp)
addq (%r14), %r12
cmpq $16, %r15
jb .LBB1_11
# %bb.8:
testq %r15, %r15
js .LBB1_57
# %bb.9:
movq %r15, %rdi
incq %rdi
js .LBB1_58
# %bb.10: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i
callq _Znwm
movq %rax, 8(%rsp)
movq %r15, 24(%rsp)
.LBB1_11:
testq %r15, %r15
je .LBB1_15
# %bb.12:
movq 8(%rsp), %rdi
cmpq $1, %r15
jne .LBB1_14
# %bb.13:
movzbl (%r12), %eax
movb %al, (%rdi)
jmp .LBB1_15
.LBB1_14:
movq %r12, %rsi
movq %r15, %rdx
callq memcpy@PLT
.LBB1_15: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2ERKS4_mm.exit
movq %r15, 16(%rsp)
movq 8(%rsp), %rax
movb $0, (%rax,%r15)
movq 8(%rsp), %r15
callq __errno_location
movq %rax, %r14
movl (%rax), %r12d
movl $0, (%rax)
leaq 40(%rsp), %rsi
movq %r15, %rdi
movl $10, %edx
callq __isoc23_strtol
cmpq %r15, 40(%rsp)
je .LBB1_16
# %bb.21:
leaq -2147483648(%rax), %rcx
movabsq $-4294967296, %rdx # imm = 0xFFFFFFFF00000000
cmpq %rdx, %rcx
jb .LBB1_23
# %bb.22:
movl (%r14), %ecx
cmpl $34, %ecx
je .LBB1_23
# %bb.25:
testl %ecx, %ecx
jne .LBB1_27
# %bb.26:
movl %r12d, (%r14)
.LBB1_27: # %_ZNSt7__cxx114stoiERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEPmi.exit
movslq %ebp, %rcx
movq 48(%rsp), %rdx # 8-byte Reload
movw %ax, (%rdx,%rcx,2)
movq 8(%rsp), %rdi
cmpq %rbx, %rdi
je .LBB1_29
# %bb.28: # %.critedge.i.i33
callq _ZdlPv
.LBB1_29: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit35
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_58: # %.noexc11.i
.cfi_def_cfa_offset 112
callq _ZSt17__throw_bad_allocv
.LBB1_4:
movl $.L.str.7, %edi
movl $.L.str.6, %esi
movq %r15, %rdx
xorl %eax, %eax
callq _ZSt24__throw_out_of_range_fmtPKcz
.LBB1_48: # %.critedge.i.i24
.Ltmp0:
movl $.L.str, %edi
callq _ZSt20__throw_out_of_rangePKc
.Ltmp1:
# %bb.49:
.LBB1_39:
.Ltmp2:
movl $.L.str, %edi
callq _ZSt24__throw_invalid_argumentPKc
.Ltmp3:
# %bb.40:
.LBB1_57: # %.noexc10.i
movl $.L.str.9, %edi
callq _ZSt20__throw_length_errorPKc
.LBB1_56:
movl $.L.str.7, %edi
movl $.L.str.6, %esi
movq %r12, %rdx
xorl %eax, %eax
callq _ZSt24__throw_out_of_range_fmtPKcz
.LBB1_16:
.Ltmp7:
movl $.L.str, %edi
callq _ZSt24__throw_invalid_argumentPKc
.Ltmp8:
# %bb.17:
.LBB1_23: # %.critedge.i.i
.Ltmp5:
movl $.L.str, %edi
callq _ZSt20__throw_out_of_rangePKc
.Ltmp6:
# %bb.24:
.LBB1_18:
.Ltmp9:
movq %rax, %r15
cmpl $0, (%r14)
jne .LBB1_20
# %bb.19:
movl %r12d, (%r14)
.LBB1_20: # %_ZZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_EN11_Save_errnoD2Ev.exit.i.i
movq 8(%rsp), %rdi
cmpq %rbx, %rdi
jne .LBB1_44
jmp .LBB1_45
.LBB1_41:
.Ltmp4:
movq %rax, %r15
cmpl $0, (%r12)
jne .LBB1_43
# %bb.42:
movl %r13d, (%r12)
.LBB1_43: # %_ZZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_EN11_Save_errnoD2Ev.exit.i.i25
movq 8(%rsp), %rdi
leaq 24(%rsp), %rax
cmpq %rax, %rdi
je .LBB1_45
.LBB1_44: # %.critedge.i.i30
callq _ZdlPv
.LBB1_45:
movq %r15, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size _Z9parseLineNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEiPt, .Lfunc_end1-_Z9parseLineNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEiPt
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp3-.Ltmp0 # Call between .Ltmp0 and .Ltmp3
.uleb128 .Ltmp4-.Lfunc_begin0 # jumps to .Ltmp4
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp7-.Ltmp3 # Call between .Ltmp3 and .Ltmp7
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp7-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp6-.Ltmp7 # Call between .Ltmp7 and .Ltmp6
.uleb128 .Ltmp9-.Lfunc_begin0 # jumps to .Ltmp9
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Lfunc_end1-.Ltmp6 # Call between .Ltmp6 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.globl _Z8readFileNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPt # -- Begin function _Z8readFileNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPt
.p2align 4, 0x90
.type _Z8readFileNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPt,@function
_Z8readFileNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPt: # @_Z8readFileNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPt
.Lfunc_begin1:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception1
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $584, %rsp # imm = 0x248
.cfi_def_cfa_offset 640
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq %rdi, %r15
leaq 64(%rsp), %r14
movq %r14, %rdi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1Ev
movq (%r15), %rsi
leaq 80(%rsp), %rdi
.Ltmp10:
movl $8, %edx
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp11:
# %bb.1: # %.noexc
movq 64(%rsp), %rcx
addq -24(%rcx), %r14
xorl %esi, %esi
testq %rax, %rax
jne .LBB2_3
# %bb.2:
movl 32(%r14), %esi
orl $4, %esi
.LBB2_3: # %.invoke
.Ltmp12:
movq %r14, %rdi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp13:
# %bb.4: # %_ZNSt14basic_ifstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit
leaq 16(%rsp), %rax
movq %rax, (%rsp)
movq $0, 8(%rsp)
movb $0, 16(%rsp)
movq 64(%rsp), %rax
movq -24(%rax), %rax
movq 304(%rsp,%rax), %r13
testq %r13, %r13
je .LBB2_8
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i.lr.ph
xorl %ebp, %ebp
leaq 48(%rsp), %r14
movq %rsp, %r15
jmp .LBB2_6
.p2align 4, 0x90
.LBB2_30: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
# in Loop: Header=BB2_6 Depth=1
movq 64(%rsp), %rax
movq -24(%rax), %rax
movq 304(%rsp,%rax), %r13
addl $16, %ebp
testq %r13, %r13
je .LBB2_8
.LBB2_6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# =>This Inner Loop Header: Depth=1
cmpb $0, 56(%r13)
je .LBB2_10
# %bb.7: # in Loop: Header=BB2_6 Depth=1
movzbl 67(%r13), %eax
jmp .LBB2_12
.p2align 4, 0x90
.LBB2_10: # in Loop: Header=BB2_6 Depth=1
.Ltmp15:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp16:
# %bb.11: # %.noexc12
# in Loop: Header=BB2_6 Depth=1
movq (%r13), %rax
.Ltmp17:
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp18:
.LBB2_12: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
# in Loop: Header=BB2_6 Depth=1
.Ltmp19:
movsbl %al, %edx
leaq 64(%rsp), %rdi
movq %r15, %rsi
callq _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EES4_
.Ltmp20:
# %bb.13: # %_ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE.exit
# in Loop: Header=BB2_6 Depth=1
movq (%rax), %rcx
movq -24(%rcx), %rcx
testb $5, 32(%rax,%rcx)
jne .LBB2_35
# %bb.14: # in Loop: Header=BB2_6 Depth=1
movq %r14, 32(%rsp)
movq (%rsp), %r12
movq 8(%rsp), %r13
cmpq $16, %r13
jb .LBB2_23
# %bb.15: # in Loop: Header=BB2_6 Depth=1
testq %r13, %r13
js .LBB2_16
# %bb.18: # in Loop: Header=BB2_6 Depth=1
movq %r13, %rdi
incq %rdi
js .LBB2_19
# %bb.21: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i
# in Loop: Header=BB2_6 Depth=1
.Ltmp21:
callq _Znwm
.Ltmp22:
# %bb.22: # %.noexc18
# in Loop: Header=BB2_6 Depth=1
movq %rax, 32(%rsp)
movq %r13, 48(%rsp)
.LBB2_23: # in Loop: Header=BB2_6 Depth=1
testq %r13, %r13
je .LBB2_27
# %bb.24: # in Loop: Header=BB2_6 Depth=1
movq 32(%rsp), %rdi
cmpq $1, %r13
jne .LBB2_26
# %bb.25: # in Loop: Header=BB2_6 Depth=1
movzbl (%r12), %eax
movb %al, (%rdi)
jmp .LBB2_27
.p2align 4, 0x90
.LBB2_26: # in Loop: Header=BB2_6 Depth=1
movq %r12, %rsi
movq %r13, %rdx
callq memcpy@PLT
.LBB2_27: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2ERKS4_.exit
# in Loop: Header=BB2_6 Depth=1
movq %r13, 40(%rsp)
movq 32(%rsp), %rax
movb $0, (%rax,%r13)
.Ltmp24:
leaq 32(%rsp), %rdi
movl %ebp, %esi
movq %rbx, %rdx
callq _Z9parseLineNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEiPt
.Ltmp25:
# %bb.28: # in Loop: Header=BB2_6 Depth=1
movq 32(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_30
# %bb.29: # %.critedge.i.i
# in Loop: Header=BB2_6 Depth=1
callq _ZdlPv
jmp .LBB2_30
.LBB2_35:
movq (%rsp), %rdi
leaq 16(%rsp), %rax
cmpq %rax, %rdi
je .LBB2_37
# %bb.36: # %.critedge.i.i22
callq _ZdlPv
.LBB2_37: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit24
leaq 64(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 320(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
addq $584, %rsp # imm = 0x248
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_19: # %.noexc6.i
.cfi_def_cfa_offset 640
.Ltmp27:
callq _ZSt17__throw_bad_allocv
.Ltmp28:
# %bb.20: # %.noexc17
.LBB2_8: # %._crit_edge
.Ltmp31:
callq _ZSt16__throw_bad_castv
.Ltmp32:
# %bb.9: # %.noexc11
.LBB2_16: # %.noexc.i
.Ltmp29:
movl $.L.str.9, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp30:
# %bb.17: # %.noexc16
.LBB2_31:
.Ltmp14:
movq %rax, %rbx
jmp .LBB2_42
.LBB2_33:
.Ltmp26:
movq %rax, %rbx
movq 32(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_40
# %bb.34: # %.critedge.i.i19
callq _ZdlPv
jmp .LBB2_40
.LBB2_38: # %.loopexit
.Ltmp23:
jmp .LBB2_39
.LBB2_32: # %.loopexit.split-lp
.Ltmp33:
.LBB2_39: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit21
movq %rax, %rbx
.LBB2_40: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit21
movq (%rsp), %rdi
leaq 16(%rsp), %rax
cmpq %rax, %rdi
je .LBB2_42
# %bb.41: # %.critedge.i.i25
callq _ZdlPv
.LBB2_42:
leaq 64(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 320(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size _Z8readFileNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPt, .Lfunc_end2-_Z8readFileNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPt
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception1:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end1-.Lcst_begin1
.Lcst_begin1:
.uleb128 .Lfunc_begin1-.Lfunc_begin1 # >> Call Site 1 <<
.uleb128 .Ltmp10-.Lfunc_begin1 # Call between .Lfunc_begin1 and .Ltmp10
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp10-.Lfunc_begin1 # >> Call Site 2 <<
.uleb128 .Ltmp13-.Ltmp10 # Call between .Ltmp10 and .Ltmp13
.uleb128 .Ltmp14-.Lfunc_begin1 # jumps to .Ltmp14
.byte 0 # On action: cleanup
.uleb128 .Ltmp15-.Lfunc_begin1 # >> Call Site 3 <<
.uleb128 .Ltmp22-.Ltmp15 # Call between .Ltmp15 and .Ltmp22
.uleb128 .Ltmp23-.Lfunc_begin1 # jumps to .Ltmp23
.byte 0 # On action: cleanup
.uleb128 .Ltmp22-.Lfunc_begin1 # >> Call Site 4 <<
.uleb128 .Ltmp24-.Ltmp22 # Call between .Ltmp22 and .Ltmp24
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp24-.Lfunc_begin1 # >> Call Site 5 <<
.uleb128 .Ltmp25-.Ltmp24 # Call between .Ltmp24 and .Ltmp25
.uleb128 .Ltmp26-.Lfunc_begin1 # jumps to .Ltmp26
.byte 0 # On action: cleanup
.uleb128 .Ltmp27-.Lfunc_begin1 # >> Call Site 6 <<
.uleb128 .Ltmp30-.Ltmp27 # Call between .Ltmp27 and .Ltmp30
.uleb128 .Ltmp33-.Lfunc_begin1 # jumps to .Ltmp33
.byte 0 # On action: cleanup
.uleb128 .Ltmp30-.Lfunc_begin1 # >> Call Site 7 <<
.uleb128 .Lfunc_end2-.Ltmp30 # Call between .Ltmp30 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end1:
.p2align 2, 0x0
# -- End function
.text
.globl _Z34__device_stub__calculateDifferencePsPyS_s # -- Begin function _Z34__device_stub__calculateDifferencePsPyS_s
.p2align 4, 0x90
.type _Z34__device_stub__calculateDifferencePsPyS_s,@function
_Z34__device_stub__calculateDifferencePsPyS_s: # @_Z34__device_stub__calculateDifferencePsPyS_s
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movw %cx, 6(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 6(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19calculateDifferencePsPyS_s, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z34__device_stub__calculateDifferencePsPyS_s, .Lfunc_end3-_Z34__device_stub__calculateDifferencePsPyS_s
.cfi_endproc
# -- End function
.globl _Z19getNearestNeighborsPsS_Pt # -- Begin function _Z19getNearestNeighborsPsS_Pt
.p2align 4, 0x90
.type _Z19getNearestNeighborsPsS_Pt,@function
_Z19getNearestNeighborsPsS_Pt: # @_Z19getNearestNeighborsPsS_Pt
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %rbx
movq %rsi, 24(%rsp) # 8-byte Spill
movq %rdi, 16(%rsp) # 8-byte Spill
movabsq $4294967312, %r12 # imm = 0x100000010
movl $8, %edi
callq malloc
movq %rax, %r13
leaq 8(%rsp), %rdi
movl $8, %esi
callq hipMalloc
movq $-1, 32(%rsp)
xorl %r15d, %r15d
leaq 32(%rsp), %rbp
leaq 18984(%r12), %r14
jmp .LBB4_1
.p2align 4, 0x90
.LBB4_3: # in Loop: Header=BB4_1 Depth=1
movq 8(%rsp), %rsi
movl $8, %edx
movq %r13, %rdi
movl $2, %ecx
callq hipMemcpy
movzwl (%r13), %eax
movw %ax, (%rbx,%r15,2)
incq %r15
cmpq $1000, %r15 # imm = 0x3E8
je .LBB4_4
.LBB4_1: # =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rdi
movl $8, %edx
movq %rbp, %rsi
movl $1, %ecx
callq hipMemcpy
movq %r14, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_3
# %bb.2: # in Loop: Header=BB4_1 Depth=1
movq 8(%rsp), %rax
movq 16(%rsp), %rcx # 8-byte Reload
movq %rcx, 104(%rsp)
movq %rax, 96(%rsp)
movq 24(%rsp), %rax # 8-byte Reload
movq %rax, 88(%rsp)
movw %r15w, 6(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 6(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z19calculateDifferencePsPyS_s, %edi
leaq 112(%rsp), %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB4_3
.LBB4_4:
movq %r13, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z19getNearestNeighborsPsS_Pt, .Lfunc_end4-_Z19getNearestNeighborsPsS_Pt
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin2:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception2
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $592, %rsp # imm = 0x250
.cfi_def_cfa_offset 640
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 64(%rsp), %r15
movq %r15, 48(%rsp)
movq _Z12testFilenameB5cxx11(%rip), %r14
movq _Z12testFilenameB5cxx11+8(%rip), %rbx
cmpq $16, %rbx
jb .LBB5_4
# %bb.1:
testq %rbx, %rbx
js .LBB5_42
# %bb.2:
movq %rbx, %rdi
incq %rdi
js .LBB5_39
# %bb.3: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i
callq _Znwm
movq %rax, 48(%rsp)
movq %rbx, 64(%rsp)
.LBB5_4:
testq %rbx, %rbx
je .LBB5_8
# %bb.5:
movq 48(%rsp), %rdi
cmpq $1, %rbx
jne .LBB5_7
# %bb.6:
movzbl (%r14), %eax
movb %al, (%rdi)
jmp .LBB5_8
.LBB5_7:
movq %r14, %rsi
movq %rbx, %rdx
callq memcpy@PLT
.LBB5_8: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2ERKS4_.exit
movq %rbx, 56(%rsp)
movq 48(%rsp), %rax
movb $0, (%rax,%rbx)
.Ltmp34:
leaq 48(%rsp), %rdi
movl $testLines, %esi
callq _Z8readFileNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPt
.Ltmp35:
# %bb.9:
movq 48(%rsp), %rdi
cmpq %r15, %rdi
je .LBB5_11
# %bb.10: # %.critedge.i.i
callq _ZdlPv
.LBB5_11: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
leaq 32(%rsp), %r15
movq %r15, 16(%rsp)
movq _Z13trainFilenameB5cxx11(%rip), %r14
movq _Z13trainFilenameB5cxx11+8(%rip), %rbx
cmpq $16, %rbx
jb .LBB5_15
# %bb.12:
testq %rbx, %rbx
js .LBB5_42
# %bb.13:
movq %rbx, %rdi
incq %rdi
js .LBB5_39
# %bb.14: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i19
callq _Znwm
movq %rax, 16(%rsp)
movq %rbx, 32(%rsp)
.LBB5_15:
testq %rbx, %rbx
je .LBB5_19
# %bb.16:
movq 16(%rsp), %rdi
cmpq $1, %rbx
jne .LBB5_18
# %bb.17:
movzbl (%r14), %eax
movb %al, (%rdi)
jmp .LBB5_19
.LBB5_18:
movq %r14, %rsi
movq %rbx, %rdx
callq memcpy@PLT
.LBB5_19: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2ERKS4_.exit22
movq %rbx, 24(%rsp)
movq 16(%rsp), %rax
movb $0, (%rax,%rbx)
.Ltmp37:
leaq 16(%rsp), %rdi
movl $trainLines, %esi
callq _Z8readFileNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPt
.Ltmp38:
# %bb.20:
movq 16(%rsp), %rdi
cmpq %r15, %rdi
je .LBB5_22
# %bb.21: # %.critedge.i.i23
callq _ZdlPv
.LBB5_22: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit25
movl $2000, %edi # imm = 0x7D0
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $32000, %esi # imm = 0x7D00
callq hipMalloc
movq %rsp, %rdi
movl $608000, %esi # imm = 0x94700
callq hipMalloc
movq 8(%rsp), %rdi
movl $testLines, %esi
movl $32000, %edx # imm = 0x7D00
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movl $trainLines, %esi
movl $608000, %edx # imm = 0x94700
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movq 8(%rsp), %rsi
movq %rbx, %rdx
callq _Z19getNearestNeighborsPsS_Pt
leaq 80(%rsp), %r14
movq %r14, %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev
movq _Z14outputFilenameB5cxx11(%rip), %rsi
leaq 88(%rsp), %rdi
.Ltmp40:
movl $16, %edx
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp41:
# %bb.23: # %.noexc
movq 80(%rsp), %rcx
addq -24(%rcx), %r14
xorl %esi, %esi
testq %rax, %rax
jne .LBB5_25
# %bb.24:
movl 32(%r14), %esi
orl $4, %esi
.LBB5_25: # %.invoke
.Ltmp42:
movq %r14, %rdi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp43:
# %bb.26: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit.preheader
xorl %r13d, %r13d
leaq 80(%rsp), %r14
.p2align 4, 0x90
.LBB5_27: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit
# =>This Inner Loop Header: Depth=1
movzwl (%rbx,%r13,2), %esi
.Ltmp44:
movq %r14, %rdi
callq _ZNSo9_M_insertImEERSoT_
.Ltmp45:
# %bb.28: # %_ZNSolsEt.exit
# in Loop: Header=BB5_27 Depth=1
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB5_40
# %bb.29: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB5_27 Depth=1
cmpb $0, 56(%r12)
je .LBB5_31
# %bb.30: # in Loop: Header=BB5_27 Depth=1
movzbl 67(%r12), %eax
jmp .LBB5_33
.p2align 4, 0x90
.LBB5_31: # in Loop: Header=BB5_27 Depth=1
.Ltmp46:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp47:
# %bb.32: # %.noexc37
# in Loop: Header=BB5_27 Depth=1
movq (%r12), %rax
.Ltmp48:
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp49:
.LBB5_33: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
# in Loop: Header=BB5_27 Depth=1
.Ltmp50:
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
.Ltmp51:
# %bb.34: # %.noexc39
# in Loop: Header=BB5_27 Depth=1
.Ltmp52:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp53:
# %bb.35: # %_ZNSolsEPFRSoS_E.exit
# in Loop: Header=BB5_27 Depth=1
incq %r13
cmpq $1000, %r13 # imm = 0x3E8
jne .LBB5_27
# %bb.36:
movq %rbx, %rdi
callq free
movq 8(%rsp), %rdi
.Ltmp55:
callq hipFree
.Ltmp56:
# %bb.37:
movq (%rsp), %rdi
.Ltmp57:
callq hipFree
.Ltmp58:
# %bb.38:
leaq 80(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
movl $1, %eax
addq $592, %rsp # imm = 0x250
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB5_39: # %.noexc6.i
.cfi_def_cfa_offset 640
callq _ZSt17__throw_bad_allocv
.LBB5_40:
.Ltmp60:
callq _ZSt16__throw_bad_castv
.Ltmp61:
# %bb.41: # %.noexc36
.LBB5_42: # %.noexc.i
movl $.L.str.9, %edi
callq _ZSt20__throw_length_errorPKc
.LBB5_43:
.Ltmp39:
movq %rax, %rbx
movq 16(%rsp), %rdi
cmpq %r15, %rdi
jne .LBB5_46
jmp .LBB5_51
.LBB5_45:
.Ltmp36:
movq %rax, %rbx
movq 48(%rsp), %rdi
cmpq %r15, %rdi
je .LBB5_51
.LBB5_46: # %.critedge.i.i28
callq _ZdlPv
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.LBB5_47:
.Ltmp59:
jmp .LBB5_50
.LBB5_48: # %.loopexit.split-lp
.Ltmp62:
jmp .LBB5_50
.LBB5_49: # %.loopexit
.Ltmp54:
.LBB5_50:
movq %rax, %rbx
leaq 80(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
.LBB5_51: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit30
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table5:
.Lexception2:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end2-.Lcst_begin2
.Lcst_begin2:
.uleb128 .Lfunc_begin2-.Lfunc_begin2 # >> Call Site 1 <<
.uleb128 .Ltmp34-.Lfunc_begin2 # Call between .Lfunc_begin2 and .Ltmp34
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp34-.Lfunc_begin2 # >> Call Site 2 <<
.uleb128 .Ltmp35-.Ltmp34 # Call between .Ltmp34 and .Ltmp35
.uleb128 .Ltmp36-.Lfunc_begin2 # jumps to .Ltmp36
.byte 0 # On action: cleanup
.uleb128 .Ltmp35-.Lfunc_begin2 # >> Call Site 3 <<
.uleb128 .Ltmp37-.Ltmp35 # Call between .Ltmp35 and .Ltmp37
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp37-.Lfunc_begin2 # >> Call Site 4 <<
.uleb128 .Ltmp38-.Ltmp37 # Call between .Ltmp37 and .Ltmp38
.uleb128 .Ltmp39-.Lfunc_begin2 # jumps to .Ltmp39
.byte 0 # On action: cleanup
.uleb128 .Ltmp38-.Lfunc_begin2 # >> Call Site 5 <<
.uleb128 .Ltmp40-.Ltmp38 # Call between .Ltmp38 and .Ltmp40
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp40-.Lfunc_begin2 # >> Call Site 6 <<
.uleb128 .Ltmp43-.Ltmp40 # Call between .Ltmp40 and .Ltmp43
.uleb128 .Ltmp59-.Lfunc_begin2 # jumps to .Ltmp59
.byte 0 # On action: cleanup
.uleb128 .Ltmp44-.Lfunc_begin2 # >> Call Site 7 <<
.uleb128 .Ltmp53-.Ltmp44 # Call between .Ltmp44 and .Ltmp53
.uleb128 .Ltmp54-.Lfunc_begin2 # jumps to .Ltmp54
.byte 0 # On action: cleanup
.uleb128 .Ltmp55-.Lfunc_begin2 # >> Call Site 8 <<
.uleb128 .Ltmp58-.Ltmp55 # Call between .Ltmp55 and .Ltmp58
.uleb128 .Ltmp59-.Lfunc_begin2 # jumps to .Ltmp59
.byte 0 # On action: cleanup
.uleb128 .Ltmp58-.Lfunc_begin2 # >> Call Site 9 <<
.uleb128 .Ltmp60-.Ltmp58 # Call between .Ltmp58 and .Ltmp60
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp60-.Lfunc_begin2 # >> Call Site 10 <<
.uleb128 .Ltmp61-.Ltmp60 # Call between .Ltmp60 and .Ltmp61
.uleb128 .Ltmp62-.Lfunc_begin2 # jumps to .Ltmp62
.byte 0 # On action: cleanup
.uleb128 .Ltmp61-.Lfunc_begin2 # >> Call Site 11 <<
.uleb128 .Lfunc_end5-.Ltmp61 # Call between .Ltmp61 and .Lfunc_end5
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end2:
.p2align 2, 0x0
# -- End function
.section .text.startup,"ax",@progbits
.p2align 4, 0x90 # -- Begin function _GLOBAL__sub_I_bfs.hip
.type _GLOBAL__sub_I_bfs.hip,@function
_GLOBAL__sub_I_bfs.hip: # @_GLOBAL__sub_I_bfs.hip
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev, %edi
movl $_Z12testFilenameB5cxx11, %esi
movl $__dso_handle, %edx
callq __cxa_atexit
movl $_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev, %edi
movl $_Z13trainFilenameB5cxx11, %esi
movl $__dso_handle, %edx
callq __cxa_atexit
movl $_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev, %edi
movl $_Z14outputFilenameB5cxx11, %esi
movl $__dso_handle, %edx
popq %rax
.cfi_def_cfa_offset 8
jmp __cxa_atexit # TAILCALL
.Lfunc_end6:
.size _GLOBAL__sub_I_bfs.hip, .Lfunc_end6-_GLOBAL__sub_I_bfs.hip
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19calculateDifferencePsPyS_s, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type testLines,@object # @testLines
.bss
.globl testLines
.p2align 4, 0x0
testLines:
.zero 32000
.size testLines, 32000
.type trainLines,@object # @trainLines
.globl trainLines
.p2align 4, 0x0
trainLines:
.zero 608000
.size trainLines, 608000
.type _Z12testFilenameB5cxx11,@object # @_Z12testFilenameB5cxx11
.data
.globl _Z12testFilenameB5cxx11
.p2align 3, 0x0
_Z12testFilenameB5cxx11:
.quad _Z12testFilenameB5cxx11+16
.quad 8 # 0x8
.ascii "test.txt"
.zero 8
.size _Z12testFilenameB5cxx11, 32
.hidden __dso_handle
.type _Z13trainFilenameB5cxx11,@object # @_Z13trainFilenameB5cxx11
.globl _Z13trainFilenameB5cxx11
.p2align 3, 0x0
_Z13trainFilenameB5cxx11:
.quad _Z13trainFilenameB5cxx11+16
.quad 9 # 0x9
.asciz "train.txt\000\000\000\000\000\000"
.size _Z13trainFilenameB5cxx11, 32
.type _Z14outputFilenameB5cxx11,@object # @_Z14outputFilenameB5cxx11
.globl _Z14outputFilenameB5cxx11
.p2align 3, 0x0
_Z14outputFilenameB5cxx11:
.quad _Z14outputFilenameB5cxx11+16
.quad 9 # 0x9
.asciz "myout.txt\000\000\000\000\000\000"
.size _Z14outputFilenameB5cxx11, 32
.type _Z19calculateDifferencePsPyS_s,@object # @_Z19calculateDifferencePsPyS_s
.section .rodata,"a",@progbits
.globl _Z19calculateDifferencePsPyS_s
.p2align 3, 0x0
_Z19calculateDifferencePsPyS_s:
.quad _Z34__device_stub__calculateDifferencePsPyS_s
.size _Z19calculateDifferencePsPyS_s, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "stoi"
.size .L.str, 5
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "basic_string::substr"
.size .L.str.6, 21
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%s: __pos (which is %zu) > this->size() (which is %zu)"
.size .L.str.7, 55
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "basic_string::_M_create"
.size .L.str.9, 24
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z19calculateDifferencePsPyS_s"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad _GLOBAL__sub_I_bfs.hip
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Z34__device_stub__calculateDifferencePsPyS_s
.addrsig_sym _GLOBAL__sub_I_bfs.hip
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym testLines
.addrsig_sym trainLines
.addrsig_sym _Z12testFilenameB5cxx11
.addrsig_sym __dso_handle
.addrsig_sym _Z13trainFilenameB5cxx11
.addrsig_sym _Z14outputFilenameB5cxx11
.addrsig_sym _Z19calculateDifferencePsPyS_s
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z19calculateDifferencePsPyS_s
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ LDC.U16 R0, c[0x0][0x178] ; /* 0x00005e00ff007b82 */
/* 0x000e220000000400 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0030*/ IMAD.MOV.U32 R5, RZ, RZ, 0x2 ; /* 0x00000002ff057424 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0050*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0060*/ STS [RZ], RZ ; /* 0x000000ffff007388 */
/* 0x000fe20000000800 */
/*0070*/ PRMT R4, R0, 0x9910, RZ ; /* 0x0000991000047816 */
/* 0x001fc400000000ff */
/*0080*/ LEA R6, R2, R3, 0x4 ; /* 0x0000000302067211 */
/* 0x002fc600078e20ff */
/*0090*/ IMAD R4, R4, 0x10, R3 ; /* 0x0000001004047824 */
/* 0x000fe400078e0203 */
/*00a0*/ IMAD.WIDE.U32 R6, R6, R5.reuse, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x080fe200078e0005 */
/*00b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*00c0*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fc600078e0005 */
/*00d0*/ LDG.E.S16 R7, [R6.64] ; /* 0x0000000606077981 */
/* 0x000ea8000c1e1700 */
/*00e0*/ LDG.E.S16 R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1700 */
/*00f0*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe200038e0100 */
/*0100*/ LOP3.LUT P0, RZ, R3, 0xf, RZ, 0xc0, !PT ; /* 0x0000000f03ff7812 */
/* 0x000fe2000780c0ff */
/*0110*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fe200080e0000 */
/*0120*/ S2R R8, SR_LANEID ; /* 0x0000000000087919 */
/* 0x000e2a0000000000 */
/*0130*/ ISETP.EQ.U32.AND P1, PT, R8, UR4, PT ; /* 0x0000000408007c0c */
/* 0x001fc4000bf22070 */
/*0140*/ IADD3 R0, R4, -R7, RZ ; /* 0x8000000704007210 */
/* 0x004fca0007ffe0ff */
/*0150*/ IMAD R0, R0, R0, RZ ; /* 0x0000000000007224 */
/* 0x000fc800078e02ff */
/*0160*/ REDUX.SUM UR5, R0 ; /* 0x00000000000573c4 */
/* 0x000e24000000c000 */
/*0170*/ IMAD.U32 R8, RZ, RZ, UR5 ; /* 0x00000005ff087e24 */
/* 0x001fca000f8e00ff */
/*0180*/ @P1 ATOMS.ADD RZ, [RZ], R8 ; /* 0x00000008ffff138c */
/* 0x0001e80000000000 */
/*0190*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01b0*/ LDS R3, [RZ] ; /* 0x00000000ff037984 */
/* 0x001e220000000800 */
/*01c0*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fc40000000f00 */
/*01d0*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fca0000000f00 */
/*01e0*/ RED.E.MIN.64.STRONG.GPU [R4.64], R2 ; /* 0x000000020400798e */
/* 0x001fe2000c90e586 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19calculateDifferencePsPyS_s
.globl _Z19calculateDifferencePsPyS_s
.p2align 8
.type _Z19calculateDifferencePsPyS_s,@function
_Z19calculateDifferencePsPyS_s:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x18
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b64 s[6:7], s[0:1], 0x0
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, 0
s_mov_b32 s2, exec_lo
ds_store_b32 v5, v5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_sext_i32_i16 s3, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshl_add_u32 v1, s3, 4, v0
s_mov_b32 s3, 0
v_lshlrev_b64 v[3:4], 1, v[1:2]
v_lshl_add_u32 v1, s15, 4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[1:2], 1, v[1:2]
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v1, vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_i16 v3, v[3:4], off
global_load_i16 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v1, v3, v1
v_mul_i32_i24_e32 v1, v1, v1
.LBB0_1:
s_ctz_i32_b32 s4, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_readlane_b32 s5, v1, s4
s_lshl_b32 s4, 1, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_not1_b32 s2, s2, s4
s_add_i32 s3, s3, s5
s_cmp_lg_u32 s2, 0
s_cbranch_scc1 .LBB0_1
v_mbcnt_lo_u32_b32 v1, exec_lo, 0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v1
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB0_4
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s3
ds_add_u32 v1, v2
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s2
v_and_b32_e32 v0, 15, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v2, 0
s_load_b64 s[0:1], s[0:1], 0x8
v_mov_b32_e32 v0, s15
ds_load_b32 v1, v2
s_waitcnt lgkmcnt(0)
global_atomic_min_u64 v2, v[0:1], s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19calculateDifferencePsPyS_s
.amdhsa_group_segment_fixed_size 4
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19calculateDifferencePsPyS_s, .Lfunc_end0-_Z19calculateDifferencePsPyS_s
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 2
.value_kind: by_value
.group_segment_fixed_size: 4
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19calculateDifferencePsPyS_s
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19calculateDifferencePsPyS_s.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | struct ProgramTestClass
{
__device__ ProgramTestClass()
{
}
int A;
int B;
int C;
};
// CudaTest.Program
extern "C" __global__ void doTheThing( ProgramTestClass* tests, int testsLen0);
// CudaTest.Program
extern "C" __global__ void addArrays( int* a, int aLen0, int* b, int bLen0, int* c, int cLen0);
// CudaTest.Program
extern "C" __global__ void findPrimes( int* toCheck, int toCheckLen0, int* results, int resultsLen0);
// CudaTest.Program
__device__ int isPrime(int a);
// CudaTest.Program
extern "C" __global__ void doTheThing( ProgramTestClass* tests, int testsLen0)
{
int x = blockIdx.x;
if (x < 1000000)
{
ProgramTestClass testClass = tests[(x)];
testClass.C = testClass.A + testClass.B;
}
}
// CudaTest.Program
extern "C" __global__ void addArrays( int* a, int aLen0, int* b, int bLen0, int* c, int cLen0)
{
int x = blockIdx.x;
if (x < 1000000)
{
c[(x)] = a[(x)] + b[(x)];
}
}
// CudaTest.Program
extern "C" __global__ void findPrimes( int* toCheck, int toCheckLen0, int* results, int resultsLen0)
{
int x = blockIdx.x;
if (x < 1000000)
{
results[(x)] = isPrime(toCheck[(x)]);
}
}
// CudaTest.Program
__device__ int isPrime(int a)
{
int result;
if (a == 1 || a == 2)
{
result = 1;
}
else
{
int num = a % 2;
if (num == 0)
{
result = 0;
}
else
{
int num2 = a / 2;
for (int num3 = 3; num3 <= num2; num3++)
{
if (a % num3 == 0)
{
result = 0;
return result;
}
}
result = 1;
}
}
return result;
} | code for sm_80
Function : findPrimes
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GT.AND P0, PT, R0, 0xf423f, PT ; /* 0x000f423f0000780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0060*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fe200078e00ff */
/*0090*/ IADD3 R3, R2, -0x1, RZ ; /* 0xffffffff02037810 */
/* 0x004fc80007ffe0ff */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R3, 0x2, PT ; /* 0x000000020300780c */
/* 0x000fe40003f06070 */
/*00b0*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fd60000011400 */
/*00c0*/ @!P0 BRA 0x350 ; /* 0x0000028000008947 */
/* 0x000fea0003800000 */
/*00d0*/ LOP3.LUT R4, R2, 0x1, RZ, 0xc0, !PT ; /* 0x0000000102047812 */
/* 0x000fe200078ec0ff */
/*00e0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fc600078e00ff */
/*00f0*/ ISETP.NE.U32.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f05070 */
/*0100*/ @P0 BRA 0x350 ; /* 0x0000024000000947 */
/* 0x000fea0003800000 */
/*0110*/ ISETP.GE.AND P0, PT, R2, 0x6, PT ; /* 0x000000060200780c */
/* 0x000fe20003f06270 */
/*0120*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fd800078e00ff */
/*0130*/ @!P0 BRA 0x350 ; /* 0x0000021000008947 */
/* 0x000fea0003800000 */
/*0140*/ LEA.HI R4, R2, R2.reuse, RZ, 0x1 ; /* 0x0000000202047211 */
/* 0x080fe200078f08ff */
/*0150*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3 ; /* 0x00000003ff097424 */
/* 0x000fe200078e00ff */
/*0160*/ IABS R8, R2 ; /* 0x0000000200087213 */
/* 0x000fe40000000000 */
/*0170*/ SHF.R.S32.HI R6, RZ, 0x1, R4 ; /* 0x00000001ff067819 */
/* 0x000fe40000011404 */
/*0180*/ IABS R10, R9.reuse ; /* 0x00000009000a7213 */
/* 0x080fe40000000000 */
/*0190*/ IABS R12, R9 ; /* 0x00000009000c7213 */
/* 0x000fe40000000000 */
/*01a0*/ I2F.RP R7, R10 ; /* 0x0000000a00077306 */
/* 0x000e220000209400 */
/*01b0*/ ISETP.GE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f46270 */
/*01c0*/ IMAD.MOV R12, RZ, RZ, -R12 ; /* 0x000000ffff0c7224 */
/* 0x000fca00078e0a0c */
/*01d0*/ MUFU.RCP R7, R7 ; /* 0x0000000700077308 */
/* 0x001e240000001000 */
/*01e0*/ IADD3 R4, R7, 0xffffffe, RZ ; /* 0x0ffffffe07047810 */
/* 0x001fe40007ffe0ff */
/*01f0*/ IABS R7, R2 ; /* 0x0000000200077213 */
/* 0x000fc80000000000 */
/*0200*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0210*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0220*/ IMAD.MOV R11, RZ, RZ, -R5 ; /* 0x000000ffff0b7224 */
/* 0x002fc800078e0a05 */
/*0230*/ IMAD R11, R11, R10, RZ ; /* 0x0000000a0b0b7224 */
/* 0x000fc800078e02ff */
/*0240*/ IMAD.HI.U32 R5, R5, R11, R4 ; /* 0x0000000b05057227 */
/* 0x000fcc00078e0004 */
/*0250*/ IMAD.HI.U32 R5, R5, R8, RZ ; /* 0x0000000805057227 */
/* 0x000fc800078e00ff */
/*0260*/ IMAD R5, R5, R12, R7 ; /* 0x0000000c05057224 */
/* 0x000fe400078e0207 */
/*0270*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fc600078e00ff */
/*0280*/ ISETP.GT.U32.AND P0, PT, R10, R5, PT ; /* 0x000000050a00720c */
/* 0x000fda0003f04070 */
/*0290*/ @!P0 IMAD.IADD R5, R5, 0x1, -R10 ; /* 0x0000000105058824 */
/* 0x000fe200078e0a0a */
/*02a0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fc80003f05270 */
/*02b0*/ ISETP.GT.U32.AND P1, PT, R10, R5, PT ; /* 0x000000050a00720c */
/* 0x000fda0003f24070 */
/*02c0*/ @!P1 IMAD.IADD R5, R5, 0x1, -R10 ; /* 0x0000000105059824 */
/* 0x000fc800078e0a0a */
/*02d0*/ @!P2 IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff05a224 */
/* 0x000fe200078e0a05 */
/*02e0*/ @!P0 LOP3.LUT R5, RZ, R9, RZ, 0x33, !PT ; /* 0x00000009ff058212 */
/* 0x000fc800078e33ff */
/*02f0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0300*/ @!P0 BRA 0x350 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0310*/ ISETP.GE.AND P0, PT, R9.reuse, R6, PT ; /* 0x000000060900720c */
/* 0x040fe40003f06270 */
/*0320*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fd60007ffe0ff */
/*0330*/ @!P0 BRA 0x180 ; /* 0xfffffe4000008947 */
/* 0x000fea000383ffff */
/*0340*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fe400078e00ff */
/*0350*/ LEA R2, P0, R0, c[0x0][0x170], 0x2 ; /* 0x00005c0000027a11 */
/* 0x000fc800078010ff */
/*0360*/ LEA.HI.X R3, R0, c[0x0][0x174], R3, 0x2, P0 ; /* 0x00005d0000037a11 */
/* 0x000fca00000f1403 */
/*0370*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0380*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0390*/ BRA 0x390; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : addArrays
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GT.AND P0, PT, R6, 0xf423f, PT ; /* 0x000f423f0600780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x180] ; /* 0x0000600006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : doTheThing
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | struct ProgramTestClass
{
__device__ ProgramTestClass()
{
}
int A;
int B;
int C;
};
// CudaTest.Program
extern "C" __global__ void doTheThing( ProgramTestClass* tests, int testsLen0);
// CudaTest.Program
extern "C" __global__ void addArrays( int* a, int aLen0, int* b, int bLen0, int* c, int cLen0);
// CudaTest.Program
extern "C" __global__ void findPrimes( int* toCheck, int toCheckLen0, int* results, int resultsLen0);
// CudaTest.Program
__device__ int isPrime(int a);
// CudaTest.Program
extern "C" __global__ void doTheThing( ProgramTestClass* tests, int testsLen0)
{
int x = blockIdx.x;
if (x < 1000000)
{
ProgramTestClass testClass = tests[(x)];
testClass.C = testClass.A + testClass.B;
}
}
// CudaTest.Program
extern "C" __global__ void addArrays( int* a, int aLen0, int* b, int bLen0, int* c, int cLen0)
{
int x = blockIdx.x;
if (x < 1000000)
{
c[(x)] = a[(x)] + b[(x)];
}
}
// CudaTest.Program
extern "C" __global__ void findPrimes( int* toCheck, int toCheckLen0, int* results, int resultsLen0)
{
int x = blockIdx.x;
if (x < 1000000)
{
results[(x)] = isPrime(toCheck[(x)]);
}
}
// CudaTest.Program
__device__ int isPrime(int a)
{
int result;
if (a == 1 || a == 2)
{
result = 1;
}
else
{
int num = a % 2;
if (num == 0)
{
result = 0;
}
else
{
int num2 = a / 2;
for (int num3 = 3; num3 <= num2; num3++)
{
if (a % num3 == 0)
{
result = 0;
return result;
}
}
result = 1;
}
}
return result;
} | .file "tmpxft_0010c867_00000000-6_CUDAFYSOURCETEMP.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2033:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2033:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7isPrimei
.type _Z7isPrimei, @function
_Z7isPrimei:
.LFB2030:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2030:
.size _Z7isPrimei, .-_Z7isPrimei
.globl _Z48__device_stub__Z10doTheThingP16ProgramTestClassiP16ProgramTestClassi
.type _Z48__device_stub__Z10doTheThingP16ProgramTestClassiP16ProgramTestClassi, @function
_Z48__device_stub__Z10doTheThingP16ProgramTestClassiP16ProgramTestClassi:
.LFB2055:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq doTheThing(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z48__device_stub__Z10doTheThingP16ProgramTestClassiP16ProgramTestClassi, .-_Z48__device_stub__Z10doTheThingP16ProgramTestClassiP16ProgramTestClassi
.globl doTheThing
.type doTheThing, @function
doTheThing:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z10doTheThingP16ProgramTestClassiP16ProgramTestClassi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size doTheThing, .-doTheThing
.globl _Z35__device_stub__Z9addArraysPiiS_iS_iPiiS_iS_i
.type _Z35__device_stub__Z9addArraysPiiS_iS_iPiiS_iS_i, @function
_Z35__device_stub__Z9addArraysPiiS_iS_iPiiS_iS_i:
.LFB2057:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 32(%rsp)
movq %r8, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq addArrays(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z35__device_stub__Z9addArraysPiiS_iS_iPiiS_iS_i, .-_Z35__device_stub__Z9addArraysPiiS_iS_iPiiS_iS_i
.globl addArrays
.type addArrays, @function
addArrays:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z9addArraysPiiS_iS_iPiiS_iS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size addArrays, .-addArrays
.globl _Z34__device_stub__Z10findPrimesPiiS_iPiiS_i
.type _Z34__device_stub__Z10findPrimesPiiS_iPiiS_i, @function
_Z34__device_stub__Z10findPrimesPiiS_iPiiS_i:
.LFB2059:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 16(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq findPrimes(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z34__device_stub__Z10findPrimesPiiS_iPiiS_i, .-_Z34__device_stub__Z10findPrimesPiiS_iPiiS_i
.globl findPrimes
.type findPrimes, @function
findPrimes:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10findPrimesPiiS_iPiiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size findPrimes, .-findPrimes
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "findPrimes"
.LC1:
.string "addArrays"
.LC2:
.string "doTheThing"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2062:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq findPrimes(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq addArrays(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq doTheThing(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | struct ProgramTestClass
{
__device__ ProgramTestClass()
{
}
int A;
int B;
int C;
};
// CudaTest.Program
extern "C" __global__ void doTheThing( ProgramTestClass* tests, int testsLen0);
// CudaTest.Program
extern "C" __global__ void addArrays( int* a, int aLen0, int* b, int bLen0, int* c, int cLen0);
// CudaTest.Program
extern "C" __global__ void findPrimes( int* toCheck, int toCheckLen0, int* results, int resultsLen0);
// CudaTest.Program
__device__ int isPrime(int a);
// CudaTest.Program
extern "C" __global__ void doTheThing( ProgramTestClass* tests, int testsLen0)
{
int x = blockIdx.x;
if (x < 1000000)
{
ProgramTestClass testClass = tests[(x)];
testClass.C = testClass.A + testClass.B;
}
}
// CudaTest.Program
extern "C" __global__ void addArrays( int* a, int aLen0, int* b, int bLen0, int* c, int cLen0)
{
int x = blockIdx.x;
if (x < 1000000)
{
c[(x)] = a[(x)] + b[(x)];
}
}
// CudaTest.Program
extern "C" __global__ void findPrimes( int* toCheck, int toCheckLen0, int* results, int resultsLen0)
{
int x = blockIdx.x;
if (x < 1000000)
{
results[(x)] = isPrime(toCheck[(x)]);
}
}
// CudaTest.Program
__device__ int isPrime(int a)
{
int result;
if (a == 1 || a == 2)
{
result = 1;
}
else
{
int num = a % 2;
if (num == 0)
{
result = 0;
}
else
{
int num2 = a / 2;
for (int num3 = 3; num3 <= num2; num3++)
{
if (a % num3 == 0)
{
result = 0;
return result;
}
}
result = 1;
}
}
return result;
} | #include <hip/hip_runtime.h>
struct ProgramTestClass
{
__device__ ProgramTestClass()
{
}
int A;
int B;
int C;
};
// CudaTest.Program
extern "C" __global__ void doTheThing( ProgramTestClass* tests, int testsLen0);
// CudaTest.Program
extern "C" __global__ void addArrays( int* a, int aLen0, int* b, int bLen0, int* c, int cLen0);
// CudaTest.Program
extern "C" __global__ void findPrimes( int* toCheck, int toCheckLen0, int* results, int resultsLen0);
// CudaTest.Program
__device__ int isPrime(int a);
// CudaTest.Program
extern "C" __global__ void doTheThing( ProgramTestClass* tests, int testsLen0)
{
int x = blockIdx.x;
if (x < 1000000)
{
ProgramTestClass testClass = tests[(x)];
testClass.C = testClass.A + testClass.B;
}
}
// CudaTest.Program
extern "C" __global__ void addArrays( int* a, int aLen0, int* b, int bLen0, int* c, int cLen0)
{
int x = blockIdx.x;
if (x < 1000000)
{
c[(x)] = a[(x)] + b[(x)];
}
}
// CudaTest.Program
extern "C" __global__ void findPrimes( int* toCheck, int toCheckLen0, int* results, int resultsLen0)
{
int x = blockIdx.x;
if (x < 1000000)
{
results[(x)] = isPrime(toCheck[(x)]);
}
}
// CudaTest.Program
__device__ int isPrime(int a)
{
int result;
if (a == 1 || a == 2)
{
result = 1;
}
else
{
int num = a % 2;
if (num == 0)
{
result = 0;
}
else
{
int num2 = a / 2;
for (int num3 = 3; num3 <= num2; num3++)
{
if (a % num3 == 0)
{
result = 0;
return result;
}
}
result = 1;
}
}
return result;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
struct ProgramTestClass
{
__device__ ProgramTestClass()
{
}
int A;
int B;
int C;
};
// CudaTest.Program
extern "C" __global__ void doTheThing( ProgramTestClass* tests, int testsLen0);
// CudaTest.Program
extern "C" __global__ void addArrays( int* a, int aLen0, int* b, int bLen0, int* c, int cLen0);
// CudaTest.Program
extern "C" __global__ void findPrimes( int* toCheck, int toCheckLen0, int* results, int resultsLen0);
// CudaTest.Program
__device__ int isPrime(int a);
// CudaTest.Program
extern "C" __global__ void doTheThing( ProgramTestClass* tests, int testsLen0)
{
int x = blockIdx.x;
if (x < 1000000)
{
ProgramTestClass testClass = tests[(x)];
testClass.C = testClass.A + testClass.B;
}
}
// CudaTest.Program
extern "C" __global__ void addArrays( int* a, int aLen0, int* b, int bLen0, int* c, int cLen0)
{
int x = blockIdx.x;
if (x < 1000000)
{
c[(x)] = a[(x)] + b[(x)];
}
}
// CudaTest.Program
extern "C" __global__ void findPrimes( int* toCheck, int toCheckLen0, int* results, int resultsLen0)
{
int x = blockIdx.x;
if (x < 1000000)
{
results[(x)] = isPrime(toCheck[(x)]);
}
}
// CudaTest.Program
__device__ int isPrime(int a)
{
int result;
if (a == 1 || a == 2)
{
result = 1;
}
else
{
int num = a % 2;
if (num == 0)
{
result = 0;
}
else
{
int num2 = a / 2;
for (int num3 = 3; num3 <= num2; num3++)
{
if (a % num3 == 0)
{
result = 0;
return result;
}
}
result = 1;
}
}
return result;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected doTheThing
.globl doTheThing
.p2align 8
.type doTheThing,@function
doTheThing:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel doTheThing
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size doTheThing, .Lfunc_end0-doTheThing
.section .AMDGPU.csdata,"",@progbits
.text
.protected addArrays
.globl addArrays
.p2align 8
.type addArrays,@function
addArrays:
s_cmp_gt_i32 s15, 0xf423f
s_cbranch_scc1 .LBB1_2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b64 s[6:7], s[0:1], 0x10
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_load_b64 s[0:1], s[0:1], 0x20
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel addArrays
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 44
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size addArrays, .Lfunc_end1-addArrays
.section .AMDGPU.csdata,"",@progbits
.text
.protected findPrimes
.globl findPrimes
.p2align 8
.type findPrimes,@function
findPrimes:
s_cmp_gt_i32 s15, 0xf423f
s_cbranch_scc1 .LBB2_13
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
v_mov_b32_e32 v0, 1
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_load_b32 s4, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s5, s4, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_u32 s5, 2
s_cbranch_scc1 .LBB2_12
v_mov_b32_e32 v0, 0
s_bitcmp0_b32 s4, 0
s_cbranch_scc1 .LBB2_12
s_cmp_lt_i32 s4, 6
s_cselect_b32 s5, -1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s5
s_cbranch_vccnz .LBB2_11
s_mul_i32 s5, s4, 0xaaaaaaab
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_u32 s5, 0x55555556
s_cbranch_scc1 .LBB2_10
s_lshr_b32 s5, s4, 31
s_mov_b32 s7, 3
s_add_i32 s5, s4, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s5, s5, 1
s_max_i32 s6, s5, 3
s_set_inst_prefetch_distance 0x1
s_branch .LBB2_7
.p2align 6
.LBB2_6:
s_and_not1_b32 vcc_lo, exec_lo, s9
s_cbranch_vccz .LBB2_9
.LBB2_7:
s_mov_b32 s8, s7
s_cmp_eq_u32 s7, s6
s_mov_b32 s9, -1
s_cbranch_scc1 .LBB2_6
s_add_i32 s7, s8, 1
s_not_b32 s10, s8
v_cvt_f32_u32_e32 v0, s7
s_waitcnt_depctr 0xfff
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_readfirstlane_b32 s9, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s10, s10, s9
s_mul_hi_u32 s10, s9, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s9, s9, s10
s_mul_hi_u32 s9, s4, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s9, s9, s7
s_sub_i32 s9, s4, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_sub_i32 s10, s9, s7
s_cmp_ge_u32 s9, s7
s_cselect_b32 s9, s10, s9
s_sub_i32 s10, s9, s7
s_cmp_ge_u32 s9, s7
s_cselect_b32 s9, s10, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s9, 0
s_cselect_b32 s9, -1, 0
s_branch .LBB2_6
.LBB2_9:
s_set_inst_prefetch_distance 0x2
s_cmp_ge_i32 s8, s5
s_cselect_b32 s5, -1, 0
s_branch .LBB2_11
.LBB2_10:
s_mov_b32 s5, 0
.LBB2_11:
s_delay_alu instid0(SALU_CYCLE_1)
v_cndmask_b32_e64 v0, 0, 1, s5
.LBB2_12:
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB2_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel findPrimes
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size findPrimes, .Lfunc_end2-findPrimes
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: doTheThing
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: doTheThing.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 44
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: addArrays
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: addArrays.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: findPrimes
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: findPrimes.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
struct ProgramTestClass
{
__device__ ProgramTestClass()
{
}
int A;
int B;
int C;
};
// CudaTest.Program
extern "C" __global__ void doTheThing( ProgramTestClass* tests, int testsLen0);
// CudaTest.Program
extern "C" __global__ void addArrays( int* a, int aLen0, int* b, int bLen0, int* c, int cLen0);
// CudaTest.Program
extern "C" __global__ void findPrimes( int* toCheck, int toCheckLen0, int* results, int resultsLen0);
// CudaTest.Program
__device__ int isPrime(int a);
// CudaTest.Program
extern "C" __global__ void doTheThing( ProgramTestClass* tests, int testsLen0)
{
int x = blockIdx.x;
if (x < 1000000)
{
ProgramTestClass testClass = tests[(x)];
testClass.C = testClass.A + testClass.B;
}
}
// CudaTest.Program
extern "C" __global__ void addArrays( int* a, int aLen0, int* b, int bLen0, int* c, int cLen0)
{
int x = blockIdx.x;
if (x < 1000000)
{
c[(x)] = a[(x)] + b[(x)];
}
}
// CudaTest.Program
extern "C" __global__ void findPrimes( int* toCheck, int toCheckLen0, int* results, int resultsLen0)
{
int x = blockIdx.x;
if (x < 1000000)
{
results[(x)] = isPrime(toCheck[(x)]);
}
}
// CudaTest.Program
__device__ int isPrime(int a)
{
int result;
if (a == 1 || a == 2)
{
result = 1;
}
else
{
int num = a % 2;
if (num == 0)
{
result = 0;
}
else
{
int num2 = a / 2;
for (int num3 = 3; num3 <= num2; num3++)
{
if (a % num3 == 0)
{
result = 0;
return result;
}
}
result = 1;
}
}
return result;
} | .text
.file "CUDAFYSOURCETEMP.hip"
.globl __device_stub__doTheThing # -- Begin function __device_stub__doTheThing
.p2align 4, 0x90
.type __device_stub__doTheThing,@function
__device_stub__doTheThing: # @__device_stub__doTheThing
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $doTheThing, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size __device_stub__doTheThing, .Lfunc_end0-__device_stub__doTheThing
.cfi_endproc
# -- End function
.globl __device_stub__addArrays # -- Begin function __device_stub__addArrays
.p2align 4, 0x90
.type __device_stub__addArrays,@function
__device_stub__addArrays: # @__device_stub__addArrays
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 80(%rsp)
movl %ecx, 16(%rsp)
movq %r8, 72(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $addArrays, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size __device_stub__addArrays, .Lfunc_end1-__device_stub__addArrays
.cfi_endproc
# -- End function
.globl __device_stub__findPrimes # -- Begin function __device_stub__findPrimes
.p2align 4, 0x90
.type __device_stub__findPrimes,@function
__device_stub__findPrimes: # @__device_stub__findPrimes
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $findPrimes, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size __device_stub__findPrimes, .Lfunc_end2-__device_stub__findPrimes
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $doTheThing, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $addArrays, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $findPrimes, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type doTheThing,@object # @doTheThing
.section .rodata,"a",@progbits
.globl doTheThing
.p2align 3, 0x0
doTheThing:
.quad __device_stub__doTheThing
.size doTheThing, 8
.type addArrays,@object # @addArrays
.globl addArrays
.p2align 3, 0x0
addArrays:
.quad __device_stub__addArrays
.size addArrays, 8
.type findPrimes,@object # @findPrimes
.globl findPrimes
.p2align 3, 0x0
findPrimes:
.quad __device_stub__findPrimes
.size findPrimes, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "doTheThing"
.size .L__unnamed_1, 11
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "addArrays"
.size .L__unnamed_2, 10
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "findPrimes"
.size .L__unnamed_3, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__doTheThing
.addrsig_sym __device_stub__addArrays
.addrsig_sym __device_stub__findPrimes
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym doTheThing
.addrsig_sym addArrays
.addrsig_sym findPrimes
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : findPrimes
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GT.AND P0, PT, R0, 0xf423f, PT ; /* 0x000f423f0000780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0060*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fe200078e00ff */
/*0090*/ IADD3 R3, R2, -0x1, RZ ; /* 0xffffffff02037810 */
/* 0x004fc80007ffe0ff */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R3, 0x2, PT ; /* 0x000000020300780c */
/* 0x000fe40003f06070 */
/*00b0*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fd60000011400 */
/*00c0*/ @!P0 BRA 0x350 ; /* 0x0000028000008947 */
/* 0x000fea0003800000 */
/*00d0*/ LOP3.LUT R4, R2, 0x1, RZ, 0xc0, !PT ; /* 0x0000000102047812 */
/* 0x000fe200078ec0ff */
/*00e0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fc600078e00ff */
/*00f0*/ ISETP.NE.U32.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f05070 */
/*0100*/ @P0 BRA 0x350 ; /* 0x0000024000000947 */
/* 0x000fea0003800000 */
/*0110*/ ISETP.GE.AND P0, PT, R2, 0x6, PT ; /* 0x000000060200780c */
/* 0x000fe20003f06270 */
/*0120*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fd800078e00ff */
/*0130*/ @!P0 BRA 0x350 ; /* 0x0000021000008947 */
/* 0x000fea0003800000 */
/*0140*/ LEA.HI R4, R2, R2.reuse, RZ, 0x1 ; /* 0x0000000202047211 */
/* 0x080fe200078f08ff */
/*0150*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3 ; /* 0x00000003ff097424 */
/* 0x000fe200078e00ff */
/*0160*/ IABS R8, R2 ; /* 0x0000000200087213 */
/* 0x000fe40000000000 */
/*0170*/ SHF.R.S32.HI R6, RZ, 0x1, R4 ; /* 0x00000001ff067819 */
/* 0x000fe40000011404 */
/*0180*/ IABS R10, R9.reuse ; /* 0x00000009000a7213 */
/* 0x080fe40000000000 */
/*0190*/ IABS R12, R9 ; /* 0x00000009000c7213 */
/* 0x000fe40000000000 */
/*01a0*/ I2F.RP R7, R10 ; /* 0x0000000a00077306 */
/* 0x000e220000209400 */
/*01b0*/ ISETP.GE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f46270 */
/*01c0*/ IMAD.MOV R12, RZ, RZ, -R12 ; /* 0x000000ffff0c7224 */
/* 0x000fca00078e0a0c */
/*01d0*/ MUFU.RCP R7, R7 ; /* 0x0000000700077308 */
/* 0x001e240000001000 */
/*01e0*/ IADD3 R4, R7, 0xffffffe, RZ ; /* 0x0ffffffe07047810 */
/* 0x001fe40007ffe0ff */
/*01f0*/ IABS R7, R2 ; /* 0x0000000200077213 */
/* 0x000fc80000000000 */
/*0200*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0210*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0220*/ IMAD.MOV R11, RZ, RZ, -R5 ; /* 0x000000ffff0b7224 */
/* 0x002fc800078e0a05 */
/*0230*/ IMAD R11, R11, R10, RZ ; /* 0x0000000a0b0b7224 */
/* 0x000fc800078e02ff */
/*0240*/ IMAD.HI.U32 R5, R5, R11, R4 ; /* 0x0000000b05057227 */
/* 0x000fcc00078e0004 */
/*0250*/ IMAD.HI.U32 R5, R5, R8, RZ ; /* 0x0000000805057227 */
/* 0x000fc800078e00ff */
/*0260*/ IMAD R5, R5, R12, R7 ; /* 0x0000000c05057224 */
/* 0x000fe400078e0207 */
/*0270*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fc600078e00ff */
/*0280*/ ISETP.GT.U32.AND P0, PT, R10, R5, PT ; /* 0x000000050a00720c */
/* 0x000fda0003f04070 */
/*0290*/ @!P0 IMAD.IADD R5, R5, 0x1, -R10 ; /* 0x0000000105058824 */
/* 0x000fe200078e0a0a */
/*02a0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fc80003f05270 */
/*02b0*/ ISETP.GT.U32.AND P1, PT, R10, R5, PT ; /* 0x000000050a00720c */
/* 0x000fda0003f24070 */
/*02c0*/ @!P1 IMAD.IADD R5, R5, 0x1, -R10 ; /* 0x0000000105059824 */
/* 0x000fc800078e0a0a */
/*02d0*/ @!P2 IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff05a224 */
/* 0x000fe200078e0a05 */
/*02e0*/ @!P0 LOP3.LUT R5, RZ, R9, RZ, 0x33, !PT ; /* 0x00000009ff058212 */
/* 0x000fc800078e33ff */
/*02f0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0300*/ @!P0 BRA 0x350 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0310*/ ISETP.GE.AND P0, PT, R9.reuse, R6, PT ; /* 0x000000060900720c */
/* 0x040fe40003f06270 */
/*0320*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fd60007ffe0ff */
/*0330*/ @!P0 BRA 0x180 ; /* 0xfffffe4000008947 */
/* 0x000fea000383ffff */
/*0340*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fe400078e00ff */
/*0350*/ LEA R2, P0, R0, c[0x0][0x170], 0x2 ; /* 0x00005c0000027a11 */
/* 0x000fc800078010ff */
/*0360*/ LEA.HI.X R3, R0, c[0x0][0x174], R3, 0x2, P0 ; /* 0x00005d0000037a11 */
/* 0x000fca00000f1403 */
/*0370*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0380*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0390*/ BRA 0x390; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : addArrays
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GT.AND P0, PT, R6, 0xf423f, PT ; /* 0x000f423f0600780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x180] ; /* 0x0000600006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : doTheThing
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected doTheThing
.globl doTheThing
.p2align 8
.type doTheThing,@function
doTheThing:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel doTheThing
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size doTheThing, .Lfunc_end0-doTheThing
.section .AMDGPU.csdata,"",@progbits
.text
.protected addArrays
.globl addArrays
.p2align 8
.type addArrays,@function
addArrays:
s_cmp_gt_i32 s15, 0xf423f
s_cbranch_scc1 .LBB1_2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b64 s[6:7], s[0:1], 0x10
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_load_b64 s[0:1], s[0:1], 0x20
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel addArrays
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 44
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size addArrays, .Lfunc_end1-addArrays
.section .AMDGPU.csdata,"",@progbits
.text
.protected findPrimes
.globl findPrimes
.p2align 8
.type findPrimes,@function
findPrimes:
s_cmp_gt_i32 s15, 0xf423f
s_cbranch_scc1 .LBB2_13
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
v_mov_b32_e32 v0, 1
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_load_b32 s4, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s5, s4, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_u32 s5, 2
s_cbranch_scc1 .LBB2_12
v_mov_b32_e32 v0, 0
s_bitcmp0_b32 s4, 0
s_cbranch_scc1 .LBB2_12
s_cmp_lt_i32 s4, 6
s_cselect_b32 s5, -1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s5
s_cbranch_vccnz .LBB2_11
s_mul_i32 s5, s4, 0xaaaaaaab
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_u32 s5, 0x55555556
s_cbranch_scc1 .LBB2_10
s_lshr_b32 s5, s4, 31
s_mov_b32 s7, 3
s_add_i32 s5, s4, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s5, s5, 1
s_max_i32 s6, s5, 3
s_set_inst_prefetch_distance 0x1
s_branch .LBB2_7
.p2align 6
.LBB2_6:
s_and_not1_b32 vcc_lo, exec_lo, s9
s_cbranch_vccz .LBB2_9
.LBB2_7:
s_mov_b32 s8, s7
s_cmp_eq_u32 s7, s6
s_mov_b32 s9, -1
s_cbranch_scc1 .LBB2_6
s_add_i32 s7, s8, 1
s_not_b32 s10, s8
v_cvt_f32_u32_e32 v0, s7
s_waitcnt_depctr 0xfff
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_readfirstlane_b32 s9, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s10, s10, s9
s_mul_hi_u32 s10, s9, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s9, s9, s10
s_mul_hi_u32 s9, s4, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s9, s9, s7
s_sub_i32 s9, s4, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_sub_i32 s10, s9, s7
s_cmp_ge_u32 s9, s7
s_cselect_b32 s9, s10, s9
s_sub_i32 s10, s9, s7
s_cmp_ge_u32 s9, s7
s_cselect_b32 s9, s10, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s9, 0
s_cselect_b32 s9, -1, 0
s_branch .LBB2_6
.LBB2_9:
s_set_inst_prefetch_distance 0x2
s_cmp_ge_i32 s8, s5
s_cselect_b32 s5, -1, 0
s_branch .LBB2_11
.LBB2_10:
s_mov_b32 s5, 0
.LBB2_11:
s_delay_alu instid0(SALU_CYCLE_1)
v_cndmask_b32_e64 v0, 0, 1, s5
.LBB2_12:
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB2_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel findPrimes
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size findPrimes, .Lfunc_end2-findPrimes
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: doTheThing
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: doTheThing.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 44
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: addArrays
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: addArrays.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: findPrimes
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: findPrimes.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010c867_00000000-6_CUDAFYSOURCETEMP.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2033:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2033:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7isPrimei
.type _Z7isPrimei, @function
_Z7isPrimei:
.LFB2030:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2030:
.size _Z7isPrimei, .-_Z7isPrimei
.globl _Z48__device_stub__Z10doTheThingP16ProgramTestClassiP16ProgramTestClassi
.type _Z48__device_stub__Z10doTheThingP16ProgramTestClassiP16ProgramTestClassi, @function
_Z48__device_stub__Z10doTheThingP16ProgramTestClassiP16ProgramTestClassi:
.LFB2055:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq doTheThing(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z48__device_stub__Z10doTheThingP16ProgramTestClassiP16ProgramTestClassi, .-_Z48__device_stub__Z10doTheThingP16ProgramTestClassiP16ProgramTestClassi
.globl doTheThing
.type doTheThing, @function
doTheThing:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z10doTheThingP16ProgramTestClassiP16ProgramTestClassi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size doTheThing, .-doTheThing
.globl _Z35__device_stub__Z9addArraysPiiS_iS_iPiiS_iS_i
.type _Z35__device_stub__Z9addArraysPiiS_iS_iPiiS_iS_i, @function
_Z35__device_stub__Z9addArraysPiiS_iS_iPiiS_iS_i:
.LFB2057:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 32(%rsp)
movq %r8, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq addArrays(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z35__device_stub__Z9addArraysPiiS_iS_iPiiS_iS_i, .-_Z35__device_stub__Z9addArraysPiiS_iS_iPiiS_iS_i
.globl addArrays
.type addArrays, @function
addArrays:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z9addArraysPiiS_iS_iPiiS_iS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size addArrays, .-addArrays
.globl _Z34__device_stub__Z10findPrimesPiiS_iPiiS_i
.type _Z34__device_stub__Z10findPrimesPiiS_iPiiS_i, @function
_Z34__device_stub__Z10findPrimesPiiS_iPiiS_i:
.LFB2059:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 16(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq findPrimes(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z34__device_stub__Z10findPrimesPiiS_iPiiS_i, .-_Z34__device_stub__Z10findPrimesPiiS_iPiiS_i
.globl findPrimes
.type findPrimes, @function
findPrimes:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10findPrimesPiiS_iPiiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size findPrimes, .-findPrimes
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "findPrimes"
.LC1:
.string "addArrays"
.LC2:
.string "doTheThing"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2062:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq findPrimes(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq addArrays(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq doTheThing(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "CUDAFYSOURCETEMP.hip"
.globl __device_stub__doTheThing # -- Begin function __device_stub__doTheThing
.p2align 4, 0x90
.type __device_stub__doTheThing,@function
__device_stub__doTheThing: # @__device_stub__doTheThing
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $doTheThing, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size __device_stub__doTheThing, .Lfunc_end0-__device_stub__doTheThing
.cfi_endproc
# -- End function
.globl __device_stub__addArrays # -- Begin function __device_stub__addArrays
.p2align 4, 0x90
.type __device_stub__addArrays,@function
__device_stub__addArrays: # @__device_stub__addArrays
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 80(%rsp)
movl %ecx, 16(%rsp)
movq %r8, 72(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $addArrays, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size __device_stub__addArrays, .Lfunc_end1-__device_stub__addArrays
.cfi_endproc
# -- End function
.globl __device_stub__findPrimes # -- Begin function __device_stub__findPrimes
.p2align 4, 0x90
.type __device_stub__findPrimes,@function
__device_stub__findPrimes: # @__device_stub__findPrimes
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $findPrimes, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size __device_stub__findPrimes, .Lfunc_end2-__device_stub__findPrimes
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $doTheThing, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $addArrays, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $findPrimes, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type doTheThing,@object # @doTheThing
.section .rodata,"a",@progbits
.globl doTheThing
.p2align 3, 0x0
doTheThing:
.quad __device_stub__doTheThing
.size doTheThing, 8
.type addArrays,@object # @addArrays
.globl addArrays
.p2align 3, 0x0
addArrays:
.quad __device_stub__addArrays
.size addArrays, 8
.type findPrimes,@object # @findPrimes
.globl findPrimes
.p2align 3, 0x0
findPrimes:
.quad __device_stub__findPrimes
.size findPrimes, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "doTheThing"
.size .L__unnamed_1, 11
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "addArrays"
.size .L__unnamed_2, 10
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "findPrimes"
.size .L__unnamed_3, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__doTheThing
.addrsig_sym __device_stub__addArrays
.addrsig_sym __device_stub__findPrimes
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym doTheThing
.addrsig_sym addArrays
.addrsig_sym findPrimes
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <stdio.h>
// CUDA kernel
__global__ void say_hello()
{
// a CUDA core executes this line
printf("GPU says, Hello world!\n");
}
// CUDA kernel for step 2
__global__ void say_hello2()
{
// a CUDA core executes this line
printf("Thread %d says, Hello world!\n", threadIdx.x);
}
// CUDA kernel for step 3
__global__ void say_hello3()
{
// a CUDA core executes this line
printf("Thread %d in block %d says, Hello world!\n",
threadIdx.x, blockIdx.x);
}
// CUDA kernel for step 4
__global__ void say_hello4()
{
// a CUDA core executes this line
if (blockIdx.x == 0)
printf("Thread %d in block %d says, Hello world!\n",
threadIdx.x, blockIdx.x);
else
printf("Thread %d in block %d says, Hello Umea!\n",
threadIdx.x, blockIdx.x);
}
// CUDA kernel for step 5
__global__ void say_hello5()
{
// a CUDA core executes this line
int thread_id = blockIdx.x * blockDim.x + threadIdx.x;
printf("Thread %d says, Hello world!\n", thread_id);
}
// CUDA kernel for step 6
__global__ void say_hello6()
{
// a CUDA core executes this line
printf("Thread (%d,%d) in block (%d,%d) says, Hello world!\n",
threadIdx.x, threadIdx.y, blockIdx.x, blockIdx.y);
}
int main()
{
// a CPU core executes these lines
printf("====== Step 1 ======\n");
printf("Host says, Hello world!\n");
// call the kernel
say_hello<<<1,1>>>();
// wait until the GPU has executed the kernel
cudaDeviceSynchronize();
printf("====== Step 2 ======\n");
printf("Host says, Hello world!\n");
say_hello2<<<1,16>>>();
cudaDeviceSynchronize();
printf("====== Step 3 ======\n");
printf("Host says, Hello world!\n");
say_hello3<<<2,16>>>();
cudaDeviceSynchronize();
printf("====== Step 4 ======\n");
printf("Host says, Hello world!\n");
say_hello4<<<2,16>>>();
cudaDeviceSynchronize();
printf("====== Step 5 ======\n");
printf("Host says, Hello world!\n");
say_hello5<<<2,16>>>();
cudaDeviceSynchronize();
printf("====== Step 6 ======\n");
printf("Host says, Hello world!\n");
dim3 threads(4, 2);
dim3 blocks(2, 3);
say_hello6<<<blocks,threads>>>();
cudaDeviceSynchronize();
printf("====== Step 7 ======\n");
printf("Host says, Hello world!\n");
//dim3 threads(4, 2);
//dim3 blocks(2, 3);
say_hello6<<<blocks,threads>>>();
return EXIT_SUCCESS;
} | code for sm_80
Function : _Z10say_hello6v
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R11, SR_CTAID.Y ; /* 0x00000000000b7919 */
/* 0x000e220000002600 */
/*0020*/ IADD3 R1, R1, -0x10, RZ ; /* 0xfffffff001017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x28] ; /* 0x01000a00ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R10, SR_CTAID.X ; /* 0x00000000000a7919 */
/* 0x000e220000002500 */
/*0060*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*0070*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x2c] ; /* 0x01000b00ff057624 */
/* 0x000fe200078e00ff */
/*0080*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0002a20000000a00 */
/*0090*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000e240000002200 */
/*00a0*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fc400000e06ff */
/*00b0*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e280000002100 */
/*00c0*/ STL.128 [R1], R8 ; /* 0x0000000801007387 */
/* 0x0013e40000100c00 */
/*00d0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x006fe40000000000 */
/*00e0*/ MOV R11, 0x150 ; /* 0x00000150000b7802 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R20, 0xd0 ; /* 0x000000d000147802 */
/* 0x000fe40000000f00 */
/*0100*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fc40000000f00 */
/*0120*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0130*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0140*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x000fea0003c00000 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10say_hello5v
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R2, 0x0 ; /* 0x0000000000027802 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe400078e00ff */
/*0070*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fca0007f1e0ff */
/*0080*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe400000e06ff */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*00a0*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000e260000000a00 */
/*00b0*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0003e40000100800 */
/*00c0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*00d0*/ MOV R11, 0x140 ; /* 0x00000140000b7802 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R20, 0xc0 ; /* 0x000000c000147802 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fc40000000f00 */
/*0100*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x002fe40000000f00 */
/*0110*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0120*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0130*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x001fea0003c00000 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10say_hello4v
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fc60007ffe0ff */
/*0030*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0040*/ IADD3 R6, P1, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fca0007f3e0ff */
/*0050*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P1 ; /* 0x00000900ff077624 */
/* 0x000fe200008e06ff */
/*0060*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x001fe20003f05270 */
/*0070*/ STL.64 [R1], R2 ; /* 0x0000000201007387 */
/* 0x0021d80000100a00 */
/*0080*/ @!P0 BRA 0x160 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0090*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*00a0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x20] ; /* 0x01000800ff047624 */
/* 0x000fe400078e00ff */
/*00b0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x24] ; /* 0x01000900ff057624 */
/* 0x000fe200078e00ff */
/*00c0*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00106c0000000a00 */
/*00d0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe20000000000 */
/*00e0*/ MOV R11, 0x150 ; /* 0x00000150000b7802 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R20, 0xd0 ; /* 0x000000d000147802 */
/* 0x000fe40000000f00 */
/*0100*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*0120*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0130*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0140*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0170*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x18] ; /* 0x01000600ff047624 */
/* 0x000fe400078e00ff */
/*0180*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x1c] ; /* 0x01000700ff057624 */
/* 0x000fe200078e00ff */
/*0190*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00106c0000000a00 */
/*01a0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe20000000000 */
/*01b0*/ MOV R11, 0x220 ; /* 0x00000220000b7802 */
/* 0x000fe40000000f00 */
/*01c0*/ MOV R20, 0x1a0 ; /* 0x000001a000147802 */
/* 0x000fe40000000f00 */
/*01d0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*01e0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*01f0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0200*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0210*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ BRA 0x230; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10say_hello3v
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e220000002500 */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x18] ; /* 0x01000600ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0060*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*0070*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x1c] ; /* 0x01000700ff057624 */
/* 0x000fe200078e00ff */
/*0080*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0002a60000000a00 */
/*0090*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*00a0*/ STL.64 [R1], R8 ; /* 0x0000000801007387 */
/* 0x0013e80000100a00 */
/*00b0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x002fc60000000000 */
/*00c0*/ MOV R11, 0x130 ; /* 0x00000130000b7802 */
/* 0x000fe40000000f00 */
/*00d0*/ MOV R20, 0xb0 ; /* 0x000000b000147802 */
/* 0x000fc40000000f00 */
/*00e0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0100*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0110*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0120*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x004fea0003c00000 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10say_hello2v
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0050*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe200078e00ff */
/*0060*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe40007f1e0ff */
/*0070*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0002a60000000a00 */
/*0080*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*0090*/ STL [R1], R8 ; /* 0x0000000801007387 */
/* 0x0013e80000100800 */
/*00a0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x002fc60000000000 */
/*00b0*/ MOV R11, 0x120 ; /* 0x00000120000b7802 */
/* 0x000fe40000000f00 */
/*00c0*/ MOV R20, 0xa0 ; /* 0x000000a000147802 */
/* 0x000fc40000000f00 */
/*00d0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*00f0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0100*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0110*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x004fea0003c00000 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9say_hellov
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <stdio.h>
// CUDA kernel
__global__ void say_hello()
{
// a CUDA core executes this line
printf("GPU says, Hello world!\n");
}
// CUDA kernel for step 2
__global__ void say_hello2()
{
// a CUDA core executes this line
printf("Thread %d says, Hello world!\n", threadIdx.x);
}
// CUDA kernel for step 3
__global__ void say_hello3()
{
// a CUDA core executes this line
printf("Thread %d in block %d says, Hello world!\n",
threadIdx.x, blockIdx.x);
}
// CUDA kernel for step 4
__global__ void say_hello4()
{
// a CUDA core executes this line
if (blockIdx.x == 0)
printf("Thread %d in block %d says, Hello world!\n",
threadIdx.x, blockIdx.x);
else
printf("Thread %d in block %d says, Hello Umea!\n",
threadIdx.x, blockIdx.x);
}
// CUDA kernel for step 5
__global__ void say_hello5()
{
// a CUDA core executes this line
int thread_id = blockIdx.x * blockDim.x + threadIdx.x;
printf("Thread %d says, Hello world!\n", thread_id);
}
// CUDA kernel for step 6
__global__ void say_hello6()
{
// a CUDA core executes this line
printf("Thread (%d,%d) in block (%d,%d) says, Hello world!\n",
threadIdx.x, threadIdx.y, blockIdx.x, blockIdx.y);
}
int main()
{
// a CPU core executes these lines
printf("====== Step 1 ======\n");
printf("Host says, Hello world!\n");
// call the kernel
say_hello<<<1,1>>>();
// wait until the GPU has executed the kernel
cudaDeviceSynchronize();
printf("====== Step 2 ======\n");
printf("Host says, Hello world!\n");
say_hello2<<<1,16>>>();
cudaDeviceSynchronize();
printf("====== Step 3 ======\n");
printf("Host says, Hello world!\n");
say_hello3<<<2,16>>>();
cudaDeviceSynchronize();
printf("====== Step 4 ======\n");
printf("Host says, Hello world!\n");
say_hello4<<<2,16>>>();
cudaDeviceSynchronize();
printf("====== Step 5 ======\n");
printf("Host says, Hello world!\n");
say_hello5<<<2,16>>>();
cudaDeviceSynchronize();
printf("====== Step 6 ======\n");
printf("Host says, Hello world!\n");
dim3 threads(4, 2);
dim3 blocks(2, 3);
say_hello6<<<blocks,threads>>>();
cudaDeviceSynchronize();
printf("====== Step 7 ======\n");
printf("Host says, Hello world!\n");
//dim3 threads(4, 2);
//dim3 blocks(2, 3);
say_hello6<<<blocks,threads>>>();
return EXIT_SUCCESS;
} | .file "tmpxft_00061c43_00000000-6_solution.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z9say_hellovv
.type _Z27__device_stub__Z9say_hellovv, @function
_Z27__device_stub__Z9say_hellovv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z9say_hellov(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z9say_hellovv, .-_Z27__device_stub__Z9say_hellovv
.globl _Z9say_hellov
.type _Z9say_hellov, @function
_Z9say_hellov:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z9say_hellovv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9say_hellov, .-_Z9say_hellov
.globl _Z29__device_stub__Z10say_hello2vv
.type _Z29__device_stub__Z10say_hello2vv, @function
_Z29__device_stub__Z10say_hello2vv:
.LFB2084:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10say_hello2v(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z29__device_stub__Z10say_hello2vv, .-_Z29__device_stub__Z10say_hello2vv
.globl _Z10say_hello2v
.type _Z10say_hello2v, @function
_Z10say_hello2v:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10say_hello2vv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z10say_hello2v, .-_Z10say_hello2v
.globl _Z29__device_stub__Z10say_hello3vv
.type _Z29__device_stub__Z10say_hello3vv, @function
_Z29__device_stub__Z10say_hello3vv:
.LFB2086:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10say_hello3v(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z29__device_stub__Z10say_hello3vv, .-_Z29__device_stub__Z10say_hello3vv
.globl _Z10say_hello3v
.type _Z10say_hello3v, @function
_Z10say_hello3v:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10say_hello3vv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z10say_hello3v, .-_Z10say_hello3v
.globl _Z29__device_stub__Z10say_hello4vv
.type _Z29__device_stub__Z10say_hello4vv, @function
_Z29__device_stub__Z10say_hello4vv:
.LFB2088:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10say_hello4v(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z29__device_stub__Z10say_hello4vv, .-_Z29__device_stub__Z10say_hello4vv
.globl _Z10say_hello4v
.type _Z10say_hello4v, @function
_Z10say_hello4v:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10say_hello4vv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z10say_hello4v, .-_Z10say_hello4v
.globl _Z29__device_stub__Z10say_hello5vv
.type _Z29__device_stub__Z10say_hello5vv, @function
_Z29__device_stub__Z10say_hello5vv:
.LFB2090:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10say_hello5v(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z29__device_stub__Z10say_hello5vv, .-_Z29__device_stub__Z10say_hello5vv
.globl _Z10say_hello5v
.type _Z10say_hello5v, @function
_Z10say_hello5v:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10say_hello5vv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z10say_hello5v, .-_Z10say_hello5v
.globl _Z29__device_stub__Z10say_hello6vv
.type _Z29__device_stub__Z10say_hello6vv, @function
_Z29__device_stub__Z10say_hello6vv:
.LFB2092:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L47
.L43:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10say_hello6v(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L43
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2092:
.size _Z29__device_stub__Z10say_hello6vv, .-_Z29__device_stub__Z10say_hello6vv
.globl _Z10say_hello6v
.type _Z10say_hello6v, @function
_Z10say_hello6v:
.LFB2093:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10say_hello6vv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _Z10say_hello6v, .-_Z10say_hello6v
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "====== Step 1 ======\n"
.LC1:
.string "Host says, Hello world!\n"
.LC2:
.string "====== Step 2 ======\n"
.LC3:
.string "====== Step 3 ======\n"
.LC4:
.string "====== Step 4 ======\n"
.LC5:
.string "====== Step 5 ======\n"
.LC6:
.string "====== Step 6 ======\n"
.LC7:
.string "====== Step 7 ======\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L60
.L52:
call cudaDeviceSynchronize@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $16, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L61
.L53:
call cudaDeviceSynchronize@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $16, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $2, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L62
.L54:
call cudaDeviceSynchronize@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $16, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $2, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L63
.L55:
call cudaDeviceSynchronize@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $16, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $2, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L64
.L56:
call cudaDeviceSynchronize@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4, 8(%rsp)
movl $2, 12(%rsp)
movl $1, 16(%rsp)
movl $2, 20(%rsp)
movl $3, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L65
.L57:
call cudaDeviceSynchronize@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 16(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movq 20(%rsp), %rdi
movl 28(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L66
.L58:
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L60:
.cfi_restore_state
call _Z27__device_stub__Z9say_hellovv
jmp .L52
.L61:
call _Z29__device_stub__Z10say_hello2vv
jmp .L53
.L62:
call _Z29__device_stub__Z10say_hello3vv
jmp .L54
.L63:
call _Z29__device_stub__Z10say_hello4vv
jmp .L55
.L64:
call _Z29__device_stub__Z10say_hello5vv
jmp .L56
.L65:
call _Z29__device_stub__Z10say_hello6vv
jmp .L57
.L66:
call _Z29__device_stub__Z10say_hello6vv
jmp .L58
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z10say_hello6v"
.LC9:
.string "_Z10say_hello5v"
.LC10:
.string "_Z10say_hello4v"
.LC11:
.string "_Z10say_hello3v"
.LC12:
.string "_Z10say_hello2v"
.LC13:
.string "_Z9say_hellov"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2095:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z10say_hello6v(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z10say_hello5v(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z10say_hello4v(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z10say_hello3v(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z10say_hello2v(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z9say_hellov(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2095:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <stdio.h>
// CUDA kernel
__global__ void say_hello()
{
// a CUDA core executes this line
printf("GPU says, Hello world!\n");
}
// CUDA kernel for step 2
__global__ void say_hello2()
{
// a CUDA core executes this line
printf("Thread %d says, Hello world!\n", threadIdx.x);
}
// CUDA kernel for step 3
__global__ void say_hello3()
{
// a CUDA core executes this line
printf("Thread %d in block %d says, Hello world!\n",
threadIdx.x, blockIdx.x);
}
// CUDA kernel for step 4
__global__ void say_hello4()
{
// a CUDA core executes this line
if (blockIdx.x == 0)
printf("Thread %d in block %d says, Hello world!\n",
threadIdx.x, blockIdx.x);
else
printf("Thread %d in block %d says, Hello Umea!\n",
threadIdx.x, blockIdx.x);
}
// CUDA kernel for step 5
__global__ void say_hello5()
{
// a CUDA core executes this line
int thread_id = blockIdx.x * blockDim.x + threadIdx.x;
printf("Thread %d says, Hello world!\n", thread_id);
}
// CUDA kernel for step 6
__global__ void say_hello6()
{
// a CUDA core executes this line
printf("Thread (%d,%d) in block (%d,%d) says, Hello world!\n",
threadIdx.x, threadIdx.y, blockIdx.x, blockIdx.y);
}
int main()
{
// a CPU core executes these lines
printf("====== Step 1 ======\n");
printf("Host says, Hello world!\n");
// call the kernel
say_hello<<<1,1>>>();
// wait until the GPU has executed the kernel
cudaDeviceSynchronize();
printf("====== Step 2 ======\n");
printf("Host says, Hello world!\n");
say_hello2<<<1,16>>>();
cudaDeviceSynchronize();
printf("====== Step 3 ======\n");
printf("Host says, Hello world!\n");
say_hello3<<<2,16>>>();
cudaDeviceSynchronize();
printf("====== Step 4 ======\n");
printf("Host says, Hello world!\n");
say_hello4<<<2,16>>>();
cudaDeviceSynchronize();
printf("====== Step 5 ======\n");
printf("Host says, Hello world!\n");
say_hello5<<<2,16>>>();
cudaDeviceSynchronize();
printf("====== Step 6 ======\n");
printf("Host says, Hello world!\n");
dim3 threads(4, 2);
dim3 blocks(2, 3);
say_hello6<<<blocks,threads>>>();
cudaDeviceSynchronize();
printf("====== Step 7 ======\n");
printf("Host says, Hello world!\n");
//dim3 threads(4, 2);
//dim3 blocks(2, 3);
say_hello6<<<blocks,threads>>>();
return EXIT_SUCCESS;
} | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
// CUDA kernel
__global__ void say_hello()
{
// a CUDA core executes this line
printf("GPU says, Hello world!\n");
}
// CUDA kernel for step 2
__global__ void say_hello2()
{
// a CUDA core executes this line
printf("Thread %d says, Hello world!\n", threadIdx.x);
}
// CUDA kernel for step 3
__global__ void say_hello3()
{
// a CUDA core executes this line
printf("Thread %d in block %d says, Hello world!\n",
threadIdx.x, blockIdx.x);
}
// CUDA kernel for step 4
__global__ void say_hello4()
{
// a CUDA core executes this line
if (blockIdx.x == 0)
printf("Thread %d in block %d says, Hello world!\n",
threadIdx.x, blockIdx.x);
else
printf("Thread %d in block %d says, Hello Umea!\n",
threadIdx.x, blockIdx.x);
}
// CUDA kernel for step 5
__global__ void say_hello5()
{
// a CUDA core executes this line
int thread_id = blockIdx.x * blockDim.x + threadIdx.x;
printf("Thread %d says, Hello world!\n", thread_id);
}
// CUDA kernel for step 6
__global__ void say_hello6()
{
// a CUDA core executes this line
printf("Thread (%d,%d) in block (%d,%d) says, Hello world!\n",
threadIdx.x, threadIdx.y, blockIdx.x, blockIdx.y);
}
int main()
{
// a CPU core executes these lines
printf("====== Step 1 ======\n");
printf("Host says, Hello world!\n");
// call the kernel
say_hello<<<1,1>>>();
// wait until the GPU has executed the kernel
hipDeviceSynchronize();
printf("====== Step 2 ======\n");
printf("Host says, Hello world!\n");
say_hello2<<<1,16>>>();
hipDeviceSynchronize();
printf("====== Step 3 ======\n");
printf("Host says, Hello world!\n");
say_hello3<<<2,16>>>();
hipDeviceSynchronize();
printf("====== Step 4 ======\n");
printf("Host says, Hello world!\n");
say_hello4<<<2,16>>>();
hipDeviceSynchronize();
printf("====== Step 5 ======\n");
printf("Host says, Hello world!\n");
say_hello5<<<2,16>>>();
hipDeviceSynchronize();
printf("====== Step 6 ======\n");
printf("Host says, Hello world!\n");
dim3 threads(4, 2);
dim3 blocks(2, 3);
say_hello6<<<blocks,threads>>>();
hipDeviceSynchronize();
printf("====== Step 7 ======\n");
printf("Host says, Hello world!\n");
//dim3 threads(4, 2);
//dim3 blocks(2, 3);
say_hello6<<<blocks,threads>>>();
return EXIT_SUCCESS;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
// CUDA kernel
__global__ void say_hello()
{
// a CUDA core executes this line
printf("GPU says, Hello world!\n");
}
// CUDA kernel for step 2
__global__ void say_hello2()
{
// a CUDA core executes this line
printf("Thread %d says, Hello world!\n", threadIdx.x);
}
// CUDA kernel for step 3
__global__ void say_hello3()
{
// a CUDA core executes this line
printf("Thread %d in block %d says, Hello world!\n",
threadIdx.x, blockIdx.x);
}
// CUDA kernel for step 4
__global__ void say_hello4()
{
// a CUDA core executes this line
if (blockIdx.x == 0)
printf("Thread %d in block %d says, Hello world!\n",
threadIdx.x, blockIdx.x);
else
printf("Thread %d in block %d says, Hello Umea!\n",
threadIdx.x, blockIdx.x);
}
// CUDA kernel for step 5
__global__ void say_hello5()
{
// a CUDA core executes this line
int thread_id = blockIdx.x * blockDim.x + threadIdx.x;
printf("Thread %d says, Hello world!\n", thread_id);
}
// CUDA kernel for step 6
__global__ void say_hello6()
{
// a CUDA core executes this line
printf("Thread (%d,%d) in block (%d,%d) says, Hello world!\n",
threadIdx.x, threadIdx.y, blockIdx.x, blockIdx.y);
}
int main()
{
// a CPU core executes these lines
printf("====== Step 1 ======\n");
printf("Host says, Hello world!\n");
// call the kernel
say_hello<<<1,1>>>();
// wait until the GPU has executed the kernel
hipDeviceSynchronize();
printf("====== Step 2 ======\n");
printf("Host says, Hello world!\n");
say_hello2<<<1,16>>>();
hipDeviceSynchronize();
printf("====== Step 3 ======\n");
printf("Host says, Hello world!\n");
say_hello3<<<2,16>>>();
hipDeviceSynchronize();
printf("====== Step 4 ======\n");
printf("Host says, Hello world!\n");
say_hello4<<<2,16>>>();
hipDeviceSynchronize();
printf("====== Step 5 ======\n");
printf("Host says, Hello world!\n");
say_hello5<<<2,16>>>();
hipDeviceSynchronize();
printf("====== Step 6 ======\n");
printf("Host says, Hello world!\n");
dim3 threads(4, 2);
dim3 blocks(2, 3);
say_hello6<<<blocks,threads>>>();
hipDeviceSynchronize();
printf("====== Step 7 ======\n");
printf("Host says, Hello world!\n");
//dim3 threads(4, 2);
//dim3 blocks(2, 3);
say_hello6<<<blocks,threads>>>();
return EXIT_SUCCESS;
} | .text
.file "solution.hip"
.globl _Z24__device_stub__say_hellov # -- Begin function _Z24__device_stub__say_hellov
.p2align 4, 0x90
.type _Z24__device_stub__say_hellov,@function
_Z24__device_stub__say_hellov: # @_Z24__device_stub__say_hellov
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z9say_hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z24__device_stub__say_hellov, .Lfunc_end0-_Z24__device_stub__say_hellov
.cfi_endproc
# -- End function
.globl _Z25__device_stub__say_hello2v # -- Begin function _Z25__device_stub__say_hello2v
.p2align 4, 0x90
.type _Z25__device_stub__say_hello2v,@function
_Z25__device_stub__say_hello2v: # @_Z25__device_stub__say_hello2v
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10say_hello2v, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end1:
.size _Z25__device_stub__say_hello2v, .Lfunc_end1-_Z25__device_stub__say_hello2v
.cfi_endproc
# -- End function
.globl _Z25__device_stub__say_hello3v # -- Begin function _Z25__device_stub__say_hello3v
.p2align 4, 0x90
.type _Z25__device_stub__say_hello3v,@function
_Z25__device_stub__say_hello3v: # @_Z25__device_stub__say_hello3v
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10say_hello3v, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end2:
.size _Z25__device_stub__say_hello3v, .Lfunc_end2-_Z25__device_stub__say_hello3v
.cfi_endproc
# -- End function
.globl _Z25__device_stub__say_hello4v # -- Begin function _Z25__device_stub__say_hello4v
.p2align 4, 0x90
.type _Z25__device_stub__say_hello4v,@function
_Z25__device_stub__say_hello4v: # @_Z25__device_stub__say_hello4v
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10say_hello4v, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end3:
.size _Z25__device_stub__say_hello4v, .Lfunc_end3-_Z25__device_stub__say_hello4v
.cfi_endproc
# -- End function
.globl _Z25__device_stub__say_hello5v # -- Begin function _Z25__device_stub__say_hello5v
.p2align 4, 0x90
.type _Z25__device_stub__say_hello5v,@function
_Z25__device_stub__say_hello5v: # @_Z25__device_stub__say_hello5v
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10say_hello5v, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end4:
.size _Z25__device_stub__say_hello5v, .Lfunc_end4-_Z25__device_stub__say_hello5v
.cfi_endproc
# -- End function
.globl _Z25__device_stub__say_hello6v # -- Begin function _Z25__device_stub__say_hello6v
.p2align 4, 0x90
.type _Z25__device_stub__say_hello6v,@function
_Z25__device_stub__say_hello6v: # @_Z25__device_stub__say_hello6v
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10say_hello6v, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end5:
.size _Z25__device_stub__say_hello6v, .Lfunc_end5-_Z25__device_stub__say_hello6v
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $56, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movabsq $4294967312, %rbx # imm = 0x100000010
movl $.Lstr, %edi
callq puts@PLT
movl $.Lstr.13, %edi
callq puts@PLT
leaq -15(%rbx), %r14
movq %r14, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z9say_hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_2:
callq hipDeviceSynchronize
movl $.Lstr.2, %edi
callq puts@PLT
movl $.Lstr.13, %edi
callq puts@PLT
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_4
# %bb.3:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10say_hello2v, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_4:
callq hipDeviceSynchronize
movl $.Lstr.4, %edi
callq puts@PLT
movl $.Lstr.13, %edi
callq puts@PLT
leaq -14(%rbx), %r14
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_6
# %bb.5:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10say_hello3v, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_6:
callq hipDeviceSynchronize
movl $.Lstr.6, %edi
callq puts@PLT
movl $.Lstr.13, %edi
callq puts@PLT
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_8
# %bb.7:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10say_hello4v, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_8:
callq hipDeviceSynchronize
movl $.Lstr.8, %edi
callq puts@PLT
movl $.Lstr.13, %edi
callq puts@PLT
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_10
# %bb.9:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10say_hello5v, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_10:
movabsq $12884901890, %r14 # imm = 0x300000002
movabsq $8589934596, %rbx # imm = 0x200000004
callq hipDeviceSynchronize
movl $.Lstr.10, %edi
callq puts@PLT
movl $.Lstr.13, %edi
callq puts@PLT
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_12
# %bb.11:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10say_hello6v, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_12:
callq hipDeviceSynchronize
movl $.Lstr.12, %edi
callq puts@PLT
movl $.Lstr.13, %edi
callq puts@PLT
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_14
# %bb.13:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10say_hello6v, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_14:
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9say_hellov, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10say_hello2v, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10say_hello3v, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10say_hello4v, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10say_hello5v, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10say_hello6v, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9say_hellov,@object # @_Z9say_hellov
.section .rodata,"a",@progbits
.globl _Z9say_hellov
.p2align 3, 0x0
_Z9say_hellov:
.quad _Z24__device_stub__say_hellov
.size _Z9say_hellov, 8
.type _Z10say_hello2v,@object # @_Z10say_hello2v
.globl _Z10say_hello2v
.p2align 3, 0x0
_Z10say_hello2v:
.quad _Z25__device_stub__say_hello2v
.size _Z10say_hello2v, 8
.type _Z10say_hello3v,@object # @_Z10say_hello3v
.globl _Z10say_hello3v
.p2align 3, 0x0
_Z10say_hello3v:
.quad _Z25__device_stub__say_hello3v
.size _Z10say_hello3v, 8
.type _Z10say_hello4v,@object # @_Z10say_hello4v
.globl _Z10say_hello4v
.p2align 3, 0x0
_Z10say_hello4v:
.quad _Z25__device_stub__say_hello4v
.size _Z10say_hello4v, 8
.type _Z10say_hello5v,@object # @_Z10say_hello5v
.globl _Z10say_hello5v
.p2align 3, 0x0
_Z10say_hello5v:
.quad _Z25__device_stub__say_hello5v
.size _Z10say_hello5v, 8
.type _Z10say_hello6v,@object # @_Z10say_hello6v
.globl _Z10say_hello6v
.p2align 3, 0x0
_Z10say_hello6v:
.quad _Z25__device_stub__say_hello6v
.size _Z10say_hello6v, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9say_hellov"
.size .L__unnamed_1, 14
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10say_hello2v"
.size .L__unnamed_2, 16
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z10say_hello3v"
.size .L__unnamed_3, 16
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z10say_hello4v"
.size .L__unnamed_4, 16
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z10say_hello5v"
.size .L__unnamed_5, 16
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "_Z10say_hello6v"
.size .L__unnamed_6, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "====== Step 1 ======"
.size .Lstr, 21
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "====== Step 2 ======"
.size .Lstr.2, 21
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "====== Step 3 ======"
.size .Lstr.4, 21
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "====== Step 4 ======"
.size .Lstr.6, 21
.type .Lstr.8,@object # @str.8
.Lstr.8:
.asciz "====== Step 5 ======"
.size .Lstr.8, 21
.type .Lstr.10,@object # @str.10
.Lstr.10:
.asciz "====== Step 6 ======"
.size .Lstr.10, 21
.type .Lstr.12,@object # @str.12
.Lstr.12:
.asciz "====== Step 7 ======"
.size .Lstr.12, 21
.type .Lstr.13,@object # @str.13
.Lstr.13:
.asciz "Host says, Hello world!"
.size .Lstr.13, 24
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__say_hellov
.addrsig_sym _Z25__device_stub__say_hello2v
.addrsig_sym _Z25__device_stub__say_hello3v
.addrsig_sym _Z25__device_stub__say_hello4v
.addrsig_sym _Z25__device_stub__say_hello5v
.addrsig_sym _Z25__device_stub__say_hello6v
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9say_hellov
.addrsig_sym _Z10say_hello2v
.addrsig_sym _Z10say_hello3v
.addrsig_sym _Z10say_hello4v
.addrsig_sym _Z10say_hello5v
.addrsig_sym _Z10say_hello6v
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00061c43_00000000-6_solution.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z9say_hellovv
.type _Z27__device_stub__Z9say_hellovv, @function
_Z27__device_stub__Z9say_hellovv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z9say_hellov(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z9say_hellovv, .-_Z27__device_stub__Z9say_hellovv
.globl _Z9say_hellov
.type _Z9say_hellov, @function
_Z9say_hellov:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z9say_hellovv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9say_hellov, .-_Z9say_hellov
.globl _Z29__device_stub__Z10say_hello2vv
.type _Z29__device_stub__Z10say_hello2vv, @function
_Z29__device_stub__Z10say_hello2vv:
.LFB2084:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10say_hello2v(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z29__device_stub__Z10say_hello2vv, .-_Z29__device_stub__Z10say_hello2vv
.globl _Z10say_hello2v
.type _Z10say_hello2v, @function
_Z10say_hello2v:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10say_hello2vv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z10say_hello2v, .-_Z10say_hello2v
.globl _Z29__device_stub__Z10say_hello3vv
.type _Z29__device_stub__Z10say_hello3vv, @function
_Z29__device_stub__Z10say_hello3vv:
.LFB2086:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10say_hello3v(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z29__device_stub__Z10say_hello3vv, .-_Z29__device_stub__Z10say_hello3vv
.globl _Z10say_hello3v
.type _Z10say_hello3v, @function
_Z10say_hello3v:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10say_hello3vv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z10say_hello3v, .-_Z10say_hello3v
.globl _Z29__device_stub__Z10say_hello4vv
.type _Z29__device_stub__Z10say_hello4vv, @function
_Z29__device_stub__Z10say_hello4vv:
.LFB2088:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10say_hello4v(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z29__device_stub__Z10say_hello4vv, .-_Z29__device_stub__Z10say_hello4vv
.globl _Z10say_hello4v
.type _Z10say_hello4v, @function
_Z10say_hello4v:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10say_hello4vv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z10say_hello4v, .-_Z10say_hello4v
.globl _Z29__device_stub__Z10say_hello5vv
.type _Z29__device_stub__Z10say_hello5vv, @function
_Z29__device_stub__Z10say_hello5vv:
.LFB2090:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10say_hello5v(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z29__device_stub__Z10say_hello5vv, .-_Z29__device_stub__Z10say_hello5vv
.globl _Z10say_hello5v
.type _Z10say_hello5v, @function
_Z10say_hello5v:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10say_hello5vv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z10say_hello5v, .-_Z10say_hello5v
.globl _Z29__device_stub__Z10say_hello6vv
.type _Z29__device_stub__Z10say_hello6vv, @function
_Z29__device_stub__Z10say_hello6vv:
.LFB2092:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L47
.L43:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10say_hello6v(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L43
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2092:
.size _Z29__device_stub__Z10say_hello6vv, .-_Z29__device_stub__Z10say_hello6vv
.globl _Z10say_hello6v
.type _Z10say_hello6v, @function
_Z10say_hello6v:
.LFB2093:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10say_hello6vv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _Z10say_hello6v, .-_Z10say_hello6v
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "====== Step 1 ======\n"
.LC1:
.string "Host says, Hello world!\n"
.LC2:
.string "====== Step 2 ======\n"
.LC3:
.string "====== Step 3 ======\n"
.LC4:
.string "====== Step 4 ======\n"
.LC5:
.string "====== Step 5 ======\n"
.LC6:
.string "====== Step 6 ======\n"
.LC7:
.string "====== Step 7 ======\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L60
.L52:
call cudaDeviceSynchronize@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $16, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L61
.L53:
call cudaDeviceSynchronize@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $16, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $2, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L62
.L54:
call cudaDeviceSynchronize@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $16, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $2, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L63
.L55:
call cudaDeviceSynchronize@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $16, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $2, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L64
.L56:
call cudaDeviceSynchronize@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4, 8(%rsp)
movl $2, 12(%rsp)
movl $1, 16(%rsp)
movl $2, 20(%rsp)
movl $3, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L65
.L57:
call cudaDeviceSynchronize@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 16(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movq 20(%rsp), %rdi
movl 28(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L66
.L58:
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L60:
.cfi_restore_state
call _Z27__device_stub__Z9say_hellovv
jmp .L52
.L61:
call _Z29__device_stub__Z10say_hello2vv
jmp .L53
.L62:
call _Z29__device_stub__Z10say_hello3vv
jmp .L54
.L63:
call _Z29__device_stub__Z10say_hello4vv
jmp .L55
.L64:
call _Z29__device_stub__Z10say_hello5vv
jmp .L56
.L65:
call _Z29__device_stub__Z10say_hello6vv
jmp .L57
.L66:
call _Z29__device_stub__Z10say_hello6vv
jmp .L58
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z10say_hello6v"
.LC9:
.string "_Z10say_hello5v"
.LC10:
.string "_Z10say_hello4v"
.LC11:
.string "_Z10say_hello3v"
.LC12:
.string "_Z10say_hello2v"
.LC13:
.string "_Z9say_hellov"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2095:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z10say_hello6v(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z10say_hello5v(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z10say_hello4v(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z10say_hello3v(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z10say_hello2v(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z9say_hellov(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2095:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "solution.hip"
.globl _Z24__device_stub__say_hellov # -- Begin function _Z24__device_stub__say_hellov
.p2align 4, 0x90
.type _Z24__device_stub__say_hellov,@function
_Z24__device_stub__say_hellov: # @_Z24__device_stub__say_hellov
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z9say_hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z24__device_stub__say_hellov, .Lfunc_end0-_Z24__device_stub__say_hellov
.cfi_endproc
# -- End function
.globl _Z25__device_stub__say_hello2v # -- Begin function _Z25__device_stub__say_hello2v
.p2align 4, 0x90
.type _Z25__device_stub__say_hello2v,@function
_Z25__device_stub__say_hello2v: # @_Z25__device_stub__say_hello2v
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10say_hello2v, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end1:
.size _Z25__device_stub__say_hello2v, .Lfunc_end1-_Z25__device_stub__say_hello2v
.cfi_endproc
# -- End function
.globl _Z25__device_stub__say_hello3v # -- Begin function _Z25__device_stub__say_hello3v
.p2align 4, 0x90
.type _Z25__device_stub__say_hello3v,@function
_Z25__device_stub__say_hello3v: # @_Z25__device_stub__say_hello3v
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10say_hello3v, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end2:
.size _Z25__device_stub__say_hello3v, .Lfunc_end2-_Z25__device_stub__say_hello3v
.cfi_endproc
# -- End function
.globl _Z25__device_stub__say_hello4v # -- Begin function _Z25__device_stub__say_hello4v
.p2align 4, 0x90
.type _Z25__device_stub__say_hello4v,@function
_Z25__device_stub__say_hello4v: # @_Z25__device_stub__say_hello4v
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10say_hello4v, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end3:
.size _Z25__device_stub__say_hello4v, .Lfunc_end3-_Z25__device_stub__say_hello4v
.cfi_endproc
# -- End function
.globl _Z25__device_stub__say_hello5v # -- Begin function _Z25__device_stub__say_hello5v
.p2align 4, 0x90
.type _Z25__device_stub__say_hello5v,@function
_Z25__device_stub__say_hello5v: # @_Z25__device_stub__say_hello5v
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10say_hello5v, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end4:
.size _Z25__device_stub__say_hello5v, .Lfunc_end4-_Z25__device_stub__say_hello5v
.cfi_endproc
# -- End function
.globl _Z25__device_stub__say_hello6v # -- Begin function _Z25__device_stub__say_hello6v
.p2align 4, 0x90
.type _Z25__device_stub__say_hello6v,@function
_Z25__device_stub__say_hello6v: # @_Z25__device_stub__say_hello6v
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10say_hello6v, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end5:
.size _Z25__device_stub__say_hello6v, .Lfunc_end5-_Z25__device_stub__say_hello6v
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $56, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movabsq $4294967312, %rbx # imm = 0x100000010
movl $.Lstr, %edi
callq puts@PLT
movl $.Lstr.13, %edi
callq puts@PLT
leaq -15(%rbx), %r14
movq %r14, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z9say_hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_2:
callq hipDeviceSynchronize
movl $.Lstr.2, %edi
callq puts@PLT
movl $.Lstr.13, %edi
callq puts@PLT
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_4
# %bb.3:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10say_hello2v, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_4:
callq hipDeviceSynchronize
movl $.Lstr.4, %edi
callq puts@PLT
movl $.Lstr.13, %edi
callq puts@PLT
leaq -14(%rbx), %r14
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_6
# %bb.5:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10say_hello3v, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_6:
callq hipDeviceSynchronize
movl $.Lstr.6, %edi
callq puts@PLT
movl $.Lstr.13, %edi
callq puts@PLT
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_8
# %bb.7:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10say_hello4v, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_8:
callq hipDeviceSynchronize
movl $.Lstr.8, %edi
callq puts@PLT
movl $.Lstr.13, %edi
callq puts@PLT
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_10
# %bb.9:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10say_hello5v, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_10:
movabsq $12884901890, %r14 # imm = 0x300000002
movabsq $8589934596, %rbx # imm = 0x200000004
callq hipDeviceSynchronize
movl $.Lstr.10, %edi
callq puts@PLT
movl $.Lstr.13, %edi
callq puts@PLT
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_12
# %bb.11:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10say_hello6v, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_12:
callq hipDeviceSynchronize
movl $.Lstr.12, %edi
callq puts@PLT
movl $.Lstr.13, %edi
callq puts@PLT
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_14
# %bb.13:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10say_hello6v, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_14:
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9say_hellov, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10say_hello2v, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10say_hello3v, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10say_hello4v, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10say_hello5v, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10say_hello6v, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9say_hellov,@object # @_Z9say_hellov
.section .rodata,"a",@progbits
.globl _Z9say_hellov
.p2align 3, 0x0
_Z9say_hellov:
.quad _Z24__device_stub__say_hellov
.size _Z9say_hellov, 8
.type _Z10say_hello2v,@object # @_Z10say_hello2v
.globl _Z10say_hello2v
.p2align 3, 0x0
_Z10say_hello2v:
.quad _Z25__device_stub__say_hello2v
.size _Z10say_hello2v, 8
.type _Z10say_hello3v,@object # @_Z10say_hello3v
.globl _Z10say_hello3v
.p2align 3, 0x0
_Z10say_hello3v:
.quad _Z25__device_stub__say_hello3v
.size _Z10say_hello3v, 8
.type _Z10say_hello4v,@object # @_Z10say_hello4v
.globl _Z10say_hello4v
.p2align 3, 0x0
_Z10say_hello4v:
.quad _Z25__device_stub__say_hello4v
.size _Z10say_hello4v, 8
.type _Z10say_hello5v,@object # @_Z10say_hello5v
.globl _Z10say_hello5v
.p2align 3, 0x0
_Z10say_hello5v:
.quad _Z25__device_stub__say_hello5v
.size _Z10say_hello5v, 8
.type _Z10say_hello6v,@object # @_Z10say_hello6v
.globl _Z10say_hello6v
.p2align 3, 0x0
_Z10say_hello6v:
.quad _Z25__device_stub__say_hello6v
.size _Z10say_hello6v, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9say_hellov"
.size .L__unnamed_1, 14
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10say_hello2v"
.size .L__unnamed_2, 16
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z10say_hello3v"
.size .L__unnamed_3, 16
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z10say_hello4v"
.size .L__unnamed_4, 16
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z10say_hello5v"
.size .L__unnamed_5, 16
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "_Z10say_hello6v"
.size .L__unnamed_6, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "====== Step 1 ======"
.size .Lstr, 21
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "====== Step 2 ======"
.size .Lstr.2, 21
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "====== Step 3 ======"
.size .Lstr.4, 21
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "====== Step 4 ======"
.size .Lstr.6, 21
.type .Lstr.8,@object # @str.8
.Lstr.8:
.asciz "====== Step 5 ======"
.size .Lstr.8, 21
.type .Lstr.10,@object # @str.10
.Lstr.10:
.asciz "====== Step 6 ======"
.size .Lstr.10, 21
.type .Lstr.12,@object # @str.12
.Lstr.12:
.asciz "====== Step 7 ======"
.size .Lstr.12, 21
.type .Lstr.13,@object # @str.13
.Lstr.13:
.asciz "Host says, Hello world!"
.size .Lstr.13, 24
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__say_hellov
.addrsig_sym _Z25__device_stub__say_hello2v
.addrsig_sym _Z25__device_stub__say_hello3v
.addrsig_sym _Z25__device_stub__say_hello4v
.addrsig_sym _Z25__device_stub__say_hello5v
.addrsig_sym _Z25__device_stub__say_hello6v
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9say_hellov
.addrsig_sym _Z10say_hello2v
.addrsig_sym _Z10say_hello3v
.addrsig_sym _Z10say_hello4v
.addrsig_sym _Z10say_hello5v
.addrsig_sym _Z10say_hello6v
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#define HANDLE_ERROR( err ) ( HandleError( err, __FILE__, __LINE__ ) )
static void HandleError( cudaError_t err, const char *file, int line )
{
if (err != cudaSuccess)
{
printf( "%s in %s at line %d\n", cudaGetErrorString( err ),
file, line );
exit( EXIT_FAILURE );
}
}
const int N = 2048;
// CUDA Kernel for Vector Addition
__global__ void
Vector_Addition ( const int *dev_a , const int *dev_b , int *dev_c)
{
//Get the id of thread within a block
unsigned int tid = blockIdx.x * blockDim.x + threadIdx.x ;
while ( tid < N ) // check the boundry condition for the threads
{
dev_c [tid] = dev_a[tid] + dev_b[tid] ;
tid+= blockDim.x * gridDim.x ;
}
}
int
main (void)
{
//Host array
int Host_a[N], Host_b[N], Host_c[N];
//Device array
int *dev_a , *dev_b, *dev_c ;
//Grid and Block dimensions
dim3 grid((N+127)/128);
dim3 block(128);
//Allocate the memory on the GPU
HANDLE_ERROR ( cudaMalloc((void **)&dev_a , N*sizeof(int) ) );
HANDLE_ERROR ( cudaMalloc((void **)&dev_b , N*sizeof(int) ) );
HANDLE_ERROR ( cudaMalloc((void **)&dev_c , N*sizeof(int) ) );
//fill the Host array with random elements on the CPU
for ( int i = 0; i <N ; i++ )
{
Host_a[i] = -i ;
Host_b[i] = i*i ;
}
//Copy Host array to Device array
HANDLE_ERROR (cudaMemcpy (dev_a , Host_a , N*sizeof(int) , cudaMemcpyHostToDevice));
HANDLE_ERROR (cudaMemcpy (dev_b , Host_b , N*sizeof(int) , cudaMemcpyHostToDevice));
//Make a call to GPU kernel
Vector_Addition <<< grid, block >>> (dev_a , dev_b , dev_c ) ;
//Copy back to Host array from Device array
HANDLE_ERROR (cudaMemcpy(Host_c , dev_c , N*sizeof(int) , cudaMemcpyDeviceToHost));
//Display the result
for ( int i = 0; i<N; i++ )
printf ("%d + %d = %d\n", Host_a[i] , Host_b[i] , Host_c[i] ) ;
//Free the Device array memory
cudaFree (dev_a) ;
cudaFree (dev_b) ;
cudaFree (dev_c) ;
return 0 ;
} | code for sm_80
Function : _Z15Vector_AdditionPKiS0_Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.U32.AND P0, PT, R0, 0x7ff, PT ; /* 0x000007ff0000780c */
/* 0x000fda0003f04070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE.U32 R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0007 */
/*0090*/ IMAD.WIDE.U32 R4, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0007 */
/*00a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE.U32 R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0007 */
/*00d0*/ MOV R11, c[0x0][0x0] ; /* 0x00000000000b7a02 */
/* 0x000fca0000000f00 */
/*00e0*/ IMAD R0, R11, c[0x0][0xc], R0 ; /* 0x000003000b007a24 */
/* 0x000fca00078e0200 */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R0, 0x800, PT ; /* 0x000008000000780c */
/* 0x000fe40003f06070 */
/*0100*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*0110*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001ec000c101904 */
/*0120*/ @!P0 BRA 0x70 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#define HANDLE_ERROR( err ) ( HandleError( err, __FILE__, __LINE__ ) )
static void HandleError( cudaError_t err, const char *file, int line )
{
if (err != cudaSuccess)
{
printf( "%s in %s at line %d\n", cudaGetErrorString( err ),
file, line );
exit( EXIT_FAILURE );
}
}
const int N = 2048;
// CUDA Kernel for Vector Addition
__global__ void
Vector_Addition ( const int *dev_a , const int *dev_b , int *dev_c)
{
//Get the id of thread within a block
unsigned int tid = blockIdx.x * blockDim.x + threadIdx.x ;
while ( tid < N ) // check the boundry condition for the threads
{
dev_c [tid] = dev_a[tid] + dev_b[tid] ;
tid+= blockDim.x * gridDim.x ;
}
}
int
main (void)
{
//Host array
int Host_a[N], Host_b[N], Host_c[N];
//Device array
int *dev_a , *dev_b, *dev_c ;
//Grid and Block dimensions
dim3 grid((N+127)/128);
dim3 block(128);
//Allocate the memory on the GPU
HANDLE_ERROR ( cudaMalloc((void **)&dev_a , N*sizeof(int) ) );
HANDLE_ERROR ( cudaMalloc((void **)&dev_b , N*sizeof(int) ) );
HANDLE_ERROR ( cudaMalloc((void **)&dev_c , N*sizeof(int) ) );
//fill the Host array with random elements on the CPU
for ( int i = 0; i <N ; i++ )
{
Host_a[i] = -i ;
Host_b[i] = i*i ;
}
//Copy Host array to Device array
HANDLE_ERROR (cudaMemcpy (dev_a , Host_a , N*sizeof(int) , cudaMemcpyHostToDevice));
HANDLE_ERROR (cudaMemcpy (dev_b , Host_b , N*sizeof(int) , cudaMemcpyHostToDevice));
//Make a call to GPU kernel
Vector_Addition <<< grid, block >>> (dev_a , dev_b , dev_c ) ;
//Copy back to Host array from Device array
HANDLE_ERROR (cudaMemcpy(Host_c , dev_c , N*sizeof(int) , cudaMemcpyDeviceToHost));
//Display the result
for ( int i = 0; i<N; i++ )
printf ("%d + %d = %d\n", Host_a[i] , Host_b[i] , Host_c[i] ) ;
//Free the Device array memory
cudaFree (dev_a) ;
cudaFree (dev_b) ;
cudaFree (dev_c) ;
return 0 ;
} | .file "tmpxft_00141335_00000000-6_add.cudafe1.cpp"
.text
#APP
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s in %s at line %d\n"
#NO_APP
.text
.type _ZL11HandleError9cudaErrorPKci, @function
_ZL11HandleError9cudaErrorPKci:
.LFB2057:
.cfi_startproc
testl %edi, %edi
jne .L6
ret
.L6:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbx
movl %edx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rdx
movl %ebp, %r8d
movq %rbx, %rcx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _ZL11HandleError9cudaErrorPKci, .-_ZL11HandleError9cudaErrorPKci
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z15Vector_AdditionPKiS0_PiPKiS0_Pi
.type _Z41__device_stub__Z15Vector_AdditionPKiS0_PiPKiS0_Pi, @function
_Z41__device_stub__Z15Vector_AdditionPKiS0_PiPKiS0_Pi:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15Vector_AdditionPKiS0_Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z41__device_stub__Z15Vector_AdditionPKiS0_PiPKiS0_Pi, .-_Z41__device_stub__Z15Vector_AdditionPKiS0_PiPKiS0_Pi
.globl _Z15Vector_AdditionPKiS0_Pi
.type _Z15Vector_AdditionPKiS0_Pi, @function
_Z15Vector_AdditionPKiS0_Pi:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z15Vector_AdditionPKiS0_PiPKiS0_Pi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z15Vector_AdditionPKiS0_Pi, .-_Z15Vector_AdditionPKiS0_Pi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/socal-ucr/NVIDIA-recon/master/suite/vector-addition/add.cu"
.section .rodata.str1.1
.LC2:
.string "%d + %d = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
leaq -24576(%rsp), %r11
.cfi_def_cfa 11, 24600
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $72, %rsp
.cfi_def_cfa_offset 24672
movq %fs:40, %rax
movq %rax, 24632(%rsp)
xorl %eax, %eax
movl $16, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $128, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movq %rsp, %rdi
movl $8192, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $48, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 8(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $49, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 16(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $50, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
movl $0, %eax
.L18:
movl %eax, %edx
negl %edx
movl %edx, 48(%rsp,%rax,4)
movl %eax, %edx
imull %eax, %edx
movl %edx, 8240(%rsp,%rax,4)
addq $1, %rax
cmpq $2048, %rax
jne .L18
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $8192, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $60, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 8240(%rsp), %rsi
movl $1, %ecx
movl $8192, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $61, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
movl 44(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movq 24(%rsp), %rdi
movl 32(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L19:
leaq 16432(%rsp), %rdi
movl $2, %ecx
movl $8192, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl %eax, %edi
movl $67, %edx
leaq .LC1(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
movl $0, %ebx
leaq .LC2(%rip), %rbp
.L20:
movl 8240(%rsp,%rbx), %ecx
movl 48(%rsp,%rbx), %edx
movl 16432(%rsp,%rbx), %r8d
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $8192, %rbx
jne .L20
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24632(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $24648, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z41__device_stub__Z15Vector_AdditionPKiS0_PiPKiS0_Pi
jmp .L19
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z15Vector_AdditionPKiS0_Pi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z15Vector_AdditionPKiS0_Pi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#define HANDLE_ERROR( err ) ( HandleError( err, __FILE__, __LINE__ ) )
static void HandleError( cudaError_t err, const char *file, int line )
{
if (err != cudaSuccess)
{
printf( "%s in %s at line %d\n", cudaGetErrorString( err ),
file, line );
exit( EXIT_FAILURE );
}
}
const int N = 2048;
// CUDA Kernel for Vector Addition
__global__ void
Vector_Addition ( const int *dev_a , const int *dev_b , int *dev_c)
{
//Get the id of thread within a block
unsigned int tid = blockIdx.x * blockDim.x + threadIdx.x ;
while ( tid < N ) // check the boundry condition for the threads
{
dev_c [tid] = dev_a[tid] + dev_b[tid] ;
tid+= blockDim.x * gridDim.x ;
}
}
int
main (void)
{
//Host array
int Host_a[N], Host_b[N], Host_c[N];
//Device array
int *dev_a , *dev_b, *dev_c ;
//Grid and Block dimensions
dim3 grid((N+127)/128);
dim3 block(128);
//Allocate the memory on the GPU
HANDLE_ERROR ( cudaMalloc((void **)&dev_a , N*sizeof(int) ) );
HANDLE_ERROR ( cudaMalloc((void **)&dev_b , N*sizeof(int) ) );
HANDLE_ERROR ( cudaMalloc((void **)&dev_c , N*sizeof(int) ) );
//fill the Host array with random elements on the CPU
for ( int i = 0; i <N ; i++ )
{
Host_a[i] = -i ;
Host_b[i] = i*i ;
}
//Copy Host array to Device array
HANDLE_ERROR (cudaMemcpy (dev_a , Host_a , N*sizeof(int) , cudaMemcpyHostToDevice));
HANDLE_ERROR (cudaMemcpy (dev_b , Host_b , N*sizeof(int) , cudaMemcpyHostToDevice));
//Make a call to GPU kernel
Vector_Addition <<< grid, block >>> (dev_a , dev_b , dev_c ) ;
//Copy back to Host array from Device array
HANDLE_ERROR (cudaMemcpy(Host_c , dev_c , N*sizeof(int) , cudaMemcpyDeviceToHost));
//Display the result
for ( int i = 0; i<N; i++ )
printf ("%d + %d = %d\n", Host_a[i] , Host_b[i] , Host_c[i] ) ;
//Free the Device array memory
cudaFree (dev_a) ;
cudaFree (dev_b) ;
cudaFree (dev_c) ;
return 0 ;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define HANDLE_ERROR( err ) ( HandleError( err, __FILE__, __LINE__ ) )
static void HandleError( hipError_t err, const char *file, int line )
{
if (err != hipSuccess)
{
printf( "%s in %s at line %d\n", hipGetErrorString( err ),
file, line );
exit( EXIT_FAILURE );
}
}
const int N = 2048;
// CUDA Kernel for Vector Addition
__global__ void
Vector_Addition ( const int *dev_a , const int *dev_b , int *dev_c)
{
//Get the id of thread within a block
unsigned int tid = blockIdx.x * blockDim.x + threadIdx.x ;
while ( tid < N ) // check the boundry condition for the threads
{
dev_c [tid] = dev_a[tid] + dev_b[tid] ;
tid+= blockDim.x * gridDim.x ;
}
}
int
main (void)
{
//Host array
int Host_a[N], Host_b[N], Host_c[N];
//Device array
int *dev_a , *dev_b, *dev_c ;
//Grid and Block dimensions
dim3 grid((N+127)/128);
dim3 block(128);
//Allocate the memory on the GPU
HANDLE_ERROR ( hipMalloc((void **)&dev_a , N*sizeof(int) ) );
HANDLE_ERROR ( hipMalloc((void **)&dev_b , N*sizeof(int) ) );
HANDLE_ERROR ( hipMalloc((void **)&dev_c , N*sizeof(int) ) );
//fill the Host array with random elements on the CPU
for ( int i = 0; i <N ; i++ )
{
Host_a[i] = -i ;
Host_b[i] = i*i ;
}
//Copy Host array to Device array
HANDLE_ERROR (hipMemcpy (dev_a , Host_a , N*sizeof(int) , hipMemcpyHostToDevice));
HANDLE_ERROR (hipMemcpy (dev_b , Host_b , N*sizeof(int) , hipMemcpyHostToDevice));
//Make a call to GPU kernel
Vector_Addition <<< grid, block >>> (dev_a , dev_b , dev_c ) ;
//Copy back to Host array from Device array
HANDLE_ERROR (hipMemcpy(Host_c , dev_c , N*sizeof(int) , hipMemcpyDeviceToHost));
//Display the result
for ( int i = 0; i<N; i++ )
printf ("%d + %d = %d\n", Host_a[i] , Host_b[i] , Host_c[i] ) ;
//Free the Device array memory
hipFree (dev_a) ;
hipFree (dev_b) ;
hipFree (dev_c) ;
return 0 ;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define HANDLE_ERROR( err ) ( HandleError( err, __FILE__, __LINE__ ) )
static void HandleError( hipError_t err, const char *file, int line )
{
if (err != hipSuccess)
{
printf( "%s in %s at line %d\n", hipGetErrorString( err ),
file, line );
exit( EXIT_FAILURE );
}
}
const int N = 2048;
// CUDA Kernel for Vector Addition
__global__ void
Vector_Addition ( const int *dev_a , const int *dev_b , int *dev_c)
{
//Get the id of thread within a block
unsigned int tid = blockIdx.x * blockDim.x + threadIdx.x ;
while ( tid < N ) // check the boundry condition for the threads
{
dev_c [tid] = dev_a[tid] + dev_b[tid] ;
tid+= blockDim.x * gridDim.x ;
}
}
int
main (void)
{
//Host array
int Host_a[N], Host_b[N], Host_c[N];
//Device array
int *dev_a , *dev_b, *dev_c ;
//Grid and Block dimensions
dim3 grid((N+127)/128);
dim3 block(128);
//Allocate the memory on the GPU
HANDLE_ERROR ( hipMalloc((void **)&dev_a , N*sizeof(int) ) );
HANDLE_ERROR ( hipMalloc((void **)&dev_b , N*sizeof(int) ) );
HANDLE_ERROR ( hipMalloc((void **)&dev_c , N*sizeof(int) ) );
//fill the Host array with random elements on the CPU
for ( int i = 0; i <N ; i++ )
{
Host_a[i] = -i ;
Host_b[i] = i*i ;
}
//Copy Host array to Device array
HANDLE_ERROR (hipMemcpy (dev_a , Host_a , N*sizeof(int) , hipMemcpyHostToDevice));
HANDLE_ERROR (hipMemcpy (dev_b , Host_b , N*sizeof(int) , hipMemcpyHostToDevice));
//Make a call to GPU kernel
Vector_Addition <<< grid, block >>> (dev_a , dev_b , dev_c ) ;
//Copy back to Host array from Device array
HANDLE_ERROR (hipMemcpy(Host_c , dev_c , N*sizeof(int) , hipMemcpyDeviceToHost));
//Display the result
for ( int i = 0; i<N; i++ )
printf ("%d + %d = %d\n", Host_a[i] , Host_b[i] , Host_c[i] ) ;
//Free the Device array memory
hipFree (dev_a) ;
hipFree (dev_b) ;
hipFree (dev_c) ;
return 0 ;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15Vector_AdditionPKiS0_Pi
.globl _Z15Vector_AdditionPKiS0_Pi
.p2align 8
.type _Z15Vector_AdditionPKiS0_Pi,@function
_Z15Vector_AdditionPKiS0_Pi:
s_load_b32 s4, s[0:1], 0x24
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e32 0x800, v1
s_cbranch_execz .LBB0_3
s_load_b32 s9, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s9, s8
s_mov_b32 s8, 0
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_add_co_u32 v5, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v4, vcc_lo
v_cmp_lt_u32_e32 vcc_lo, 0x7ff, v1
global_load_b32 v0, v[5:6], off
global_load_b32 v5, v[7:8], off
v_add_co_u32 v3, s0, s2, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s0, s3, v4, s0
s_or_b32 s8, vcc_lo, s8
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v5, v0
global_store_b32 v[3:4], v0, off
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15Vector_AdditionPKiS0_Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15Vector_AdditionPKiS0_Pi, .Lfunc_end0-_Z15Vector_AdditionPKiS0_Pi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15Vector_AdditionPKiS0_Pi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15Vector_AdditionPKiS0_Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define HANDLE_ERROR( err ) ( HandleError( err, __FILE__, __LINE__ ) )
static void HandleError( hipError_t err, const char *file, int line )
{
if (err != hipSuccess)
{
printf( "%s in %s at line %d\n", hipGetErrorString( err ),
file, line );
exit( EXIT_FAILURE );
}
}
const int N = 2048;
// CUDA Kernel for Vector Addition
__global__ void
Vector_Addition ( const int *dev_a , const int *dev_b , int *dev_c)
{
//Get the id of thread within a block
unsigned int tid = blockIdx.x * blockDim.x + threadIdx.x ;
while ( tid < N ) // check the boundry condition for the threads
{
dev_c [tid] = dev_a[tid] + dev_b[tid] ;
tid+= blockDim.x * gridDim.x ;
}
}
int
main (void)
{
//Host array
int Host_a[N], Host_b[N], Host_c[N];
//Device array
int *dev_a , *dev_b, *dev_c ;
//Grid and Block dimensions
dim3 grid((N+127)/128);
dim3 block(128);
//Allocate the memory on the GPU
HANDLE_ERROR ( hipMalloc((void **)&dev_a , N*sizeof(int) ) );
HANDLE_ERROR ( hipMalloc((void **)&dev_b , N*sizeof(int) ) );
HANDLE_ERROR ( hipMalloc((void **)&dev_c , N*sizeof(int) ) );
//fill the Host array with random elements on the CPU
for ( int i = 0; i <N ; i++ )
{
Host_a[i] = -i ;
Host_b[i] = i*i ;
}
//Copy Host array to Device array
HANDLE_ERROR (hipMemcpy (dev_a , Host_a , N*sizeof(int) , hipMemcpyHostToDevice));
HANDLE_ERROR (hipMemcpy (dev_b , Host_b , N*sizeof(int) , hipMemcpyHostToDevice));
//Make a call to GPU kernel
Vector_Addition <<< grid, block >>> (dev_a , dev_b , dev_c ) ;
//Copy back to Host array from Device array
HANDLE_ERROR (hipMemcpy(Host_c , dev_c , N*sizeof(int) , hipMemcpyDeviceToHost));
//Display the result
for ( int i = 0; i<N; i++ )
printf ("%d + %d = %d\n", Host_a[i] , Host_b[i] , Host_c[i] ) ;
//Free the Device array memory
hipFree (dev_a) ;
hipFree (dev_b) ;
hipFree (dev_c) ;
return 0 ;
} | .text
.file "add.hip"
.globl _Z30__device_stub__Vector_AdditionPKiS0_Pi # -- Begin function _Z30__device_stub__Vector_AdditionPKiS0_Pi
.p2align 4, 0x90
.type _Z30__device_stub__Vector_AdditionPKiS0_Pi,@function
_Z30__device_stub__Vector_AdditionPKiS0_Pi: # @_Z30__device_stub__Vector_AdditionPKiS0_Pi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15Vector_AdditionPKiS0_Pi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z30__device_stub__Vector_AdditionPKiS0_Pi, .Lfunc_end0-_Z30__device_stub__Vector_AdditionPKiS0_Pi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $24672, %rsp # imm = 0x6060
.cfi_def_cfa_offset 24688
.cfi_offset %rbx, -16
leaq 16(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.3: # %_ZL11HandleError10hipError_tPKci.exit
leaq 8(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
testl %eax, %eax
jne .LBB1_4
# %bb.5: # %_ZL11HandleError10hipError_tPKci.exit20
movq %rsp, %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
testl %eax, %eax
jne .LBB1_19
# %bb.6: # %_ZL11HandleError10hipError_tPKci.exit22.preheader
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_7: # %_ZL11HandleError10hipError_tPKci.exit22
# =>This Inner Loop Header: Depth=1
movl %eax, 16480(%rsp,%rcx,4)
movl %ecx, %edx
imull %ecx, %edx
movl %edx, 8288(%rsp,%rcx,4)
incq %rcx
decl %eax
cmpq $2048, %rcx # imm = 0x800
jne .LBB1_7
# %bb.8:
movq 16(%rsp), %rdi
leaq 16480(%rsp), %rsi
movl $8192, %edx # imm = 0x2000
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_9
# %bb.10: # %_ZL11HandleError10hipError_tPKci.exit24
movq 8(%rsp), %rdi
leaq 8288(%rsp), %rsi
movl $8192, %edx # imm = 0x2000
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_11
# %bb.12: # %_ZL11HandleError10hipError_tPKci.exit26
movabsq $4294967312, %rdi # imm = 0x100000010
leaq 112(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_14
# %bb.13:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15Vector_AdditionPKiS0_Pi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_14:
movq (%rsp), %rsi
leaq 96(%rsp), %rdi
movl $8192, %edx # imm = 0x2000
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_18
# %bb.15: # %_ZL11HandleError10hipError_tPKci.exit28.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_16: # %_ZL11HandleError10hipError_tPKci.exit28
# =>This Inner Loop Header: Depth=1
movl 16480(%rsp,%rbx,4), %esi
movl 8288(%rsp,%rbx,4), %edx
movl 96(%rsp,%rbx,4), %ecx
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $2048, %rbx # imm = 0x800
jne .LBB1_16
# %bb.17:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $24672, %rsp # imm = 0x6060
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 24688
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $50, %ecx
jmp .LBB1_2
.LBB1_4:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $51, %ecx
jmp .LBB1_2
.LBB1_19:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $52, %ecx
jmp .LBB1_2
.LBB1_9:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $62, %ecx
jmp .LBB1_2
.LBB1_11:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $63, %ecx
jmp .LBB1_2
.LBB1_18:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $69, %ecx
.LBB1_2:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15Vector_AdditionPKiS0_Pi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15Vector_AdditionPKiS0_Pi,@object # @_Z15Vector_AdditionPKiS0_Pi
.section .rodata,"a",@progbits
.globl _Z15Vector_AdditionPKiS0_Pi
.p2align 3, 0x0
_Z15Vector_AdditionPKiS0_Pi:
.quad _Z30__device_stub__Vector_AdditionPKiS0_Pi
.size _Z15Vector_AdditionPKiS0_Pi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/socal-ucr/NVIDIA-recon/master/suite/vector-addition/add.hip"
.size .L.str, 117
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d + %d = %d\n"
.size .L.str.1, 14
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%s in %s at line %d\n"
.size .L.str.2, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15Vector_AdditionPKiS0_Pi"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__Vector_AdditionPKiS0_Pi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15Vector_AdditionPKiS0_Pi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15Vector_AdditionPKiS0_Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.U32.AND P0, PT, R0, 0x7ff, PT ; /* 0x000007ff0000780c */
/* 0x000fda0003f04070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE.U32 R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0007 */
/*0090*/ IMAD.WIDE.U32 R4, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0007 */
/*00a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE.U32 R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0007 */
/*00d0*/ MOV R11, c[0x0][0x0] ; /* 0x00000000000b7a02 */
/* 0x000fca0000000f00 */
/*00e0*/ IMAD R0, R11, c[0x0][0xc], R0 ; /* 0x000003000b007a24 */
/* 0x000fca00078e0200 */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R0, 0x800, PT ; /* 0x000008000000780c */
/* 0x000fe40003f06070 */
/*0100*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*0110*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001ec000c101904 */
/*0120*/ @!P0 BRA 0x70 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15Vector_AdditionPKiS0_Pi
.globl _Z15Vector_AdditionPKiS0_Pi
.p2align 8
.type _Z15Vector_AdditionPKiS0_Pi,@function
_Z15Vector_AdditionPKiS0_Pi:
s_load_b32 s4, s[0:1], 0x24
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e32 0x800, v1
s_cbranch_execz .LBB0_3
s_load_b32 s9, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s9, s8
s_mov_b32 s8, 0
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_add_co_u32 v5, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v4, vcc_lo
v_cmp_lt_u32_e32 vcc_lo, 0x7ff, v1
global_load_b32 v0, v[5:6], off
global_load_b32 v5, v[7:8], off
v_add_co_u32 v3, s0, s2, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s0, s3, v4, s0
s_or_b32 s8, vcc_lo, s8
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v5, v0
global_store_b32 v[3:4], v0, off
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15Vector_AdditionPKiS0_Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15Vector_AdditionPKiS0_Pi, .Lfunc_end0-_Z15Vector_AdditionPKiS0_Pi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15Vector_AdditionPKiS0_Pi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15Vector_AdditionPKiS0_Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00141335_00000000-6_add.cudafe1.cpp"
.text
#APP
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s in %s at line %d\n"
#NO_APP
.text
.type _ZL11HandleError9cudaErrorPKci, @function
_ZL11HandleError9cudaErrorPKci:
.LFB2057:
.cfi_startproc
testl %edi, %edi
jne .L6
ret
.L6:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbx
movl %edx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rdx
movl %ebp, %r8d
movq %rbx, %rcx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _ZL11HandleError9cudaErrorPKci, .-_ZL11HandleError9cudaErrorPKci
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z15Vector_AdditionPKiS0_PiPKiS0_Pi
.type _Z41__device_stub__Z15Vector_AdditionPKiS0_PiPKiS0_Pi, @function
_Z41__device_stub__Z15Vector_AdditionPKiS0_PiPKiS0_Pi:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15Vector_AdditionPKiS0_Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z41__device_stub__Z15Vector_AdditionPKiS0_PiPKiS0_Pi, .-_Z41__device_stub__Z15Vector_AdditionPKiS0_PiPKiS0_Pi
.globl _Z15Vector_AdditionPKiS0_Pi
.type _Z15Vector_AdditionPKiS0_Pi, @function
_Z15Vector_AdditionPKiS0_Pi:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z15Vector_AdditionPKiS0_PiPKiS0_Pi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z15Vector_AdditionPKiS0_Pi, .-_Z15Vector_AdditionPKiS0_Pi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/socal-ucr/NVIDIA-recon/master/suite/vector-addition/add.cu"
.section .rodata.str1.1
.LC2:
.string "%d + %d = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
leaq -24576(%rsp), %r11
.cfi_def_cfa 11, 24600
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $72, %rsp
.cfi_def_cfa_offset 24672
movq %fs:40, %rax
movq %rax, 24632(%rsp)
xorl %eax, %eax
movl $16, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $128, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movq %rsp, %rdi
movl $8192, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $48, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 8(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $49, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 16(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $50, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
movl $0, %eax
.L18:
movl %eax, %edx
negl %edx
movl %edx, 48(%rsp,%rax,4)
movl %eax, %edx
imull %eax, %edx
movl %edx, 8240(%rsp,%rax,4)
addq $1, %rax
cmpq $2048, %rax
jne .L18
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $8192, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $60, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 8240(%rsp), %rsi
movl $1, %ecx
movl $8192, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $61, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
movl 44(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movq 24(%rsp), %rdi
movl 32(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L19:
leaq 16432(%rsp), %rdi
movl $2, %ecx
movl $8192, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl %eax, %edi
movl $67, %edx
leaq .LC1(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
movl $0, %ebx
leaq .LC2(%rip), %rbp
.L20:
movl 8240(%rsp,%rbx), %ecx
movl 48(%rsp,%rbx), %edx
movl 16432(%rsp,%rbx), %r8d
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $8192, %rbx
jne .L20
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24632(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $24648, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z41__device_stub__Z15Vector_AdditionPKiS0_PiPKiS0_Pi
jmp .L19
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z15Vector_AdditionPKiS0_Pi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z15Vector_AdditionPKiS0_Pi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "add.hip"
.globl _Z30__device_stub__Vector_AdditionPKiS0_Pi # -- Begin function _Z30__device_stub__Vector_AdditionPKiS0_Pi
.p2align 4, 0x90
.type _Z30__device_stub__Vector_AdditionPKiS0_Pi,@function
_Z30__device_stub__Vector_AdditionPKiS0_Pi: # @_Z30__device_stub__Vector_AdditionPKiS0_Pi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15Vector_AdditionPKiS0_Pi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z30__device_stub__Vector_AdditionPKiS0_Pi, .Lfunc_end0-_Z30__device_stub__Vector_AdditionPKiS0_Pi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $24672, %rsp # imm = 0x6060
.cfi_def_cfa_offset 24688
.cfi_offset %rbx, -16
leaq 16(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.3: # %_ZL11HandleError10hipError_tPKci.exit
leaq 8(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
testl %eax, %eax
jne .LBB1_4
# %bb.5: # %_ZL11HandleError10hipError_tPKci.exit20
movq %rsp, %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
testl %eax, %eax
jne .LBB1_19
# %bb.6: # %_ZL11HandleError10hipError_tPKci.exit22.preheader
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_7: # %_ZL11HandleError10hipError_tPKci.exit22
# =>This Inner Loop Header: Depth=1
movl %eax, 16480(%rsp,%rcx,4)
movl %ecx, %edx
imull %ecx, %edx
movl %edx, 8288(%rsp,%rcx,4)
incq %rcx
decl %eax
cmpq $2048, %rcx # imm = 0x800
jne .LBB1_7
# %bb.8:
movq 16(%rsp), %rdi
leaq 16480(%rsp), %rsi
movl $8192, %edx # imm = 0x2000
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_9
# %bb.10: # %_ZL11HandleError10hipError_tPKci.exit24
movq 8(%rsp), %rdi
leaq 8288(%rsp), %rsi
movl $8192, %edx # imm = 0x2000
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_11
# %bb.12: # %_ZL11HandleError10hipError_tPKci.exit26
movabsq $4294967312, %rdi # imm = 0x100000010
leaq 112(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_14
# %bb.13:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15Vector_AdditionPKiS0_Pi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_14:
movq (%rsp), %rsi
leaq 96(%rsp), %rdi
movl $8192, %edx # imm = 0x2000
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_18
# %bb.15: # %_ZL11HandleError10hipError_tPKci.exit28.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_16: # %_ZL11HandleError10hipError_tPKci.exit28
# =>This Inner Loop Header: Depth=1
movl 16480(%rsp,%rbx,4), %esi
movl 8288(%rsp,%rbx,4), %edx
movl 96(%rsp,%rbx,4), %ecx
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $2048, %rbx # imm = 0x800
jne .LBB1_16
# %bb.17:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $24672, %rsp # imm = 0x6060
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 24688
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $50, %ecx
jmp .LBB1_2
.LBB1_4:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $51, %ecx
jmp .LBB1_2
.LBB1_19:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $52, %ecx
jmp .LBB1_2
.LBB1_9:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $62, %ecx
jmp .LBB1_2
.LBB1_11:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $63, %ecx
jmp .LBB1_2
.LBB1_18:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $69, %ecx
.LBB1_2:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15Vector_AdditionPKiS0_Pi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15Vector_AdditionPKiS0_Pi,@object # @_Z15Vector_AdditionPKiS0_Pi
.section .rodata,"a",@progbits
.globl _Z15Vector_AdditionPKiS0_Pi
.p2align 3, 0x0
_Z15Vector_AdditionPKiS0_Pi:
.quad _Z30__device_stub__Vector_AdditionPKiS0_Pi
.size _Z15Vector_AdditionPKiS0_Pi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/socal-ucr/NVIDIA-recon/master/suite/vector-addition/add.hip"
.size .L.str, 117
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d + %d = %d\n"
.size .L.str.1, 14
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%s in %s at line %d\n"
.size .L.str.2, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15Vector_AdditionPKiS0_Pi"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__Vector_AdditionPKiS0_Pi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15Vector_AdditionPKiS0_Pi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <assert.h>
#include <cstdio>
#include <cstdlib>
#include <cmath>
#include <cstring>
#include <ctime>
#include <sys/time.h>
#include <cuda.h>
#include <cuda_runtime_api.h>
#include <float.h>
#include <cmath>
/*
* This macro checks for API errors in the CUDA calls.
*/
#define gpuErrchk(ans) { gpuAssert( (ans), __FILE__, __LINE__ ); }
inline void
gpuAssert( cudaError_t code, const char * file, int line, bool abort = true )
{
if ( cudaSuccess != code )
{
fprintf( stderr, "\nGPUassert: %s %s %d\n", cudaGetErrorString( code ), file, line );
if ( abort )
exit( code );
}
return;
} /* gpuAssert */
/* ========================================================================== */
/* Voronoi2D */
/* -------------------------------------------------------------------------- */
/*!
* @function Voronoi2D
*
* @abstract
*
* @discussion Calculates Voronoi cells
*
* @param inNbOfSites [input] The number of the sites (seeds).
* type: const size_t
*
* @param inWidth [input] The width of the Voronoi image.
* type: const size_t
*
* @param inHeight [input] The height of the Voronoi image.
* type: const size_t
*
* @param inX [input] The x coordinates of the points
* Dimensions : Nx , type: float
*
* @param inY [input] The y coordinates of the points
* Dimensions : Ny , type: float
*
* @param inV [input] The inV holds for applying a threshold/color
* to the cell region
* Dimensions : inNbOfSites, type: int
*
* @param ouVoronoi [output] The output data (pixels)
* Dimensions : The total number of threads in the grid
* ( theBlocksPerGridX * theBlocksPerGridY * theThreadsPerBlockX * theThreadsPerBlockY )
* type: float
*/
/* ========================================================================== */
__global__ void Voronoi2D(
const size_t inNbOfSites,
const size_t inWidth,
const size_t inHeight,
float * const inX,
float * const inY,
int * const inV,
int * const ouVoronoi )
{
float distX , distY;
float theTempDistance ,theDistance = FLT_MAX;
int theThreshold;
//loop through all points calculating distance
for ( int y = ( ( blockIdx.y * blockDim.y ) + threadIdx.y ); y < inHeight; y += blockDim.y * gridDim.y )
{
for ( int x = ( ( blockIdx.x * blockDim.x ) + threadIdx.x ); x < inWidth; x += blockDim.x * gridDim.x )
{
int theGlobalIdx = y * ( blockDim.x * gridDim.x ) + x;
//Calculate distances for all the points
for ( int i = 0; i < inNbOfSites; i++ )
{
distX = inX[ i ] - x;
distY = inY[ i ] - y;
theTempDistance = distX * distX + distY * distY;
//if this Point is closer , assign proper threshold
if ( theTempDistance < theDistance )
{
theDistance = theTempDistance;
theThreshold = inV[ i ];
}
}
//write result back to global memory
*( ouVoronoi + theGlobalIdx ) = theThreshold;
} /* x */
} /* y */
}
int main()
{
const size_t Width = 256 , Height = 256;
const size_t Nx = 128 , Ny = 128;
const size_t NbOfSites = 100; //should be <= Nx and Ny
const size_t ThreadsPerBlockX = 16 , ThreadsPerBlockY = 16 ,BlocksPerGridX = Width / 16 , BlocksPerGridY = Height / 16;
const size_t TotalNbOfPixels = ( Width * Height );
// Allocate host memory
float * X = (float*) malloc( Nx * sizeof (*X) );
assert( NULL != X );
float * Y = (float*) malloc( Ny * sizeof (*Y) );
assert( NULL != Y );
int * V = (int*) malloc( NbOfSites * sizeof (*V) );
assert( NULL != V );
int * VoronoiDiagram = (int*) malloc ( TotalNbOfPixels * sizeof(*VoronoiDiagram) );
assert( NULL != VoronoiDiagram );
float * devX , * devY;
int * devVoronoiDiagram , * devV;
// Allocate device memory
gpuErrchk( cudaMalloc( (void**) &devX, Nx * sizeof(*devX) ) );
gpuErrchk( cudaMalloc( (void**) &devY, Ny * sizeof(*devY) ) );
gpuErrchk( cudaMalloc( (void**) &devV, NbOfSites * sizeof(*devV) ) );
gpuErrchk( cudaMalloc( (void**) &devVoronoiDiagram, TotalNbOfPixels * sizeof(*devVoronoiDiagram) ) );
// Create random coordinates
srand((unsigned int)time(NULL));
for ( int i = 0; i < Nx; i++ ) X[ i ] = ( ( (float) rand() / (float) ( RAND_MAX ) ) * Width );
for ( int i = 0; i < Ny; i++ ) Y[ i ] = ( ( (float) rand() / (float) ( RAND_MAX ) ) * Height );
for ( int i = 0; i < NbOfSites; i++ ) V[ i ] = i;
// Define grid dimensions
dim3 BlocksDim ( BlocksPerGridX , BlocksPerGridY );
dim3 ThreadsPerBlock ( ThreadsPerBlockX , ThreadsPerBlockY );
gpuErrchk( cudaMemcpy( devV , V , NbOfSites * sizeof( *V ), cudaMemcpyHostToDevice ) );
gpuErrchk( cudaMemcpy( devX , X , Nx * sizeof( *X ), cudaMemcpyHostToDevice ) );
gpuErrchk( cudaMemcpy( devY , Y , Ny * sizeof( *Y ), cudaMemcpyHostToDevice ) );
cudaEvent_t CurrentEventPre,
CurrentEventPost;
float CurrentPostPreTimeMS;
gpuErrchk( cudaEventCreate( &CurrentEventPre ) );
gpuErrchk( cudaEventCreate( &CurrentEventPost ) );
gpuErrchk( cudaEventRecord( CurrentEventPre ) );
Voronoi2D<<< BlocksDim,ThreadsPerBlock >>>( NbOfSites,
Width,
Height,
devX,
devY,
devV,
devVoronoiDiagram );
gpuErrchk( cudaPeekAtLastError() );
gpuErrchk( cudaDeviceSynchronize() );
gpuErrchk( cudaEventRecord( CurrentEventPost ) );
gpuErrchk( cudaEventSynchronize( CurrentEventPost ) );
gpuErrchk( cudaEventElapsedTime( &CurrentPostPreTimeMS, CurrentEventPre, CurrentEventPost ) );
printf( "\nGPU time for calling Voronoi: %f ms\n", CurrentPostPreTimeMS );
gpuErrchk( cudaMemcpy( VoronoiDiagram,
devVoronoiDiagram ,
TotalNbOfPixels * sizeof(*devVoronoiDiagram), cudaMemcpyDeviceToHost ) );
{
FILE * theFile;
theFile = fopen( "Voronoi2D", "wb" );
assert( NULL != theFile );
assert( TotalNbOfPixels == fwrite( VoronoiDiagram , sizeof(*devVoronoiDiagram), TotalNbOfPixels , theFile ) );
fclose( theFile );
}
//free memory
gpuErrchk( cudaFree( devX ) );
gpuErrchk( cudaFree( devY ) );
gpuErrchk( cudaFree( devV ) );
gpuErrchk( cudaFree( devVoronoiDiagram ) );
free( X );
free( Y );
free( V );
free( VoronoiDiagram );
return 0;
} | code for sm_80
Function : _Z9Voronoi2DmmmPfS_PiS0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R12, SR_CTAID.Y ; /* 0x00000000000c7919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002200 */
/*0030*/ IMAD R12, R12, c[0x0][0x4], R3 ; /* 0x000001000c0c7a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R12, c[0x0][0x170], PT ; /* 0x00005c000c007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R0, RZ, 0x1f, R12 ; /* 0x0000001fff007819 */
/* 0x000fc8000001140c */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R0, c[0x0][0x174], PT, P0 ; /* 0x00005d0000007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ S2R R15, SR_CTAID.X ; /* 0x00000000000f7919 */
/* 0x000e220000002500 */
/*0090*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x160], PT ; /* 0x00005800ff007a0c */
/* 0x000fc60003f05070 */
/*00a0*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*00b0*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x164], PT, P0 ; /* 0x00005900ff007a0c */
/* 0x000fe20003f05300 */
/*00c0*/ IMAD R15, R15, c[0x0][0x0], R0 ; /* 0x000000000f0f7a24 */
/* 0x001fd800078e0200 */
/*00d0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00e0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*00f0*/ MOV R2, c[0x0][0x164] ; /* 0x0000590000027a02 */
/* 0x000fe20000000f00 */
/*0100*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff0e7624 */
/* 0x000fe200078e00ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R15, c[0x0][0x168], PT ; /* 0x00005a000f007a0c */
/* 0x000fe20003f06070 */
/*0120*/ IMAD.MOV.U32 R11, RZ, RZ, 0x7f7fffff ; /* 0x7f7fffffff0b7424 */
/* 0x000fe200078e00ff */
/*0130*/ IADD3 R0, P2, -R0, c[0x0][0x160], RZ ; /* 0x0000580000007a10 */
/* 0x000fe20007f5e1ff */
/*0140*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0150*/ LOP3.LUT R14, R14, 0x3, RZ, 0xc0, !PT ; /* 0x000000030e0e7812 */
/* 0x000fe200078ec0ff */
/*0160*/ ULDC UR5, c[0x0][0xc] ; /* 0x0000030000057ab9 */
/* 0x000fe20000000800 */
/*0170*/ ISETP.GE.U32.AND P1, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe20003f26070 */
/*0180*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fe2000f8e023f */
/*0190*/ IADD3.X R0, R2, -0x1, RZ, P2, !PT ; /* 0xffffffff02007810 */
/* 0x000fe200017fe4ff */
/*01a0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*01b0*/ SHF.R.S32.HI R3, RZ, 0x1f, R15 ; /* 0x0000001fff037819 */
/* 0x000fc4000001140f */
/*01c0*/ IADD3 R13, P2, R14, -c[0x0][0x160], RZ ; /* 0x800058000e0d7a10 */
/* 0x000fe40007f5e0ff */
/*01d0*/ ISETP.GE.U32.AND.EX P0, PT, R3, c[0x0][0x16c], PT, P0 ; /* 0x00005b0003007a0c */
/* 0x000fe40003f06100 */
/*01e0*/ ISETP.GE.U32.AND.EX P1, PT, R0, RZ, PT, P1 ; /* 0x000000ff0000720c */
/* 0x000fe40003f26110 */
/*01f0*/ IADD3.X R10, RZ, ~c[0x0][0x164], RZ, P2, !PT ; /* 0x80005900ff0a7a10 */
/* 0x000fd000017fe4ff */
/*0200*/ BSSY B0, 0x9f0 ; /* 0x000007e000007945 */
/* 0x000fe20003800000 */
/*0210*/ @P0 BRA 0x9e0 ; /* 0x000007c000000947 */
/* 0x00efea0003800000 */
/*0220*/ IMAD.MOV.U32 R9, RZ, RZ, R15 ; /* 0x000000ffff097224 */
/* 0x000fe400078e000f */
/*0230*/ ISETP.NE.U32.AND P2, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe20003f45070 */
/*0240*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fc600078e00ff */
/*0250*/ ISETP.NE.AND.EX P2, PT, RZ, RZ, PT, P2 ; /* 0x000000ffff00720c */
/* 0x000fe20003f45320 */
/*0260*/ @!P1 BRA 0x640 ; /* 0x000003d000009947 */
/* 0x00efd80003800000 */
/*0270*/ I2F R16, R12 ; /* 0x0000000c00107306 */
/* 0x0000620000201400 */
/*0280*/ HFMA2.MMA R8, -RZ, RZ, 0, 0 ; /* 0x00000000ff087435 */
/* 0x000fe200000001ff */
/*0290*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff067624 */
/* 0x000fe200078e00ff */
/*02a0*/ MOV R7, c[0x0][0x18c] ; /* 0x0000630000077a02 */
/* 0x000fe20000000f00 */
/*02b0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff027624 */
/* 0x000fe200078e00ff */
/*02c0*/ MOV R3, c[0x0][0x184] ; /* 0x0000610000037a02 */
/* 0x000fe20000000f00 */
/*02d0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff047624 */
/* 0x000fe200078e00ff */
/*02e0*/ MOV R5, c[0x0][0x17c] ; /* 0x00005f0000057a02 */
/* 0x000fe20000000f00 */
/*02f0*/ I2F R17, R9 ; /* 0x0000000900117306 */
/* 0x0000a20000201400 */
/*0300*/ IMAD.MOV.U32 R20, RZ, RZ, R13 ; /* 0x000000ffff147224 */
/* 0x000fe200078e000d */
/*0310*/ MOV R19, R10 ; /* 0x0000000a00137202 */
/* 0x000fcc0000000f00 */
/*0320*/ LDG.E R23, [R2.64+0x4] ; /* 0x0000040602177981 */
/* 0x000ee8000c1e1900 */
/*0330*/ LDG.E R21, [R4.64+0x4] ; /* 0x0000040604157981 */
/* 0x000f28000c1e1900 */
/*0340*/ LDG.E R25, [R2.64] ; /* 0x0000000602197981 */
/* 0x004ea8000c1e1900 */
/*0350*/ LDG.E R26, [R4.64] ; /* 0x00000006041a7981 */
/* 0x000ea2000c1e1900 */
/*0360*/ I2F R24, R12 ; /* 0x0000000c00187306 */
/* 0x000ef00000201400 */
/*0370*/ I2F R18, R9 ; /* 0x0000000900127306 */
/* 0x000f220000201400 */
/*0380*/ FADD R23, R23, -R24 ; /* 0x8000001817177221 */
/* 0x008fc40000000000 */
/*0390*/ FADD R21, R21, -R18 ; /* 0x8000001215157221 */
/* 0x010fe40000000000 */
/*03a0*/ FMUL R22, R23, R23 ; /* 0x0000001717167220 */
/* 0x000fe40000400000 */
/*03b0*/ FADD R25, -R16, R25 ; /* 0x0000001910197221 */
/* 0x006fe20000000100 */
/*03c0*/ LDG.E R23, [R2.64+0xc] ; /* 0x00000c0602177981 */
/* 0x000ea2000c1e1900 */
/*03d0*/ FFMA R22, R21, R21, R22 ; /* 0x0000001515167223 */
/* 0x000fc60000000016 */
/*03e0*/ LDG.E R21, [R2.64+0x8] ; /* 0x0000080602157981 */
/* 0x000ee2000c1e1900 */
/*03f0*/ FADD R26, -R17, R26 ; /* 0x0000001a111a7221 */
/* 0x000fe40000000100 */
/*0400*/ FMUL R25, R25, R25 ; /* 0x0000001919197220 */
/* 0x000fc80000400000 */
/*0410*/ FFMA R26, R26, R26, R25 ; /* 0x0000001a1a1a7223 */
/* 0x000fca0000000019 */
/*0420*/ FSETP.GEU.AND P3, PT, R26, R11, PT ; /* 0x0000000b1a00720b */
/* 0x000fda0003f6e000 */
/*0430*/ @!P3 LDG.E R0, [R6.64] ; /* 0x000000060600b981 */
/* 0x020322000c1e1900 */
/*0440*/ @!P3 IMAD.MOV.U32 R11, RZ, RZ, R26 ; /* 0x000000ffff0bb224 */
/* 0x000fca00078e001a */
/*0450*/ FSETP.GEU.AND P3, PT, R22, R11, PT ; /* 0x0000000b1600720b */
/* 0x000fe20003f6e000 */
/*0460*/ FADD R25, R21, -R24.reuse ; /* 0x8000001815197221 */
/* 0x108fe40000000000 */
/*0470*/ LDG.E R21, [R4.64+0x8] ; /* 0x0000080604157981 */
/* 0x000ef4000c1e1900 */
/*0480*/ @!P3 LDG.E R0, [R6.64+0x4] ; /* 0x000004060600b981 */
/* 0x010322000c1e1900 */
/*0490*/ FADD R23, R23, -R24 ; /* 0x8000001817177221 */
/* 0x004fc40000000000 */
/*04a0*/ FMUL R24, R25, R25 ; /* 0x0000001919187220 */
/* 0x000fe20000400000 */
/*04b0*/ @!P3 MOV R11, R22 ; /* 0x00000016000bb202 */
/* 0x000fe20000000f00 */
/*04c0*/ FADD R21, R21, -R18 ; /* 0x8000001215157221 */
/* 0x008fc80000000000 */
/*04d0*/ FFMA R24, R21, R21, R24 ; /* 0x0000001515187223 */
/* 0x000fe40000000018 */
/*04e0*/ LDG.E R21, [R4.64+0xc] ; /* 0x00000c0604157981 */
/* 0x0004e6000c1e1900 */
/*04f0*/ FSETP.GEU.AND P3, PT, R24, R11, PT ; /* 0x0000000b1800720b */
/* 0x000fda0003f6e000 */
/*0500*/ @!P3 LDG.E R0, [R6.64+0x8] ; /* 0x000008060600b981 */
/* 0x010322000c1e1900 */
/*0510*/ @!P3 IMAD.MOV.U32 R11, RZ, RZ, R24 ; /* 0x000000ffff0bb224 */
/* 0x000fe200078e0018 */
/*0520*/ IADD3 R20, P3, R20, 0x4, RZ ; /* 0x0000000414147810 */
/* 0x000fc80007f7e0ff */
/*0530*/ IADD3.X R19, RZ, R19, RZ, P3, !PT ; /* 0x00000013ff137210 */
/* 0x000fe40001ffe4ff */
/*0540*/ ISETP.NE.U32.AND P3, PT, R20, RZ, PT ; /* 0x000000ff1400720c */
/* 0x000fc80003f65070 */
/*0550*/ ISETP.NE.AND.EX P3, PT, R19, RZ, PT, P3 ; /* 0x000000ff1300720c */
/* 0x000fe40003f65330 */
/*0560*/ IADD3 R4, P5, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x004fe40007fbe0ff */
/*0570*/ IADD3 R2, P6, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fc60007fde0ff */
/*0580*/ IMAD.X R5, RZ, RZ, R5, P5 ; /* 0x000000ffff057224 */
/* 0x000fe200028e0605 */
/*0590*/ IADD3.X R3, RZ, R3, RZ, P6, !PT ; /* 0x00000003ff037210 */
/* 0x000fe400037fe4ff */
/*05a0*/ IADD3 R8, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fe20007ffe0ff */
/*05b0*/ FADD R21, R21, -R18 ; /* 0x8000001215157221 */
/* 0x008fe40000000000 */
/*05c0*/ FMUL R18, R23, R23 ; /* 0x0000001717127220 */
/* 0x000fc80000400000 */
/*05d0*/ FFMA R18, R21, R21, R18 ; /* 0x0000001515127223 */
/* 0x000fca0000000012 */
/*05e0*/ FSETP.GEU.AND P4, PT, R18, R11, PT ; /* 0x0000000b1200720b */
/* 0x000fda0003f8e000 */
/*05f0*/ @!P4 LDG.E R0, [R6.64+0xc] ; /* 0x00000c060600c981 */
/* 0x010362000c1e1900 */
/*0600*/ @!P4 MOV R11, R18 ; /* 0x00000012000bc202 */
/* 0x000fe40000000f00 */
/*0610*/ IADD3 R6, P5, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x002fca0007fbe0ff */
/*0620*/ IMAD.X R7, RZ, RZ, R7, P5 ; /* 0x000000ffff077224 */
/* 0x000fe200028e0607 */
/*0630*/ @P3 BRA 0x320 ; /* 0xfffffce000003947 */
/* 0x000fea000383ffff */
/*0640*/ @!P2 BRA 0x950 ; /* 0x000003000000a947 */
/* 0x000fea0003800000 */
/*0650*/ IMAD.MOV.U32 R19, RZ, RZ, 0x4 ; /* 0x00000004ff137424 */
/* 0x000fc800078e00ff */
/*0660*/ IMAD.WIDE R2, R8, R19, c[0x0][0x180] ; /* 0x0000600008027625 */
/* 0x000fc800078e0213 */
/*0670*/ IMAD.WIDE R4, R8, R19, c[0x0][0x178] ; /* 0x00005e0008047625 */
/* 0x000fe200078e0213 */
/*0680*/ LDG.E R6, [R2.64] ; /* 0x0000000602067981 */
/* 0x000ea8000c1e1900 */
/*0690*/ LDG.E R7, [R4.64] ; /* 0x0000000604077981 */
/* 0x000ee2000c1e1900 */
/*06a0*/ I2F R17, R12 ; /* 0x0000000c00117306 */
/* 0x000ea20000201400 */
/*06b0*/ ISETP.NE.U32.AND P2, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fe20003f45070 */
/*06c0*/ BSSY B1, 0x790 ; /* 0x000000c000017945 */
/* 0x000fe60003800000 */
/*06d0*/ ISETP.NE.AND.EX P2, PT, RZ, RZ, PT, P2 ; /* 0x000000ffff00720c */
/* 0x000fc60003f45320 */
/*06e0*/ I2F R16, R9 ; /* 0x0000000900107306 */
/* 0x000ee20000201400 */
/*06f0*/ FADD R6, R6, -R17 ; /* 0x8000001106067221 */
/* 0x004fe40000000000 */
/*0700*/ FADD R7, R7, -R16 ; /* 0x8000001007077221 */
/* 0x008fe40000000000 */
/*0710*/ FMUL R6, R6, R6 ; /* 0x0000000606067220 */
/* 0x000fc80000400000 */
/*0720*/ FFMA R18, R7, R7, R6 ; /* 0x0000000707127223 */
/* 0x000fe40000000006 */
/*0730*/ IMAD.WIDE R6, R8, R19, c[0x0][0x188] ; /* 0x0000620008067625 */
/* 0x000fc600078e0213 */
/*0740*/ FSETP.GEU.AND P3, PT, R18, R11, PT ; /* 0x0000000b1200720b */
/* 0x000fda0003f6e000 */
/*0750*/ @P3 BRA 0x780 ; /* 0x0000002000003947 */
/* 0x000fea0003800000 */
/*0760*/ LDG.E R0, [R6.64] ; /* 0x0000000606007981 */
/* 0x020362000c1e1900 */
/*0770*/ MOV R11, R18 ; /* 0x00000012000b7202 */
/* 0x000fc60000000f00 */
/*0780*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0790*/ BSSY B1, 0x950 ; /* 0x000001b000017945 */
/* 0x000fe20003800000 */
/*07a0*/ @!P2 BRA 0x940 ; /* 0x000001900000a947 */
/* 0x000fea0003800000 */
/*07b0*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040602087981 */
/* 0x000ea8000c1e1900 */
/*07c0*/ LDG.E R19, [R4.64+0x4] ; /* 0x0000040604137981 */
/* 0x000ee2000c1e1900 */
/*07d0*/ ISETP.NE.U32.AND P2, PT, R14, 0x2, PT ; /* 0x000000020e00780c */
/* 0x000fe20003f45070 */
/*07e0*/ BSSY B2, 0x890 ; /* 0x000000a000027945 */
/* 0x000fe60003800000 */
/*07f0*/ ISETP.NE.AND.EX P2, PT, RZ, RZ, PT, P2 ; /* 0x000000ffff00720c */
/* 0x000fe20003f45320 */
/*0800*/ FADD R8, R8, -R17 ; /* 0x8000001108087221 */
/* 0x004fc40000000000 */
/*0810*/ FADD R19, R19, -R16 ; /* 0x8000001013137221 */
/* 0x008fe40000000000 */
/*0820*/ FMUL R8, R8, R8 ; /* 0x0000000808087220 */
/* 0x000fc80000400000 */
/*0830*/ FFMA R8, R19, R19, R8 ; /* 0x0000001313087223 */
/* 0x000fca0000000008 */
/*0840*/ FSETP.GEU.AND P3, PT, R8, R11, PT ; /* 0x0000000b0800720b */
/* 0x000fda0003f6e000 */
/*0850*/ @P3 BRA 0x880 ; /* 0x0000002000003947 */
/* 0x000fea0003800000 */
/*0860*/ LDG.E R0, [R6.64+0x4] ; /* 0x0000040606007981 */
/* 0x020562000c1e1900 */
/*0870*/ IMAD.MOV.U32 R11, RZ, RZ, R8 ; /* 0x000000ffff0b7224 */
/* 0x000fc600078e0008 */
/*0880*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0890*/ @!P2 BRA 0x940 ; /* 0x000000a00000a947 */
/* 0x000fea0003800000 */
/*08a0*/ LDG.E R2, [R2.64+0x8] ; /* 0x0000080602027981 */
/* 0x000ee8000c1e1900 */
/*08b0*/ LDG.E R5, [R4.64+0x8] ; /* 0x0000080604057981 */
/* 0x000f22000c1e1900 */
/*08c0*/ FADD R17, R2, -R17 ; /* 0x8000001102117221 */
/* 0x008fe40000000000 */
/*08d0*/ FADD R16, R5, -R16 ; /* 0x8000001005107221 */
/* 0x010fe40000000000 */
/*08e0*/ FMUL R17, R17, R17 ; /* 0x0000001111117220 */
/* 0x000fc80000400000 */
/*08f0*/ FFMA R16, R16, R16, R17 ; /* 0x0000001010107223 */
/* 0x000fca0000000011 */
/*0900*/ FSETP.GEU.AND P2, PT, R16, R11, PT ; /* 0x0000000b1000720b */
/* 0x000fda0003f4e000 */
/*0910*/ @P2 BRA 0x940 ; /* 0x0000002000002947 */
/* 0x000fea0003800000 */
/*0920*/ LDG.E R0, [R6.64+0x8] ; /* 0x0000080606007981 */
/* 0x020762000c1e1900 */
/*0930*/ MOV R11, R16 ; /* 0x00000010000b7202 */
/* 0x000fc60000000f00 */
/*0940*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0950*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*0960*/ IMAD R2, R12, UR4, R9 ; /* 0x000000040c027c24 */
/* 0x000fe2000f8e0209 */
/*0970*/ IADD3 R9, R9, UR4, RZ ; /* 0x0000000409097c10 */
/* 0x001fc6000fffe0ff */
/*0980*/ IMAD.WIDE R2, R2, R3, c[0x0][0x190] ; /* 0x0000640002027625 */
/* 0x000fe200078e0203 */
/*0990*/ ISETP.GE.U32.AND P2, PT, R9, c[0x0][0x168], PT ; /* 0x00005a0009007a0c */
/* 0x000fe40003f46070 */
/*09a0*/ SHF.R.S32.HI R4, RZ, 0x1f, R9 ; /* 0x0000001fff047819 */
/* 0x000fe40000011409 */
/*09b0*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x0201e4000c101906 */
/*09c0*/ ISETP.GE.U32.AND.EX P2, PT, R4, c[0x0][0x16c], PT, P2 ; /* 0x00005b0004007a0c */
/* 0x000fda0003f46120 */
/*09d0*/ @!P2 BRA 0x230 ; /* 0xfffff8500000a947 */
/* 0x001fea000383ffff */
/*09e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*09f0*/ MOV R3, c[0x0][0x4] ; /* 0x0000010000037a02 */
/* 0x000fca0000000f00 */
/*0a00*/ IMAD R12, R3, c[0x0][0x10], R12 ; /* 0x00000400030c7a24 */
/* 0x000fca00078e020c */
/*0a10*/ ISETP.GE.U32.AND P2, PT, R12, c[0x0][0x170], PT ; /* 0x00005c000c007a0c */
/* 0x000fe40003f46070 */
/*0a20*/ SHF.R.S32.HI R2, RZ, 0x1f, R12 ; /* 0x0000001fff027819 */
/* 0x000fc8000001140c */
/*0a30*/ ISETP.GE.U32.AND.EX P2, PT, R2, c[0x0][0x174], PT, P2 ; /* 0x00005d0002007a0c */
/* 0x000fda0003f46120 */
/*0a40*/ @!P2 BRA 0x200 ; /* 0xfffff7b00000a947 */
/* 0x000fea000383ffff */
/*0a50*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a60*/ BRA 0xa60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <assert.h>
#include <cstdio>
#include <cstdlib>
#include <cmath>
#include <cstring>
#include <ctime>
#include <sys/time.h>
#include <cuda.h>
#include <cuda_runtime_api.h>
#include <float.h>
#include <cmath>
/*
* This macro checks for API errors in the CUDA calls.
*/
#define gpuErrchk(ans) { gpuAssert( (ans), __FILE__, __LINE__ ); }
inline void
gpuAssert( cudaError_t code, const char * file, int line, bool abort = true )
{
if ( cudaSuccess != code )
{
fprintf( stderr, "\nGPUassert: %s %s %d\n", cudaGetErrorString( code ), file, line );
if ( abort )
exit( code );
}
return;
} /* gpuAssert */
/* ========================================================================== */
/* Voronoi2D */
/* -------------------------------------------------------------------------- */
/*!
* @function Voronoi2D
*
* @abstract
*
* @discussion Calculates Voronoi cells
*
* @param inNbOfSites [input] The number of the sites (seeds).
* type: const size_t
*
* @param inWidth [input] The width of the Voronoi image.
* type: const size_t
*
* @param inHeight [input] The height of the Voronoi image.
* type: const size_t
*
* @param inX [input] The x coordinates of the points
* Dimensions : Nx , type: float
*
* @param inY [input] The y coordinates of the points
* Dimensions : Ny , type: float
*
* @param inV [input] The inV holds for applying a threshold/color
* to the cell region
* Dimensions : inNbOfSites, type: int
*
* @param ouVoronoi [output] The output data (pixels)
* Dimensions : The total number of threads in the grid
* ( theBlocksPerGridX * theBlocksPerGridY * theThreadsPerBlockX * theThreadsPerBlockY )
* type: float
*/
/* ========================================================================== */
__global__ void Voronoi2D(
const size_t inNbOfSites,
const size_t inWidth,
const size_t inHeight,
float * const inX,
float * const inY,
int * const inV,
int * const ouVoronoi )
{
float distX , distY;
float theTempDistance ,theDistance = FLT_MAX;
int theThreshold;
//loop through all points calculating distance
for ( int y = ( ( blockIdx.y * blockDim.y ) + threadIdx.y ); y < inHeight; y += blockDim.y * gridDim.y )
{
for ( int x = ( ( blockIdx.x * blockDim.x ) + threadIdx.x ); x < inWidth; x += blockDim.x * gridDim.x )
{
int theGlobalIdx = y * ( blockDim.x * gridDim.x ) + x;
//Calculate distances for all the points
for ( int i = 0; i < inNbOfSites; i++ )
{
distX = inX[ i ] - x;
distY = inY[ i ] - y;
theTempDistance = distX * distX + distY * distY;
//if this Point is closer , assign proper threshold
if ( theTempDistance < theDistance )
{
theDistance = theTempDistance;
theThreshold = inV[ i ];
}
}
//write result back to global memory
*( ouVoronoi + theGlobalIdx ) = theThreshold;
} /* x */
} /* y */
}
int main()
{
const size_t Width = 256 , Height = 256;
const size_t Nx = 128 , Ny = 128;
const size_t NbOfSites = 100; //should be <= Nx and Ny
const size_t ThreadsPerBlockX = 16 , ThreadsPerBlockY = 16 ,BlocksPerGridX = Width / 16 , BlocksPerGridY = Height / 16;
const size_t TotalNbOfPixels = ( Width * Height );
// Allocate host memory
float * X = (float*) malloc( Nx * sizeof (*X) );
assert( NULL != X );
float * Y = (float*) malloc( Ny * sizeof (*Y) );
assert( NULL != Y );
int * V = (int*) malloc( NbOfSites * sizeof (*V) );
assert( NULL != V );
int * VoronoiDiagram = (int*) malloc ( TotalNbOfPixels * sizeof(*VoronoiDiagram) );
assert( NULL != VoronoiDiagram );
float * devX , * devY;
int * devVoronoiDiagram , * devV;
// Allocate device memory
gpuErrchk( cudaMalloc( (void**) &devX, Nx * sizeof(*devX) ) );
gpuErrchk( cudaMalloc( (void**) &devY, Ny * sizeof(*devY) ) );
gpuErrchk( cudaMalloc( (void**) &devV, NbOfSites * sizeof(*devV) ) );
gpuErrchk( cudaMalloc( (void**) &devVoronoiDiagram, TotalNbOfPixels * sizeof(*devVoronoiDiagram) ) );
// Create random coordinates
srand((unsigned int)time(NULL));
for ( int i = 0; i < Nx; i++ ) X[ i ] = ( ( (float) rand() / (float) ( RAND_MAX ) ) * Width );
for ( int i = 0; i < Ny; i++ ) Y[ i ] = ( ( (float) rand() / (float) ( RAND_MAX ) ) * Height );
for ( int i = 0; i < NbOfSites; i++ ) V[ i ] = i;
// Define grid dimensions
dim3 BlocksDim ( BlocksPerGridX , BlocksPerGridY );
dim3 ThreadsPerBlock ( ThreadsPerBlockX , ThreadsPerBlockY );
gpuErrchk( cudaMemcpy( devV , V , NbOfSites * sizeof( *V ), cudaMemcpyHostToDevice ) );
gpuErrchk( cudaMemcpy( devX , X , Nx * sizeof( *X ), cudaMemcpyHostToDevice ) );
gpuErrchk( cudaMemcpy( devY , Y , Ny * sizeof( *Y ), cudaMemcpyHostToDevice ) );
cudaEvent_t CurrentEventPre,
CurrentEventPost;
float CurrentPostPreTimeMS;
gpuErrchk( cudaEventCreate( &CurrentEventPre ) );
gpuErrchk( cudaEventCreate( &CurrentEventPost ) );
gpuErrchk( cudaEventRecord( CurrentEventPre ) );
Voronoi2D<<< BlocksDim,ThreadsPerBlock >>>( NbOfSites,
Width,
Height,
devX,
devY,
devV,
devVoronoiDiagram );
gpuErrchk( cudaPeekAtLastError() );
gpuErrchk( cudaDeviceSynchronize() );
gpuErrchk( cudaEventRecord( CurrentEventPost ) );
gpuErrchk( cudaEventSynchronize( CurrentEventPost ) );
gpuErrchk( cudaEventElapsedTime( &CurrentPostPreTimeMS, CurrentEventPre, CurrentEventPost ) );
printf( "\nGPU time for calling Voronoi: %f ms\n", CurrentPostPreTimeMS );
gpuErrchk( cudaMemcpy( VoronoiDiagram,
devVoronoiDiagram ,
TotalNbOfPixels * sizeof(*devVoronoiDiagram), cudaMemcpyDeviceToHost ) );
{
FILE * theFile;
theFile = fopen( "Voronoi2D", "wb" );
assert( NULL != theFile );
assert( TotalNbOfPixels == fwrite( VoronoiDiagram , sizeof(*devVoronoiDiagram), TotalNbOfPixels , theFile ) );
fclose( theFile );
}
//free memory
gpuErrchk( cudaFree( devX ) );
gpuErrchk( cudaFree( devY ) );
gpuErrchk( cudaFree( devV ) );
gpuErrchk( cudaFree( devVoronoiDiagram ) );
free( X );
free( Y );
free( V );
free( VoronoiDiagram );
return 0;
} | .file "tmpxft_00040d98_00000000-6_Voronoi2D.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
.string "\nGPUassert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L10
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.text
.globl _Z38__device_stub__Z9Voronoi2DmmmPfS_PiS0_mmmPfS_PiS0_
.type _Z38__device_stub__Z9Voronoi2DmmmPfS_PiS0_mmmPfS_PiS0_, @function
_Z38__device_stub__Z9Voronoi2DmmmPfS_PiS0_mmmPfS_PiS0_:
.LFB2083:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z9Voronoi2DmmmPfS_PiS0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z38__device_stub__Z9Voronoi2DmmmPfS_PiS0_mmmPfS_PiS0_, .-_Z38__device_stub__Z9Voronoi2DmmmPfS_PiS0_mmmPfS_PiS0_
.globl _Z9Voronoi2DmmmPfS_PiS0_
.type _Z9Voronoi2DmmmPfS_PiS0_, @function
_Z9Voronoi2DmmmPfS_PiS0_:
.LFB2084:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z38__device_stub__Z9Voronoi2DmmmPfS_PiS0_mmmPfS_PiS0_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z9Voronoi2DmmmPfS_PiS0_, .-_Z9Voronoi2DmmmPfS_PiS0_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/ggeo/Cuda/master/Voronoi/Voronoi2D.cu"
.align 8
.LC4:
.string "\nGPU time for calling Voronoi: %f ms\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "wb"
.LC6:
.string "Voronoi2D"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $512, %edi
call malloc@PLT
movq %rax, %r13
movl $512, %edi
call malloc@PLT
movq %rax, %r14
movl $400, %edi
call malloc@PLT
movq %rax, %rbp
movl $262144, %edi
call malloc@PLT
movq %rax, %r15
leaq 16(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $142, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 24(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $143, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 40(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $144, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 32(%rsp), %rdi
movl $262144, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $145, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movq %r13, %rbx
leaq 512(%r13), %r12
.L20:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC2(%rip), %xmm0
mulss .LC3(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %r12, %rbx
jne .L20
movq %r14, %rbx
leaq 512(%r14), %r12
.L21:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC2(%rip), %xmm0
mulss .LC3(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbx, %r12
jne .L21
movl $0, %eax
.L22:
movl %eax, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $100, %rax
jne .L22
movl $16, 64(%rsp)
movl $16, 68(%rsp)
movl $1, 72(%rsp)
movl $16, 76(%rsp)
movl $16, 80(%rsp)
movl $1, 84(%rsp)
movl $1, %ecx
movl $400, %edx
movq %rbp, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $158, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movl $512, %edx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $159, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movl $512, %edx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $160, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %edi
movl $1, %ecx
movl $166, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %edi
movl $1, %ecx
movl $167, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %edi
movl $1, %ecx
movl $169, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl 84(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movq 64(%rsp), %rdi
movl 72(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L23:
call cudaPeekAtLastError@PLT
movl %eax, %edi
movl $1, %ecx
movl $180, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $1, %ecx
movl $181, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %edi
movl $1, %ecx
movl $183, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
movl %eax, %edi
movl $1, %ecx
movl $184, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 12(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl %eax, %edi
movl $1, %ecx
movl $185, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $262144, %edx
movq 32(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $188, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq .LC5(%rip), %rsi
leaq .LC6(%rip), %rdi
call fopen@PLT
movq %rax, %rdi
call fclose@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $201, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 24(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $202, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 40(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $203, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 32(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $204, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq %r13, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
movq 56(%rsp), %r9
movq 40(%rsp), %r8
movq 32(%rsp), %rcx
movl $256, %edx
movl $256, %esi
movl $100, %edi
call _Z38__device_stub__Z9Voronoi2DmmmPfS_PiS0_mmmPfS_PiS0_
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L23
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z9Voronoi2DmmmPfS_PiS0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z9Voronoi2DmmmPfS_PiS0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 805306368
.align 4
.LC3:
.long 1132462080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <assert.h>
#include <cstdio>
#include <cstdlib>
#include <cmath>
#include <cstring>
#include <ctime>
#include <sys/time.h>
#include <cuda.h>
#include <cuda_runtime_api.h>
#include <float.h>
#include <cmath>
/*
* This macro checks for API errors in the CUDA calls.
*/
#define gpuErrchk(ans) { gpuAssert( (ans), __FILE__, __LINE__ ); }
inline void
gpuAssert( cudaError_t code, const char * file, int line, bool abort = true )
{
if ( cudaSuccess != code )
{
fprintf( stderr, "\nGPUassert: %s %s %d\n", cudaGetErrorString( code ), file, line );
if ( abort )
exit( code );
}
return;
} /* gpuAssert */
/* ========================================================================== */
/* Voronoi2D */
/* -------------------------------------------------------------------------- */
/*!
* @function Voronoi2D
*
* @abstract
*
* @discussion Calculates Voronoi cells
*
* @param inNbOfSites [input] The number of the sites (seeds).
* type: const size_t
*
* @param inWidth [input] The width of the Voronoi image.
* type: const size_t
*
* @param inHeight [input] The height of the Voronoi image.
* type: const size_t
*
* @param inX [input] The x coordinates of the points
* Dimensions : Nx , type: float
*
* @param inY [input] The y coordinates of the points
* Dimensions : Ny , type: float
*
* @param inV [input] The inV holds for applying a threshold/color
* to the cell region
* Dimensions : inNbOfSites, type: int
*
* @param ouVoronoi [output] The output data (pixels)
* Dimensions : The total number of threads in the grid
* ( theBlocksPerGridX * theBlocksPerGridY * theThreadsPerBlockX * theThreadsPerBlockY )
* type: float
*/
/* ========================================================================== */
__global__ void Voronoi2D(
const size_t inNbOfSites,
const size_t inWidth,
const size_t inHeight,
float * const inX,
float * const inY,
int * const inV,
int * const ouVoronoi )
{
float distX , distY;
float theTempDistance ,theDistance = FLT_MAX;
int theThreshold;
//loop through all points calculating distance
for ( int y = ( ( blockIdx.y * blockDim.y ) + threadIdx.y ); y < inHeight; y += blockDim.y * gridDim.y )
{
for ( int x = ( ( blockIdx.x * blockDim.x ) + threadIdx.x ); x < inWidth; x += blockDim.x * gridDim.x )
{
int theGlobalIdx = y * ( blockDim.x * gridDim.x ) + x;
//Calculate distances for all the points
for ( int i = 0; i < inNbOfSites; i++ )
{
distX = inX[ i ] - x;
distY = inY[ i ] - y;
theTempDistance = distX * distX + distY * distY;
//if this Point is closer , assign proper threshold
if ( theTempDistance < theDistance )
{
theDistance = theTempDistance;
theThreshold = inV[ i ];
}
}
//write result back to global memory
*( ouVoronoi + theGlobalIdx ) = theThreshold;
} /* x */
} /* y */
}
int main()
{
const size_t Width = 256 , Height = 256;
const size_t Nx = 128 , Ny = 128;
const size_t NbOfSites = 100; //should be <= Nx and Ny
const size_t ThreadsPerBlockX = 16 , ThreadsPerBlockY = 16 ,BlocksPerGridX = Width / 16 , BlocksPerGridY = Height / 16;
const size_t TotalNbOfPixels = ( Width * Height );
// Allocate host memory
float * X = (float*) malloc( Nx * sizeof (*X) );
assert( NULL != X );
float * Y = (float*) malloc( Ny * sizeof (*Y) );
assert( NULL != Y );
int * V = (int*) malloc( NbOfSites * sizeof (*V) );
assert( NULL != V );
int * VoronoiDiagram = (int*) malloc ( TotalNbOfPixels * sizeof(*VoronoiDiagram) );
assert( NULL != VoronoiDiagram );
float * devX , * devY;
int * devVoronoiDiagram , * devV;
// Allocate device memory
gpuErrchk( cudaMalloc( (void**) &devX, Nx * sizeof(*devX) ) );
gpuErrchk( cudaMalloc( (void**) &devY, Ny * sizeof(*devY) ) );
gpuErrchk( cudaMalloc( (void**) &devV, NbOfSites * sizeof(*devV) ) );
gpuErrchk( cudaMalloc( (void**) &devVoronoiDiagram, TotalNbOfPixels * sizeof(*devVoronoiDiagram) ) );
// Create random coordinates
srand((unsigned int)time(NULL));
for ( int i = 0; i < Nx; i++ ) X[ i ] = ( ( (float) rand() / (float) ( RAND_MAX ) ) * Width );
for ( int i = 0; i < Ny; i++ ) Y[ i ] = ( ( (float) rand() / (float) ( RAND_MAX ) ) * Height );
for ( int i = 0; i < NbOfSites; i++ ) V[ i ] = i;
// Define grid dimensions
dim3 BlocksDim ( BlocksPerGridX , BlocksPerGridY );
dim3 ThreadsPerBlock ( ThreadsPerBlockX , ThreadsPerBlockY );
gpuErrchk( cudaMemcpy( devV , V , NbOfSites * sizeof( *V ), cudaMemcpyHostToDevice ) );
gpuErrchk( cudaMemcpy( devX , X , Nx * sizeof( *X ), cudaMemcpyHostToDevice ) );
gpuErrchk( cudaMemcpy( devY , Y , Ny * sizeof( *Y ), cudaMemcpyHostToDevice ) );
cudaEvent_t CurrentEventPre,
CurrentEventPost;
float CurrentPostPreTimeMS;
gpuErrchk( cudaEventCreate( &CurrentEventPre ) );
gpuErrchk( cudaEventCreate( &CurrentEventPost ) );
gpuErrchk( cudaEventRecord( CurrentEventPre ) );
Voronoi2D<<< BlocksDim,ThreadsPerBlock >>>( NbOfSites,
Width,
Height,
devX,
devY,
devV,
devVoronoiDiagram );
gpuErrchk( cudaPeekAtLastError() );
gpuErrchk( cudaDeviceSynchronize() );
gpuErrchk( cudaEventRecord( CurrentEventPost ) );
gpuErrchk( cudaEventSynchronize( CurrentEventPost ) );
gpuErrchk( cudaEventElapsedTime( &CurrentPostPreTimeMS, CurrentEventPre, CurrentEventPost ) );
printf( "\nGPU time for calling Voronoi: %f ms\n", CurrentPostPreTimeMS );
gpuErrchk( cudaMemcpy( VoronoiDiagram,
devVoronoiDiagram ,
TotalNbOfPixels * sizeof(*devVoronoiDiagram), cudaMemcpyDeviceToHost ) );
{
FILE * theFile;
theFile = fopen( "Voronoi2D", "wb" );
assert( NULL != theFile );
assert( TotalNbOfPixels == fwrite( VoronoiDiagram , sizeof(*devVoronoiDiagram), TotalNbOfPixels , theFile ) );
fclose( theFile );
}
//free memory
gpuErrchk( cudaFree( devX ) );
gpuErrchk( cudaFree( devY ) );
gpuErrchk( cudaFree( devV ) );
gpuErrchk( cudaFree( devVoronoiDiagram ) );
free( X );
free( Y );
free( V );
free( VoronoiDiagram );
return 0;
} | #include <assert.h>
#include <cstdio>
#include <cstdlib>
#include <cmath>
#include <cstring>
#include <ctime>
#include <sys/time.h>
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <float.h>
#include <cmath>
/*
* This macro checks for API errors in the CUDA calls.
*/
#define gpuErrchk(ans) { gpuAssert( (ans), __FILE__, __LINE__ ); }
inline void
gpuAssert( hipError_t code, const char * file, int line, bool abort = true )
{
if ( hipSuccess != code )
{
fprintf( stderr, "\nGPUassert: %s %s %d\n", hipGetErrorString( code ), file, line );
if ( abort )
exit( code );
}
return;
} /* gpuAssert */
/* ========================================================================== */
/* Voronoi2D */
/* -------------------------------------------------------------------------- */
/*!
* @function Voronoi2D
*
* @abstract
*
* @discussion Calculates Voronoi cells
*
* @param inNbOfSites [input] The number of the sites (seeds).
* type: const size_t
*
* @param inWidth [input] The width of the Voronoi image.
* type: const size_t
*
* @param inHeight [input] The height of the Voronoi image.
* type: const size_t
*
* @param inX [input] The x coordinates of the points
* Dimensions : Nx , type: float
*
* @param inY [input] The y coordinates of the points
* Dimensions : Ny , type: float
*
* @param inV [input] The inV holds for applying a threshold/color
* to the cell region
* Dimensions : inNbOfSites, type: int
*
* @param ouVoronoi [output] The output data (pixels)
* Dimensions : The total number of threads in the grid
* ( theBlocksPerGridX * theBlocksPerGridY * theThreadsPerBlockX * theThreadsPerBlockY )
* type: float
*/
/* ========================================================================== */
__global__ void Voronoi2D(
const size_t inNbOfSites,
const size_t inWidth,
const size_t inHeight,
float * const inX,
float * const inY,
int * const inV,
int * const ouVoronoi )
{
float distX , distY;
float theTempDistance ,theDistance = FLT_MAX;
int theThreshold;
//loop through all points calculating distance
for ( int y = ( ( blockIdx.y * blockDim.y ) + threadIdx.y ); y < inHeight; y += blockDim.y * gridDim.y )
{
for ( int x = ( ( blockIdx.x * blockDim.x ) + threadIdx.x ); x < inWidth; x += blockDim.x * gridDim.x )
{
int theGlobalIdx = y * ( blockDim.x * gridDim.x ) + x;
//Calculate distances for all the points
for ( int i = 0; i < inNbOfSites; i++ )
{
distX = inX[ i ] - x;
distY = inY[ i ] - y;
theTempDistance = distX * distX + distY * distY;
//if this Point is closer , assign proper threshold
if ( theTempDistance < theDistance )
{
theDistance = theTempDistance;
theThreshold = inV[ i ];
}
}
//write result back to global memory
*( ouVoronoi + theGlobalIdx ) = theThreshold;
} /* x */
} /* y */
}
int main()
{
const size_t Width = 256 , Height = 256;
const size_t Nx = 128 , Ny = 128;
const size_t NbOfSites = 100; //should be <= Nx and Ny
const size_t ThreadsPerBlockX = 16 , ThreadsPerBlockY = 16 ,BlocksPerGridX = Width / 16 , BlocksPerGridY = Height / 16;
const size_t TotalNbOfPixels = ( Width * Height );
// Allocate host memory
float * X = (float*) malloc( Nx * sizeof (*X) );
assert( NULL != X );
float * Y = (float*) malloc( Ny * sizeof (*Y) );
assert( NULL != Y );
int * V = (int*) malloc( NbOfSites * sizeof (*V) );
assert( NULL != V );
int * VoronoiDiagram = (int*) malloc ( TotalNbOfPixels * sizeof(*VoronoiDiagram) );
assert( NULL != VoronoiDiagram );
float * devX , * devY;
int * devVoronoiDiagram , * devV;
// Allocate device memory
gpuErrchk( hipMalloc( (void**) &devX, Nx * sizeof(*devX) ) );
gpuErrchk( hipMalloc( (void**) &devY, Ny * sizeof(*devY) ) );
gpuErrchk( hipMalloc( (void**) &devV, NbOfSites * sizeof(*devV) ) );
gpuErrchk( hipMalloc( (void**) &devVoronoiDiagram, TotalNbOfPixels * sizeof(*devVoronoiDiagram) ) );
// Create random coordinates
srand((unsigned int)time(NULL));
for ( int i = 0; i < Nx; i++ ) X[ i ] = ( ( (float) rand() / (float) ( RAND_MAX ) ) * Width );
for ( int i = 0; i < Ny; i++ ) Y[ i ] = ( ( (float) rand() / (float) ( RAND_MAX ) ) * Height );
for ( int i = 0; i < NbOfSites; i++ ) V[ i ] = i;
// Define grid dimensions
dim3 BlocksDim ( BlocksPerGridX , BlocksPerGridY );
dim3 ThreadsPerBlock ( ThreadsPerBlockX , ThreadsPerBlockY );
gpuErrchk( hipMemcpy( devV , V , NbOfSites * sizeof( *V ), hipMemcpyHostToDevice ) );
gpuErrchk( hipMemcpy( devX , X , Nx * sizeof( *X ), hipMemcpyHostToDevice ) );
gpuErrchk( hipMemcpy( devY , Y , Ny * sizeof( *Y ), hipMemcpyHostToDevice ) );
hipEvent_t CurrentEventPre,
CurrentEventPost;
float CurrentPostPreTimeMS;
gpuErrchk( hipEventCreate( &CurrentEventPre ) );
gpuErrchk( hipEventCreate( &CurrentEventPost ) );
gpuErrchk( hipEventRecord( CurrentEventPre ) );
Voronoi2D<<< BlocksDim,ThreadsPerBlock >>>( NbOfSites,
Width,
Height,
devX,
devY,
devV,
devVoronoiDiagram );
gpuErrchk( hipPeekAtLastError() );
gpuErrchk( hipDeviceSynchronize() );
gpuErrchk( hipEventRecord( CurrentEventPost ) );
gpuErrchk( hipEventSynchronize( CurrentEventPost ) );
gpuErrchk( hipEventElapsedTime( &CurrentPostPreTimeMS, CurrentEventPre, CurrentEventPost ) );
printf( "\nGPU time for calling Voronoi: %f ms\n", CurrentPostPreTimeMS );
gpuErrchk( hipMemcpy( VoronoiDiagram,
devVoronoiDiagram ,
TotalNbOfPixels * sizeof(*devVoronoiDiagram), hipMemcpyDeviceToHost ) );
{
FILE * theFile;
theFile = fopen( "Voronoi2D", "wb" );
assert( NULL != theFile );
assert( TotalNbOfPixels == fwrite( VoronoiDiagram , sizeof(*devVoronoiDiagram), TotalNbOfPixels , theFile ) );
fclose( theFile );
}
//free memory
gpuErrchk( hipFree( devX ) );
gpuErrchk( hipFree( devY ) );
gpuErrchk( hipFree( devV ) );
gpuErrchk( hipFree( devVoronoiDiagram ) );
free( X );
free( Y );
free( V );
free( VoronoiDiagram );
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <assert.h>
#include <cstdio>
#include <cstdlib>
#include <cmath>
#include <cstring>
#include <ctime>
#include <sys/time.h>
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <float.h>
#include <cmath>
/*
* This macro checks for API errors in the CUDA calls.
*/
#define gpuErrchk(ans) { gpuAssert( (ans), __FILE__, __LINE__ ); }
inline void
gpuAssert( hipError_t code, const char * file, int line, bool abort = true )
{
if ( hipSuccess != code )
{
fprintf( stderr, "\nGPUassert: %s %s %d\n", hipGetErrorString( code ), file, line );
if ( abort )
exit( code );
}
return;
} /* gpuAssert */
/* ========================================================================== */
/* Voronoi2D */
/* -------------------------------------------------------------------------- */
/*!
* @function Voronoi2D
*
* @abstract
*
* @discussion Calculates Voronoi cells
*
* @param inNbOfSites [input] The number of the sites (seeds).
* type: const size_t
*
* @param inWidth [input] The width of the Voronoi image.
* type: const size_t
*
* @param inHeight [input] The height of the Voronoi image.
* type: const size_t
*
* @param inX [input] The x coordinates of the points
* Dimensions : Nx , type: float
*
* @param inY [input] The y coordinates of the points
* Dimensions : Ny , type: float
*
* @param inV [input] The inV holds for applying a threshold/color
* to the cell region
* Dimensions : inNbOfSites, type: int
*
* @param ouVoronoi [output] The output data (pixels)
* Dimensions : The total number of threads in the grid
* ( theBlocksPerGridX * theBlocksPerGridY * theThreadsPerBlockX * theThreadsPerBlockY )
* type: float
*/
/* ========================================================================== */
__global__ void Voronoi2D(
const size_t inNbOfSites,
const size_t inWidth,
const size_t inHeight,
float * const inX,
float * const inY,
int * const inV,
int * const ouVoronoi )
{
float distX , distY;
float theTempDistance ,theDistance = FLT_MAX;
int theThreshold;
//loop through all points calculating distance
for ( int y = ( ( blockIdx.y * blockDim.y ) + threadIdx.y ); y < inHeight; y += blockDim.y * gridDim.y )
{
for ( int x = ( ( blockIdx.x * blockDim.x ) + threadIdx.x ); x < inWidth; x += blockDim.x * gridDim.x )
{
int theGlobalIdx = y * ( blockDim.x * gridDim.x ) + x;
//Calculate distances for all the points
for ( int i = 0; i < inNbOfSites; i++ )
{
distX = inX[ i ] - x;
distY = inY[ i ] - y;
theTempDistance = distX * distX + distY * distY;
//if this Point is closer , assign proper threshold
if ( theTempDistance < theDistance )
{
theDistance = theTempDistance;
theThreshold = inV[ i ];
}
}
//write result back to global memory
*( ouVoronoi + theGlobalIdx ) = theThreshold;
} /* x */
} /* y */
}
int main()
{
const size_t Width = 256 , Height = 256;
const size_t Nx = 128 , Ny = 128;
const size_t NbOfSites = 100; //should be <= Nx and Ny
const size_t ThreadsPerBlockX = 16 , ThreadsPerBlockY = 16 ,BlocksPerGridX = Width / 16 , BlocksPerGridY = Height / 16;
const size_t TotalNbOfPixels = ( Width * Height );
// Allocate host memory
float * X = (float*) malloc( Nx * sizeof (*X) );
assert( NULL != X );
float * Y = (float*) malloc( Ny * sizeof (*Y) );
assert( NULL != Y );
int * V = (int*) malloc( NbOfSites * sizeof (*V) );
assert( NULL != V );
int * VoronoiDiagram = (int*) malloc ( TotalNbOfPixels * sizeof(*VoronoiDiagram) );
assert( NULL != VoronoiDiagram );
float * devX , * devY;
int * devVoronoiDiagram , * devV;
// Allocate device memory
gpuErrchk( hipMalloc( (void**) &devX, Nx * sizeof(*devX) ) );
gpuErrchk( hipMalloc( (void**) &devY, Ny * sizeof(*devY) ) );
gpuErrchk( hipMalloc( (void**) &devV, NbOfSites * sizeof(*devV) ) );
gpuErrchk( hipMalloc( (void**) &devVoronoiDiagram, TotalNbOfPixels * sizeof(*devVoronoiDiagram) ) );
// Create random coordinates
srand((unsigned int)time(NULL));
for ( int i = 0; i < Nx; i++ ) X[ i ] = ( ( (float) rand() / (float) ( RAND_MAX ) ) * Width );
for ( int i = 0; i < Ny; i++ ) Y[ i ] = ( ( (float) rand() / (float) ( RAND_MAX ) ) * Height );
for ( int i = 0; i < NbOfSites; i++ ) V[ i ] = i;
// Define grid dimensions
dim3 BlocksDim ( BlocksPerGridX , BlocksPerGridY );
dim3 ThreadsPerBlock ( ThreadsPerBlockX , ThreadsPerBlockY );
gpuErrchk( hipMemcpy( devV , V , NbOfSites * sizeof( *V ), hipMemcpyHostToDevice ) );
gpuErrchk( hipMemcpy( devX , X , Nx * sizeof( *X ), hipMemcpyHostToDevice ) );
gpuErrchk( hipMemcpy( devY , Y , Ny * sizeof( *Y ), hipMemcpyHostToDevice ) );
hipEvent_t CurrentEventPre,
CurrentEventPost;
float CurrentPostPreTimeMS;
gpuErrchk( hipEventCreate( &CurrentEventPre ) );
gpuErrchk( hipEventCreate( &CurrentEventPost ) );
gpuErrchk( hipEventRecord( CurrentEventPre ) );
Voronoi2D<<< BlocksDim,ThreadsPerBlock >>>( NbOfSites,
Width,
Height,
devX,
devY,
devV,
devVoronoiDiagram );
gpuErrchk( hipPeekAtLastError() );
gpuErrchk( hipDeviceSynchronize() );
gpuErrchk( hipEventRecord( CurrentEventPost ) );
gpuErrchk( hipEventSynchronize( CurrentEventPost ) );
gpuErrchk( hipEventElapsedTime( &CurrentPostPreTimeMS, CurrentEventPre, CurrentEventPost ) );
printf( "\nGPU time for calling Voronoi: %f ms\n", CurrentPostPreTimeMS );
gpuErrchk( hipMemcpy( VoronoiDiagram,
devVoronoiDiagram ,
TotalNbOfPixels * sizeof(*devVoronoiDiagram), hipMemcpyDeviceToHost ) );
{
FILE * theFile;
theFile = fopen( "Voronoi2D", "wb" );
assert( NULL != theFile );
assert( TotalNbOfPixels == fwrite( VoronoiDiagram , sizeof(*devVoronoiDiagram), TotalNbOfPixels , theFile ) );
fclose( theFile );
}
//free memory
gpuErrchk( hipFree( devX ) );
gpuErrchk( hipFree( devY ) );
gpuErrchk( hipFree( devV ) );
gpuErrchk( hipFree( devVoronoiDiagram ) );
free( X );
free( Y );
free( V );
free( VoronoiDiagram );
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9Voronoi2DmmmPfS_PiS0_
.globl _Z9Voronoi2DmmmPfS_PiS0_
.p2align 8
.type _Z9Voronoi2DmmmPfS_PiS0_,@function
_Z9Voronoi2DmmmPfS_PiS0_:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x44
s_load_b64 s[2:3], s[0:1], 0x10
v_bfe_u32 v3, v0, 10, 10
s_add_u32 s4, s0, 56
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s12, s6, 16
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s12, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_12
s_load_b32 s6, s[4:5], 0xc
s_load_b128 s[16:19], s[0:1], 0x0
v_and_b32_e32 v0, 0x3ff, v0
s_load_b64 s[20:21], s[4:5], 0x0
v_mov_b32_e32 v6, 0
s_mov_b32 s27, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s13, s6, 0xffff
s_load_b256 s[4:11], s[0:1], 0x18
v_mad_u64_u32 v[3:4], null, s14, s13, v[0:1]
v_mov_b32_e32 v0, 0x7f7fffff
s_cmp_lg_u64 s[16:17], 0
s_mul_i32 s25, s20, s13
s_cselect_b32 s24, -1, 0
s_mul_i32 s26, s21, s12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_cmp_gt_u64_e64 s0, s[18:19], v[3:4]
s_branch .LBB0_4
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s29
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s28
v_add_nc_u32_e32 v1, s26, v1
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[1:2]
s_or_b32 s27, vcc_lo, s27
s_and_not1_b32 exec_lo, exec_lo, s27
s_cbranch_execz .LBB0_12
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s28, s0
s_cbranch_execz .LBB0_3
v_mul_lo_u32 v2, s25, v1
v_cvt_f32_i32_e32 v8, v1
v_mov_b32_e32 v4, v3
s_mov_b32 s29, 0
s_branch .LBB0_7
.LBB0_6:
s_set_inst_prefetch_distance 0x2
v_add_nc_u32_e32 v9, v4, v2
v_add_nc_u32_e32 v4, s25, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v10, 31, v9
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_cmp_le_u64_e32 vcc_lo, s[18:19], v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v9, s1, s10, v9
v_add_co_ci_u32_e64 v10, s1, s11, v10, s1
s_or_b32 s29, vcc_lo, s29
s_waitcnt vmcnt(0)
global_store_b32 v[9:10], v7, off
s_and_not1_b32 exec_lo, exec_lo, s29
s_cbranch_execz .LBB0_2
.LBB0_7:
s_and_not1_b32 vcc_lo, exec_lo, s24
s_cbranch_vccnz .LBB0_6
v_cvt_f32_i32_e32 v5, v4
s_mov_b64 s[12:13], 0
s_waitcnt lgkmcnt(0)
s_mov_b64 s[14:15], s[4:5]
s_mov_b64 s[20:21], s[6:7]
s_mov_b64 s[22:23], s[8:9]
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_10
.p2align 6
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s1
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_add_u32 s22, s22, 4
v_cmp_ge_u64_e64 s1, s[12:13], s[16:17]
s_addc_u32 s23, s23, 0
s_add_u32 s20, s20, 4
s_addc_u32 s21, s21, 0
s_add_u32 s14, s14, 4
s_addc_u32 s15, s15, 0
s_and_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB0_6
.LBB0_10:
s_load_b32 s1, s[20:21], 0x0
s_load_b32 s30, s[14:15], 0x0
s_waitcnt lgkmcnt(0)
v_dual_sub_f32 v9, s1, v8 :: v_dual_sub_f32 v10, s30, v5
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v9, v9, v9
v_fmac_f32_e32 v9, v10, v10
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_f32_e32 v9, v0
s_cbranch_execz .LBB0_9
global_load_b32 v7, v6, s[22:23]
v_mov_b32_e32 v0, v9
s_branch .LBB0_9
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9Voronoi2DmmmPfS_PiS0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 31
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9Voronoi2DmmmPfS_PiS0_, .Lfunc_end0-_Z9Voronoi2DmmmPfS_PiS0_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9Voronoi2DmmmPfS_PiS0_
.private_segment_fixed_size: 0
.sgpr_count: 33
.sgpr_spill_count: 0
.symbol: _Z9Voronoi2DmmmPfS_PiS0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <assert.h>
#include <cstdio>
#include <cstdlib>
#include <cmath>
#include <cstring>
#include <ctime>
#include <sys/time.h>
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <float.h>
#include <cmath>
/*
* This macro checks for API errors in the CUDA calls.
*/
#define gpuErrchk(ans) { gpuAssert( (ans), __FILE__, __LINE__ ); }
inline void
gpuAssert( hipError_t code, const char * file, int line, bool abort = true )
{
if ( hipSuccess != code )
{
fprintf( stderr, "\nGPUassert: %s %s %d\n", hipGetErrorString( code ), file, line );
if ( abort )
exit( code );
}
return;
} /* gpuAssert */
/* ========================================================================== */
/* Voronoi2D */
/* -------------------------------------------------------------------------- */
/*!
* @function Voronoi2D
*
* @abstract
*
* @discussion Calculates Voronoi cells
*
* @param inNbOfSites [input] The number of the sites (seeds).
* type: const size_t
*
* @param inWidth [input] The width of the Voronoi image.
* type: const size_t
*
* @param inHeight [input] The height of the Voronoi image.
* type: const size_t
*
* @param inX [input] The x coordinates of the points
* Dimensions : Nx , type: float
*
* @param inY [input] The y coordinates of the points
* Dimensions : Ny , type: float
*
* @param inV [input] The inV holds for applying a threshold/color
* to the cell region
* Dimensions : inNbOfSites, type: int
*
* @param ouVoronoi [output] The output data (pixels)
* Dimensions : The total number of threads in the grid
* ( theBlocksPerGridX * theBlocksPerGridY * theThreadsPerBlockX * theThreadsPerBlockY )
* type: float
*/
/* ========================================================================== */
__global__ void Voronoi2D(
const size_t inNbOfSites,
const size_t inWidth,
const size_t inHeight,
float * const inX,
float * const inY,
int * const inV,
int * const ouVoronoi )
{
float distX , distY;
float theTempDistance ,theDistance = FLT_MAX;
int theThreshold;
//loop through all points calculating distance
for ( int y = ( ( blockIdx.y * blockDim.y ) + threadIdx.y ); y < inHeight; y += blockDim.y * gridDim.y )
{
for ( int x = ( ( blockIdx.x * blockDim.x ) + threadIdx.x ); x < inWidth; x += blockDim.x * gridDim.x )
{
int theGlobalIdx = y * ( blockDim.x * gridDim.x ) + x;
//Calculate distances for all the points
for ( int i = 0; i < inNbOfSites; i++ )
{
distX = inX[ i ] - x;
distY = inY[ i ] - y;
theTempDistance = distX * distX + distY * distY;
//if this Point is closer , assign proper threshold
if ( theTempDistance < theDistance )
{
theDistance = theTempDistance;
theThreshold = inV[ i ];
}
}
//write result back to global memory
*( ouVoronoi + theGlobalIdx ) = theThreshold;
} /* x */
} /* y */
}
int main()
{
const size_t Width = 256 , Height = 256;
const size_t Nx = 128 , Ny = 128;
const size_t NbOfSites = 100; //should be <= Nx and Ny
const size_t ThreadsPerBlockX = 16 , ThreadsPerBlockY = 16 ,BlocksPerGridX = Width / 16 , BlocksPerGridY = Height / 16;
const size_t TotalNbOfPixels = ( Width * Height );
// Allocate host memory
float * X = (float*) malloc( Nx * sizeof (*X) );
assert( NULL != X );
float * Y = (float*) malloc( Ny * sizeof (*Y) );
assert( NULL != Y );
int * V = (int*) malloc( NbOfSites * sizeof (*V) );
assert( NULL != V );
int * VoronoiDiagram = (int*) malloc ( TotalNbOfPixels * sizeof(*VoronoiDiagram) );
assert( NULL != VoronoiDiagram );
float * devX , * devY;
int * devVoronoiDiagram , * devV;
// Allocate device memory
gpuErrchk( hipMalloc( (void**) &devX, Nx * sizeof(*devX) ) );
gpuErrchk( hipMalloc( (void**) &devY, Ny * sizeof(*devY) ) );
gpuErrchk( hipMalloc( (void**) &devV, NbOfSites * sizeof(*devV) ) );
gpuErrchk( hipMalloc( (void**) &devVoronoiDiagram, TotalNbOfPixels * sizeof(*devVoronoiDiagram) ) );
// Create random coordinates
srand((unsigned int)time(NULL));
for ( int i = 0; i < Nx; i++ ) X[ i ] = ( ( (float) rand() / (float) ( RAND_MAX ) ) * Width );
for ( int i = 0; i < Ny; i++ ) Y[ i ] = ( ( (float) rand() / (float) ( RAND_MAX ) ) * Height );
for ( int i = 0; i < NbOfSites; i++ ) V[ i ] = i;
// Define grid dimensions
dim3 BlocksDim ( BlocksPerGridX , BlocksPerGridY );
dim3 ThreadsPerBlock ( ThreadsPerBlockX , ThreadsPerBlockY );
gpuErrchk( hipMemcpy( devV , V , NbOfSites * sizeof( *V ), hipMemcpyHostToDevice ) );
gpuErrchk( hipMemcpy( devX , X , Nx * sizeof( *X ), hipMemcpyHostToDevice ) );
gpuErrchk( hipMemcpy( devY , Y , Ny * sizeof( *Y ), hipMemcpyHostToDevice ) );
hipEvent_t CurrentEventPre,
CurrentEventPost;
float CurrentPostPreTimeMS;
gpuErrchk( hipEventCreate( &CurrentEventPre ) );
gpuErrchk( hipEventCreate( &CurrentEventPost ) );
gpuErrchk( hipEventRecord( CurrentEventPre ) );
Voronoi2D<<< BlocksDim,ThreadsPerBlock >>>( NbOfSites,
Width,
Height,
devX,
devY,
devV,
devVoronoiDiagram );
gpuErrchk( hipPeekAtLastError() );
gpuErrchk( hipDeviceSynchronize() );
gpuErrchk( hipEventRecord( CurrentEventPost ) );
gpuErrchk( hipEventSynchronize( CurrentEventPost ) );
gpuErrchk( hipEventElapsedTime( &CurrentPostPreTimeMS, CurrentEventPre, CurrentEventPost ) );
printf( "\nGPU time for calling Voronoi: %f ms\n", CurrentPostPreTimeMS );
gpuErrchk( hipMemcpy( VoronoiDiagram,
devVoronoiDiagram ,
TotalNbOfPixels * sizeof(*devVoronoiDiagram), hipMemcpyDeviceToHost ) );
{
FILE * theFile;
theFile = fopen( "Voronoi2D", "wb" );
assert( NULL != theFile );
assert( TotalNbOfPixels == fwrite( VoronoiDiagram , sizeof(*devVoronoiDiagram), TotalNbOfPixels , theFile ) );
fclose( theFile );
}
//free memory
gpuErrchk( hipFree( devX ) );
gpuErrchk( hipFree( devY ) );
gpuErrchk( hipFree( devV ) );
gpuErrchk( hipFree( devVoronoiDiagram ) );
free( X );
free( Y );
free( V );
free( VoronoiDiagram );
return 0;
} | .text
.file "Voronoi2D.hip"
.globl _Z24__device_stub__Voronoi2DmmmPfS_PiS0_ # -- Begin function _Z24__device_stub__Voronoi2DmmmPfS_PiS0_
.p2align 4, 0x90
.type _Z24__device_stub__Voronoi2DmmmPfS_PiS0_,@function
_Z24__device_stub__Voronoi2DmmmPfS_PiS0_: # @_Z24__device_stub__Voronoi2DmmmPfS_PiS0_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9Voronoi2DmmmPfS_PiS0_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z24__device_stub__Voronoi2DmmmPfS_PiS0_, .Lfunc_end0-_Z24__device_stub__Voronoi2DmmmPfS_PiS0_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI1_1:
.long 0x43800000 # float 256
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $512, %edi # imm = 0x200
callq malloc
movq %rax, %rbx
movl $512, %edi # imm = 0x200
callq malloc
movq %rax, %r14
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %r15
movl $262144, %edi # imm = 0x40000
callq malloc
movq %rax, %r12
leaq 40(%rsp), %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.3: # %_Z9gpuAssert10hipError_tPKcib.exit
leaq 32(%rsp), %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
testl %eax, %eax
jne .LBB1_4
# %bb.5: # %_Z9gpuAssert10hipError_tPKcib.exit33
leaq 16(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
testl %eax, %eax
jne .LBB1_6
# %bb.7: # %_Z9gpuAssert10hipError_tPKcib.exit35
leaq 24(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
testl %eax, %eax
jne .LBB1_8
# %bb.9: # %_Z9gpuAssert10hipError_tPKcib.exit37
xorl %r13d, %r13d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
.p2align 4, 0x90
.LBB1_10: # =>This Inner Loop Header: Depth=1
callq rand
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movss %xmm0, (%rbx,%r13,4)
incq %r13
cmpq $128, %r13
jne .LBB1_10
# %bb.11: # %.preheader72.preheader
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_12: # %.preheader72
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
mulss .LCPI1_1(%rip), %xmm0
movss %xmm0, (%r14,%r13,4)
incq %r13
cmpq $128, %r13
jne .LBB1_12
# %bb.13: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_14: # %.preheader
# =>This Inner Loop Header: Depth=1
movl %eax, (%r15,%rax,4)
incq %rax
cmpq $100, %rax
jne .LBB1_14
# %bb.15:
movq 16(%rsp), %rdi
movl $400, %edx # imm = 0x190
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_16
# %bb.17: # %_Z9gpuAssert10hipError_tPKcib.exit39
movq 40(%rsp), %rdi
movl $512, %edx # imm = 0x200
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_18
# %bb.19: # %_Z9gpuAssert10hipError_tPKcib.exit41
movq 32(%rsp), %rdi
movl $512, %edx # imm = 0x200
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_20
# %bb.21: # %_Z9gpuAssert10hipError_tPKcib.exit43
leaq 48(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB1_22
# %bb.23: # %_Z9gpuAssert10hipError_tPKcib.exit45
leaq 8(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB1_24
# %bb.25: # %_Z9gpuAssert10hipError_tPKcib.exit47
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB1_26
# %bb.27: # %_Z9gpuAssert10hipError_tPKcib.exit49
movabsq $68719476752, %rdi # imm = 0x1000000010
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_29
# %bb.28:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 16(%rsp), %rdx
movq 24(%rsp), %rsi
movq $100, 152(%rsp)
movq $256, 144(%rsp) # imm = 0x100
movq $256, 136(%rsp) # imm = 0x100
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movq %rdx, 112(%rsp)
movq %rsi, 104(%rsp)
leaq 152(%rsp), %rax
movq %rax, 160(%rsp)
leaq 144(%rsp), %rax
movq %rax, 168(%rsp)
leaq 136(%rsp), %rax
movq %rax, 176(%rsp)
leaq 128(%rsp), %rax
movq %rax, 184(%rsp)
leaq 120(%rsp), %rax
movq %rax, 192(%rsp)
leaq 112(%rsp), %rax
movq %rax, 200(%rsp)
leaq 104(%rsp), %rax
movq %rax, 208(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z9Voronoi2DmmmPfS_PiS0_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_29:
callq hipPeekAtLastError
testl %eax, %eax
jne .LBB1_30
# %bb.31: # %_Z9gpuAssert10hipError_tPKcib.exit51
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_32
# %bb.33: # %_Z9gpuAssert10hipError_tPKcib.exit53
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB1_34
# %bb.35: # %_Z9gpuAssert10hipError_tPKcib.exit55
movq 8(%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
jne .LBB1_36
# %bb.37: # %_Z9gpuAssert10hipError_tPKcib.exit57
movq 48(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 160(%rsp), %rdi
callq hipEventElapsedTime
testl %eax, %eax
jne .LBB1_38
# %bb.39: # %_Z9gpuAssert10hipError_tPKcib.exit59
movss 160(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 24(%rsp), %rsi
movl $262144, %edx # imm = 0x40000
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_40
# %bb.41: # %_Z9gpuAssert10hipError_tPKcib.exit61
movl $.L.str.2, %edi
movl $.L.str.3, %esi
callq fopen
movq %rax, %rdi
callq fclose
movq 40(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_42
# %bb.43: # %_Z9gpuAssert10hipError_tPKcib.exit63
movq 32(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_44
# %bb.45: # %_Z9gpuAssert10hipError_tPKcib.exit65
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_46
# %bb.47: # %_Z9gpuAssert10hipError_tPKcib.exit67
movq 24(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_48
# %bb.49: # %_Z9gpuAssert10hipError_tPKcib.exit69
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 272
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $142, %r8d
jmp .LBB1_2
.LBB1_4:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $143, %r8d
jmp .LBB1_2
.LBB1_6:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $144, %r8d
jmp .LBB1_2
.LBB1_8:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $145, %r8d
jmp .LBB1_2
.LBB1_16:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $158, %r8d
jmp .LBB1_2
.LBB1_18:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $159, %r8d
jmp .LBB1_2
.LBB1_20:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $160, %r8d
jmp .LBB1_2
.LBB1_22:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $166, %r8d
jmp .LBB1_2
.LBB1_24:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $167, %r8d
jmp .LBB1_2
.LBB1_26:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $169, %r8d
jmp .LBB1_2
.LBB1_30:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $180, %r8d
jmp .LBB1_2
.LBB1_32:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $181, %r8d
jmp .LBB1_2
.LBB1_34:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $183, %r8d
jmp .LBB1_2
.LBB1_36:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $184, %r8d
jmp .LBB1_2
.LBB1_38:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $185, %r8d
jmp .LBB1_2
.LBB1_40:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $190, %r8d
jmp .LBB1_2
.LBB1_42:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $201, %r8d
jmp .LBB1_2
.LBB1_44:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $202, %r8d
jmp .LBB1_2
.LBB1_46:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $203, %r8d
jmp .LBB1_2
.LBB1_48:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $204, %r8d
.LBB1_2:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9Voronoi2DmmmPfS_PiS0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9Voronoi2DmmmPfS_PiS0_,@object # @_Z9Voronoi2DmmmPfS_PiS0_
.section .rodata,"a",@progbits
.globl _Z9Voronoi2DmmmPfS_PiS0_
.p2align 3, 0x0
_Z9Voronoi2DmmmPfS_PiS0_:
.quad _Z24__device_stub__Voronoi2DmmmPfS_PiS0_
.size _Z9Voronoi2DmmmPfS_PiS0_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/ggeo/Cuda/master/Voronoi/Voronoi2D.hip"
.size .L.str, 96
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\nGPU time for calling Voronoi: %f ms\n"
.size .L.str.1, 38
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Voronoi2D"
.size .L.str.2, 10
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "wb"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\nGPUassert: %s %s %d\n"
.size .L.str.4, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9Voronoi2DmmmPfS_PiS0_"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__Voronoi2DmmmPfS_PiS0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9Voronoi2DmmmPfS_PiS0_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9Voronoi2DmmmPfS_PiS0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R12, SR_CTAID.Y ; /* 0x00000000000c7919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002200 */
/*0030*/ IMAD R12, R12, c[0x0][0x4], R3 ; /* 0x000001000c0c7a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R12, c[0x0][0x170], PT ; /* 0x00005c000c007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R0, RZ, 0x1f, R12 ; /* 0x0000001fff007819 */
/* 0x000fc8000001140c */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R0, c[0x0][0x174], PT, P0 ; /* 0x00005d0000007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ S2R R15, SR_CTAID.X ; /* 0x00000000000f7919 */
/* 0x000e220000002500 */
/*0090*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x160], PT ; /* 0x00005800ff007a0c */
/* 0x000fc60003f05070 */
/*00a0*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*00b0*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x164], PT, P0 ; /* 0x00005900ff007a0c */
/* 0x000fe20003f05300 */
/*00c0*/ IMAD R15, R15, c[0x0][0x0], R0 ; /* 0x000000000f0f7a24 */
/* 0x001fd800078e0200 */
/*00d0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00e0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*00f0*/ MOV R2, c[0x0][0x164] ; /* 0x0000590000027a02 */
/* 0x000fe20000000f00 */
/*0100*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff0e7624 */
/* 0x000fe200078e00ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R15, c[0x0][0x168], PT ; /* 0x00005a000f007a0c */
/* 0x000fe20003f06070 */
/*0120*/ IMAD.MOV.U32 R11, RZ, RZ, 0x7f7fffff ; /* 0x7f7fffffff0b7424 */
/* 0x000fe200078e00ff */
/*0130*/ IADD3 R0, P2, -R0, c[0x0][0x160], RZ ; /* 0x0000580000007a10 */
/* 0x000fe20007f5e1ff */
/*0140*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0150*/ LOP3.LUT R14, R14, 0x3, RZ, 0xc0, !PT ; /* 0x000000030e0e7812 */
/* 0x000fe200078ec0ff */
/*0160*/ ULDC UR5, c[0x0][0xc] ; /* 0x0000030000057ab9 */
/* 0x000fe20000000800 */
/*0170*/ ISETP.GE.U32.AND P1, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe20003f26070 */
/*0180*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fe2000f8e023f */
/*0190*/ IADD3.X R0, R2, -0x1, RZ, P2, !PT ; /* 0xffffffff02007810 */
/* 0x000fe200017fe4ff */
/*01a0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*01b0*/ SHF.R.S32.HI R3, RZ, 0x1f, R15 ; /* 0x0000001fff037819 */
/* 0x000fc4000001140f */
/*01c0*/ IADD3 R13, P2, R14, -c[0x0][0x160], RZ ; /* 0x800058000e0d7a10 */
/* 0x000fe40007f5e0ff */
/*01d0*/ ISETP.GE.U32.AND.EX P0, PT, R3, c[0x0][0x16c], PT, P0 ; /* 0x00005b0003007a0c */
/* 0x000fe40003f06100 */
/*01e0*/ ISETP.GE.U32.AND.EX P1, PT, R0, RZ, PT, P1 ; /* 0x000000ff0000720c */
/* 0x000fe40003f26110 */
/*01f0*/ IADD3.X R10, RZ, ~c[0x0][0x164], RZ, P2, !PT ; /* 0x80005900ff0a7a10 */
/* 0x000fd000017fe4ff */
/*0200*/ BSSY B0, 0x9f0 ; /* 0x000007e000007945 */
/* 0x000fe20003800000 */
/*0210*/ @P0 BRA 0x9e0 ; /* 0x000007c000000947 */
/* 0x00efea0003800000 */
/*0220*/ IMAD.MOV.U32 R9, RZ, RZ, R15 ; /* 0x000000ffff097224 */
/* 0x000fe400078e000f */
/*0230*/ ISETP.NE.U32.AND P2, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe20003f45070 */
/*0240*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fc600078e00ff */
/*0250*/ ISETP.NE.AND.EX P2, PT, RZ, RZ, PT, P2 ; /* 0x000000ffff00720c */
/* 0x000fe20003f45320 */
/*0260*/ @!P1 BRA 0x640 ; /* 0x000003d000009947 */
/* 0x00efd80003800000 */
/*0270*/ I2F R16, R12 ; /* 0x0000000c00107306 */
/* 0x0000620000201400 */
/*0280*/ HFMA2.MMA R8, -RZ, RZ, 0, 0 ; /* 0x00000000ff087435 */
/* 0x000fe200000001ff */
/*0290*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff067624 */
/* 0x000fe200078e00ff */
/*02a0*/ MOV R7, c[0x0][0x18c] ; /* 0x0000630000077a02 */
/* 0x000fe20000000f00 */
/*02b0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff027624 */
/* 0x000fe200078e00ff */
/*02c0*/ MOV R3, c[0x0][0x184] ; /* 0x0000610000037a02 */
/* 0x000fe20000000f00 */
/*02d0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff047624 */
/* 0x000fe200078e00ff */
/*02e0*/ MOV R5, c[0x0][0x17c] ; /* 0x00005f0000057a02 */
/* 0x000fe20000000f00 */
/*02f0*/ I2F R17, R9 ; /* 0x0000000900117306 */
/* 0x0000a20000201400 */
/*0300*/ IMAD.MOV.U32 R20, RZ, RZ, R13 ; /* 0x000000ffff147224 */
/* 0x000fe200078e000d */
/*0310*/ MOV R19, R10 ; /* 0x0000000a00137202 */
/* 0x000fcc0000000f00 */
/*0320*/ LDG.E R23, [R2.64+0x4] ; /* 0x0000040602177981 */
/* 0x000ee8000c1e1900 */
/*0330*/ LDG.E R21, [R4.64+0x4] ; /* 0x0000040604157981 */
/* 0x000f28000c1e1900 */
/*0340*/ LDG.E R25, [R2.64] ; /* 0x0000000602197981 */
/* 0x004ea8000c1e1900 */
/*0350*/ LDG.E R26, [R4.64] ; /* 0x00000006041a7981 */
/* 0x000ea2000c1e1900 */
/*0360*/ I2F R24, R12 ; /* 0x0000000c00187306 */
/* 0x000ef00000201400 */
/*0370*/ I2F R18, R9 ; /* 0x0000000900127306 */
/* 0x000f220000201400 */
/*0380*/ FADD R23, R23, -R24 ; /* 0x8000001817177221 */
/* 0x008fc40000000000 */
/*0390*/ FADD R21, R21, -R18 ; /* 0x8000001215157221 */
/* 0x010fe40000000000 */
/*03a0*/ FMUL R22, R23, R23 ; /* 0x0000001717167220 */
/* 0x000fe40000400000 */
/*03b0*/ FADD R25, -R16, R25 ; /* 0x0000001910197221 */
/* 0x006fe20000000100 */
/*03c0*/ LDG.E R23, [R2.64+0xc] ; /* 0x00000c0602177981 */
/* 0x000ea2000c1e1900 */
/*03d0*/ FFMA R22, R21, R21, R22 ; /* 0x0000001515167223 */
/* 0x000fc60000000016 */
/*03e0*/ LDG.E R21, [R2.64+0x8] ; /* 0x0000080602157981 */
/* 0x000ee2000c1e1900 */
/*03f0*/ FADD R26, -R17, R26 ; /* 0x0000001a111a7221 */
/* 0x000fe40000000100 */
/*0400*/ FMUL R25, R25, R25 ; /* 0x0000001919197220 */
/* 0x000fc80000400000 */
/*0410*/ FFMA R26, R26, R26, R25 ; /* 0x0000001a1a1a7223 */
/* 0x000fca0000000019 */
/*0420*/ FSETP.GEU.AND P3, PT, R26, R11, PT ; /* 0x0000000b1a00720b */
/* 0x000fda0003f6e000 */
/*0430*/ @!P3 LDG.E R0, [R6.64] ; /* 0x000000060600b981 */
/* 0x020322000c1e1900 */
/*0440*/ @!P3 IMAD.MOV.U32 R11, RZ, RZ, R26 ; /* 0x000000ffff0bb224 */
/* 0x000fca00078e001a */
/*0450*/ FSETP.GEU.AND P3, PT, R22, R11, PT ; /* 0x0000000b1600720b */
/* 0x000fe20003f6e000 */
/*0460*/ FADD R25, R21, -R24.reuse ; /* 0x8000001815197221 */
/* 0x108fe40000000000 */
/*0470*/ LDG.E R21, [R4.64+0x8] ; /* 0x0000080604157981 */
/* 0x000ef4000c1e1900 */
/*0480*/ @!P3 LDG.E R0, [R6.64+0x4] ; /* 0x000004060600b981 */
/* 0x010322000c1e1900 */
/*0490*/ FADD R23, R23, -R24 ; /* 0x8000001817177221 */
/* 0x004fc40000000000 */
/*04a0*/ FMUL R24, R25, R25 ; /* 0x0000001919187220 */
/* 0x000fe20000400000 */
/*04b0*/ @!P3 MOV R11, R22 ; /* 0x00000016000bb202 */
/* 0x000fe20000000f00 */
/*04c0*/ FADD R21, R21, -R18 ; /* 0x8000001215157221 */
/* 0x008fc80000000000 */
/*04d0*/ FFMA R24, R21, R21, R24 ; /* 0x0000001515187223 */
/* 0x000fe40000000018 */
/*04e0*/ LDG.E R21, [R4.64+0xc] ; /* 0x00000c0604157981 */
/* 0x0004e6000c1e1900 */
/*04f0*/ FSETP.GEU.AND P3, PT, R24, R11, PT ; /* 0x0000000b1800720b */
/* 0x000fda0003f6e000 */
/*0500*/ @!P3 LDG.E R0, [R6.64+0x8] ; /* 0x000008060600b981 */
/* 0x010322000c1e1900 */
/*0510*/ @!P3 IMAD.MOV.U32 R11, RZ, RZ, R24 ; /* 0x000000ffff0bb224 */
/* 0x000fe200078e0018 */
/*0520*/ IADD3 R20, P3, R20, 0x4, RZ ; /* 0x0000000414147810 */
/* 0x000fc80007f7e0ff */
/*0530*/ IADD3.X R19, RZ, R19, RZ, P3, !PT ; /* 0x00000013ff137210 */
/* 0x000fe40001ffe4ff */
/*0540*/ ISETP.NE.U32.AND P3, PT, R20, RZ, PT ; /* 0x000000ff1400720c */
/* 0x000fc80003f65070 */
/*0550*/ ISETP.NE.AND.EX P3, PT, R19, RZ, PT, P3 ; /* 0x000000ff1300720c */
/* 0x000fe40003f65330 */
/*0560*/ IADD3 R4, P5, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x004fe40007fbe0ff */
/*0570*/ IADD3 R2, P6, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fc60007fde0ff */
/*0580*/ IMAD.X R5, RZ, RZ, R5, P5 ; /* 0x000000ffff057224 */
/* 0x000fe200028e0605 */
/*0590*/ IADD3.X R3, RZ, R3, RZ, P6, !PT ; /* 0x00000003ff037210 */
/* 0x000fe400037fe4ff */
/*05a0*/ IADD3 R8, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fe20007ffe0ff */
/*05b0*/ FADD R21, R21, -R18 ; /* 0x8000001215157221 */
/* 0x008fe40000000000 */
/*05c0*/ FMUL R18, R23, R23 ; /* 0x0000001717127220 */
/* 0x000fc80000400000 */
/*05d0*/ FFMA R18, R21, R21, R18 ; /* 0x0000001515127223 */
/* 0x000fca0000000012 */
/*05e0*/ FSETP.GEU.AND P4, PT, R18, R11, PT ; /* 0x0000000b1200720b */
/* 0x000fda0003f8e000 */
/*05f0*/ @!P4 LDG.E R0, [R6.64+0xc] ; /* 0x00000c060600c981 */
/* 0x010362000c1e1900 */
/*0600*/ @!P4 MOV R11, R18 ; /* 0x00000012000bc202 */
/* 0x000fe40000000f00 */
/*0610*/ IADD3 R6, P5, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x002fca0007fbe0ff */
/*0620*/ IMAD.X R7, RZ, RZ, R7, P5 ; /* 0x000000ffff077224 */
/* 0x000fe200028e0607 */
/*0630*/ @P3 BRA 0x320 ; /* 0xfffffce000003947 */
/* 0x000fea000383ffff */
/*0640*/ @!P2 BRA 0x950 ; /* 0x000003000000a947 */
/* 0x000fea0003800000 */
/*0650*/ IMAD.MOV.U32 R19, RZ, RZ, 0x4 ; /* 0x00000004ff137424 */
/* 0x000fc800078e00ff */
/*0660*/ IMAD.WIDE R2, R8, R19, c[0x0][0x180] ; /* 0x0000600008027625 */
/* 0x000fc800078e0213 */
/*0670*/ IMAD.WIDE R4, R8, R19, c[0x0][0x178] ; /* 0x00005e0008047625 */
/* 0x000fe200078e0213 */
/*0680*/ LDG.E R6, [R2.64] ; /* 0x0000000602067981 */
/* 0x000ea8000c1e1900 */
/*0690*/ LDG.E R7, [R4.64] ; /* 0x0000000604077981 */
/* 0x000ee2000c1e1900 */
/*06a0*/ I2F R17, R12 ; /* 0x0000000c00117306 */
/* 0x000ea20000201400 */
/*06b0*/ ISETP.NE.U32.AND P2, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fe20003f45070 */
/*06c0*/ BSSY B1, 0x790 ; /* 0x000000c000017945 */
/* 0x000fe60003800000 */
/*06d0*/ ISETP.NE.AND.EX P2, PT, RZ, RZ, PT, P2 ; /* 0x000000ffff00720c */
/* 0x000fc60003f45320 */
/*06e0*/ I2F R16, R9 ; /* 0x0000000900107306 */
/* 0x000ee20000201400 */
/*06f0*/ FADD R6, R6, -R17 ; /* 0x8000001106067221 */
/* 0x004fe40000000000 */
/*0700*/ FADD R7, R7, -R16 ; /* 0x8000001007077221 */
/* 0x008fe40000000000 */
/*0710*/ FMUL R6, R6, R6 ; /* 0x0000000606067220 */
/* 0x000fc80000400000 */
/*0720*/ FFMA R18, R7, R7, R6 ; /* 0x0000000707127223 */
/* 0x000fe40000000006 */
/*0730*/ IMAD.WIDE R6, R8, R19, c[0x0][0x188] ; /* 0x0000620008067625 */
/* 0x000fc600078e0213 */
/*0740*/ FSETP.GEU.AND P3, PT, R18, R11, PT ; /* 0x0000000b1200720b */
/* 0x000fda0003f6e000 */
/*0750*/ @P3 BRA 0x780 ; /* 0x0000002000003947 */
/* 0x000fea0003800000 */
/*0760*/ LDG.E R0, [R6.64] ; /* 0x0000000606007981 */
/* 0x020362000c1e1900 */
/*0770*/ MOV R11, R18 ; /* 0x00000012000b7202 */
/* 0x000fc60000000f00 */
/*0780*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0790*/ BSSY B1, 0x950 ; /* 0x000001b000017945 */
/* 0x000fe20003800000 */
/*07a0*/ @!P2 BRA 0x940 ; /* 0x000001900000a947 */
/* 0x000fea0003800000 */
/*07b0*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040602087981 */
/* 0x000ea8000c1e1900 */
/*07c0*/ LDG.E R19, [R4.64+0x4] ; /* 0x0000040604137981 */
/* 0x000ee2000c1e1900 */
/*07d0*/ ISETP.NE.U32.AND P2, PT, R14, 0x2, PT ; /* 0x000000020e00780c */
/* 0x000fe20003f45070 */
/*07e0*/ BSSY B2, 0x890 ; /* 0x000000a000027945 */
/* 0x000fe60003800000 */
/*07f0*/ ISETP.NE.AND.EX P2, PT, RZ, RZ, PT, P2 ; /* 0x000000ffff00720c */
/* 0x000fe20003f45320 */
/*0800*/ FADD R8, R8, -R17 ; /* 0x8000001108087221 */
/* 0x004fc40000000000 */
/*0810*/ FADD R19, R19, -R16 ; /* 0x8000001013137221 */
/* 0x008fe40000000000 */
/*0820*/ FMUL R8, R8, R8 ; /* 0x0000000808087220 */
/* 0x000fc80000400000 */
/*0830*/ FFMA R8, R19, R19, R8 ; /* 0x0000001313087223 */
/* 0x000fca0000000008 */
/*0840*/ FSETP.GEU.AND P3, PT, R8, R11, PT ; /* 0x0000000b0800720b */
/* 0x000fda0003f6e000 */
/*0850*/ @P3 BRA 0x880 ; /* 0x0000002000003947 */
/* 0x000fea0003800000 */
/*0860*/ LDG.E R0, [R6.64+0x4] ; /* 0x0000040606007981 */
/* 0x020562000c1e1900 */
/*0870*/ IMAD.MOV.U32 R11, RZ, RZ, R8 ; /* 0x000000ffff0b7224 */
/* 0x000fc600078e0008 */
/*0880*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0890*/ @!P2 BRA 0x940 ; /* 0x000000a00000a947 */
/* 0x000fea0003800000 */
/*08a0*/ LDG.E R2, [R2.64+0x8] ; /* 0x0000080602027981 */
/* 0x000ee8000c1e1900 */
/*08b0*/ LDG.E R5, [R4.64+0x8] ; /* 0x0000080604057981 */
/* 0x000f22000c1e1900 */
/*08c0*/ FADD R17, R2, -R17 ; /* 0x8000001102117221 */
/* 0x008fe40000000000 */
/*08d0*/ FADD R16, R5, -R16 ; /* 0x8000001005107221 */
/* 0x010fe40000000000 */
/*08e0*/ FMUL R17, R17, R17 ; /* 0x0000001111117220 */
/* 0x000fc80000400000 */
/*08f0*/ FFMA R16, R16, R16, R17 ; /* 0x0000001010107223 */
/* 0x000fca0000000011 */
/*0900*/ FSETP.GEU.AND P2, PT, R16, R11, PT ; /* 0x0000000b1000720b */
/* 0x000fda0003f4e000 */
/*0910*/ @P2 BRA 0x940 ; /* 0x0000002000002947 */
/* 0x000fea0003800000 */
/*0920*/ LDG.E R0, [R6.64+0x8] ; /* 0x0000080606007981 */
/* 0x020762000c1e1900 */
/*0930*/ MOV R11, R16 ; /* 0x00000010000b7202 */
/* 0x000fc60000000f00 */
/*0940*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0950*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*0960*/ IMAD R2, R12, UR4, R9 ; /* 0x000000040c027c24 */
/* 0x000fe2000f8e0209 */
/*0970*/ IADD3 R9, R9, UR4, RZ ; /* 0x0000000409097c10 */
/* 0x001fc6000fffe0ff */
/*0980*/ IMAD.WIDE R2, R2, R3, c[0x0][0x190] ; /* 0x0000640002027625 */
/* 0x000fe200078e0203 */
/*0990*/ ISETP.GE.U32.AND P2, PT, R9, c[0x0][0x168], PT ; /* 0x00005a0009007a0c */
/* 0x000fe40003f46070 */
/*09a0*/ SHF.R.S32.HI R4, RZ, 0x1f, R9 ; /* 0x0000001fff047819 */
/* 0x000fe40000011409 */
/*09b0*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x0201e4000c101906 */
/*09c0*/ ISETP.GE.U32.AND.EX P2, PT, R4, c[0x0][0x16c], PT, P2 ; /* 0x00005b0004007a0c */
/* 0x000fda0003f46120 */
/*09d0*/ @!P2 BRA 0x230 ; /* 0xfffff8500000a947 */
/* 0x001fea000383ffff */
/*09e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*09f0*/ MOV R3, c[0x0][0x4] ; /* 0x0000010000037a02 */
/* 0x000fca0000000f00 */
/*0a00*/ IMAD R12, R3, c[0x0][0x10], R12 ; /* 0x00000400030c7a24 */
/* 0x000fca00078e020c */
/*0a10*/ ISETP.GE.U32.AND P2, PT, R12, c[0x0][0x170], PT ; /* 0x00005c000c007a0c */
/* 0x000fe40003f46070 */
/*0a20*/ SHF.R.S32.HI R2, RZ, 0x1f, R12 ; /* 0x0000001fff027819 */
/* 0x000fc8000001140c */
/*0a30*/ ISETP.GE.U32.AND.EX P2, PT, R2, c[0x0][0x174], PT, P2 ; /* 0x00005d0002007a0c */
/* 0x000fda0003f46120 */
/*0a40*/ @!P2 BRA 0x200 ; /* 0xfffff7b00000a947 */
/* 0x000fea000383ffff */
/*0a50*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a60*/ BRA 0xa60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9Voronoi2DmmmPfS_PiS0_
.globl _Z9Voronoi2DmmmPfS_PiS0_
.p2align 8
.type _Z9Voronoi2DmmmPfS_PiS0_,@function
_Z9Voronoi2DmmmPfS_PiS0_:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x44
s_load_b64 s[2:3], s[0:1], 0x10
v_bfe_u32 v3, v0, 10, 10
s_add_u32 s4, s0, 56
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s12, s6, 16
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s12, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_12
s_load_b32 s6, s[4:5], 0xc
s_load_b128 s[16:19], s[0:1], 0x0
v_and_b32_e32 v0, 0x3ff, v0
s_load_b64 s[20:21], s[4:5], 0x0
v_mov_b32_e32 v6, 0
s_mov_b32 s27, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s13, s6, 0xffff
s_load_b256 s[4:11], s[0:1], 0x18
v_mad_u64_u32 v[3:4], null, s14, s13, v[0:1]
v_mov_b32_e32 v0, 0x7f7fffff
s_cmp_lg_u64 s[16:17], 0
s_mul_i32 s25, s20, s13
s_cselect_b32 s24, -1, 0
s_mul_i32 s26, s21, s12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_cmp_gt_u64_e64 s0, s[18:19], v[3:4]
s_branch .LBB0_4
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s29
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s28
v_add_nc_u32_e32 v1, s26, v1
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[1:2]
s_or_b32 s27, vcc_lo, s27
s_and_not1_b32 exec_lo, exec_lo, s27
s_cbranch_execz .LBB0_12
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s28, s0
s_cbranch_execz .LBB0_3
v_mul_lo_u32 v2, s25, v1
v_cvt_f32_i32_e32 v8, v1
v_mov_b32_e32 v4, v3
s_mov_b32 s29, 0
s_branch .LBB0_7
.LBB0_6:
s_set_inst_prefetch_distance 0x2
v_add_nc_u32_e32 v9, v4, v2
v_add_nc_u32_e32 v4, s25, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v10, 31, v9
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_cmp_le_u64_e32 vcc_lo, s[18:19], v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v9, s1, s10, v9
v_add_co_ci_u32_e64 v10, s1, s11, v10, s1
s_or_b32 s29, vcc_lo, s29
s_waitcnt vmcnt(0)
global_store_b32 v[9:10], v7, off
s_and_not1_b32 exec_lo, exec_lo, s29
s_cbranch_execz .LBB0_2
.LBB0_7:
s_and_not1_b32 vcc_lo, exec_lo, s24
s_cbranch_vccnz .LBB0_6
v_cvt_f32_i32_e32 v5, v4
s_mov_b64 s[12:13], 0
s_waitcnt lgkmcnt(0)
s_mov_b64 s[14:15], s[4:5]
s_mov_b64 s[20:21], s[6:7]
s_mov_b64 s[22:23], s[8:9]
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_10
.p2align 6
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s1
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_add_u32 s22, s22, 4
v_cmp_ge_u64_e64 s1, s[12:13], s[16:17]
s_addc_u32 s23, s23, 0
s_add_u32 s20, s20, 4
s_addc_u32 s21, s21, 0
s_add_u32 s14, s14, 4
s_addc_u32 s15, s15, 0
s_and_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB0_6
.LBB0_10:
s_load_b32 s1, s[20:21], 0x0
s_load_b32 s30, s[14:15], 0x0
s_waitcnt lgkmcnt(0)
v_dual_sub_f32 v9, s1, v8 :: v_dual_sub_f32 v10, s30, v5
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v9, v9, v9
v_fmac_f32_e32 v9, v10, v10
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_f32_e32 v9, v0
s_cbranch_execz .LBB0_9
global_load_b32 v7, v6, s[22:23]
v_mov_b32_e32 v0, v9
s_branch .LBB0_9
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9Voronoi2DmmmPfS_PiS0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 31
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9Voronoi2DmmmPfS_PiS0_, .Lfunc_end0-_Z9Voronoi2DmmmPfS_PiS0_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9Voronoi2DmmmPfS_PiS0_
.private_segment_fixed_size: 0
.sgpr_count: 33
.sgpr_spill_count: 0
.symbol: _Z9Voronoi2DmmmPfS_PiS0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00040d98_00000000-6_Voronoi2D.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
.string "\nGPUassert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L10
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.text
.globl _Z38__device_stub__Z9Voronoi2DmmmPfS_PiS0_mmmPfS_PiS0_
.type _Z38__device_stub__Z9Voronoi2DmmmPfS_PiS0_mmmPfS_PiS0_, @function
_Z38__device_stub__Z9Voronoi2DmmmPfS_PiS0_mmmPfS_PiS0_:
.LFB2083:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z9Voronoi2DmmmPfS_PiS0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z38__device_stub__Z9Voronoi2DmmmPfS_PiS0_mmmPfS_PiS0_, .-_Z38__device_stub__Z9Voronoi2DmmmPfS_PiS0_mmmPfS_PiS0_
.globl _Z9Voronoi2DmmmPfS_PiS0_
.type _Z9Voronoi2DmmmPfS_PiS0_, @function
_Z9Voronoi2DmmmPfS_PiS0_:
.LFB2084:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z38__device_stub__Z9Voronoi2DmmmPfS_PiS0_mmmPfS_PiS0_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z9Voronoi2DmmmPfS_PiS0_, .-_Z9Voronoi2DmmmPfS_PiS0_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/ggeo/Cuda/master/Voronoi/Voronoi2D.cu"
.align 8
.LC4:
.string "\nGPU time for calling Voronoi: %f ms\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "wb"
.LC6:
.string "Voronoi2D"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $512, %edi
call malloc@PLT
movq %rax, %r13
movl $512, %edi
call malloc@PLT
movq %rax, %r14
movl $400, %edi
call malloc@PLT
movq %rax, %rbp
movl $262144, %edi
call malloc@PLT
movq %rax, %r15
leaq 16(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $142, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 24(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $143, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 40(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $144, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 32(%rsp), %rdi
movl $262144, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $145, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movq %r13, %rbx
leaq 512(%r13), %r12
.L20:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC2(%rip), %xmm0
mulss .LC3(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %r12, %rbx
jne .L20
movq %r14, %rbx
leaq 512(%r14), %r12
.L21:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC2(%rip), %xmm0
mulss .LC3(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbx, %r12
jne .L21
movl $0, %eax
.L22:
movl %eax, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $100, %rax
jne .L22
movl $16, 64(%rsp)
movl $16, 68(%rsp)
movl $1, 72(%rsp)
movl $16, 76(%rsp)
movl $16, 80(%rsp)
movl $1, 84(%rsp)
movl $1, %ecx
movl $400, %edx
movq %rbp, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $158, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movl $512, %edx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $159, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movl $512, %edx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $160, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %edi
movl $1, %ecx
movl $166, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %edi
movl $1, %ecx
movl $167, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %edi
movl $1, %ecx
movl $169, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl 84(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movq 64(%rsp), %rdi
movl 72(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L23:
call cudaPeekAtLastError@PLT
movl %eax, %edi
movl $1, %ecx
movl $180, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $1, %ecx
movl $181, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %edi
movl $1, %ecx
movl $183, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
movl %eax, %edi
movl $1, %ecx
movl $184, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 12(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl %eax, %edi
movl $1, %ecx
movl $185, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $262144, %edx
movq 32(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $188, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq .LC5(%rip), %rsi
leaq .LC6(%rip), %rdi
call fopen@PLT
movq %rax, %rdi
call fclose@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $201, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 24(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $202, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 40(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $203, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 32(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $204, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq %r13, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
movq 56(%rsp), %r9
movq 40(%rsp), %r8
movq 32(%rsp), %rcx
movl $256, %edx
movl $256, %esi
movl $100, %edi
call _Z38__device_stub__Z9Voronoi2DmmmPfS_PiS0_mmmPfS_PiS0_
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L23
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z9Voronoi2DmmmPfS_PiS0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z9Voronoi2DmmmPfS_PiS0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 805306368
.align 4
.LC3:
.long 1132462080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Voronoi2D.hip"
.globl _Z24__device_stub__Voronoi2DmmmPfS_PiS0_ # -- Begin function _Z24__device_stub__Voronoi2DmmmPfS_PiS0_
.p2align 4, 0x90
.type _Z24__device_stub__Voronoi2DmmmPfS_PiS0_,@function
_Z24__device_stub__Voronoi2DmmmPfS_PiS0_: # @_Z24__device_stub__Voronoi2DmmmPfS_PiS0_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9Voronoi2DmmmPfS_PiS0_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z24__device_stub__Voronoi2DmmmPfS_PiS0_, .Lfunc_end0-_Z24__device_stub__Voronoi2DmmmPfS_PiS0_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI1_1:
.long 0x43800000 # float 256
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $512, %edi # imm = 0x200
callq malloc
movq %rax, %rbx
movl $512, %edi # imm = 0x200
callq malloc
movq %rax, %r14
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %r15
movl $262144, %edi # imm = 0x40000
callq malloc
movq %rax, %r12
leaq 40(%rsp), %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.3: # %_Z9gpuAssert10hipError_tPKcib.exit
leaq 32(%rsp), %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
testl %eax, %eax
jne .LBB1_4
# %bb.5: # %_Z9gpuAssert10hipError_tPKcib.exit33
leaq 16(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
testl %eax, %eax
jne .LBB1_6
# %bb.7: # %_Z9gpuAssert10hipError_tPKcib.exit35
leaq 24(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
testl %eax, %eax
jne .LBB1_8
# %bb.9: # %_Z9gpuAssert10hipError_tPKcib.exit37
xorl %r13d, %r13d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
.p2align 4, 0x90
.LBB1_10: # =>This Inner Loop Header: Depth=1
callq rand
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movss %xmm0, (%rbx,%r13,4)
incq %r13
cmpq $128, %r13
jne .LBB1_10
# %bb.11: # %.preheader72.preheader
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_12: # %.preheader72
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
mulss .LCPI1_1(%rip), %xmm0
movss %xmm0, (%r14,%r13,4)
incq %r13
cmpq $128, %r13
jne .LBB1_12
# %bb.13: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_14: # %.preheader
# =>This Inner Loop Header: Depth=1
movl %eax, (%r15,%rax,4)
incq %rax
cmpq $100, %rax
jne .LBB1_14
# %bb.15:
movq 16(%rsp), %rdi
movl $400, %edx # imm = 0x190
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_16
# %bb.17: # %_Z9gpuAssert10hipError_tPKcib.exit39
movq 40(%rsp), %rdi
movl $512, %edx # imm = 0x200
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_18
# %bb.19: # %_Z9gpuAssert10hipError_tPKcib.exit41
movq 32(%rsp), %rdi
movl $512, %edx # imm = 0x200
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_20
# %bb.21: # %_Z9gpuAssert10hipError_tPKcib.exit43
leaq 48(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB1_22
# %bb.23: # %_Z9gpuAssert10hipError_tPKcib.exit45
leaq 8(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB1_24
# %bb.25: # %_Z9gpuAssert10hipError_tPKcib.exit47
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB1_26
# %bb.27: # %_Z9gpuAssert10hipError_tPKcib.exit49
movabsq $68719476752, %rdi # imm = 0x1000000010
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_29
# %bb.28:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 16(%rsp), %rdx
movq 24(%rsp), %rsi
movq $100, 152(%rsp)
movq $256, 144(%rsp) # imm = 0x100
movq $256, 136(%rsp) # imm = 0x100
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movq %rdx, 112(%rsp)
movq %rsi, 104(%rsp)
leaq 152(%rsp), %rax
movq %rax, 160(%rsp)
leaq 144(%rsp), %rax
movq %rax, 168(%rsp)
leaq 136(%rsp), %rax
movq %rax, 176(%rsp)
leaq 128(%rsp), %rax
movq %rax, 184(%rsp)
leaq 120(%rsp), %rax
movq %rax, 192(%rsp)
leaq 112(%rsp), %rax
movq %rax, 200(%rsp)
leaq 104(%rsp), %rax
movq %rax, 208(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z9Voronoi2DmmmPfS_PiS0_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_29:
callq hipPeekAtLastError
testl %eax, %eax
jne .LBB1_30
# %bb.31: # %_Z9gpuAssert10hipError_tPKcib.exit51
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_32
# %bb.33: # %_Z9gpuAssert10hipError_tPKcib.exit53
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB1_34
# %bb.35: # %_Z9gpuAssert10hipError_tPKcib.exit55
movq 8(%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
jne .LBB1_36
# %bb.37: # %_Z9gpuAssert10hipError_tPKcib.exit57
movq 48(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 160(%rsp), %rdi
callq hipEventElapsedTime
testl %eax, %eax
jne .LBB1_38
# %bb.39: # %_Z9gpuAssert10hipError_tPKcib.exit59
movss 160(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 24(%rsp), %rsi
movl $262144, %edx # imm = 0x40000
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_40
# %bb.41: # %_Z9gpuAssert10hipError_tPKcib.exit61
movl $.L.str.2, %edi
movl $.L.str.3, %esi
callq fopen
movq %rax, %rdi
callq fclose
movq 40(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_42
# %bb.43: # %_Z9gpuAssert10hipError_tPKcib.exit63
movq 32(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_44
# %bb.45: # %_Z9gpuAssert10hipError_tPKcib.exit65
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_46
# %bb.47: # %_Z9gpuAssert10hipError_tPKcib.exit67
movq 24(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_48
# %bb.49: # %_Z9gpuAssert10hipError_tPKcib.exit69
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 272
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $142, %r8d
jmp .LBB1_2
.LBB1_4:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $143, %r8d
jmp .LBB1_2
.LBB1_6:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $144, %r8d
jmp .LBB1_2
.LBB1_8:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $145, %r8d
jmp .LBB1_2
.LBB1_16:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $158, %r8d
jmp .LBB1_2
.LBB1_18:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $159, %r8d
jmp .LBB1_2
.LBB1_20:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $160, %r8d
jmp .LBB1_2
.LBB1_22:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $166, %r8d
jmp .LBB1_2
.LBB1_24:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $167, %r8d
jmp .LBB1_2
.LBB1_26:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $169, %r8d
jmp .LBB1_2
.LBB1_30:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $180, %r8d
jmp .LBB1_2
.LBB1_32:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $181, %r8d
jmp .LBB1_2
.LBB1_34:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $183, %r8d
jmp .LBB1_2
.LBB1_36:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $184, %r8d
jmp .LBB1_2
.LBB1_38:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $185, %r8d
jmp .LBB1_2
.LBB1_40:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $190, %r8d
jmp .LBB1_2
.LBB1_42:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $201, %r8d
jmp .LBB1_2
.LBB1_44:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $202, %r8d
jmp .LBB1_2
.LBB1_46:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $203, %r8d
jmp .LBB1_2
.LBB1_48:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $204, %r8d
.LBB1_2:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9Voronoi2DmmmPfS_PiS0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9Voronoi2DmmmPfS_PiS0_,@object # @_Z9Voronoi2DmmmPfS_PiS0_
.section .rodata,"a",@progbits
.globl _Z9Voronoi2DmmmPfS_PiS0_
.p2align 3, 0x0
_Z9Voronoi2DmmmPfS_PiS0_:
.quad _Z24__device_stub__Voronoi2DmmmPfS_PiS0_
.size _Z9Voronoi2DmmmPfS_PiS0_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/ggeo/Cuda/master/Voronoi/Voronoi2D.hip"
.size .L.str, 96
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\nGPU time for calling Voronoi: %f ms\n"
.size .L.str.1, 38
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Voronoi2D"
.size .L.str.2, 10
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "wb"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\nGPUassert: %s %s %d\n"
.size .L.str.4, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9Voronoi2DmmmPfS_PiS0_"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__Voronoi2DmmmPfS_PiS0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9Voronoi2DmmmPfS_PiS0_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // a simple code to understand the grid and block layout
// and thread numbering scheme
#include <cuda_runtime.h>
#include <stdio.h>
__global__ void checkIndex(void) {
printf("threadIdx:(%d, %d, %d) blockIdx:(%d, %d, %d) blockDim:(%d, %d, %d) "
"gridDim:(%d, %d, %d)\n", threadIdx.x, threadIdx.y, threadIdx.z,
blockIdx.x, blockIdx.y, blockIdx.z, blockDim.x, blockDim.y, blockDim.z,
gridDim.x,gridDim.y,gridDim.z);
}
__global__ void
vectorAdd(int *A, int numElements)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < numElements)
{
A[i] = A[i] * 2;
}
}
int main(int argc, char **argv) {
int nElem = 102173;
int *h_vect = (int *)malloc(nElem * sizeof(int));
int *d_vect = NULL;
for (int i = 0; i < nElem; ++i)
{
h_vect[i] = rand();
}
cudaMalloc((void **)&d_vect, nElem * sizeof(int));
int threadsPerBlock = 8388608;
int blocksPerGrid = (nElem+threadsPerBlock-1)/threadsPerBlock;
// check grid and block dimension from host side
//printf("grid.x %d grid.y %d grid.z %d\n",grid.x, grid.y, grid.z);
//printf("block.x %d block.y %d block.z %d\n",block.x, block.y, block.z);
cudaMemcpy(d_vect, h_vect, nElem * sizeof(int), cudaMemcpyHostToDevice);
vectorAdd<<<threadsPerBlock, blocksPerGrid>>>(d_vect, nElem);
cudaDeviceSynchronize();
cudaMemcpy(h_vect, d_vect, nElem * sizeof(int), cudaMemcpyDeviceToHost);
// check grid and block dimension from device side
//checkIndex <<<grid, block>>> ();
// reset device before you leave
cudaDeviceReset();
free(h_vect);
cudaFree(d_vect);
return(0);
} | code for sm_80
Function : _Z9vectorAddPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ SHF.L.U32 R5, R0, 0x1, RZ ; /* 0x0000000100057819 */
/* 0x004fca00000006ff */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10checkIndexv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R11, SR_CTAID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002500 */
/*0020*/ IADD3 R1, R1, -0x30, RZ ; /* 0xffffffd001017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0e7624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R18, c[0x0][0x10] ; /* 0x0000040000127a02 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R10, SR_TID.Z ; /* 0x00000000000a7919 */
/* 0x000e220000002300 */
/*0060*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x4] ; /* 0x00000100ff0f7624 */
/* 0x000fe200078e00ff */
/*0070*/ MOV R0, 0x8 ; /* 0x0000000800007802 */
/* 0x000fe20000000f00 */
/*0080*/ IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x8] ; /* 0x00000200ff107624 */
/* 0x000fe200078e00ff */
/*0090*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000e220000002200 */
/*00a0*/ IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff117624 */
/* 0x000fe200078e00ff */
/*00b0*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0002a20000000a00 */
/*00c0*/ IMAD.MOV.U32 R19, RZ, RZ, c[0x0][0x14] ; /* 0x00000500ff137624 */
/* 0x000fe200078e00ff */
/*00d0*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*00e0*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*00f0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x0] ; /* 0x01000000ff047624 */
/* 0x000fe200078e00ff */
/*0100*/ MOV R5, c[0x4][0x4] ; /* 0x0100010000057a02 */
/* 0x000fe20000000f00 */
/*0110*/ S2R R13, SR_CTAID.Z ; /* 0x00000000000d7919 */
/* 0x000ee40000002700 */
/*0120*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fc400000e06ff */
/*0130*/ S2R R12, SR_CTAID.Y ; /* 0x00000000000c7919 */
/* 0x000ee80000002600 */
/*0140*/ STL.128 [R1+0x20], R16 ; /* 0x0000201001007387 */
/* 0x0003e80000100c00 */
/*0150*/ STL.128 [R1], R8 ; /* 0x0000000801007387 */
/* 0x0013e80000100c00 */
/*0160*/ STL.128 [R1+0x10], R12 ; /* 0x0000100c01007387 */
/* 0x0083e40000100c00 */
/*0170*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x006fe40000000000 */
/*0180*/ MOV R11, 0x1f0 ; /* 0x000001f0000b7802 */
/* 0x000fe40000000f00 */
/*0190*/ MOV R20, 0x170 ; /* 0x0000017000147802 */
/* 0x000fc40000000f00 */
/*01a0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*01b0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*01c0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*01d0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*01e0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x000fea0003c00000 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // a simple code to understand the grid and block layout
// and thread numbering scheme
#include <cuda_runtime.h>
#include <stdio.h>
__global__ void checkIndex(void) {
printf("threadIdx:(%d, %d, %d) blockIdx:(%d, %d, %d) blockDim:(%d, %d, %d) "
"gridDim:(%d, %d, %d)\n", threadIdx.x, threadIdx.y, threadIdx.z,
blockIdx.x, blockIdx.y, blockIdx.z, blockDim.x, blockDim.y, blockDim.z,
gridDim.x,gridDim.y,gridDim.z);
}
__global__ void
vectorAdd(int *A, int numElements)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < numElements)
{
A[i] = A[i] * 2;
}
}
int main(int argc, char **argv) {
int nElem = 102173;
int *h_vect = (int *)malloc(nElem * sizeof(int));
int *d_vect = NULL;
for (int i = 0; i < nElem; ++i)
{
h_vect[i] = rand();
}
cudaMalloc((void **)&d_vect, nElem * sizeof(int));
int threadsPerBlock = 8388608;
int blocksPerGrid = (nElem+threadsPerBlock-1)/threadsPerBlock;
// check grid and block dimension from host side
//printf("grid.x %d grid.y %d grid.z %d\n",grid.x, grid.y, grid.z);
//printf("block.x %d block.y %d block.z %d\n",block.x, block.y, block.z);
cudaMemcpy(d_vect, h_vect, nElem * sizeof(int), cudaMemcpyHostToDevice);
vectorAdd<<<threadsPerBlock, blocksPerGrid>>>(d_vect, nElem);
cudaDeviceSynchronize();
cudaMemcpy(h_vect, d_vect, nElem * sizeof(int), cudaMemcpyDeviceToHost);
// check grid and block dimension from device side
//checkIndex <<<grid, block>>> ();
// reset device before you leave
cudaDeviceReset();
free(h_vect);
cudaFree(d_vect);
return(0);
} | .file "tmpxft_00141bdf_00000000-6_grid_debug2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10checkIndexvv
.type _Z29__device_stub__Z10checkIndexvv, @function
_Z29__device_stub__Z10checkIndexvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10checkIndexv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z10checkIndexvv, .-_Z29__device_stub__Z10checkIndexvv
.globl _Z10checkIndexv
.type _Z10checkIndexv, @function
_Z10checkIndexv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10checkIndexvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10checkIndexv, .-_Z10checkIndexv
.globl _Z29__device_stub__Z9vectorAddPiiPii
.type _Z29__device_stub__Z9vectorAddPiiPii, @function
_Z29__device_stub__Z9vectorAddPiiPii:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9vectorAddPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z29__device_stub__Z9vectorAddPiiPii, .-_Z29__device_stub__Z9vectorAddPiiPii
.globl _Z9vectorAddPii
.type _Z9vectorAddPii, @function
_Z9vectorAddPii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z9vectorAddPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z9vectorAddPii, .-_Z9vectorAddPii
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $408692, %edi
call malloc@PLT
movq %rax, %r12
movq $0, 8(%rsp)
movq %rax, %rbx
leaq 408692(%rax), %rbp
.L20:
call rand@PLT
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L20
leaq 8(%rsp), %rdi
movl $408692, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $408692, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $8388608, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $408692, %edx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
call cudaDeviceReset@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movl $102173, %esi
movq 8(%rsp), %rdi
call _Z29__device_stub__Z9vectorAddPiiPii
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9vectorAddPii"
.LC1:
.string "_Z10checkIndexv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9vectorAddPii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z10checkIndexv(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // a simple code to understand the grid and block layout
// and thread numbering scheme
#include <cuda_runtime.h>
#include <stdio.h>
__global__ void checkIndex(void) {
printf("threadIdx:(%d, %d, %d) blockIdx:(%d, %d, %d) blockDim:(%d, %d, %d) "
"gridDim:(%d, %d, %d)\n", threadIdx.x, threadIdx.y, threadIdx.z,
blockIdx.x, blockIdx.y, blockIdx.z, blockDim.x, blockDim.y, blockDim.z,
gridDim.x,gridDim.y,gridDim.z);
}
__global__ void
vectorAdd(int *A, int numElements)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < numElements)
{
A[i] = A[i] * 2;
}
}
int main(int argc, char **argv) {
int nElem = 102173;
int *h_vect = (int *)malloc(nElem * sizeof(int));
int *d_vect = NULL;
for (int i = 0; i < nElem; ++i)
{
h_vect[i] = rand();
}
cudaMalloc((void **)&d_vect, nElem * sizeof(int));
int threadsPerBlock = 8388608;
int blocksPerGrid = (nElem+threadsPerBlock-1)/threadsPerBlock;
// check grid and block dimension from host side
//printf("grid.x %d grid.y %d grid.z %d\n",grid.x, grid.y, grid.z);
//printf("block.x %d block.y %d block.z %d\n",block.x, block.y, block.z);
cudaMemcpy(d_vect, h_vect, nElem * sizeof(int), cudaMemcpyHostToDevice);
vectorAdd<<<threadsPerBlock, blocksPerGrid>>>(d_vect, nElem);
cudaDeviceSynchronize();
cudaMemcpy(h_vect, d_vect, nElem * sizeof(int), cudaMemcpyDeviceToHost);
// check grid and block dimension from device side
//checkIndex <<<grid, block>>> ();
// reset device before you leave
cudaDeviceReset();
free(h_vect);
cudaFree(d_vect);
return(0);
} | // a simple code to understand the grid and block layout
// and thread numbering scheme
#include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void checkIndex(void) {
printf("threadIdx:(%d, %d, %d) blockIdx:(%d, %d, %d) blockDim:(%d, %d, %d) "
"gridDim:(%d, %d, %d)\n", threadIdx.x, threadIdx.y, threadIdx.z,
blockIdx.x, blockIdx.y, blockIdx.z, blockDim.x, blockDim.y, blockDim.z,
gridDim.x,gridDim.y,gridDim.z);
}
__global__ void
vectorAdd(int *A, int numElements)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < numElements)
{
A[i] = A[i] * 2;
}
}
int main(int argc, char **argv) {
int nElem = 102173;
int *h_vect = (int *)malloc(nElem * sizeof(int));
int *d_vect = NULL;
for (int i = 0; i < nElem; ++i)
{
h_vect[i] = rand();
}
hipMalloc((void **)&d_vect, nElem * sizeof(int));
int threadsPerBlock = 8388608;
int blocksPerGrid = (nElem+threadsPerBlock-1)/threadsPerBlock;
// check grid and block dimension from host side
//printf("grid.x %d grid.y %d grid.z %d\n",grid.x, grid.y, grid.z);
//printf("block.x %d block.y %d block.z %d\n",block.x, block.y, block.z);
hipMemcpy(d_vect, h_vect, nElem * sizeof(int), hipMemcpyHostToDevice);
vectorAdd<<<threadsPerBlock, blocksPerGrid>>>(d_vect, nElem);
hipDeviceSynchronize();
hipMemcpy(h_vect, d_vect, nElem * sizeof(int), hipMemcpyDeviceToHost);
// check grid and block dimension from device side
//checkIndex <<<grid, block>>> ();
// reset device before you leave
hipDeviceReset();
free(h_vect);
hipFree(d_vect);
return(0);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // a simple code to understand the grid and block layout
// and thread numbering scheme
#include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void checkIndex(void) {
printf("threadIdx:(%d, %d, %d) blockIdx:(%d, %d, %d) blockDim:(%d, %d, %d) "
"gridDim:(%d, %d, %d)\n", threadIdx.x, threadIdx.y, threadIdx.z,
blockIdx.x, blockIdx.y, blockIdx.z, blockDim.x, blockDim.y, blockDim.z,
gridDim.x,gridDim.y,gridDim.z);
}
__global__ void
vectorAdd(int *A, int numElements)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < numElements)
{
A[i] = A[i] * 2;
}
}
int main(int argc, char **argv) {
int nElem = 102173;
int *h_vect = (int *)malloc(nElem * sizeof(int));
int *d_vect = NULL;
for (int i = 0; i < nElem; ++i)
{
h_vect[i] = rand();
}
hipMalloc((void **)&d_vect, nElem * sizeof(int));
int threadsPerBlock = 8388608;
int blocksPerGrid = (nElem+threadsPerBlock-1)/threadsPerBlock;
// check grid and block dimension from host side
//printf("grid.x %d grid.y %d grid.z %d\n",grid.x, grid.y, grid.z);
//printf("block.x %d block.y %d block.z %d\n",block.x, block.y, block.z);
hipMemcpy(d_vect, h_vect, nElem * sizeof(int), hipMemcpyHostToDevice);
vectorAdd<<<threadsPerBlock, blocksPerGrid>>>(d_vect, nElem);
hipDeviceSynchronize();
hipMemcpy(h_vect, d_vect, nElem * sizeof(int), hipMemcpyDeviceToHost);
// check grid and block dimension from device side
//checkIndex <<<grid, block>>> ();
// reset device before you leave
hipDeviceReset();
free(h_vect);
hipFree(d_vect);
return(0);
} | .text
.file "grid_debug2.hip"
.globl _Z25__device_stub__checkIndexv # -- Begin function _Z25__device_stub__checkIndexv
.p2align 4, 0x90
.type _Z25__device_stub__checkIndexv,@function
_Z25__device_stub__checkIndexv: # @_Z25__device_stub__checkIndexv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10checkIndexv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z25__device_stub__checkIndexv, .Lfunc_end0-_Z25__device_stub__checkIndexv
.cfi_endproc
# -- End function
.globl _Z24__device_stub__vectorAddPii # -- Begin function _Z24__device_stub__vectorAddPii
.p2align 4, 0x90
.type _Z24__device_stub__vectorAddPii,@function
_Z24__device_stub__vectorAddPii: # @_Z24__device_stub__vectorAddPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9vectorAddPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z24__device_stub__vectorAddPii, .Lfunc_end1-_Z24__device_stub__vectorAddPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $408692, %edi # imm = 0x63C74
callq malloc
movq %rax, %rbx
movq $0, 8(%rsp)
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
callq rand
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $102173, %r14 # imm = 0x18F1D
jne .LBB2_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $408692, %esi # imm = 0x63C74
callq hipMalloc
movq 8(%rsp), %rdi
movl $408692, %edx # imm = 0x63C74
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 8388607(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $102173, 20(%rsp) # imm = 0x18F1D
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9vectorAddPii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movl $408692, %edx # imm = 0x63C74
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipDeviceReset
movq %rbx, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10checkIndexv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9vectorAddPii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10checkIndexv,@object # @_Z10checkIndexv
.section .rodata,"a",@progbits
.globl _Z10checkIndexv
.p2align 3, 0x0
_Z10checkIndexv:
.quad _Z25__device_stub__checkIndexv
.size _Z10checkIndexv, 8
.type _Z9vectorAddPii,@object # @_Z9vectorAddPii
.globl _Z9vectorAddPii
.p2align 3, 0x0
_Z9vectorAddPii:
.quad _Z24__device_stub__vectorAddPii
.size _Z9vectorAddPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10checkIndexv"
.size .L__unnamed_1, 16
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9vectorAddPii"
.size .L__unnamed_2, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__checkIndexv
.addrsig_sym _Z24__device_stub__vectorAddPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10checkIndexv
.addrsig_sym _Z9vectorAddPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00141bdf_00000000-6_grid_debug2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10checkIndexvv
.type _Z29__device_stub__Z10checkIndexvv, @function
_Z29__device_stub__Z10checkIndexvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10checkIndexv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z10checkIndexvv, .-_Z29__device_stub__Z10checkIndexvv
.globl _Z10checkIndexv
.type _Z10checkIndexv, @function
_Z10checkIndexv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10checkIndexvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10checkIndexv, .-_Z10checkIndexv
.globl _Z29__device_stub__Z9vectorAddPiiPii
.type _Z29__device_stub__Z9vectorAddPiiPii, @function
_Z29__device_stub__Z9vectorAddPiiPii:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9vectorAddPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z29__device_stub__Z9vectorAddPiiPii, .-_Z29__device_stub__Z9vectorAddPiiPii
.globl _Z9vectorAddPii
.type _Z9vectorAddPii, @function
_Z9vectorAddPii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z9vectorAddPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z9vectorAddPii, .-_Z9vectorAddPii
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $408692, %edi
call malloc@PLT
movq %rax, %r12
movq $0, 8(%rsp)
movq %rax, %rbx
leaq 408692(%rax), %rbp
.L20:
call rand@PLT
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L20
leaq 8(%rsp), %rdi
movl $408692, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $408692, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $8388608, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $408692, %edx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
call cudaDeviceReset@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movl $102173, %esi
movq 8(%rsp), %rdi
call _Z29__device_stub__Z9vectorAddPiiPii
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9vectorAddPii"
.LC1:
.string "_Z10checkIndexv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9vectorAddPii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z10checkIndexv(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "grid_debug2.hip"
.globl _Z25__device_stub__checkIndexv # -- Begin function _Z25__device_stub__checkIndexv
.p2align 4, 0x90
.type _Z25__device_stub__checkIndexv,@function
_Z25__device_stub__checkIndexv: # @_Z25__device_stub__checkIndexv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10checkIndexv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z25__device_stub__checkIndexv, .Lfunc_end0-_Z25__device_stub__checkIndexv
.cfi_endproc
# -- End function
.globl _Z24__device_stub__vectorAddPii # -- Begin function _Z24__device_stub__vectorAddPii
.p2align 4, 0x90
.type _Z24__device_stub__vectorAddPii,@function
_Z24__device_stub__vectorAddPii: # @_Z24__device_stub__vectorAddPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9vectorAddPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z24__device_stub__vectorAddPii, .Lfunc_end1-_Z24__device_stub__vectorAddPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $408692, %edi # imm = 0x63C74
callq malloc
movq %rax, %rbx
movq $0, 8(%rsp)
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
callq rand
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $102173, %r14 # imm = 0x18F1D
jne .LBB2_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $408692, %esi # imm = 0x63C74
callq hipMalloc
movq 8(%rsp), %rdi
movl $408692, %edx # imm = 0x63C74
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 8388607(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $102173, 20(%rsp) # imm = 0x18F1D
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9vectorAddPii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movl $408692, %edx # imm = 0x63C74
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipDeviceReset
movq %rbx, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10checkIndexv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9vectorAddPii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10checkIndexv,@object # @_Z10checkIndexv
.section .rodata,"a",@progbits
.globl _Z10checkIndexv
.p2align 3, 0x0
_Z10checkIndexv:
.quad _Z25__device_stub__checkIndexv
.size _Z10checkIndexv, 8
.type _Z9vectorAddPii,@object # @_Z9vectorAddPii
.globl _Z9vectorAddPii
.p2align 3, 0x0
_Z9vectorAddPii:
.quad _Z24__device_stub__vectorAddPii
.size _Z9vectorAddPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10checkIndexv"
.size .L__unnamed_1, 16
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9vectorAddPii"
.size .L__unnamed_2, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__checkIndexv
.addrsig_sym _Z24__device_stub__vectorAddPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10checkIndexv
.addrsig_sym _Z9vectorAddPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#define INF 2147483647
extern "C" {
__global__ void init(int * tab, int len) {
for(int i = threadIdx.x + len*blockIdx.x; i < len*blockIdx.x + len; i += 1024) {
tab[i] = INF;
}
}
__global__ void oneReduction(int * tab, int len, int mod) {
__shared__ int begin, end;
__shared__ int tmp_T[1024];
if(threadIdx.x == 0) {
begin = blockIdx.x*len;
end = blockIdx.x*len + len;
}
__syncthreads();
if(blockIdx.x % mod < mod/2) {
for(int k = len/2; k >= 1024; k /= 2) {
for(int g = begin; g < end; g += 2*k) {
for(int j = g; j < g + k; j += 512) {
__syncthreads();
if(threadIdx.x < 512)
tmp_T[threadIdx.x] = tab[j + threadIdx.x];
else
tmp_T[threadIdx.x] = tab[j + threadIdx.x - 512 + k];
__syncthreads();
if(threadIdx.x < 512 && tmp_T[threadIdx.x] > tmp_T[threadIdx.x + 512]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
tmp_T[threadIdx.x + 512] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
}
__syncthreads();
if(threadIdx.x < 512)
tab[j + threadIdx.x] = tmp_T[threadIdx.x];
else
tab[j + threadIdx.x - 512 + k] = tmp_T[threadIdx.x];
}
}
}
for(int i = begin; i < begin+len; i += 1024) {
__syncthreads();
tmp_T[threadIdx.x] = tab[i + threadIdx.x];
__syncthreads();
for(int jump = 512; jump >= 1; jump /= 2) {
if(threadIdx.x % (jump*2) < jump && threadIdx.x + jump < 1024 && tmp_T[threadIdx.x] > tmp_T[threadIdx.x + jump]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + jump];
tmp_T[threadIdx.x + jump] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + jump];
}
__syncthreads();
}
tab[i + threadIdx.x] = tmp_T[threadIdx.x];
}
} else {
for(int k = len/2; k >= 1024; k /= 2) {
for(int g = begin; g < end; g += 2*k) {
for(int j = g; j < g + k; j += 512) {
__syncthreads();
if(threadIdx.x < 512)
tmp_T[threadIdx.x] = tab[j + threadIdx.x];
else
tmp_T[threadIdx.x] = tab[j + threadIdx.x - 512 + k];
__syncthreads();
if(threadIdx.x < 512 && tmp_T[threadIdx.x] < tmp_T[threadIdx.x + 512]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
tmp_T[threadIdx.x + 512] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
}
__syncthreads();
if(threadIdx.x < 512)
tab[j + threadIdx.x] = tmp_T[threadIdx.x];
else
tab[j + threadIdx.x - 512 + k] = tmp_T[threadIdx.x];
}
}
}
for(int i = begin; i < begin + len; i += 1024) {
__syncthreads();
tmp_T[threadIdx.x] = tab[i + threadIdx.x];
__syncthreads();
for(int jump = 512; jump >= 1; jump /= 2) {
if(threadIdx.x % (jump*2) < jump && threadIdx.x + jump < 1024 && tmp_T[threadIdx.x] < tmp_T[threadIdx.x + jump]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + jump];
tmp_T[threadIdx.x + jump] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + jump];
}
__syncthreads();
}
tab[i + threadIdx.x] = tmp_T[threadIdx.x];
}
}
}
__global__ void oneBlock(int * tab, int len) {
__shared__ int begin, end;
__shared__ int tmp_T[1024];
if(threadIdx.x == 0) {
begin = blockIdx.x*len;
end = blockIdx.x*len + len;
}
__syncthreads();
//first phase
for(int i = begin; i < end; i += 2048) {
tmp_T[threadIdx.x] = tab[i + threadIdx.x];
__syncthreads();
for(int bSize = 2; bSize <= 1024; bSize *= 2) {
for(int jump = bSize/2; jump >= 1; jump /= 2) {
if(threadIdx.x % (jump*2) < jump && threadIdx.x + jump < 1024 && (
( tmp_T[threadIdx.x] > tmp_T[threadIdx.x + jump] && threadIdx.x % (bSize*2) < bSize ) ||
( tmp_T[threadIdx.x] < tmp_T[threadIdx.x + jump] && threadIdx.x % (bSize*2) >= bSize ))) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + jump];
tmp_T[threadIdx.x + jump] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + jump];
}
__syncthreads();
}
}
tab[i + threadIdx.x] = tmp_T[threadIdx.x];
__syncthreads();
tmp_T[threadIdx.x] = tab[i + 1024 + threadIdx.x];
__syncthreads();
for(int bSize = 2; bSize <= 1024; bSize *= 2) {
for(int jump = bSize/2; jump >= 1; jump /= 2) {
if(threadIdx.x % (jump*2) < jump && threadIdx.x + jump < 1024 && (
( tmp_T[threadIdx.x] < tmp_T[threadIdx.x + jump] && threadIdx.x % (bSize*2) < bSize ) ||
( tmp_T[threadIdx.x] > tmp_T[threadIdx.x + jump] && threadIdx.x % (bSize*2) >= bSize ))) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + jump];
tmp_T[threadIdx.x + jump] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + jump];
}
__syncthreads();
}
}
tab[i + 1024 + threadIdx.x] = tmp_T[threadIdx.x];
__syncthreads();
}
// second phase
for(int task_size = 2048; task_size < len; task_size *= 2) {
for(int pos = begin; pos < end; pos += 2*task_size) {
for(int k = task_size/2; k >= 1024; k /= 2) {
for(int lilPos = pos; lilPos < pos + task_size; lilPos += 2*k) {
for(int i = lilPos; i < lilPos + k; i += 512) {
__syncthreads();
if(threadIdx.x < 512)
tmp_T[threadIdx.x] = tab[i + threadIdx.x];
else
tmp_T[threadIdx.x] = tab[i + threadIdx.x - 512 + k];
__syncthreads();
if(threadIdx.x < 512 && tmp_T[threadIdx.x] > tmp_T[threadIdx.x + 512]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
tmp_T[threadIdx.x + 512] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
}
__syncthreads();
if(threadIdx.x < 512)
tab[i + threadIdx.x] = tmp_T[threadIdx.x];
else
tab[i + threadIdx.x - 512 + k] = tmp_T[threadIdx.x];
}
}
}
for(int i = pos; i < pos + task_size; i += 1024) {
tmp_T[threadIdx.x] = tab[i + threadIdx.x];
for(int jump = 512; jump >= 1; jump /= 2) {
__syncthreads();
if(threadIdx.x % (jump*2) < jump && threadIdx.x + jump < 1024 && tmp_T[threadIdx.x] > tmp_T[threadIdx.x + jump]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + jump];
tmp_T[threadIdx.x + jump] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + jump];
}
__syncthreads();
}
tab[i + threadIdx.x] = tmp_T[threadIdx.x];
__syncthreads();
}
}
__syncthreads();
for(int pos = begin + task_size; pos < end; pos += 2*task_size) {
for(int k = task_size/2; k >= 1024; k /= 2) {
for(int lilPos = pos; lilPos < pos + task_size; lilPos += 2*k) {
for(int i = lilPos; i < lilPos + k; i += 512) {
__syncthreads();
if(threadIdx.x < 512)
tmp_T[threadIdx.x] = tab[i + threadIdx.x];
else
tmp_T[threadIdx.x] = tab[i + threadIdx.x - 512 + k];
__syncthreads();
if(threadIdx.x < 512 && tmp_T[threadIdx.x] < tmp_T[threadIdx.x + 512]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
tmp_T[threadIdx.x + 512] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
}
__syncthreads();
if(threadIdx.x < 512)
tab[i + threadIdx.x] = tmp_T[threadIdx.x];
else
tab[i + threadIdx.x - 512 + k] = tmp_T[threadIdx.x];
}
}
}
for(int i = pos; i < pos + task_size; i += 1024) {
tmp_T[threadIdx.x] = tab[i + threadIdx.x];
__syncthreads();
for(int jump = 512; jump >= 1; jump /= 2) {
__syncthreads();
if(threadIdx.x % (jump*2) < jump && threadIdx.x + jump < 1024 && tmp_T[threadIdx.x] < tmp_T[threadIdx.x + jump]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + jump];
tmp_T[threadIdx.x + jump] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + jump];
}
__syncthreads();
}
__syncthreads();
tab[i + threadIdx.x] = tmp_T[threadIdx.x];
__syncthreads();
}
}
}
}
__global__ void oneMove(int * tab, int dist, int pow, int blocksPerTask, int period) {
__shared__ int tmp_T[1024];
__shared__ int begin;
if(threadIdx.x == 0)
begin = (blockIdx.x/blocksPerTask)*dist*2 + (blockIdx.x%blocksPerTask)*512*pow;
__syncthreads();
if((blockIdx.x / period) % 2 == 0) {
for(int i = begin; i < begin + pow*512; i += 512) {
if(threadIdx.x < 512) tmp_T[threadIdx.x] = tab[i + threadIdx.x];
else tmp_T[threadIdx.x] = tab[i + threadIdx.x - 512 + dist];
__syncthreads();
if(threadIdx.x < 512 && tmp_T[threadIdx.x] > tmp_T[threadIdx.x + 512]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
tmp_T[threadIdx.x + 512] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
}
__syncthreads();
if(threadIdx.x < 512) tab[i + threadIdx.x] = tmp_T[threadIdx.x];
else tab[i + threadIdx.x - 512 + dist] = tmp_T[threadIdx.x];
__syncthreads();
}
} else {
for(int i = begin; i < begin + pow*512; i += 512) {
if(threadIdx.x < 512) tmp_T[threadIdx.x] = tab[i + threadIdx.x];
else tmp_T[threadIdx.x] = tab[i + threadIdx.x - 512 + dist];
__syncthreads();
if(threadIdx.x < 512 && tmp_T[threadIdx.x] < tmp_T[threadIdx.x + 512]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
tmp_T[threadIdx.x + 512] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
}
__syncthreads();
if(threadIdx.x < 512) tab[i + threadIdx.x] = tmp_T[threadIdx.x];
else tab[i + threadIdx.x - 512 + dist] = tmp_T[threadIdx.x];
__syncthreads();
}
}
}
} | .file "tmpxft_0013e018_00000000-6_bitonic.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z4initPiiPii
.type _Z24__device_stub__Z4initPiiPii, @function
_Z24__device_stub__Z4initPiiPii:
.LFB2081:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq init(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z24__device_stub__Z4initPiiPii, .-_Z24__device_stub__Z4initPiiPii
.globl init
.type init, @function
init:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z4initPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size init, .-init
.globl _Z34__device_stub__Z12oneReductionPiiiPiii
.type _Z34__device_stub__Z12oneReductionPiiiPiii, @function
_Z34__device_stub__Z12oneReductionPiiiPiii:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq oneReduction(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z34__device_stub__Z12oneReductionPiiiPiii, .-_Z34__device_stub__Z12oneReductionPiiiPiii
.globl oneReduction
.type oneReduction, @function
oneReduction:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z12oneReductionPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size oneReduction, .-oneReduction
.globl _Z28__device_stub__Z8oneBlockPiiPii
.type _Z28__device_stub__Z8oneBlockPiiPii, @function
_Z28__device_stub__Z8oneBlockPiiPii:
.LFB2085:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq oneBlock(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z28__device_stub__Z8oneBlockPiiPii, .-_Z28__device_stub__Z8oneBlockPiiPii
.globl oneBlock
.type oneBlock, @function
oneBlock:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z8oneBlockPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size oneBlock, .-oneBlock
.globl _Z30__device_stub__Z7oneMovePiiiiiPiiiii
.type _Z30__device_stub__Z7oneMovePiiiiiPiiiii, @function
_Z30__device_stub__Z7oneMovePiiiiiPiiiii:
.LFB2087:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq oneMove(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z30__device_stub__Z7oneMovePiiiiiPiiiii, .-_Z30__device_stub__Z7oneMovePiiiiiPiiiii
.globl oneMove
.type oneMove, @function
oneMove:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7oneMovePiiiiiPiiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size oneMove, .-oneMove
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "oneMove"
.LC1:
.string "oneBlock"
.LC2:
.string "oneReduction"
.LC3:
.string "init"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq oneMove(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq oneBlock(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq oneReduction(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq init(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#define INF 2147483647
extern "C" {
__global__ void init(int * tab, int len) {
for(int i = threadIdx.x + len*blockIdx.x; i < len*blockIdx.x + len; i += 1024) {
tab[i] = INF;
}
}
__global__ void oneReduction(int * tab, int len, int mod) {
__shared__ int begin, end;
__shared__ int tmp_T[1024];
if(threadIdx.x == 0) {
begin = blockIdx.x*len;
end = blockIdx.x*len + len;
}
__syncthreads();
if(blockIdx.x % mod < mod/2) {
for(int k = len/2; k >= 1024; k /= 2) {
for(int g = begin; g < end; g += 2*k) {
for(int j = g; j < g + k; j += 512) {
__syncthreads();
if(threadIdx.x < 512)
tmp_T[threadIdx.x] = tab[j + threadIdx.x];
else
tmp_T[threadIdx.x] = tab[j + threadIdx.x - 512 + k];
__syncthreads();
if(threadIdx.x < 512 && tmp_T[threadIdx.x] > tmp_T[threadIdx.x + 512]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
tmp_T[threadIdx.x + 512] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
}
__syncthreads();
if(threadIdx.x < 512)
tab[j + threadIdx.x] = tmp_T[threadIdx.x];
else
tab[j + threadIdx.x - 512 + k] = tmp_T[threadIdx.x];
}
}
}
for(int i = begin; i < begin+len; i += 1024) {
__syncthreads();
tmp_T[threadIdx.x] = tab[i + threadIdx.x];
__syncthreads();
for(int jump = 512; jump >= 1; jump /= 2) {
if(threadIdx.x % (jump*2) < jump && threadIdx.x + jump < 1024 && tmp_T[threadIdx.x] > tmp_T[threadIdx.x + jump]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + jump];
tmp_T[threadIdx.x + jump] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + jump];
}
__syncthreads();
}
tab[i + threadIdx.x] = tmp_T[threadIdx.x];
}
} else {
for(int k = len/2; k >= 1024; k /= 2) {
for(int g = begin; g < end; g += 2*k) {
for(int j = g; j < g + k; j += 512) {
__syncthreads();
if(threadIdx.x < 512)
tmp_T[threadIdx.x] = tab[j + threadIdx.x];
else
tmp_T[threadIdx.x] = tab[j + threadIdx.x - 512 + k];
__syncthreads();
if(threadIdx.x < 512 && tmp_T[threadIdx.x] < tmp_T[threadIdx.x + 512]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
tmp_T[threadIdx.x + 512] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
}
__syncthreads();
if(threadIdx.x < 512)
tab[j + threadIdx.x] = tmp_T[threadIdx.x];
else
tab[j + threadIdx.x - 512 + k] = tmp_T[threadIdx.x];
}
}
}
for(int i = begin; i < begin + len; i += 1024) {
__syncthreads();
tmp_T[threadIdx.x] = tab[i + threadIdx.x];
__syncthreads();
for(int jump = 512; jump >= 1; jump /= 2) {
if(threadIdx.x % (jump*2) < jump && threadIdx.x + jump < 1024 && tmp_T[threadIdx.x] < tmp_T[threadIdx.x + jump]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + jump];
tmp_T[threadIdx.x + jump] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + jump];
}
__syncthreads();
}
tab[i + threadIdx.x] = tmp_T[threadIdx.x];
}
}
}
__global__ void oneBlock(int * tab, int len) {
__shared__ int begin, end;
__shared__ int tmp_T[1024];
if(threadIdx.x == 0) {
begin = blockIdx.x*len;
end = blockIdx.x*len + len;
}
__syncthreads();
//first phase
for(int i = begin; i < end; i += 2048) {
tmp_T[threadIdx.x] = tab[i + threadIdx.x];
__syncthreads();
for(int bSize = 2; bSize <= 1024; bSize *= 2) {
for(int jump = bSize/2; jump >= 1; jump /= 2) {
if(threadIdx.x % (jump*2) < jump && threadIdx.x + jump < 1024 && (
( tmp_T[threadIdx.x] > tmp_T[threadIdx.x + jump] && threadIdx.x % (bSize*2) < bSize ) ||
( tmp_T[threadIdx.x] < tmp_T[threadIdx.x + jump] && threadIdx.x % (bSize*2) >= bSize ))) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + jump];
tmp_T[threadIdx.x + jump] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + jump];
}
__syncthreads();
}
}
tab[i + threadIdx.x] = tmp_T[threadIdx.x];
__syncthreads();
tmp_T[threadIdx.x] = tab[i + 1024 + threadIdx.x];
__syncthreads();
for(int bSize = 2; bSize <= 1024; bSize *= 2) {
for(int jump = bSize/2; jump >= 1; jump /= 2) {
if(threadIdx.x % (jump*2) < jump && threadIdx.x + jump < 1024 && (
( tmp_T[threadIdx.x] < tmp_T[threadIdx.x + jump] && threadIdx.x % (bSize*2) < bSize ) ||
( tmp_T[threadIdx.x] > tmp_T[threadIdx.x + jump] && threadIdx.x % (bSize*2) >= bSize ))) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + jump];
tmp_T[threadIdx.x + jump] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + jump];
}
__syncthreads();
}
}
tab[i + 1024 + threadIdx.x] = tmp_T[threadIdx.x];
__syncthreads();
}
// second phase
for(int task_size = 2048; task_size < len; task_size *= 2) {
for(int pos = begin; pos < end; pos += 2*task_size) {
for(int k = task_size/2; k >= 1024; k /= 2) {
for(int lilPos = pos; lilPos < pos + task_size; lilPos += 2*k) {
for(int i = lilPos; i < lilPos + k; i += 512) {
__syncthreads();
if(threadIdx.x < 512)
tmp_T[threadIdx.x] = tab[i + threadIdx.x];
else
tmp_T[threadIdx.x] = tab[i + threadIdx.x - 512 + k];
__syncthreads();
if(threadIdx.x < 512 && tmp_T[threadIdx.x] > tmp_T[threadIdx.x + 512]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
tmp_T[threadIdx.x + 512] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
}
__syncthreads();
if(threadIdx.x < 512)
tab[i + threadIdx.x] = tmp_T[threadIdx.x];
else
tab[i + threadIdx.x - 512 + k] = tmp_T[threadIdx.x];
}
}
}
for(int i = pos; i < pos + task_size; i += 1024) {
tmp_T[threadIdx.x] = tab[i + threadIdx.x];
for(int jump = 512; jump >= 1; jump /= 2) {
__syncthreads();
if(threadIdx.x % (jump*2) < jump && threadIdx.x + jump < 1024 && tmp_T[threadIdx.x] > tmp_T[threadIdx.x + jump]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + jump];
tmp_T[threadIdx.x + jump] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + jump];
}
__syncthreads();
}
tab[i + threadIdx.x] = tmp_T[threadIdx.x];
__syncthreads();
}
}
__syncthreads();
for(int pos = begin + task_size; pos < end; pos += 2*task_size) {
for(int k = task_size/2; k >= 1024; k /= 2) {
for(int lilPos = pos; lilPos < pos + task_size; lilPos += 2*k) {
for(int i = lilPos; i < lilPos + k; i += 512) {
__syncthreads();
if(threadIdx.x < 512)
tmp_T[threadIdx.x] = tab[i + threadIdx.x];
else
tmp_T[threadIdx.x] = tab[i + threadIdx.x - 512 + k];
__syncthreads();
if(threadIdx.x < 512 && tmp_T[threadIdx.x] < tmp_T[threadIdx.x + 512]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
tmp_T[threadIdx.x + 512] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
}
__syncthreads();
if(threadIdx.x < 512)
tab[i + threadIdx.x] = tmp_T[threadIdx.x];
else
tab[i + threadIdx.x - 512 + k] = tmp_T[threadIdx.x];
}
}
}
for(int i = pos; i < pos + task_size; i += 1024) {
tmp_T[threadIdx.x] = tab[i + threadIdx.x];
__syncthreads();
for(int jump = 512; jump >= 1; jump /= 2) {
__syncthreads();
if(threadIdx.x % (jump*2) < jump && threadIdx.x + jump < 1024 && tmp_T[threadIdx.x] < tmp_T[threadIdx.x + jump]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + jump];
tmp_T[threadIdx.x + jump] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + jump];
}
__syncthreads();
}
__syncthreads();
tab[i + threadIdx.x] = tmp_T[threadIdx.x];
__syncthreads();
}
}
}
}
__global__ void oneMove(int * tab, int dist, int pow, int blocksPerTask, int period) {
__shared__ int tmp_T[1024];
__shared__ int begin;
if(threadIdx.x == 0)
begin = (blockIdx.x/blocksPerTask)*dist*2 + (blockIdx.x%blocksPerTask)*512*pow;
__syncthreads();
if((blockIdx.x / period) % 2 == 0) {
for(int i = begin; i < begin + pow*512; i += 512) {
if(threadIdx.x < 512) tmp_T[threadIdx.x] = tab[i + threadIdx.x];
else tmp_T[threadIdx.x] = tab[i + threadIdx.x - 512 + dist];
__syncthreads();
if(threadIdx.x < 512 && tmp_T[threadIdx.x] > tmp_T[threadIdx.x + 512]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
tmp_T[threadIdx.x + 512] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
}
__syncthreads();
if(threadIdx.x < 512) tab[i + threadIdx.x] = tmp_T[threadIdx.x];
else tab[i + threadIdx.x - 512 + dist] = tmp_T[threadIdx.x];
__syncthreads();
}
} else {
for(int i = begin; i < begin + pow*512; i += 512) {
if(threadIdx.x < 512) tmp_T[threadIdx.x] = tab[i + threadIdx.x];
else tmp_T[threadIdx.x] = tab[i + threadIdx.x - 512 + dist];
__syncthreads();
if(threadIdx.x < 512 && tmp_T[threadIdx.x] < tmp_T[threadIdx.x + 512]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
tmp_T[threadIdx.x + 512] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
}
__syncthreads();
if(threadIdx.x < 512) tab[i + threadIdx.x] = tmp_T[threadIdx.x];
else tab[i + threadIdx.x - 512 + dist] = tmp_T[threadIdx.x];
__syncthreads();
}
}
}
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define INF 2147483647
extern "C" {
__global__ void init(int * tab, int len) {
for(int i = threadIdx.x + len*blockIdx.x; i < len*blockIdx.x + len; i += 1024) {
tab[i] = INF;
}
}
__global__ void oneReduction(int * tab, int len, int mod) {
__shared__ int begin, end;
__shared__ int tmp_T[1024];
if(threadIdx.x == 0) {
begin = blockIdx.x*len;
end = blockIdx.x*len + len;
}
__syncthreads();
if(blockIdx.x % mod < mod/2) {
for(int k = len/2; k >= 1024; k /= 2) {
for(int g = begin; g < end; g += 2*k) {
for(int j = g; j < g + k; j += 512) {
__syncthreads();
if(threadIdx.x < 512)
tmp_T[threadIdx.x] = tab[j + threadIdx.x];
else
tmp_T[threadIdx.x] = tab[j + threadIdx.x - 512 + k];
__syncthreads();
if(threadIdx.x < 512 && tmp_T[threadIdx.x] > tmp_T[threadIdx.x + 512]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
tmp_T[threadIdx.x + 512] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
}
__syncthreads();
if(threadIdx.x < 512)
tab[j + threadIdx.x] = tmp_T[threadIdx.x];
else
tab[j + threadIdx.x - 512 + k] = tmp_T[threadIdx.x];
}
}
}
for(int i = begin; i < begin+len; i += 1024) {
__syncthreads();
tmp_T[threadIdx.x] = tab[i + threadIdx.x];
__syncthreads();
for(int jump = 512; jump >= 1; jump /= 2) {
if(threadIdx.x % (jump*2) < jump && threadIdx.x + jump < 1024 && tmp_T[threadIdx.x] > tmp_T[threadIdx.x + jump]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + jump];
tmp_T[threadIdx.x + jump] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + jump];
}
__syncthreads();
}
tab[i + threadIdx.x] = tmp_T[threadIdx.x];
}
} else {
for(int k = len/2; k >= 1024; k /= 2) {
for(int g = begin; g < end; g += 2*k) {
for(int j = g; j < g + k; j += 512) {
__syncthreads();
if(threadIdx.x < 512)
tmp_T[threadIdx.x] = tab[j + threadIdx.x];
else
tmp_T[threadIdx.x] = tab[j + threadIdx.x - 512 + k];
__syncthreads();
if(threadIdx.x < 512 && tmp_T[threadIdx.x] < tmp_T[threadIdx.x + 512]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
tmp_T[threadIdx.x + 512] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
}
__syncthreads();
if(threadIdx.x < 512)
tab[j + threadIdx.x] = tmp_T[threadIdx.x];
else
tab[j + threadIdx.x - 512 + k] = tmp_T[threadIdx.x];
}
}
}
for(int i = begin; i < begin + len; i += 1024) {
__syncthreads();
tmp_T[threadIdx.x] = tab[i + threadIdx.x];
__syncthreads();
for(int jump = 512; jump >= 1; jump /= 2) {
if(threadIdx.x % (jump*2) < jump && threadIdx.x + jump < 1024 && tmp_T[threadIdx.x] < tmp_T[threadIdx.x + jump]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + jump];
tmp_T[threadIdx.x + jump] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + jump];
}
__syncthreads();
}
tab[i + threadIdx.x] = tmp_T[threadIdx.x];
}
}
}
__global__ void oneBlock(int * tab, int len) {
__shared__ int begin, end;
__shared__ int tmp_T[1024];
if(threadIdx.x == 0) {
begin = blockIdx.x*len;
end = blockIdx.x*len + len;
}
__syncthreads();
//first phase
for(int i = begin; i < end; i += 2048) {
tmp_T[threadIdx.x] = tab[i + threadIdx.x];
__syncthreads();
for(int bSize = 2; bSize <= 1024; bSize *= 2) {
for(int jump = bSize/2; jump >= 1; jump /= 2) {
if(threadIdx.x % (jump*2) < jump && threadIdx.x + jump < 1024 && (
( tmp_T[threadIdx.x] > tmp_T[threadIdx.x + jump] && threadIdx.x % (bSize*2) < bSize ) ||
( tmp_T[threadIdx.x] < tmp_T[threadIdx.x + jump] && threadIdx.x % (bSize*2) >= bSize ))) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + jump];
tmp_T[threadIdx.x + jump] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + jump];
}
__syncthreads();
}
}
tab[i + threadIdx.x] = tmp_T[threadIdx.x];
__syncthreads();
tmp_T[threadIdx.x] = tab[i + 1024 + threadIdx.x];
__syncthreads();
for(int bSize = 2; bSize <= 1024; bSize *= 2) {
for(int jump = bSize/2; jump >= 1; jump /= 2) {
if(threadIdx.x % (jump*2) < jump && threadIdx.x + jump < 1024 && (
( tmp_T[threadIdx.x] < tmp_T[threadIdx.x + jump] && threadIdx.x % (bSize*2) < bSize ) ||
( tmp_T[threadIdx.x] > tmp_T[threadIdx.x + jump] && threadIdx.x % (bSize*2) >= bSize ))) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + jump];
tmp_T[threadIdx.x + jump] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + jump];
}
__syncthreads();
}
}
tab[i + 1024 + threadIdx.x] = tmp_T[threadIdx.x];
__syncthreads();
}
// second phase
for(int task_size = 2048; task_size < len; task_size *= 2) {
for(int pos = begin; pos < end; pos += 2*task_size) {
for(int k = task_size/2; k >= 1024; k /= 2) {
for(int lilPos = pos; lilPos < pos + task_size; lilPos += 2*k) {
for(int i = lilPos; i < lilPos + k; i += 512) {
__syncthreads();
if(threadIdx.x < 512)
tmp_T[threadIdx.x] = tab[i + threadIdx.x];
else
tmp_T[threadIdx.x] = tab[i + threadIdx.x - 512 + k];
__syncthreads();
if(threadIdx.x < 512 && tmp_T[threadIdx.x] > tmp_T[threadIdx.x + 512]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
tmp_T[threadIdx.x + 512] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
}
__syncthreads();
if(threadIdx.x < 512)
tab[i + threadIdx.x] = tmp_T[threadIdx.x];
else
tab[i + threadIdx.x - 512 + k] = tmp_T[threadIdx.x];
}
}
}
for(int i = pos; i < pos + task_size; i += 1024) {
tmp_T[threadIdx.x] = tab[i + threadIdx.x];
for(int jump = 512; jump >= 1; jump /= 2) {
__syncthreads();
if(threadIdx.x % (jump*2) < jump && threadIdx.x + jump < 1024 && tmp_T[threadIdx.x] > tmp_T[threadIdx.x + jump]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + jump];
tmp_T[threadIdx.x + jump] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + jump];
}
__syncthreads();
}
tab[i + threadIdx.x] = tmp_T[threadIdx.x];
__syncthreads();
}
}
__syncthreads();
for(int pos = begin + task_size; pos < end; pos += 2*task_size) {
for(int k = task_size/2; k >= 1024; k /= 2) {
for(int lilPos = pos; lilPos < pos + task_size; lilPos += 2*k) {
for(int i = lilPos; i < lilPos + k; i += 512) {
__syncthreads();
if(threadIdx.x < 512)
tmp_T[threadIdx.x] = tab[i + threadIdx.x];
else
tmp_T[threadIdx.x] = tab[i + threadIdx.x - 512 + k];
__syncthreads();
if(threadIdx.x < 512 && tmp_T[threadIdx.x] < tmp_T[threadIdx.x + 512]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
tmp_T[threadIdx.x + 512] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
}
__syncthreads();
if(threadIdx.x < 512)
tab[i + threadIdx.x] = tmp_T[threadIdx.x];
else
tab[i + threadIdx.x - 512 + k] = tmp_T[threadIdx.x];
}
}
}
for(int i = pos; i < pos + task_size; i += 1024) {
tmp_T[threadIdx.x] = tab[i + threadIdx.x];
__syncthreads();
for(int jump = 512; jump >= 1; jump /= 2) {
__syncthreads();
if(threadIdx.x % (jump*2) < jump && threadIdx.x + jump < 1024 && tmp_T[threadIdx.x] < tmp_T[threadIdx.x + jump]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + jump];
tmp_T[threadIdx.x + jump] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + jump];
}
__syncthreads();
}
__syncthreads();
tab[i + threadIdx.x] = tmp_T[threadIdx.x];
__syncthreads();
}
}
}
}
__global__ void oneMove(int * tab, int dist, int pow, int blocksPerTask, int period) {
__shared__ int tmp_T[1024];
__shared__ int begin;
if(threadIdx.x == 0)
begin = (blockIdx.x/blocksPerTask)*dist*2 + (blockIdx.x%blocksPerTask)*512*pow;
__syncthreads();
if((blockIdx.x / period) % 2 == 0) {
for(int i = begin; i < begin + pow*512; i += 512) {
if(threadIdx.x < 512) tmp_T[threadIdx.x] = tab[i + threadIdx.x];
else tmp_T[threadIdx.x] = tab[i + threadIdx.x - 512 + dist];
__syncthreads();
if(threadIdx.x < 512 && tmp_T[threadIdx.x] > tmp_T[threadIdx.x + 512]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
tmp_T[threadIdx.x + 512] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
}
__syncthreads();
if(threadIdx.x < 512) tab[i + threadIdx.x] = tmp_T[threadIdx.x];
else tab[i + threadIdx.x - 512 + dist] = tmp_T[threadIdx.x];
__syncthreads();
}
} else {
for(int i = begin; i < begin + pow*512; i += 512) {
if(threadIdx.x < 512) tmp_T[threadIdx.x] = tab[i + threadIdx.x];
else tmp_T[threadIdx.x] = tab[i + threadIdx.x - 512 + dist];
__syncthreads();
if(threadIdx.x < 512 && tmp_T[threadIdx.x] < tmp_T[threadIdx.x + 512]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
tmp_T[threadIdx.x + 512] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
}
__syncthreads();
if(threadIdx.x < 512) tab[i + threadIdx.x] = tmp_T[threadIdx.x];
else tab[i + threadIdx.x - 512 + dist] = tmp_T[threadIdx.x];
__syncthreads();
}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define INF 2147483647
extern "C" {
__global__ void init(int * tab, int len) {
for(int i = threadIdx.x + len*blockIdx.x; i < len*blockIdx.x + len; i += 1024) {
tab[i] = INF;
}
}
__global__ void oneReduction(int * tab, int len, int mod) {
__shared__ int begin, end;
__shared__ int tmp_T[1024];
if(threadIdx.x == 0) {
begin = blockIdx.x*len;
end = blockIdx.x*len + len;
}
__syncthreads();
if(blockIdx.x % mod < mod/2) {
for(int k = len/2; k >= 1024; k /= 2) {
for(int g = begin; g < end; g += 2*k) {
for(int j = g; j < g + k; j += 512) {
__syncthreads();
if(threadIdx.x < 512)
tmp_T[threadIdx.x] = tab[j + threadIdx.x];
else
tmp_T[threadIdx.x] = tab[j + threadIdx.x - 512 + k];
__syncthreads();
if(threadIdx.x < 512 && tmp_T[threadIdx.x] > tmp_T[threadIdx.x + 512]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
tmp_T[threadIdx.x + 512] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
}
__syncthreads();
if(threadIdx.x < 512)
tab[j + threadIdx.x] = tmp_T[threadIdx.x];
else
tab[j + threadIdx.x - 512 + k] = tmp_T[threadIdx.x];
}
}
}
for(int i = begin; i < begin+len; i += 1024) {
__syncthreads();
tmp_T[threadIdx.x] = tab[i + threadIdx.x];
__syncthreads();
for(int jump = 512; jump >= 1; jump /= 2) {
if(threadIdx.x % (jump*2) < jump && threadIdx.x + jump < 1024 && tmp_T[threadIdx.x] > tmp_T[threadIdx.x + jump]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + jump];
tmp_T[threadIdx.x + jump] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + jump];
}
__syncthreads();
}
tab[i + threadIdx.x] = tmp_T[threadIdx.x];
}
} else {
for(int k = len/2; k >= 1024; k /= 2) {
for(int g = begin; g < end; g += 2*k) {
for(int j = g; j < g + k; j += 512) {
__syncthreads();
if(threadIdx.x < 512)
tmp_T[threadIdx.x] = tab[j + threadIdx.x];
else
tmp_T[threadIdx.x] = tab[j + threadIdx.x - 512 + k];
__syncthreads();
if(threadIdx.x < 512 && tmp_T[threadIdx.x] < tmp_T[threadIdx.x + 512]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
tmp_T[threadIdx.x + 512] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
}
__syncthreads();
if(threadIdx.x < 512)
tab[j + threadIdx.x] = tmp_T[threadIdx.x];
else
tab[j + threadIdx.x - 512 + k] = tmp_T[threadIdx.x];
}
}
}
for(int i = begin; i < begin + len; i += 1024) {
__syncthreads();
tmp_T[threadIdx.x] = tab[i + threadIdx.x];
__syncthreads();
for(int jump = 512; jump >= 1; jump /= 2) {
if(threadIdx.x % (jump*2) < jump && threadIdx.x + jump < 1024 && tmp_T[threadIdx.x] < tmp_T[threadIdx.x + jump]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + jump];
tmp_T[threadIdx.x + jump] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + jump];
}
__syncthreads();
}
tab[i + threadIdx.x] = tmp_T[threadIdx.x];
}
}
}
__global__ void oneBlock(int * tab, int len) {
__shared__ int begin, end;
__shared__ int tmp_T[1024];
if(threadIdx.x == 0) {
begin = blockIdx.x*len;
end = blockIdx.x*len + len;
}
__syncthreads();
//first phase
for(int i = begin; i < end; i += 2048) {
tmp_T[threadIdx.x] = tab[i + threadIdx.x];
__syncthreads();
for(int bSize = 2; bSize <= 1024; bSize *= 2) {
for(int jump = bSize/2; jump >= 1; jump /= 2) {
if(threadIdx.x % (jump*2) < jump && threadIdx.x + jump < 1024 && (
( tmp_T[threadIdx.x] > tmp_T[threadIdx.x + jump] && threadIdx.x % (bSize*2) < bSize ) ||
( tmp_T[threadIdx.x] < tmp_T[threadIdx.x + jump] && threadIdx.x % (bSize*2) >= bSize ))) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + jump];
tmp_T[threadIdx.x + jump] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + jump];
}
__syncthreads();
}
}
tab[i + threadIdx.x] = tmp_T[threadIdx.x];
__syncthreads();
tmp_T[threadIdx.x] = tab[i + 1024 + threadIdx.x];
__syncthreads();
for(int bSize = 2; bSize <= 1024; bSize *= 2) {
for(int jump = bSize/2; jump >= 1; jump /= 2) {
if(threadIdx.x % (jump*2) < jump && threadIdx.x + jump < 1024 && (
( tmp_T[threadIdx.x] < tmp_T[threadIdx.x + jump] && threadIdx.x % (bSize*2) < bSize ) ||
( tmp_T[threadIdx.x] > tmp_T[threadIdx.x + jump] && threadIdx.x % (bSize*2) >= bSize ))) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + jump];
tmp_T[threadIdx.x + jump] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + jump];
}
__syncthreads();
}
}
tab[i + 1024 + threadIdx.x] = tmp_T[threadIdx.x];
__syncthreads();
}
// second phase
for(int task_size = 2048; task_size < len; task_size *= 2) {
for(int pos = begin; pos < end; pos += 2*task_size) {
for(int k = task_size/2; k >= 1024; k /= 2) {
for(int lilPos = pos; lilPos < pos + task_size; lilPos += 2*k) {
for(int i = lilPos; i < lilPos + k; i += 512) {
__syncthreads();
if(threadIdx.x < 512)
tmp_T[threadIdx.x] = tab[i + threadIdx.x];
else
tmp_T[threadIdx.x] = tab[i + threadIdx.x - 512 + k];
__syncthreads();
if(threadIdx.x < 512 && tmp_T[threadIdx.x] > tmp_T[threadIdx.x + 512]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
tmp_T[threadIdx.x + 512] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
}
__syncthreads();
if(threadIdx.x < 512)
tab[i + threadIdx.x] = tmp_T[threadIdx.x];
else
tab[i + threadIdx.x - 512 + k] = tmp_T[threadIdx.x];
}
}
}
for(int i = pos; i < pos + task_size; i += 1024) {
tmp_T[threadIdx.x] = tab[i + threadIdx.x];
for(int jump = 512; jump >= 1; jump /= 2) {
__syncthreads();
if(threadIdx.x % (jump*2) < jump && threadIdx.x + jump < 1024 && tmp_T[threadIdx.x] > tmp_T[threadIdx.x + jump]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + jump];
tmp_T[threadIdx.x + jump] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + jump];
}
__syncthreads();
}
tab[i + threadIdx.x] = tmp_T[threadIdx.x];
__syncthreads();
}
}
__syncthreads();
for(int pos = begin + task_size; pos < end; pos += 2*task_size) {
for(int k = task_size/2; k >= 1024; k /= 2) {
for(int lilPos = pos; lilPos < pos + task_size; lilPos += 2*k) {
for(int i = lilPos; i < lilPos + k; i += 512) {
__syncthreads();
if(threadIdx.x < 512)
tmp_T[threadIdx.x] = tab[i + threadIdx.x];
else
tmp_T[threadIdx.x] = tab[i + threadIdx.x - 512 + k];
__syncthreads();
if(threadIdx.x < 512 && tmp_T[threadIdx.x] < tmp_T[threadIdx.x + 512]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
tmp_T[threadIdx.x + 512] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
}
__syncthreads();
if(threadIdx.x < 512)
tab[i + threadIdx.x] = tmp_T[threadIdx.x];
else
tab[i + threadIdx.x - 512 + k] = tmp_T[threadIdx.x];
}
}
}
for(int i = pos; i < pos + task_size; i += 1024) {
tmp_T[threadIdx.x] = tab[i + threadIdx.x];
__syncthreads();
for(int jump = 512; jump >= 1; jump /= 2) {
__syncthreads();
if(threadIdx.x % (jump*2) < jump && threadIdx.x + jump < 1024 && tmp_T[threadIdx.x] < tmp_T[threadIdx.x + jump]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + jump];
tmp_T[threadIdx.x + jump] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + jump];
}
__syncthreads();
}
__syncthreads();
tab[i + threadIdx.x] = tmp_T[threadIdx.x];
__syncthreads();
}
}
}
}
__global__ void oneMove(int * tab, int dist, int pow, int blocksPerTask, int period) {
__shared__ int tmp_T[1024];
__shared__ int begin;
if(threadIdx.x == 0)
begin = (blockIdx.x/blocksPerTask)*dist*2 + (blockIdx.x%blocksPerTask)*512*pow;
__syncthreads();
if((blockIdx.x / period) % 2 == 0) {
for(int i = begin; i < begin + pow*512; i += 512) {
if(threadIdx.x < 512) tmp_T[threadIdx.x] = tab[i + threadIdx.x];
else tmp_T[threadIdx.x] = tab[i + threadIdx.x - 512 + dist];
__syncthreads();
if(threadIdx.x < 512 && tmp_T[threadIdx.x] > tmp_T[threadIdx.x + 512]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
tmp_T[threadIdx.x + 512] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
}
__syncthreads();
if(threadIdx.x < 512) tab[i + threadIdx.x] = tmp_T[threadIdx.x];
else tab[i + threadIdx.x - 512 + dist] = tmp_T[threadIdx.x];
__syncthreads();
}
} else {
for(int i = begin; i < begin + pow*512; i += 512) {
if(threadIdx.x < 512) tmp_T[threadIdx.x] = tab[i + threadIdx.x];
else tmp_T[threadIdx.x] = tab[i + threadIdx.x - 512 + dist];
__syncthreads();
if(threadIdx.x < 512 && tmp_T[threadIdx.x] < tmp_T[threadIdx.x + 512]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
tmp_T[threadIdx.x + 512] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
}
__syncthreads();
if(threadIdx.x < 512) tab[i + threadIdx.x] = tmp_T[threadIdx.x];
else tab[i + threadIdx.x - 512 + dist] = tmp_T[threadIdx.x];
__syncthreads();
}
}
}
} | .text
.file "bitonic.hip"
.globl __device_stub__init # -- Begin function __device_stub__init
.p2align 4, 0x90
.type __device_stub__init,@function
__device_stub__init: # @__device_stub__init
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $init, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size __device_stub__init, .Lfunc_end0-__device_stub__init
.cfi_endproc
# -- End function
.globl __device_stub__oneReduction # -- Begin function __device_stub__oneReduction
.p2align 4, 0x90
.type __device_stub__oneReduction,@function
__device_stub__oneReduction: # @__device_stub__oneReduction
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $oneReduction, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size __device_stub__oneReduction, .Lfunc_end1-__device_stub__oneReduction
.cfi_endproc
# -- End function
.globl __device_stub__oneBlock # -- Begin function __device_stub__oneBlock
.p2align 4, 0x90
.type __device_stub__oneBlock,@function
__device_stub__oneBlock: # @__device_stub__oneBlock
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $oneBlock, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size __device_stub__oneBlock, .Lfunc_end2-__device_stub__oneBlock
.cfi_endproc
# -- End function
.globl __device_stub__oneMove # -- Begin function __device_stub__oneMove
.p2align 4, 0x90
.type __device_stub__oneMove,@function
__device_stub__oneMove: # @__device_stub__oneMove
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $oneMove, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size __device_stub__oneMove, .Lfunc_end3-__device_stub__oneMove
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $init, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $oneReduction, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $oneBlock, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $oneMove, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type init,@object # @init
.section .rodata,"a",@progbits
.globl init
.p2align 3, 0x0
init:
.quad __device_stub__init
.size init, 8
.type oneReduction,@object # @oneReduction
.globl oneReduction
.p2align 3, 0x0
oneReduction:
.quad __device_stub__oneReduction
.size oneReduction, 8
.type oneBlock,@object # @oneBlock
.globl oneBlock
.p2align 3, 0x0
oneBlock:
.quad __device_stub__oneBlock
.size oneBlock, 8
.type oneMove,@object # @oneMove
.globl oneMove
.p2align 3, 0x0
oneMove:
.quad __device_stub__oneMove
.size oneMove, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "init"
.size .L__unnamed_1, 5
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "oneReduction"
.size .L__unnamed_2, 13
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "oneBlock"
.size .L__unnamed_3, 9
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "oneMove"
.size .L__unnamed_4, 8
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__init
.addrsig_sym __device_stub__oneReduction
.addrsig_sym __device_stub__oneBlock
.addrsig_sym __device_stub__oneMove
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym init
.addrsig_sym oneReduction
.addrsig_sym oneBlock
.addrsig_sym oneMove
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013e018_00000000-6_bitonic.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z4initPiiPii
.type _Z24__device_stub__Z4initPiiPii, @function
_Z24__device_stub__Z4initPiiPii:
.LFB2081:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq init(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z24__device_stub__Z4initPiiPii, .-_Z24__device_stub__Z4initPiiPii
.globl init
.type init, @function
init:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z4initPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size init, .-init
.globl _Z34__device_stub__Z12oneReductionPiiiPiii
.type _Z34__device_stub__Z12oneReductionPiiiPiii, @function
_Z34__device_stub__Z12oneReductionPiiiPiii:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq oneReduction(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z34__device_stub__Z12oneReductionPiiiPiii, .-_Z34__device_stub__Z12oneReductionPiiiPiii
.globl oneReduction
.type oneReduction, @function
oneReduction:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z12oneReductionPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size oneReduction, .-oneReduction
.globl _Z28__device_stub__Z8oneBlockPiiPii
.type _Z28__device_stub__Z8oneBlockPiiPii, @function
_Z28__device_stub__Z8oneBlockPiiPii:
.LFB2085:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq oneBlock(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z28__device_stub__Z8oneBlockPiiPii, .-_Z28__device_stub__Z8oneBlockPiiPii
.globl oneBlock
.type oneBlock, @function
oneBlock:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z8oneBlockPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size oneBlock, .-oneBlock
.globl _Z30__device_stub__Z7oneMovePiiiiiPiiiii
.type _Z30__device_stub__Z7oneMovePiiiiiPiiiii, @function
_Z30__device_stub__Z7oneMovePiiiiiPiiiii:
.LFB2087:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq oneMove(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z30__device_stub__Z7oneMovePiiiiiPiiiii, .-_Z30__device_stub__Z7oneMovePiiiiiPiiiii
.globl oneMove
.type oneMove, @function
oneMove:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7oneMovePiiiiiPiiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size oneMove, .-oneMove
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "oneMove"
.LC1:
.string "oneBlock"
.LC2:
.string "oneReduction"
.LC3:
.string "init"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq oneMove(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq oneBlock(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq oneReduction(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq init(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "bitonic.hip"
.globl __device_stub__init # -- Begin function __device_stub__init
.p2align 4, 0x90
.type __device_stub__init,@function
__device_stub__init: # @__device_stub__init
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $init, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size __device_stub__init, .Lfunc_end0-__device_stub__init
.cfi_endproc
# -- End function
.globl __device_stub__oneReduction # -- Begin function __device_stub__oneReduction
.p2align 4, 0x90
.type __device_stub__oneReduction,@function
__device_stub__oneReduction: # @__device_stub__oneReduction
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $oneReduction, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size __device_stub__oneReduction, .Lfunc_end1-__device_stub__oneReduction
.cfi_endproc
# -- End function
.globl __device_stub__oneBlock # -- Begin function __device_stub__oneBlock
.p2align 4, 0x90
.type __device_stub__oneBlock,@function
__device_stub__oneBlock: # @__device_stub__oneBlock
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $oneBlock, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size __device_stub__oneBlock, .Lfunc_end2-__device_stub__oneBlock
.cfi_endproc
# -- End function
.globl __device_stub__oneMove # -- Begin function __device_stub__oneMove
.p2align 4, 0x90
.type __device_stub__oneMove,@function
__device_stub__oneMove: # @__device_stub__oneMove
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $oneMove, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size __device_stub__oneMove, .Lfunc_end3-__device_stub__oneMove
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $init, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $oneReduction, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $oneBlock, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $oneMove, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type init,@object # @init
.section .rodata,"a",@progbits
.globl init
.p2align 3, 0x0
init:
.quad __device_stub__init
.size init, 8
.type oneReduction,@object # @oneReduction
.globl oneReduction
.p2align 3, 0x0
oneReduction:
.quad __device_stub__oneReduction
.size oneReduction, 8
.type oneBlock,@object # @oneBlock
.globl oneBlock
.p2align 3, 0x0
oneBlock:
.quad __device_stub__oneBlock
.size oneBlock, 8
.type oneMove,@object # @oneMove
.globl oneMove
.p2align 3, 0x0
oneMove:
.quad __device_stub__oneMove
.size oneMove, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "init"
.size .L__unnamed_1, 5
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "oneReduction"
.size .L__unnamed_2, 13
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "oneBlock"
.size .L__unnamed_3, 9
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "oneMove"
.size .L__unnamed_4, 8
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__init
.addrsig_sym __device_stub__oneReduction
.addrsig_sym __device_stub__oneBlock
.addrsig_sym __device_stub__oneMove
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym init
.addrsig_sym oneReduction
.addrsig_sym oneBlock
.addrsig_sym oneMove
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__global__ void multiplyNumbersByAScalar(float numbers[], float scalar) {
int x = blockIdx.x;
numbers[x] = numbers[x] * scalar;
}
int main(int argc, char** args)
{
float numbersInSystemMemory[] = { 0, 1, 2 , 3 , 4 , 5 , 6 ,7 ,8 , 9};
float* numbersInDeviceMemory;
cudaMalloc( (void**)&numbersInDeviceMemory, sizeof(float) * 10);
cudaMemcpy( numbersInDeviceMemory, numbersInSystemMemory, sizeof(float) * 10, cudaMemcpyHostToDevice );
multiplyNumbersByAScalar<<<10,1>>>(numbersInDeviceMemory, 2.0f);
cudaMemcpy( numbersInSystemMemory, numbersInDeviceMemory, sizeof(float) * 10, cudaMemcpyDeviceToHost );
cudaFree( numbersInDeviceMemory );
for(int x = 0; x < 10 ; x++){
printf("%f ", numbersInSystemMemory[x]);
}
return 1;
} | code for sm_80
Function : _Z24multiplyNumbersByAScalarPff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x001fca00078e0203 */
/*0050*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0060*/ FMUL R5, R0, c[0x0][0x168] ; /* 0x00005a0000057a20 */
/* 0x004fca0000400000 */
/*0070*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__ void multiplyNumbersByAScalar(float numbers[], float scalar) {
int x = blockIdx.x;
numbers[x] = numbers[x] * scalar;
}
int main(int argc, char** args)
{
float numbersInSystemMemory[] = { 0, 1, 2 , 3 , 4 , 5 , 6 ,7 ,8 , 9};
float* numbersInDeviceMemory;
cudaMalloc( (void**)&numbersInDeviceMemory, sizeof(float) * 10);
cudaMemcpy( numbersInDeviceMemory, numbersInSystemMemory, sizeof(float) * 10, cudaMemcpyHostToDevice );
multiplyNumbersByAScalar<<<10,1>>>(numbersInDeviceMemory, 2.0f);
cudaMemcpy( numbersInSystemMemory, numbersInDeviceMemory, sizeof(float) * 10, cudaMemcpyDeviceToHost );
cudaFree( numbersInDeviceMemory );
for(int x = 0; x < 10 ; x++){
printf("%f ", numbersInSystemMemory[x]);
}
return 1;
} | .file "tmpxft_0012b8a5_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z24multiplyNumbersByAScalarPffPff
.type _Z45__device_stub__Z24multiplyNumbersByAScalarPffPff, @function
_Z45__device_stub__Z24multiplyNumbersByAScalarPffPff:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z24multiplyNumbersByAScalarPff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z45__device_stub__Z24multiplyNumbersByAScalarPffPff, .-_Z45__device_stub__Z24multiplyNumbersByAScalarPffPff
.globl _Z24multiplyNumbersByAScalarPff
.type _Z24multiplyNumbersByAScalarPff, @function
_Z24multiplyNumbersByAScalarPff:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z24multiplyNumbersByAScalarPffPff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z24multiplyNumbersByAScalarPff, .-_Z24multiplyNumbersByAScalarPff
.section .rodata.str1.1,"aMS",@progbits,1
.LC10:
.string "%f "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $0x00000000, 32(%rsp)
movl $0x3f800000, 36(%rsp)
movl $0x40000000, 40(%rsp)
movl $0x40400000, 44(%rsp)
movl $0x40800000, 48(%rsp)
movl $0x40a00000, 52(%rsp)
movl $0x40c00000, 56(%rsp)
movl $0x40e00000, 60(%rsp)
movl $0x41000000, 64(%rsp)
movl $0x41100000, 68(%rsp)
movq %rsp, %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $10, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
leaq 32(%rsp), %rbx
movl $2, %ecx
movl $40, %edx
movq (%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
leaq 72(%rsp), %r12
leaq .LC10(%rip), %rbp
.L13:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L13
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $1, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movss .LC2(%rip), %xmm0
movq (%rsp), %rdi
call _Z45__device_stub__Z24multiplyNumbersByAScalarPffPff
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC11:
.string "_Z24multiplyNumbersByAScalarPff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z24multiplyNumbersByAScalarPff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__ void multiplyNumbersByAScalar(float numbers[], float scalar) {
int x = blockIdx.x;
numbers[x] = numbers[x] * scalar;
}
int main(int argc, char** args)
{
float numbersInSystemMemory[] = { 0, 1, 2 , 3 , 4 , 5 , 6 ,7 ,8 , 9};
float* numbersInDeviceMemory;
cudaMalloc( (void**)&numbersInDeviceMemory, sizeof(float) * 10);
cudaMemcpy( numbersInDeviceMemory, numbersInSystemMemory, sizeof(float) * 10, cudaMemcpyHostToDevice );
multiplyNumbersByAScalar<<<10,1>>>(numbersInDeviceMemory, 2.0f);
cudaMemcpy( numbersInSystemMemory, numbersInDeviceMemory, sizeof(float) * 10, cudaMemcpyDeviceToHost );
cudaFree( numbersInDeviceMemory );
for(int x = 0; x < 10 ; x++){
printf("%f ", numbersInSystemMemory[x]);
}
return 1;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void multiplyNumbersByAScalar(float numbers[], float scalar) {
int x = blockIdx.x;
numbers[x] = numbers[x] * scalar;
}
int main(int argc, char** args)
{
float numbersInSystemMemory[] = { 0, 1, 2 , 3 , 4 , 5 , 6 ,7 ,8 , 9};
float* numbersInDeviceMemory;
hipMalloc( (void**)&numbersInDeviceMemory, sizeof(float) * 10);
hipMemcpy( numbersInDeviceMemory, numbersInSystemMemory, sizeof(float) * 10, hipMemcpyHostToDevice );
multiplyNumbersByAScalar<<<10,1>>>(numbersInDeviceMemory, 2.0f);
hipMemcpy( numbersInSystemMemory, numbersInDeviceMemory, sizeof(float) * 10, hipMemcpyDeviceToHost );
hipFree( numbersInDeviceMemory );
for(int x = 0; x < 10 ; x++){
printf("%f ", numbersInSystemMemory[x]);
}
return 1;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void multiplyNumbersByAScalar(float numbers[], float scalar) {
int x = blockIdx.x;
numbers[x] = numbers[x] * scalar;
}
int main(int argc, char** args)
{
float numbersInSystemMemory[] = { 0, 1, 2 , 3 , 4 , 5 , 6 ,7 ,8 , 9};
float* numbersInDeviceMemory;
hipMalloc( (void**)&numbersInDeviceMemory, sizeof(float) * 10);
hipMemcpy( numbersInDeviceMemory, numbersInSystemMemory, sizeof(float) * 10, hipMemcpyHostToDevice );
multiplyNumbersByAScalar<<<10,1>>>(numbersInDeviceMemory, 2.0f);
hipMemcpy( numbersInSystemMemory, numbersInDeviceMemory, sizeof(float) * 10, hipMemcpyDeviceToHost );
hipFree( numbersInDeviceMemory );
for(int x = 0; x < 10 ; x++){
printf("%f ", numbersInSystemMemory[x]);
}
return 1;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24multiplyNumbersByAScalarPff
.globl _Z24multiplyNumbersByAScalarPff
.p2align 8
.type _Z24multiplyNumbersByAScalarPff,@function
_Z24multiplyNumbersByAScalarPff:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x8
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
v_mov_b32_e32 v0, 0
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s4, s2
s_addc_u32 s1, s5, s3
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mul_f32_e64 v1, s2, s6
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24multiplyNumbersByAScalarPff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24multiplyNumbersByAScalarPff, .Lfunc_end0-_Z24multiplyNumbersByAScalarPff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24multiplyNumbersByAScalarPff
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z24multiplyNumbersByAScalarPff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void multiplyNumbersByAScalar(float numbers[], float scalar) {
int x = blockIdx.x;
numbers[x] = numbers[x] * scalar;
}
int main(int argc, char** args)
{
float numbersInSystemMemory[] = { 0, 1, 2 , 3 , 4 , 5 , 6 ,7 ,8 , 9};
float* numbersInDeviceMemory;
hipMalloc( (void**)&numbersInDeviceMemory, sizeof(float) * 10);
hipMemcpy( numbersInDeviceMemory, numbersInSystemMemory, sizeof(float) * 10, hipMemcpyHostToDevice );
multiplyNumbersByAScalar<<<10,1>>>(numbersInDeviceMemory, 2.0f);
hipMemcpy( numbersInSystemMemory, numbersInDeviceMemory, sizeof(float) * 10, hipMemcpyDeviceToHost );
hipFree( numbersInDeviceMemory );
for(int x = 0; x < 10 ; x++){
printf("%f ", numbersInSystemMemory[x]);
}
return 1;
} | .text
.file "main.hip"
.globl _Z39__device_stub__multiplyNumbersByAScalarPff # -- Begin function _Z39__device_stub__multiplyNumbersByAScalarPff
.p2align 4, 0x90
.type _Z39__device_stub__multiplyNumbersByAScalarPff,@function
_Z39__device_stub__multiplyNumbersByAScalarPff: # @_Z39__device_stub__multiplyNumbersByAScalarPff
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movss %xmm0, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z24multiplyNumbersByAScalarPff, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z39__device_stub__multiplyNumbersByAScalarPff, .Lfunc_end0-_Z39__device_stub__multiplyNumbersByAScalarPff
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x00000000 # float 0
.long 0x3f800000 # float 1
.long 0x40000000 # float 2
.long 0x40400000 # float 3
.LCPI1_1:
.long 0x40800000 # float 4
.long 0x40a00000 # float 5
.long 0x40c00000 # float 6
.long 0x40e00000 # float 7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $144, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -16
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [0.0E+0,1.0E+0,2.0E+0,3.0E+0]
movaps %xmm0, 96(%rsp)
movaps .LCPI1_1(%rip), %xmm0 # xmm0 = [4.0E+0,5.0E+0,6.0E+0,7.0E+0]
movaps %xmm0, 112(%rsp)
movabsq $4688247213183205376, %rax # imm = 0x4110000041000000
movq %rax, 128(%rsp)
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 96(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 9(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $1073741824, 20(%rsp) # imm = 0x40000000
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z24multiplyNumbersByAScalarPff, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
leaq 96(%rsp), %rdi
movl $40, %edx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movss 96(%rsp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %rbx
cmpq $10, %rbx
jne .LBB1_3
# %bb.4:
movl $1, %eax
addq $144, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24multiplyNumbersByAScalarPff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24multiplyNumbersByAScalarPff,@object # @_Z24multiplyNumbersByAScalarPff
.section .rodata,"a",@progbits
.globl _Z24multiplyNumbersByAScalarPff
.p2align 3, 0x0
_Z24multiplyNumbersByAScalarPff:
.quad _Z39__device_stub__multiplyNumbersByAScalarPff
.size _Z24multiplyNumbersByAScalarPff, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z24multiplyNumbersByAScalarPff"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__multiplyNumbersByAScalarPff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24multiplyNumbersByAScalarPff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z24multiplyNumbersByAScalarPff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x001fca00078e0203 */
/*0050*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0060*/ FMUL R5, R0, c[0x0][0x168] ; /* 0x00005a0000057a20 */
/* 0x004fca0000400000 */
/*0070*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24multiplyNumbersByAScalarPff
.globl _Z24multiplyNumbersByAScalarPff
.p2align 8
.type _Z24multiplyNumbersByAScalarPff,@function
_Z24multiplyNumbersByAScalarPff:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x8
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
v_mov_b32_e32 v0, 0
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s4, s2
s_addc_u32 s1, s5, s3
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mul_f32_e64 v1, s2, s6
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24multiplyNumbersByAScalarPff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24multiplyNumbersByAScalarPff, .Lfunc_end0-_Z24multiplyNumbersByAScalarPff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24multiplyNumbersByAScalarPff
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z24multiplyNumbersByAScalarPff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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