system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cstdio>
#include <cstdlib>
#include <math.h>
#include <time.h>
#define MINVAL 0.00
#define MAXVAL 10.0
#define TOL 1e-5
#define NUM_THREADS 16
double CPS = 2.9e9;
int LEN; // to be defined via cmd args
//////////////////////////// CUDA RELATED ////////////////////////////////////
// Assertion to check for errors
#define CUDA_SAFE_CALL(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"CUDA_SAFE_CALL: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__ void MMM_kernel(float* A, float* B, float* dst, int len)
{
__shared__ float Ms [NUM_THREADS][NUM_THREADS];
__shared__ float Ns [NUM_THREADS][NUM_THREADS];
int bx, by, tx, ty, row, col;
bx = blockIdx.x;
by = blockIdx.y;
tx = threadIdx.x;
ty = threadIdx.y;
row = by * NUM_THREADS + ty;
col = bx * NUM_THREADS + tx;
float partial = 0;
for(int k = 0; k < len/NUM_THREADS; k++)
{
Ms[ty][tx] = A[row * len + (k * NUM_THREADS + tx)];
Ns[ty][tx] = B[col + (k * NUM_THREADS + ty) * len];
__syncthreads();
for(int r = 0; r < NUM_THREADS; r++)
partial += Ms[ty][r] * Ns[r][tx];
__syncthreads();
}
dst[row * len + col] = partial;
}
////////////////////////////// MATRIX /////////////////////////////////////////
float* matrix_create(int len);
int matrix_init(float* mat, int len);
int matrix_zero(float* mat, int len);
int matrix_copy(float* src, float* dst, int len);
void MMM_CPU(float* A, float* B, float* dst, int len);
///////////////// Time related //////////////////////////////
//rdtsc related
typedef union {
unsigned long long int64;
struct {unsigned int lo, hi;} int32;
} mcps_tctr;
#define MCPS_RDTSC(cpu_c) __asm__ __volatile__ ("rdtsc" : \
"=a" ((cpu_c).int32.lo), "=d"((cpu_c).int32.hi))
int clock_gettime(clockid_t clk_id, struct timespec *tp);
struct timespec diff(struct timespec start, struct timespec end);
double ts_ms(struct timespec ts);
struct timespec ts_diff(struct timespec start, struct timespec end);
double measure_cps(void);
////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////
int main(int argc, char *argv[])
{
if(argc != 2)
{
printf("\nPlease pass a length in.\n");
return 0;
}
LEN = strtol(argv[1], NULL, 10);
if(LEN <= 0)
{
printf("\nLength must be greater than zero\n");
return 0;
}
int size = LEN * LEN * sizeof(float);
int NUM_BLOCKS = LEN / NUM_THREADS;
if(LEN % NUM_THREADS != 0) // die if not a good fit
{
printf("\nOdd Numbr of blocks\n");
return 0;
}
// CUDA Timing
cudaEvent_t start_full, start_mmm, stop_full, stop_mmm;
float d_time_full, d_time_mmm;
// CPU Timing
struct timespec time1, time2;
double h_time;
// CPU set up
float *h_A, *h_B, *h_dst_gpu, *h_dst_cpu, *d_A, *d_B, *d_dst;
measure_cps();
h_A = matrix_create(LEN);
if(!h_A) return 0;
if(!matrix_init(h_A, LEN)) return 0;
h_B = matrix_create(LEN);
if(!h_B) return 0;
if(!matrix_init(h_B, LEN)) return 0;
h_dst_cpu = matrix_create(LEN); // cpu result
if(!h_dst_cpu) return 0;
if(!matrix_zero(h_dst_cpu, LEN)) return 0;
h_dst_gpu = matrix_create(LEN); // gpu result
if(!h_dst_gpu) return 0;
if(!matrix_zero(h_dst_gpu, LEN)) return 0;
// GPU Set up
d_A = NULL;
d_B = NULL;
d_dst = NULL;
CUDA_SAFE_CALL(cudaSetDevice(0));
CUDA_SAFE_CALL(cudaMalloc((void**)&d_A, size));
CUDA_SAFE_CALL(cudaMalloc((void**)&d_B, size));
CUDA_SAFE_CALL(cudaMalloc((void**)&d_dst, size));
cudaEventCreate(&start_full);
cudaEventCreate(&start_mmm);
cudaEventCreate(&stop_full);
cudaEventCreate(&stop_mmm);
// start the GPU calculations
dim3 dimBlock(NUM_THREADS, NUM_THREADS, 1);
dim3 dimGrid(NUM_BLOCKS, NUM_BLOCKS, 1);
cudaEventRecord(start_full,0);
CUDA_SAFE_CALL(cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice));
CUDA_SAFE_CALL(cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice));
cudaEventRecord(start_mmm,0);
MMM_kernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_dst, LEN);
cudaEventRecord(stop_mmm,0);
cudaEventSynchronize(stop_mmm);
CUDA_SAFE_CALL(cudaPeekAtLastError());
CUDA_SAFE_CALL(cudaThreadSynchronize());
CUDA_SAFE_CALL(cudaMemcpy(h_dst_gpu, d_dst, size, cudaMemcpyDeviceToHost));
cudaEventRecord(stop_full, 0);
cudaEventSynchronize(stop_full);
cudaEventElapsedTime(&d_time_mmm, start_mmm, stop_mmm);
cudaEventElapsedTime(&d_time_full, start_full, stop_full);
printf("\nGPU MMM Time: %f ms", d_time_mmm);
printf("\nGPU FUll Time: %f ms", d_time_full);
cudaEventDestroy(start_full);
cudaEventDestroy(stop_full);
//CPU calculation
clock_gettime(CLOCK_REALTIME, &time1);
MMM_CPU(h_A, h_B, h_dst_cpu, LEN);
clock_gettime(CLOCK_REALTIME, &time2);
h_time = ts_ms(ts_diff(time1, time2));
printf("\nCPU Time: %lf ms\n", h_time);
int i, num_elements;
num_elements = LEN * LEN;
for(i = 0; i < num_elements; i++)
{
if((h_dst_cpu - h_dst_gpu) > (float) TOL)
{
printf("\nResult verification issue at element %d | CPU: %f | GPU: %f\n", i, h_dst_cpu, h_dst_gpu);
return 0;
}
}
// Free stuff
CUDA_SAFE_CALL(cudaFree(d_A));
CUDA_SAFE_CALL(cudaFree(d_B));
CUDA_SAFE_CALL(cudaFree(d_dst));
free(h_A);
free(h_B);
free(h_dst_gpu);
free(h_dst_cpu);
printf("\nDone\n");
return 0;
}
/////////////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////// MATRIX IMPLEMENTATIONS ////////////////////////////////////////
float float_rand(float min, float max)
{
float f = (float)random()/RAND_MAX;
return min + f * (max - min);
}
float* matrix_create(int len)
{
float* arr;
if(len > 0)
{
arr = (float*) calloc(len*len, sizeof(float));
if(!arr)
{
printf("\n\tFailed to allocate array\n");
return NULL;
}
}
else return NULL;
return arr;
}
int matrix_init(float* mat, int len)
{
int len_sq, i;
if(len > 0)
{
len_sq = len * len;
for (i = 0; i < len_sq; i++)
{
mat[i] = float_rand(MINVAL, MAXVAL);
}
return 1;
}
printf("\nError in initializing matrix\n");
return 0;
}
int matrix_zero(float* mat, int len)
{
int len_sq, i;
if(len > 0)
{
len_sq = len * len;
for(i = 0; i < len_sq; i++)
{
mat[i] = 0;
}
return 1;
}
printf("\nFailed to zero matrix\n");
return 0;
}
int matrix_copy(float* src, float* dst, int len)
{
int len_sq, i;
if(len > 0)
{
len_sq = len * len;
for(i = 0; i < len_sq; i++)
{
dst[i] = src[i];
}
return 1;
}
printf("\nFailed to copy matrix\n");
return 0;
}
void MMM_CPU(float* A, float* B, float* dst, int len)
{
int i, j, k;
for (i = 0; i < len; i++)
{
for(j = 0; j < len; j++)
{
for(k = 0; k < len; k++)
dst[i * len + j] += A[i * len + k] * B[k * len + j];
}
}
}
///////////////////////////// Timing related ///////////////////////////////
double ts_ms(struct timespec ts)
{
return ((((double)(ts.tv_sec))*1.0e9) + ((double)(ts.tv_nsec)))/(1.0e6);
}
/* ---------------------------------------------------------------------------
| Make the CPU busy, and measure CPS (cycles per second).
|
| Explanation:
| If tests are very fast, they can run so quickly that the SpeedStep control
| (in kernel and/or on-chip) doesn't notice in time, and the first few tests
| might finish while the CPU is still in its sleep state (about 800 MHz,
| judging from my measurements)
| A simple way to get around this is to run some kind of busy-loop that
| forces the OS and/or CPU to notice it needs to go to full clock speed.
| We print out the results of the computation so the loop won't get optimised
| away.
|
| Copy this code into other programs as desired. It provides three entry
| points:
|
| double ts_sec(ts): converts a timespec into seconds
| timespec ts_diff(ts1, ts2): computes interval between two timespecs
| measure_cps(): Does the busy loop and prints out measured CPS (cycles/sec)
--------------------------------------------------------------------------- */
struct timespec ts_diff(struct timespec start, struct timespec end)
{
struct timespec temp;
if ((end.tv_nsec-start.tv_nsec)<0) {
temp.tv_sec = end.tv_sec-start.tv_sec-1;
temp.tv_nsec = 1000000000+end.tv_nsec-start.tv_nsec;
} else {
temp.tv_sec = end.tv_sec-start.tv_sec;
temp.tv_nsec = end.tv_nsec-start.tv_nsec;
}
return temp;
}
double measure_cps()
{
struct timespec cal_start, cal_end;
mcps_tctr tsc_start, tsc_end;
double total_time;
double total_cycles;
/* We perform a chaotic iteration and print the result, to defeat
compiler optimisation */
double chaosC = -1.8464323952913974; double z = 0.0;
long int i, ilim, j;
/* Do it twice and throw away results from the first time; this ensures the
* OS and CPU will notice it's busy and set the clock speed. */
for(j=0; j<2; j++) {
clock_gettime(CLOCK_PROCESS_CPUTIME_ID, &cal_start);
MCPS_RDTSC(tsc_start);
ilim = 50*1000*1000;
for (i=0; i<ilim; i++)
z = z * z + chaosC;
clock_gettime(CLOCK_PROCESS_CPUTIME_ID, &cal_end);
MCPS_RDTSC(tsc_end);
}
total_time = ts_ms(ts_diff(cal_start, cal_end));
total_cycles = (double)(tsc_end.int64-tsc_start.int64);
CPS = total_cycles / total_time;
printf("z == %f, CPS == %g\n", z, CPS);
return CPS;
}
/* ---------------------------------------------------------------------------
| End of measure_cps code
--------------------------------------------------------------------------- */
struct timespec diff(struct timespec start, struct timespec end)
{
struct timespec temp;
if ((end.tv_nsec-start.tv_nsec)<0) {
temp.tv_sec = end.tv_sec-start.tv_sec-1;
temp.tv_nsec = 1000000000+end.tv_nsec-start.tv_nsec;
} else {
temp.tv_sec = end.tv_sec-start.tv_sec;
temp.tv_nsec = end.tv_nsec-start.tv_nsec;
}
return temp;
} | .file "tmpxft_000b604c_00000000-6_shared_mmm.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2071:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2071:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPcib.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA_SAFE_CALL: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPcib,comdat
.weak _Z9gpuAssert9cudaErrorPcib
.type _Z9gpuAssert9cudaErrorPcib, @function
_Z9gpuAssert9cudaErrorPcib:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L10
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z9gpuAssert9cudaErrorPcib, .-_Z9gpuAssert9cudaErrorPcib
.text
.globl _Z10float_randff
.type _Z10float_randff, @function
_Z10float_randff:
.LFB2059:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movss %xmm0, 8(%rsp)
movss %xmm1, 12(%rsp)
call random@PLT
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
mulss .LC1(%rip), %xmm0
movss 12(%rsp), %xmm1
movss 8(%rsp), %xmm2
subss %xmm2, %xmm1
mulss %xmm1, %xmm0
addss %xmm2, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z10float_randff, .-_Z10float_randff
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "\n\tFailed to allocate array\n"
.text
.globl _Z13matrix_createi
.type _Z13matrix_createi, @function
_Z13matrix_createi:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl $0, %ebx
testl %edi, %edi
jle .L13
imull %edi, %edi
movslq %edi, %rdi
movl $4, %esi
call calloc@PLT
movq %rax, %rbx
testq %rax, %rax
je .L17
.L13:
movq %rbx, %rax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L13
.cfi_endproc
.LFE2060:
.size _Z13matrix_createi, .-_Z13matrix_createi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "\nError in initializing matrix\n"
.text
.globl _Z11matrix_initPfi
.type _Z11matrix_initPfi, @function
_Z11matrix_initPfi:
.LFB2061:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
testl %esi, %esi
jle .L19
movq %rdi, %rbx
imull %esi, %esi
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L20:
movss .LC3(%rip), %xmm1
pxor %xmm0, %xmm0
call _Z10float_randff
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L20
movl $1, %eax
.L18:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
jmp .L18
.cfi_endproc
.LFE2061:
.size _Z11matrix_initPfi, .-_Z11matrix_initPfi
.section .rodata.str1.1
.LC6:
.string "\nFailed to zero matrix\n"
.text
.globl _Z11matrix_zeroPfi
.type _Z11matrix_zeroPfi, @function
_Z11matrix_zeroPfi:
.LFB2062:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L25
movq %rdi, %rax
imull %esi, %esi
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rdx
.L26:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L26
movl $1, %eax
ret
.L25:
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z11matrix_zeroPfi, .-_Z11matrix_zeroPfi
.section .rodata.str1.1
.LC7:
.string "\nFailed to copy matrix\n"
.text
.globl _Z11matrix_copyPfS_i
.type _Z11matrix_copyPfS_i, @function
_Z11matrix_copyPfS_i:
.LFB2063:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L33
imull %edx, %edx
movslq %edx, %rdx
salq $2, %rdx
movl $0, %eax
.L34:
movss (%rdi,%rax), %xmm0
movss %xmm0, (%rsi,%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L34
movl $1, %eax
ret
.L33:
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _Z11matrix_copyPfS_i, .-_Z11matrix_copyPfS_i
.globl _Z7MMM_CPUPfS_S_i
.type _Z7MMM_CPUPfS_S_i, @function
_Z7MMM_CPUPfS_S_i:
.LFB2064:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L48
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
movq %rsi, %rbp
movq %rdx, %rbx
movl %ecx, %r11d
movslq %ecx, %rsi
salq $2, %rsi
movq %rdi, %r10
addq %rsi, %rdi
movl $0, %r12d
movl $0, %r13d
jmp .L42
.L44:
leal 1(%r12), %eax
addq %rsi, %r10
addq %rsi, %rdi
addq %rsi, %rbx
cmpl %r9d, %r12d
je .L40
movl %eax, %r12d
.L42:
movq %rbp, %r8
movq %rbx, %rcx
movl %r13d, %r9d
.L45:
movq %r8, %rdx
movq %r10, %rax
.L43:
movss (%rax), %xmm0
mulss (%rdx), %xmm0
addss (%rcx), %xmm0
movss %xmm0, (%rcx)
addq $4, %rax
addq %rsi, %rdx
cmpq %rdi, %rax
jne .L43
leal 1(%r9), %eax
addq $4, %r8
addq $4, %rcx
cmpl %eax, %r11d
je .L44
movl %eax, %r9d
jmp .L45
.L40:
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
ret
.cfi_endproc
.LFE2064:
.size _Z7MMM_CPUPfS_S_i, .-_Z7MMM_CPUPfS_S_i
.globl _Z5ts_ms8timespec
.type _Z5ts_ms8timespec, @function
_Z5ts_ms8timespec:
.LFB2065:
.cfi_startproc
endbr64
pxor %xmm0, %xmm0
cvtsi2sdq %rdi, %xmm0
mulsd .LC8(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq %rsi, %xmm1
addsd %xmm1, %xmm0
divsd .LC9(%rip), %xmm0
ret
.cfi_endproc
.LFE2065:
.size _Z5ts_ms8timespec, .-_Z5ts_ms8timespec
.globl _Z7ts_diff8timespecS_
.type _Z7ts_diff8timespecS_, @function
_Z7ts_diff8timespecS_:
.LFB2066:
.cfi_startproc
endbr64
movq %rdx, %rax
subq %rdi, %rax
movq %rcx, %r8
subq %rsi, %r8
js .L55
.L54:
movq %r8, %rdx
ret
.L55:
leaq -1(%rax), %rax
leaq 1000000000(%rcx), %r8
subq %rsi, %r8
jmp .L54
.cfi_endproc
.LFE2066:
.size _Z7ts_diff8timespecS_, .-_Z7ts_diff8timespecS_
.section .rodata.str1.1
.LC12:
.string "z == %f, CPS == %g\n"
.text
.globl _Z11measure_cpsv
.type _Z11measure_cpsv, @function
_Z11measure_cpsv:
.LFB2067:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rsi
movl $2, %edi
call clock_gettime@PLT
#APP
# 369 "/home/ubuntu/Datasets/stackv2/train-structured/jsburke/ec527_lab_private/master/lab8/final/code/shared_mmm.cu" 1
rdtsc
# 0 "" 2
#NO_APP
movl $50000000, %eax
movq $0x000000000, 8(%rsp)
movsd .LC11(%rip), %xmm1
.L57:
movsd 8(%rsp), %xmm0
mulsd %xmm0, %xmm0
subsd %xmm1, %xmm0
movsd %xmm0, 8(%rsp)
subq $1, %rax
jne .L57
leaq 32(%rsp), %rsi
movl $2, %edi
call clock_gettime@PLT
#APP
# 374 "/home/ubuntu/Datasets/stackv2/train-structured/jsburke/ec527_lab_private/master/lab8/final/code/shared_mmm.cu" 1
rdtsc
# 0 "" 2
#NO_APP
leaq 16(%rsp), %rsi
movl $2, %edi
call clock_gettime@PLT
#APP
# 369 "/home/ubuntu/Datasets/stackv2/train-structured/jsburke/ec527_lab_private/master/lab8/final/code/shared_mmm.cu" 1
rdtsc
# 0 "" 2
#NO_APP
salq $32, %rdx
movl %eax, %ebp
orq %rdx, %rbp
movl $50000000, %eax
movsd .LC11(%rip), %xmm1
.L58:
movsd 8(%rsp), %xmm0
mulsd %xmm0, %xmm0
subsd %xmm1, %xmm0
movsd %xmm0, 8(%rsp)
subq $1, %rax
jne .L58
leaq 32(%rsp), %rsi
movl $2, %edi
call clock_gettime@PLT
#APP
# 374 "/home/ubuntu/Datasets/stackv2/train-structured/jsburke/ec527_lab_private/master/lab8/final/code/shared_mmm.cu" 1
rdtsc
# 0 "" 2
#NO_APP
salq $32, %rdx
movl %eax, %ebx
orq %rdx, %rbx
movq 32(%rsp), %rdx
movq 40(%rsp), %rcx
movq 16(%rsp), %rdi
movq 24(%rsp), %rsi
call _Z7ts_diff8timespecS_
movq %rax, %rdi
movq %rdx, %rsi
call _Z5ts_ms8timespec
subq %rbp, %rbx
js .L59
pxor %xmm1, %xmm1
cvtsi2sdq %rbx, %xmm1
.L60:
divsd %xmm0, %xmm1
movsd %xmm1, CPS(%rip)
movsd 8(%rsp), %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movsd CPS(%rip), %xmm0
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L65
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L59:
.cfi_restore_state
movq %rbx, %rax
shrq %rax
andl $1, %ebx
orq %rbx, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm1
jmp .L60
.L65:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2067:
.size _Z11measure_cpsv, .-_Z11measure_cpsv
.globl _Z4diff8timespecS_
.type _Z4diff8timespecS_, @function
_Z4diff8timespecS_:
.LFB2068:
.cfi_startproc
endbr64
movq %rdx, %rax
subq %rdi, %rax
movq %rcx, %r8
subq %rsi, %r8
js .L69
.L68:
movq %r8, %rdx
ret
.L69:
leaq -1(%rax), %rax
leaq 1000000000(%rcx), %r8
subq %rsi, %r8
jmp .L68
.cfi_endproc
.LFE2068:
.size _Z4diff8timespecS_, .-_Z4diff8timespecS_
.globl _Z35__device_stub__Z10MMM_kernelPfS_S_iPfS_S_i
.type _Z35__device_stub__Z10MMM_kernelPfS_S_iPfS_S_i, @function
_Z35__device_stub__Z10MMM_kernelPfS_S_iPfS_S_i:
.LFB2093:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L74
.L70:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L75
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L74:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10MMM_kernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L70
.L75:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2093:
.size _Z35__device_stub__Z10MMM_kernelPfS_S_iPfS_S_i, .-_Z35__device_stub__Z10MMM_kernelPfS_S_iPfS_S_i
.globl _Z10MMM_kernelPfS_S_i
.type _Z10MMM_kernelPfS_S_i, @function
_Z10MMM_kernelPfS_S_i:
.LFB2094:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10MMM_kernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2094:
.size _Z10MMM_kernelPfS_S_i, .-_Z10MMM_kernelPfS_S_i
.section .rodata.str1.1
.LC13:
.string "\nPlease pass a length in.\n"
.section .rodata.str1.8
.align 8
.LC14:
.string "\nLength must be greater than zero\n"
.section .rodata.str1.1
.LC15:
.string "\nOdd Numbr of blocks\n"
.section .rodata.str1.8
.align 8
.LC16:
.string "/home/ubuntu/Datasets/stackv2/train-structured/jsburke/ec527_lab_private/master/lab8/final/code/shared_mmm.cu"
.section .rodata.str1.1
.LC17:
.string "\nGPU MMM Time: %f ms"
.LC18:
.string "\nGPU FUll Time: %f ms"
.LC19:
.string "\nCPU Time: %lf ms\n"
.section .rodata.str1.8
.align 8
.LC21:
.string "\nResult verification issue at element %d | CPU: %f | GPU: %f\n"
.section .rodata.str1.1
.LC22:
.string "\nDone\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $168, %rsp
.cfi_def_cfa_offset 224
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
cmpl $2, %edi
je .L79
leaq .LC13(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
.L80:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L92
movl $0, %eax
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L79:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, 12(%rsp)
movl %eax, LEN(%rip)
testl %eax, %eax
jle .L93
movl %eax, %r12d
andl $15, %r12d
jne .L94
call _Z11measure_cpsv
movl LEN(%rip), %edi
call _Z13matrix_createi
movq %rax, %rbp
testq %rax, %rax
je .L80
movl LEN(%rip), %esi
movq %rax, %rdi
call _Z11matrix_initPfi
testl %eax, %eax
je .L80
movl LEN(%rip), %edi
call _Z13matrix_createi
movq %rax, %r13
testq %rax, %rax
je .L80
movl LEN(%rip), %esi
movq %rax, %rdi
call _Z11matrix_initPfi
testl %eax, %eax
je .L80
movl LEN(%rip), %edi
call _Z13matrix_createi
movq %rax, %r14
testq %rax, %rax
je .L80
movl LEN(%rip), %esi
movq %rax, %rdi
call _Z11matrix_zeroPfi
testl %eax, %eax
je .L80
movl LEN(%rip), %edi
call _Z13matrix_createi
movq %rax, %r15
testq %rax, %rax
je .L80
movl LEN(%rip), %esi
movq %rax, %rdi
call _Z11matrix_zeroPfi
testl %eax, %eax
je .L80
movq $0, 64(%rsp)
movq $0, 72(%rsp)
movq $0, 80(%rsp)
movl $0, %edi
call cudaSetDevice@PLT
movl %eax, %edi
movl $1, %ecx
movl $147, %edx
leaq .LC16(%rip), %rsi
call _Z9gpuAssert9cudaErrorPcib
imull %ebx, %ebx
sall $2, %ebx
movslq %ebx, %rbx
leaq 64(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $149, %edx
leaq .LC16(%rip), %rsi
call _Z9gpuAssert9cudaErrorPcib
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $150, %edx
leaq .LC16(%rip), %rsi
call _Z9gpuAssert9cudaErrorPcib
leaq 80(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $151, %edx
leaq .LC16(%rip), %rsi
call _Z9gpuAssert9cudaErrorPcib
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl $16, 88(%rsp)
movl $16, 92(%rsp)
movl $1, 96(%rsp)
movl $16, %ecx
movl 12(%rsp), %eax
cltd
idivl %ecx
movl %eax, 100(%rsp)
movl %eax, 104(%rsp)
movl $1, 108(%rsp)
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $164, %edx
leaq .LC16(%rip), %rsi
call _Z9gpuAssert9cudaErrorPcib
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $165, %edx
leaq .LC16(%rip), %rsi
call _Z9gpuAssert9cudaErrorPcib
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl 96(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 88(%rsp), %rdx
movq 100(%rsp), %rdi
movl 108(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L95
.L83:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
call cudaPeekAtLastError@PLT
movl %eax, %edi
movl $1, %ecx
movl $172, %edx
leaq .LC16(%rip), %rsi
call _Z9gpuAssert9cudaErrorPcib
call cudaThreadSynchronize@PLT
movl %eax, %edi
movl $1, %ecx
movl $173, %edx
leaq .LC16(%rip), %rsi
call _Z9gpuAssert9cudaErrorPcib
movl $2, %ecx
movq %rbx, %rdx
movq 80(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $175, %edx
leaq .LC16(%rip), %rsi
call _Z9gpuAssert9cudaErrorPcib
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 28(%rsp), %rdi
movq 56(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq 24(%rsp), %rdi
movq 48(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 28(%rsp), %xmm0
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 24(%rsp), %xmm0
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
leaq 112(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
movl LEN(%rip), %ecx
movq %r14, %rdx
movq %r13, %rsi
movq %rbp, %rdi
call _Z7MMM_CPUPfS_S_i
leaq 128(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
movq 128(%rsp), %rdx
movq 136(%rsp), %rcx
movq 112(%rsp), %rdi
movq 120(%rsp), %rsi
call _Z7ts_diff8timespecS_
movq %rax, %rdi
movq %rdx, %rsi
call _Z5ts_ms8timespec
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl LEN(%rip), %eax
imull %eax, %eax
movq %r14, %rdx
subq %r15, %rdx
sarq $2, %rdx
.L84:
cmpl %eax, %r12d
je .L96
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
comiss .LC20(%rip), %xmm0
ja .L97
addl $1, %r12d
jmp .L84
.L93:
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L80
.L94:
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L80
.L95:
movl LEN(%rip), %ecx
movq 80(%rsp), %rdx
movq 72(%rsp), %rsi
movq 64(%rsp), %rdi
call _Z35__device_stub__Z10MMM_kernelPfS_S_iPfS_S_i
jmp .L83
.L97:
movq %r15, %r8
movq %r14, %rcx
movl %r12d, %edx
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L80
.L96:
movq 64(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $208, %edx
leaq .LC16(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPcib
movq 72(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $209, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPcib
movq 80(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $210, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPcib
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L80
.L92:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC23:
.string "_Z10MMM_kernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2096:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC23(%rip), %rdx
movq %rdx, %rcx
leaq _Z10MMM_kernelPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl LEN
.bss
.align 4
.type LEN, @object
.size LEN, 4
LEN:
.zero 4
.globl CPS
.data
.align 8
.type CPS, @object
.size CPS, 8
CPS:
.long -1610612736
.long 1105566543
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 805306368
.align 4
.LC3:
.long 1092616192
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC8:
.long 0
.long 1104006501
.align 8
.LC9:
.long 0
.long 1093567616
.align 8
.LC11:
.long -1308568850
.long 1073580796
.section .rodata.cst4
.align 4
.LC20:
.long 925353388
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cstdio>
#include <cstdlib>
#include <math.h>
#include <time.h>
#define MINVAL 0.00
#define MAXVAL 10.0
#define TOL 1e-5
#define NUM_THREADS 16
double CPS = 2.9e9;
int LEN; // to be defined via cmd args
//////////////////////////// CUDA RELATED ////////////////////////////////////
// Assertion to check for errors
#define CUDA_SAFE_CALL(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"CUDA_SAFE_CALL: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__ void MMM_kernel(float* A, float* B, float* dst, int len)
{
__shared__ float Ms [NUM_THREADS][NUM_THREADS];
__shared__ float Ns [NUM_THREADS][NUM_THREADS];
int bx, by, tx, ty, row, col;
bx = blockIdx.x;
by = blockIdx.y;
tx = threadIdx.x;
ty = threadIdx.y;
row = by * NUM_THREADS + ty;
col = bx * NUM_THREADS + tx;
float partial = 0;
for(int k = 0; k < len/NUM_THREADS; k++)
{
Ms[ty][tx] = A[row * len + (k * NUM_THREADS + tx)];
Ns[ty][tx] = B[col + (k * NUM_THREADS + ty) * len];
__syncthreads();
for(int r = 0; r < NUM_THREADS; r++)
partial += Ms[ty][r] * Ns[r][tx];
__syncthreads();
}
dst[row * len + col] = partial;
}
////////////////////////////// MATRIX /////////////////////////////////////////
float* matrix_create(int len);
int matrix_init(float* mat, int len);
int matrix_zero(float* mat, int len);
int matrix_copy(float* src, float* dst, int len);
void MMM_CPU(float* A, float* B, float* dst, int len);
///////////////// Time related //////////////////////////////
//rdtsc related
typedef union {
unsigned long long int64;
struct {unsigned int lo, hi;} int32;
} mcps_tctr;
#define MCPS_RDTSC(cpu_c) __asm__ __volatile__ ("rdtsc" : \
"=a" ((cpu_c).int32.lo), "=d"((cpu_c).int32.hi))
int clock_gettime(clockid_t clk_id, struct timespec *tp);
struct timespec diff(struct timespec start, struct timespec end);
double ts_ms(struct timespec ts);
struct timespec ts_diff(struct timespec start, struct timespec end);
double measure_cps(void);
////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////
int main(int argc, char *argv[])
{
if(argc != 2)
{
printf("\nPlease pass a length in.\n");
return 0;
}
LEN = strtol(argv[1], NULL, 10);
if(LEN <= 0)
{
printf("\nLength must be greater than zero\n");
return 0;
}
int size = LEN * LEN * sizeof(float);
int NUM_BLOCKS = LEN / NUM_THREADS;
if(LEN % NUM_THREADS != 0) // die if not a good fit
{
printf("\nOdd Numbr of blocks\n");
return 0;
}
// CUDA Timing
cudaEvent_t start_full, start_mmm, stop_full, stop_mmm;
float d_time_full, d_time_mmm;
// CPU Timing
struct timespec time1, time2;
double h_time;
// CPU set up
float *h_A, *h_B, *h_dst_gpu, *h_dst_cpu, *d_A, *d_B, *d_dst;
measure_cps();
h_A = matrix_create(LEN);
if(!h_A) return 0;
if(!matrix_init(h_A, LEN)) return 0;
h_B = matrix_create(LEN);
if(!h_B) return 0;
if(!matrix_init(h_B, LEN)) return 0;
h_dst_cpu = matrix_create(LEN); // cpu result
if(!h_dst_cpu) return 0;
if(!matrix_zero(h_dst_cpu, LEN)) return 0;
h_dst_gpu = matrix_create(LEN); // gpu result
if(!h_dst_gpu) return 0;
if(!matrix_zero(h_dst_gpu, LEN)) return 0;
// GPU Set up
d_A = NULL;
d_B = NULL;
d_dst = NULL;
CUDA_SAFE_CALL(cudaSetDevice(0));
CUDA_SAFE_CALL(cudaMalloc((void**)&d_A, size));
CUDA_SAFE_CALL(cudaMalloc((void**)&d_B, size));
CUDA_SAFE_CALL(cudaMalloc((void**)&d_dst, size));
cudaEventCreate(&start_full);
cudaEventCreate(&start_mmm);
cudaEventCreate(&stop_full);
cudaEventCreate(&stop_mmm);
// start the GPU calculations
dim3 dimBlock(NUM_THREADS, NUM_THREADS, 1);
dim3 dimGrid(NUM_BLOCKS, NUM_BLOCKS, 1);
cudaEventRecord(start_full,0);
CUDA_SAFE_CALL(cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice));
CUDA_SAFE_CALL(cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice));
cudaEventRecord(start_mmm,0);
MMM_kernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_dst, LEN);
cudaEventRecord(stop_mmm,0);
cudaEventSynchronize(stop_mmm);
CUDA_SAFE_CALL(cudaPeekAtLastError());
CUDA_SAFE_CALL(cudaThreadSynchronize());
CUDA_SAFE_CALL(cudaMemcpy(h_dst_gpu, d_dst, size, cudaMemcpyDeviceToHost));
cudaEventRecord(stop_full, 0);
cudaEventSynchronize(stop_full);
cudaEventElapsedTime(&d_time_mmm, start_mmm, stop_mmm);
cudaEventElapsedTime(&d_time_full, start_full, stop_full);
printf("\nGPU MMM Time: %f ms", d_time_mmm);
printf("\nGPU FUll Time: %f ms", d_time_full);
cudaEventDestroy(start_full);
cudaEventDestroy(stop_full);
//CPU calculation
clock_gettime(CLOCK_REALTIME, &time1);
MMM_CPU(h_A, h_B, h_dst_cpu, LEN);
clock_gettime(CLOCK_REALTIME, &time2);
h_time = ts_ms(ts_diff(time1, time2));
printf("\nCPU Time: %lf ms\n", h_time);
int i, num_elements;
num_elements = LEN * LEN;
for(i = 0; i < num_elements; i++)
{
if((h_dst_cpu - h_dst_gpu) > (float) TOL)
{
printf("\nResult verification issue at element %d | CPU: %f | GPU: %f\n", i, h_dst_cpu, h_dst_gpu);
return 0;
}
}
// Free stuff
CUDA_SAFE_CALL(cudaFree(d_A));
CUDA_SAFE_CALL(cudaFree(d_B));
CUDA_SAFE_CALL(cudaFree(d_dst));
free(h_A);
free(h_B);
free(h_dst_gpu);
free(h_dst_cpu);
printf("\nDone\n");
return 0;
}
/////////////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////// MATRIX IMPLEMENTATIONS ////////////////////////////////////////
float float_rand(float min, float max)
{
float f = (float)random()/RAND_MAX;
return min + f * (max - min);
}
float* matrix_create(int len)
{
float* arr;
if(len > 0)
{
arr = (float*) calloc(len*len, sizeof(float));
if(!arr)
{
printf("\n\tFailed to allocate array\n");
return NULL;
}
}
else return NULL;
return arr;
}
int matrix_init(float* mat, int len)
{
int len_sq, i;
if(len > 0)
{
len_sq = len * len;
for (i = 0; i < len_sq; i++)
{
mat[i] = float_rand(MINVAL, MAXVAL);
}
return 1;
}
printf("\nError in initializing matrix\n");
return 0;
}
int matrix_zero(float* mat, int len)
{
int len_sq, i;
if(len > 0)
{
len_sq = len * len;
for(i = 0; i < len_sq; i++)
{
mat[i] = 0;
}
return 1;
}
printf("\nFailed to zero matrix\n");
return 0;
}
int matrix_copy(float* src, float* dst, int len)
{
int len_sq, i;
if(len > 0)
{
len_sq = len * len;
for(i = 0; i < len_sq; i++)
{
dst[i] = src[i];
}
return 1;
}
printf("\nFailed to copy matrix\n");
return 0;
}
void MMM_CPU(float* A, float* B, float* dst, int len)
{
int i, j, k;
for (i = 0; i < len; i++)
{
for(j = 0; j < len; j++)
{
for(k = 0; k < len; k++)
dst[i * len + j] += A[i * len + k] * B[k * len + j];
}
}
}
///////////////////////////// Timing related ///////////////////////////////
double ts_ms(struct timespec ts)
{
return ((((double)(ts.tv_sec))*1.0e9) + ((double)(ts.tv_nsec)))/(1.0e6);
}
/* ---------------------------------------------------------------------------
| Make the CPU busy, and measure CPS (cycles per second).
|
| Explanation:
| If tests are very fast, they can run so quickly that the SpeedStep control
| (in kernel and/or on-chip) doesn't notice in time, and the first few tests
| might finish while the CPU is still in its sleep state (about 800 MHz,
| judging from my measurements)
| A simple way to get around this is to run some kind of busy-loop that
| forces the OS and/or CPU to notice it needs to go to full clock speed.
| We print out the results of the computation so the loop won't get optimised
| away.
|
| Copy this code into other programs as desired. It provides three entry
| points:
|
| double ts_sec(ts): converts a timespec into seconds
| timespec ts_diff(ts1, ts2): computes interval between two timespecs
| measure_cps(): Does the busy loop and prints out measured CPS (cycles/sec)
--------------------------------------------------------------------------- */
struct timespec ts_diff(struct timespec start, struct timespec end)
{
struct timespec temp;
if ((end.tv_nsec-start.tv_nsec)<0) {
temp.tv_sec = end.tv_sec-start.tv_sec-1;
temp.tv_nsec = 1000000000+end.tv_nsec-start.tv_nsec;
} else {
temp.tv_sec = end.tv_sec-start.tv_sec;
temp.tv_nsec = end.tv_nsec-start.tv_nsec;
}
return temp;
}
double measure_cps()
{
struct timespec cal_start, cal_end;
mcps_tctr tsc_start, tsc_end;
double total_time;
double total_cycles;
/* We perform a chaotic iteration and print the result, to defeat
compiler optimisation */
double chaosC = -1.8464323952913974; double z = 0.0;
long int i, ilim, j;
/* Do it twice and throw away results from the first time; this ensures the
* OS and CPU will notice it's busy and set the clock speed. */
for(j=0; j<2; j++) {
clock_gettime(CLOCK_PROCESS_CPUTIME_ID, &cal_start);
MCPS_RDTSC(tsc_start);
ilim = 50*1000*1000;
for (i=0; i<ilim; i++)
z = z * z + chaosC;
clock_gettime(CLOCK_PROCESS_CPUTIME_ID, &cal_end);
MCPS_RDTSC(tsc_end);
}
total_time = ts_ms(ts_diff(cal_start, cal_end));
total_cycles = (double)(tsc_end.int64-tsc_start.int64);
CPS = total_cycles / total_time;
printf("z == %f, CPS == %g\n", z, CPS);
return CPS;
}
/* ---------------------------------------------------------------------------
| End of measure_cps code
--------------------------------------------------------------------------- */
struct timespec diff(struct timespec start, struct timespec end)
{
struct timespec temp;
if ((end.tv_nsec-start.tv_nsec)<0) {
temp.tv_sec = end.tv_sec-start.tv_sec-1;
temp.tv_nsec = 1000000000+end.tv_nsec-start.tv_nsec;
} else {
temp.tv_sec = end.tv_sec-start.tv_sec;
temp.tv_nsec = end.tv_nsec-start.tv_nsec;
}
return temp;
} | #include <hip/hip_runtime.h>
#include <cstdio>
#include <cstdlib>
#include <math.h>
#include <time.h>
#define MINVAL 0.00
#define MAXVAL 10.0
#define TOL 1e-5
#define NUM_THREADS 16
double CPS = 2.9e9;
int LEN; // to be defined via cmd args
//////////////////////////// CUDA RELATED ////////////////////////////////////
// Assertion to check for errors
#define CUDA_SAFE_CALL(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"CUDA_SAFE_CALL: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__ void MMM_kernel(float* A, float* B, float* dst, int len)
{
__shared__ float Ms [NUM_THREADS][NUM_THREADS];
__shared__ float Ns [NUM_THREADS][NUM_THREADS];
int bx, by, tx, ty, row, col;
bx = blockIdx.x;
by = blockIdx.y;
tx = threadIdx.x;
ty = threadIdx.y;
row = by * NUM_THREADS + ty;
col = bx * NUM_THREADS + tx;
float partial = 0;
for(int k = 0; k < len/NUM_THREADS; k++)
{
Ms[ty][tx] = A[row * len + (k * NUM_THREADS + tx)];
Ns[ty][tx] = B[col + (k * NUM_THREADS + ty) * len];
__syncthreads();
for(int r = 0; r < NUM_THREADS; r++)
partial += Ms[ty][r] * Ns[r][tx];
__syncthreads();
}
dst[row * len + col] = partial;
}
////////////////////////////// MATRIX /////////////////////////////////////////
float* matrix_create(int len);
int matrix_init(float* mat, int len);
int matrix_zero(float* mat, int len);
int matrix_copy(float* src, float* dst, int len);
void MMM_CPU(float* A, float* B, float* dst, int len);
///////////////// Time related //////////////////////////////
//rdtsc related
typedef union {
unsigned long long int64;
struct {unsigned int lo, hi;} int32;
} mcps_tctr;
#define MCPS_RDTSC(cpu_c) __asm__ __volatile__ ("rdtsc" : \
"=a" ((cpu_c).int32.lo), "=d"((cpu_c).int32.hi))
int clock_gettime(clockid_t clk_id, struct timespec *tp);
struct timespec diff(struct timespec start, struct timespec end);
double ts_ms(struct timespec ts);
struct timespec ts_diff(struct timespec start, struct timespec end);
double measure_cps(void);
////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////
int main(int argc, char *argv[])
{
if(argc != 2)
{
printf("\nPlease pass a length in.\n");
return 0;
}
LEN = strtol(argv[1], NULL, 10);
if(LEN <= 0)
{
printf("\nLength must be greater than zero\n");
return 0;
}
int size = LEN * LEN * sizeof(float);
int NUM_BLOCKS = LEN / NUM_THREADS;
if(LEN % NUM_THREADS != 0) // die if not a good fit
{
printf("\nOdd Numbr of blocks\n");
return 0;
}
// CUDA Timing
hipEvent_t start_full, start_mmm, stop_full, stop_mmm;
float d_time_full, d_time_mmm;
// CPU Timing
struct timespec time1, time2;
double h_time;
// CPU set up
float *h_A, *h_B, *h_dst_gpu, *h_dst_cpu, *d_A, *d_B, *d_dst;
measure_cps();
h_A = matrix_create(LEN);
if(!h_A) return 0;
if(!matrix_init(h_A, LEN)) return 0;
h_B = matrix_create(LEN);
if(!h_B) return 0;
if(!matrix_init(h_B, LEN)) return 0;
h_dst_cpu = matrix_create(LEN); // cpu result
if(!h_dst_cpu) return 0;
if(!matrix_zero(h_dst_cpu, LEN)) return 0;
h_dst_gpu = matrix_create(LEN); // gpu result
if(!h_dst_gpu) return 0;
if(!matrix_zero(h_dst_gpu, LEN)) return 0;
// GPU Set up
d_A = NULL;
d_B = NULL;
d_dst = NULL;
CUDA_SAFE_CALL(hipSetDevice(0));
CUDA_SAFE_CALL(hipMalloc((void**)&d_A, size));
CUDA_SAFE_CALL(hipMalloc((void**)&d_B, size));
CUDA_SAFE_CALL(hipMalloc((void**)&d_dst, size));
hipEventCreate(&start_full);
hipEventCreate(&start_mmm);
hipEventCreate(&stop_full);
hipEventCreate(&stop_mmm);
// start the GPU calculations
dim3 dimBlock(NUM_THREADS, NUM_THREADS, 1);
dim3 dimGrid(NUM_BLOCKS, NUM_BLOCKS, 1);
hipEventRecord(start_full,0);
CUDA_SAFE_CALL(hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice));
CUDA_SAFE_CALL(hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice));
hipEventRecord(start_mmm,0);
MMM_kernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_dst, LEN);
hipEventRecord(stop_mmm,0);
hipEventSynchronize(stop_mmm);
CUDA_SAFE_CALL(hipPeekAtLastError());
CUDA_SAFE_CALL(hipDeviceSynchronize());
CUDA_SAFE_CALL(hipMemcpy(h_dst_gpu, d_dst, size, hipMemcpyDeviceToHost));
hipEventRecord(stop_full, 0);
hipEventSynchronize(stop_full);
hipEventElapsedTime(&d_time_mmm, start_mmm, stop_mmm);
hipEventElapsedTime(&d_time_full, start_full, stop_full);
printf("\nGPU MMM Time: %f ms", d_time_mmm);
printf("\nGPU FUll Time: %f ms", d_time_full);
hipEventDestroy(start_full);
hipEventDestroy(stop_full);
//CPU calculation
clock_gettime(CLOCK_REALTIME, &time1);
MMM_CPU(h_A, h_B, h_dst_cpu, LEN);
clock_gettime(CLOCK_REALTIME, &time2);
h_time = ts_ms(ts_diff(time1, time2));
printf("\nCPU Time: %lf ms\n", h_time);
int i, num_elements;
num_elements = LEN * LEN;
for(i = 0; i < num_elements; i++)
{
if((h_dst_cpu - h_dst_gpu) > (float) TOL)
{
printf("\nResult verification issue at element %d | CPU: %f | GPU: %f\n", i, h_dst_cpu, h_dst_gpu);
return 0;
}
}
// Free stuff
CUDA_SAFE_CALL(hipFree(d_A));
CUDA_SAFE_CALL(hipFree(d_B));
CUDA_SAFE_CALL(hipFree(d_dst));
free(h_A);
free(h_B);
free(h_dst_gpu);
free(h_dst_cpu);
printf("\nDone\n");
return 0;
}
/////////////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////// MATRIX IMPLEMENTATIONS ////////////////////////////////////////
float float_rand(float min, float max)
{
float f = (float)random()/RAND_MAX;
return min + f * (max - min);
}
float* matrix_create(int len)
{
float* arr;
if(len > 0)
{
arr = (float*) calloc(len*len, sizeof(float));
if(!arr)
{
printf("\n\tFailed to allocate array\n");
return NULL;
}
}
else return NULL;
return arr;
}
int matrix_init(float* mat, int len)
{
int len_sq, i;
if(len > 0)
{
len_sq = len * len;
for (i = 0; i < len_sq; i++)
{
mat[i] = float_rand(MINVAL, MAXVAL);
}
return 1;
}
printf("\nError in initializing matrix\n");
return 0;
}
int matrix_zero(float* mat, int len)
{
int len_sq, i;
if(len > 0)
{
len_sq = len * len;
for(i = 0; i < len_sq; i++)
{
mat[i] = 0;
}
return 1;
}
printf("\nFailed to zero matrix\n");
return 0;
}
int matrix_copy(float* src, float* dst, int len)
{
int len_sq, i;
if(len > 0)
{
len_sq = len * len;
for(i = 0; i < len_sq; i++)
{
dst[i] = src[i];
}
return 1;
}
printf("\nFailed to copy matrix\n");
return 0;
}
void MMM_CPU(float* A, float* B, float* dst, int len)
{
int i, j, k;
for (i = 0; i < len; i++)
{
for(j = 0; j < len; j++)
{
for(k = 0; k < len; k++)
dst[i * len + j] += A[i * len + k] * B[k * len + j];
}
}
}
///////////////////////////// Timing related ///////////////////////////////
double ts_ms(struct timespec ts)
{
return ((((double)(ts.tv_sec))*1.0e9) + ((double)(ts.tv_nsec)))/(1.0e6);
}
/* ---------------------------------------------------------------------------
| Make the CPU busy, and measure CPS (cycles per second).
|
| Explanation:
| If tests are very fast, they can run so quickly that the SpeedStep control
| (in kernel and/or on-chip) doesn't notice in time, and the first few tests
| might finish while the CPU is still in its sleep state (about 800 MHz,
| judging from my measurements)
| A simple way to get around this is to run some kind of busy-loop that
| forces the OS and/or CPU to notice it needs to go to full clock speed.
| We print out the results of the computation so the loop won't get optimised
| away.
|
| Copy this code into other programs as desired. It provides three entry
| points:
|
| double ts_sec(ts): converts a timespec into seconds
| timespec ts_diff(ts1, ts2): computes interval between two timespecs
| measure_cps(): Does the busy loop and prints out measured CPS (cycles/sec)
--------------------------------------------------------------------------- */
struct timespec ts_diff(struct timespec start, struct timespec end)
{
struct timespec temp;
if ((end.tv_nsec-start.tv_nsec)<0) {
temp.tv_sec = end.tv_sec-start.tv_sec-1;
temp.tv_nsec = 1000000000+end.tv_nsec-start.tv_nsec;
} else {
temp.tv_sec = end.tv_sec-start.tv_sec;
temp.tv_nsec = end.tv_nsec-start.tv_nsec;
}
return temp;
}
double measure_cps()
{
struct timespec cal_start, cal_end;
mcps_tctr tsc_start, tsc_end;
double total_time;
double total_cycles;
/* We perform a chaotic iteration and print the result, to defeat
compiler optimisation */
double chaosC = -1.8464323952913974; double z = 0.0;
long int i, ilim, j;
/* Do it twice and throw away results from the first time; this ensures the
* OS and CPU will notice it's busy and set the clock speed. */
for(j=0; j<2; j++) {
clock_gettime(CLOCK_PROCESS_CPUTIME_ID, &cal_start);
MCPS_RDTSC(tsc_start);
ilim = 50*1000*1000;
for (i=0; i<ilim; i++)
z = z * z + chaosC;
clock_gettime(CLOCK_PROCESS_CPUTIME_ID, &cal_end);
MCPS_RDTSC(tsc_end);
}
total_time = ts_ms(ts_diff(cal_start, cal_end));
total_cycles = (double)(tsc_end.int64-tsc_start.int64);
CPS = total_cycles / total_time;
printf("z == %f, CPS == %g\n", z, CPS);
return CPS;
}
/* ---------------------------------------------------------------------------
| End of measure_cps code
--------------------------------------------------------------------------- */
struct timespec diff(struct timespec start, struct timespec end)
{
struct timespec temp;
if ((end.tv_nsec-start.tv_nsec)<0) {
temp.tv_sec = end.tv_sec-start.tv_sec-1;
temp.tv_nsec = 1000000000+end.tv_nsec-start.tv_nsec;
} else {
temp.tv_sec = end.tv_sec-start.tv_sec;
temp.tv_nsec = end.tv_nsec-start.tv_nsec;
}
return temp;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
#include <cstdlib>
#include <math.h>
#include <time.h>
#define MINVAL 0.00
#define MAXVAL 10.0
#define TOL 1e-5
#define NUM_THREADS 16
double CPS = 2.9e9;
int LEN; // to be defined via cmd args
//////////////////////////// CUDA RELATED ////////////////////////////////////
// Assertion to check for errors
#define CUDA_SAFE_CALL(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"CUDA_SAFE_CALL: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__ void MMM_kernel(float* A, float* B, float* dst, int len)
{
__shared__ float Ms [NUM_THREADS][NUM_THREADS];
__shared__ float Ns [NUM_THREADS][NUM_THREADS];
int bx, by, tx, ty, row, col;
bx = blockIdx.x;
by = blockIdx.y;
tx = threadIdx.x;
ty = threadIdx.y;
row = by * NUM_THREADS + ty;
col = bx * NUM_THREADS + tx;
float partial = 0;
for(int k = 0; k < len/NUM_THREADS; k++)
{
Ms[ty][tx] = A[row * len + (k * NUM_THREADS + tx)];
Ns[ty][tx] = B[col + (k * NUM_THREADS + ty) * len];
__syncthreads();
for(int r = 0; r < NUM_THREADS; r++)
partial += Ms[ty][r] * Ns[r][tx];
__syncthreads();
}
dst[row * len + col] = partial;
}
////////////////////////////// MATRIX /////////////////////////////////////////
float* matrix_create(int len);
int matrix_init(float* mat, int len);
int matrix_zero(float* mat, int len);
int matrix_copy(float* src, float* dst, int len);
void MMM_CPU(float* A, float* B, float* dst, int len);
///////////////// Time related //////////////////////////////
//rdtsc related
typedef union {
unsigned long long int64;
struct {unsigned int lo, hi;} int32;
} mcps_tctr;
#define MCPS_RDTSC(cpu_c) __asm__ __volatile__ ("rdtsc" : \
"=a" ((cpu_c).int32.lo), "=d"((cpu_c).int32.hi))
int clock_gettime(clockid_t clk_id, struct timespec *tp);
struct timespec diff(struct timespec start, struct timespec end);
double ts_ms(struct timespec ts);
struct timespec ts_diff(struct timespec start, struct timespec end);
double measure_cps(void);
////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////
int main(int argc, char *argv[])
{
if(argc != 2)
{
printf("\nPlease pass a length in.\n");
return 0;
}
LEN = strtol(argv[1], NULL, 10);
if(LEN <= 0)
{
printf("\nLength must be greater than zero\n");
return 0;
}
int size = LEN * LEN * sizeof(float);
int NUM_BLOCKS = LEN / NUM_THREADS;
if(LEN % NUM_THREADS != 0) // die if not a good fit
{
printf("\nOdd Numbr of blocks\n");
return 0;
}
// CUDA Timing
hipEvent_t start_full, start_mmm, stop_full, stop_mmm;
float d_time_full, d_time_mmm;
// CPU Timing
struct timespec time1, time2;
double h_time;
// CPU set up
float *h_A, *h_B, *h_dst_gpu, *h_dst_cpu, *d_A, *d_B, *d_dst;
measure_cps();
h_A = matrix_create(LEN);
if(!h_A) return 0;
if(!matrix_init(h_A, LEN)) return 0;
h_B = matrix_create(LEN);
if(!h_B) return 0;
if(!matrix_init(h_B, LEN)) return 0;
h_dst_cpu = matrix_create(LEN); // cpu result
if(!h_dst_cpu) return 0;
if(!matrix_zero(h_dst_cpu, LEN)) return 0;
h_dst_gpu = matrix_create(LEN); // gpu result
if(!h_dst_gpu) return 0;
if(!matrix_zero(h_dst_gpu, LEN)) return 0;
// GPU Set up
d_A = NULL;
d_B = NULL;
d_dst = NULL;
CUDA_SAFE_CALL(hipSetDevice(0));
CUDA_SAFE_CALL(hipMalloc((void**)&d_A, size));
CUDA_SAFE_CALL(hipMalloc((void**)&d_B, size));
CUDA_SAFE_CALL(hipMalloc((void**)&d_dst, size));
hipEventCreate(&start_full);
hipEventCreate(&start_mmm);
hipEventCreate(&stop_full);
hipEventCreate(&stop_mmm);
// start the GPU calculations
dim3 dimBlock(NUM_THREADS, NUM_THREADS, 1);
dim3 dimGrid(NUM_BLOCKS, NUM_BLOCKS, 1);
hipEventRecord(start_full,0);
CUDA_SAFE_CALL(hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice));
CUDA_SAFE_CALL(hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice));
hipEventRecord(start_mmm,0);
MMM_kernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_dst, LEN);
hipEventRecord(stop_mmm,0);
hipEventSynchronize(stop_mmm);
CUDA_SAFE_CALL(hipPeekAtLastError());
CUDA_SAFE_CALL(hipDeviceSynchronize());
CUDA_SAFE_CALL(hipMemcpy(h_dst_gpu, d_dst, size, hipMemcpyDeviceToHost));
hipEventRecord(stop_full, 0);
hipEventSynchronize(stop_full);
hipEventElapsedTime(&d_time_mmm, start_mmm, stop_mmm);
hipEventElapsedTime(&d_time_full, start_full, stop_full);
printf("\nGPU MMM Time: %f ms", d_time_mmm);
printf("\nGPU FUll Time: %f ms", d_time_full);
hipEventDestroy(start_full);
hipEventDestroy(stop_full);
//CPU calculation
clock_gettime(CLOCK_REALTIME, &time1);
MMM_CPU(h_A, h_B, h_dst_cpu, LEN);
clock_gettime(CLOCK_REALTIME, &time2);
h_time = ts_ms(ts_diff(time1, time2));
printf("\nCPU Time: %lf ms\n", h_time);
int i, num_elements;
num_elements = LEN * LEN;
for(i = 0; i < num_elements; i++)
{
if((h_dst_cpu - h_dst_gpu) > (float) TOL)
{
printf("\nResult verification issue at element %d | CPU: %f | GPU: %f\n", i, h_dst_cpu, h_dst_gpu);
return 0;
}
}
// Free stuff
CUDA_SAFE_CALL(hipFree(d_A));
CUDA_SAFE_CALL(hipFree(d_B));
CUDA_SAFE_CALL(hipFree(d_dst));
free(h_A);
free(h_B);
free(h_dst_gpu);
free(h_dst_cpu);
printf("\nDone\n");
return 0;
}
/////////////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////// MATRIX IMPLEMENTATIONS ////////////////////////////////////////
float float_rand(float min, float max)
{
float f = (float)random()/RAND_MAX;
return min + f * (max - min);
}
float* matrix_create(int len)
{
float* arr;
if(len > 0)
{
arr = (float*) calloc(len*len, sizeof(float));
if(!arr)
{
printf("\n\tFailed to allocate array\n");
return NULL;
}
}
else return NULL;
return arr;
}
int matrix_init(float* mat, int len)
{
int len_sq, i;
if(len > 0)
{
len_sq = len * len;
for (i = 0; i < len_sq; i++)
{
mat[i] = float_rand(MINVAL, MAXVAL);
}
return 1;
}
printf("\nError in initializing matrix\n");
return 0;
}
int matrix_zero(float* mat, int len)
{
int len_sq, i;
if(len > 0)
{
len_sq = len * len;
for(i = 0; i < len_sq; i++)
{
mat[i] = 0;
}
return 1;
}
printf("\nFailed to zero matrix\n");
return 0;
}
int matrix_copy(float* src, float* dst, int len)
{
int len_sq, i;
if(len > 0)
{
len_sq = len * len;
for(i = 0; i < len_sq; i++)
{
dst[i] = src[i];
}
return 1;
}
printf("\nFailed to copy matrix\n");
return 0;
}
void MMM_CPU(float* A, float* B, float* dst, int len)
{
int i, j, k;
for (i = 0; i < len; i++)
{
for(j = 0; j < len; j++)
{
for(k = 0; k < len; k++)
dst[i * len + j] += A[i * len + k] * B[k * len + j];
}
}
}
///////////////////////////// Timing related ///////////////////////////////
double ts_ms(struct timespec ts)
{
return ((((double)(ts.tv_sec))*1.0e9) + ((double)(ts.tv_nsec)))/(1.0e6);
}
/* ---------------------------------------------------------------------------
| Make the CPU busy, and measure CPS (cycles per second).
|
| Explanation:
| If tests are very fast, they can run so quickly that the SpeedStep control
| (in kernel and/or on-chip) doesn't notice in time, and the first few tests
| might finish while the CPU is still in its sleep state (about 800 MHz,
| judging from my measurements)
| A simple way to get around this is to run some kind of busy-loop that
| forces the OS and/or CPU to notice it needs to go to full clock speed.
| We print out the results of the computation so the loop won't get optimised
| away.
|
| Copy this code into other programs as desired. It provides three entry
| points:
|
| double ts_sec(ts): converts a timespec into seconds
| timespec ts_diff(ts1, ts2): computes interval between two timespecs
| measure_cps(): Does the busy loop and prints out measured CPS (cycles/sec)
--------------------------------------------------------------------------- */
struct timespec ts_diff(struct timespec start, struct timespec end)
{
struct timespec temp;
if ((end.tv_nsec-start.tv_nsec)<0) {
temp.tv_sec = end.tv_sec-start.tv_sec-1;
temp.tv_nsec = 1000000000+end.tv_nsec-start.tv_nsec;
} else {
temp.tv_sec = end.tv_sec-start.tv_sec;
temp.tv_nsec = end.tv_nsec-start.tv_nsec;
}
return temp;
}
double measure_cps()
{
struct timespec cal_start, cal_end;
mcps_tctr tsc_start, tsc_end;
double total_time;
double total_cycles;
/* We perform a chaotic iteration and print the result, to defeat
compiler optimisation */
double chaosC = -1.8464323952913974; double z = 0.0;
long int i, ilim, j;
/* Do it twice and throw away results from the first time; this ensures the
* OS and CPU will notice it's busy and set the clock speed. */
for(j=0; j<2; j++) {
clock_gettime(CLOCK_PROCESS_CPUTIME_ID, &cal_start);
MCPS_RDTSC(tsc_start);
ilim = 50*1000*1000;
for (i=0; i<ilim; i++)
z = z * z + chaosC;
clock_gettime(CLOCK_PROCESS_CPUTIME_ID, &cal_end);
MCPS_RDTSC(tsc_end);
}
total_time = ts_ms(ts_diff(cal_start, cal_end));
total_cycles = (double)(tsc_end.int64-tsc_start.int64);
CPS = total_cycles / total_time;
printf("z == %f, CPS == %g\n", z, CPS);
return CPS;
}
/* ---------------------------------------------------------------------------
| End of measure_cps code
--------------------------------------------------------------------------- */
struct timespec diff(struct timespec start, struct timespec end)
{
struct timespec temp;
if ((end.tv_nsec-start.tv_nsec)<0) {
temp.tv_sec = end.tv_sec-start.tv_sec-1;
temp.tv_nsec = 1000000000+end.tv_nsec-start.tv_nsec;
} else {
temp.tv_sec = end.tv_sec-start.tv_sec;
temp.tv_nsec = end.tv_nsec-start.tv_nsec;
}
return temp;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10MMM_kernelPfS_S_i
.globl _Z10MMM_kernelPfS_S_i
.p2align 8
.type _Z10MMM_kernelPfS_S_i,@function
_Z10MMM_kernelPfS_S_i:
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v5, v0, 10, 10
v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v3, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v4, s15, 4, v5
v_lshl_add_u32 v0, s14, 4, v3
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 16
s_cbranch_scc1 .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v8, 2, v3
v_lshlrev_b32_e32 v6, 6, v5
s_ashr_i32 s3, s2, 31
v_mad_u64_u32 v[1:2], null, v4, s2, v[3:4]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v7, 0x400, v8
s_lshr_b32 s3, s3, 28
v_add_nc_u32_e32 v3, v6, v8
s_add_i32 s3, s2, s3
v_add_nc_u32_e32 v8, v7, v6
s_ashr_i32 s3, s3, 4
s_mov_b32 s8, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
s_lshl_b32 s9, s8, 4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v10, s9, v5
v_add_nc_u32_e32 v9, s9, v1
s_mov_b32 s9, 0
v_mad_u64_u32 v[11:12], null, v10, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v12, 31, v11
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, vcc_lo, s4, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v11, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
global_load_b32 v10, v[9:10], off
global_load_b32 v11, v[11:12], off
v_mov_b32_e32 v9, v7
s_waitcnt vmcnt(1)
ds_store_b32 v3, v10
s_waitcnt vmcnt(0)
ds_store_b32 v8, v11
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3:
v_add_nc_u32_e32 v10, s9, v6
s_add_i32 s9, s9, 4
ds_load_b32 v11, v9
ds_load_b32 v10, v10
v_add_nc_u32_e32 v9, 64, v9
s_cmp_eq_u32 s9, 64
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, v10, v11
s_cbranch_scc0 .LBB0_3
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s8, s3
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[5:6], null, v4, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[0:1], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10MMM_kernelPfS_S_i
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10MMM_kernelPfS_S_i, .Lfunc_end0-_Z10MMM_kernelPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10MMM_kernelPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10MMM_kernelPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
#include <cstdlib>
#include <math.h>
#include <time.h>
#define MINVAL 0.00
#define MAXVAL 10.0
#define TOL 1e-5
#define NUM_THREADS 16
double CPS = 2.9e9;
int LEN; // to be defined via cmd args
//////////////////////////// CUDA RELATED ////////////////////////////////////
// Assertion to check for errors
#define CUDA_SAFE_CALL(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"CUDA_SAFE_CALL: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__ void MMM_kernel(float* A, float* B, float* dst, int len)
{
__shared__ float Ms [NUM_THREADS][NUM_THREADS];
__shared__ float Ns [NUM_THREADS][NUM_THREADS];
int bx, by, tx, ty, row, col;
bx = blockIdx.x;
by = blockIdx.y;
tx = threadIdx.x;
ty = threadIdx.y;
row = by * NUM_THREADS + ty;
col = bx * NUM_THREADS + tx;
float partial = 0;
for(int k = 0; k < len/NUM_THREADS; k++)
{
Ms[ty][tx] = A[row * len + (k * NUM_THREADS + tx)];
Ns[ty][tx] = B[col + (k * NUM_THREADS + ty) * len];
__syncthreads();
for(int r = 0; r < NUM_THREADS; r++)
partial += Ms[ty][r] * Ns[r][tx];
__syncthreads();
}
dst[row * len + col] = partial;
}
////////////////////////////// MATRIX /////////////////////////////////////////
float* matrix_create(int len);
int matrix_init(float* mat, int len);
int matrix_zero(float* mat, int len);
int matrix_copy(float* src, float* dst, int len);
void MMM_CPU(float* A, float* B, float* dst, int len);
///////////////// Time related //////////////////////////////
//rdtsc related
typedef union {
unsigned long long int64;
struct {unsigned int lo, hi;} int32;
} mcps_tctr;
#define MCPS_RDTSC(cpu_c) __asm__ __volatile__ ("rdtsc" : \
"=a" ((cpu_c).int32.lo), "=d"((cpu_c).int32.hi))
int clock_gettime(clockid_t clk_id, struct timespec *tp);
struct timespec diff(struct timespec start, struct timespec end);
double ts_ms(struct timespec ts);
struct timespec ts_diff(struct timespec start, struct timespec end);
double measure_cps(void);
////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////
int main(int argc, char *argv[])
{
if(argc != 2)
{
printf("\nPlease pass a length in.\n");
return 0;
}
LEN = strtol(argv[1], NULL, 10);
if(LEN <= 0)
{
printf("\nLength must be greater than zero\n");
return 0;
}
int size = LEN * LEN * sizeof(float);
int NUM_BLOCKS = LEN / NUM_THREADS;
if(LEN % NUM_THREADS != 0) // die if not a good fit
{
printf("\nOdd Numbr of blocks\n");
return 0;
}
// CUDA Timing
hipEvent_t start_full, start_mmm, stop_full, stop_mmm;
float d_time_full, d_time_mmm;
// CPU Timing
struct timespec time1, time2;
double h_time;
// CPU set up
float *h_A, *h_B, *h_dst_gpu, *h_dst_cpu, *d_A, *d_B, *d_dst;
measure_cps();
h_A = matrix_create(LEN);
if(!h_A) return 0;
if(!matrix_init(h_A, LEN)) return 0;
h_B = matrix_create(LEN);
if(!h_B) return 0;
if(!matrix_init(h_B, LEN)) return 0;
h_dst_cpu = matrix_create(LEN); // cpu result
if(!h_dst_cpu) return 0;
if(!matrix_zero(h_dst_cpu, LEN)) return 0;
h_dst_gpu = matrix_create(LEN); // gpu result
if(!h_dst_gpu) return 0;
if(!matrix_zero(h_dst_gpu, LEN)) return 0;
// GPU Set up
d_A = NULL;
d_B = NULL;
d_dst = NULL;
CUDA_SAFE_CALL(hipSetDevice(0));
CUDA_SAFE_CALL(hipMalloc((void**)&d_A, size));
CUDA_SAFE_CALL(hipMalloc((void**)&d_B, size));
CUDA_SAFE_CALL(hipMalloc((void**)&d_dst, size));
hipEventCreate(&start_full);
hipEventCreate(&start_mmm);
hipEventCreate(&stop_full);
hipEventCreate(&stop_mmm);
// start the GPU calculations
dim3 dimBlock(NUM_THREADS, NUM_THREADS, 1);
dim3 dimGrid(NUM_BLOCKS, NUM_BLOCKS, 1);
hipEventRecord(start_full,0);
CUDA_SAFE_CALL(hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice));
CUDA_SAFE_CALL(hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice));
hipEventRecord(start_mmm,0);
MMM_kernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_dst, LEN);
hipEventRecord(stop_mmm,0);
hipEventSynchronize(stop_mmm);
CUDA_SAFE_CALL(hipPeekAtLastError());
CUDA_SAFE_CALL(hipDeviceSynchronize());
CUDA_SAFE_CALL(hipMemcpy(h_dst_gpu, d_dst, size, hipMemcpyDeviceToHost));
hipEventRecord(stop_full, 0);
hipEventSynchronize(stop_full);
hipEventElapsedTime(&d_time_mmm, start_mmm, stop_mmm);
hipEventElapsedTime(&d_time_full, start_full, stop_full);
printf("\nGPU MMM Time: %f ms", d_time_mmm);
printf("\nGPU FUll Time: %f ms", d_time_full);
hipEventDestroy(start_full);
hipEventDestroy(stop_full);
//CPU calculation
clock_gettime(CLOCK_REALTIME, &time1);
MMM_CPU(h_A, h_B, h_dst_cpu, LEN);
clock_gettime(CLOCK_REALTIME, &time2);
h_time = ts_ms(ts_diff(time1, time2));
printf("\nCPU Time: %lf ms\n", h_time);
int i, num_elements;
num_elements = LEN * LEN;
for(i = 0; i < num_elements; i++)
{
if((h_dst_cpu - h_dst_gpu) > (float) TOL)
{
printf("\nResult verification issue at element %d | CPU: %f | GPU: %f\n", i, h_dst_cpu, h_dst_gpu);
return 0;
}
}
// Free stuff
CUDA_SAFE_CALL(hipFree(d_A));
CUDA_SAFE_CALL(hipFree(d_B));
CUDA_SAFE_CALL(hipFree(d_dst));
free(h_A);
free(h_B);
free(h_dst_gpu);
free(h_dst_cpu);
printf("\nDone\n");
return 0;
}
/////////////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////// MATRIX IMPLEMENTATIONS ////////////////////////////////////////
float float_rand(float min, float max)
{
float f = (float)random()/RAND_MAX;
return min + f * (max - min);
}
float* matrix_create(int len)
{
float* arr;
if(len > 0)
{
arr = (float*) calloc(len*len, sizeof(float));
if(!arr)
{
printf("\n\tFailed to allocate array\n");
return NULL;
}
}
else return NULL;
return arr;
}
int matrix_init(float* mat, int len)
{
int len_sq, i;
if(len > 0)
{
len_sq = len * len;
for (i = 0; i < len_sq; i++)
{
mat[i] = float_rand(MINVAL, MAXVAL);
}
return 1;
}
printf("\nError in initializing matrix\n");
return 0;
}
int matrix_zero(float* mat, int len)
{
int len_sq, i;
if(len > 0)
{
len_sq = len * len;
for(i = 0; i < len_sq; i++)
{
mat[i] = 0;
}
return 1;
}
printf("\nFailed to zero matrix\n");
return 0;
}
int matrix_copy(float* src, float* dst, int len)
{
int len_sq, i;
if(len > 0)
{
len_sq = len * len;
for(i = 0; i < len_sq; i++)
{
dst[i] = src[i];
}
return 1;
}
printf("\nFailed to copy matrix\n");
return 0;
}
void MMM_CPU(float* A, float* B, float* dst, int len)
{
int i, j, k;
for (i = 0; i < len; i++)
{
for(j = 0; j < len; j++)
{
for(k = 0; k < len; k++)
dst[i * len + j] += A[i * len + k] * B[k * len + j];
}
}
}
///////////////////////////// Timing related ///////////////////////////////
double ts_ms(struct timespec ts)
{
return ((((double)(ts.tv_sec))*1.0e9) + ((double)(ts.tv_nsec)))/(1.0e6);
}
/* ---------------------------------------------------------------------------
| Make the CPU busy, and measure CPS (cycles per second).
|
| Explanation:
| If tests are very fast, they can run so quickly that the SpeedStep control
| (in kernel and/or on-chip) doesn't notice in time, and the first few tests
| might finish while the CPU is still in its sleep state (about 800 MHz,
| judging from my measurements)
| A simple way to get around this is to run some kind of busy-loop that
| forces the OS and/or CPU to notice it needs to go to full clock speed.
| We print out the results of the computation so the loop won't get optimised
| away.
|
| Copy this code into other programs as desired. It provides three entry
| points:
|
| double ts_sec(ts): converts a timespec into seconds
| timespec ts_diff(ts1, ts2): computes interval between two timespecs
| measure_cps(): Does the busy loop and prints out measured CPS (cycles/sec)
--------------------------------------------------------------------------- */
struct timespec ts_diff(struct timespec start, struct timespec end)
{
struct timespec temp;
if ((end.tv_nsec-start.tv_nsec)<0) {
temp.tv_sec = end.tv_sec-start.tv_sec-1;
temp.tv_nsec = 1000000000+end.tv_nsec-start.tv_nsec;
} else {
temp.tv_sec = end.tv_sec-start.tv_sec;
temp.tv_nsec = end.tv_nsec-start.tv_nsec;
}
return temp;
}
double measure_cps()
{
struct timespec cal_start, cal_end;
mcps_tctr tsc_start, tsc_end;
double total_time;
double total_cycles;
/* We perform a chaotic iteration and print the result, to defeat
compiler optimisation */
double chaosC = -1.8464323952913974; double z = 0.0;
long int i, ilim, j;
/* Do it twice and throw away results from the first time; this ensures the
* OS and CPU will notice it's busy and set the clock speed. */
for(j=0; j<2; j++) {
clock_gettime(CLOCK_PROCESS_CPUTIME_ID, &cal_start);
MCPS_RDTSC(tsc_start);
ilim = 50*1000*1000;
for (i=0; i<ilim; i++)
z = z * z + chaosC;
clock_gettime(CLOCK_PROCESS_CPUTIME_ID, &cal_end);
MCPS_RDTSC(tsc_end);
}
total_time = ts_ms(ts_diff(cal_start, cal_end));
total_cycles = (double)(tsc_end.int64-tsc_start.int64);
CPS = total_cycles / total_time;
printf("z == %f, CPS == %g\n", z, CPS);
return CPS;
}
/* ---------------------------------------------------------------------------
| End of measure_cps code
--------------------------------------------------------------------------- */
struct timespec diff(struct timespec start, struct timespec end)
{
struct timespec temp;
if ((end.tv_nsec-start.tv_nsec)<0) {
temp.tv_sec = end.tv_sec-start.tv_sec-1;
temp.tv_nsec = 1000000000+end.tv_nsec-start.tv_nsec;
} else {
temp.tv_sec = end.tv_sec-start.tv_sec;
temp.tv_nsec = end.tv_nsec-start.tv_nsec;
}
return temp;
} | .text
.file "shared_mmm.hip"
.globl _Z25__device_stub__MMM_kernelPfS_S_i # -- Begin function _Z25__device_stub__MMM_kernelPfS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__MMM_kernelPfS_S_i,@function
_Z25__device_stub__MMM_kernelPfS_S_i: # @_Z25__device_stub__MMM_kernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10MMM_kernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__MMM_kernelPfS_S_i, .Lfunc_end0-_Z25__device_stub__MMM_kernelPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI1_1:
.long 0x41200000 # float 10
.LCPI1_4:
.long 0x00000000 # float 0
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_2:
.quad 0x41cdcd6500000000 # double 1.0E+9
.LCPI1_3:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB1_1
# %bb.2:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, LEN(%rip)
testl %eax, %eax
jle .LBB1_3
# %bb.4:
testb $15, %al
je .LBB1_6
# %bb.5:
movl $.Lstr.1, %edi
jmp .LBB1_44
.LBB1_1:
movl $.Lstr.3, %edi
jmp .LBB1_44
.LBB1_3:
movl $.Lstr.2, %edi
.LBB1_44:
callq puts@PLT
.LBB1_45:
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_6:
.cfi_def_cfa_offset 160
movq %rax, %r13
callq _Z11measure_cpsv
movl LEN(%rip), %edi
testl %edi, %edi
jle .LBB1_9
# %bb.7:
imull %edi, %edi
movl $4, %esi
callq calloc
movq %rax, %rbx
testq %rax, %rax
jne .LBB1_10
# %bb.8:
movl $.Lstr.4, %edi
callq puts@PLT
.LBB1_9: # %_Z13matrix_createi.exit
xorl %ebx, %ebx
.LBB1_10: # %_Z13matrix_createi.exit
testq %rbx, %rbx
je .LBB1_45
# %bb.11:
movl LEN(%rip), %ebp
testl %ebp, %ebp
jle .LBB1_14
# %bb.12:
movl %ebp, %r14d
imull %r14d, %r14d
cmpl $1, %r14d
adcl $0, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_13: # =>This Inner Loop Header: Depth=1
callq random
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
mulss .LCPI1_1(%rip), %xmm0
addss .LCPI1_4(%rip), %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_13
# %bb.15: # %_Z11matrix_initPfi.exit
testl %ebp, %ebp
jg .LBB1_16
jmp .LBB1_45
.LBB1_14:
movl $.Lstr.5, %edi
callq puts@PLT
testl %ebp, %ebp
jle .LBB1_45
.LBB1_16:
movl LEN(%rip), %edi
testl %edi, %edi
jle .LBB1_19
# %bb.17:
imull %edi, %edi
movl $4, %esi
callq calloc
movq %rax, %r14
testq %rax, %rax
jne .LBB1_20
# %bb.18:
movl $.Lstr.4, %edi
callq puts@PLT
.LBB1_19: # %_Z13matrix_createi.exit71
xorl %r14d, %r14d
.LBB1_20: # %_Z13matrix_createi.exit71
testq %r14, %r14
je .LBB1_45
# %bb.21:
movl LEN(%rip), %ebp
testl %ebp, %ebp
jle .LBB1_24
# %bb.22:
movl %ebp, %r15d
imull %r15d, %r15d
cmpl $1, %r15d
adcl $0, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_23: # =>This Inner Loop Header: Depth=1
callq random
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
mulss .LCPI1_1(%rip), %xmm0
addss .LCPI1_4(%rip), %xmm0
movss %xmm0, (%r14,%r12,4)
incq %r12
cmpq %r12, %r15
jne .LBB1_23
jmp .LBB1_25
.LBB1_24:
movl $.Lstr.5, %edi
callq puts@PLT
.LBB1_25: # %_Z11matrix_initPfi.exit79
testl %ebp, %ebp
jle .LBB1_45
# %bb.26:
movl LEN(%rip), %edi
callq _Z13matrix_createi
testq %rax, %rax
je .LBB1_45
# %bb.27:
movq %rax, %r15
movl LEN(%rip), %ebp
testl %ebp, %ebp
jle .LBB1_29
# %bb.28: # %.loopexit.loopexit.i
movl %ebp, %edx
imull %edx, %edx
cmpl $1, %edx
adcl $0, %edx
shlq $2, %rdx
movq %r15, %rdi
xorl %esi, %esi
callq memset@PLT
jmp .LBB1_30
.LBB1_29:
movl $.Lstr.6, %edi
callq puts@PLT
.LBB1_30: # %_Z11matrix_zeroPfi.exit
testl %ebp, %ebp
jle .LBB1_45
# %bb.31:
movl LEN(%rip), %edi
callq _Z13matrix_createi
testq %rax, %rax
je .LBB1_45
# %bb.32:
movq %rax, %r12
movl LEN(%rip), %ebp
testl %ebp, %ebp
jle .LBB1_34
# %bb.33: # %.loopexit.loopexit.i85
movl %ebp, %edx
imull %edx, %edx
cmpl $1, %edx
adcl $0, %edx
shlq $2, %rdx
movq %r12, %rdi
xorl %esi, %esi
callq memset@PLT
jmp .LBB1_35
.LBB1_34:
movl $.Lstr.6, %edi
callq puts@PLT
.LBB1_35: # %_Z11matrix_zeroPfi.exit87
testl %ebp, %ebp
jle .LBB1_45
# %bb.36:
movq %r12, 64(%rsp) # 8-byte Spill
movl %r13d, %ebp
imull %r13d, %ebp
shll $2, %ebp
shrq $4, %r13
movq $0, 16(%rsp)
movq $0, 8(%rsp)
movq $0, (%rsp)
xorl %edi, %edi
callq hipSetDevice
movl $.L.str.3, %esi
movl %eax, %edi
movl $149, %edx
movl $1, %ecx
callq _Z9gpuAssert10hipError_tPcib
movslq %ebp, %r12
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movl $.L.str.3, %esi
movl %eax, %edi
movl $151, %edx
movl $1, %ecx
callq _Z9gpuAssert10hipError_tPcib
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movl $.L.str.3, %esi
movl %eax, %edi
movl $152, %edx
movl $1, %ecx
callq _Z9gpuAssert10hipError_tPcib
movq %rsp, %rdi
movq %r12, %rsi
callq hipMalloc
movl $.L.str.3, %esi
movl %eax, %edi
movl $153, %edx
movl $1, %ecx
callq _Z9gpuAssert10hipError_tPcib
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 56(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 32(%rsp), %rdi
callq hipEventCreate
andl $268435455, %r13d # imm = 0xFFFFFFF
movq %r13, %rbp
shlq $32, %rbp
orq %r13, %rbp
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movl $.L.str.3, %esi
movl %eax, %edi
movl $166, %edx
movl $1, %ecx
callq _Z9gpuAssert10hipError_tPcib
movq 8(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movl $.L.str.3, %esi
movl %eax, %edi
movl $167, %edx
movl $1, %ecx
callq _Z9gpuAssert10hipError_tPcib
movq 56(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $68719476752, %rdx # imm = 0x1000000010
movq %rbp, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_38
# %bb.37:
movq 16(%rsp), %rdi
movq 8(%rsp), %rsi
movq (%rsp), %rdx
movl LEN(%rip), %ecx
callq _Z25__device_stub__MMM_kernelPfS_S_i
.LBB1_38: # %_Z7ts_diff8timespecS_.exit
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rdi
callq hipEventSynchronize
callq hipPeekAtLastError
movl $.L.str.3, %esi
movl %eax, %edi
movl $174, %edx
movl $1, %ecx
callq _Z9gpuAssert10hipError_tPcib
callq hipDeviceSynchronize
movl $.L.str.3, %esi
movl %eax, %edi
movl $175, %edx
movl $1, %ecx
callq _Z9gpuAssert10hipError_tPcib
movq (%rsp), %rsi
movq 64(%rsp), %rdi # 8-byte Reload
movq %r12, %rdx
movq %rdi, %r12
movl $2, %ecx
callq hipMemcpy
movl $.L.str.3, %esi
movl %eax, %edi
movl $177, %edx
movl $1, %ecx
callq _Z9gpuAssert10hipError_tPcib
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 56(%rsp), %rsi
movq 32(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
movq 40(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 52(%rsp), %rdi
callq hipEventElapsedTime
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movss 52(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
movq 40(%rsp), %rdi
callq hipEventDestroy
movq 24(%rsp), %rdi
callq hipEventDestroy
leaq 88(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movl LEN(%rip), %ecx
movq %rbx, %rdi
movq %r14, %rsi
movq %r15, %rdx
callq _Z7MMM_CPUPfS_S_i
leaq 72(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movq 88(%rsp), %rax
movq 80(%rsp), %rcx
subq 96(%rsp), %rcx
leaq 1000000000(%rcx), %rdx
movq %rax, %rsi
negq %rsi
testq %rcx, %rcx
notq %rax
cmovnsq %rsi, %rax
cmovnsq %rcx, %rdx
addq 72(%rsp), %rax
cvtsi2sd %rax, %xmm1
mulsd .LCPI1_2(%rip), %xmm1
xorps %xmm0, %xmm0
cvtsi2sd %rdx, %xmm0
addsd %xmm1, %xmm0
divsd .LCPI1_3(%rip), %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movl LEN(%rip), %eax
testl %eax, %eax
je .LBB1_43
# %bb.39: # %.lr.ph
imull %eax, %eax
movq %r15, %rcx
subq %r12, %rcx
cmpl $1, %eax
adcl $0, %eax
.LBB1_40: # =>This Inner Loop Header: Depth=1
testq %rcx, %rcx
jg .LBB1_41
# %bb.42: # in Loop: Header=BB1_40 Depth=1
decl %eax
jne .LBB1_40
.LBB1_43: # %._crit_edge
movq 16(%rsp), %rdi
callq hipFree
movl $.L.str.3, %esi
movl %eax, %edi
movl $210, %edx
movl $1, %ecx
callq _Z9gpuAssert10hipError_tPcib
movq 8(%rsp), %rdi
callq hipFree
movl $.L.str.3, %esi
movl %eax, %edi
movl $211, %edx
movl $1, %ecx
callq _Z9gpuAssert10hipError_tPcib
movq (%rsp), %rdi
callq hipFree
movl $.L.str.3, %esi
movl %eax, %edi
movl $212, %edx
movl $1, %ecx
callq _Z9gpuAssert10hipError_tPcib
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r12, %rdi
callq free
movq %r15, %rdi
callq free
movl $.Lstr, %edi
jmp .LBB1_44
.LBB1_41:
movl $.L.str.7, %edi
xorl %esi, %esi
movq %r15, %rdx
movq %r12, %rcx
xorl %eax, %eax
callq printf
jmp .LBB1_45
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z11measure_cpsv
.LCPI2_0:
.quad 0xbffd8afcb200d2ee # double -1.8464323952913975
.LCPI2_1:
.quad 0x41cdcd6500000000 # double 1.0E+9
.LCPI2_2:
.quad 0x412e848000000000 # double 1.0E+6
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI2_3:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI2_4:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.text
.globl _Z11measure_cpsv
.p2align 4, 0x90
.type _Z11measure_cpsv,@function
_Z11measure_cpsv: # @_Z11measure_cpsv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $48, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorpd %xmm0, %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
xorl %r12d, %r12d
leaq 32(%rsp), %r14
leaq 16(%rsp), %r15
.p2align 4, 0x90
.LBB2_1: # =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
movl $2, %edi
movq %r14, %rsi
callq clock_gettime
movl $50000000, %ecx # imm = 0x2FAF080
#APP
rdtsc
#NO_APP
movl %edx, %ebx
movl %eax, %ebp
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
mulsd %xmm0, %xmm0
addsd %xmm1, %xmm0
decq %rcx
jne .LBB2_2
# %bb.3: # in Loop: Header=BB2_1 Depth=1
movsd %xmm0, 8(%rsp) # 8-byte Spill
movl $2, %edi
movq %r15, %rsi
callq clock_gettime
#APP
rdtsc
#NO_APP
# kill: def $edx killed $edx def $rdx
leaq 1(%r12), %rcx
testq %r12, %r12
movq %rcx, %r12
je .LBB2_1
# %bb.4: # %_Z7ts_diff8timespecS_.exit
movq 32(%rsp), %rcx
movq 24(%rsp), %rsi
subq 40(%rsp), %rsi
leaq 1000000000(%rsi), %rdi
movq %rcx, %r8
negq %r8
testq %rsi, %rsi
notq %rcx
cmovnsq %r8, %rcx
cmovnsq %rsi, %rdi
addq 16(%rsp), %rcx
xorps %xmm1, %xmm1
cvtsi2sd %rcx, %xmm1
mulsd .LCPI2_1(%rip), %xmm1
xorps %xmm0, %xmm0
cvtsi2sd %rdi, %xmm0
addsd %xmm1, %xmm0
divsd .LCPI2_2(%rip), %xmm0
shlq $32, %rdx
movl %eax, %eax
orq %rdx, %rax
negl %ebx
shlq $32, %rbx
movl %ebp, %ecx
subq %rcx, %rax
addq %rbx, %rax
movq %rax, %xmm2
punpckldq .LCPI2_3(%rip), %xmm2 # xmm2 = xmm2[0],mem[0],xmm2[1],mem[1]
subpd .LCPI2_4(%rip), %xmm2
movapd %xmm2, %xmm1
unpckhpd %xmm2, %xmm1 # xmm1 = xmm1[1],xmm2[1]
addsd %xmm2, %xmm1
divsd %xmm0, %xmm1
movsd %xmm1, CPS(%rip)
movl $.L.str.13, %edi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $2, %al
callq printf
movsd CPS(%rip), %xmm0 # xmm0 = mem[0],zero
addq $48, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z11measure_cpsv, .Lfunc_end2-_Z11measure_cpsv
.cfi_endproc
# -- End function
.globl _Z13matrix_createi # -- Begin function _Z13matrix_createi
.p2align 4, 0x90
.type _Z13matrix_createi,@function
_Z13matrix_createi: # @_Z13matrix_createi
.cfi_startproc
# %bb.0:
# kill: def $edi killed $edi def $rdi
testl %edi, %edi
jle .LBB3_1
# %bb.3:
pushq %rax
.cfi_def_cfa_offset 16
imull %edi, %edi
movl $4, %esi
callq calloc
testq %rax, %rax
je .LBB3_4
# %bb.5:
addq $8, %rsp
.cfi_def_cfa_offset 8
retq
.LBB3_1:
xorl %eax, %eax
retq
.LBB3_4:
.cfi_def_cfa_offset 16
movl $.Lstr.4, %edi
callq puts@PLT
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z13matrix_createi, .Lfunc_end3-_Z13matrix_createi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z11matrix_initPfi
.LCPI4_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI4_1:
.long 0x41200000 # float 10
.LCPI4_2:
.long 0x00000000 # float 0
.text
.globl _Z11matrix_initPfi
.p2align 4, 0x90
.type _Z11matrix_initPfi,@function
_Z11matrix_initPfi: # @_Z11matrix_initPfi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
testl %esi, %esi
jle .LBB4_4
# %bb.1:
movl %esi, %ebx
movq %rdi, %r14
imull %ebx, %ebx
cmpl $1, %ebx
adcl $0, %ebx
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_2: # =>This Inner Loop Header: Depth=1
callq random
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
mulss .LCPI4_0(%rip), %xmm0
mulss .LCPI4_1(%rip), %xmm0
addss .LCPI4_2(%rip), %xmm0
movss %xmm0, (%r14,%r15,4)
incq %r15
cmpq %r15, %rbx
jne .LBB4_2
# %bb.3:
movl $1, %eax
jmp .LBB4_5
.LBB4_4:
movl $.Lstr.5, %edi
callq puts@PLT
xorl %eax, %eax
.LBB4_5: # %.loopexit
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z11matrix_initPfi, .Lfunc_end4-_Z11matrix_initPfi
.cfi_endproc
# -- End function
.globl _Z11matrix_zeroPfi # -- Begin function _Z11matrix_zeroPfi
.p2align 4, 0x90
.type _Z11matrix_zeroPfi,@function
_Z11matrix_zeroPfi: # @_Z11matrix_zeroPfi
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
testl %esi, %esi
jle .LBB5_2
# %bb.1: # %.loopexit.loopexit
movl %esi, %edx
imull %edx, %edx
cmpl $1, %edx
adcl $0, %edx
shlq $2, %rdx
xorl %esi, %esi
callq memset@PLT
movl $1, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.LBB5_2:
.cfi_def_cfa_offset 16
movl $.Lstr.6, %edi
callq puts@PLT
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z11matrix_zeroPfi, .Lfunc_end5-_Z11matrix_zeroPfi
.cfi_endproc
# -- End function
.section .text._Z9gpuAssert10hipError_tPcib,"axG",@progbits,_Z9gpuAssert10hipError_tPcib,comdat
.weak _Z9gpuAssert10hipError_tPcib # -- Begin function _Z9gpuAssert10hipError_tPcib
.p2align 4, 0x90
.type _Z9gpuAssert10hipError_tPcib,@function
_Z9gpuAssert10hipError_tPcib: # @_Z9gpuAssert10hipError_tPcib
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
testl %edi, %edi
jne .LBB6_1
.LBB6_2:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB6_1:
.cfi_def_cfa_offset 48
movq stderr(%rip), %r14
movl %edi, %ebx
movl %ecx, %r12d
movl %edx, %ebp
movq %rsi, %r15
callq hipGetErrorString
movl $.L.str.14, %esi
movq %r14, %rdi
movq %rax, %rdx
movq %r15, %rcx
movl %ebp, %r8d
xorl %eax, %eax
callq fprintf
testb %r12b, %r12b
je .LBB6_2
# %bb.3:
movl %ebx, %edi
callq exit
.Lfunc_end6:
.size _Z9gpuAssert10hipError_tPcib, .Lfunc_end6-_Z9gpuAssert10hipError_tPcib
.cfi_endproc
# -- End function
.text
.globl _Z7MMM_CPUPfS_S_i # -- Begin function _Z7MMM_CPUPfS_S_i
.p2align 4, 0x90
.type _Z7MMM_CPUPfS_S_i,@function
_Z7MMM_CPUPfS_S_i: # @_Z7MMM_CPUPfS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB7_8
# %bb.1: # %.preheader23.lr.ph
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %eax
leaq (,%rax,4), %r8
xorl %r9d, %r9d
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB7_2: # %.preheader23
# =>This Loop Header: Depth=1
# Child Loop BB7_3 Depth 2
# Child Loop BB7_4 Depth 3
movl %r9d, %r11d
leaq (%rdi,%r11,4), %r11
movq %r10, %rbx
imulq %rax, %rbx
leaq (%rdx,%rbx,4), %rbx
movq %rsi, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB7_3: # %.preheader
# Parent Loop BB7_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB7_4 Depth 3
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %r14, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB7_4: # Parent Loop BB7_2 Depth=1
# Parent Loop BB7_3 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r11,%r13,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r12), %xmm1
addss %xmm1, %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r13
addq %r8, %r12
cmpq %r13, %rax
jne .LBB7_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB7_3 Depth=2
incq %r15
addq $4, %r14
cmpq %rax, %r15
jne .LBB7_3
# %bb.6: # %._crit_edge26
# in Loop: Header=BB7_2 Depth=1
incq %r10
addl %ecx, %r9d
cmpq %rax, %r10
jne .LBB7_2
# %bb.7:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.LBB7_8: # %._crit_edge28
retq
.Lfunc_end7:
.size _Z7MMM_CPUPfS_S_i, .Lfunc_end7-_Z7MMM_CPUPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z5ts_ms8timespec
.LCPI8_0:
.quad 0x41cdcd6500000000 # double 1.0E+9
.LCPI8_1:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z5ts_ms8timespec
.p2align 4, 0x90
.type _Z5ts_ms8timespec,@function
_Z5ts_ms8timespec: # @_Z5ts_ms8timespec
.cfi_startproc
# %bb.0:
cvtsi2sd %rdi, %xmm1
mulsd .LCPI8_0(%rip), %xmm1
cvtsi2sd %rsi, %xmm0
addsd %xmm1, %xmm0
divsd .LCPI8_1(%rip), %xmm0
retq
.Lfunc_end8:
.size _Z5ts_ms8timespec, .Lfunc_end8-_Z5ts_ms8timespec
.cfi_endproc
# -- End function
.globl _Z7ts_diff8timespecS_ # -- Begin function _Z7ts_diff8timespecS_
.p2align 4, 0x90
.type _Z7ts_diff8timespecS_,@function
_Z7ts_diff8timespecS_: # @_Z7ts_diff8timespecS_
.cfi_startproc
# %bb.0:
movq %rdx, %r8
movq %rdi, %rax
movq %rcx, %rdx
subq %rsi, %rdx
js .LBB9_1
# %bb.2:
subq %rax, %r8
movq %r8, %rax
retq
.LBB9_1:
notq %rax
addq %r8, %rax
subq %rsi, %rcx
addq $1000000000, %rcx # imm = 0x3B9ACA00
movq %rcx, %rdx
retq
.Lfunc_end9:
.size _Z7ts_diff8timespecS_, .Lfunc_end9-_Z7ts_diff8timespecS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z10float_randff
.LCPI10_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl _Z10float_randff
.p2align 4, 0x90
.type _Z10float_randff,@function
_Z10float_randff: # @_Z10float_randff
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm1, 4(%rsp) # 4-byte Spill
movss %xmm0, (%rsp) # 4-byte Spill
callq random
xorps %xmm1, %xmm1
cvtsi2ss %rax, %xmm1
mulss .LCPI10_0(%rip), %xmm1
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss (%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
subss %xmm2, %xmm0
mulss %xmm1, %xmm0
addss %xmm2, %xmm0
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end10:
.size _Z10float_randff, .Lfunc_end10-_Z10float_randff
.cfi_endproc
# -- End function
.globl _Z11matrix_copyPfS_i # -- Begin function _Z11matrix_copyPfS_i
.p2align 4, 0x90
.type _Z11matrix_copyPfS_i,@function
_Z11matrix_copyPfS_i: # @_Z11matrix_copyPfS_i
.cfi_startproc
# %bb.0:
# kill: def $edx killed $edx def $rdx
testl %edx, %edx
jle .LBB11_4
# %bb.1:
imull %edx, %edx
cmpl $1, %edx
adcl $0, %edx
xorl %eax, %eax
.p2align 4, 0x90
.LBB11_2: # =>This Inner Loop Header: Depth=1
movss (%rdi,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%rsi,%rax,4)
incq %rax
cmpq %rax, %rdx
jne .LBB11_2
# %bb.3:
movl $1, %eax
retq
.LBB11_4:
pushq %rax
.cfi_def_cfa_offset 16
movl $.Lstr.7, %edi
callq puts@PLT
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end11:
.size _Z11matrix_copyPfS_i, .Lfunc_end11-_Z11matrix_copyPfS_i
.cfi_endproc
# -- End function
.globl _Z4diff8timespecS_ # -- Begin function _Z4diff8timespecS_
.p2align 4, 0x90
.type _Z4diff8timespecS_,@function
_Z4diff8timespecS_: # @_Z4diff8timespecS_
.cfi_startproc
# %bb.0:
movq %rdx, %r8
movq %rdi, %rax
movq %rcx, %rdx
subq %rsi, %rdx
js .LBB12_1
# %bb.2:
subq %rax, %r8
movq %r8, %rax
retq
.LBB12_1:
notq %rax
addq %r8, %rax
subq %rsi, %rcx
addq $1000000000, %rcx # imm = 0x3B9ACA00
movq %rcx, %rdx
retq
.Lfunc_end12:
.size _Z4diff8timespecS_, .Lfunc_end12-_Z4diff8timespecS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB13_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB13_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10MMM_kernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end13:
.size __hip_module_ctor, .Lfunc_end13-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB14_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB14_2:
retq
.Lfunc_end14:
.size __hip_module_dtor, .Lfunc_end14-__hip_module_dtor
.cfi_endproc
# -- End function
.type CPS,@object # @CPS
.data
.globl CPS
.p2align 3, 0x0
CPS:
.quad 0x41e59b4fa0000000 # double 2.9E+9
.size CPS, 8
.type LEN,@object # @LEN
.bss
.globl LEN
.p2align 2, 0x0
LEN:
.long 0 # 0x0
.size LEN, 4
.type _Z10MMM_kernelPfS_S_i,@object # @_Z10MMM_kernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z10MMM_kernelPfS_S_i
.p2align 3, 0x0
_Z10MMM_kernelPfS_S_i:
.quad _Z25__device_stub__MMM_kernelPfS_S_i
.size _Z10MMM_kernelPfS_S_i, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/jsburke/ec527_lab_private/master/lab8/final/code/shared_mmm.hip"
.size .L.str.3, 121
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\nGPU MMM Time: %f ms"
.size .L.str.4, 22
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\nGPU FUll Time: %f ms"
.size .L.str.5, 22
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\nCPU Time: %lf ms\n"
.size .L.str.6, 19
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "\nResult verification issue at element %d | CPU: %f | GPU: %f\n"
.size .L.str.7, 62
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "z == %f, CPS == %g\n"
.size .L.str.13, 20
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "CUDA_SAFE_CALL: %s %s %d\n"
.size .L.str.14, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10MMM_kernelPfS_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nDone"
.size .Lstr, 6
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\nOdd Numbr of blocks"
.size .Lstr.1, 21
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\nLength must be greater than zero"
.size .Lstr.2, 34
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "\nPlease pass a length in."
.size .Lstr.3, 26
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "\n\tFailed to allocate array"
.size .Lstr.4, 27
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "\nError in initializing matrix"
.size .Lstr.5, 30
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "\nFailed to zero matrix"
.size .Lstr.6, 23
.type .Lstr.7,@object # @str.7
.Lstr.7:
.asciz "\nFailed to copy matrix"
.size .Lstr.7, 23
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__MMM_kernelPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10MMM_kernelPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10MMM_kernelPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002600 */
/*0020*/ MOV R19, c[0x0][0x178] ; /* 0x00005e0000137a02 */
/* 0x000fe20000000f00 */
/*0030*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0040*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R17, SR_TID.Y ; /* 0x0000000000117919 */
/* 0x000e220000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R19, 0x10, PT ; /* 0x000000101300780c */
/* 0x000fe20003f06270 */
/*0070*/ HFMA2.MMA R23, -RZ, RZ, 0, 0 ; /* 0x00000000ff177435 */
/* 0x000fe400000001ff */
/*0080*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e680000002500 */
/*0090*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*00a0*/ LEA R5, R5, R17, 0x4 ; /* 0x0000001105057211 */
/* 0x001fc400078e20ff */
/*00b0*/ LEA R2, R7, R0, 0x4 ; /* 0x0000000007027211 */
/* 0x002fca00078e20ff */
/*00c0*/ IMAD R2, R5, c[0x0][0x178], R2 ; /* 0x00005e0005027a24 */
/* 0x000fc800078e0202 */
/*00d0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fe200078e0203 */
/*00e0*/ @!P0 BRA 0x4f0 ; /* 0x0000040000008947 */
/* 0x000fea0003800000 */
/*00f0*/ MOV R13, 0x4 ; /* 0x00000004000d7802 */
/* 0x000fe20000000f00 */
/*0100*/ IMAD R14, R5, c[0x0][0x178], R0.reuse ; /* 0x00005e00050e7a24 */
/* 0x100fe200078e0200 */
/*0110*/ SHF.R.S32.HI R5, RZ, 0x1f, R19 ; /* 0x0000001fff057819 */
/* 0x000fe20000011413 */
/*0120*/ IMAD R4, R17.reuse, c[0x0][0x178], R0 ; /* 0x00005e0011047a24 */
/* 0x040fe200078e0200 */
/*0130*/ SHF.L.U32 R17, R17, 0x6, RZ ; /* 0x0000000611117819 */
/* 0x000fe200000006ff */
/*0140*/ IMAD.WIDE R14, R14, R13, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x000fe200078e020d */
/*0150*/ LEA.HI R5, R5, c[0x0][0x178], RZ, 0x4 ; /* 0x00005e0005057a11 */
/* 0x000fe200078f20ff */
/*0160*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0170*/ LEA R4, R7, R4, 0x4 ; /* 0x0000000407047211 */
/* 0x000fe400078e20ff */
/*0180*/ MOV R21, R15 ; /* 0x0000000f00157202 */
/* 0x000fc40000000f00 */
/*0190*/ SHF.L.U32 R19, R19, 0x4, RZ ; /* 0x0000000413137819 */
/* 0x000fe200000006ff */
/*01a0*/ IMAD.WIDE R12, R4, R13, c[0x0][0x168] ; /* 0x00005a00040c7625 */
/* 0x000fe200078e020d */
/*01b0*/ MOV R23, RZ ; /* 0x000000ff00177202 */
/* 0x000fe40000000f00 */
/*01c0*/ LEA R16, R0, R17, 0x2 ; /* 0x0000001100107211 */
/* 0x000fe400078e10ff */
/*01d0*/ SHF.R.S32.HI R15, RZ, 0x4, R5 ; /* 0x00000004ff0f7819 */
/* 0x000fe40000011405 */
/*01e0*/ MOV R20, R14 ; /* 0x0000000e00147202 */
/* 0x000fe20000000f00 */
/*01f0*/ LDG.E R24, [R12.64] ; /* 0x000000060c187981 */
/* 0x0000a8000c1e1900 */
/*0200*/ LDG.E R27, [R20.64] ; /* 0x00000006141b7981 */
/* 0x0002e2000c1e1900 */
/*0210*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*0220*/ IADD3 R14, P1, R14, 0x40, RZ ; /* 0x000000400e0e7810 */
/* 0x000fe20007f3e0ff */
/*0230*/ IMAD.WIDE R12, R19, 0x4, R12 ; /* 0x00000004130c7825 */
/* 0x001fc800078e020c */
/*0240*/ ISETP.LE.AND P0, PT, R15, UR4, PT ; /* 0x000000040f007c0c */
/* 0x000fe4000bf03270 */
/*0250*/ IADD3.X R21, RZ, R21, RZ, P1, !PT ; /* 0x00000015ff157210 */
/* 0x002fe20000ffe4ff */
/*0260*/ STS [R16+0x400], R24 ; /* 0x0004001810007388 */
/* 0x004fe80000000800 */
/*0270*/ STS [R16], R27 ; /* 0x0000001b10007388 */
/* 0x008fe80000000800 */
/*0280*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0290*/ LDS R26, [R0.X4+0x400] ; /* 0x00040000001a7984 */
/* 0x000fe80000004800 */
/*02a0*/ LDS.128 R8, [R17] ; /* 0x0000000011087984 */
/* 0x000e280000000c00 */
/*02b0*/ LDS R28, [R0.X4+0x440] ; /* 0x00044000001c7984 */
/* 0x000e680000004800 */
/*02c0*/ LDS R29, [R0.X4+0x480] ; /* 0x00048000001d7984 */
/* 0x000ea80000004800 */
/*02d0*/ LDS R22, [R0.X4+0x4c0] ; /* 0x0004c00000167984 */
/* 0x000ee80000004800 */
/*02e0*/ LDS R25, [R0.X4+0x500] ; /* 0x0005000000197984 */
/* 0x000fe80000004800 */
/*02f0*/ LDS.128 R4, [R17+0x10] ; /* 0x0000100011047984 */
/* 0x000f280000000c00 */
/*0300*/ LDS R18, [R0.X4+0x540] ; /* 0x0005400000127984 */
/* 0x000f680000004800 */
/*0310*/ LDS R27, [R0.X4+0x580] ; /* 0x00058000001b7984 */
/* 0x000f680000004800 */
/*0320*/ LDS R20, [R0.X4+0x5c0] ; /* 0x0005c00000147984 */
/* 0x000f620000004800 */
/*0330*/ FFMA R8, R26, R8, R23 ; /* 0x000000081a087223 */
/* 0x001fc60000000017 */
/*0340*/ LDS R23, [R0.X4+0x600] ; /* 0x0006000000177984 */
/* 0x000fe20000004800 */
/*0350*/ FFMA R8, R28, R9, R8 ; /* 0x000000091c087223 */
/* 0x002fc80000000008 */
/*0360*/ FFMA R8, R29, R10, R8 ; /* 0x0000000a1d087223 */
/* 0x004fc80000000008 */
/*0370*/ FFMA R22, R22, R11, R8 ; /* 0x0000000b16167223 */
/* 0x008fe40000000008 */
/*0380*/ LDS.128 R8, [R17+0x20] ; /* 0x0000200011087984 */
/* 0x000e240000000c00 */
/*0390*/ FFMA R4, R25, R4, R22 ; /* 0x0000000419047223 */
/* 0x010fe40000000016 */
/*03a0*/ LDS R22, [R0.X4+0x640] ; /* 0x0006400000167984 */
/* 0x000e640000004800 */
/*03b0*/ FFMA R4, R18, R5, R4 ; /* 0x0000000512047223 */
/* 0x020fe40000000004 */
/*03c0*/ LDS R25, [R0.X4+0x680] ; /* 0x0006800000197984 */
/* 0x000ea40000004800 */
/*03d0*/ FFMA R4, R27, R6, R4 ; /* 0x000000061b047223 */
/* 0x000fc40000000004 */
/*03e0*/ LDS R18, [R0.X4+0x6c0] ; /* 0x0006c00000127984 */
/* 0x000ee40000004800 */
/*03f0*/ FFMA R24, R20, R7, R4 ; /* 0x0000000714187223 */
/* 0x000fe40000000004 */
/*0400*/ LDS R27, [R0.X4+0x700] ; /* 0x00070000001b7984 */
/* 0x000fe80000004800 */
/*0410*/ LDS.128 R4, [R17+0x30] ; /* 0x0000300011047984 */
/* 0x000f280000000c00 */
/*0420*/ LDS R20, [R0.X4+0x740] ; /* 0x0007400000147984 */
/* 0x000f620000004800 */
/*0430*/ FFMA R24, R23, R8, R24 ; /* 0x0000000817187223 */
/* 0x001fc60000000018 */
/*0440*/ LDS R23, [R0.X4+0x780] ; /* 0x0007800000177984 */
/* 0x000e280000004800 */
/*0450*/ LDS R8, [R0.X4+0x7c0] ; /* 0x0007c00000087984 */
/* 0x000e220000004800 */
/*0460*/ FFMA R9, R22, R9, R24 ; /* 0x0000000916097223 */
/* 0x002fc80000000018 */
/*0470*/ FFMA R9, R25, R10, R9 ; /* 0x0000000a19097223 */
/* 0x004fc80000000009 */
/*0480*/ FFMA R9, R18, R11, R9 ; /* 0x0000000b12097223 */
/* 0x008fc80000000009 */
/*0490*/ FFMA R4, R27, R4, R9 ; /* 0x000000041b047223 */
/* 0x010fc80000000009 */
/*04a0*/ FFMA R4, R20, R5, R4 ; /* 0x0000000514047223 */
/* 0x020fc80000000004 */
/*04b0*/ FFMA R23, R23, R6, R4 ; /* 0x0000000617177223 */
/* 0x001fc80000000004 */
/*04c0*/ FFMA R23, R8, R7, R23 ; /* 0x0000000708177223 */
/* 0x000fe20000000017 */
/*04d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04e0*/ @!P0 BRA 0x1e0 ; /* 0xfffffcf000008947 */
/* 0x000fea000383ffff */
/*04f0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x000fe2000c101906 */
/*0500*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0510*/ BRA 0x510; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10MMM_kernelPfS_S_i
.globl _Z10MMM_kernelPfS_S_i
.p2align 8
.type _Z10MMM_kernelPfS_S_i,@function
_Z10MMM_kernelPfS_S_i:
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v5, v0, 10, 10
v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v3, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v4, s15, 4, v5
v_lshl_add_u32 v0, s14, 4, v3
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 16
s_cbranch_scc1 .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v8, 2, v3
v_lshlrev_b32_e32 v6, 6, v5
s_ashr_i32 s3, s2, 31
v_mad_u64_u32 v[1:2], null, v4, s2, v[3:4]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v7, 0x400, v8
s_lshr_b32 s3, s3, 28
v_add_nc_u32_e32 v3, v6, v8
s_add_i32 s3, s2, s3
v_add_nc_u32_e32 v8, v7, v6
s_ashr_i32 s3, s3, 4
s_mov_b32 s8, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
s_lshl_b32 s9, s8, 4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v10, s9, v5
v_add_nc_u32_e32 v9, s9, v1
s_mov_b32 s9, 0
v_mad_u64_u32 v[11:12], null, v10, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v12, 31, v11
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, vcc_lo, s4, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v11, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
global_load_b32 v10, v[9:10], off
global_load_b32 v11, v[11:12], off
v_mov_b32_e32 v9, v7
s_waitcnt vmcnt(1)
ds_store_b32 v3, v10
s_waitcnt vmcnt(0)
ds_store_b32 v8, v11
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3:
v_add_nc_u32_e32 v10, s9, v6
s_add_i32 s9, s9, 4
ds_load_b32 v11, v9
ds_load_b32 v10, v10
v_add_nc_u32_e32 v9, 64, v9
s_cmp_eq_u32 s9, 64
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, v10, v11
s_cbranch_scc0 .LBB0_3
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s8, s3
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[5:6], null, v4, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[0:1], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10MMM_kernelPfS_S_i
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10MMM_kernelPfS_S_i, .Lfunc_end0-_Z10MMM_kernelPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10MMM_kernelPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10MMM_kernelPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__ void maxPerRow(double *values, int *gl_max, int n){
// Get our global thread ID
int id = blockIdx.x*blockDim.x+threadIdx.x;
int val = values[id];
//figure this out
if(id < n)
atomicMax(&gl_max[blockIdx.x], val);
}
int main( int argc, char* argv[] ){
// variable size of matrix < 1024
int col_size = 10, row_size = 1024;
//check that sizes are correct
if(col_size > 1025 || row_size > 1025){
printf("size not valid\n");
return 1;
}
//how many data points there are row*col
int data_size = col_size * row_size;
// Host input matrix
double *h_a;
//Host output matrix
int *h_c;
// Device input matrix
double *d_a;
//Device output matrix
int *d_c;
// Size, in bytes, of each matrix
size_t bytes_input = data_size*sizeof(double);
size_t bytes_output = col_size*sizeof(int);
// Allocate memory for each matrix on host
h_a = (double*)malloc(bytes_input);
h_c = (int*)malloc(bytes_output);
// Allocate memory for each matrix on GPU
cudaMalloc(&d_a, bytes_input);
cudaMalloc(&d_c, bytes_output);
int row_id;
// Initialize matrix on host
// Simple initialize for now
for( row_id = 0; row_id < data_size; row_id++ ) {
h_a[row_id] = 4;
}
// initialize output to zeroes
for(row_id = 0; row_id < col_size; row_id++){
h_c[row_id] = 0;
}
//some max values to test
h_a[4] = 19;
h_a[16] = 21;
h_a[98] = 49;
// Copy host matrices to device
cudaMemcpy( d_a, h_a, bytes_input, cudaMemcpyHostToDevice);
cudaMemcpy( d_c, h_c, bytes_output, cudaMemcpyHostToDevice);
// Initialize grid and block
int blockSize, gridSize;
// Number of threads in each thread block
blockSize = 1024;
// Number of thread blocks in grid 1024 height*width/blockSize
gridSize = (int)ceil(data_size/(float)blockSize);
// Execute the kernel add each thread for one output
maxPerRow<<<gridSize, col_size>>>(d_a, d_c, data_size);
// Copy result back to host
cudaMemcpy( h_c, d_c, bytes_output, cudaMemcpyDeviceToHost );
// print out data
for(row_id = 0; row_id < col_size; row_id++){
printf("%d ", (int)h_c[row_id]);
}
printf("\n done\n");
// Release device memory
cudaFree(d_a);
cudaFree(d_c);
// Release host memory
free(h_a);
free(h_c);
return 0;
} | code for sm_80
Function : _Z9maxPerRowPdPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R4, c[0x0][0x0], R3 ; /* 0x0000000004027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0203 */
/*0090*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe400038e0100 */
/*00b0*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fe200080e0000 */
/*00c0*/ S2R R5, SR_LANEID ; /* 0x0000000000057919 */
/* 0x000e2a0000000000 */
/*00d0*/ ISETP.EQ.U32.AND P0, PT, R5, UR4, PT ; /* 0x0000000405007c0c */
/* 0x001fe2000bf02070 */
/*00e0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fd400000001ff */
/*00f0*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe200078e0005 */
/*0100*/ F2I.F64.TRUNC R0, R2 ; /* 0x0000000200007311 */
/* 0x004e24000030d100 */
/*0110*/ REDUX.MAX.S32 UR5, R0 ; /* 0x00000000000573c4 */
/* 0x001e240000014200 */
/*0120*/ MOV R7, UR5 ; /* 0x0000000500077c02 */
/* 0x001fca0008000f00 */
/*0130*/ @P0 RED.E.MAX.S32.STRONG.GPU [R4.64], R7 ; /* 0x000000070400098e */
/* 0x000fe2000d10e386 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__ void maxPerRow(double *values, int *gl_max, int n){
// Get our global thread ID
int id = blockIdx.x*blockDim.x+threadIdx.x;
int val = values[id];
//figure this out
if(id < n)
atomicMax(&gl_max[blockIdx.x], val);
}
int main( int argc, char* argv[] ){
// variable size of matrix < 1024
int col_size = 10, row_size = 1024;
//check that sizes are correct
if(col_size > 1025 || row_size > 1025){
printf("size not valid\n");
return 1;
}
//how many data points there are row*col
int data_size = col_size * row_size;
// Host input matrix
double *h_a;
//Host output matrix
int *h_c;
// Device input matrix
double *d_a;
//Device output matrix
int *d_c;
// Size, in bytes, of each matrix
size_t bytes_input = data_size*sizeof(double);
size_t bytes_output = col_size*sizeof(int);
// Allocate memory for each matrix on host
h_a = (double*)malloc(bytes_input);
h_c = (int*)malloc(bytes_output);
// Allocate memory for each matrix on GPU
cudaMalloc(&d_a, bytes_input);
cudaMalloc(&d_c, bytes_output);
int row_id;
// Initialize matrix on host
// Simple initialize for now
for( row_id = 0; row_id < data_size; row_id++ ) {
h_a[row_id] = 4;
}
// initialize output to zeroes
for(row_id = 0; row_id < col_size; row_id++){
h_c[row_id] = 0;
}
//some max values to test
h_a[4] = 19;
h_a[16] = 21;
h_a[98] = 49;
// Copy host matrices to device
cudaMemcpy( d_a, h_a, bytes_input, cudaMemcpyHostToDevice);
cudaMemcpy( d_c, h_c, bytes_output, cudaMemcpyHostToDevice);
// Initialize grid and block
int blockSize, gridSize;
// Number of threads in each thread block
blockSize = 1024;
// Number of thread blocks in grid 1024 height*width/blockSize
gridSize = (int)ceil(data_size/(float)blockSize);
// Execute the kernel add each thread for one output
maxPerRow<<<gridSize, col_size>>>(d_a, d_c, data_size);
// Copy result back to host
cudaMemcpy( h_c, d_c, bytes_output, cudaMemcpyDeviceToHost );
// print out data
for(row_id = 0; row_id < col_size; row_id++){
printf("%d ", (int)h_c[row_id]);
}
printf("\n done\n");
// Release device memory
cudaFree(d_a);
cudaFree(d_c);
// Release host memory
free(h_a);
free(h_c);
return 0;
} | .file "tmpxft_000491f8_00000000-6_maxPerRow.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z9maxPerRowPdPiiPdPii
.type _Z31__device_stub__Z9maxPerRowPdPiiPdPii, @function
_Z31__device_stub__Z9maxPerRowPdPiiPdPii:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9maxPerRowPdPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z9maxPerRowPdPiiPdPii, .-_Z31__device_stub__Z9maxPerRowPdPiiPdPii
.globl _Z9maxPerRowPdPii
.type _Z9maxPerRowPdPii, @function
_Z9maxPerRowPdPii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9maxPerRowPdPiiPdPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9maxPerRowPdPii, .-_Z9maxPerRowPdPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "%d "
.LC5:
.string "\n done\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $81920, %edi
call malloc@PLT
movq %rax, %rbp
movl $40, %edi
call malloc@PLT
movq %rax, %r12
movq %rsp, %rdi
movl $81920, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movq %rbp, %rax
leaq 81920(%rbp), %rdx
movsd .LC0(%rip), %xmm0
.L12:
movsd %xmm0, (%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L12
movq %r12, %rbx
leaq 40(%r12), %r13
movq %r12, %rax
.L13:
movl $0, (%rax)
addq $4, %rax
cmpq %r13, %rax
jne .L13
movq .LC1(%rip), %rax
movq %rax, 32(%rbp)
movq .LC2(%rip), %rax
movq %rax, 128(%rbp)
movq .LC3(%rip), %rax
movq %rax, 784(%rbp)
movl $1, %ecx
movl $81920, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $40, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $10, 28(%rsp)
movl $1, 32(%rsp)
movl $10, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L14:
movl $2, %ecx
movl $40, %edx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq .LC4(%rip), %r14
.L15:
movl (%rbx), %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r13, %rbx
jne .L15
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl $10240, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z31__device_stub__Z9maxPerRowPdPiiPdPii
jmp .L14
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z9maxPerRowPdPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z9maxPerRowPdPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1074790400
.align 8
.LC1:
.long 0
.long 1077084160
.align 8
.LC2:
.long 0
.long 1077215232
.align 8
.LC3:
.long 0
.long 1078493184
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__ void maxPerRow(double *values, int *gl_max, int n){
// Get our global thread ID
int id = blockIdx.x*blockDim.x+threadIdx.x;
int val = values[id];
//figure this out
if(id < n)
atomicMax(&gl_max[blockIdx.x], val);
}
int main( int argc, char* argv[] ){
// variable size of matrix < 1024
int col_size = 10, row_size = 1024;
//check that sizes are correct
if(col_size > 1025 || row_size > 1025){
printf("size not valid\n");
return 1;
}
//how many data points there are row*col
int data_size = col_size * row_size;
// Host input matrix
double *h_a;
//Host output matrix
int *h_c;
// Device input matrix
double *d_a;
//Device output matrix
int *d_c;
// Size, in bytes, of each matrix
size_t bytes_input = data_size*sizeof(double);
size_t bytes_output = col_size*sizeof(int);
// Allocate memory for each matrix on host
h_a = (double*)malloc(bytes_input);
h_c = (int*)malloc(bytes_output);
// Allocate memory for each matrix on GPU
cudaMalloc(&d_a, bytes_input);
cudaMalloc(&d_c, bytes_output);
int row_id;
// Initialize matrix on host
// Simple initialize for now
for( row_id = 0; row_id < data_size; row_id++ ) {
h_a[row_id] = 4;
}
// initialize output to zeroes
for(row_id = 0; row_id < col_size; row_id++){
h_c[row_id] = 0;
}
//some max values to test
h_a[4] = 19;
h_a[16] = 21;
h_a[98] = 49;
// Copy host matrices to device
cudaMemcpy( d_a, h_a, bytes_input, cudaMemcpyHostToDevice);
cudaMemcpy( d_c, h_c, bytes_output, cudaMemcpyHostToDevice);
// Initialize grid and block
int blockSize, gridSize;
// Number of threads in each thread block
blockSize = 1024;
// Number of thread blocks in grid 1024 height*width/blockSize
gridSize = (int)ceil(data_size/(float)blockSize);
// Execute the kernel add each thread for one output
maxPerRow<<<gridSize, col_size>>>(d_a, d_c, data_size);
// Copy result back to host
cudaMemcpy( h_c, d_c, bytes_output, cudaMemcpyDeviceToHost );
// print out data
for(row_id = 0; row_id < col_size; row_id++){
printf("%d ", (int)h_c[row_id]);
}
printf("\n done\n");
// Release device memory
cudaFree(d_a);
cudaFree(d_c);
// Release host memory
free(h_a);
free(h_c);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__ void maxPerRow(double *values, int *gl_max, int n){
// Get our global thread ID
int id = blockIdx.x*blockDim.x+threadIdx.x;
int val = values[id];
//figure this out
if(id < n)
atomicMax(&gl_max[blockIdx.x], val);
}
int main( int argc, char* argv[] ){
// variable size of matrix < 1024
int col_size = 10, row_size = 1024;
//check that sizes are correct
if(col_size > 1025 || row_size > 1025){
printf("size not valid\n");
return 1;
}
//how many data points there are row*col
int data_size = col_size * row_size;
// Host input matrix
double *h_a;
//Host output matrix
int *h_c;
// Device input matrix
double *d_a;
//Device output matrix
int *d_c;
// Size, in bytes, of each matrix
size_t bytes_input = data_size*sizeof(double);
size_t bytes_output = col_size*sizeof(int);
// Allocate memory for each matrix on host
h_a = (double*)malloc(bytes_input);
h_c = (int*)malloc(bytes_output);
// Allocate memory for each matrix on GPU
hipMalloc(&d_a, bytes_input);
hipMalloc(&d_c, bytes_output);
int row_id;
// Initialize matrix on host
// Simple initialize for now
for( row_id = 0; row_id < data_size; row_id++ ) {
h_a[row_id] = 4;
}
// initialize output to zeroes
for(row_id = 0; row_id < col_size; row_id++){
h_c[row_id] = 0;
}
//some max values to test
h_a[4] = 19;
h_a[16] = 21;
h_a[98] = 49;
// Copy host matrices to device
hipMemcpy( d_a, h_a, bytes_input, hipMemcpyHostToDevice);
hipMemcpy( d_c, h_c, bytes_output, hipMemcpyHostToDevice);
// Initialize grid and block
int blockSize, gridSize;
// Number of threads in each thread block
blockSize = 1024;
// Number of thread blocks in grid 1024 height*width/blockSize
gridSize = (int)ceil(data_size/(float)blockSize);
// Execute the kernel add each thread for one output
maxPerRow<<<gridSize, col_size>>>(d_a, d_c, data_size);
// Copy result back to host
hipMemcpy( h_c, d_c, bytes_output, hipMemcpyDeviceToHost );
// print out data
for(row_id = 0; row_id < col_size; row_id++){
printf("%d ", (int)h_c[row_id]);
}
printf("\n done\n");
// Release device memory
hipFree(d_a);
hipFree(d_c);
// Release host memory
free(h_a);
free(h_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__ void maxPerRow(double *values, int *gl_max, int n){
// Get our global thread ID
int id = blockIdx.x*blockDim.x+threadIdx.x;
int val = values[id];
//figure this out
if(id < n)
atomicMax(&gl_max[blockIdx.x], val);
}
int main( int argc, char* argv[] ){
// variable size of matrix < 1024
int col_size = 10, row_size = 1024;
//check that sizes are correct
if(col_size > 1025 || row_size > 1025){
printf("size not valid\n");
return 1;
}
//how many data points there are row*col
int data_size = col_size * row_size;
// Host input matrix
double *h_a;
//Host output matrix
int *h_c;
// Device input matrix
double *d_a;
//Device output matrix
int *d_c;
// Size, in bytes, of each matrix
size_t bytes_input = data_size*sizeof(double);
size_t bytes_output = col_size*sizeof(int);
// Allocate memory for each matrix on host
h_a = (double*)malloc(bytes_input);
h_c = (int*)malloc(bytes_output);
// Allocate memory for each matrix on GPU
hipMalloc(&d_a, bytes_input);
hipMalloc(&d_c, bytes_output);
int row_id;
// Initialize matrix on host
// Simple initialize for now
for( row_id = 0; row_id < data_size; row_id++ ) {
h_a[row_id] = 4;
}
// initialize output to zeroes
for(row_id = 0; row_id < col_size; row_id++){
h_c[row_id] = 0;
}
//some max values to test
h_a[4] = 19;
h_a[16] = 21;
h_a[98] = 49;
// Copy host matrices to device
hipMemcpy( d_a, h_a, bytes_input, hipMemcpyHostToDevice);
hipMemcpy( d_c, h_c, bytes_output, hipMemcpyHostToDevice);
// Initialize grid and block
int blockSize, gridSize;
// Number of threads in each thread block
blockSize = 1024;
// Number of thread blocks in grid 1024 height*width/blockSize
gridSize = (int)ceil(data_size/(float)blockSize);
// Execute the kernel add each thread for one output
maxPerRow<<<gridSize, col_size>>>(d_a, d_c, data_size);
// Copy result back to host
hipMemcpy( h_c, d_c, bytes_output, hipMemcpyDeviceToHost );
// print out data
for(row_id = 0; row_id < col_size; row_id++){
printf("%d ", (int)h_c[row_id]);
}
printf("\n done\n");
// Release device memory
hipFree(d_a);
hipFree(d_c);
// Release host memory
free(h_a);
free(h_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9maxPerRowPdPii
.globl _Z9maxPerRowPdPii
.p2align 8
.type _Z9maxPerRowPdPii,@function
_Z9maxPerRowPdPii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_5
s_load_b64 s[4:5], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_brev_b32 s4, 1
global_load_b64 v[0:1], v[0:1], off
s_waitcnt vmcnt(0)
v_cvt_i32_f64_e32 v0, v[0:1]
.LBB0_2:
s_ctz_i32_b32 s5, s3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_readlane_b32 s6, v0, s5
s_lshl_b32 s5, 1, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_not1_b32 s3, s3, s5
s_max_i32 s4, s4, s6
s_cmp_lg_u32 s3, 0
s_cbranch_scc1 .LBB0_2
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
s_mov_b32 s3, 0
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_xor_b32 s5, exec_lo, s5
s_cbranch_execz .LBB0_5
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[2:3], 2
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_atomic_max_i32 v0, v1, s[0:1]
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9maxPerRowPdPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9maxPerRowPdPii, .Lfunc_end0-_Z9maxPerRowPdPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9maxPerRowPdPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9maxPerRowPdPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__ void maxPerRow(double *values, int *gl_max, int n){
// Get our global thread ID
int id = blockIdx.x*blockDim.x+threadIdx.x;
int val = values[id];
//figure this out
if(id < n)
atomicMax(&gl_max[blockIdx.x], val);
}
int main( int argc, char* argv[] ){
// variable size of matrix < 1024
int col_size = 10, row_size = 1024;
//check that sizes are correct
if(col_size > 1025 || row_size > 1025){
printf("size not valid\n");
return 1;
}
//how many data points there are row*col
int data_size = col_size * row_size;
// Host input matrix
double *h_a;
//Host output matrix
int *h_c;
// Device input matrix
double *d_a;
//Device output matrix
int *d_c;
// Size, in bytes, of each matrix
size_t bytes_input = data_size*sizeof(double);
size_t bytes_output = col_size*sizeof(int);
// Allocate memory for each matrix on host
h_a = (double*)malloc(bytes_input);
h_c = (int*)malloc(bytes_output);
// Allocate memory for each matrix on GPU
hipMalloc(&d_a, bytes_input);
hipMalloc(&d_c, bytes_output);
int row_id;
// Initialize matrix on host
// Simple initialize for now
for( row_id = 0; row_id < data_size; row_id++ ) {
h_a[row_id] = 4;
}
// initialize output to zeroes
for(row_id = 0; row_id < col_size; row_id++){
h_c[row_id] = 0;
}
//some max values to test
h_a[4] = 19;
h_a[16] = 21;
h_a[98] = 49;
// Copy host matrices to device
hipMemcpy( d_a, h_a, bytes_input, hipMemcpyHostToDevice);
hipMemcpy( d_c, h_c, bytes_output, hipMemcpyHostToDevice);
// Initialize grid and block
int blockSize, gridSize;
// Number of threads in each thread block
blockSize = 1024;
// Number of thread blocks in grid 1024 height*width/blockSize
gridSize = (int)ceil(data_size/(float)blockSize);
// Execute the kernel add each thread for one output
maxPerRow<<<gridSize, col_size>>>(d_a, d_c, data_size);
// Copy result back to host
hipMemcpy( h_c, d_c, bytes_output, hipMemcpyDeviceToHost );
// print out data
for(row_id = 0; row_id < col_size; row_id++){
printf("%d ", (int)h_c[row_id]);
}
printf("\n done\n");
// Release device memory
hipFree(d_a);
hipFree(d_c);
// Release host memory
free(h_a);
free(h_c);
return 0;
} | .text
.file "maxPerRow.hip"
.globl _Z24__device_stub__maxPerRowPdPii # -- Begin function _Z24__device_stub__maxPerRowPdPii
.p2align 4, 0x90
.type _Z24__device_stub__maxPerRowPdPii,@function
_Z24__device_stub__maxPerRowPdPii: # @_Z24__device_stub__maxPerRowPdPii
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9maxPerRowPdPii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__maxPerRowPdPii, .Lfunc_end0-_Z24__device_stub__maxPerRowPdPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $81920, %edi # imm = 0x14000
callq malloc
movq %rax, %rbx
movl $40, %edi
callq malloc
movq %rax, %r14
leaq 16(%rsp), %rdi
movl $81920, %esi # imm = 0x14000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
xorl %eax, %eax
movabsq $4616189618054758400, %rcx # imm = 0x4010000000000000
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movq %rcx, (%rbx,%rax,8)
incq %rax
cmpq $10240, %rax # imm = 0x2800
jne .LBB1_1
# %bb.2: # %.preheader.preheader
xorps %xmm0, %xmm0
movups %xmm0, 16(%r14)
movups %xmm0, (%r14)
movq $0, 32(%r14)
movabsq $4626041242239631360, %rax # imm = 0x4033000000000000
movq %rax, 32(%rbx)
movabsq $4626604192193052672, %rax # imm = 0x4035000000000000
movq %rax, 128(%rbx)
movabsq $4632092954238910464, %rax # imm = 0x4048800000000000
movq %rax, 784(%rbx)
movq 16(%rsp), %rdi
movl $81920, %edx # imm = 0x14000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $40, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967306, %rdi # imm = 0x10000000A
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $10240, 28(%rsp) # imm = 0x2800
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9maxPerRowPdPii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
movl $40, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl (%r14,%r15,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $10, %r15
jne .LBB1_5
# %bb.6:
movl $.Lstr, %edi
callq puts@PLT
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9maxPerRowPdPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9maxPerRowPdPii,@object # @_Z9maxPerRowPdPii
.section .rodata,"a",@progbits
.globl _Z9maxPerRowPdPii
.p2align 3, 0x0
_Z9maxPerRowPdPii:
.quad _Z24__device_stub__maxPerRowPdPii
.size _Z9maxPerRowPdPii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d "
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9maxPerRowPdPii"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n done"
.size .Lstr, 7
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__maxPerRowPdPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9maxPerRowPdPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9maxPerRowPdPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R4, c[0x0][0x0], R3 ; /* 0x0000000004027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0203 */
/*0090*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe400038e0100 */
/*00b0*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fe200080e0000 */
/*00c0*/ S2R R5, SR_LANEID ; /* 0x0000000000057919 */
/* 0x000e2a0000000000 */
/*00d0*/ ISETP.EQ.U32.AND P0, PT, R5, UR4, PT ; /* 0x0000000405007c0c */
/* 0x001fe2000bf02070 */
/*00e0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fd400000001ff */
/*00f0*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe200078e0005 */
/*0100*/ F2I.F64.TRUNC R0, R2 ; /* 0x0000000200007311 */
/* 0x004e24000030d100 */
/*0110*/ REDUX.MAX.S32 UR5, R0 ; /* 0x00000000000573c4 */
/* 0x001e240000014200 */
/*0120*/ MOV R7, UR5 ; /* 0x0000000500077c02 */
/* 0x001fca0008000f00 */
/*0130*/ @P0 RED.E.MAX.S32.STRONG.GPU [R4.64], R7 ; /* 0x000000070400098e */
/* 0x000fe2000d10e386 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9maxPerRowPdPii
.globl _Z9maxPerRowPdPii
.p2align 8
.type _Z9maxPerRowPdPii,@function
_Z9maxPerRowPdPii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_5
s_load_b64 s[4:5], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_brev_b32 s4, 1
global_load_b64 v[0:1], v[0:1], off
s_waitcnt vmcnt(0)
v_cvt_i32_f64_e32 v0, v[0:1]
.LBB0_2:
s_ctz_i32_b32 s5, s3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_readlane_b32 s6, v0, s5
s_lshl_b32 s5, 1, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_not1_b32 s3, s3, s5
s_max_i32 s4, s4, s6
s_cmp_lg_u32 s3, 0
s_cbranch_scc1 .LBB0_2
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
s_mov_b32 s3, 0
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_xor_b32 s5, exec_lo, s5
s_cbranch_execz .LBB0_5
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[2:3], 2
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_atomic_max_i32 v0, v1, s[0:1]
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9maxPerRowPdPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9maxPerRowPdPii, .Lfunc_end0-_Z9maxPerRowPdPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9maxPerRowPdPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9maxPerRowPdPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000491f8_00000000-6_maxPerRow.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z9maxPerRowPdPiiPdPii
.type _Z31__device_stub__Z9maxPerRowPdPiiPdPii, @function
_Z31__device_stub__Z9maxPerRowPdPiiPdPii:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9maxPerRowPdPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z9maxPerRowPdPiiPdPii, .-_Z31__device_stub__Z9maxPerRowPdPiiPdPii
.globl _Z9maxPerRowPdPii
.type _Z9maxPerRowPdPii, @function
_Z9maxPerRowPdPii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9maxPerRowPdPiiPdPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9maxPerRowPdPii, .-_Z9maxPerRowPdPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "%d "
.LC5:
.string "\n done\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $81920, %edi
call malloc@PLT
movq %rax, %rbp
movl $40, %edi
call malloc@PLT
movq %rax, %r12
movq %rsp, %rdi
movl $81920, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movq %rbp, %rax
leaq 81920(%rbp), %rdx
movsd .LC0(%rip), %xmm0
.L12:
movsd %xmm0, (%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L12
movq %r12, %rbx
leaq 40(%r12), %r13
movq %r12, %rax
.L13:
movl $0, (%rax)
addq $4, %rax
cmpq %r13, %rax
jne .L13
movq .LC1(%rip), %rax
movq %rax, 32(%rbp)
movq .LC2(%rip), %rax
movq %rax, 128(%rbp)
movq .LC3(%rip), %rax
movq %rax, 784(%rbp)
movl $1, %ecx
movl $81920, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $40, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $10, 28(%rsp)
movl $1, 32(%rsp)
movl $10, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L14:
movl $2, %ecx
movl $40, %edx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq .LC4(%rip), %r14
.L15:
movl (%rbx), %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r13, %rbx
jne .L15
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl $10240, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z31__device_stub__Z9maxPerRowPdPiiPdPii
jmp .L14
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z9maxPerRowPdPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z9maxPerRowPdPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1074790400
.align 8
.LC1:
.long 0
.long 1077084160
.align 8
.LC2:
.long 0
.long 1077215232
.align 8
.LC3:
.long 0
.long 1078493184
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "maxPerRow.hip"
.globl _Z24__device_stub__maxPerRowPdPii # -- Begin function _Z24__device_stub__maxPerRowPdPii
.p2align 4, 0x90
.type _Z24__device_stub__maxPerRowPdPii,@function
_Z24__device_stub__maxPerRowPdPii: # @_Z24__device_stub__maxPerRowPdPii
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9maxPerRowPdPii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__maxPerRowPdPii, .Lfunc_end0-_Z24__device_stub__maxPerRowPdPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $81920, %edi # imm = 0x14000
callq malloc
movq %rax, %rbx
movl $40, %edi
callq malloc
movq %rax, %r14
leaq 16(%rsp), %rdi
movl $81920, %esi # imm = 0x14000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
xorl %eax, %eax
movabsq $4616189618054758400, %rcx # imm = 0x4010000000000000
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movq %rcx, (%rbx,%rax,8)
incq %rax
cmpq $10240, %rax # imm = 0x2800
jne .LBB1_1
# %bb.2: # %.preheader.preheader
xorps %xmm0, %xmm0
movups %xmm0, 16(%r14)
movups %xmm0, (%r14)
movq $0, 32(%r14)
movabsq $4626041242239631360, %rax # imm = 0x4033000000000000
movq %rax, 32(%rbx)
movabsq $4626604192193052672, %rax # imm = 0x4035000000000000
movq %rax, 128(%rbx)
movabsq $4632092954238910464, %rax # imm = 0x4048800000000000
movq %rax, 784(%rbx)
movq 16(%rsp), %rdi
movl $81920, %edx # imm = 0x14000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $40, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967306, %rdi # imm = 0x10000000A
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $10240, 28(%rsp) # imm = 0x2800
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9maxPerRowPdPii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
movl $40, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl (%r14,%r15,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $10, %r15
jne .LBB1_5
# %bb.6:
movl $.Lstr, %edi
callq puts@PLT
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9maxPerRowPdPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9maxPerRowPdPii,@object # @_Z9maxPerRowPdPii
.section .rodata,"a",@progbits
.globl _Z9maxPerRowPdPii
.p2align 3, 0x0
_Z9maxPerRowPdPii:
.quad _Z24__device_stub__maxPerRowPdPii
.size _Z9maxPerRowPdPii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d "
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9maxPerRowPdPii"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n done"
.size .Lstr, 7
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__maxPerRowPdPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9maxPerRowPdPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
struct MyCudaTime {
cudaEvent_t _start;
cudaEvent_t _beforeKernel, _afterKernel, _stop;
MyCudaTime() {
cudaEventCreate(&_start);
cudaEventCreate(&_beforeKernel);
cudaEventCreate(&_afterKernel);
cudaEventCreate(&_stop);
cudaEventRecord(_start, 0);
}
void beforeKernel() {
cudaEventRecord(_beforeKernel, 0);
}
void afterKernel() {
cudaEventRecord(_afterKernel, 0);
}
void stop() { // return elapsed time in milliseconds
cudaEventRecord(_stop, 0);
cudaEventSynchronize(_stop);
}
void report() {
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, _start, _stop);
printf("Total time %3.2f ms\n", elapsedTime); // why 3.1?
cudaEventElapsedTime(&elapsedTime, _start, _beforeKernel);
printf("\t Before calling kernel %3.2f ms\n", elapsedTime);
cudaEventElapsedTime(&elapsedTime, _beforeKernel, _afterKernel);
printf("\t In kernel %3.2f ms\n", elapsedTime);
cudaEventElapsedTime(&elapsedTime, _afterKernel, _stop);
printf("\t After calling kernel %3.2f ms\n", elapsedTime);
}
}; | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
struct MyCudaTime {
cudaEvent_t _start;
cudaEvent_t _beforeKernel, _afterKernel, _stop;
MyCudaTime() {
cudaEventCreate(&_start);
cudaEventCreate(&_beforeKernel);
cudaEventCreate(&_afterKernel);
cudaEventCreate(&_stop);
cudaEventRecord(_start, 0);
}
void beforeKernel() {
cudaEventRecord(_beforeKernel, 0);
}
void afterKernel() {
cudaEventRecord(_afterKernel, 0);
}
void stop() { // return elapsed time in milliseconds
cudaEventRecord(_stop, 0);
cudaEventSynchronize(_stop);
}
void report() {
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, _start, _stop);
printf("Total time %3.2f ms\n", elapsedTime); // why 3.1?
cudaEventElapsedTime(&elapsedTime, _start, _beforeKernel);
printf("\t Before calling kernel %3.2f ms\n", elapsedTime);
cudaEventElapsedTime(&elapsedTime, _beforeKernel, _afterKernel);
printf("\t In kernel %3.2f ms\n", elapsedTime);
cudaEventElapsedTime(&elapsedTime, _afterKernel, _stop);
printf("\t After calling kernel %3.2f ms\n", elapsedTime);
}
}; | .file "tmpxft_000c154c_00000000-6_my_cuda_time.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
struct MyCudaTime {
cudaEvent_t _start;
cudaEvent_t _beforeKernel, _afterKernel, _stop;
MyCudaTime() {
cudaEventCreate(&_start);
cudaEventCreate(&_beforeKernel);
cudaEventCreate(&_afterKernel);
cudaEventCreate(&_stop);
cudaEventRecord(_start, 0);
}
void beforeKernel() {
cudaEventRecord(_beforeKernel, 0);
}
void afterKernel() {
cudaEventRecord(_afterKernel, 0);
}
void stop() { // return elapsed time in milliseconds
cudaEventRecord(_stop, 0);
cudaEventSynchronize(_stop);
}
void report() {
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, _start, _stop);
printf("Total time %3.2f ms\n", elapsedTime); // why 3.1?
cudaEventElapsedTime(&elapsedTime, _start, _beforeKernel);
printf("\t Before calling kernel %3.2f ms\n", elapsedTime);
cudaEventElapsedTime(&elapsedTime, _beforeKernel, _afterKernel);
printf("\t In kernel %3.2f ms\n", elapsedTime);
cudaEventElapsedTime(&elapsedTime, _afterKernel, _stop);
printf("\t After calling kernel %3.2f ms\n", elapsedTime);
}
}; | #include <hip/hip_runtime.h>
#include <stdio.h>
struct MyCudaTime {
hipEvent_t _start;
hipEvent_t _beforeKernel, _afterKernel, _stop;
MyCudaTime() {
hipEventCreate(&_start);
hipEventCreate(&_beforeKernel);
hipEventCreate(&_afterKernel);
hipEventCreate(&_stop);
hipEventRecord(_start, 0);
}
void beforeKernel() {
hipEventRecord(_beforeKernel, 0);
}
void afterKernel() {
hipEventRecord(_afterKernel, 0);
}
void stop() { // return elapsed time in milliseconds
hipEventRecord(_stop, 0);
hipEventSynchronize(_stop);
}
void report() {
float elapsedTime;
hipEventElapsedTime(&elapsedTime, _start, _stop);
printf("Total time %3.2f ms\n", elapsedTime); // why 3.1?
hipEventElapsedTime(&elapsedTime, _start, _beforeKernel);
printf("\t Before calling kernel %3.2f ms\n", elapsedTime);
hipEventElapsedTime(&elapsedTime, _beforeKernel, _afterKernel);
printf("\t In kernel %3.2f ms\n", elapsedTime);
hipEventElapsedTime(&elapsedTime, _afterKernel, _stop);
printf("\t After calling kernel %3.2f ms\n", elapsedTime);
}
}; |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
struct MyCudaTime {
hipEvent_t _start;
hipEvent_t _beforeKernel, _afterKernel, _stop;
MyCudaTime() {
hipEventCreate(&_start);
hipEventCreate(&_beforeKernel);
hipEventCreate(&_afterKernel);
hipEventCreate(&_stop);
hipEventRecord(_start, 0);
}
void beforeKernel() {
hipEventRecord(_beforeKernel, 0);
}
void afterKernel() {
hipEventRecord(_afterKernel, 0);
}
void stop() { // return elapsed time in milliseconds
hipEventRecord(_stop, 0);
hipEventSynchronize(_stop);
}
void report() {
float elapsedTime;
hipEventElapsedTime(&elapsedTime, _start, _stop);
printf("Total time %3.2f ms\n", elapsedTime); // why 3.1?
hipEventElapsedTime(&elapsedTime, _start, _beforeKernel);
printf("\t Before calling kernel %3.2f ms\n", elapsedTime);
hipEventElapsedTime(&elapsedTime, _beforeKernel, _afterKernel);
printf("\t In kernel %3.2f ms\n", elapsedTime);
hipEventElapsedTime(&elapsedTime, _afterKernel, _stop);
printf("\t After calling kernel %3.2f ms\n", elapsedTime);
}
}; | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
struct MyCudaTime {
hipEvent_t _start;
hipEvent_t _beforeKernel, _afterKernel, _stop;
MyCudaTime() {
hipEventCreate(&_start);
hipEventCreate(&_beforeKernel);
hipEventCreate(&_afterKernel);
hipEventCreate(&_stop);
hipEventRecord(_start, 0);
}
void beforeKernel() {
hipEventRecord(_beforeKernel, 0);
}
void afterKernel() {
hipEventRecord(_afterKernel, 0);
}
void stop() { // return elapsed time in milliseconds
hipEventRecord(_stop, 0);
hipEventSynchronize(_stop);
}
void report() {
float elapsedTime;
hipEventElapsedTime(&elapsedTime, _start, _stop);
printf("Total time %3.2f ms\n", elapsedTime); // why 3.1?
hipEventElapsedTime(&elapsedTime, _start, _beforeKernel);
printf("\t Before calling kernel %3.2f ms\n", elapsedTime);
hipEventElapsedTime(&elapsedTime, _beforeKernel, _afterKernel);
printf("\t In kernel %3.2f ms\n", elapsedTime);
hipEventElapsedTime(&elapsedTime, _afterKernel, _stop);
printf("\t After calling kernel %3.2f ms\n", elapsedTime);
}
}; | .text
.file "my_cuda_time.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c154c_00000000-6_my_cuda_time.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "my_cuda_time.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <sys/time.h>
#define EPSILON 1.0e-6
struct Particle
{
float3 position;
float3 velocity;
};
__host__ __device__ uint gen_random(uint a, uint b, uint c = 10, uint seed = 10)
{
return (seed*a+b) % c;
}
__device__ void update_position(Particle* part_array_gpu, float dt, uint i)
{
part_array_gpu[i].position.x += part_array_gpu[i].velocity.x * dt;
part_array_gpu[i].position.y += part_array_gpu[i].velocity.y * dt;
part_array_gpu[i].position.z += part_array_gpu[i].velocity.z * dt;
}
__device__ void update_velocity(Particle* part_array_gpu, float dt, uint i, uint j)
{
part_array_gpu[i].velocity.x += (float)(gen_random(i, j)) * dt;
part_array_gpu[i].velocity.y += (float)(gen_random(i, j)) * dt;
part_array_gpu[i].velocity.z += (float)(gen_random(i, j)) * dt;
}
__global__ void updateKernel(Particle* part_array_gpu, float dt, uint j)
{
const int i = blockIdx.x*blockDim.x + threadIdx.x;
update_velocity(part_array_gpu, dt, i, j);
update_position(part_array_gpu, dt, i);
}
__host__ void updateCPU(Particle* part_array_cpu, float dt, uint j, uint NPARTICLES)
{
for (int i = 0; i < NPARTICLES; i++)
{
if(i < NPARTICLES)
{
part_array_cpu[i].velocity.x += (float)(gen_random(i, j)) * dt;
part_array_cpu[i].velocity.y += (float)(gen_random(i, j)) * dt;
part_array_cpu[i].velocity.z += (float)(gen_random(i, j)) * dt;
part_array_cpu[i].position.x += part_array_cpu[i].velocity.x * dt;
part_array_cpu[i].position.y += part_array_cpu[i].velocity.y * dt;
part_array_cpu[i].position.z += part_array_cpu[i].velocity.z * dt;
}
}
}
__host__ bool compare_float(float a, float b)
{
return (fabs(a-b) < EPSILON);
}
__host__ bool compare_float3(float3 a, float3 b)
{
return (compare_float(a.x, b.x) && compare_float(a.y, b.y) && compare_float(a.z, b.z));
}
__host__ bool compareParticle(Particle particle1, Particle particle2)
{
bool result = true;
result &= compare_float3(particle1.position, particle2.position);
result &= compare_float3(particle1.velocity, particle2.velocity);
return result;
}
double cpuSecond()
{
struct timeval tp;
gettimeofday(&tp,NULL);
return ((double)tp.tv_sec + (double)tp.tv_usec*1.e-6);
}
int main(int argc, char** argv)
{
const float dt = 1.0;
bool flag = 1;
const int NITER = atoi(argv[1]);
const int TPB = atoi(argv[2]);
const int NPARTICLES = atoi(argv[3]);
// Declare a pointer for an array of particles
Particle* particles_gpu;
Particle* particles_cpu;
Particle* particles_res;
cudaHostAlloc((void **) &particles_cpu, NPARTICLES*sizeof(Particle), cudaHostAllocDefault);
cudaHostAlloc((void **) &particles_res, NPARTICLES*sizeof(Particle), cudaHostAllocDefault);
// Allocate device memory to store the output array
cudaMalloc(&particles_gpu, NPARTICLES*sizeof(Particle));
for (int i = 0; i < NPARTICLES; i++)
{
if(i < NPARTICLES)
{
particles_cpu[i].velocity.x = 0;
particles_cpu[i].velocity.y = 0;
particles_cpu[i].velocity.z = 0;
particles_cpu[i].position.x = 1;
particles_cpu[i].position.y = 1;
particles_cpu[i].position.z = 1;
particles_res[i].velocity.x = 0;
particles_res[i].velocity.y = 0;
particles_res[i].velocity.z = 0;
particles_res[i].position.x = 1;
particles_res[i].position.y = 1;
particles_res[i].position.z = 1;
}
}
//double iStart_HtoD = cpuSecond();
//double iElaps_HtoD = cpuSecond() - iStart_HtoD;
double iStart_gpu = cpuSecond();
//GPU computation
for (int j = 0; j < NITER; j++)
{
//printf("GPU iteration numéro %d : \n", j);
cudaMemcpy(particles_gpu, particles_res, NPARTICLES*sizeof(Particle), cudaMemcpyHostToDevice);
updateKernel<<<(NPARTICLES+TPB-1) / TPB, TPB>>>(particles_gpu, dt, j);
cudaMemcpy(particles_res, particles_gpu, NPARTICLES*sizeof(Particle), cudaMemcpyDeviceToHost);
}
cudaDeviceSynchronize();
//double iElaps_gpu = cpuSecond() - iStart_gpu;
//double iStart_cpu = cpuSecond();
//CPU computation
for (int j = 0; j < NITER; j++)
{
updateCPU(particles_cpu, dt, j, NPARTICLES);
}
//double iElaps_cpu = cpuSecond() - iStart_cpu;
for (int i = 0; i < NPARTICLES; i++) {
if(i < NPARTICLES)
{
if(!(compareParticle(particles_cpu[i], particles_res[i]))) {
flag = 0;
break;
}
}
}
/*double iStart_DtoH = cpuSecond();
cudaMemcpy(particles_cpu, particles_gpu, NPARTICLES*sizeof(Particle), cudaMemcpyDeviceToHost);
double iElaps_DtoH = cpuSecond() - iStart_DtoH; */
printf("Comparing the output for each implementation… ");
if (flag)
{
printf("Correct!\n");
} else {
printf("Incorrect\n");
}
//delete[] particles_cpu;
//delete[] particles_res;
cudaFree(particles_gpu);
cudaFreeHost(particles_gpu);
cudaFreeHost(particles_res); // Free the memory
return 0;
} | code for sm_80
Function : _Z12updateKernelP8Particlefj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 1.430511474609375e-06 ; /* 0x00000018ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE.U32 R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0005 */
/*0070*/ LDG.E R7, [R2.64+0xc] ; /* 0x00000c0402077981 */
/* 0x000ea8000c1e1900 */
/*0080*/ LDG.E R9, [R2.64+0x10] ; /* 0x0000100402097981 */
/* 0x000ee8000c1e1900 */
/*0090*/ LDG.E R11, [R2.64+0x14] ; /* 0x00001404020b7981 */
/* 0x000f28000c1e1900 */
/*00a0*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000f68000c1e1900 */
/*00b0*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040402087981 */
/* 0x000f68000c1e1900 */
/*00c0*/ LDG.E R10, [R2.64+0x8] ; /* 0x00000804020a7981 */
/* 0x000f62000c1e1900 */
/*00d0*/ HFMA2.MMA R5, -RZ, RZ, 0, 5.9604644775390625e-07 ; /* 0x0000000aff057435 */
/* 0x000fd400000001ff */
/*00e0*/ IMAD R0, R0, R5, c[0x0][0x16c] ; /* 0x00005b0000007624 */
/* 0x000fc800078e0205 */
/*00f0*/ IMAD.WIDE.U32 R4, R0, -0x33333333, RZ ; /* 0xcccccccd00047825 */
/* 0x000fca00078e00ff */
/*0100*/ SHF.R.U32.HI R5, RZ, 0x3, R5 ; /* 0x00000003ff057819 */
/* 0x000fca0000011605 */
/*0110*/ IMAD R0, R5, -0xa, R0 ; /* 0xfffffff605007824 */
/* 0x000fcc00078e0200 */
/*0120*/ I2F.U32 R0, R0 ; /* 0x0000000000007306 */
/* 0x000ea40000201000 */
/*0130*/ FFMA R7, R0.reuse, c[0x0][0x168], R7 ; /* 0x00005a0000077a23 */
/* 0x044fe40000000007 */
/*0140*/ FFMA R9, R0, c[0x0][0x168], R9 ; /* 0x00005a0000097a23 */
/* 0x008fc60000000009 */
/*0150*/ STG.E [R2.64+0xc], R7 ; /* 0x00000c0702007986 */
/* 0x000fe2000c101904 */
/*0160*/ FFMA R11, R0, c[0x0][0x168], R11 ; /* 0x00005a00000b7a23 */
/* 0x010fc6000000000b */
/*0170*/ STG.E [R2.64+0x10], R9 ; /* 0x0000100902007986 */
/* 0x000fe2000c101904 */
/*0180*/ FFMA R5, R7, c[0x0][0x168], R6 ; /* 0x00005a0007057a23 */
/* 0x020fc60000000006 */
/*0190*/ STG.E [R2.64+0x14], R11 ; /* 0x0000140b02007986 */
/* 0x000fe2000c101904 */
/*01a0*/ FFMA R13, R9, c[0x0][0x168], R8 ; /* 0x00005a00090d7a23 */
/* 0x000fc60000000008 */
/*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*01c0*/ FFMA R15, R11, c[0x0][0x168], R10 ; /* 0x00005a000b0f7a23 */
/* 0x000fc6000000000a */
/*01d0*/ STG.E [R2.64+0x4], R13 ; /* 0x0000040d02007986 */
/* 0x000fe8000c101904 */
/*01e0*/ STG.E [R2.64+0x8], R15 ; /* 0x0000080f02007986 */
/* 0x000fe2000c101904 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <sys/time.h>
#define EPSILON 1.0e-6
struct Particle
{
float3 position;
float3 velocity;
};
__host__ __device__ uint gen_random(uint a, uint b, uint c = 10, uint seed = 10)
{
return (seed*a+b) % c;
}
__device__ void update_position(Particle* part_array_gpu, float dt, uint i)
{
part_array_gpu[i].position.x += part_array_gpu[i].velocity.x * dt;
part_array_gpu[i].position.y += part_array_gpu[i].velocity.y * dt;
part_array_gpu[i].position.z += part_array_gpu[i].velocity.z * dt;
}
__device__ void update_velocity(Particle* part_array_gpu, float dt, uint i, uint j)
{
part_array_gpu[i].velocity.x += (float)(gen_random(i, j)) * dt;
part_array_gpu[i].velocity.y += (float)(gen_random(i, j)) * dt;
part_array_gpu[i].velocity.z += (float)(gen_random(i, j)) * dt;
}
__global__ void updateKernel(Particle* part_array_gpu, float dt, uint j)
{
const int i = blockIdx.x*blockDim.x + threadIdx.x;
update_velocity(part_array_gpu, dt, i, j);
update_position(part_array_gpu, dt, i);
}
__host__ void updateCPU(Particle* part_array_cpu, float dt, uint j, uint NPARTICLES)
{
for (int i = 0; i < NPARTICLES; i++)
{
if(i < NPARTICLES)
{
part_array_cpu[i].velocity.x += (float)(gen_random(i, j)) * dt;
part_array_cpu[i].velocity.y += (float)(gen_random(i, j)) * dt;
part_array_cpu[i].velocity.z += (float)(gen_random(i, j)) * dt;
part_array_cpu[i].position.x += part_array_cpu[i].velocity.x * dt;
part_array_cpu[i].position.y += part_array_cpu[i].velocity.y * dt;
part_array_cpu[i].position.z += part_array_cpu[i].velocity.z * dt;
}
}
}
__host__ bool compare_float(float a, float b)
{
return (fabs(a-b) < EPSILON);
}
__host__ bool compare_float3(float3 a, float3 b)
{
return (compare_float(a.x, b.x) && compare_float(a.y, b.y) && compare_float(a.z, b.z));
}
__host__ bool compareParticle(Particle particle1, Particle particle2)
{
bool result = true;
result &= compare_float3(particle1.position, particle2.position);
result &= compare_float3(particle1.velocity, particle2.velocity);
return result;
}
double cpuSecond()
{
struct timeval tp;
gettimeofday(&tp,NULL);
return ((double)tp.tv_sec + (double)tp.tv_usec*1.e-6);
}
int main(int argc, char** argv)
{
const float dt = 1.0;
bool flag = 1;
const int NITER = atoi(argv[1]);
const int TPB = atoi(argv[2]);
const int NPARTICLES = atoi(argv[3]);
// Declare a pointer for an array of particles
Particle* particles_gpu;
Particle* particles_cpu;
Particle* particles_res;
cudaHostAlloc((void **) &particles_cpu, NPARTICLES*sizeof(Particle), cudaHostAllocDefault);
cudaHostAlloc((void **) &particles_res, NPARTICLES*sizeof(Particle), cudaHostAllocDefault);
// Allocate device memory to store the output array
cudaMalloc(&particles_gpu, NPARTICLES*sizeof(Particle));
for (int i = 0; i < NPARTICLES; i++)
{
if(i < NPARTICLES)
{
particles_cpu[i].velocity.x = 0;
particles_cpu[i].velocity.y = 0;
particles_cpu[i].velocity.z = 0;
particles_cpu[i].position.x = 1;
particles_cpu[i].position.y = 1;
particles_cpu[i].position.z = 1;
particles_res[i].velocity.x = 0;
particles_res[i].velocity.y = 0;
particles_res[i].velocity.z = 0;
particles_res[i].position.x = 1;
particles_res[i].position.y = 1;
particles_res[i].position.z = 1;
}
}
//double iStart_HtoD = cpuSecond();
//double iElaps_HtoD = cpuSecond() - iStart_HtoD;
double iStart_gpu = cpuSecond();
//GPU computation
for (int j = 0; j < NITER; j++)
{
//printf("GPU iteration numéro %d : \n", j);
cudaMemcpy(particles_gpu, particles_res, NPARTICLES*sizeof(Particle), cudaMemcpyHostToDevice);
updateKernel<<<(NPARTICLES+TPB-1) / TPB, TPB>>>(particles_gpu, dt, j);
cudaMemcpy(particles_res, particles_gpu, NPARTICLES*sizeof(Particle), cudaMemcpyDeviceToHost);
}
cudaDeviceSynchronize();
//double iElaps_gpu = cpuSecond() - iStart_gpu;
//double iStart_cpu = cpuSecond();
//CPU computation
for (int j = 0; j < NITER; j++)
{
updateCPU(particles_cpu, dt, j, NPARTICLES);
}
//double iElaps_cpu = cpuSecond() - iStart_cpu;
for (int i = 0; i < NPARTICLES; i++) {
if(i < NPARTICLES)
{
if(!(compareParticle(particles_cpu[i], particles_res[i]))) {
flag = 0;
break;
}
}
}
/*double iStart_DtoH = cpuSecond();
cudaMemcpy(particles_cpu, particles_gpu, NPARTICLES*sizeof(Particle), cudaMemcpyDeviceToHost);
double iElaps_DtoH = cpuSecond() - iStart_DtoH; */
printf("Comparing the output for each implementation… ");
if (flag)
{
printf("Correct!\n");
} else {
printf("Incorrect\n");
}
//delete[] particles_cpu;
//delete[] particles_res;
cudaFree(particles_gpu);
cudaFreeHost(particles_gpu);
cudaFreeHost(particles_res); // Free the memory
return 0;
} | .file "tmpxft_000b6019_00000000-6_exercise_2a.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2068:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2068:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10gen_randomjjjj
.type _Z10gen_randomjjjj, @function
_Z10gen_randomjjjj:
.LFB2057:
.cfi_startproc
endbr64
movl %edx, %r8d
imull %edi, %ecx
leal (%rcx,%rsi), %eax
movl $0, %edx
divl %r8d
movl %edx, %eax
ret
.cfi_endproc
.LFE2057:
.size _Z10gen_randomjjjj, .-_Z10gen_randomjjjj
.globl _Z15update_positionP8Particlefj
.type _Z15update_positionP8Particlefj, @function
_Z15update_positionP8Particlefj:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z15update_positionP8Particlefj, .-_Z15update_positionP8Particlefj
.globl _Z15update_velocityP8Particlefjj
.type _Z15update_velocityP8Particlefjj, @function
_Z15update_velocityP8Particlefjj:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z15update_velocityP8Particlefjj, .-_Z15update_velocityP8Particlefjj
.globl _Z9updateCPUP8Particlefjj
.type _Z9updateCPUP8Particlefjj, @function
_Z9updateCPUP8Particlefjj:
.LFB2060:
.cfi_startproc
endbr64
movl %esi, %ecx
testl %edx, %edx
je .L8
movq %rdi, %rax
movl %edx, %edx
leaq (%rdx,%rdx,2), %rdx
leaq (%rdi,%rdx,8), %rsi
movl $3435973837, %edx
.L12:
movl %ecx, %edi
imulq %rdx, %rdi
shrq $35, %rdi
leal (%rdi,%rdi,4), %edi
addl %edi, %edi
movl %ecx, %r8d
subl %edi, %r8d
pxor %xmm1, %xmm1
cvtsi2ssq %r8, %xmm1
mulss %xmm0, %xmm1
movaps %xmm1, %xmm3
addss 12(%rax), %xmm3
movss %xmm3, 12(%rax)
movaps %xmm1, %xmm2
addss 16(%rax), %xmm2
movss %xmm2, 16(%rax)
addss 20(%rax), %xmm1
movss %xmm1, 20(%rax)
mulss %xmm0, %xmm3
addss (%rax), %xmm3
movss %xmm3, (%rax)
mulss %xmm0, %xmm2
addss 4(%rax), %xmm2
movss %xmm2, 4(%rax)
mulss %xmm0, %xmm1
addss 8(%rax), %xmm1
movss %xmm1, 8(%rax)
addl $10, %ecx
addq $24, %rax
cmpq %rsi, %rax
jne .L12
.L8:
ret
.cfi_endproc
.LFE2060:
.size _Z9updateCPUP8Particlefjj, .-_Z9updateCPUP8Particlefjj
.globl _Z13compare_floatff
.type _Z13compare_floatff, @function
_Z13compare_floatff:
.LFB2061:
.cfi_startproc
endbr64
subss %xmm1, %xmm0
andps .LC0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movsd .LC1(%rip), %xmm1
comisd %xmm0, %xmm1
seta %al
ret
.cfi_endproc
.LFE2061:
.size _Z13compare_floatff, .-_Z13compare_floatff
.globl _Z14compare_float36float3S_
.type _Z14compare_float36float3S_, @function
_Z14compare_float36float3S_:
.LFB2062:
.cfi_startproc
endbr64
movq %xmm0, -16(%rsp)
movss %xmm1, -8(%rsp)
movq %xmm2, -32(%rsp)
movss %xmm3, -24(%rsp)
movss -16(%rsp), %xmm0
subss -32(%rsp), %xmm0
andps .LC0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movsd .LC1(%rip), %xmm1
comisd %xmm0, %xmm1
jbe .L23
movss -12(%rsp), %xmm0
subss -28(%rsp), %xmm0
andps .LC0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
comisd %xmm0, %xmm1
jbe .L24
movss -8(%rsp), %xmm0
subss %xmm3, %xmm0
andps .LC0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
comisd %xmm0, %xmm1
seta %al
ret
.L23:
movl $0, %eax
ret
.L24:
movl $0, %eax
ret
.cfi_endproc
.LFE2062:
.size _Z14compare_float36float3S_, .-_Z14compare_float36float3S_
.globl _Z15compareParticle8ParticleS_
.type _Z15compareParticle8ParticleS_, @function
_Z15compareParticle8ParticleS_:
.LFB2063:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq 40(%rsp), %xmm2
movss 48(%rsp), %xmm3
movq 16(%rsp), %xmm0
movss 24(%rsp), %xmm1
call _Z14compare_float36float3S_
movl %eax, %ebx
movq 52(%rsp), %xmm2
movss 60(%rsp), %xmm3
movq 28(%rsp), %xmm0
movss 36(%rsp), %xmm1
call _Z14compare_float36float3S_
andl %ebx, %eax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _Z15compareParticle8ParticleS_, .-_Z15compareParticle8ParticleS_
.globl _Z9cpuSecondv
.type _Z9cpuSecondv, @function
_Z9cpuSecondv:
.LFB2064:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LC1(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2064:
.size _Z9cpuSecondv, .-_Z9cpuSecondv
.globl _Z42__device_stub__Z12updateKernelP8ParticlefjP8Particlefj
.type _Z42__device_stub__Z12updateKernelP8ParticlefjP8Particlefj, @function
_Z42__device_stub__Z12updateKernelP8ParticlefjP8Particlefj:
.LFB2090:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movss %xmm0, 4(%rsp)
movl %esi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L35
.L31:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12updateKernelP8Particlefj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L31
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z42__device_stub__Z12updateKernelP8ParticlefjP8Particlefj, .-_Z42__device_stub__Z12updateKernelP8ParticlefjP8Particlefj
.globl _Z12updateKernelP8Particlefj
.type _Z12updateKernelP8Particlefj, @function
_Z12updateKernelP8Particlefj:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z12updateKernelP8ParticlefjP8Particlefj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z12updateKernelP8Particlefj, .-_Z12updateKernelP8Particlefj
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "Correct!\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "Comparing the output for each implementation\342\200\246 "
.section .rodata.str1.1
.LC6:
.string "Incorrect\n"
.text
.globl main
.type main, @function
main:
.LFB2065:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, %r13d
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
movl %eax, %r12d
movq 24(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r14
movl %eax, 12(%rsp)
cltq
leaq (%rax,%rax,2), %rbp
salq $3, %rbp
leaq 32(%rsp), %rdi
movl $0, %edx
movq %rbp, %rsi
call cudaHostAlloc@PLT
leaq 40(%rsp), %rdi
movl $0, %edx
movq %rbp, %rsi
call cudaHostAlloc@PLT
leaq 24(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
testl %r14d, %r14d
jle .L40
leal -1(%r14), %eax
leaq 3(%rax,%rax,2), %rcx
salq $3, %rcx
movl $0, %eax
movss .LC3(%rip), %xmm0
.L41:
movq %rax, %rdx
addq 32(%rsp), %rdx
movl $0x00000000, 12(%rdx)
movl $0x00000000, 16(%rdx)
movl $0x00000000, 20(%rdx)
movss %xmm0, (%rdx)
movq 32(%rsp), %rdx
movss %xmm0, 4(%rdx,%rax)
movq 32(%rsp), %rdx
movss %xmm0, 8(%rdx,%rax)
movq %rax, %rdx
addq 40(%rsp), %rdx
movl $0x00000000, 12(%rdx)
movl $0x00000000, 16(%rdx)
movl $0x00000000, 20(%rdx)
movss %xmm0, (%rdx)
movq 40(%rsp), %rdx
movss %xmm0, 4(%rdx,%rax)
movq 40(%rsp), %rdx
movss %xmm0, 8(%rdx,%rax)
addq $24, %rax
cmpq %rcx, %rax
jne .L41
.L40:
call _Z9cpuSecondv
testl %ebx, %ebx
jle .L42
movl $0, %ebx
movl 12(%rsp), %eax
leal -1(%rax,%r12), %eax
movl %eax, 12(%rsp)
jmp .L44
.L43:
movl $2, %ecx
movq %rbp, %rdx
movq 24(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
addl $1, %ebx
cmpl %r13d, %ebx
je .L61
.L44:
movl $1, %ecx
movq %rbp, %rdx
movq 40(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %r15d, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl 12(%rsp), %eax
cltd
idivl %r12d
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L43
movl %ebx, %esi
movss .LC3(%rip), %xmm0
movq 24(%rsp), %rdi
call _Z42__device_stub__Z12updateKernelP8ParticlefjP8Particlefj
jmp .L43
.L61:
call cudaDeviceSynchronize@PLT
movl $0, %ebx
.L45:
movl %r14d, %edx
movl %ebx, %esi
movss .LC3(%rip), %xmm0
movq 32(%rsp), %rdi
call _Z9updateCPUP8Particlefjj
addl $1, %ebx
cmpl %r13d, %ebx
jne .L45
.L51:
testl %r14d, %r14d
jle .L46
movq 32(%rsp), %rbx
movq 40(%rsp), %rbp
leal -1(%r14), %eax
leaq (%rax,%rax,2), %rax
leaq 24(%rbx,%rax,8), %r12
.L48:
subq $48, %rsp
.cfi_def_cfa_offset 192
movdqu 0(%rbp), %xmm1
movups %xmm1, 24(%rsp)
movq 16(%rbp), %rax
movq %rax, 40(%rsp)
movdqu (%rbx), %xmm2
movups %xmm2, (%rsp)
movq 16(%rbx), %rax
movq %rax, 16(%rsp)
call _Z15compareParticle8ParticleS_
addq $48, %rsp
.cfi_def_cfa_offset 144
testb %al, %al
je .L47
addq $24, %rbx
addq $24, %rbp
cmpq %rbx, %r12
jne .L48
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L50:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L52:
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFreeHost@PLT
movq 40(%rsp), %rdi
call cudaFreeHost@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L62
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L50
.L42:
call cudaDeviceSynchronize@PLT
jmp .L51
.L47:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L52
.L62:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2065:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z12updateKernelP8Particlefj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2093:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z12updateKernelP8Particlefj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC0:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long -1598689907
.long 1051772663
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <sys/time.h>
#define EPSILON 1.0e-6
struct Particle
{
float3 position;
float3 velocity;
};
__host__ __device__ uint gen_random(uint a, uint b, uint c = 10, uint seed = 10)
{
return (seed*a+b) % c;
}
__device__ void update_position(Particle* part_array_gpu, float dt, uint i)
{
part_array_gpu[i].position.x += part_array_gpu[i].velocity.x * dt;
part_array_gpu[i].position.y += part_array_gpu[i].velocity.y * dt;
part_array_gpu[i].position.z += part_array_gpu[i].velocity.z * dt;
}
__device__ void update_velocity(Particle* part_array_gpu, float dt, uint i, uint j)
{
part_array_gpu[i].velocity.x += (float)(gen_random(i, j)) * dt;
part_array_gpu[i].velocity.y += (float)(gen_random(i, j)) * dt;
part_array_gpu[i].velocity.z += (float)(gen_random(i, j)) * dt;
}
__global__ void updateKernel(Particle* part_array_gpu, float dt, uint j)
{
const int i = blockIdx.x*blockDim.x + threadIdx.x;
update_velocity(part_array_gpu, dt, i, j);
update_position(part_array_gpu, dt, i);
}
__host__ void updateCPU(Particle* part_array_cpu, float dt, uint j, uint NPARTICLES)
{
for (int i = 0; i < NPARTICLES; i++)
{
if(i < NPARTICLES)
{
part_array_cpu[i].velocity.x += (float)(gen_random(i, j)) * dt;
part_array_cpu[i].velocity.y += (float)(gen_random(i, j)) * dt;
part_array_cpu[i].velocity.z += (float)(gen_random(i, j)) * dt;
part_array_cpu[i].position.x += part_array_cpu[i].velocity.x * dt;
part_array_cpu[i].position.y += part_array_cpu[i].velocity.y * dt;
part_array_cpu[i].position.z += part_array_cpu[i].velocity.z * dt;
}
}
}
__host__ bool compare_float(float a, float b)
{
return (fabs(a-b) < EPSILON);
}
__host__ bool compare_float3(float3 a, float3 b)
{
return (compare_float(a.x, b.x) && compare_float(a.y, b.y) && compare_float(a.z, b.z));
}
__host__ bool compareParticle(Particle particle1, Particle particle2)
{
bool result = true;
result &= compare_float3(particle1.position, particle2.position);
result &= compare_float3(particle1.velocity, particle2.velocity);
return result;
}
double cpuSecond()
{
struct timeval tp;
gettimeofday(&tp,NULL);
return ((double)tp.tv_sec + (double)tp.tv_usec*1.e-6);
}
int main(int argc, char** argv)
{
const float dt = 1.0;
bool flag = 1;
const int NITER = atoi(argv[1]);
const int TPB = atoi(argv[2]);
const int NPARTICLES = atoi(argv[3]);
// Declare a pointer for an array of particles
Particle* particles_gpu;
Particle* particles_cpu;
Particle* particles_res;
cudaHostAlloc((void **) &particles_cpu, NPARTICLES*sizeof(Particle), cudaHostAllocDefault);
cudaHostAlloc((void **) &particles_res, NPARTICLES*sizeof(Particle), cudaHostAllocDefault);
// Allocate device memory to store the output array
cudaMalloc(&particles_gpu, NPARTICLES*sizeof(Particle));
for (int i = 0; i < NPARTICLES; i++)
{
if(i < NPARTICLES)
{
particles_cpu[i].velocity.x = 0;
particles_cpu[i].velocity.y = 0;
particles_cpu[i].velocity.z = 0;
particles_cpu[i].position.x = 1;
particles_cpu[i].position.y = 1;
particles_cpu[i].position.z = 1;
particles_res[i].velocity.x = 0;
particles_res[i].velocity.y = 0;
particles_res[i].velocity.z = 0;
particles_res[i].position.x = 1;
particles_res[i].position.y = 1;
particles_res[i].position.z = 1;
}
}
//double iStart_HtoD = cpuSecond();
//double iElaps_HtoD = cpuSecond() - iStart_HtoD;
double iStart_gpu = cpuSecond();
//GPU computation
for (int j = 0; j < NITER; j++)
{
//printf("GPU iteration numéro %d : \n", j);
cudaMemcpy(particles_gpu, particles_res, NPARTICLES*sizeof(Particle), cudaMemcpyHostToDevice);
updateKernel<<<(NPARTICLES+TPB-1) / TPB, TPB>>>(particles_gpu, dt, j);
cudaMemcpy(particles_res, particles_gpu, NPARTICLES*sizeof(Particle), cudaMemcpyDeviceToHost);
}
cudaDeviceSynchronize();
//double iElaps_gpu = cpuSecond() - iStart_gpu;
//double iStart_cpu = cpuSecond();
//CPU computation
for (int j = 0; j < NITER; j++)
{
updateCPU(particles_cpu, dt, j, NPARTICLES);
}
//double iElaps_cpu = cpuSecond() - iStart_cpu;
for (int i = 0; i < NPARTICLES; i++) {
if(i < NPARTICLES)
{
if(!(compareParticle(particles_cpu[i], particles_res[i]))) {
flag = 0;
break;
}
}
}
/*double iStart_DtoH = cpuSecond();
cudaMemcpy(particles_cpu, particles_gpu, NPARTICLES*sizeof(Particle), cudaMemcpyDeviceToHost);
double iElaps_DtoH = cpuSecond() - iStart_DtoH; */
printf("Comparing the output for each implementation… ");
if (flag)
{
printf("Correct!\n");
} else {
printf("Incorrect\n");
}
//delete[] particles_cpu;
//delete[] particles_res;
cudaFree(particles_gpu);
cudaFreeHost(particles_gpu);
cudaFreeHost(particles_res); // Free the memory
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <sys/time.h>
#define EPSILON 1.0e-6
struct Particle
{
float3 position;
float3 velocity;
};
__host__ __device__ uint gen_random(uint a, uint b, uint c = 10, uint seed = 10)
{
return (seed*a+b) % c;
}
__device__ void update_position(Particle* part_array_gpu, float dt, uint i)
{
part_array_gpu[i].position.x += part_array_gpu[i].velocity.x * dt;
part_array_gpu[i].position.y += part_array_gpu[i].velocity.y * dt;
part_array_gpu[i].position.z += part_array_gpu[i].velocity.z * dt;
}
__device__ void update_velocity(Particle* part_array_gpu, float dt, uint i, uint j)
{
part_array_gpu[i].velocity.x += (float)(gen_random(i, j)) * dt;
part_array_gpu[i].velocity.y += (float)(gen_random(i, j)) * dt;
part_array_gpu[i].velocity.z += (float)(gen_random(i, j)) * dt;
}
__global__ void updateKernel(Particle* part_array_gpu, float dt, uint j)
{
const int i = blockIdx.x*blockDim.x + threadIdx.x;
update_velocity(part_array_gpu, dt, i, j);
update_position(part_array_gpu, dt, i);
}
__host__ void updateCPU(Particle* part_array_cpu, float dt, uint j, uint NPARTICLES)
{
for (int i = 0; i < NPARTICLES; i++)
{
if(i < NPARTICLES)
{
part_array_cpu[i].velocity.x += (float)(gen_random(i, j)) * dt;
part_array_cpu[i].velocity.y += (float)(gen_random(i, j)) * dt;
part_array_cpu[i].velocity.z += (float)(gen_random(i, j)) * dt;
part_array_cpu[i].position.x += part_array_cpu[i].velocity.x * dt;
part_array_cpu[i].position.y += part_array_cpu[i].velocity.y * dt;
part_array_cpu[i].position.z += part_array_cpu[i].velocity.z * dt;
}
}
}
__host__ bool compare_float(float a, float b)
{
return (fabs(a-b) < EPSILON);
}
__host__ bool compare_float3(float3 a, float3 b)
{
return (compare_float(a.x, b.x) && compare_float(a.y, b.y) && compare_float(a.z, b.z));
}
__host__ bool compareParticle(Particle particle1, Particle particle2)
{
bool result = true;
result &= compare_float3(particle1.position, particle2.position);
result &= compare_float3(particle1.velocity, particle2.velocity);
return result;
}
double cpuSecond()
{
struct timeval tp;
gettimeofday(&tp,NULL);
return ((double)tp.tv_sec + (double)tp.tv_usec*1.e-6);
}
int main(int argc, char** argv)
{
const float dt = 1.0;
bool flag = 1;
const int NITER = atoi(argv[1]);
const int TPB = atoi(argv[2]);
const int NPARTICLES = atoi(argv[3]);
// Declare a pointer for an array of particles
Particle* particles_gpu;
Particle* particles_cpu;
Particle* particles_res;
hipHostAlloc((void **) &particles_cpu, NPARTICLES*sizeof(Particle), hipHostMallocDefault);
hipHostAlloc((void **) &particles_res, NPARTICLES*sizeof(Particle), hipHostMallocDefault);
// Allocate device memory to store the output array
hipMalloc(&particles_gpu, NPARTICLES*sizeof(Particle));
for (int i = 0; i < NPARTICLES; i++)
{
if(i < NPARTICLES)
{
particles_cpu[i].velocity.x = 0;
particles_cpu[i].velocity.y = 0;
particles_cpu[i].velocity.z = 0;
particles_cpu[i].position.x = 1;
particles_cpu[i].position.y = 1;
particles_cpu[i].position.z = 1;
particles_res[i].velocity.x = 0;
particles_res[i].velocity.y = 0;
particles_res[i].velocity.z = 0;
particles_res[i].position.x = 1;
particles_res[i].position.y = 1;
particles_res[i].position.z = 1;
}
}
//double iStart_HtoD = cpuSecond();
//double iElaps_HtoD = cpuSecond() - iStart_HtoD;
double iStart_gpu = cpuSecond();
//GPU computation
for (int j = 0; j < NITER; j++)
{
//printf("GPU iteration numéro %d : \n", j);
hipMemcpy(particles_gpu, particles_res, NPARTICLES*sizeof(Particle), hipMemcpyHostToDevice);
updateKernel<<<(NPARTICLES+TPB-1) / TPB, TPB>>>(particles_gpu, dt, j);
hipMemcpy(particles_res, particles_gpu, NPARTICLES*sizeof(Particle), hipMemcpyDeviceToHost);
}
hipDeviceSynchronize();
//double iElaps_gpu = cpuSecond() - iStart_gpu;
//double iStart_cpu = cpuSecond();
//CPU computation
for (int j = 0; j < NITER; j++)
{
updateCPU(particles_cpu, dt, j, NPARTICLES);
}
//double iElaps_cpu = cpuSecond() - iStart_cpu;
for (int i = 0; i < NPARTICLES; i++) {
if(i < NPARTICLES)
{
if(!(compareParticle(particles_cpu[i], particles_res[i]))) {
flag = 0;
break;
}
}
}
/*double iStart_DtoH = cpuSecond();
cudaMemcpy(particles_cpu, particles_gpu, NPARTICLES*sizeof(Particle), cudaMemcpyDeviceToHost);
double iElaps_DtoH = cpuSecond() - iStart_DtoH; */
printf("Comparing the output for each implementation… ");
if (flag)
{
printf("Correct!\n");
} else {
printf("Incorrect\n");
}
//delete[] particles_cpu;
//delete[] particles_res;
hipFree(particles_gpu);
hipHostFree(particles_gpu);
hipHostFree(particles_res); // Free the memory
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <sys/time.h>
#define EPSILON 1.0e-6
struct Particle
{
float3 position;
float3 velocity;
};
__host__ __device__ uint gen_random(uint a, uint b, uint c = 10, uint seed = 10)
{
return (seed*a+b) % c;
}
__device__ void update_position(Particle* part_array_gpu, float dt, uint i)
{
part_array_gpu[i].position.x += part_array_gpu[i].velocity.x * dt;
part_array_gpu[i].position.y += part_array_gpu[i].velocity.y * dt;
part_array_gpu[i].position.z += part_array_gpu[i].velocity.z * dt;
}
__device__ void update_velocity(Particle* part_array_gpu, float dt, uint i, uint j)
{
part_array_gpu[i].velocity.x += (float)(gen_random(i, j)) * dt;
part_array_gpu[i].velocity.y += (float)(gen_random(i, j)) * dt;
part_array_gpu[i].velocity.z += (float)(gen_random(i, j)) * dt;
}
__global__ void updateKernel(Particle* part_array_gpu, float dt, uint j)
{
const int i = blockIdx.x*blockDim.x + threadIdx.x;
update_velocity(part_array_gpu, dt, i, j);
update_position(part_array_gpu, dt, i);
}
__host__ void updateCPU(Particle* part_array_cpu, float dt, uint j, uint NPARTICLES)
{
for (int i = 0; i < NPARTICLES; i++)
{
if(i < NPARTICLES)
{
part_array_cpu[i].velocity.x += (float)(gen_random(i, j)) * dt;
part_array_cpu[i].velocity.y += (float)(gen_random(i, j)) * dt;
part_array_cpu[i].velocity.z += (float)(gen_random(i, j)) * dt;
part_array_cpu[i].position.x += part_array_cpu[i].velocity.x * dt;
part_array_cpu[i].position.y += part_array_cpu[i].velocity.y * dt;
part_array_cpu[i].position.z += part_array_cpu[i].velocity.z * dt;
}
}
}
__host__ bool compare_float(float a, float b)
{
return (fabs(a-b) < EPSILON);
}
__host__ bool compare_float3(float3 a, float3 b)
{
return (compare_float(a.x, b.x) && compare_float(a.y, b.y) && compare_float(a.z, b.z));
}
__host__ bool compareParticle(Particle particle1, Particle particle2)
{
bool result = true;
result &= compare_float3(particle1.position, particle2.position);
result &= compare_float3(particle1.velocity, particle2.velocity);
return result;
}
double cpuSecond()
{
struct timeval tp;
gettimeofday(&tp,NULL);
return ((double)tp.tv_sec + (double)tp.tv_usec*1.e-6);
}
int main(int argc, char** argv)
{
const float dt = 1.0;
bool flag = 1;
const int NITER = atoi(argv[1]);
const int TPB = atoi(argv[2]);
const int NPARTICLES = atoi(argv[3]);
// Declare a pointer for an array of particles
Particle* particles_gpu;
Particle* particles_cpu;
Particle* particles_res;
hipHostAlloc((void **) &particles_cpu, NPARTICLES*sizeof(Particle), hipHostMallocDefault);
hipHostAlloc((void **) &particles_res, NPARTICLES*sizeof(Particle), hipHostMallocDefault);
// Allocate device memory to store the output array
hipMalloc(&particles_gpu, NPARTICLES*sizeof(Particle));
for (int i = 0; i < NPARTICLES; i++)
{
if(i < NPARTICLES)
{
particles_cpu[i].velocity.x = 0;
particles_cpu[i].velocity.y = 0;
particles_cpu[i].velocity.z = 0;
particles_cpu[i].position.x = 1;
particles_cpu[i].position.y = 1;
particles_cpu[i].position.z = 1;
particles_res[i].velocity.x = 0;
particles_res[i].velocity.y = 0;
particles_res[i].velocity.z = 0;
particles_res[i].position.x = 1;
particles_res[i].position.y = 1;
particles_res[i].position.z = 1;
}
}
//double iStart_HtoD = cpuSecond();
//double iElaps_HtoD = cpuSecond() - iStart_HtoD;
double iStart_gpu = cpuSecond();
//GPU computation
for (int j = 0; j < NITER; j++)
{
//printf("GPU iteration numéro %d : \n", j);
hipMemcpy(particles_gpu, particles_res, NPARTICLES*sizeof(Particle), hipMemcpyHostToDevice);
updateKernel<<<(NPARTICLES+TPB-1) / TPB, TPB>>>(particles_gpu, dt, j);
hipMemcpy(particles_res, particles_gpu, NPARTICLES*sizeof(Particle), hipMemcpyDeviceToHost);
}
hipDeviceSynchronize();
//double iElaps_gpu = cpuSecond() - iStart_gpu;
//double iStart_cpu = cpuSecond();
//CPU computation
for (int j = 0; j < NITER; j++)
{
updateCPU(particles_cpu, dt, j, NPARTICLES);
}
//double iElaps_cpu = cpuSecond() - iStart_cpu;
for (int i = 0; i < NPARTICLES; i++) {
if(i < NPARTICLES)
{
if(!(compareParticle(particles_cpu[i], particles_res[i]))) {
flag = 0;
break;
}
}
}
/*double iStart_DtoH = cpuSecond();
cudaMemcpy(particles_cpu, particles_gpu, NPARTICLES*sizeof(Particle), cudaMemcpyDeviceToHost);
double iElaps_DtoH = cpuSecond() - iStart_DtoH; */
printf("Comparing the output for each implementation… ");
if (flag)
{
printf("Correct!\n");
} else {
printf("Incorrect\n");
}
//delete[] particles_cpu;
//delete[] particles_res;
hipFree(particles_gpu);
hipHostFree(particles_gpu);
hipHostFree(particles_res); // Free the memory
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12updateKernelP8Particlefj
.globl _Z12updateKernelP8Particlefj
.p2align 8
.type _Z12updateKernelP8Particlefj,@function
_Z12updateKernelP8Particlefj:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, s15, s4, v[0:1]
v_mad_u64_u32 v[5:6], null, v4, 24, s[0:1]
s_mov_b32 s0, s3
s_clause 0x1
global_load_b128 v[0:3], v[5:6], off
global_load_b64 v[7:8], v[5:6], off offset:16
v_mad_u64_u32 v[9:10], null, v4, 10, s[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v4, v9, 0xcccccccd
v_lshrrev_b32_e32 v4, 3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v4, 10
v_sub_nc_u32_e32 v4, v9, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v4, v4
s_waitcnt vmcnt(1)
v_fma_f32 v3, s2, v4, v3
s_waitcnt vmcnt(0)
v_fma_f32 v7, s2, v4, v7
v_fmac_f32_e32 v8, s2, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v0, s2, v3, v0
v_fma_f32 v1, s2, v7, v1
s_delay_alu instid0(VALU_DEP_3)
v_fmac_f32_e32 v2, s2, v8
s_clause 0x1
global_store_b64 v[5:6], v[7:8], off offset:16
global_store_b128 v[5:6], v[0:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12updateKernelP8Particlefj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12updateKernelP8Particlefj, .Lfunc_end0-_Z12updateKernelP8Particlefj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12updateKernelP8Particlefj
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z12updateKernelP8Particlefj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <sys/time.h>
#define EPSILON 1.0e-6
struct Particle
{
float3 position;
float3 velocity;
};
__host__ __device__ uint gen_random(uint a, uint b, uint c = 10, uint seed = 10)
{
return (seed*a+b) % c;
}
__device__ void update_position(Particle* part_array_gpu, float dt, uint i)
{
part_array_gpu[i].position.x += part_array_gpu[i].velocity.x * dt;
part_array_gpu[i].position.y += part_array_gpu[i].velocity.y * dt;
part_array_gpu[i].position.z += part_array_gpu[i].velocity.z * dt;
}
__device__ void update_velocity(Particle* part_array_gpu, float dt, uint i, uint j)
{
part_array_gpu[i].velocity.x += (float)(gen_random(i, j)) * dt;
part_array_gpu[i].velocity.y += (float)(gen_random(i, j)) * dt;
part_array_gpu[i].velocity.z += (float)(gen_random(i, j)) * dt;
}
__global__ void updateKernel(Particle* part_array_gpu, float dt, uint j)
{
const int i = blockIdx.x*blockDim.x + threadIdx.x;
update_velocity(part_array_gpu, dt, i, j);
update_position(part_array_gpu, dt, i);
}
__host__ void updateCPU(Particle* part_array_cpu, float dt, uint j, uint NPARTICLES)
{
for (int i = 0; i < NPARTICLES; i++)
{
if(i < NPARTICLES)
{
part_array_cpu[i].velocity.x += (float)(gen_random(i, j)) * dt;
part_array_cpu[i].velocity.y += (float)(gen_random(i, j)) * dt;
part_array_cpu[i].velocity.z += (float)(gen_random(i, j)) * dt;
part_array_cpu[i].position.x += part_array_cpu[i].velocity.x * dt;
part_array_cpu[i].position.y += part_array_cpu[i].velocity.y * dt;
part_array_cpu[i].position.z += part_array_cpu[i].velocity.z * dt;
}
}
}
__host__ bool compare_float(float a, float b)
{
return (fabs(a-b) < EPSILON);
}
__host__ bool compare_float3(float3 a, float3 b)
{
return (compare_float(a.x, b.x) && compare_float(a.y, b.y) && compare_float(a.z, b.z));
}
__host__ bool compareParticle(Particle particle1, Particle particle2)
{
bool result = true;
result &= compare_float3(particle1.position, particle2.position);
result &= compare_float3(particle1.velocity, particle2.velocity);
return result;
}
double cpuSecond()
{
struct timeval tp;
gettimeofday(&tp,NULL);
return ((double)tp.tv_sec + (double)tp.tv_usec*1.e-6);
}
int main(int argc, char** argv)
{
const float dt = 1.0;
bool flag = 1;
const int NITER = atoi(argv[1]);
const int TPB = atoi(argv[2]);
const int NPARTICLES = atoi(argv[3]);
// Declare a pointer for an array of particles
Particle* particles_gpu;
Particle* particles_cpu;
Particle* particles_res;
hipHostAlloc((void **) &particles_cpu, NPARTICLES*sizeof(Particle), hipHostMallocDefault);
hipHostAlloc((void **) &particles_res, NPARTICLES*sizeof(Particle), hipHostMallocDefault);
// Allocate device memory to store the output array
hipMalloc(&particles_gpu, NPARTICLES*sizeof(Particle));
for (int i = 0; i < NPARTICLES; i++)
{
if(i < NPARTICLES)
{
particles_cpu[i].velocity.x = 0;
particles_cpu[i].velocity.y = 0;
particles_cpu[i].velocity.z = 0;
particles_cpu[i].position.x = 1;
particles_cpu[i].position.y = 1;
particles_cpu[i].position.z = 1;
particles_res[i].velocity.x = 0;
particles_res[i].velocity.y = 0;
particles_res[i].velocity.z = 0;
particles_res[i].position.x = 1;
particles_res[i].position.y = 1;
particles_res[i].position.z = 1;
}
}
//double iStart_HtoD = cpuSecond();
//double iElaps_HtoD = cpuSecond() - iStart_HtoD;
double iStart_gpu = cpuSecond();
//GPU computation
for (int j = 0; j < NITER; j++)
{
//printf("GPU iteration numéro %d : \n", j);
hipMemcpy(particles_gpu, particles_res, NPARTICLES*sizeof(Particle), hipMemcpyHostToDevice);
updateKernel<<<(NPARTICLES+TPB-1) / TPB, TPB>>>(particles_gpu, dt, j);
hipMemcpy(particles_res, particles_gpu, NPARTICLES*sizeof(Particle), hipMemcpyDeviceToHost);
}
hipDeviceSynchronize();
//double iElaps_gpu = cpuSecond() - iStart_gpu;
//double iStart_cpu = cpuSecond();
//CPU computation
for (int j = 0; j < NITER; j++)
{
updateCPU(particles_cpu, dt, j, NPARTICLES);
}
//double iElaps_cpu = cpuSecond() - iStart_cpu;
for (int i = 0; i < NPARTICLES; i++) {
if(i < NPARTICLES)
{
if(!(compareParticle(particles_cpu[i], particles_res[i]))) {
flag = 0;
break;
}
}
}
/*double iStart_DtoH = cpuSecond();
cudaMemcpy(particles_cpu, particles_gpu, NPARTICLES*sizeof(Particle), cudaMemcpyDeviceToHost);
double iElaps_DtoH = cpuSecond() - iStart_DtoH; */
printf("Comparing the output for each implementation… ");
if (flag)
{
printf("Correct!\n");
} else {
printf("Incorrect\n");
}
//delete[] particles_cpu;
//delete[] particles_res;
hipFree(particles_gpu);
hipHostFree(particles_gpu);
hipHostFree(particles_res); // Free the memory
return 0;
} | .text
.file "exercise_2a.hip"
.globl _Z10gen_randomjjjj # -- Begin function _Z10gen_randomjjjj
.p2align 4, 0x90
.type _Z10gen_randomjjjj,@function
_Z10gen_randomjjjj: # @_Z10gen_randomjjjj
.cfi_startproc
# %bb.0:
movl %edx, %r8d
# kill: def $esi killed $esi def $rsi
# kill: def $edi killed $edi def $rdi
imull %ecx, %edi
leal (%rdi,%rsi), %eax
xorl %edx, %edx
divl %r8d
movl %edx, %eax
retq
.Lfunc_end0:
.size _Z10gen_randomjjjj, .Lfunc_end0-_Z10gen_randomjjjj
.cfi_endproc
# -- End function
.globl _Z27__device_stub__updateKernelP8Particlefj # -- Begin function _Z27__device_stub__updateKernelP8Particlefj
.p2align 4, 0x90
.type _Z27__device_stub__updateKernelP8Particlefj,@function
_Z27__device_stub__updateKernelP8Particlefj: # @_Z27__device_stub__updateKernelP8Particlefj
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movss %xmm0, 4(%rsp)
movl %esi, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12updateKernelP8Particlefj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z27__device_stub__updateKernelP8Particlefj, .Lfunc_end1-_Z27__device_stub__updateKernelP8Particlefj
.cfi_endproc
# -- End function
.globl _Z9updateCPUP8Particlefjj # -- Begin function _Z9updateCPUP8Particlefjj
.p2align 4, 0x90
.type _Z9updateCPUP8Particlefjj,@function
_Z9updateCPUP8Particlefjj: # @_Z9updateCPUP8Particlefjj
.cfi_startproc
# %bb.0:
testl %edx, %edx
je .LBB2_3
# %bb.1: # %.lr.ph.preheader
movl %edx, %eax
shlq $3, %rax
leaq (%rax,%rax,2), %rax
xorl %ecx, %ecx
movl $3435973837, %edx # imm = 0xCCCCCCCD
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %esi, %r8d
imulq %rdx, %r8
shrq $35, %r8
addl %r8d, %r8d
leal (%r8,%r8,4), %r8d
movl %esi, %r9d
subl %r8d, %r9d
xorps %xmm1, %xmm1
cvtsi2ss %r9, %xmm1
mulss %xmm0, %xmm1
movss 12(%rdi,%rcx), %xmm2 # xmm2 = mem[0],zero,zero,zero
addss %xmm1, %xmm2
movss %xmm2, 12(%rdi,%rcx)
movss 16(%rdi,%rcx), %xmm3 # xmm3 = mem[0],zero,zero,zero
addss %xmm1, %xmm3
movss %xmm3, 16(%rdi,%rcx)
addss 20(%rdi,%rcx), %xmm1
movss %xmm1, 20(%rdi,%rcx)
mulss %xmm0, %xmm2
addss (%rdi,%rcx), %xmm2
movss %xmm2, (%rdi,%rcx)
mulss %xmm0, %xmm3
addss 4(%rdi,%rcx), %xmm3
movss %xmm3, 4(%rdi,%rcx)
mulss %xmm0, %xmm1
addss 8(%rdi,%rcx), %xmm1
movss %xmm1, 8(%rdi,%rcx)
addq $24, %rcx
addl $10, %esi
cmpq %rcx, %rax
jne .LBB2_2
.LBB2_3: # %._crit_edge
retq
.Lfunc_end2:
.size _Z9updateCPUP8Particlefjj, .Lfunc_end2-_Z9updateCPUP8Particlefjj
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z13compare_floatff
.LCPI3_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI3_1:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z13compare_floatff
.p2align 4, 0x90
.type _Z13compare_floatff,@function
_Z13compare_floatff: # @_Z13compare_floatff
.cfi_startproc
# %bb.0:
subss %xmm1, %xmm0
andps .LCPI3_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movsd .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero
ucomisd %xmm0, %xmm1
seta %al
retq
.Lfunc_end3:
.size _Z13compare_floatff, .Lfunc_end3-_Z13compare_floatff
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z14compare_float315HIP_vector_typeIfLj3EES0_
.LCPI4_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI4_1:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z14compare_float315HIP_vector_typeIfLj3EES0_
.p2align 4, 0x90
.type _Z14compare_float315HIP_vector_typeIfLj3EES0_,@function
_Z14compare_float315HIP_vector_typeIfLj3EES0_: # @_Z14compare_float315HIP_vector_typeIfLj3EES0_
.cfi_startproc
# %bb.0:
movaps %xmm0, %xmm4
subss %xmm2, %xmm4
andps .LCPI4_0(%rip), %xmm4
cvtss2sd %xmm4, %xmm5
movsd .LCPI4_1(%rip), %xmm4 # xmm4 = mem[0],zero
ucomisd %xmm5, %xmm4
jbe .LBB4_4
# %bb.1:
subps %xmm2, %xmm0
shufps $85, %xmm0, %xmm0 # xmm0 = xmm0[1,1,1,1]
andps .LCPI4_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
ucomisd %xmm0, %xmm4
jbe .LBB4_4
# %bb.2:
subss %xmm3, %xmm1
andps .LCPI4_0(%rip), %xmm1
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
ucomisd %xmm0, %xmm4
seta %al
# kill: def $al killed $al killed $eax
retq
.LBB4_4:
xorl %eax, %eax
# kill: def $al killed $al killed $eax
retq
.Lfunc_end4:
.size _Z14compare_float315HIP_vector_typeIfLj3EES0_, .Lfunc_end4-_Z14compare_float315HIP_vector_typeIfLj3EES0_
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z15compareParticle8ParticleS_
.LCPI5_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI5_1:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z15compareParticle8ParticleS_
.p2align 4, 0x90
.type _Z15compareParticle8ParticleS_,@function
_Z15compareParticle8ParticleS_: # @_Z15compareParticle8ParticleS_
.cfi_startproc
# %bb.0:
leaq 32(%rsp), %rcx
leaq 8(%rsp), %rdx
movsd 8(%rsp), %xmm1 # xmm1 = mem[0],zero
movsd 32(%rsp), %xmm2 # xmm2 = mem[0],zero
movaps %xmm1, %xmm0
subss %xmm2, %xmm0
andps .LCPI5_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm3
movsd .LCPI5_1(%rip), %xmm0 # xmm0 = mem[0],zero
ucomisd %xmm3, %xmm0
jbe .LBB5_4
# %bb.1:
subps %xmm2, %xmm1
shufps $85, %xmm1, %xmm1 # xmm1 = xmm1[1,1,1,1]
andps .LCPI5_0(%rip), %xmm1
cvtss2sd %xmm1, %xmm1
ucomisd %xmm1, %xmm0
jbe .LBB5_4
# %bb.2:
movss 16(%rsp), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss 40(%rsp), %xmm1
andps .LCPI5_0(%rip), %xmm1
cvtss2sd %xmm1, %xmm1
ucomisd %xmm1, %xmm0
seta %al
jmp .LBB5_5
.LBB5_4:
xorl %eax, %eax
.LBB5_5: # %_Z14compare_float315HIP_vector_typeIfLj3EES0_.exit
movsd 12(%rdx), %xmm1 # xmm1 = mem[0],zero
movsd 12(%rcx), %xmm2 # xmm2 = mem[0],zero
movaps %xmm1, %xmm3
subss %xmm2, %xmm3
andps .LCPI5_0(%rip), %xmm3
cvtss2sd %xmm3, %xmm3
ucomisd %xmm3, %xmm0
jbe .LBB5_9
# %bb.6:
subps %xmm2, %xmm1
shufps $85, %xmm1, %xmm1 # xmm1 = xmm1[1,1,1,1]
andps .LCPI5_0(%rip), %xmm1
cvtss2sd %xmm1, %xmm1
ucomisd %xmm1, %xmm0
jbe .LBB5_9
# %bb.7:
movss 20(%rdx), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss 20(%rcx), %xmm1
andps .LCPI5_0(%rip), %xmm1
cvtss2sd %xmm1, %xmm1
ucomisd %xmm1, %xmm0
seta %cl
andb %cl, %al
# kill: def $al killed $al killed $eax
retq
.LBB5_9:
xorl %ecx, %ecx
andb %cl, %al
# kill: def $al killed $al killed $eax
retq
.Lfunc_end5:
.size _Z15compareParticle8ParticleS_, .Lfunc_end5-_Z15compareParticle8ParticleS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z9cpuSecondv
.LCPI6_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z9cpuSecondv
.p2align 4, 0x90
.type _Z9cpuSecondv,@function
_Z9cpuSecondv: # @_Z9cpuSecondv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm1
cvtsi2sdq 16(%rsp), %xmm0
mulsd .LCPI6_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z9cpuSecondv, .Lfunc_end6-_Z9cpuSecondv
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI7_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI7_1:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 24(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
movslq %r13d, %r14
leaq (,%r14,8), %rax
leaq (%rax,%rax,2), %r12
leaq 8(%rsp), %rdi
movq %r12, %rsi
xorl %edx, %edx
callq hipHostAlloc
movq %rsp, %rdi
movq %r12, %rsi
xorl %edx, %edx
callq hipHostAlloc
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
testl %r14d, %r14d
jle .LBB7_3
# %bb.1: # %.lr.ph.preheader
movl %r13d, %eax
shlq $3, %rax
leaq (%rax,%rax,2), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB7_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rdx
movl $0, 12(%rdx,%rcx)
movq 8(%rsp), %rdx
movl $0, 16(%rdx,%rcx)
movq 8(%rsp), %rdx
movl $0, 20(%rdx,%rcx)
movq 8(%rsp), %rdx
movl $1065353216, (%rdx,%rcx) # imm = 0x3F800000
movq 8(%rsp), %rdx
movl $1065353216, 4(%rdx,%rcx) # imm = 0x3F800000
movq 8(%rsp), %rdx
movl $1065353216, 8(%rdx,%rcx) # imm = 0x3F800000
movq (%rsp), %rdx
movl $0, 12(%rdx,%rcx)
movq (%rsp), %rdx
movl $0, 16(%rdx,%rcx)
movq (%rsp), %rdx
movl $0, 20(%rdx,%rcx)
movq (%rsp), %rdx
movl $1065353216, (%rdx,%rcx) # imm = 0x3F800000
movq (%rsp), %rdx
movl $1065353216, 4(%rdx,%rcx) # imm = 0x3F800000
movq (%rsp), %rdx
movl $1065353216, 8(%rdx,%rcx) # imm = 0x3F800000
addq $24, %rcx
cmpq %rcx, %rax
jne .LBB7_2
.LBB7_3: # %._crit_edge
movq %r13, 32(%rsp) # 8-byte Spill
xorl %r14d, %r14d
leaq 96(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
testl %ebx, %ebx
jle .LBB7_8
# %bb.4: # %.lr.ph72
movabsq $4294967296, %rcx # imm = 0x100000000
movq 32(%rsp), %rax # 8-byte Reload
leal (%r15,%rax), %ebp
decl %ebp
movl %r15d, %r13d
orq %rcx, %r13
jmp .LBB7_6
.p2align 4, 0x90
.LBB7_5: # in Loop: Header=BB7_6 Depth=1
movq (%rsp), %rdi
movq 16(%rsp), %rsi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
incl %r14d
cmpl %r14d, %ebx
je .LBB7_8
.LBB7_6: # =>This Inner Loop Header: Depth=1
movq 16(%rsp), %rdi
movq (%rsp), %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movl %ebp, %eax
cltd
idivl %r15d
# kill: def $eax killed $eax def $rax
movabsq $4294967296, %rcx # imm = 0x100000000
orq %rcx, %rax
movq %rax, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_5
# %bb.7: # in Loop: Header=BB7_6 Depth=1
movq 16(%rsp), %rax
movq %rax, 88(%rsp)
movl $1065353216, 28(%rsp) # imm = 0x3F800000
movl %r14d, 24(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 28(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z12updateKernelP8Particlefj, %edi
leaq 96(%rsp), %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB7_5
.LBB7_8: # %._crit_edge73
callq hipDeviceSynchronize
testl %ebx, %ebx
movq 32(%rsp), %r11 # 8-byte Reload
jle .LBB7_14
# %bb.9: # %.lr.ph76
movl %r11d, %eax
shlq $3, %rax
leaq (%rax,%rax,2), %rax
xorl %ecx, %ecx
movl $3435973837, %edx # imm = 0xCCCCCCCD
jmp .LBB7_11
.p2align 4, 0x90
.LBB7_10: # %_Z9updateCPUP8Particlefjj.exit
# in Loop: Header=BB7_11 Depth=1
incl %ecx
cmpl %ebx, %ecx
je .LBB7_14
.LBB7_11: # =>This Loop Header: Depth=1
# Child Loop BB7_13 Depth 2
testl %r11d, %r11d
je .LBB7_10
# %bb.12: # %.lr.ph.i.preheader
# in Loop: Header=BB7_11 Depth=1
movq 8(%rsp), %rsi
movl %ecx, %edi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB7_13: # %.lr.ph.i
# Parent Loop BB7_11 Depth=1
# => This Inner Loop Header: Depth=2
movl %edi, %r9d
imulq %rdx, %r9
shrq $35, %r9
addl %r9d, %r9d
leal (%r9,%r9,4), %r9d
movl %edi, %r10d
subl %r9d, %r10d
xorps %xmm0, %xmm0
cvtsi2ss %r10, %xmm0
movss 12(%rsi,%r8), %xmm1 # xmm1 = mem[0],zero,zero,zero
addss %xmm0, %xmm1
movss %xmm1, 12(%rsi,%r8)
movss 16(%rsi,%r8), %xmm2 # xmm2 = mem[0],zero,zero,zero
addss %xmm0, %xmm2
movss %xmm2, 16(%rsi,%r8)
addss 20(%rsi,%r8), %xmm0
movss %xmm0, 20(%rsi,%r8)
addss (%rsi,%r8), %xmm1
movss %xmm1, (%rsi,%r8)
addss 4(%rsi,%r8), %xmm2
movss %xmm2, 4(%rsi,%r8)
addss 8(%rsi,%r8), %xmm0
movss %xmm0, 8(%rsi,%r8)
addq $24, %r8
addl $10, %edi
cmpq %r8, %rax
jne .LBB7_13
jmp .LBB7_10
.LBB7_14: # %.preheader
movl $.Lstr.1, %ebx
testl %r11d, %r11d
jle .LBB7_28
# %bb.15: # %.lr.ph79
movq 8(%rsp), %rax
movq (%rsp), %rcx
movl %r11d, %edx
shlq $3, %rdx
leaq (%rdx,%rdx,2), %rdx
xorl %esi, %esi
movaps .LCPI7_0(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN]
movsd .LCPI7_1(%rip), %xmm1 # xmm1 = mem[0],zero
jmp .LBB7_16
.p2align 4, 0x90
.LBB7_25: # in Loop: Header=BB7_16 Depth=1
xorl %r8d, %r8d
testb %r8b, %dil
je .LBB7_27
.LBB7_26: # in Loop: Header=BB7_16 Depth=1
addq $24, %rsi
cmpq %rsi, %rdx
je .LBB7_28
.LBB7_16: # =>This Inner Loop Header: Depth=1
movsd (%rax,%rsi), %xmm2 # xmm2 = mem[0],zero
movsd (%rcx,%rsi), %xmm3 # xmm3 = mem[0],zero
movaps %xmm2, %xmm4
subss %xmm3, %xmm4
andps %xmm0, %xmm4
cvtss2sd %xmm4, %xmm4
ucomisd %xmm4, %xmm1
jbe .LBB7_20
# %bb.17: # in Loop: Header=BB7_16 Depth=1
subps %xmm3, %xmm2
shufps $85, %xmm2, %xmm2 # xmm2 = xmm2[1,1,1,1]
andps %xmm0, %xmm2
cvtss2sd %xmm2, %xmm2
ucomisd %xmm2, %xmm1
jbe .LBB7_20
# %bb.18: # in Loop: Header=BB7_16 Depth=1
movss 8(%rax,%rsi), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss 8(%rcx,%rsi), %xmm2
andps %xmm0, %xmm2
cvtss2sd %xmm2, %xmm2
ucomisd %xmm2, %xmm1
seta %dil
jmp .LBB7_21
.p2align 4, 0x90
.LBB7_20: # in Loop: Header=BB7_16 Depth=1
xorl %edi, %edi
.LBB7_21: # %_Z14compare_float315HIP_vector_typeIfLj3EES0_.exit.i
# in Loop: Header=BB7_16 Depth=1
movsd 12(%rax,%rsi), %xmm2 # xmm2 = mem[0],zero
movsd 12(%rcx,%rsi), %xmm3 # xmm3 = mem[0],zero
movaps %xmm2, %xmm4
subss %xmm3, %xmm4
andps %xmm0, %xmm4
cvtss2sd %xmm4, %xmm4
ucomisd %xmm4, %xmm1
jbe .LBB7_25
# %bb.22: # in Loop: Header=BB7_16 Depth=1
subps %xmm3, %xmm2
shufps $85, %xmm2, %xmm2 # xmm2 = xmm2[1,1,1,1]
andps %xmm0, %xmm2
cvtss2sd %xmm2, %xmm2
ucomisd %xmm2, %xmm1
jbe .LBB7_25
# %bb.23: # in Loop: Header=BB7_16 Depth=1
movss 20(%rax,%rsi), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss 20(%rcx,%rsi), %xmm2
andps %xmm0, %xmm2
cvtss2sd %xmm2, %xmm2
ucomisd %xmm2, %xmm1
seta %r8b
testb %r8b, %dil
jne .LBB7_26
.LBB7_27:
movl $.Lstr, %ebx
.LBB7_28: # %.critedge
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq puts@PLT
movq 16(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipHostFree
movq (%rsp), %rdi
callq hipHostFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size main, .Lfunc_end7-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12updateKernelP8Particlefj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12updateKernelP8Particlefj,@object # @_Z12updateKernelP8Particlefj
.section .rodata,"a",@progbits
.globl _Z12updateKernelP8Particlefj
.p2align 3, 0x0
_Z12updateKernelP8Particlefj:
.quad _Z27__device_stub__updateKernelP8Particlefj
.size _Z12updateKernelP8Particlefj, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Comparing the output for each implementation\342\200\246 "
.size .L.str, 49
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12updateKernelP8Particlefj"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Incorrect"
.size .Lstr, 10
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Correct!"
.size .Lstr.1, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__updateKernelP8Particlefj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12updateKernelP8Particlefj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12updateKernelP8Particlefj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 1.430511474609375e-06 ; /* 0x00000018ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE.U32 R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0005 */
/*0070*/ LDG.E R7, [R2.64+0xc] ; /* 0x00000c0402077981 */
/* 0x000ea8000c1e1900 */
/*0080*/ LDG.E R9, [R2.64+0x10] ; /* 0x0000100402097981 */
/* 0x000ee8000c1e1900 */
/*0090*/ LDG.E R11, [R2.64+0x14] ; /* 0x00001404020b7981 */
/* 0x000f28000c1e1900 */
/*00a0*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000f68000c1e1900 */
/*00b0*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040402087981 */
/* 0x000f68000c1e1900 */
/*00c0*/ LDG.E R10, [R2.64+0x8] ; /* 0x00000804020a7981 */
/* 0x000f62000c1e1900 */
/*00d0*/ HFMA2.MMA R5, -RZ, RZ, 0, 5.9604644775390625e-07 ; /* 0x0000000aff057435 */
/* 0x000fd400000001ff */
/*00e0*/ IMAD R0, R0, R5, c[0x0][0x16c] ; /* 0x00005b0000007624 */
/* 0x000fc800078e0205 */
/*00f0*/ IMAD.WIDE.U32 R4, R0, -0x33333333, RZ ; /* 0xcccccccd00047825 */
/* 0x000fca00078e00ff */
/*0100*/ SHF.R.U32.HI R5, RZ, 0x3, R5 ; /* 0x00000003ff057819 */
/* 0x000fca0000011605 */
/*0110*/ IMAD R0, R5, -0xa, R0 ; /* 0xfffffff605007824 */
/* 0x000fcc00078e0200 */
/*0120*/ I2F.U32 R0, R0 ; /* 0x0000000000007306 */
/* 0x000ea40000201000 */
/*0130*/ FFMA R7, R0.reuse, c[0x0][0x168], R7 ; /* 0x00005a0000077a23 */
/* 0x044fe40000000007 */
/*0140*/ FFMA R9, R0, c[0x0][0x168], R9 ; /* 0x00005a0000097a23 */
/* 0x008fc60000000009 */
/*0150*/ STG.E [R2.64+0xc], R7 ; /* 0x00000c0702007986 */
/* 0x000fe2000c101904 */
/*0160*/ FFMA R11, R0, c[0x0][0x168], R11 ; /* 0x00005a00000b7a23 */
/* 0x010fc6000000000b */
/*0170*/ STG.E [R2.64+0x10], R9 ; /* 0x0000100902007986 */
/* 0x000fe2000c101904 */
/*0180*/ FFMA R5, R7, c[0x0][0x168], R6 ; /* 0x00005a0007057a23 */
/* 0x020fc60000000006 */
/*0190*/ STG.E [R2.64+0x14], R11 ; /* 0x0000140b02007986 */
/* 0x000fe2000c101904 */
/*01a0*/ FFMA R13, R9, c[0x0][0x168], R8 ; /* 0x00005a00090d7a23 */
/* 0x000fc60000000008 */
/*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*01c0*/ FFMA R15, R11, c[0x0][0x168], R10 ; /* 0x00005a000b0f7a23 */
/* 0x000fc6000000000a */
/*01d0*/ STG.E [R2.64+0x4], R13 ; /* 0x0000040d02007986 */
/* 0x000fe8000c101904 */
/*01e0*/ STG.E [R2.64+0x8], R15 ; /* 0x0000080f02007986 */
/* 0x000fe2000c101904 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12updateKernelP8Particlefj
.globl _Z12updateKernelP8Particlefj
.p2align 8
.type _Z12updateKernelP8Particlefj,@function
_Z12updateKernelP8Particlefj:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, s15, s4, v[0:1]
v_mad_u64_u32 v[5:6], null, v4, 24, s[0:1]
s_mov_b32 s0, s3
s_clause 0x1
global_load_b128 v[0:3], v[5:6], off
global_load_b64 v[7:8], v[5:6], off offset:16
v_mad_u64_u32 v[9:10], null, v4, 10, s[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v4, v9, 0xcccccccd
v_lshrrev_b32_e32 v4, 3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v4, 10
v_sub_nc_u32_e32 v4, v9, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v4, v4
s_waitcnt vmcnt(1)
v_fma_f32 v3, s2, v4, v3
s_waitcnt vmcnt(0)
v_fma_f32 v7, s2, v4, v7
v_fmac_f32_e32 v8, s2, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v0, s2, v3, v0
v_fma_f32 v1, s2, v7, v1
s_delay_alu instid0(VALU_DEP_3)
v_fmac_f32_e32 v2, s2, v8
s_clause 0x1
global_store_b64 v[5:6], v[7:8], off offset:16
global_store_b128 v[5:6], v[0:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12updateKernelP8Particlefj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12updateKernelP8Particlefj, .Lfunc_end0-_Z12updateKernelP8Particlefj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12updateKernelP8Particlefj
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z12updateKernelP8Particlefj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b6019_00000000-6_exercise_2a.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2068:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2068:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10gen_randomjjjj
.type _Z10gen_randomjjjj, @function
_Z10gen_randomjjjj:
.LFB2057:
.cfi_startproc
endbr64
movl %edx, %r8d
imull %edi, %ecx
leal (%rcx,%rsi), %eax
movl $0, %edx
divl %r8d
movl %edx, %eax
ret
.cfi_endproc
.LFE2057:
.size _Z10gen_randomjjjj, .-_Z10gen_randomjjjj
.globl _Z15update_positionP8Particlefj
.type _Z15update_positionP8Particlefj, @function
_Z15update_positionP8Particlefj:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z15update_positionP8Particlefj, .-_Z15update_positionP8Particlefj
.globl _Z15update_velocityP8Particlefjj
.type _Z15update_velocityP8Particlefjj, @function
_Z15update_velocityP8Particlefjj:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z15update_velocityP8Particlefjj, .-_Z15update_velocityP8Particlefjj
.globl _Z9updateCPUP8Particlefjj
.type _Z9updateCPUP8Particlefjj, @function
_Z9updateCPUP8Particlefjj:
.LFB2060:
.cfi_startproc
endbr64
movl %esi, %ecx
testl %edx, %edx
je .L8
movq %rdi, %rax
movl %edx, %edx
leaq (%rdx,%rdx,2), %rdx
leaq (%rdi,%rdx,8), %rsi
movl $3435973837, %edx
.L12:
movl %ecx, %edi
imulq %rdx, %rdi
shrq $35, %rdi
leal (%rdi,%rdi,4), %edi
addl %edi, %edi
movl %ecx, %r8d
subl %edi, %r8d
pxor %xmm1, %xmm1
cvtsi2ssq %r8, %xmm1
mulss %xmm0, %xmm1
movaps %xmm1, %xmm3
addss 12(%rax), %xmm3
movss %xmm3, 12(%rax)
movaps %xmm1, %xmm2
addss 16(%rax), %xmm2
movss %xmm2, 16(%rax)
addss 20(%rax), %xmm1
movss %xmm1, 20(%rax)
mulss %xmm0, %xmm3
addss (%rax), %xmm3
movss %xmm3, (%rax)
mulss %xmm0, %xmm2
addss 4(%rax), %xmm2
movss %xmm2, 4(%rax)
mulss %xmm0, %xmm1
addss 8(%rax), %xmm1
movss %xmm1, 8(%rax)
addl $10, %ecx
addq $24, %rax
cmpq %rsi, %rax
jne .L12
.L8:
ret
.cfi_endproc
.LFE2060:
.size _Z9updateCPUP8Particlefjj, .-_Z9updateCPUP8Particlefjj
.globl _Z13compare_floatff
.type _Z13compare_floatff, @function
_Z13compare_floatff:
.LFB2061:
.cfi_startproc
endbr64
subss %xmm1, %xmm0
andps .LC0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movsd .LC1(%rip), %xmm1
comisd %xmm0, %xmm1
seta %al
ret
.cfi_endproc
.LFE2061:
.size _Z13compare_floatff, .-_Z13compare_floatff
.globl _Z14compare_float36float3S_
.type _Z14compare_float36float3S_, @function
_Z14compare_float36float3S_:
.LFB2062:
.cfi_startproc
endbr64
movq %xmm0, -16(%rsp)
movss %xmm1, -8(%rsp)
movq %xmm2, -32(%rsp)
movss %xmm3, -24(%rsp)
movss -16(%rsp), %xmm0
subss -32(%rsp), %xmm0
andps .LC0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movsd .LC1(%rip), %xmm1
comisd %xmm0, %xmm1
jbe .L23
movss -12(%rsp), %xmm0
subss -28(%rsp), %xmm0
andps .LC0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
comisd %xmm0, %xmm1
jbe .L24
movss -8(%rsp), %xmm0
subss %xmm3, %xmm0
andps .LC0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
comisd %xmm0, %xmm1
seta %al
ret
.L23:
movl $0, %eax
ret
.L24:
movl $0, %eax
ret
.cfi_endproc
.LFE2062:
.size _Z14compare_float36float3S_, .-_Z14compare_float36float3S_
.globl _Z15compareParticle8ParticleS_
.type _Z15compareParticle8ParticleS_, @function
_Z15compareParticle8ParticleS_:
.LFB2063:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq 40(%rsp), %xmm2
movss 48(%rsp), %xmm3
movq 16(%rsp), %xmm0
movss 24(%rsp), %xmm1
call _Z14compare_float36float3S_
movl %eax, %ebx
movq 52(%rsp), %xmm2
movss 60(%rsp), %xmm3
movq 28(%rsp), %xmm0
movss 36(%rsp), %xmm1
call _Z14compare_float36float3S_
andl %ebx, %eax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _Z15compareParticle8ParticleS_, .-_Z15compareParticle8ParticleS_
.globl _Z9cpuSecondv
.type _Z9cpuSecondv, @function
_Z9cpuSecondv:
.LFB2064:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LC1(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2064:
.size _Z9cpuSecondv, .-_Z9cpuSecondv
.globl _Z42__device_stub__Z12updateKernelP8ParticlefjP8Particlefj
.type _Z42__device_stub__Z12updateKernelP8ParticlefjP8Particlefj, @function
_Z42__device_stub__Z12updateKernelP8ParticlefjP8Particlefj:
.LFB2090:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movss %xmm0, 4(%rsp)
movl %esi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L35
.L31:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12updateKernelP8Particlefj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L31
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z42__device_stub__Z12updateKernelP8ParticlefjP8Particlefj, .-_Z42__device_stub__Z12updateKernelP8ParticlefjP8Particlefj
.globl _Z12updateKernelP8Particlefj
.type _Z12updateKernelP8Particlefj, @function
_Z12updateKernelP8Particlefj:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z12updateKernelP8ParticlefjP8Particlefj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z12updateKernelP8Particlefj, .-_Z12updateKernelP8Particlefj
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "Correct!\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "Comparing the output for each implementation\342\200\246 "
.section .rodata.str1.1
.LC6:
.string "Incorrect\n"
.text
.globl main
.type main, @function
main:
.LFB2065:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, %r13d
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
movl %eax, %r12d
movq 24(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r14
movl %eax, 12(%rsp)
cltq
leaq (%rax,%rax,2), %rbp
salq $3, %rbp
leaq 32(%rsp), %rdi
movl $0, %edx
movq %rbp, %rsi
call cudaHostAlloc@PLT
leaq 40(%rsp), %rdi
movl $0, %edx
movq %rbp, %rsi
call cudaHostAlloc@PLT
leaq 24(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
testl %r14d, %r14d
jle .L40
leal -1(%r14), %eax
leaq 3(%rax,%rax,2), %rcx
salq $3, %rcx
movl $0, %eax
movss .LC3(%rip), %xmm0
.L41:
movq %rax, %rdx
addq 32(%rsp), %rdx
movl $0x00000000, 12(%rdx)
movl $0x00000000, 16(%rdx)
movl $0x00000000, 20(%rdx)
movss %xmm0, (%rdx)
movq 32(%rsp), %rdx
movss %xmm0, 4(%rdx,%rax)
movq 32(%rsp), %rdx
movss %xmm0, 8(%rdx,%rax)
movq %rax, %rdx
addq 40(%rsp), %rdx
movl $0x00000000, 12(%rdx)
movl $0x00000000, 16(%rdx)
movl $0x00000000, 20(%rdx)
movss %xmm0, (%rdx)
movq 40(%rsp), %rdx
movss %xmm0, 4(%rdx,%rax)
movq 40(%rsp), %rdx
movss %xmm0, 8(%rdx,%rax)
addq $24, %rax
cmpq %rcx, %rax
jne .L41
.L40:
call _Z9cpuSecondv
testl %ebx, %ebx
jle .L42
movl $0, %ebx
movl 12(%rsp), %eax
leal -1(%rax,%r12), %eax
movl %eax, 12(%rsp)
jmp .L44
.L43:
movl $2, %ecx
movq %rbp, %rdx
movq 24(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
addl $1, %ebx
cmpl %r13d, %ebx
je .L61
.L44:
movl $1, %ecx
movq %rbp, %rdx
movq 40(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %r15d, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl 12(%rsp), %eax
cltd
idivl %r12d
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L43
movl %ebx, %esi
movss .LC3(%rip), %xmm0
movq 24(%rsp), %rdi
call _Z42__device_stub__Z12updateKernelP8ParticlefjP8Particlefj
jmp .L43
.L61:
call cudaDeviceSynchronize@PLT
movl $0, %ebx
.L45:
movl %r14d, %edx
movl %ebx, %esi
movss .LC3(%rip), %xmm0
movq 32(%rsp), %rdi
call _Z9updateCPUP8Particlefjj
addl $1, %ebx
cmpl %r13d, %ebx
jne .L45
.L51:
testl %r14d, %r14d
jle .L46
movq 32(%rsp), %rbx
movq 40(%rsp), %rbp
leal -1(%r14), %eax
leaq (%rax,%rax,2), %rax
leaq 24(%rbx,%rax,8), %r12
.L48:
subq $48, %rsp
.cfi_def_cfa_offset 192
movdqu 0(%rbp), %xmm1
movups %xmm1, 24(%rsp)
movq 16(%rbp), %rax
movq %rax, 40(%rsp)
movdqu (%rbx), %xmm2
movups %xmm2, (%rsp)
movq 16(%rbx), %rax
movq %rax, 16(%rsp)
call _Z15compareParticle8ParticleS_
addq $48, %rsp
.cfi_def_cfa_offset 144
testb %al, %al
je .L47
addq $24, %rbx
addq $24, %rbp
cmpq %rbx, %r12
jne .L48
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L50:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L52:
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFreeHost@PLT
movq 40(%rsp), %rdi
call cudaFreeHost@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L62
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L50
.L42:
call cudaDeviceSynchronize@PLT
jmp .L51
.L47:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L52
.L62:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2065:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z12updateKernelP8Particlefj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2093:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z12updateKernelP8Particlefj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC0:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long -1598689907
.long 1051772663
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "exercise_2a.hip"
.globl _Z10gen_randomjjjj # -- Begin function _Z10gen_randomjjjj
.p2align 4, 0x90
.type _Z10gen_randomjjjj,@function
_Z10gen_randomjjjj: # @_Z10gen_randomjjjj
.cfi_startproc
# %bb.0:
movl %edx, %r8d
# kill: def $esi killed $esi def $rsi
# kill: def $edi killed $edi def $rdi
imull %ecx, %edi
leal (%rdi,%rsi), %eax
xorl %edx, %edx
divl %r8d
movl %edx, %eax
retq
.Lfunc_end0:
.size _Z10gen_randomjjjj, .Lfunc_end0-_Z10gen_randomjjjj
.cfi_endproc
# -- End function
.globl _Z27__device_stub__updateKernelP8Particlefj # -- Begin function _Z27__device_stub__updateKernelP8Particlefj
.p2align 4, 0x90
.type _Z27__device_stub__updateKernelP8Particlefj,@function
_Z27__device_stub__updateKernelP8Particlefj: # @_Z27__device_stub__updateKernelP8Particlefj
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movss %xmm0, 4(%rsp)
movl %esi, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12updateKernelP8Particlefj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z27__device_stub__updateKernelP8Particlefj, .Lfunc_end1-_Z27__device_stub__updateKernelP8Particlefj
.cfi_endproc
# -- End function
.globl _Z9updateCPUP8Particlefjj # -- Begin function _Z9updateCPUP8Particlefjj
.p2align 4, 0x90
.type _Z9updateCPUP8Particlefjj,@function
_Z9updateCPUP8Particlefjj: # @_Z9updateCPUP8Particlefjj
.cfi_startproc
# %bb.0:
testl %edx, %edx
je .LBB2_3
# %bb.1: # %.lr.ph.preheader
movl %edx, %eax
shlq $3, %rax
leaq (%rax,%rax,2), %rax
xorl %ecx, %ecx
movl $3435973837, %edx # imm = 0xCCCCCCCD
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %esi, %r8d
imulq %rdx, %r8
shrq $35, %r8
addl %r8d, %r8d
leal (%r8,%r8,4), %r8d
movl %esi, %r9d
subl %r8d, %r9d
xorps %xmm1, %xmm1
cvtsi2ss %r9, %xmm1
mulss %xmm0, %xmm1
movss 12(%rdi,%rcx), %xmm2 # xmm2 = mem[0],zero,zero,zero
addss %xmm1, %xmm2
movss %xmm2, 12(%rdi,%rcx)
movss 16(%rdi,%rcx), %xmm3 # xmm3 = mem[0],zero,zero,zero
addss %xmm1, %xmm3
movss %xmm3, 16(%rdi,%rcx)
addss 20(%rdi,%rcx), %xmm1
movss %xmm1, 20(%rdi,%rcx)
mulss %xmm0, %xmm2
addss (%rdi,%rcx), %xmm2
movss %xmm2, (%rdi,%rcx)
mulss %xmm0, %xmm3
addss 4(%rdi,%rcx), %xmm3
movss %xmm3, 4(%rdi,%rcx)
mulss %xmm0, %xmm1
addss 8(%rdi,%rcx), %xmm1
movss %xmm1, 8(%rdi,%rcx)
addq $24, %rcx
addl $10, %esi
cmpq %rcx, %rax
jne .LBB2_2
.LBB2_3: # %._crit_edge
retq
.Lfunc_end2:
.size _Z9updateCPUP8Particlefjj, .Lfunc_end2-_Z9updateCPUP8Particlefjj
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z13compare_floatff
.LCPI3_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI3_1:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z13compare_floatff
.p2align 4, 0x90
.type _Z13compare_floatff,@function
_Z13compare_floatff: # @_Z13compare_floatff
.cfi_startproc
# %bb.0:
subss %xmm1, %xmm0
andps .LCPI3_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movsd .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero
ucomisd %xmm0, %xmm1
seta %al
retq
.Lfunc_end3:
.size _Z13compare_floatff, .Lfunc_end3-_Z13compare_floatff
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z14compare_float315HIP_vector_typeIfLj3EES0_
.LCPI4_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI4_1:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z14compare_float315HIP_vector_typeIfLj3EES0_
.p2align 4, 0x90
.type _Z14compare_float315HIP_vector_typeIfLj3EES0_,@function
_Z14compare_float315HIP_vector_typeIfLj3EES0_: # @_Z14compare_float315HIP_vector_typeIfLj3EES0_
.cfi_startproc
# %bb.0:
movaps %xmm0, %xmm4
subss %xmm2, %xmm4
andps .LCPI4_0(%rip), %xmm4
cvtss2sd %xmm4, %xmm5
movsd .LCPI4_1(%rip), %xmm4 # xmm4 = mem[0],zero
ucomisd %xmm5, %xmm4
jbe .LBB4_4
# %bb.1:
subps %xmm2, %xmm0
shufps $85, %xmm0, %xmm0 # xmm0 = xmm0[1,1,1,1]
andps .LCPI4_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
ucomisd %xmm0, %xmm4
jbe .LBB4_4
# %bb.2:
subss %xmm3, %xmm1
andps .LCPI4_0(%rip), %xmm1
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
ucomisd %xmm0, %xmm4
seta %al
# kill: def $al killed $al killed $eax
retq
.LBB4_4:
xorl %eax, %eax
# kill: def $al killed $al killed $eax
retq
.Lfunc_end4:
.size _Z14compare_float315HIP_vector_typeIfLj3EES0_, .Lfunc_end4-_Z14compare_float315HIP_vector_typeIfLj3EES0_
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z15compareParticle8ParticleS_
.LCPI5_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI5_1:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z15compareParticle8ParticleS_
.p2align 4, 0x90
.type _Z15compareParticle8ParticleS_,@function
_Z15compareParticle8ParticleS_: # @_Z15compareParticle8ParticleS_
.cfi_startproc
# %bb.0:
leaq 32(%rsp), %rcx
leaq 8(%rsp), %rdx
movsd 8(%rsp), %xmm1 # xmm1 = mem[0],zero
movsd 32(%rsp), %xmm2 # xmm2 = mem[0],zero
movaps %xmm1, %xmm0
subss %xmm2, %xmm0
andps .LCPI5_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm3
movsd .LCPI5_1(%rip), %xmm0 # xmm0 = mem[0],zero
ucomisd %xmm3, %xmm0
jbe .LBB5_4
# %bb.1:
subps %xmm2, %xmm1
shufps $85, %xmm1, %xmm1 # xmm1 = xmm1[1,1,1,1]
andps .LCPI5_0(%rip), %xmm1
cvtss2sd %xmm1, %xmm1
ucomisd %xmm1, %xmm0
jbe .LBB5_4
# %bb.2:
movss 16(%rsp), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss 40(%rsp), %xmm1
andps .LCPI5_0(%rip), %xmm1
cvtss2sd %xmm1, %xmm1
ucomisd %xmm1, %xmm0
seta %al
jmp .LBB5_5
.LBB5_4:
xorl %eax, %eax
.LBB5_5: # %_Z14compare_float315HIP_vector_typeIfLj3EES0_.exit
movsd 12(%rdx), %xmm1 # xmm1 = mem[0],zero
movsd 12(%rcx), %xmm2 # xmm2 = mem[0],zero
movaps %xmm1, %xmm3
subss %xmm2, %xmm3
andps .LCPI5_0(%rip), %xmm3
cvtss2sd %xmm3, %xmm3
ucomisd %xmm3, %xmm0
jbe .LBB5_9
# %bb.6:
subps %xmm2, %xmm1
shufps $85, %xmm1, %xmm1 # xmm1 = xmm1[1,1,1,1]
andps .LCPI5_0(%rip), %xmm1
cvtss2sd %xmm1, %xmm1
ucomisd %xmm1, %xmm0
jbe .LBB5_9
# %bb.7:
movss 20(%rdx), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss 20(%rcx), %xmm1
andps .LCPI5_0(%rip), %xmm1
cvtss2sd %xmm1, %xmm1
ucomisd %xmm1, %xmm0
seta %cl
andb %cl, %al
# kill: def $al killed $al killed $eax
retq
.LBB5_9:
xorl %ecx, %ecx
andb %cl, %al
# kill: def $al killed $al killed $eax
retq
.Lfunc_end5:
.size _Z15compareParticle8ParticleS_, .Lfunc_end5-_Z15compareParticle8ParticleS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z9cpuSecondv
.LCPI6_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z9cpuSecondv
.p2align 4, 0x90
.type _Z9cpuSecondv,@function
_Z9cpuSecondv: # @_Z9cpuSecondv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm1
cvtsi2sdq 16(%rsp), %xmm0
mulsd .LCPI6_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z9cpuSecondv, .Lfunc_end6-_Z9cpuSecondv
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI7_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI7_1:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 24(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
movslq %r13d, %r14
leaq (,%r14,8), %rax
leaq (%rax,%rax,2), %r12
leaq 8(%rsp), %rdi
movq %r12, %rsi
xorl %edx, %edx
callq hipHostAlloc
movq %rsp, %rdi
movq %r12, %rsi
xorl %edx, %edx
callq hipHostAlloc
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
testl %r14d, %r14d
jle .LBB7_3
# %bb.1: # %.lr.ph.preheader
movl %r13d, %eax
shlq $3, %rax
leaq (%rax,%rax,2), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB7_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rdx
movl $0, 12(%rdx,%rcx)
movq 8(%rsp), %rdx
movl $0, 16(%rdx,%rcx)
movq 8(%rsp), %rdx
movl $0, 20(%rdx,%rcx)
movq 8(%rsp), %rdx
movl $1065353216, (%rdx,%rcx) # imm = 0x3F800000
movq 8(%rsp), %rdx
movl $1065353216, 4(%rdx,%rcx) # imm = 0x3F800000
movq 8(%rsp), %rdx
movl $1065353216, 8(%rdx,%rcx) # imm = 0x3F800000
movq (%rsp), %rdx
movl $0, 12(%rdx,%rcx)
movq (%rsp), %rdx
movl $0, 16(%rdx,%rcx)
movq (%rsp), %rdx
movl $0, 20(%rdx,%rcx)
movq (%rsp), %rdx
movl $1065353216, (%rdx,%rcx) # imm = 0x3F800000
movq (%rsp), %rdx
movl $1065353216, 4(%rdx,%rcx) # imm = 0x3F800000
movq (%rsp), %rdx
movl $1065353216, 8(%rdx,%rcx) # imm = 0x3F800000
addq $24, %rcx
cmpq %rcx, %rax
jne .LBB7_2
.LBB7_3: # %._crit_edge
movq %r13, 32(%rsp) # 8-byte Spill
xorl %r14d, %r14d
leaq 96(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
testl %ebx, %ebx
jle .LBB7_8
# %bb.4: # %.lr.ph72
movabsq $4294967296, %rcx # imm = 0x100000000
movq 32(%rsp), %rax # 8-byte Reload
leal (%r15,%rax), %ebp
decl %ebp
movl %r15d, %r13d
orq %rcx, %r13
jmp .LBB7_6
.p2align 4, 0x90
.LBB7_5: # in Loop: Header=BB7_6 Depth=1
movq (%rsp), %rdi
movq 16(%rsp), %rsi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
incl %r14d
cmpl %r14d, %ebx
je .LBB7_8
.LBB7_6: # =>This Inner Loop Header: Depth=1
movq 16(%rsp), %rdi
movq (%rsp), %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movl %ebp, %eax
cltd
idivl %r15d
# kill: def $eax killed $eax def $rax
movabsq $4294967296, %rcx # imm = 0x100000000
orq %rcx, %rax
movq %rax, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_5
# %bb.7: # in Loop: Header=BB7_6 Depth=1
movq 16(%rsp), %rax
movq %rax, 88(%rsp)
movl $1065353216, 28(%rsp) # imm = 0x3F800000
movl %r14d, 24(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 28(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z12updateKernelP8Particlefj, %edi
leaq 96(%rsp), %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB7_5
.LBB7_8: # %._crit_edge73
callq hipDeviceSynchronize
testl %ebx, %ebx
movq 32(%rsp), %r11 # 8-byte Reload
jle .LBB7_14
# %bb.9: # %.lr.ph76
movl %r11d, %eax
shlq $3, %rax
leaq (%rax,%rax,2), %rax
xorl %ecx, %ecx
movl $3435973837, %edx # imm = 0xCCCCCCCD
jmp .LBB7_11
.p2align 4, 0x90
.LBB7_10: # %_Z9updateCPUP8Particlefjj.exit
# in Loop: Header=BB7_11 Depth=1
incl %ecx
cmpl %ebx, %ecx
je .LBB7_14
.LBB7_11: # =>This Loop Header: Depth=1
# Child Loop BB7_13 Depth 2
testl %r11d, %r11d
je .LBB7_10
# %bb.12: # %.lr.ph.i.preheader
# in Loop: Header=BB7_11 Depth=1
movq 8(%rsp), %rsi
movl %ecx, %edi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB7_13: # %.lr.ph.i
# Parent Loop BB7_11 Depth=1
# => This Inner Loop Header: Depth=2
movl %edi, %r9d
imulq %rdx, %r9
shrq $35, %r9
addl %r9d, %r9d
leal (%r9,%r9,4), %r9d
movl %edi, %r10d
subl %r9d, %r10d
xorps %xmm0, %xmm0
cvtsi2ss %r10, %xmm0
movss 12(%rsi,%r8), %xmm1 # xmm1 = mem[0],zero,zero,zero
addss %xmm0, %xmm1
movss %xmm1, 12(%rsi,%r8)
movss 16(%rsi,%r8), %xmm2 # xmm2 = mem[0],zero,zero,zero
addss %xmm0, %xmm2
movss %xmm2, 16(%rsi,%r8)
addss 20(%rsi,%r8), %xmm0
movss %xmm0, 20(%rsi,%r8)
addss (%rsi,%r8), %xmm1
movss %xmm1, (%rsi,%r8)
addss 4(%rsi,%r8), %xmm2
movss %xmm2, 4(%rsi,%r8)
addss 8(%rsi,%r8), %xmm0
movss %xmm0, 8(%rsi,%r8)
addq $24, %r8
addl $10, %edi
cmpq %r8, %rax
jne .LBB7_13
jmp .LBB7_10
.LBB7_14: # %.preheader
movl $.Lstr.1, %ebx
testl %r11d, %r11d
jle .LBB7_28
# %bb.15: # %.lr.ph79
movq 8(%rsp), %rax
movq (%rsp), %rcx
movl %r11d, %edx
shlq $3, %rdx
leaq (%rdx,%rdx,2), %rdx
xorl %esi, %esi
movaps .LCPI7_0(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN]
movsd .LCPI7_1(%rip), %xmm1 # xmm1 = mem[0],zero
jmp .LBB7_16
.p2align 4, 0x90
.LBB7_25: # in Loop: Header=BB7_16 Depth=1
xorl %r8d, %r8d
testb %r8b, %dil
je .LBB7_27
.LBB7_26: # in Loop: Header=BB7_16 Depth=1
addq $24, %rsi
cmpq %rsi, %rdx
je .LBB7_28
.LBB7_16: # =>This Inner Loop Header: Depth=1
movsd (%rax,%rsi), %xmm2 # xmm2 = mem[0],zero
movsd (%rcx,%rsi), %xmm3 # xmm3 = mem[0],zero
movaps %xmm2, %xmm4
subss %xmm3, %xmm4
andps %xmm0, %xmm4
cvtss2sd %xmm4, %xmm4
ucomisd %xmm4, %xmm1
jbe .LBB7_20
# %bb.17: # in Loop: Header=BB7_16 Depth=1
subps %xmm3, %xmm2
shufps $85, %xmm2, %xmm2 # xmm2 = xmm2[1,1,1,1]
andps %xmm0, %xmm2
cvtss2sd %xmm2, %xmm2
ucomisd %xmm2, %xmm1
jbe .LBB7_20
# %bb.18: # in Loop: Header=BB7_16 Depth=1
movss 8(%rax,%rsi), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss 8(%rcx,%rsi), %xmm2
andps %xmm0, %xmm2
cvtss2sd %xmm2, %xmm2
ucomisd %xmm2, %xmm1
seta %dil
jmp .LBB7_21
.p2align 4, 0x90
.LBB7_20: # in Loop: Header=BB7_16 Depth=1
xorl %edi, %edi
.LBB7_21: # %_Z14compare_float315HIP_vector_typeIfLj3EES0_.exit.i
# in Loop: Header=BB7_16 Depth=1
movsd 12(%rax,%rsi), %xmm2 # xmm2 = mem[0],zero
movsd 12(%rcx,%rsi), %xmm3 # xmm3 = mem[0],zero
movaps %xmm2, %xmm4
subss %xmm3, %xmm4
andps %xmm0, %xmm4
cvtss2sd %xmm4, %xmm4
ucomisd %xmm4, %xmm1
jbe .LBB7_25
# %bb.22: # in Loop: Header=BB7_16 Depth=1
subps %xmm3, %xmm2
shufps $85, %xmm2, %xmm2 # xmm2 = xmm2[1,1,1,1]
andps %xmm0, %xmm2
cvtss2sd %xmm2, %xmm2
ucomisd %xmm2, %xmm1
jbe .LBB7_25
# %bb.23: # in Loop: Header=BB7_16 Depth=1
movss 20(%rax,%rsi), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss 20(%rcx,%rsi), %xmm2
andps %xmm0, %xmm2
cvtss2sd %xmm2, %xmm2
ucomisd %xmm2, %xmm1
seta %r8b
testb %r8b, %dil
jne .LBB7_26
.LBB7_27:
movl $.Lstr, %ebx
.LBB7_28: # %.critedge
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq puts@PLT
movq 16(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipHostFree
movq (%rsp), %rdi
callq hipHostFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size main, .Lfunc_end7-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12updateKernelP8Particlefj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12updateKernelP8Particlefj,@object # @_Z12updateKernelP8Particlefj
.section .rodata,"a",@progbits
.globl _Z12updateKernelP8Particlefj
.p2align 3, 0x0
_Z12updateKernelP8Particlefj:
.quad _Z27__device_stub__updateKernelP8Particlefj
.size _Z12updateKernelP8Particlefj, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Comparing the output for each implementation\342\200\246 "
.size .L.str, 49
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12updateKernelP8Particlefj"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Incorrect"
.size .Lstr, 10
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Correct!"
.size .Lstr.1, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__updateKernelP8Particlefj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12updateKernelP8Particlefj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /* Program : To add two randomly generated vectors with the help of a GPU
* Author : Anant Shah
* Roll Number : EE16B105
* Date : 14-8-2018
**/
#include<stdio.h>
#include<cuda.h>
#include<time.h>
#include<math.h>
#include<stdlib.h>
#define MAX_NUM 10000000 /* Maximum integer upto which random numbers are produced */
#define ERROR_HANDLER(error_msg) error_handler(error_msg)
void error_handler(cudaError_t error_msg){
/* Handles error messages */
if(error_msg != cudaSuccess){
printf("%s in %s at line %d\n",cudaGetErrorString(error_msg),__FILE__,__LINE__);
exit(EXIT_FAILURE);
}
}
__global__ void vecAdd(int *A,int *B,double *C,int vector_size,int num_ops_per_thread) {
/* One of the parameters of this kernel function is the number of operations per thread.
* This code follows the cyclic distribution of elements to each thread.
* eg : num_ops_per_thread = 2.
* Then C[0] and C[vector_size/2] will be calculated by thread with Id = 0.
* C[1] and C[vector_size/2+1] will be calculated by thread with Id = 1 and so on.
*/
int id = blockIdx.x*blockDim.x+threadIdx.x;
/* Since we are performing the cyclic distribution, we need to make sure thread Ids grater than (vector_size/num_ops_per_thread) do not execute as the * y will only repeat the addition performed by another thread. Also, if the size of the vector and number of operations per thread are not perfectly
* , then some threads will have to do some extra operations.
*/
if(id<vector_size/num_ops_per_thread){
for(int i=id;i<vector_size;i+=(vector_size/num_ops_per_thread)){
C[i] = A[i] + B[i];
}
}
}
void readFileData(char *file,int size,int *vector){
/* Function to read the integers from a .txt or .dat file */
FILE *fp;
fp = fopen(file,"r+");
if(fp!=NULL){
for(int i=0;i<size;i++){
fscanf(fp,"%d",(vector+i));
}
fclose(fp);
}
else{
printf("error : File %s not found",file);
exit(EXIT_FAILURE);
}
}
int main(int argc,char **argv) {
if(argc!=6){
printf("Error : Invalid number of arguments \n");
exit(EXIT_FAILURE);
}
/*************************** Variable Declaration ****************************/
int *h_A; /* Vector declared on the host */
int *h_B; /* Vector declared on the host */
double *h_C; /* Vector which will be the sum of previously deined vectors */
int *d_A; /* Vector which will be a copy of <h_A> but on the device(GPU) */
int *d_B; /* Vector which will be a copy of <h_B> but on the device(GPU) */
double *d_C; /* Vector which stores the sum of <d_A> and <d_B> on the device */
size_t size_input; /* Bytes required to store the vectors */
size_t size_output; /* Bytes required to store the output vector */
clock_t start; /* Start time of the program */
clock_t stop; /* Stop time of the program */
int num_ops_per_thread; /* Number of operations per thread */
int num_blocks; /* Number of blocks in the grid */
int num_threads; /* Number of threads per block */
int vector_size; /* Size of the vector(number of data elements) */
char *file_A; /* File which contains the data elements of the integer vector A */
char *file_B; /* File which contains the data elements of the integer vector B*/
num_threads = atoi(argv[1]);
num_ops_per_thread = atoi(argv[2]);
vector_size = atoi(argv[3]);
file_A = argv[4];
file_B = argv[5];
size_input = vector_size*sizeof(int);
size_output = vector_size*sizeof(double);
/******************************************************************************/
/************************** Memory Allocation *********************************/
h_A = (int *)malloc(size_input); /* Allocate memory to the vector on the host */
h_B = (int *)malloc(size_input);
h_C = (double *)malloc(size_output);
/************************** Store the integers from the input files ***************************/
readFileData(file_A,vector_size,h_A);
readFileData(file_B,vector_size,h_B);
/******************************************************************************/
ERROR_HANDLER(cudaMalloc((void **)&d_A,size_input));
ERROR_HANDLER(cudaMalloc((void **)&d_B,size_input));
ERROR_HANDLER(cudaMalloc((void **)&d_C,size_output));
/************************* Copy vectors to the host ***************************/
ERROR_HANDLER(cudaMemcpy(d_A, h_A, size_input, cudaMemcpyHostToDevice));
ERROR_HANDLER(cudaMemcpy(d_B, h_B, size_input, cudaMemcpyHostToDevice));
/************************ Add the vectors *************************************/
num_blocks = (vector_size+num_threads*num_ops_per_thread-1)/(num_threads*num_ops_per_thread);
/* The ceiling function for the number of blocks is not applied as the number of threads is exactly equal to the number of data items to work on */
start = clock();
vecAdd<<<num_blocks,num_threads>>>(d_A, d_B, d_C, vector_size, num_ops_per_thread);
ERROR_HANDLER(cudaDeviceSynchronize());
stop = clock();
ERROR_HANDLER(cudaMemcpy(h_C, d_C, size_output, cudaMemcpyDeviceToHost)); /* Copy the result back to the host */
printf("Time for the vector addition : %f (milli-seconds) \n",1000*(stop-start)/(float)CLOCKS_PER_SEC);
/************************* Free Memory ****************************************/
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
free(h_A);
free(h_B);
free(h_C);
} | code for sm_80
Function : _Z6vecAddPiS_Pdii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R4, c[0x0][0x17c] ; /* 0x00005f0000047a13 */
/* 0x000fe20000000000 */
/*0020*/ ULDC.64 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IABS R6, c[0x0][0x178] ; /* 0x00005e0000067a13 */
/* 0x000fe20000000000 */
/*0040*/ ULOP3.LUT UR4, UR4, UR5, URZ, 0x3c, !UPT ; /* 0x0000000504047292 */
/* 0x000fe2000f8e3c3f */
/*0050*/ I2F.RP R0, R4 ; /* 0x0000000400007306 */
/* 0x000e2a0000209400 */
/*0060*/ ISETP.LE.AND P2, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fc6000bf43270 */
/*0070*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*0080*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fcc0007ffe0ff */
/*0090*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe200078e00ff */
/*00b0*/ IADD3 R5, RZ, -R3, RZ ; /* 0x80000003ff057210 */
/* 0x002fca0007ffe0ff */
/*00c0*/ IMAD R5, R5, R4, RZ ; /* 0x0000000405057224 */
/* 0x000fc800078e02ff */
/*00d0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fe200078e0002 */
/*00e0*/ MOV R5, R6 ; /* 0x0000000600057202 */
/* 0x000fe20000000f00 */
/*00f0*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0100*/ IMAD.HI.U32 R0, R3, R5, RZ ; /* 0x0000000503007227 */
/* 0x000fc800078e00ff */
/*0110*/ IMAD.MOV R3, RZ, RZ, -R0 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a00 */
/*0120*/ IMAD R3, R4.reuse, R3, R5 ; /* 0x0000000304037224 */
/* 0x040fe400078e0205 */
/*0130*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e260000002100 */
/*0140*/ ISETP.GT.U32.AND P1, PT, R4, R3, PT ; /* 0x000000030400720c */
/* 0x000fda0003f24070 */
/*0150*/ @!P1 IADD3 R3, R3, -R4.reuse, RZ ; /* 0x8000000403039210 */
/* 0x080fe40007ffe0ff */
/*0160*/ @!P1 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100009810 */
/* 0x000fe40007ffe0ff */
/*0170*/ ISETP.GE.U32.AND P0, PT, R3, R4, PT ; /* 0x000000040300720c */
/* 0x000fe40003f06070 */
/*0180*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fe20003f25270 */
/*0190*/ IMAD R3, R2, c[0x0][0x0], R5 ; /* 0x0000000002037a24 */
/* 0x001fd400078e0205 */
/*01a0*/ @P0 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100000810 */
/* 0x000fe40007ffe0ff */
/*01b0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fc60003f06270 */
/*01c0*/ @!P2 IMAD.MOV R0, RZ, RZ, -R0 ; /* 0x000000ffff00a224 */
/* 0x000fe200078e0a00 */
/*01d0*/ @!P1 LOP3.LUT R0, RZ, c[0x0][0x17c], RZ, 0x33, !PT ; /* 0x00005f00ff009a12 */
/* 0x000fc800078e33ff */
/*01e0*/ ISETP.GE.OR P0, PT, R3, R0, P0 ; /* 0x000000000300720c */
/* 0x000fda0000706670 */
/*01f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0200*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000209000 */
/*0210*/ IADD3 R7, RZ, -R0, RZ ; /* 0x80000000ff077210 */
/* 0x000fe20007ffe0ff */
/*0220*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0230*/ LOP3.LUT R2, RZ, R3, RZ, 0x33, !PT ; /* 0x00000003ff027212 */
/* 0x000fe200078e33ff */
/*0240*/ BSSY B0, 0x4c0 ; /* 0x0000027000007945 */
/* 0x000fe20003800000 */
/*0250*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc60003f45070 */
/*0260*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0270*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0280*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0290*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*02a0*/ IMAD R7, R7, R5, RZ ; /* 0x0000000507077224 */
/* 0x002fc800078e02ff */
/*02b0*/ IMAD.HI.U32 R8, R5, R7, R4 ; /* 0x0000000705087227 */
/* 0x000fe200078e0004 */
/*02c0*/ IADD3 R5, R2, c[0x0][0x178], RZ ; /* 0x00005e0002057a10 */
/* 0x000fca0007ffe0ff */
/*02d0*/ IMAD.HI.U32 R8, R8, R5, RZ ; /* 0x0000000508087227 */
/* 0x000fca00078e00ff */
/*02e0*/ IADD3 R2, -R8, RZ, RZ ; /* 0x000000ff08027210 */
/* 0x000fca0007ffe1ff */
/*02f0*/ IMAD R5, R0, R2, R5 ; /* 0x0000000200057224 */
/* 0x000fca00078e0205 */
/*0300*/ ISETP.GE.U32.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f06070 */
/*0310*/ @P0 IMAD.IADD R5, R5, 0x1, -R0 ; /* 0x0000000105050824 */
/* 0x000fe200078e0a00 */
/*0320*/ @P0 IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108080810 */
/* 0x000fc80007ffe0ff */
/*0330*/ ISETP.GE.U32.AND P1, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f26070 */
/*0340*/ @P1 IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108081810 */
/* 0x000fe40007ffe0ff */
/*0350*/ @!P2 LOP3.LUT R8, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff08a212 */
/* 0x000fc800078e33ff */
/*0360*/ IADD3 R2, R8.reuse, 0x1, RZ ; /* 0x0000000108027810 */
/* 0x040fe40007ffe0ff */
/*0370*/ ISETP.GE.U32.AND P1, PT, R8, 0x3, PT ; /* 0x000000030800780c */
/* 0x000fe40003f26070 */
/*0380*/ LOP3.LUT P0, R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fda000780c0ff */
/*0390*/ @!P0 BRA 0x4b0 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*03a0*/ HFMA2.MMA R4, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff047435 */
/* 0x000fe200000001ff */
/*03b0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fc800078e00ff */
/*03c0*/ IMAD.WIDE R6, R3, R8, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fc800078e0208 */
/*03d0*/ IMAD.WIDE R8, R3, R8, c[0x0][0x160] ; /* 0x0000580003087625 */
/* 0x000fc800078e0208 */
/*03e0*/ IMAD.WIDE R4, R3, R4, c[0x0][0x170] ; /* 0x00005c0003047625 */
/* 0x000fc800078e0204 */
/*03f0*/ LDG.E R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x0000a8000c1e1900 */
/*0400*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0002a2000c1e1900 */
/*0410*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe20007ffe0ff */
/*0420*/ IMAD.IADD R3, R0, 0x1, R3 ; /* 0x0000000100037824 */
/* 0x000fc600078e0203 */
/*0430*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*0440*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x001fc800078e0206 */
/*0450*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x002fe200078e0208 */
/*0460*/ IADD3 R10, R10, R11, RZ ; /* 0x0000000b0a0a7210 */
/* 0x004fcc0007ffe0ff */
/*0470*/ I2F.F64 R10, R10 ; /* 0x0000000a000a7312 */
/* 0x000e240000201c00 */
/*0480*/ STG.E.64 [R4.64], R10 ; /* 0x0000000a04007986 */
/* 0x0011e4000c101b04 */
/*0490*/ IMAD.WIDE R4, R0, 0x8, R4 ; /* 0x0000000800047825 */
/* 0x001fe200078e0204 */
/*04a0*/ @P0 BRA 0x3f0 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*04b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04c0*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*04d0*/ MOV R4, 0x4 ; /* 0x0000000400047802 */
/* 0x001fca0000000f00 */
/*04e0*/ IMAD.WIDE R6, R3, R4, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fc800078e0204 */
/*04f0*/ IMAD.WIDE R4, R3, R4, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fe200078e0204 */
/*0500*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea8000c1e1900 */
/*0510*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea2000c1e1900 */
/*0520*/ HFMA2.MMA R10, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff0a7435 */
/* 0x000fe200000001ff */
/*0530*/ IMAD.WIDE R14, R0, 0x4, R6 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0206 */
/*0540*/ IMAD.WIDE R12, R0, 0x4, R4 ; /* 0x00000004000c7825 */
/* 0x000fca00078e0204 */
/*0550*/ IMAD.WIDE R10, R3, R10, c[0x0][0x170] ; /* 0x00005c00030a7625 */
/* 0x000fc800078e020a */
/*0560*/ IMAD.IADD R9, R2, 0x1, R9 ; /* 0x0000000102097824 */
/* 0x004fcc00078e0209 */
/*0570*/ I2F.F64 R8, R9 ; /* 0x0000000900087312 */
/* 0x000e240000201c00 */
/*0580*/ STG.E.64 [R10.64], R8 ; /* 0x000000080a007986 */
/* 0x0011e8000c101b04 */
/*0590*/ LDG.E R2, [R14.64] ; /* 0x000000040e027981 */
/* 0x000ea8000c1e1900 */
/*05a0*/ LDG.E R17, [R12.64] ; /* 0x000000040c117981 */
/* 0x000ea2000c1e1900 */
/*05b0*/ IMAD.WIDE R6, R0, 0x8, R10 ; /* 0x0000000800067825 */
/* 0x000fc800078e020a */
/*05c0*/ IMAD.WIDE R18, R0, 0x4, R14 ; /* 0x0000000400127825 */
/* 0x000fc800078e020e */
/*05d0*/ IMAD.IADD R2, R2, 0x1, R17 ; /* 0x0000000102027824 */
/* 0x004fe400078e0211 */
/*05e0*/ IMAD.WIDE R16, R0.reuse, 0x4, R12 ; /* 0x0000000400107825 */
/* 0x040fe400078e020c */
/*05f0*/ I2F.F64 R4, R2 ; /* 0x0000000200047312 */
/* 0x000e640000201c00 */
/*0600*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */
/* 0x0023e8000c101b04 */
/*0610*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000ea8000c1e1900 */
/*0620*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x000ea2000c1e1900 */
/*0630*/ IMAD.WIDE R10, R0, 0x8, R6 ; /* 0x00000008000a7825 */
/* 0x001fc800078e0206 */
/*0640*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0212 */
/*0650*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fe200078e0210 */
/*0660*/ IADD3 R8, R20, R21, RZ ; /* 0x0000001514087210 */
/* 0x004fcc0007ffe0ff */
/*0670*/ I2F.F64 R8, R8 ; /* 0x0000000800087312 */
/* 0x000e240000201c00 */
/*0680*/ STG.E.64 [R10.64], R8 ; /* 0x000000080a007986 */
/* 0x0011e8000c101b04 */
/*0690*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea8000c1e1900 */
/*06a0*/ LDG.E R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000ea2000c1e1900 */
/*06b0*/ IMAD.WIDE R6, R0.reuse, 0x8, R10 ; /* 0x0000000800067825 */
/* 0x042fe200078e020a */
/*06c0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*06d0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*06e0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe20003f06270 */
/*06f0*/ IMAD.IADD R4, R14, 0x1, R13 ; /* 0x000000010e047824 */
/* 0x004fcc00078e020d */
/*0700*/ I2F.F64 R4, R4 ; /* 0x0000000400047312 */
/* 0x000e640000201c00 */
/*0710*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */
/* 0x0021e8000c101b04 */
/*0720*/ @!P0 BRA 0x4d0 ; /* 0xfffffda000008947 */
/* 0x000fea000383ffff */
/*0730*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0740*/ BRA 0x740; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* Program : To add two randomly generated vectors with the help of a GPU
* Author : Anant Shah
* Roll Number : EE16B105
* Date : 14-8-2018
**/
#include<stdio.h>
#include<cuda.h>
#include<time.h>
#include<math.h>
#include<stdlib.h>
#define MAX_NUM 10000000 /* Maximum integer upto which random numbers are produced */
#define ERROR_HANDLER(error_msg) error_handler(error_msg)
void error_handler(cudaError_t error_msg){
/* Handles error messages */
if(error_msg != cudaSuccess){
printf("%s in %s at line %d\n",cudaGetErrorString(error_msg),__FILE__,__LINE__);
exit(EXIT_FAILURE);
}
}
__global__ void vecAdd(int *A,int *B,double *C,int vector_size,int num_ops_per_thread) {
/* One of the parameters of this kernel function is the number of operations per thread.
* This code follows the cyclic distribution of elements to each thread.
* eg : num_ops_per_thread = 2.
* Then C[0] and C[vector_size/2] will be calculated by thread with Id = 0.
* C[1] and C[vector_size/2+1] will be calculated by thread with Id = 1 and so on.
*/
int id = blockIdx.x*blockDim.x+threadIdx.x;
/* Since we are performing the cyclic distribution, we need to make sure thread Ids grater than (vector_size/num_ops_per_thread) do not execute as the * y will only repeat the addition performed by another thread. Also, if the size of the vector and number of operations per thread are not perfectly
* , then some threads will have to do some extra operations.
*/
if(id<vector_size/num_ops_per_thread){
for(int i=id;i<vector_size;i+=(vector_size/num_ops_per_thread)){
C[i] = A[i] + B[i];
}
}
}
void readFileData(char *file,int size,int *vector){
/* Function to read the integers from a .txt or .dat file */
FILE *fp;
fp = fopen(file,"r+");
if(fp!=NULL){
for(int i=0;i<size;i++){
fscanf(fp,"%d",(vector+i));
}
fclose(fp);
}
else{
printf("error : File %s not found",file);
exit(EXIT_FAILURE);
}
}
int main(int argc,char **argv) {
if(argc!=6){
printf("Error : Invalid number of arguments \n");
exit(EXIT_FAILURE);
}
/*************************** Variable Declaration ****************************/
int *h_A; /* Vector declared on the host */
int *h_B; /* Vector declared on the host */
double *h_C; /* Vector which will be the sum of previously deined vectors */
int *d_A; /* Vector which will be a copy of <h_A> but on the device(GPU) */
int *d_B; /* Vector which will be a copy of <h_B> but on the device(GPU) */
double *d_C; /* Vector which stores the sum of <d_A> and <d_B> on the device */
size_t size_input; /* Bytes required to store the vectors */
size_t size_output; /* Bytes required to store the output vector */
clock_t start; /* Start time of the program */
clock_t stop; /* Stop time of the program */
int num_ops_per_thread; /* Number of operations per thread */
int num_blocks; /* Number of blocks in the grid */
int num_threads; /* Number of threads per block */
int vector_size; /* Size of the vector(number of data elements) */
char *file_A; /* File which contains the data elements of the integer vector A */
char *file_B; /* File which contains the data elements of the integer vector B*/
num_threads = atoi(argv[1]);
num_ops_per_thread = atoi(argv[2]);
vector_size = atoi(argv[3]);
file_A = argv[4];
file_B = argv[5];
size_input = vector_size*sizeof(int);
size_output = vector_size*sizeof(double);
/******************************************************************************/
/************************** Memory Allocation *********************************/
h_A = (int *)malloc(size_input); /* Allocate memory to the vector on the host */
h_B = (int *)malloc(size_input);
h_C = (double *)malloc(size_output);
/************************** Store the integers from the input files ***************************/
readFileData(file_A,vector_size,h_A);
readFileData(file_B,vector_size,h_B);
/******************************************************************************/
ERROR_HANDLER(cudaMalloc((void **)&d_A,size_input));
ERROR_HANDLER(cudaMalloc((void **)&d_B,size_input));
ERROR_HANDLER(cudaMalloc((void **)&d_C,size_output));
/************************* Copy vectors to the host ***************************/
ERROR_HANDLER(cudaMemcpy(d_A, h_A, size_input, cudaMemcpyHostToDevice));
ERROR_HANDLER(cudaMemcpy(d_B, h_B, size_input, cudaMemcpyHostToDevice));
/************************ Add the vectors *************************************/
num_blocks = (vector_size+num_threads*num_ops_per_thread-1)/(num_threads*num_ops_per_thread);
/* The ceiling function for the number of blocks is not applied as the number of threads is exactly equal to the number of data items to work on */
start = clock();
vecAdd<<<num_blocks,num_threads>>>(d_A, d_B, d_C, vector_size, num_ops_per_thread);
ERROR_HANDLER(cudaDeviceSynchronize());
stop = clock();
ERROR_HANDLER(cudaMemcpy(h_C, d_C, size_output, cudaMemcpyDeviceToHost)); /* Copy the result back to the host */
printf("Time for the vector addition : %f (milli-seconds) \n",1000*(stop-start)/(float)CLOCKS_PER_SEC);
/************************* Free Memory ****************************************/
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
free(h_A);
free(h_B);
free(h_C);
} | .file "tmpxft_0006a439_00000000-6_ee16b105_456.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/anantshah200/CS6023/master/Assignment1/ee16b105_456.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%s in %s at line %d\n"
.text
.globl _Z13error_handler9cudaError
.type _Z13error_handler9cudaError, @function
_Z13error_handler9cudaError:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L8
ret
.L8:
subq $8, %rsp
.cfi_def_cfa_offset 16
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $19, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z13error_handler9cudaError, .-_Z13error_handler9cudaError
.section .rodata.str1.1
.LC2:
.string "r+"
.LC3:
.string "%d"
.LC4:
.string "error : File %s not found"
.text
.globl _Z12readFileDataPciPi
.type _Z12readFileDataPciPi, @function
_Z12readFileDataPciPi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movl %esi, %r12d
movq %rdx, %r13
leaq .LC2(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L10
movq %rax, %rbp
testl %r12d, %r12d
jle .L11
movq %r13, %rbx
movslq %r12d, %r12
leaq 0(%r13,%r12,4), %r13
leaq .LC3(%rip), %r12
.L12:
movq %rbx, %rdx
movq %r12, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $4, %rbx
cmpq %r13, %rbx
jne .L12
.L11:
movq %rbp, %rdi
call fclose@PLT
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movq %rbx, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z12readFileDataPciPi, .-_Z12readFileDataPciPi
.globl _Z31__device_stub__Z6vecAddPiS_PdiiPiS_Pdii
.type _Z31__device_stub__Z6vecAddPiS_PdiiPiS_Pdii, @function
_Z31__device_stub__Z6vecAddPiS_PdiiPiS_Pdii:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6vecAddPiS_Pdii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z31__device_stub__Z6vecAddPiS_PdiiPiS_Pdii, .-_Z31__device_stub__Z6vecAddPiS_PdiiPiS_Pdii
.globl _Z6vecAddPiS_Pdii
.type _Z6vecAddPiS_Pdii, @function
_Z6vecAddPiS_Pdii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z6vecAddPiS_PdiiPiS_Pdii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z6vecAddPiS_Pdii, .-_Z6vecAddPiS_Pdii
.section .rodata.str1.8
.align 8
.LC5:
.string "Error : Invalid number of arguments \n"
.align 8
.LC7:
.string "Time for the vector addition : %f (milli-seconds) \n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
cmpl $6, %edi
jne .L29
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 16(%rsp)
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r14
movl %eax, 12(%rsp)
movq 32(%rbx), %rdx
movq %rdx, 24(%rsp)
movq 40(%rbx), %rcx
movq %rcx, 32(%rsp)
movslq %eax, %rbx
leaq 0(,%rbx,4), %rbp
salq $3, %rbx
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbx, %rdi
call malloc@PLT
movq %rax, 40(%rsp)
movq %r13, %rdx
movl 12(%rsp), %esi
movq 24(%rsp), %rdi
call _Z12readFileDataPciPi
movq %r12, %rdx
movl 12(%rsp), %esi
movq 32(%rsp), %rdi
call _Z12readFileDataPciPi
leaq 56(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl %eax, %edi
call _Z13error_handler9cudaError
leaq 64(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl %eax, %edi
call _Z13error_handler9cudaError
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %edi
call _Z13error_handler9cudaError
movl $1, %ecx
movq %rbp, %rdx
movq %r13, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z13error_handler9cudaError
movl $1, %ecx
movq %rbp, %rdx
movq %r12, %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z13error_handler9cudaError
movl 16(%rsp), %ecx
imull %r15d, %ecx
leal -1(%rcx,%r14), %eax
cltd
idivl %ecx
movl %eax, %ebp
call clock@PLT
movq %rax, %r14
movl %r15d, 92(%rsp)
movl $1, 96(%rsp)
movl %ebp, 80(%rsp)
movl $1, 84(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L26:
call cudaDeviceSynchronize@PLT
movl %eax, %edi
call _Z13error_handler9cudaError
call clock@PLT
movq %rax, %rbp
movl $2, %ecx
movq %rbx, %rdx
movq 72(%rsp), %rsi
movq 40(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z13error_handler9cudaError
subq %r14, %rbp
imulq $1000, %rbp, %rbp
pxor %xmm0, %xmm0
cvtsi2ssq %rbp, %xmm0
divss .LC6(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L31
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
leaq .LC5(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L30:
movl 16(%rsp), %r8d
movl 12(%rsp), %ecx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z31__device_stub__Z6vecAddPiS_PdiiPiS_Pdii
jmp .L26
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z6vecAddPiS_Pdii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecAddPiS_Pdii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC6:
.long 1232348160
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* Program : To add two randomly generated vectors with the help of a GPU
* Author : Anant Shah
* Roll Number : EE16B105
* Date : 14-8-2018
**/
#include<stdio.h>
#include<cuda.h>
#include<time.h>
#include<math.h>
#include<stdlib.h>
#define MAX_NUM 10000000 /* Maximum integer upto which random numbers are produced */
#define ERROR_HANDLER(error_msg) error_handler(error_msg)
void error_handler(cudaError_t error_msg){
/* Handles error messages */
if(error_msg != cudaSuccess){
printf("%s in %s at line %d\n",cudaGetErrorString(error_msg),__FILE__,__LINE__);
exit(EXIT_FAILURE);
}
}
__global__ void vecAdd(int *A,int *B,double *C,int vector_size,int num_ops_per_thread) {
/* One of the parameters of this kernel function is the number of operations per thread.
* This code follows the cyclic distribution of elements to each thread.
* eg : num_ops_per_thread = 2.
* Then C[0] and C[vector_size/2] will be calculated by thread with Id = 0.
* C[1] and C[vector_size/2+1] will be calculated by thread with Id = 1 and so on.
*/
int id = blockIdx.x*blockDim.x+threadIdx.x;
/* Since we are performing the cyclic distribution, we need to make sure thread Ids grater than (vector_size/num_ops_per_thread) do not execute as the * y will only repeat the addition performed by another thread. Also, if the size of the vector and number of operations per thread are not perfectly
* , then some threads will have to do some extra operations.
*/
if(id<vector_size/num_ops_per_thread){
for(int i=id;i<vector_size;i+=(vector_size/num_ops_per_thread)){
C[i] = A[i] + B[i];
}
}
}
void readFileData(char *file,int size,int *vector){
/* Function to read the integers from a .txt or .dat file */
FILE *fp;
fp = fopen(file,"r+");
if(fp!=NULL){
for(int i=0;i<size;i++){
fscanf(fp,"%d",(vector+i));
}
fclose(fp);
}
else{
printf("error : File %s not found",file);
exit(EXIT_FAILURE);
}
}
int main(int argc,char **argv) {
if(argc!=6){
printf("Error : Invalid number of arguments \n");
exit(EXIT_FAILURE);
}
/*************************** Variable Declaration ****************************/
int *h_A; /* Vector declared on the host */
int *h_B; /* Vector declared on the host */
double *h_C; /* Vector which will be the sum of previously deined vectors */
int *d_A; /* Vector which will be a copy of <h_A> but on the device(GPU) */
int *d_B; /* Vector which will be a copy of <h_B> but on the device(GPU) */
double *d_C; /* Vector which stores the sum of <d_A> and <d_B> on the device */
size_t size_input; /* Bytes required to store the vectors */
size_t size_output; /* Bytes required to store the output vector */
clock_t start; /* Start time of the program */
clock_t stop; /* Stop time of the program */
int num_ops_per_thread; /* Number of operations per thread */
int num_blocks; /* Number of blocks in the grid */
int num_threads; /* Number of threads per block */
int vector_size; /* Size of the vector(number of data elements) */
char *file_A; /* File which contains the data elements of the integer vector A */
char *file_B; /* File which contains the data elements of the integer vector B*/
num_threads = atoi(argv[1]);
num_ops_per_thread = atoi(argv[2]);
vector_size = atoi(argv[3]);
file_A = argv[4];
file_B = argv[5];
size_input = vector_size*sizeof(int);
size_output = vector_size*sizeof(double);
/******************************************************************************/
/************************** Memory Allocation *********************************/
h_A = (int *)malloc(size_input); /* Allocate memory to the vector on the host */
h_B = (int *)malloc(size_input);
h_C = (double *)malloc(size_output);
/************************** Store the integers from the input files ***************************/
readFileData(file_A,vector_size,h_A);
readFileData(file_B,vector_size,h_B);
/******************************************************************************/
ERROR_HANDLER(cudaMalloc((void **)&d_A,size_input));
ERROR_HANDLER(cudaMalloc((void **)&d_B,size_input));
ERROR_HANDLER(cudaMalloc((void **)&d_C,size_output));
/************************* Copy vectors to the host ***************************/
ERROR_HANDLER(cudaMemcpy(d_A, h_A, size_input, cudaMemcpyHostToDevice));
ERROR_HANDLER(cudaMemcpy(d_B, h_B, size_input, cudaMemcpyHostToDevice));
/************************ Add the vectors *************************************/
num_blocks = (vector_size+num_threads*num_ops_per_thread-1)/(num_threads*num_ops_per_thread);
/* The ceiling function for the number of blocks is not applied as the number of threads is exactly equal to the number of data items to work on */
start = clock();
vecAdd<<<num_blocks,num_threads>>>(d_A, d_B, d_C, vector_size, num_ops_per_thread);
ERROR_HANDLER(cudaDeviceSynchronize());
stop = clock();
ERROR_HANDLER(cudaMemcpy(h_C, d_C, size_output, cudaMemcpyDeviceToHost)); /* Copy the result back to the host */
printf("Time for the vector addition : %f (milli-seconds) \n",1000*(stop-start)/(float)CLOCKS_PER_SEC);
/************************* Free Memory ****************************************/
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
free(h_A);
free(h_B);
free(h_C);
} | /* Program : To add two randomly generated vectors with the help of a GPU
* Author : Anant Shah
* Roll Number : EE16B105
* Date : 14-8-2018
**/
#include<stdio.h>
#include<hip/hip_runtime.h>
#include<time.h>
#include<math.h>
#include<stdlib.h>
#define MAX_NUM 10000000 /* Maximum integer upto which random numbers are produced */
#define ERROR_HANDLER(error_msg) error_handler(error_msg)
void error_handler(hipError_t error_msg){
/* Handles error messages */
if(error_msg != hipSuccess){
printf("%s in %s at line %d\n",hipGetErrorString(error_msg),__FILE__,__LINE__);
exit(EXIT_FAILURE);
}
}
__global__ void vecAdd(int *A,int *B,double *C,int vector_size,int num_ops_per_thread) {
/* One of the parameters of this kernel function is the number of operations per thread.
* This code follows the cyclic distribution of elements to each thread.
* eg : num_ops_per_thread = 2.
* Then C[0] and C[vector_size/2] will be calculated by thread with Id = 0.
* C[1] and C[vector_size/2+1] will be calculated by thread with Id = 1 and so on.
*/
int id = blockIdx.x*blockDim.x+threadIdx.x;
/* Since we are performing the cyclic distribution, we need to make sure thread Ids grater than (vector_size/num_ops_per_thread) do not execute as the * y will only repeat the addition performed by another thread. Also, if the size of the vector and number of operations per thread are not perfectly
* , then some threads will have to do some extra operations.
*/
if(id<vector_size/num_ops_per_thread){
for(int i=id;i<vector_size;i+=(vector_size/num_ops_per_thread)){
C[i] = A[i] + B[i];
}
}
}
void readFileData(char *file,int size,int *vector){
/* Function to read the integers from a .txt or .dat file */
FILE *fp;
fp = fopen(file,"r+");
if(fp!=NULL){
for(int i=0;i<size;i++){
fscanf(fp,"%d",(vector+i));
}
fclose(fp);
}
else{
printf("error : File %s not found",file);
exit(EXIT_FAILURE);
}
}
int main(int argc,char **argv) {
if(argc!=6){
printf("Error : Invalid number of arguments \n");
exit(EXIT_FAILURE);
}
/*************************** Variable Declaration ****************************/
int *h_A; /* Vector declared on the host */
int *h_B; /* Vector declared on the host */
double *h_C; /* Vector which will be the sum of previously deined vectors */
int *d_A; /* Vector which will be a copy of <h_A> but on the device(GPU) */
int *d_B; /* Vector which will be a copy of <h_B> but on the device(GPU) */
double *d_C; /* Vector which stores the sum of <d_A> and <d_B> on the device */
size_t size_input; /* Bytes required to store the vectors */
size_t size_output; /* Bytes required to store the output vector */
clock_t start; /* Start time of the program */
clock_t stop; /* Stop time of the program */
int num_ops_per_thread; /* Number of operations per thread */
int num_blocks; /* Number of blocks in the grid */
int num_threads; /* Number of threads per block */
int vector_size; /* Size of the vector(number of data elements) */
char *file_A; /* File which contains the data elements of the integer vector A */
char *file_B; /* File which contains the data elements of the integer vector B*/
num_threads = atoi(argv[1]);
num_ops_per_thread = atoi(argv[2]);
vector_size = atoi(argv[3]);
file_A = argv[4];
file_B = argv[5];
size_input = vector_size*sizeof(int);
size_output = vector_size*sizeof(double);
/******************************************************************************/
/************************** Memory Allocation *********************************/
h_A = (int *)malloc(size_input); /* Allocate memory to the vector on the host */
h_B = (int *)malloc(size_input);
h_C = (double *)malloc(size_output);
/************************** Store the integers from the input files ***************************/
readFileData(file_A,vector_size,h_A);
readFileData(file_B,vector_size,h_B);
/******************************************************************************/
ERROR_HANDLER(hipMalloc((void **)&d_A,size_input));
ERROR_HANDLER(hipMalloc((void **)&d_B,size_input));
ERROR_HANDLER(hipMalloc((void **)&d_C,size_output));
/************************* Copy vectors to the host ***************************/
ERROR_HANDLER(hipMemcpy(d_A, h_A, size_input, hipMemcpyHostToDevice));
ERROR_HANDLER(hipMemcpy(d_B, h_B, size_input, hipMemcpyHostToDevice));
/************************ Add the vectors *************************************/
num_blocks = (vector_size+num_threads*num_ops_per_thread-1)/(num_threads*num_ops_per_thread);
/* The ceiling function for the number of blocks is not applied as the number of threads is exactly equal to the number of data items to work on */
start = clock();
vecAdd<<<num_blocks,num_threads>>>(d_A, d_B, d_C, vector_size, num_ops_per_thread);
ERROR_HANDLER(hipDeviceSynchronize());
stop = clock();
ERROR_HANDLER(hipMemcpy(h_C, d_C, size_output, hipMemcpyDeviceToHost)); /* Copy the result back to the host */
printf("Time for the vector addition : %f (milli-seconds) \n",1000*(stop-start)/(float)CLOCKS_PER_SEC);
/************************* Free Memory ****************************************/
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
free(h_A);
free(h_B);
free(h_C);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /* Program : To add two randomly generated vectors with the help of a GPU
* Author : Anant Shah
* Roll Number : EE16B105
* Date : 14-8-2018
**/
#include<stdio.h>
#include<hip/hip_runtime.h>
#include<time.h>
#include<math.h>
#include<stdlib.h>
#define MAX_NUM 10000000 /* Maximum integer upto which random numbers are produced */
#define ERROR_HANDLER(error_msg) error_handler(error_msg)
void error_handler(hipError_t error_msg){
/* Handles error messages */
if(error_msg != hipSuccess){
printf("%s in %s at line %d\n",hipGetErrorString(error_msg),__FILE__,__LINE__);
exit(EXIT_FAILURE);
}
}
__global__ void vecAdd(int *A,int *B,double *C,int vector_size,int num_ops_per_thread) {
/* One of the parameters of this kernel function is the number of operations per thread.
* This code follows the cyclic distribution of elements to each thread.
* eg : num_ops_per_thread = 2.
* Then C[0] and C[vector_size/2] will be calculated by thread with Id = 0.
* C[1] and C[vector_size/2+1] will be calculated by thread with Id = 1 and so on.
*/
int id = blockIdx.x*blockDim.x+threadIdx.x;
/* Since we are performing the cyclic distribution, we need to make sure thread Ids grater than (vector_size/num_ops_per_thread) do not execute as the * y will only repeat the addition performed by another thread. Also, if the size of the vector and number of operations per thread are not perfectly
* , then some threads will have to do some extra operations.
*/
if(id<vector_size/num_ops_per_thread){
for(int i=id;i<vector_size;i+=(vector_size/num_ops_per_thread)){
C[i] = A[i] + B[i];
}
}
}
void readFileData(char *file,int size,int *vector){
/* Function to read the integers from a .txt or .dat file */
FILE *fp;
fp = fopen(file,"r+");
if(fp!=NULL){
for(int i=0;i<size;i++){
fscanf(fp,"%d",(vector+i));
}
fclose(fp);
}
else{
printf("error : File %s not found",file);
exit(EXIT_FAILURE);
}
}
int main(int argc,char **argv) {
if(argc!=6){
printf("Error : Invalid number of arguments \n");
exit(EXIT_FAILURE);
}
/*************************** Variable Declaration ****************************/
int *h_A; /* Vector declared on the host */
int *h_B; /* Vector declared on the host */
double *h_C; /* Vector which will be the sum of previously deined vectors */
int *d_A; /* Vector which will be a copy of <h_A> but on the device(GPU) */
int *d_B; /* Vector which will be a copy of <h_B> but on the device(GPU) */
double *d_C; /* Vector which stores the sum of <d_A> and <d_B> on the device */
size_t size_input; /* Bytes required to store the vectors */
size_t size_output; /* Bytes required to store the output vector */
clock_t start; /* Start time of the program */
clock_t stop; /* Stop time of the program */
int num_ops_per_thread; /* Number of operations per thread */
int num_blocks; /* Number of blocks in the grid */
int num_threads; /* Number of threads per block */
int vector_size; /* Size of the vector(number of data elements) */
char *file_A; /* File which contains the data elements of the integer vector A */
char *file_B; /* File which contains the data elements of the integer vector B*/
num_threads = atoi(argv[1]);
num_ops_per_thread = atoi(argv[2]);
vector_size = atoi(argv[3]);
file_A = argv[4];
file_B = argv[5];
size_input = vector_size*sizeof(int);
size_output = vector_size*sizeof(double);
/******************************************************************************/
/************************** Memory Allocation *********************************/
h_A = (int *)malloc(size_input); /* Allocate memory to the vector on the host */
h_B = (int *)malloc(size_input);
h_C = (double *)malloc(size_output);
/************************** Store the integers from the input files ***************************/
readFileData(file_A,vector_size,h_A);
readFileData(file_B,vector_size,h_B);
/******************************************************************************/
ERROR_HANDLER(hipMalloc((void **)&d_A,size_input));
ERROR_HANDLER(hipMalloc((void **)&d_B,size_input));
ERROR_HANDLER(hipMalloc((void **)&d_C,size_output));
/************************* Copy vectors to the host ***************************/
ERROR_HANDLER(hipMemcpy(d_A, h_A, size_input, hipMemcpyHostToDevice));
ERROR_HANDLER(hipMemcpy(d_B, h_B, size_input, hipMemcpyHostToDevice));
/************************ Add the vectors *************************************/
num_blocks = (vector_size+num_threads*num_ops_per_thread-1)/(num_threads*num_ops_per_thread);
/* The ceiling function for the number of blocks is not applied as the number of threads is exactly equal to the number of data items to work on */
start = clock();
vecAdd<<<num_blocks,num_threads>>>(d_A, d_B, d_C, vector_size, num_ops_per_thread);
ERROR_HANDLER(hipDeviceSynchronize());
stop = clock();
ERROR_HANDLER(hipMemcpy(h_C, d_C, size_output, hipMemcpyDeviceToHost)); /* Copy the result back to the host */
printf("Time for the vector addition : %f (milli-seconds) \n",1000*(stop-start)/(float)CLOCKS_PER_SEC);
/************************* Free Memory ****************************************/
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
free(h_A);
free(h_B);
free(h_C);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecAddPiS_Pdii
.globl _Z6vecAddPiS_Pdii
.p2align 8
.type _Z6vecAddPiS_Pdii,@function
_Z6vecAddPiS_Pdii:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b32 s4, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_ashr_i32 s5, s3, 31
s_ashr_i32 s8, s2, 31
s_add_i32 s3, s3, s5
s_add_i32 s9, s2, s8
s_xor_b32 s3, s3, s5
s_xor_b32 s9, s9, s8
v_cvt_f32_u32_e32 v1, s3
s_sub_i32 s7, 0, s3
s_and_b32 s4, s4, 0xffff
s_xor_b32 s5, s8, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_readfirstlane_b32 s6, v1
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_mul_i32 s7, s7, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s7, s6, s7
s_add_i32 s6, s6, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s6, s9, s6
s_mul_i32 s7, s6, s3
s_add_i32 s8, s6, 1
s_sub_i32 s7, s9, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s9, s7, s3
s_cmp_ge_u32 s7, s3
s_cselect_b32 s6, s8, s6
s_cselect_b32 s7, s9, s7
s_add_i32 s8, s6, 1
s_cmp_ge_u32 s7, s3
s_cselect_b32 s3, s8, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s3, s3, s5
s_sub_i32 s8, s3, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_min_i32 s3, s8, s2
v_cmp_gt_i32_e32 vcc_lo, s3, v1
s_mov_b32 s3, 0
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_3
s_clause 0x1
s_load_b64 s[10:11], s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_lshl_b64 s[12:13], s[8:9], 3
v_lshlrev_b64 v[4:5], 3, v[1:2]
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s10, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
s_lshl_b64 s[10:11], s[8:9], 2
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v8, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v3, vcc_lo
v_add_nc_u32_e32 v1, s8, v1
global_load_b32 v0, v[6:7], off
global_load_b32 v6, v[8:9], off
v_add_co_u32 v2, vcc_lo, v2, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s2, v1
s_or_b32 s3, vcc_lo, s3
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v6, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cvt_f64_i32_e32 v[6:7], v0
global_store_b64 v[4:5], v[6:7], off
v_add_co_u32 v4, s0, v4, s12
v_add_co_ci_u32_e64 v5, s0, s13, v5, s0
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecAddPiS_Pdii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecAddPiS_Pdii, .Lfunc_end0-_Z6vecAddPiS_Pdii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecAddPiS_Pdii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6vecAddPiS_Pdii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* Program : To add two randomly generated vectors with the help of a GPU
* Author : Anant Shah
* Roll Number : EE16B105
* Date : 14-8-2018
**/
#include<stdio.h>
#include<hip/hip_runtime.h>
#include<time.h>
#include<math.h>
#include<stdlib.h>
#define MAX_NUM 10000000 /* Maximum integer upto which random numbers are produced */
#define ERROR_HANDLER(error_msg) error_handler(error_msg)
void error_handler(hipError_t error_msg){
/* Handles error messages */
if(error_msg != hipSuccess){
printf("%s in %s at line %d\n",hipGetErrorString(error_msg),__FILE__,__LINE__);
exit(EXIT_FAILURE);
}
}
__global__ void vecAdd(int *A,int *B,double *C,int vector_size,int num_ops_per_thread) {
/* One of the parameters of this kernel function is the number of operations per thread.
* This code follows the cyclic distribution of elements to each thread.
* eg : num_ops_per_thread = 2.
* Then C[0] and C[vector_size/2] will be calculated by thread with Id = 0.
* C[1] and C[vector_size/2+1] will be calculated by thread with Id = 1 and so on.
*/
int id = blockIdx.x*blockDim.x+threadIdx.x;
/* Since we are performing the cyclic distribution, we need to make sure thread Ids grater than (vector_size/num_ops_per_thread) do not execute as the * y will only repeat the addition performed by another thread. Also, if the size of the vector and number of operations per thread are not perfectly
* , then some threads will have to do some extra operations.
*/
if(id<vector_size/num_ops_per_thread){
for(int i=id;i<vector_size;i+=(vector_size/num_ops_per_thread)){
C[i] = A[i] + B[i];
}
}
}
void readFileData(char *file,int size,int *vector){
/* Function to read the integers from a .txt or .dat file */
FILE *fp;
fp = fopen(file,"r+");
if(fp!=NULL){
for(int i=0;i<size;i++){
fscanf(fp,"%d",(vector+i));
}
fclose(fp);
}
else{
printf("error : File %s not found",file);
exit(EXIT_FAILURE);
}
}
int main(int argc,char **argv) {
if(argc!=6){
printf("Error : Invalid number of arguments \n");
exit(EXIT_FAILURE);
}
/*************************** Variable Declaration ****************************/
int *h_A; /* Vector declared on the host */
int *h_B; /* Vector declared on the host */
double *h_C; /* Vector which will be the sum of previously deined vectors */
int *d_A; /* Vector which will be a copy of <h_A> but on the device(GPU) */
int *d_B; /* Vector which will be a copy of <h_B> but on the device(GPU) */
double *d_C; /* Vector which stores the sum of <d_A> and <d_B> on the device */
size_t size_input; /* Bytes required to store the vectors */
size_t size_output; /* Bytes required to store the output vector */
clock_t start; /* Start time of the program */
clock_t stop; /* Stop time of the program */
int num_ops_per_thread; /* Number of operations per thread */
int num_blocks; /* Number of blocks in the grid */
int num_threads; /* Number of threads per block */
int vector_size; /* Size of the vector(number of data elements) */
char *file_A; /* File which contains the data elements of the integer vector A */
char *file_B; /* File which contains the data elements of the integer vector B*/
num_threads = atoi(argv[1]);
num_ops_per_thread = atoi(argv[2]);
vector_size = atoi(argv[3]);
file_A = argv[4];
file_B = argv[5];
size_input = vector_size*sizeof(int);
size_output = vector_size*sizeof(double);
/******************************************************************************/
/************************** Memory Allocation *********************************/
h_A = (int *)malloc(size_input); /* Allocate memory to the vector on the host */
h_B = (int *)malloc(size_input);
h_C = (double *)malloc(size_output);
/************************** Store the integers from the input files ***************************/
readFileData(file_A,vector_size,h_A);
readFileData(file_B,vector_size,h_B);
/******************************************************************************/
ERROR_HANDLER(hipMalloc((void **)&d_A,size_input));
ERROR_HANDLER(hipMalloc((void **)&d_B,size_input));
ERROR_HANDLER(hipMalloc((void **)&d_C,size_output));
/************************* Copy vectors to the host ***************************/
ERROR_HANDLER(hipMemcpy(d_A, h_A, size_input, hipMemcpyHostToDevice));
ERROR_HANDLER(hipMemcpy(d_B, h_B, size_input, hipMemcpyHostToDevice));
/************************ Add the vectors *************************************/
num_blocks = (vector_size+num_threads*num_ops_per_thread-1)/(num_threads*num_ops_per_thread);
/* The ceiling function for the number of blocks is not applied as the number of threads is exactly equal to the number of data items to work on */
start = clock();
vecAdd<<<num_blocks,num_threads>>>(d_A, d_B, d_C, vector_size, num_ops_per_thread);
ERROR_HANDLER(hipDeviceSynchronize());
stop = clock();
ERROR_HANDLER(hipMemcpy(h_C, d_C, size_output, hipMemcpyDeviceToHost)); /* Copy the result back to the host */
printf("Time for the vector addition : %f (milli-seconds) \n",1000*(stop-start)/(float)CLOCKS_PER_SEC);
/************************* Free Memory ****************************************/
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
free(h_A);
free(h_B);
free(h_C);
} | .text
.file "ee16b105_456.hip"
.globl _Z13error_handler10hipError_t # -- Begin function _Z13error_handler10hipError_t
.p2align 4, 0x90
.type _Z13error_handler10hipError_t,@function
_Z13error_handler10hipError_t: # @_Z13error_handler10hipError_t
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB0_2
# %bb.1:
retq
.LBB0_2:
pushq %rax
.cfi_def_cfa_offset 16
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $19, %ecx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z13error_handler10hipError_t, .Lfunc_end0-_Z13error_handler10hipError_t
.cfi_endproc
# -- End function
.globl _Z21__device_stub__vecAddPiS_Pdii # -- Begin function _Z21__device_stub__vecAddPiS_Pdii
.p2align 4, 0x90
.type _Z21__device_stub__vecAddPiS_Pdii,@function
_Z21__device_stub__vecAddPiS_Pdii: # @_Z21__device_stub__vecAddPiS_Pdii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecAddPiS_Pdii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z21__device_stub__vecAddPiS_Pdii, .Lfunc_end1-_Z21__device_stub__vecAddPiS_Pdii
.cfi_endproc
# -- End function
.globl _Z12readFileDataPciPi # -- Begin function _Z12readFileDataPciPi
.p2align 4, 0x90
.type _Z12readFileDataPciPi,@function
_Z12readFileDataPciPi: # @_Z12readFileDataPciPi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %rbx
movl %esi, %ebp
movq %rdi, %r15
movl $.L.str.2, %esi
callq fopen
testq %rax, %rax
je .LBB2_5
# %bb.1: # %.preheader
movq %rax, %r14
testl %ebp, %ebp
jle .LBB2_4
# %bb.2: # %.lr.ph.preheader
movl %ebp, %r15d
.p2align 4, 0x90
.LBB2_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.3, %esi
movq %r14, %rdi
movq %rbx, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
addq $4, %rbx
decq %r15
jne .LBB2_3
.LBB2_4: # %._crit_edge
movq %r14, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.LBB2_5:
.cfi_def_cfa_offset 48
movl $.L.str.4, %edi
movq %r15, %rsi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end2:
.size _Z12readFileDataPciPi, .Lfunc_end2-_Z12readFileDataPciPi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI3_0:
.long 0x49742400 # float 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $6, %edi
jne .LBB3_23
# %bb.1:
movq %rsi, %rbx
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 64(%rsp) # 8-byte Spill
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 72(%rsp) # 8-byte Spill
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
movq 32(%rbx), %r15
movq 40(%rbx), %rax
movq %rax, 80(%rsp) # 8-byte Spill
movq %r13, %rbp
shlq $32, %rbp
movq %rbp, %r12
sarq $30, %r12
sarq $29, %rbp
movq %r12, %rdi
callq malloc
movq %rax, 16(%rsp) # 8-byte Spill
movq %r12, %rdi
callq malloc
movq %rax, 8(%rsp) # 8-byte Spill
movq %rbp, %rdi
callq malloc
movq %rax, 56(%rsp) # 8-byte Spill
movl $.L.str.2, %esi
movq %r15, %rdi
callq fopen
testq %rax, %rax
je .LBB3_11
# %bb.2: # %.preheader.i
movq %rax, %r14
testl %r13d, %r13d
jle .LBB3_5
# %bb.3: # %.lr.ph.preheader.i
movl %r13d, %ebx
movq 16(%rsp), %r15 # 8-byte Reload
.p2align 4, 0x90
.LBB3_4: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl $.L.str.3, %esi
movq %r14, %rdi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
addq $4, %r15
decq %rbx
jne .LBB3_4
.LBB3_5: # %_Z12readFileDataPciPi.exit
movq %r14, %rdi
callq fclose
movl $.L.str.2, %esi
movq 80(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
callq fopen
testq %rax, %rax
je .LBB3_13
# %bb.6: # %.preheader.i44
movq %rax, %r14
testl %r13d, %r13d
jle .LBB3_9
# %bb.7: # %.lr.ph.preheader.i45
movl %r13d, %r15d
movq 8(%rsp), %rbx # 8-byte Reload
.p2align 4, 0x90
.LBB3_8: # %.lr.ph.i47
# =>This Inner Loop Header: Depth=1
movl $.L.str.3, %esi
movq %r14, %rdi
movq %rbx, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
addq $4, %rbx
decq %r15
jne .LBB3_8
.LBB3_9: # %_Z12readFileDataPciPi.exit51
movq %r14, %rdi
callq fclose
leaq 40(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB3_10
# %bb.14: # %_Z13error_handler10hipError_t.exit
leaq 32(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
movq 16(%rsp), %r15 # 8-byte Reload
movq 8(%rsp), %r14 # 8-byte Reload
movq 72(%rsp), %rbx # 8-byte Reload
jne .LBB3_10
# %bb.15: # %_Z13error_handler10hipError_t.exit54
leaq 24(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB3_10
# %bb.16: # %_Z13error_handler10hipError_t.exit56
movq 40(%rsp), %rdi
movq %r15, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_10
# %bb.17: # %_Z13error_handler10hipError_t.exit58
movq 32(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_10
# %bb.18: # %_Z13error_handler10hipError_t.exit60
movq 64(%rsp), %r14 # 8-byte Reload
movl %r14d, %ecx
imull %ebx, %ecx
leal (%rcx,%r13), %eax
decl %eax
cltd
idivl %ecx
movq %rbx, %r15
movl %eax, %ebx
callq clock
movq %rax, %r12
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rbx
movl %r14d, %edx
orq %rax, %rdx
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_20
# %bb.19:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
movl %r13d, 52(%rsp)
movl %r15d, 48(%rsp)
leaq 152(%rsp), %rax
movq %rax, 160(%rsp)
leaq 144(%rsp), %rax
movq %rax, 168(%rsp)
leaq 136(%rsp), %rax
movq %rax, 176(%rsp)
leaq 52(%rsp), %rax
movq %rax, 184(%rsp)
leaq 48(%rsp), %rax
movq %rax, 192(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z6vecAddPiS_Pdii, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_20:
callq hipDeviceSynchronize
testl %eax, %eax
movq 16(%rsp), %r15 # 8-byte Reload
jne .LBB3_10
# %bb.21: # %_Z13error_handler10hipError_t.exit62
callq clock
movq %rax, %rbx
movq 24(%rsp), %rsi
movq 56(%rsp), %r13 # 8-byte Reload
movq %r13, %rdi
movq %rbp, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
movq 8(%rsp), %r14 # 8-byte Reload
jne .LBB3_10
# %bb.22: # %_Z13error_handler10hipError_t.exit64
subq %r12, %rbx
imulq $1000, %rbx, %rax # imm = 0x3E8
cvtsi2ss %rax, %xmm0
divss .LCPI3_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq %r15, %rdi
callq free
movq %r14, %rdi
callq free
movq %r13, %rdi
callq free
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_10:
.cfi_def_cfa_offset 256
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $19, %ecx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.LBB3_23:
movl $.Lstr, %edi
callq puts@PLT
movl $1, %edi
callq exit
.LBB3_11:
movl $.L.str.4, %edi
movq %r15, %rsi
jmp .LBB3_12
.LBB3_13:
movl $.L.str.4, %edi
movq %rbx, %rsi
.LBB3_12:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecAddPiS_Pdii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%s in %s at line %d\n"
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/anantshah200/CS6023/master/Assignment1/ee16b105_456.hip"
.size .L.str.1, 113
.type _Z6vecAddPiS_Pdii,@object # @_Z6vecAddPiS_Pdii
.section .rodata,"a",@progbits
.globl _Z6vecAddPiS_Pdii
.p2align 3, 0x0
_Z6vecAddPiS_Pdii:
.quad _Z21__device_stub__vecAddPiS_Pdii
.size _Z6vecAddPiS_Pdii, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "r+"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "error : File %s not found"
.size .L.str.4, 26
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Time for the vector addition : %f (milli-seconds) \n"
.size .L.str.6, 53
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6vecAddPiS_Pdii"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Error : Invalid number of arguments "
.size .Lstr, 37
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecAddPiS_Pdii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6vecAddPiS_Pdii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6vecAddPiS_Pdii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R4, c[0x0][0x17c] ; /* 0x00005f0000047a13 */
/* 0x000fe20000000000 */
/*0020*/ ULDC.64 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IABS R6, c[0x0][0x178] ; /* 0x00005e0000067a13 */
/* 0x000fe20000000000 */
/*0040*/ ULOP3.LUT UR4, UR4, UR5, URZ, 0x3c, !UPT ; /* 0x0000000504047292 */
/* 0x000fe2000f8e3c3f */
/*0050*/ I2F.RP R0, R4 ; /* 0x0000000400007306 */
/* 0x000e2a0000209400 */
/*0060*/ ISETP.LE.AND P2, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fc6000bf43270 */
/*0070*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*0080*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fcc0007ffe0ff */
/*0090*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe200078e00ff */
/*00b0*/ IADD3 R5, RZ, -R3, RZ ; /* 0x80000003ff057210 */
/* 0x002fca0007ffe0ff */
/*00c0*/ IMAD R5, R5, R4, RZ ; /* 0x0000000405057224 */
/* 0x000fc800078e02ff */
/*00d0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fe200078e0002 */
/*00e0*/ MOV R5, R6 ; /* 0x0000000600057202 */
/* 0x000fe20000000f00 */
/*00f0*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0100*/ IMAD.HI.U32 R0, R3, R5, RZ ; /* 0x0000000503007227 */
/* 0x000fc800078e00ff */
/*0110*/ IMAD.MOV R3, RZ, RZ, -R0 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a00 */
/*0120*/ IMAD R3, R4.reuse, R3, R5 ; /* 0x0000000304037224 */
/* 0x040fe400078e0205 */
/*0130*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e260000002100 */
/*0140*/ ISETP.GT.U32.AND P1, PT, R4, R3, PT ; /* 0x000000030400720c */
/* 0x000fda0003f24070 */
/*0150*/ @!P1 IADD3 R3, R3, -R4.reuse, RZ ; /* 0x8000000403039210 */
/* 0x080fe40007ffe0ff */
/*0160*/ @!P1 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100009810 */
/* 0x000fe40007ffe0ff */
/*0170*/ ISETP.GE.U32.AND P0, PT, R3, R4, PT ; /* 0x000000040300720c */
/* 0x000fe40003f06070 */
/*0180*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fe20003f25270 */
/*0190*/ IMAD R3, R2, c[0x0][0x0], R5 ; /* 0x0000000002037a24 */
/* 0x001fd400078e0205 */
/*01a0*/ @P0 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100000810 */
/* 0x000fe40007ffe0ff */
/*01b0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fc60003f06270 */
/*01c0*/ @!P2 IMAD.MOV R0, RZ, RZ, -R0 ; /* 0x000000ffff00a224 */
/* 0x000fe200078e0a00 */
/*01d0*/ @!P1 LOP3.LUT R0, RZ, c[0x0][0x17c], RZ, 0x33, !PT ; /* 0x00005f00ff009a12 */
/* 0x000fc800078e33ff */
/*01e0*/ ISETP.GE.OR P0, PT, R3, R0, P0 ; /* 0x000000000300720c */
/* 0x000fda0000706670 */
/*01f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0200*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000209000 */
/*0210*/ IADD3 R7, RZ, -R0, RZ ; /* 0x80000000ff077210 */
/* 0x000fe20007ffe0ff */
/*0220*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0230*/ LOP3.LUT R2, RZ, R3, RZ, 0x33, !PT ; /* 0x00000003ff027212 */
/* 0x000fe200078e33ff */
/*0240*/ BSSY B0, 0x4c0 ; /* 0x0000027000007945 */
/* 0x000fe20003800000 */
/*0250*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc60003f45070 */
/*0260*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0270*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0280*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0290*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*02a0*/ IMAD R7, R7, R5, RZ ; /* 0x0000000507077224 */
/* 0x002fc800078e02ff */
/*02b0*/ IMAD.HI.U32 R8, R5, R7, R4 ; /* 0x0000000705087227 */
/* 0x000fe200078e0004 */
/*02c0*/ IADD3 R5, R2, c[0x0][0x178], RZ ; /* 0x00005e0002057a10 */
/* 0x000fca0007ffe0ff */
/*02d0*/ IMAD.HI.U32 R8, R8, R5, RZ ; /* 0x0000000508087227 */
/* 0x000fca00078e00ff */
/*02e0*/ IADD3 R2, -R8, RZ, RZ ; /* 0x000000ff08027210 */
/* 0x000fca0007ffe1ff */
/*02f0*/ IMAD R5, R0, R2, R5 ; /* 0x0000000200057224 */
/* 0x000fca00078e0205 */
/*0300*/ ISETP.GE.U32.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f06070 */
/*0310*/ @P0 IMAD.IADD R5, R5, 0x1, -R0 ; /* 0x0000000105050824 */
/* 0x000fe200078e0a00 */
/*0320*/ @P0 IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108080810 */
/* 0x000fc80007ffe0ff */
/*0330*/ ISETP.GE.U32.AND P1, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f26070 */
/*0340*/ @P1 IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108081810 */
/* 0x000fe40007ffe0ff */
/*0350*/ @!P2 LOP3.LUT R8, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff08a212 */
/* 0x000fc800078e33ff */
/*0360*/ IADD3 R2, R8.reuse, 0x1, RZ ; /* 0x0000000108027810 */
/* 0x040fe40007ffe0ff */
/*0370*/ ISETP.GE.U32.AND P1, PT, R8, 0x3, PT ; /* 0x000000030800780c */
/* 0x000fe40003f26070 */
/*0380*/ LOP3.LUT P0, R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fda000780c0ff */
/*0390*/ @!P0 BRA 0x4b0 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*03a0*/ HFMA2.MMA R4, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff047435 */
/* 0x000fe200000001ff */
/*03b0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fc800078e00ff */
/*03c0*/ IMAD.WIDE R6, R3, R8, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fc800078e0208 */
/*03d0*/ IMAD.WIDE R8, R3, R8, c[0x0][0x160] ; /* 0x0000580003087625 */
/* 0x000fc800078e0208 */
/*03e0*/ IMAD.WIDE R4, R3, R4, c[0x0][0x170] ; /* 0x00005c0003047625 */
/* 0x000fc800078e0204 */
/*03f0*/ LDG.E R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x0000a8000c1e1900 */
/*0400*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0002a2000c1e1900 */
/*0410*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe20007ffe0ff */
/*0420*/ IMAD.IADD R3, R0, 0x1, R3 ; /* 0x0000000100037824 */
/* 0x000fc600078e0203 */
/*0430*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*0440*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x001fc800078e0206 */
/*0450*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x002fe200078e0208 */
/*0460*/ IADD3 R10, R10, R11, RZ ; /* 0x0000000b0a0a7210 */
/* 0x004fcc0007ffe0ff */
/*0470*/ I2F.F64 R10, R10 ; /* 0x0000000a000a7312 */
/* 0x000e240000201c00 */
/*0480*/ STG.E.64 [R4.64], R10 ; /* 0x0000000a04007986 */
/* 0x0011e4000c101b04 */
/*0490*/ IMAD.WIDE R4, R0, 0x8, R4 ; /* 0x0000000800047825 */
/* 0x001fe200078e0204 */
/*04a0*/ @P0 BRA 0x3f0 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*04b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04c0*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*04d0*/ MOV R4, 0x4 ; /* 0x0000000400047802 */
/* 0x001fca0000000f00 */
/*04e0*/ IMAD.WIDE R6, R3, R4, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fc800078e0204 */
/*04f0*/ IMAD.WIDE R4, R3, R4, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fe200078e0204 */
/*0500*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea8000c1e1900 */
/*0510*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea2000c1e1900 */
/*0520*/ HFMA2.MMA R10, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff0a7435 */
/* 0x000fe200000001ff */
/*0530*/ IMAD.WIDE R14, R0, 0x4, R6 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0206 */
/*0540*/ IMAD.WIDE R12, R0, 0x4, R4 ; /* 0x00000004000c7825 */
/* 0x000fca00078e0204 */
/*0550*/ IMAD.WIDE R10, R3, R10, c[0x0][0x170] ; /* 0x00005c00030a7625 */
/* 0x000fc800078e020a */
/*0560*/ IMAD.IADD R9, R2, 0x1, R9 ; /* 0x0000000102097824 */
/* 0x004fcc00078e0209 */
/*0570*/ I2F.F64 R8, R9 ; /* 0x0000000900087312 */
/* 0x000e240000201c00 */
/*0580*/ STG.E.64 [R10.64], R8 ; /* 0x000000080a007986 */
/* 0x0011e8000c101b04 */
/*0590*/ LDG.E R2, [R14.64] ; /* 0x000000040e027981 */
/* 0x000ea8000c1e1900 */
/*05a0*/ LDG.E R17, [R12.64] ; /* 0x000000040c117981 */
/* 0x000ea2000c1e1900 */
/*05b0*/ IMAD.WIDE R6, R0, 0x8, R10 ; /* 0x0000000800067825 */
/* 0x000fc800078e020a */
/*05c0*/ IMAD.WIDE R18, R0, 0x4, R14 ; /* 0x0000000400127825 */
/* 0x000fc800078e020e */
/*05d0*/ IMAD.IADD R2, R2, 0x1, R17 ; /* 0x0000000102027824 */
/* 0x004fe400078e0211 */
/*05e0*/ IMAD.WIDE R16, R0.reuse, 0x4, R12 ; /* 0x0000000400107825 */
/* 0x040fe400078e020c */
/*05f0*/ I2F.F64 R4, R2 ; /* 0x0000000200047312 */
/* 0x000e640000201c00 */
/*0600*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */
/* 0x0023e8000c101b04 */
/*0610*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000ea8000c1e1900 */
/*0620*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x000ea2000c1e1900 */
/*0630*/ IMAD.WIDE R10, R0, 0x8, R6 ; /* 0x00000008000a7825 */
/* 0x001fc800078e0206 */
/*0640*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0212 */
/*0650*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fe200078e0210 */
/*0660*/ IADD3 R8, R20, R21, RZ ; /* 0x0000001514087210 */
/* 0x004fcc0007ffe0ff */
/*0670*/ I2F.F64 R8, R8 ; /* 0x0000000800087312 */
/* 0x000e240000201c00 */
/*0680*/ STG.E.64 [R10.64], R8 ; /* 0x000000080a007986 */
/* 0x0011e8000c101b04 */
/*0690*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea8000c1e1900 */
/*06a0*/ LDG.E R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000ea2000c1e1900 */
/*06b0*/ IMAD.WIDE R6, R0.reuse, 0x8, R10 ; /* 0x0000000800067825 */
/* 0x042fe200078e020a */
/*06c0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*06d0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*06e0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe20003f06270 */
/*06f0*/ IMAD.IADD R4, R14, 0x1, R13 ; /* 0x000000010e047824 */
/* 0x004fcc00078e020d */
/*0700*/ I2F.F64 R4, R4 ; /* 0x0000000400047312 */
/* 0x000e640000201c00 */
/*0710*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */
/* 0x0021e8000c101b04 */
/*0720*/ @!P0 BRA 0x4d0 ; /* 0xfffffda000008947 */
/* 0x000fea000383ffff */
/*0730*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0740*/ BRA 0x740; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecAddPiS_Pdii
.globl _Z6vecAddPiS_Pdii
.p2align 8
.type _Z6vecAddPiS_Pdii,@function
_Z6vecAddPiS_Pdii:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b32 s4, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_ashr_i32 s5, s3, 31
s_ashr_i32 s8, s2, 31
s_add_i32 s3, s3, s5
s_add_i32 s9, s2, s8
s_xor_b32 s3, s3, s5
s_xor_b32 s9, s9, s8
v_cvt_f32_u32_e32 v1, s3
s_sub_i32 s7, 0, s3
s_and_b32 s4, s4, 0xffff
s_xor_b32 s5, s8, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_readfirstlane_b32 s6, v1
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_mul_i32 s7, s7, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s7, s6, s7
s_add_i32 s6, s6, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s6, s9, s6
s_mul_i32 s7, s6, s3
s_add_i32 s8, s6, 1
s_sub_i32 s7, s9, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s9, s7, s3
s_cmp_ge_u32 s7, s3
s_cselect_b32 s6, s8, s6
s_cselect_b32 s7, s9, s7
s_add_i32 s8, s6, 1
s_cmp_ge_u32 s7, s3
s_cselect_b32 s3, s8, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s3, s3, s5
s_sub_i32 s8, s3, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_min_i32 s3, s8, s2
v_cmp_gt_i32_e32 vcc_lo, s3, v1
s_mov_b32 s3, 0
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_3
s_clause 0x1
s_load_b64 s[10:11], s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_lshl_b64 s[12:13], s[8:9], 3
v_lshlrev_b64 v[4:5], 3, v[1:2]
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s10, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
s_lshl_b64 s[10:11], s[8:9], 2
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v8, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v3, vcc_lo
v_add_nc_u32_e32 v1, s8, v1
global_load_b32 v0, v[6:7], off
global_load_b32 v6, v[8:9], off
v_add_co_u32 v2, vcc_lo, v2, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s2, v1
s_or_b32 s3, vcc_lo, s3
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v6, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cvt_f64_i32_e32 v[6:7], v0
global_store_b64 v[4:5], v[6:7], off
v_add_co_u32 v4, s0, v4, s12
v_add_co_ci_u32_e64 v5, s0, s13, v5, s0
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecAddPiS_Pdii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecAddPiS_Pdii, .Lfunc_end0-_Z6vecAddPiS_Pdii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecAddPiS_Pdii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6vecAddPiS_Pdii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0006a439_00000000-6_ee16b105_456.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/anantshah200/CS6023/master/Assignment1/ee16b105_456.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%s in %s at line %d\n"
.text
.globl _Z13error_handler9cudaError
.type _Z13error_handler9cudaError, @function
_Z13error_handler9cudaError:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L8
ret
.L8:
subq $8, %rsp
.cfi_def_cfa_offset 16
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $19, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z13error_handler9cudaError, .-_Z13error_handler9cudaError
.section .rodata.str1.1
.LC2:
.string "r+"
.LC3:
.string "%d"
.LC4:
.string "error : File %s not found"
.text
.globl _Z12readFileDataPciPi
.type _Z12readFileDataPciPi, @function
_Z12readFileDataPciPi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movl %esi, %r12d
movq %rdx, %r13
leaq .LC2(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L10
movq %rax, %rbp
testl %r12d, %r12d
jle .L11
movq %r13, %rbx
movslq %r12d, %r12
leaq 0(%r13,%r12,4), %r13
leaq .LC3(%rip), %r12
.L12:
movq %rbx, %rdx
movq %r12, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $4, %rbx
cmpq %r13, %rbx
jne .L12
.L11:
movq %rbp, %rdi
call fclose@PLT
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movq %rbx, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z12readFileDataPciPi, .-_Z12readFileDataPciPi
.globl _Z31__device_stub__Z6vecAddPiS_PdiiPiS_Pdii
.type _Z31__device_stub__Z6vecAddPiS_PdiiPiS_Pdii, @function
_Z31__device_stub__Z6vecAddPiS_PdiiPiS_Pdii:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6vecAddPiS_Pdii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z31__device_stub__Z6vecAddPiS_PdiiPiS_Pdii, .-_Z31__device_stub__Z6vecAddPiS_PdiiPiS_Pdii
.globl _Z6vecAddPiS_Pdii
.type _Z6vecAddPiS_Pdii, @function
_Z6vecAddPiS_Pdii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z6vecAddPiS_PdiiPiS_Pdii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z6vecAddPiS_Pdii, .-_Z6vecAddPiS_Pdii
.section .rodata.str1.8
.align 8
.LC5:
.string "Error : Invalid number of arguments \n"
.align 8
.LC7:
.string "Time for the vector addition : %f (milli-seconds) \n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
cmpl $6, %edi
jne .L29
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 16(%rsp)
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r14
movl %eax, 12(%rsp)
movq 32(%rbx), %rdx
movq %rdx, 24(%rsp)
movq 40(%rbx), %rcx
movq %rcx, 32(%rsp)
movslq %eax, %rbx
leaq 0(,%rbx,4), %rbp
salq $3, %rbx
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbx, %rdi
call malloc@PLT
movq %rax, 40(%rsp)
movq %r13, %rdx
movl 12(%rsp), %esi
movq 24(%rsp), %rdi
call _Z12readFileDataPciPi
movq %r12, %rdx
movl 12(%rsp), %esi
movq 32(%rsp), %rdi
call _Z12readFileDataPciPi
leaq 56(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl %eax, %edi
call _Z13error_handler9cudaError
leaq 64(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl %eax, %edi
call _Z13error_handler9cudaError
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %edi
call _Z13error_handler9cudaError
movl $1, %ecx
movq %rbp, %rdx
movq %r13, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z13error_handler9cudaError
movl $1, %ecx
movq %rbp, %rdx
movq %r12, %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z13error_handler9cudaError
movl 16(%rsp), %ecx
imull %r15d, %ecx
leal -1(%rcx,%r14), %eax
cltd
idivl %ecx
movl %eax, %ebp
call clock@PLT
movq %rax, %r14
movl %r15d, 92(%rsp)
movl $1, 96(%rsp)
movl %ebp, 80(%rsp)
movl $1, 84(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L26:
call cudaDeviceSynchronize@PLT
movl %eax, %edi
call _Z13error_handler9cudaError
call clock@PLT
movq %rax, %rbp
movl $2, %ecx
movq %rbx, %rdx
movq 72(%rsp), %rsi
movq 40(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z13error_handler9cudaError
subq %r14, %rbp
imulq $1000, %rbp, %rbp
pxor %xmm0, %xmm0
cvtsi2ssq %rbp, %xmm0
divss .LC6(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L31
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
leaq .LC5(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L30:
movl 16(%rsp), %r8d
movl 12(%rsp), %ecx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z31__device_stub__Z6vecAddPiS_PdiiPiS_Pdii
jmp .L26
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z6vecAddPiS_Pdii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecAddPiS_Pdii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC6:
.long 1232348160
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ee16b105_456.hip"
.globl _Z13error_handler10hipError_t # -- Begin function _Z13error_handler10hipError_t
.p2align 4, 0x90
.type _Z13error_handler10hipError_t,@function
_Z13error_handler10hipError_t: # @_Z13error_handler10hipError_t
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB0_2
# %bb.1:
retq
.LBB0_2:
pushq %rax
.cfi_def_cfa_offset 16
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $19, %ecx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z13error_handler10hipError_t, .Lfunc_end0-_Z13error_handler10hipError_t
.cfi_endproc
# -- End function
.globl _Z21__device_stub__vecAddPiS_Pdii # -- Begin function _Z21__device_stub__vecAddPiS_Pdii
.p2align 4, 0x90
.type _Z21__device_stub__vecAddPiS_Pdii,@function
_Z21__device_stub__vecAddPiS_Pdii: # @_Z21__device_stub__vecAddPiS_Pdii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecAddPiS_Pdii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z21__device_stub__vecAddPiS_Pdii, .Lfunc_end1-_Z21__device_stub__vecAddPiS_Pdii
.cfi_endproc
# -- End function
.globl _Z12readFileDataPciPi # -- Begin function _Z12readFileDataPciPi
.p2align 4, 0x90
.type _Z12readFileDataPciPi,@function
_Z12readFileDataPciPi: # @_Z12readFileDataPciPi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %rbx
movl %esi, %ebp
movq %rdi, %r15
movl $.L.str.2, %esi
callq fopen
testq %rax, %rax
je .LBB2_5
# %bb.1: # %.preheader
movq %rax, %r14
testl %ebp, %ebp
jle .LBB2_4
# %bb.2: # %.lr.ph.preheader
movl %ebp, %r15d
.p2align 4, 0x90
.LBB2_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.3, %esi
movq %r14, %rdi
movq %rbx, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
addq $4, %rbx
decq %r15
jne .LBB2_3
.LBB2_4: # %._crit_edge
movq %r14, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.LBB2_5:
.cfi_def_cfa_offset 48
movl $.L.str.4, %edi
movq %r15, %rsi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end2:
.size _Z12readFileDataPciPi, .Lfunc_end2-_Z12readFileDataPciPi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI3_0:
.long 0x49742400 # float 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $6, %edi
jne .LBB3_23
# %bb.1:
movq %rsi, %rbx
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 64(%rsp) # 8-byte Spill
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 72(%rsp) # 8-byte Spill
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
movq 32(%rbx), %r15
movq 40(%rbx), %rax
movq %rax, 80(%rsp) # 8-byte Spill
movq %r13, %rbp
shlq $32, %rbp
movq %rbp, %r12
sarq $30, %r12
sarq $29, %rbp
movq %r12, %rdi
callq malloc
movq %rax, 16(%rsp) # 8-byte Spill
movq %r12, %rdi
callq malloc
movq %rax, 8(%rsp) # 8-byte Spill
movq %rbp, %rdi
callq malloc
movq %rax, 56(%rsp) # 8-byte Spill
movl $.L.str.2, %esi
movq %r15, %rdi
callq fopen
testq %rax, %rax
je .LBB3_11
# %bb.2: # %.preheader.i
movq %rax, %r14
testl %r13d, %r13d
jle .LBB3_5
# %bb.3: # %.lr.ph.preheader.i
movl %r13d, %ebx
movq 16(%rsp), %r15 # 8-byte Reload
.p2align 4, 0x90
.LBB3_4: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl $.L.str.3, %esi
movq %r14, %rdi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
addq $4, %r15
decq %rbx
jne .LBB3_4
.LBB3_5: # %_Z12readFileDataPciPi.exit
movq %r14, %rdi
callq fclose
movl $.L.str.2, %esi
movq 80(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
callq fopen
testq %rax, %rax
je .LBB3_13
# %bb.6: # %.preheader.i44
movq %rax, %r14
testl %r13d, %r13d
jle .LBB3_9
# %bb.7: # %.lr.ph.preheader.i45
movl %r13d, %r15d
movq 8(%rsp), %rbx # 8-byte Reload
.p2align 4, 0x90
.LBB3_8: # %.lr.ph.i47
# =>This Inner Loop Header: Depth=1
movl $.L.str.3, %esi
movq %r14, %rdi
movq %rbx, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
addq $4, %rbx
decq %r15
jne .LBB3_8
.LBB3_9: # %_Z12readFileDataPciPi.exit51
movq %r14, %rdi
callq fclose
leaq 40(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB3_10
# %bb.14: # %_Z13error_handler10hipError_t.exit
leaq 32(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
movq 16(%rsp), %r15 # 8-byte Reload
movq 8(%rsp), %r14 # 8-byte Reload
movq 72(%rsp), %rbx # 8-byte Reload
jne .LBB3_10
# %bb.15: # %_Z13error_handler10hipError_t.exit54
leaq 24(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB3_10
# %bb.16: # %_Z13error_handler10hipError_t.exit56
movq 40(%rsp), %rdi
movq %r15, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_10
# %bb.17: # %_Z13error_handler10hipError_t.exit58
movq 32(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_10
# %bb.18: # %_Z13error_handler10hipError_t.exit60
movq 64(%rsp), %r14 # 8-byte Reload
movl %r14d, %ecx
imull %ebx, %ecx
leal (%rcx,%r13), %eax
decl %eax
cltd
idivl %ecx
movq %rbx, %r15
movl %eax, %ebx
callq clock
movq %rax, %r12
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rbx
movl %r14d, %edx
orq %rax, %rdx
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_20
# %bb.19:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
movl %r13d, 52(%rsp)
movl %r15d, 48(%rsp)
leaq 152(%rsp), %rax
movq %rax, 160(%rsp)
leaq 144(%rsp), %rax
movq %rax, 168(%rsp)
leaq 136(%rsp), %rax
movq %rax, 176(%rsp)
leaq 52(%rsp), %rax
movq %rax, 184(%rsp)
leaq 48(%rsp), %rax
movq %rax, 192(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z6vecAddPiS_Pdii, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_20:
callq hipDeviceSynchronize
testl %eax, %eax
movq 16(%rsp), %r15 # 8-byte Reload
jne .LBB3_10
# %bb.21: # %_Z13error_handler10hipError_t.exit62
callq clock
movq %rax, %rbx
movq 24(%rsp), %rsi
movq 56(%rsp), %r13 # 8-byte Reload
movq %r13, %rdi
movq %rbp, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
movq 8(%rsp), %r14 # 8-byte Reload
jne .LBB3_10
# %bb.22: # %_Z13error_handler10hipError_t.exit64
subq %r12, %rbx
imulq $1000, %rbx, %rax # imm = 0x3E8
cvtsi2ss %rax, %xmm0
divss .LCPI3_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq %r15, %rdi
callq free
movq %r14, %rdi
callq free
movq %r13, %rdi
callq free
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_10:
.cfi_def_cfa_offset 256
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $19, %ecx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.LBB3_23:
movl $.Lstr, %edi
callq puts@PLT
movl $1, %edi
callq exit
.LBB3_11:
movl $.L.str.4, %edi
movq %r15, %rsi
jmp .LBB3_12
.LBB3_13:
movl $.L.str.4, %edi
movq %rbx, %rsi
.LBB3_12:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecAddPiS_Pdii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%s in %s at line %d\n"
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/anantshah200/CS6023/master/Assignment1/ee16b105_456.hip"
.size .L.str.1, 113
.type _Z6vecAddPiS_Pdii,@object # @_Z6vecAddPiS_Pdii
.section .rodata,"a",@progbits
.globl _Z6vecAddPiS_Pdii
.p2align 3, 0x0
_Z6vecAddPiS_Pdii:
.quad _Z21__device_stub__vecAddPiS_Pdii
.size _Z6vecAddPiS_Pdii, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "r+"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "error : File %s not found"
.size .L.str.4, 26
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Time for the vector addition : %f (milli-seconds) \n"
.size .L.str.6, 53
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6vecAddPiS_Pdii"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Error : Invalid number of arguments "
.size .Lstr, 37
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecAddPiS_Pdii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6vecAddPiS_Pdii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void cunnx_BlockSparse_updateGradOutput_kernel( float *_gradOutput, float* gradOutputScale, const float *gradOutput, const float *output, const float *outputScale, int outputWindowSize, int outputSize)
{
__shared__ float buffer[BLOCKSPARSE_THREADS];
int tx = threadIdx.x;
int i_step = blockDim.x;
int k = blockIdx.x;
float *_gradOutput_k = _gradOutput + k*outputWindowSize*outputSize;
float *gradOutputScale_k = gradOutputScale + k*outputWindowSize;
const float *gradOutput_k = gradOutput + k*outputWindowSize*outputSize;
const float *output_k = output + k*outputWindowSize*outputSize;
const float *outputScale_k = outputScale + k*outputWindowSize;
// get gradients for outputScale (to be backwarded to a Gater)
for (int m=0; m<outputWindowSize; m++)
{
float outputScale = outputScale_k[m];
float *_blockGradOutput = _gradOutput_k + m*outputSize;
const float *blockGradOutput = gradOutput_k + m*outputSize;
const float *blockOutput = output_k + m*outputSize;
buffer[tx] = 0;
for (int j=tx; j<outputSize; j+=i_step)
{
const float grad = blockGradOutput[j];
buffer[tx] += blockOutput[j]*grad;
_blockGradOutput[j] = grad*outputScale;
}
// add (reduce)
for (unsigned int stride = blockDim.x >> 1; stride > 0; stride >>= 1)
{
__syncthreads();
if (tx < stride)
buffer[tx] += buffer[tx+stride];
}
if (tx == 0)
gradOutputScale_k[m] = buffer[0]/(outputScale+0.00000001);
}
} | code for sm_80
Function : _Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ I2F.U32.RP R3, c[0x0][0x0] ; /* 0x0000000000037b06 */
/* 0x000e220000209000 */
/*0050*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0060*/ S2UR UR5, SR_CTAID.X ; /* 0x00000000000579c3 */
/* 0x000ea20000002500 */
/*0070*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fe20003f45070 */
/*0080*/ ULDC.64 UR6, c[0x0][0x188] ; /* 0x0000620000067ab9 */
/* 0x000fe40000000a00 */
/*0090*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*00a0*/ ULDC.64 UR14, c[0x0][0x118] ; /* 0x00004600000e7ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ MUFU.RCP R3, R3 ; /* 0x0000000300037308 */
/* 0x001e220000001000 */
/*00c0*/ LOP3.LUT R0, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff007212 */
/* 0x002fe200078e33ff */
/*00d0*/ UIMAD UR5, UR5, UR6, URZ ; /* 0x00000006050572a4 */
/* 0x004fe2000f8e023f */
/*00e0*/ IMAD.SHL.U32 R6, R2, 0x4, RZ ; /* 0x0000000402067824 */
/* 0x000fc400078e00ff */
/*00f0*/ IADD3 R0, R0, c[0x0][0x18c], RZ ; /* 0x0000630000007a10 */
/* 0x000fe20007ffe0ff */
/*0100*/ ULDC UR6, c[0x0][0x0] ; /* 0x0000000000067ab9 */
/* 0x000fe20000000800 */
/*0110*/ IADD3 R4, R3, 0xffffffe, RZ ; /* 0x0ffffffe03047810 */
/* 0x001fe20007ffe0ff */
/*0120*/ UIMAD UR7, UR5, UR7, URZ ; /* 0x00000007050772a4 */
/* 0x000fe4000f8e023f */
/*0130*/ USHF.R.U32.HI UR6, URZ, 0x1, UR6 ; /* 0x000000013f067899 */
/* 0x000fe20008011606 */
/*0140*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0150*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0160*/ IMAD.MOV R7, RZ, RZ, -R5 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a05 */
/*0170*/ IMAD R7, R7, c[0x0][0x0], RZ ; /* 0x0000000007077a24 */
/* 0x000fc800078e02ff */
/*0180*/ IMAD.HI.U32 R5, R5, R7, R4 ; /* 0x0000000705057227 */
/* 0x000fe200078e0004 */
/*0190*/ IADD3 R4, R2, c[0x0][0x0], RZ ; /* 0x0000000002047a10 */
/* 0x000fca0007ffe0ff */
/*01a0*/ IMAD.HI.U32 R3, R5, R0, RZ ; /* 0x0000000005037227 */
/* 0x000fc800078e00ff */
/*01b0*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a03 */
/*01c0*/ IMAD R0, R5, c[0x0][0x0], R0 ; /* 0x0000000005007a24 */
/* 0x000fe200078e0200 */
/*01d0*/ IADD3 R5, R4, c[0x0][0x0], RZ ; /* 0x0000000004057a10 */
/* 0x000fc80007ffe0ff */
/*01e0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x0], PT ; /* 0x0000000000007a0c */
/* 0x000fe40003f06070 */
/*01f0*/ IADD3 R7, R5, c[0x0][0x0], RZ ; /* 0x0000000005077a10 */
/* 0x000fd60007ffe0ff */
/*0200*/ @P0 IADD3 R0, R0, -c[0x0][0x0], RZ ; /* 0x8000000000000a10 */
/* 0x000fe40007ffe0ff */
/*0210*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fe40007ffe0ff */
/*0220*/ ISETP.GE.U32.AND P1, PT, R0, c[0x0][0x0], PT ; /* 0x0000000000007a0c */
/* 0x000fda0003f26070 */
/*0230*/ @P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103031810 */
/* 0x000fe40007ffe0ff */
/*0240*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x0], RZ, 0x33, !PT ; /* 0x00000000ff03aa12 */
/* 0x000fc800078e33ff */
/*0250*/ IADD3 R22, R3, 0x1, RZ ; /* 0x0000000103167810 */
/* 0x000fc80007ffe0ff */
/*0260*/ LOP3.LUT R22, R22, 0x3, RZ, 0xc0, !PT ; /* 0x0000000316167812 */
/* 0x000fe400078ec0ff */
/*0270*/ USHF.R.S32.HI UR8, URZ, 0x1f, UR4 ; /* 0x0000001f3f087899 */
/* 0x000fe40008011404 */
/*0280*/ UIADD3 UR9, UP0, UR5, UR4, URZ ; /* 0x0000000405097290 */
/* 0x000fe4000ff1e03f */
/*0290*/ ULDC.64 UR12, c[0x0][0x180] ; /* 0x00006000000c7ab9 */
/* 0x000fe40000000a00 */
/*02a0*/ ULEA.HI.X.SX32 UR8, UR5, UR8, 0x1, UP0 ; /* 0x0000000805087291 */
/* 0x000fe400080f0e3f */
/*02b0*/ USHF.L.U32 UR11, UR9, 0x2, URZ ; /* 0x00000002090b7899 */
/* 0x000fe4000800063f */
/*02c0*/ USHF.L.U64.HI UR10, UR9, 0x2, UR8 ; /* 0x00000002090a7899 */
/* 0x000fc40008010208 */
/*02d0*/ UIADD3 UR8, UP0, UR11, UR12, URZ ; /* 0x0000000c0b087290 */
/* 0x000fc8000ff1e03f */
/*02e0*/ UIADD3.X UR9, UR10, UR13, URZ, UP0, !UPT ; /* 0x0000000d0a097290 */
/* 0x000fe400087fe43f */
/*02f0*/ IMAD.U32 R8, RZ, RZ, UR8 ; /* 0x00000008ff087e24 */
/* 0x000fe2000f8e00ff */
/*0300*/ STS [R2.X4], RZ ; /* 0x000000ff02007388 */
/* 0x0011e20000004800 */
/*0310*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x18c], PT ; /* 0x0000630002007a0c */
/* 0x000fe20003f06270 */
/*0320*/ ULDC.64 UR12, c[0x0][0x188] ; /* 0x00006200000c7ab9 */
/* 0x000fe20000000a00 */
/*0330*/ IMAD.U32 R9, RZ, RZ, UR9 ; /* 0x00000009ff097e24 */
/* 0x002fca000f8e00ff */
/*0340*/ LDG.E R0, [R8.64] ; /* 0x0000000e08007981 */
/* 0x020162000c1e1900 */
/*0350*/ UIMAD UR8, UR4, UR13, URZ ; /* 0x0000000d040872a4 */
/* 0x000fe2000f8e023f */
/*0360*/ BSSY B0, 0xaa0 ; /* 0x0000073000007945 */
/* 0x000fe20003800000 */
/*0370*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe4000fffe03f */
/*0380*/ USHF.R.S32.HI UR9, URZ, 0x1f, UR8 ; /* 0x0000001f3f097899 */
/* 0x000fe40008011408 */
/*0390*/ UIADD3 UR8, UP1, UR7, UR8, URZ ; /* 0x0000000807087290 */
/* 0x000fe4000ff3e03f */
/*03a0*/ UISETP.GE.AND UP0, UPT, UR4, UR12, UPT ; /* 0x0000000c0400728c */
/* 0x000fe4000bf06270 */
/*03b0*/ ULEA.HI.X.SX32 UR9, UR7, UR9, 0x1, UP1 ; /* 0x0000000907097291 */
/* 0x000fe200088f0e3f */
/*03c0*/ @P0 BRA 0xa90 ; /* 0x000006c000000947 */
/* 0x000fec0003800000 */
/*03d0*/ ISETP.NE.AND P0, PT, R22, RZ, PT ; /* 0x000000ff1600720c */
/* 0x001fe20003f05270 */
/*03e0*/ BSSY B1, 0x770 ; /* 0x0000038000017945 */
/* 0x000fe20003800000 */
/*03f0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fc400078e00ff */
/*0400*/ IMAD.MOV.U32 R10, RZ, RZ, R2 ; /* 0x000000ffff0a7224 */
/* 0x000fd200078e0002 */
/*0410*/ @!P0 BRA 0x760 ; /* 0x0000034000008947 */
/* 0x000fea0003800000 */
/*0420*/ IADD3 R8, P0, R2, UR8, RZ ; /* 0x0000000802087c10 */
/* 0x000fc8000ff1e0ff */
/*0430*/ LEA.HI.X.SX32 R9, R2, UR9, 0x1, P0 ; /* 0x0000000902097c11 */
/* 0x000fe200080f0eff */
/*0440*/ IMAD.SHL.U32 R16, R8, 0x4, RZ ; /* 0x0000000408107824 */
/* 0x000fc600078e00ff */
/*0450*/ SHF.L.U64.HI R8, R8, 0x2, R9 ; /* 0x0000000208087819 */
/* 0x000fe40000010209 */
/*0460*/ IADD3 R14, P0, R16, c[0x0][0x170], RZ ; /* 0x00005c00100e7a10 */
/* 0x000fc80007f1e0ff */
/*0470*/ IADD3.X R15, R8, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d00080f7a10 */
/* 0x000fcc00007fe4ff */
/*0480*/ LDG.E R15, [R14.64] ; /* 0x0000000e0e0f7981 */
/* 0x000ea2000c1e1900 */
/*0490*/ IADD3 R12, P0, R16, c[0x0][0x178], RZ ; /* 0x00005e00100c7a10 */
/* 0x000fc80007f1e0ff */
/*04a0*/ IADD3.X R13, R8, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f00080d7a10 */
/* 0x000fca00007fe4ff */
/*04b0*/ LDG.E R12, [R12.64] ; /* 0x0000000e0c0c7981 */
/* 0x000ee2000c1e1900 */
/*04c0*/ IADD3 R16, P0, R16, c[0x0][0x160], RZ ; /* 0x0000580010107a10 */
/* 0x000fe20007f1e0ff */
/*04d0*/ IMAD.MOV.U32 R10, RZ, RZ, R4 ; /* 0x000000ffff0a7224 */
/* 0x000fc600078e0004 */
/*04e0*/ IADD3.X R17, R8, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590008117a10 */
/* 0x000fe400007fe4ff */
/*04f0*/ ISETP.NE.AND P0, PT, R22, 0x1, PT ; /* 0x000000011600780c */
/* 0x000fe20003f05270 */
/*0500*/ FMUL R11, R0, R15 ; /* 0x0000000f000b7220 */
/* 0x024fca0000400000 */
/*0510*/ STG.E [R16.64], R11 ; /* 0x0000000b10007986 */
/* 0x0001e2000c10190e */
/*0520*/ FFMA R9, R12, R15, RZ ; /* 0x0000000f0c097223 */
/* 0x008fcc00000000ff */
/*0530*/ @!P0 BRA 0x760 ; /* 0x0000022000008947 */
/* 0x000fea0003800000 */
/*0540*/ IADD3 R8, P0, R4, UR8, RZ ; /* 0x0000000804087c10 */
/* 0x000fc8000ff1e0ff */
/*0550*/ LEA.HI.X.SX32 R11, R4, UR9, 0x1, P0 ; /* 0x00000009040b7c11 */
/* 0x001fe200080f0eff */
/*0560*/ IMAD.SHL.U32 R16, R8, 0x4, RZ ; /* 0x0000000408107824 */
/* 0x000fc600078e00ff */
/*0570*/ SHF.L.U64.HI R8, R8, 0x2, R11 ; /* 0x0000000208087819 */
/* 0x000fe4000001020b */
/*0580*/ IADD3 R14, P0, R16, c[0x0][0x170], RZ ; /* 0x00005c00100e7a10 */
/* 0x000fc80007f1e0ff */
/*0590*/ IADD3.X R15, R8, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d00080f7a10 */
/* 0x000fcc00007fe4ff */
/*05a0*/ LDG.E R15, [R14.64] ; /* 0x0000000e0e0f7981 */
/* 0x000ea2000c1e1900 */
/*05b0*/ IADD3 R12, P0, R16, c[0x0][0x178], RZ ; /* 0x00005e00100c7a10 */
/* 0x000fc80007f1e0ff */
/*05c0*/ IADD3.X R13, R8, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f00080d7a10 */
/* 0x000fca00007fe4ff */
/*05d0*/ LDG.E R12, [R12.64] ; /* 0x0000000e0c0c7981 */
/* 0x000ee2000c1e1900 */
/*05e0*/ IADD3 R16, P0, R16, c[0x0][0x160], RZ ; /* 0x0000580010107a10 */
/* 0x000fe20007f1e0ff */
/*05f0*/ IMAD.MOV.U32 R10, RZ, RZ, R5 ; /* 0x000000ffff0a7224 */
/* 0x000fc600078e0005 */
/*0600*/ IADD3.X R17, R8, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590008117a10 */
/* 0x000fe400007fe4ff */
/*0610*/ ISETP.NE.AND P0, PT, R22, 0x2, PT ; /* 0x000000021600780c */
/* 0x000fe20003f05270 */
/*0620*/ FMUL R11, R0, R15 ; /* 0x0000000f000b7220 */
/* 0x004fca0000400000 */
/*0630*/ STG.E [R16.64], R11 ; /* 0x0000000b10007986 */
/* 0x0001e2000c10190e */
/*0640*/ FFMA R9, R12, R15, R9 ; /* 0x0000000f0c097223 */
/* 0x008fcc0000000009 */
/*0650*/ @!P0 BRA 0x760 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0660*/ IADD3 R8, P0, R5, UR8, RZ ; /* 0x0000000805087c10 */
/* 0x000fc8000ff1e0ff */
/*0670*/ LEA.HI.X.SX32 R11, R5, UR9, 0x1, P0 ; /* 0x00000009050b7c11 */
/* 0x001fe200080f0eff */
/*0680*/ IMAD.SHL.U32 R16, R8, 0x4, RZ ; /* 0x0000000408107824 */
/* 0x000fc600078e00ff */
/*0690*/ SHF.L.U64.HI R8, R8, 0x2, R11 ; /* 0x0000000208087819 */
/* 0x000fe4000001020b */
/*06a0*/ IADD3 R14, P0, R16, c[0x0][0x170], RZ ; /* 0x00005c00100e7a10 */
/* 0x000fc80007f1e0ff */
/*06b0*/ IADD3.X R15, R8, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d00080f7a10 */
/* 0x000fcc00007fe4ff */
/*06c0*/ LDG.E R15, [R14.64] ; /* 0x0000000e0e0f7981 */
/* 0x000ea2000c1e1900 */
/*06d0*/ IADD3 R12, P0, R16, c[0x0][0x178], RZ ; /* 0x00005e00100c7a10 */
/* 0x000fc80007f1e0ff */
/*06e0*/ IADD3.X R13, R8, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f00080d7a10 */
/* 0x000fca00007fe4ff */
/*06f0*/ LDG.E R12, [R12.64] ; /* 0x0000000e0c0c7981 */
/* 0x000ee2000c1e1900 */
/*0700*/ IADD3 R16, P0, R16, c[0x0][0x160], RZ ; /* 0x0000580010107a10 */
/* 0x000fe20007f1e0ff */
/*0710*/ IMAD.MOV.U32 R10, RZ, RZ, R7 ; /* 0x000000ffff0a7224 */
/* 0x000fc600078e0007 */
/*0720*/ IADD3.X R17, R8, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590008117a10 */
/* 0x000fe200007fe4ff */
/*0730*/ FMUL R11, R0, R15 ; /* 0x0000000f000b7220 */
/* 0x004fca0000400000 */
/*0740*/ STG.E [R16.64], R11 ; /* 0x0000000b10007986 */
/* 0x0001e2000c10190e */
/*0750*/ FFMA R9, R12, R15, R9 ; /* 0x0000000f0c097223 */
/* 0x008fc60000000009 */
/*0760*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0770*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe20003f06070 */
/*0780*/ BSSY B1, 0xa80 ; /* 0x000002f000017945 */
/* 0x000fd80003800000 */
/*0790*/ @!P0 BRA 0xa70 ; /* 0x000002d000008947 */
/* 0x000fea0003800000 */
/*07a0*/ IADD3 R8, P0, R10, UR8, RZ ; /* 0x000000080a087c10 */
/* 0x000fc8000ff1e0ff */
/*07b0*/ LEA.HI.X.SX32 R11, R10, UR9, 0x1, P0 ; /* 0x000000090a0b7c11 */
/* 0x001fe200080f0eff */
/*07c0*/ IMAD.SHL.U32 R16, R8, 0x4, RZ ; /* 0x0000000408107824 */
/* 0x000fc600078e00ff */
/*07d0*/ SHF.L.U64.HI R8, R8, 0x2, R11 ; /* 0x0000000208087819 */
/* 0x000fe4000001020b */
/*07e0*/ IADD3 R12, P0, R16, c[0x0][0x170], RZ ; /* 0x00005c00100c7a10 */
/* 0x000fc80007f1e0ff */
/*07f0*/ IADD3.X R13, R8, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d00080d7a10 */
/* 0x000fca00007fe4ff */
/*0800*/ LDG.E R27, [R12.64] ; /* 0x0000000e0c1b7981 */
/* 0x000ea2000c1e1900 */
/*0810*/ IADD3 R18, P0, R16.reuse, c[0x0][0x178], RZ ; /* 0x00005e0010127a10 */
/* 0x040fe20007f1e0ff */
/*0820*/ IMAD.MOV.U32 R29, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff1d7624 */
/* 0x000fe200078e00ff */
/*0830*/ IADD3 R16, P1, R16, c[0x0][0x160], RZ ; /* 0x0000580010107a10 */
/* 0x000fe40007f3e0ff */
/*0840*/ IADD3.X R19, R8.reuse, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f0008137a10 */
/* 0x040fe200007fe4ff */
/*0850*/ IMAD.WIDE R24, R29, 0x4, R12 ; /* 0x000000041d187825 */
/* 0x000fe200078e020c */
/*0860*/ IADD3.X R17, R8, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590008117a10 */
/* 0x000fc60000ffe4ff */
/*0870*/ LDG.E R26, [R18.64] ; /* 0x0000000e121a7981 */
/* 0x0000e2000c1e1900 */
/*0880*/ FMUL R28, R0, R27 ; /* 0x0000001b001c7220 */
/* 0x024fca0000400000 */
/*0890*/ STG.E [R16.64], R28 ; /* 0x0000001c10007986 */
/* 0x0003e8000c10190e */
/*08a0*/ LDG.E R23, [R24.64] ; /* 0x0000000e18177981 */
/* 0x000ea2000c1e1900 */
/*08b0*/ IMAD.WIDE R20, R29, 0x4, R18 ; /* 0x000000041d147825 */
/* 0x000fc800078e0212 */
/*08c0*/ IMAD.WIDE R14, R29.reuse, 0x4, R24 ; /* 0x000000041d0e7825 */
/* 0x040fe200078e0218 */
/*08d0*/ LDG.E R8, [R20.64] ; /* 0x0000000e14087981 */
/* 0x0008e6000c1e1900 */
/*08e0*/ IMAD.WIDE R16, R29, 0x4, R16 ; /* 0x000000041d107825 */
/* 0x002fc800078e0210 */
/*08f0*/ FMUL R11, R0, R23 ; /* 0x00000017000b7220 */
/* 0x004fca0000400000 */
/*0900*/ STG.E [R16.64], R11 ; /* 0x0000000b10007986 */
/* 0x0003e8000c10190e */
/*0910*/ LDG.E R11, [R14.64] ; /* 0x0000000e0e0b7981 */
/* 0x002f22000c1e1900 */
/*0920*/ IMAD.WIDE R12, R29, 0x4, R20 ; /* 0x000000041d0c7825 */
/* 0x000fc800078e0214 */
/*0930*/ IMAD.WIDE R18, R29.reuse, 0x4, R16 ; /* 0x000000041d127825 */
/* 0x041fe200078e0210 */
/*0940*/ LDG.E R28, [R12.64] ; /* 0x0000000e0c1c7981 */
/* 0x0000a6000c1e1900 */
/*0950*/ IMAD.WIDE R24, R29, 0x4, R14 ; /* 0x000000041d187825 */
/* 0x000fc800078e020e */
/*0960*/ IMAD.WIDE R12, R29, 0x4, R12 ; /* 0x000000041d0c7825 */
/* 0x001fc800078e020c */
/*0970*/ FMUL R21, R0, R11 ; /* 0x0000000b00157220 */
/* 0x010fca0000400000 */
/*0980*/ STG.E [R18.64], R21 ; /* 0x0000001512007986 */
/* 0x0001e8000c10190e */
/*0990*/ LDG.E R25, [R24.64] ; /* 0x0000000e18197981 */
/* 0x000f28000c1e1900 */
/*09a0*/ LDG.E R20, [R12.64] ; /* 0x0000000e0c147981 */
/* 0x000f22000c1e1900 */
/*09b0*/ IMAD.WIDE R16, R29, 0x4, R18 ; /* 0x000000041d107825 */
/* 0x000fc800078e0212 */
/*09c0*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0e7624 */
/* 0x000fe400078e00ff */
/*09d0*/ IMAD R10, R29, 0x2, R10 ; /* 0x000000021d0a7824 */
/* 0x000fc800078e020a */
/*09e0*/ IMAD R10, R14, 0x2, R10 ; /* 0x000000020e0a7824 */
/* 0x000fe400078e020a */
/*09f0*/ FFMA R26, R26, R27, R9 ; /* 0x0000001b1a1a7223 */
/* 0x008fc60000000009 */
/*0a00*/ ISETP.GE.AND P0, PT, R10, c[0x0][0x18c], PT ; /* 0x000063000a007a0c */
/* 0x000fe20003f06270 */
/*0a10*/ FFMA R8, R8, R23, R26 ; /* 0x0000001708087223 */
/* 0x000fc8000000001a */
/*0a20*/ FFMA R8, R28, R11, R8 ; /* 0x0000000b1c087223 */
/* 0x004fe40000000008 */
/*0a30*/ FMUL R15, R0, R25 ; /* 0x00000019000f7220 */
/* 0x010fca0000400000 */
/*0a40*/ STG.E [R16.64], R15 ; /* 0x0000000f10007986 */
/* 0x0001e2000c10190e */
/*0a50*/ FFMA R9, R20, R25, R8 ; /* 0x0000001914097223 */
/* 0x000fe20000000008 */
/*0a60*/ @!P0 BRA 0x7a0 ; /* 0xfffffd3000008947 */
/* 0x000fea000383ffff */
/*0a70*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0a80*/ STS [R2.X4], R9 ; /* 0x0000000902007388 */
/* 0x0003e40000004800 */
/*0a90*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0aa0*/ ISETP.NE.AND P0, PT, RZ, UR6, PT ; /* 0x00000006ff007c0c */
/* 0x000fe4000bf05270 */
/*0ab0*/ ISETP.NE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fd60003f25270 */
/*0ac0*/ @!P0 BRA 0xb80 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0ad0*/ IMAD.U32 R9, RZ, RZ, UR6 ; /* 0x00000006ff097e24 */
/* 0x002fc8000f8e00ff */
/*0ae0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0af0*/ ISETP.GE.U32.AND P0, PT, R2, R9, PT ; /* 0x000000090200720c */
/* 0x000fda0003f06070 */
/*0b00*/ @!P0 IMAD R8, R9, 0x4, R6 ; /* 0x0000000409088824 */
/* 0x000fe200078e0206 */
/*0b10*/ SHF.R.U32.HI R9, RZ, 0x1, R9 ; /* 0x00000001ff097819 */
/* 0x000fe20000011609 */
/*0b20*/ @!P0 LDS R10, [R2.X4] ; /* 0x00000000020a8984 */
/* 0x000fe80000004800 */
/*0b30*/ @!P0 LDS R11, [R8] ; /* 0x00000000080b8984 */
/* 0x000e240000000800 */
/*0b40*/ @!P0 FADD R11, R10, R11 ; /* 0x0000000b0a0b8221 */
/* 0x001fca0000000000 */
/*0b50*/ @!P0 STS [R2.X4], R11 ; /* 0x0000000b02008388 */
/* 0x0001e20000004800 */
/*0b60*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fda0003f05270 */
/*0b70*/ @P0 BRA 0xae0 ; /* 0xffffff6000000947 */
/* 0x001fea000383ffff */
/*0b80*/ BSSY B0, 0xd80 ; /* 0x000001f000007945 */
/* 0x000fe20003800000 */
/*0b90*/ @P1 BRA 0xd70 ; /* 0x000001d000001947 */
/* 0x000fea0003800000 */
/*0ba0*/ F2F.F64.F32 R20, R0 ; /* 0x0000000000147310 */
/* 0x020e220000201800 */
/*0bb0*/ LDS R12, [RZ] ; /* 0x00000000ff0c7984 */
/* 0x000ea20000000800 */
/*0bc0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x000fe200078e00ff */
/*0bd0*/ DADD R20, R20, c[0x2][0x0] ; /* 0x0080000014147629 */
/* 0x001e0c0000000000 */
/*0be0*/ MUFU.RCP64H R9, R21 ; /* 0x0000001500097308 */
/* 0x003e240000001800 */
/*0bf0*/ DFMA R10, -R20, R8, 1 ; /* 0x3ff00000140a742b */
/* 0x001e0c0000000108 */
/*0c00*/ F2F.F64.F32 R12, R12 ; /* 0x0000000c000c7310 */
/* 0x004e620000201800 */
/*0c10*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*0c20*/ DFMA R10, R8, R10, R8 ; /* 0x0000000a080a722b */
/* 0x001e0c0000000008 */
/*0c30*/ DFMA R8, -R20, R10, 1 ; /* 0x3ff000001408742b */
/* 0x001e22000000010a */
/*0c40*/ FSETP.GEU.AND P1, PT, |R13|, 6.5827683646048100446e-37, PT ; /* 0x036000000d00780b */
/* 0x002fca0003f2e200 */
/*0c50*/ DFMA R8, R10, R8, R10 ; /* 0x000000080a08722b */
/* 0x001e0c000000000a */
/*0c60*/ DMUL R10, R12, R8 ; /* 0x000000080c0a7228 */
/* 0x001e0c0000000000 */
/*0c70*/ DFMA R14, -R20, R10, R12 ; /* 0x0000000a140e722b */
/* 0x001e0c000000010c */
/*0c80*/ DFMA R8, R8, R14, R10 ; /* 0x0000000e0808722b */
/* 0x001e14000000000a */
/*0c90*/ FFMA R0, RZ, R21, R9 ; /* 0x00000015ff007223 */
/* 0x001fca0000000009 */
/*0ca0*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*0cb0*/ @P0 BRA P1, 0xd00 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*0cc0*/ MOV R0, 0xce0 ; /* 0x00000ce000007802 */
/* 0x000fe40000000f00 */
/*0cd0*/ CALL.REL.NOINC 0xdb0 ; /* 0x000000d000007944 */
/* 0x000fea0003c00000 */
/*0ce0*/ IMAD.MOV.U32 R8, RZ, RZ, R16 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0010 */
/*0cf0*/ IMAD.MOV.U32 R9, RZ, RZ, R17 ; /* 0x000000ffff097224 */
/* 0x000fca00078e0011 */
/*0d00*/ ULDC.64 UR8, c[0x0][0x168] ; /* 0x00005a0000087ab9 */
/* 0x000fe20000000a00 */
/*0d10*/ F2F.F32.F64 R9, R8 ; /* 0x0000000800097310 */
/* 0x000e220000301000 */
/*0d20*/ UIADD3 UR8, UP1, UR11, UR8, URZ ; /* 0x000000080b087290 */
/* 0x000fc8000ff3e03f */
/*0d30*/ UIADD3.X UR9, UR10, UR9, URZ, UP1, !UPT ; /* 0x000000090a097290 */
/* 0x000fe40008ffe43f */
/*0d40*/ IMAD.U32 R10, RZ, RZ, UR8 ; /* 0x00000008ff0a7e24 */
/* 0x000fc8000f8e00ff */
/*0d50*/ IMAD.U32 R11, RZ, RZ, UR9 ; /* 0x00000009ff0b7e24 */
/* 0x000fca000f8e00ff */
/*0d60*/ STG.E [R10.64], R9 ; /* 0x000000090a007986 */
/* 0x0011e4000c10190e */
/*0d70*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0d80*/ PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0003f0f008 */
/*0d90*/ @!P0 BRA 0x270 ; /* 0xfffff4d000008947 */
/* 0x000fea000383ffff */
/*0da0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0db0*/ FSETP.GEU.AND P0, PT, |R21|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000001500780b */
/* 0x040fe20003f0e200 */
/*0dc0*/ IMAD.MOV.U32 R10, RZ, RZ, R20.reuse ; /* 0x000000ffff0a7224 */
/* 0x100fe200078e0014 */
/*0dd0*/ LOP3.LUT R8, R21, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff15087812 */
/* 0x000fe200078ec0ff */
/*0de0*/ IMAD.MOV.U32 R11, RZ, RZ, R21 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0015 */
/*0df0*/ FSETP.GEU.AND P2, PT, |R13|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000d00780b */
/* 0x040fe20003f4e200 */
/*0e00*/ IMAD.MOV.U32 R24, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff187424 */
/* 0x000fe200078e00ff */
/*0e10*/ LOP3.LUT R9, R8, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000008097812 */
/* 0x000fe200078efcff */
/*0e20*/ IMAD.MOV.U32 R8, RZ, RZ, R20 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0014 */
/*0e30*/ LOP3.LUT R23, R13, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000d177812 */
/* 0x000fe200078ec0ff */
/*0e40*/ IMAD.MOV.U32 R26, RZ, RZ, 0x1 ; /* 0x00000001ff1a7424 */
/* 0x000fe200078e00ff */
/*0e50*/ LOP3.LUT R20, R21, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000015147812 */
/* 0x000fe200078ec0ff */
/*0e60*/ BSSY B1, 0x1370 ; /* 0x0000050000017945 */
/* 0x000fe40003800000 */
/*0e70*/ @!P0 DMUL R8, R10, 8.98846567431157953865e+307 ; /* 0x7fe000000a088828 */
/* 0x000e220000000000 */
/*0e80*/ ISETP.GE.U32.AND P1, PT, R23, R20, PT ; /* 0x000000141700720c */
/* 0x000fe20003f26070 */
/*0e90*/ IMAD.MOV.U32 R25, RZ, RZ, R23 ; /* 0x000000ffff197224 */
/* 0x000fc400078e0017 */
/*0ea0*/ @!P2 LOP3.LUT R14, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b0ea812 */
/* 0x000fe200078ec0ff */
/*0eb0*/ @!P2 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff12a224 */
/* 0x000fe200078e00ff */
/*0ec0*/ MUFU.RCP64H R27, R9 ; /* 0x00000009001b7308 */
/* 0x001e220000001800 */
/*0ed0*/ SEL R15, R24.reuse, 0x63400000, !P1 ; /* 0x63400000180f7807 */
/* 0x040fe40004800000 */
/*0ee0*/ @!P2 ISETP.GE.U32.AND P3, PT, R23, R14, PT ; /* 0x0000000e1700a20c */
/* 0x000fe20003f66070 */
/*0ef0*/ IMAD.MOV.U32 R14, RZ, RZ, R12 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e000c */
/*0f00*/ LOP3.LUT R15, R15, 0x800fffff, R13, 0xf8, !PT ; /* 0x800fffff0f0f7812 */
/* 0x000fe400078ef80d */
/*0f10*/ @!P2 SEL R19, R24, 0x63400000, !P3 ; /* 0x634000001813a807 */
/* 0x000fc80005800000 */
/*0f20*/ @!P2 LOP3.LUT R19, R19, 0x80000000, R13, 0xf8, !PT ; /* 0x800000001313a812 */
/* 0x000fc800078ef80d */
/*0f30*/ @!P2 LOP3.LUT R19, R19, 0x100000, RZ, 0xfc, !PT ; /* 0x001000001313a812 */
/* 0x000fe200078efcff */
/*0f40*/ DFMA R16, R26, -R8, 1 ; /* 0x3ff000001a10742b */
/* 0x001e0a0000000808 */
/*0f50*/ @!P2 DFMA R14, R14, 2, -R18 ; /* 0x400000000e0ea82b */
/* 0x000fc80000000812 */
/*0f60*/ DFMA R16, R16, R16, R16 ; /* 0x000000101010722b */
/* 0x001e0c0000000010 */
/*0f70*/ DFMA R16, R26, R16, R26 ; /* 0x000000101a10722b */
/* 0x001062000000001a */
/*0f80*/ @!P2 LOP3.LUT R25, R15, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000f19a812 */
/* 0x000fe200078ec0ff */
/*0f90*/ IMAD.MOV.U32 R26, RZ, RZ, R20 ; /* 0x000000ffff1a7224 */
/* 0x001fe200078e0014 */
/*0fa0*/ @!P0 LOP3.LUT R26, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000091a8812 */
/* 0x000fe400078ec0ff */
/*0fb0*/ IADD3 R20, R25, -0x1, RZ ; /* 0xffffffff19147810 */
/* 0x000fe20007ffe0ff */
/*0fc0*/ DFMA R18, R16, -R8, 1 ; /* 0x3ff000001012742b */
/* 0x002e220000000808 */
/*0fd0*/ IADD3 R27, R26, -0x1, RZ ; /* 0xffffffff1a1b7810 */
/* 0x000fe40007ffe0ff */
/*0fe0*/ ISETP.GT.U32.AND P0, PT, R20, 0x7feffffe, PT ; /* 0x7feffffe1400780c */
/* 0x000fc60003f04070 */
/*0ff0*/ DFMA R16, R16, R18, R16 ; /* 0x000000121010722b */
/* 0x001e220000000010 */
/*1000*/ ISETP.GT.U32.OR P0, PT, R27, 0x7feffffe, P0 ; /* 0x7feffffe1b00780c */
/* 0x000fca0000704470 */
/*1010*/ DMUL R18, R16, R14 ; /* 0x0000000e10127228 */
/* 0x001e0c0000000000 */
/*1020*/ DFMA R20, R18, -R8, R14 ; /* 0x800000081214722b */
/* 0x001e0c000000000e */
/*1030*/ DFMA R20, R16, R20, R18 ; /* 0x000000141014722b */
/* 0x0010620000000012 */
/*1040*/ @P0 BRA 0x1210 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*1050*/ LOP3.LUT R16, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b107812 */
/* 0x001fc800078ec0ff */
/*1060*/ ISETP.GE.U32.AND P0, PT, R23.reuse, R16, PT ; /* 0x000000101700720c */
/* 0x040fe20003f06070 */
/*1070*/ IMAD.IADD R12, R23, 0x1, -R16 ; /* 0x00000001170c7824 */
/* 0x000fc600078e0a10 */
/*1080*/ SEL R13, R24, 0x63400000, !P0 ; /* 0x63400000180d7807 */
/* 0x000fe40004000000 */
/*1090*/ IMNMX R12, R12, -0x46a00000, !PT ; /* 0xb96000000c0c7817 */
/* 0x000fc80007800200 */
/*10a0*/ IMNMX R12, R12, 0x46a00000, PT ; /* 0x46a000000c0c7817 */
/* 0x000fca0003800200 */
/*10b0*/ IMAD.IADD R18, R12, 0x1, -R13 ; /* 0x000000010c127824 */
/* 0x000fe400078e0a0d */
/*10c0*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fc600078e00ff */
/*10d0*/ IADD3 R13, R18, 0x7fe00000, RZ ; /* 0x7fe00000120d7810 */
/* 0x000fcc0007ffe0ff */
/*10e0*/ DMUL R16, R20, R12 ; /* 0x0000000c14107228 */
/* 0x002e140000000000 */
/*10f0*/ FSETP.GTU.AND P0, PT, |R17|, 1.469367938527859385e-39, PT ; /* 0x001000001100780b */
/* 0x001fda0003f0c200 */
/*1100*/ @P0 BRA 0x1360 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*1110*/ DFMA R8, R20, -R8, R14 ; /* 0x800000081408722b */
/* 0x000e22000000000e */
/*1120*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fd200078e00ff */
/*1130*/ FSETP.NEU.AND P0, PT, R9.reuse, RZ, PT ; /* 0x000000ff0900720b */
/* 0x041fe40003f0d000 */
/*1140*/ LOP3.LUT R11, R9, 0x80000000, R11, 0x48, !PT ; /* 0x80000000090b7812 */
/* 0x000fc800078e480b */
/*1150*/ LOP3.LUT R13, R11, R13, RZ, 0xfc, !PT ; /* 0x0000000d0b0d7212 */
/* 0x000fce00078efcff */
/*1160*/ @!P0 BRA 0x1360 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*1170*/ IMAD.MOV R9, RZ, RZ, -R18 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a12 */
/*1180*/ DMUL.RP R12, R20, R12 ; /* 0x0000000c140c7228 */
/* 0x000e220000008000 */
/*1190*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fcc00078e00ff */
/*11a0*/ DFMA R8, R16, -R8, R20 ; /* 0x800000081008722b */
/* 0x000e460000000014 */
/*11b0*/ LOP3.LUT R11, R13, R11, RZ, 0x3c, !PT ; /* 0x0000000b0d0b7212 */
/* 0x001fc600078e3cff */
/*11c0*/ IADD3 R8, -R18, -0x43300000, RZ ; /* 0xbcd0000012087810 */
/* 0x002fc80007ffe1ff */
/*11d0*/ FSETP.NEU.AND P0, PT, |R9|, R8, PT ; /* 0x000000080900720b */
/* 0x000fc80003f0d200 */
/*11e0*/ FSEL R16, R12, R16, !P0 ; /* 0x000000100c107208 */
/* 0x000fe40004000000 */
/*11f0*/ FSEL R17, R11, R17, !P0 ; /* 0x000000110b117208 */
/* 0x000fe20004000000 */
/*1200*/ BRA 0x1360 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*1210*/ DSETP.NAN.AND P0, PT, R12, R12, PT ; /* 0x0000000c0c00722a */
/* 0x000e9c0003f08000 */
/*1220*/ @P0 BRA 0x1340 ; /* 0x0000011000000947 */
/* 0x004fea0003800000 */
/*1230*/ DSETP.NAN.AND P0, PT, R10, R10, PT ; /* 0x0000000a0a00722a */
/* 0x000e9c0003f08000 */
/*1240*/ @P0 BRA 0x1310 ; /* 0x000000c000000947 */
/* 0x004fea0003800000 */
/*1250*/ ISETP.NE.AND P0, PT, R25, R26, PT ; /* 0x0000001a1900720c */
/* 0x000fe20003f05270 */
/*1260*/ IMAD.MOV.U32 R16, RZ, RZ, 0x0 ; /* 0x00000000ff107424 */
/* 0x001fe400078e00ff */
/*1270*/ IMAD.MOV.U32 R17, RZ, RZ, -0x80000 ; /* 0xfff80000ff117424 */
/* 0x000fd400078e00ff */
/*1280*/ @!P0 BRA 0x1360 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*1290*/ ISETP.NE.AND P0, PT, R25, 0x7ff00000, PT ; /* 0x7ff000001900780c */
/* 0x000fe40003f05270 */
/*12a0*/ LOP3.LUT R17, R13, 0x80000000, R11, 0x48, !PT ; /* 0x800000000d117812 */
/* 0x000fe400078e480b */
/*12b0*/ ISETP.EQ.OR P0, PT, R26, RZ, !P0 ; /* 0x000000ff1a00720c */
/* 0x000fda0004702670 */
/*12c0*/ @P0 LOP3.LUT R8, R17, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000011080812 */
/* 0x000fe200078efcff */
/*12d0*/ @!P0 IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff108224 */
/* 0x000fe400078e00ff */
/*12e0*/ @P0 IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff100224 */
/* 0x000fe400078e00ff */
/*12f0*/ @P0 IMAD.MOV.U32 R17, RZ, RZ, R8 ; /* 0x000000ffff110224 */
/* 0x000fe200078e0008 */
/*1300*/ BRA 0x1360 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*1310*/ LOP3.LUT R17, R11, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000b117812 */
/* 0x001fe200078efcff */
/*1320*/ IMAD.MOV.U32 R16, RZ, RZ, R10 ; /* 0x000000ffff107224 */
/* 0x000fe200078e000a */
/*1330*/ BRA 0x1360 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*1340*/ LOP3.LUT R17, R13, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000d117812 */
/* 0x001fe200078efcff */
/*1350*/ IMAD.MOV.U32 R16, RZ, RZ, R12 ; /* 0x000000ffff107224 */
/* 0x000fe400078e000c */
/*1360*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*1370*/ IMAD.MOV.U32 R8, RZ, RZ, R0 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0000 */
/*1380*/ IMAD.MOV.U32 R9, RZ, RZ, 0x0 ; /* 0x00000000ff097424 */
/* 0x000fc800078e00ff */
/*1390*/ RET.REL.NODEC R8 0x0 ; /* 0xffffec6008007950 */
/* 0x000fea0003c3ffff */
/*13a0*/ BRA 0x13a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*13b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void cunnx_BlockSparse_updateGradOutput_kernel( float *_gradOutput, float* gradOutputScale, const float *gradOutput, const float *output, const float *outputScale, int outputWindowSize, int outputSize)
{
__shared__ float buffer[BLOCKSPARSE_THREADS];
int tx = threadIdx.x;
int i_step = blockDim.x;
int k = blockIdx.x;
float *_gradOutput_k = _gradOutput + k*outputWindowSize*outputSize;
float *gradOutputScale_k = gradOutputScale + k*outputWindowSize;
const float *gradOutput_k = gradOutput + k*outputWindowSize*outputSize;
const float *output_k = output + k*outputWindowSize*outputSize;
const float *outputScale_k = outputScale + k*outputWindowSize;
// get gradients for outputScale (to be backwarded to a Gater)
for (int m=0; m<outputWindowSize; m++)
{
float outputScale = outputScale_k[m];
float *_blockGradOutput = _gradOutput_k + m*outputSize;
const float *blockGradOutput = gradOutput_k + m*outputSize;
const float *blockOutput = output_k + m*outputSize;
buffer[tx] = 0;
for (int j=tx; j<outputSize; j+=i_step)
{
const float grad = blockGradOutput[j];
buffer[tx] += blockOutput[j]*grad;
_blockGradOutput[j] = grad*outputScale;
}
// add (reduce)
for (unsigned int stride = blockDim.x >> 1; stride > 0; stride >>= 1)
{
__syncthreads();
if (tx < stride)
buffer[tx] += buffer[tx+stride];
}
if (tx == 0)
gradOutputScale_k[m] = buffer[0]/(outputScale+0.00000001);
}
} | .file "tmpxft_00035039_00000000-6_cunnx_BlockSparse_updateGradOutput_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z74__device_stub__Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_iiPfS_PKfS1_S1_ii
.type _Z74__device_stub__Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_iiPfS_PKfS1_S1_ii, @function
_Z74__device_stub__Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_iiPfS_PKfS1_S1_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z74__device_stub__Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_iiPfS_PKfS1_S1_ii, .-_Z74__device_stub__Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_iiPfS_PKfS1_S1_ii
.globl _Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii
.type _Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii, @function
_Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z74__device_stub__Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_iiPfS_PKfS1_S1_ii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii, .-_Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void cunnx_BlockSparse_updateGradOutput_kernel( float *_gradOutput, float* gradOutputScale, const float *gradOutput, const float *output, const float *outputScale, int outputWindowSize, int outputSize)
{
__shared__ float buffer[BLOCKSPARSE_THREADS];
int tx = threadIdx.x;
int i_step = blockDim.x;
int k = blockIdx.x;
float *_gradOutput_k = _gradOutput + k*outputWindowSize*outputSize;
float *gradOutputScale_k = gradOutputScale + k*outputWindowSize;
const float *gradOutput_k = gradOutput + k*outputWindowSize*outputSize;
const float *output_k = output + k*outputWindowSize*outputSize;
const float *outputScale_k = outputScale + k*outputWindowSize;
// get gradients for outputScale (to be backwarded to a Gater)
for (int m=0; m<outputWindowSize; m++)
{
float outputScale = outputScale_k[m];
float *_blockGradOutput = _gradOutput_k + m*outputSize;
const float *blockGradOutput = gradOutput_k + m*outputSize;
const float *blockOutput = output_k + m*outputSize;
buffer[tx] = 0;
for (int j=tx; j<outputSize; j+=i_step)
{
const float grad = blockGradOutput[j];
buffer[tx] += blockOutput[j]*grad;
_blockGradOutput[j] = grad*outputScale;
}
// add (reduce)
for (unsigned int stride = blockDim.x >> 1; stride > 0; stride >>= 1)
{
__syncthreads();
if (tx < stride)
buffer[tx] += buffer[tx+stride];
}
if (tx == 0)
gradOutputScale_k[m] = buffer[0]/(outputScale+0.00000001);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cunnx_BlockSparse_updateGradOutput_kernel( float *_gradOutput, float* gradOutputScale, const float *gradOutput, const float *output, const float *outputScale, int outputWindowSize, int outputSize)
{
__shared__ float buffer[BLOCKSPARSE_THREADS];
int tx = threadIdx.x;
int i_step = blockDim.x;
int k = blockIdx.x;
float *_gradOutput_k = _gradOutput + k*outputWindowSize*outputSize;
float *gradOutputScale_k = gradOutputScale + k*outputWindowSize;
const float *gradOutput_k = gradOutput + k*outputWindowSize*outputSize;
const float *output_k = output + k*outputWindowSize*outputSize;
const float *outputScale_k = outputScale + k*outputWindowSize;
// get gradients for outputScale (to be backwarded to a Gater)
for (int m=0; m<outputWindowSize; m++)
{
float outputScale = outputScale_k[m];
float *_blockGradOutput = _gradOutput_k + m*outputSize;
const float *blockGradOutput = gradOutput_k + m*outputSize;
const float *blockOutput = output_k + m*outputSize;
buffer[tx] = 0;
for (int j=tx; j<outputSize; j+=i_step)
{
const float grad = blockGradOutput[j];
buffer[tx] += blockOutput[j]*grad;
_blockGradOutput[j] = grad*outputScale;
}
// add (reduce)
for (unsigned int stride = blockDim.x >> 1; stride > 0; stride >>= 1)
{
__syncthreads();
if (tx < stride)
buffer[tx] += buffer[tx+stride];
}
if (tx == 0)
gradOutputScale_k[m] = buffer[0]/(outputScale+0.00000001);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cunnx_BlockSparse_updateGradOutput_kernel( float *_gradOutput, float* gradOutputScale, const float *gradOutput, const float *output, const float *outputScale, int outputWindowSize, int outputSize)
{
__shared__ float buffer[BLOCKSPARSE_THREADS];
int tx = threadIdx.x;
int i_step = blockDim.x;
int k = blockIdx.x;
float *_gradOutput_k = _gradOutput + k*outputWindowSize*outputSize;
float *gradOutputScale_k = gradOutputScale + k*outputWindowSize;
const float *gradOutput_k = gradOutput + k*outputWindowSize*outputSize;
const float *output_k = output + k*outputWindowSize*outputSize;
const float *outputScale_k = outputScale + k*outputWindowSize;
// get gradients for outputScale (to be backwarded to a Gater)
for (int m=0; m<outputWindowSize; m++)
{
float outputScale = outputScale_k[m];
float *_blockGradOutput = _gradOutput_k + m*outputSize;
const float *blockGradOutput = gradOutput_k + m*outputSize;
const float *blockOutput = output_k + m*outputSize;
buffer[tx] = 0;
for (int j=tx; j<outputSize; j+=i_step)
{
const float grad = blockGradOutput[j];
buffer[tx] += blockOutput[j]*grad;
_blockGradOutput[j] = grad*outputScale;
}
// add (reduce)
for (unsigned int stride = blockDim.x >> 1; stride > 0; stride >>= 1)
{
__syncthreads();
if (tx < stride)
buffer[tx] += buffer[tx+stride];
}
if (tx == 0)
gradOutputScale_k[m] = buffer[0]/(outputScale+0.00000001);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii
.globl _Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii
.p2align 8
.type _Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii,@function
_Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii:
s_load_b32 s3, s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_13
s_clause 0x3
s_load_b32 s20, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x3c
s_load_b256 s[4:11], s[0:1], 0x0
s_load_b64 s[16:17], s[0:1], 0x20
s_mul_i32 s14, s15, s3
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 2, v0
s_ashr_i32 s15, s14, 31
v_cmp_eq_u32_e64 s0, 0, v0
s_lshl_b64 s[18:19], s[14:15], 2
s_mov_b32 s13, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s14, s14, s20
s_and_b32 s21, s2, 0xffff
s_ashr_i32 s15, s14, 31
s_add_u32 s22, s6, s18
s_addc_u32 s23, s7, s19
s_add_u32 s24, s16, s18
s_addc_u32 s25, s17, s19
s_cmp_gt_u32 s21, 1
v_cmp_gt_i32_e64 s1, s20, v0
s_cselect_b32 s26, -1, 0
s_lshl_b64 s[6:7], s[14:15], 2
s_lshl_b32 s12, s21, 2
v_add_co_u32 v3, s2, s6, v1
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, null, s7, 0, s2
s_mov_b64 s[6:7], s[12:13]
s_mov_b32 s15, 0x3e45798e
s_mov_b32 s14, 0xe2308c3a
s_mov_b32 s16, s13
s_mov_b32 s12, s13
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
s_add_i32 s12, s12, 1
s_add_i32 s16, s16, s20
s_cmp_eq_u32 s12, s3
s_cbranch_scc1 .LBB0_13
.LBB0_3:
s_lshl_b64 s[18:19], s[12:13], 2
ds_store_b32 v1, v2
s_add_u32 s28, s24, s18
s_addc_u32 s29, s25, s19
global_load_b32 v5, v2, s[28:29]
s_and_saveexec_b32 s27, s1
s_cbranch_execz .LBB0_7
ds_load_b32 v6, v1
s_ashr_i32 s17, s16, 31
v_mov_b32_e32 v9, v0
s_lshl_b64 s[28:29], s[16:17], 2
s_mov_b32 s17, 0
v_add_co_u32 v7, vcc_lo, v3, s28
v_add_co_ci_u32_e32 v8, vcc_lo, s29, v4, vcc_lo
.p2align 6
.LBB0_5:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, s8, v7
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v8, vcc_lo
v_add_co_u32 v12, vcc_lo, s10, v7
v_add_co_ci_u32_e32 v13, vcc_lo, s11, v8, vcc_lo
global_load_b32 v14, v[10:11], off
global_load_b32 v12, v[12:13], off
v_add_nc_u32_e32 v9, s21, v9
v_add_co_u32 v10, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v8, vcc_lo
v_add_co_u32 v7, vcc_lo, v7, s6
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
s_waitcnt vmcnt(0) lgkmcnt(0)
v_dual_mul_f32 v13, v5, v14 :: v_dual_fmac_f32 v6, v14, v12
v_cmp_le_i32_e64 s2, s20, v9
global_store_b32 v[10:11], v13, off
s_or_b32 s17, s2, s17
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s17
s_cbranch_execnz .LBB0_5
s_or_b32 exec_lo, exec_lo, s17
ds_store_b32 v1, v6
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s27
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s26
s_mov_b32 s2, s21
s_cbranch_vccz .LBB0_11
.LBB0_8:
s_and_saveexec_b32 s2, s0
s_cbranch_execz .LBB0_2
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[5:6], v5
ds_load_b32 v7, v2
s_add_u32 s18, s22, s18
s_addc_u32 s19, s23, s19
s_waitcnt lgkmcnt(0)
v_cvt_f64_f32_e32 v[7:8], v7
v_add_f64 v[5:6], v[5:6], s[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[9:10], null, v[5:6], v[5:6], v[7:8]
v_rcp_f64_e32 v[11:12], v[9:10]
s_waitcnt_depctr 0xfff
v_fma_f64 v[13:14], -v[9:10], v[11:12], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[11:12], v[11:12], v[13:14], v[11:12]
v_fma_f64 v[13:14], -v[9:10], v[11:12], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[11:12], v[11:12], v[13:14], v[11:12]
v_div_scale_f64 v[13:14], vcc_lo, v[7:8], v[5:6], v[7:8]
v_mul_f64 v[15:16], v[13:14], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], -v[9:10], v[15:16], v[13:14]
v_div_fmas_f64 v[9:10], v[9:10], v[11:12], v[15:16]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[5:6], v[9:10], v[5:6], v[7:8]
v_cvt_f32_f64_e32 v5, v[5:6]
global_store_b32 v2, v5, s[18:19]
s_branch .LBB0_2
.p2align 6
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s27
s_cmp_lt_u32 s2, 4
s_mov_b32 s2, s17
s_cbranch_scc1 .LBB0_8
.LBB0_11:
s_lshr_b32 s17, s2, 1
s_mov_b32 s27, exec_lo
s_waitcnt vmcnt(0) lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s17, v0
s_cbranch_execz .LBB0_10
v_add_lshl_u32 v6, s17, v0, 2
ds_load_b32 v6, v6
ds_load_b32 v7, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v6, v6, v7
ds_store_b32 v1, v6
s_branch .LBB0_10
.LBB0_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii
.amdhsa_group_segment_fixed_size 128
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 30
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii, .Lfunc_end0-_Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 128
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii
.private_segment_fixed_size: 0
.sgpr_count: 32
.sgpr_spill_count: 0
.symbol: _Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cunnx_BlockSparse_updateGradOutput_kernel( float *_gradOutput, float* gradOutputScale, const float *gradOutput, const float *output, const float *outputScale, int outputWindowSize, int outputSize)
{
__shared__ float buffer[BLOCKSPARSE_THREADS];
int tx = threadIdx.x;
int i_step = blockDim.x;
int k = blockIdx.x;
float *_gradOutput_k = _gradOutput + k*outputWindowSize*outputSize;
float *gradOutputScale_k = gradOutputScale + k*outputWindowSize;
const float *gradOutput_k = gradOutput + k*outputWindowSize*outputSize;
const float *output_k = output + k*outputWindowSize*outputSize;
const float *outputScale_k = outputScale + k*outputWindowSize;
// get gradients for outputScale (to be backwarded to a Gater)
for (int m=0; m<outputWindowSize; m++)
{
float outputScale = outputScale_k[m];
float *_blockGradOutput = _gradOutput_k + m*outputSize;
const float *blockGradOutput = gradOutput_k + m*outputSize;
const float *blockOutput = output_k + m*outputSize;
buffer[tx] = 0;
for (int j=tx; j<outputSize; j+=i_step)
{
const float grad = blockGradOutput[j];
buffer[tx] += blockOutput[j]*grad;
_blockGradOutput[j] = grad*outputScale;
}
// add (reduce)
for (unsigned int stride = blockDim.x >> 1; stride > 0; stride >>= 1)
{
__syncthreads();
if (tx < stride)
buffer[tx] += buffer[tx+stride];
}
if (tx == 0)
gradOutputScale_k[m] = buffer[0]/(outputScale+0.00000001);
}
} | .text
.file "cunnx_BlockSparse_updateGradOutput_kernel.hip"
.globl _Z56__device_stub__cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii # -- Begin function _Z56__device_stub__cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii
.p2align 4, 0x90
.type _Z56__device_stub__cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii,@function
_Z56__device_stub__cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii: # @_Z56__device_stub__cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z56__device_stub__cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii, .Lfunc_end0-_Z56__device_stub__cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii,@object # @_Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii
.section .rodata,"a",@progbits
.globl _Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii
.p2align 3, 0x0
_Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii:
.quad _Z56__device_stub__cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii
.size _Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii"
.size .L__unnamed_1, 61
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z56__device_stub__cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00035039_00000000-6_cunnx_BlockSparse_updateGradOutput_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z74__device_stub__Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_iiPfS_PKfS1_S1_ii
.type _Z74__device_stub__Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_iiPfS_PKfS1_S1_ii, @function
_Z74__device_stub__Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_iiPfS_PKfS1_S1_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z74__device_stub__Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_iiPfS_PKfS1_S1_ii, .-_Z74__device_stub__Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_iiPfS_PKfS1_S1_ii
.globl _Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii
.type _Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii, @function
_Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z74__device_stub__Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_iiPfS_PKfS1_S1_ii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii, .-_Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cunnx_BlockSparse_updateGradOutput_kernel.hip"
.globl _Z56__device_stub__cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii # -- Begin function _Z56__device_stub__cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii
.p2align 4, 0x90
.type _Z56__device_stub__cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii,@function
_Z56__device_stub__cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii: # @_Z56__device_stub__cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z56__device_stub__cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii, .Lfunc_end0-_Z56__device_stub__cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii,@object # @_Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii
.section .rodata,"a",@progbits
.globl _Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii
.p2align 3, 0x0
_Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii:
.quad _Z56__device_stub__cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii
.size _Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii"
.size .L__unnamed_1, 61
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z56__device_stub__cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z41cunnx_BlockSparse_updateGradOutput_kernelPfS_PKfS1_S1_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <numeric>
#include <stdlib.h>
#include <stdio.h>
typedef struct{
int width;
int height;
float* elements;
} Matrix;
#define BLOCK_SIZE 3
__global__ void MatMulKernel(const Matrix, const Matrix, Matrix);
void MatMul(const Matrix A, const Matrix B, Matrix C)
{
Matrix d_A;
d_A.width = A.width; d_A.height = A.height;
size_t size = A.width*A.height*sizeof(float);
//allocate memory for matrix A on device
cudaMalloc(&d_A.elements,size);
//copy matrix A elements to memory allocated on device
cudaMemcpy(d_A.elements, A.elements,size,cudaMemcpyHostToDevice);
//do the same thing for matrix B
Matrix d_B;
d_B.width = B.width; d_B.height = B.height;
//allocate memory for matrix B on device
cudaMalloc(&d_B.elements,size);
//copy matrix B elements to memory allocated on device
cudaMemcpy(d_B.elements, B.elements,size,cudaMemcpyHostToDevice);
//allocate memory for matrix C on device - obviously nothing to copy
Matrix d_C;
d_C.width = C.width; d_C.height = C.height;
cudaMalloc(&d_C.elements,size);
//define block size and grid size for kernel
dim3 dimBlock(1,3);
//dim3 dimGrid(B.width/dimBlock.x,A.height/dimBlock.y);
//invoke kernel
MatMulKernel<<<3, dimBlock>>>(d_A, d_B, d_C);
//read matrix multiplication result from device
cudaMemcpy(C.elements, d_C.elements, size, cudaMemcpyDeviceToHost);
//Free device memory
cudaFree(d_A.elements);
cudaFree(d_B.elements);
cudaFree(d_C.elements);
}
//The ACTUAL kernel that performs matrix multiplication in the GPU
__global__ void MatMulKernel(Matrix A, Matrix B, Matrix C)
{
//each kernel thread computes one element of C
float Cvalue=0;
//therefore, each thread is needs to read the row of A and column of B for its element of C.
//reading from global memory here - would be better if the row and column were stored in shared memory
int row = blockIdx.y*blockDim.y+threadIdx.y;
int col = blockIdx.x*blockDim.x+threadIdx.x;
for (int e = 0; e < A.width; ++e)
Cvalue += A.elements[row * A.width + e]* B.elements[e * B.width + col];
C.elements[row * C.width + col] = Cvalue;
}
int main(void)
{
float *a_els = new float[9];
for(int i = 0; i<9; ++i)
a_els[i]=2.0;
float *b_els = new float[9];
for(int i = 0; i<9; ++i)
b_els[i]=2.0;
Matrix m_a;
m_a.height=3;
m_a.width=3;
m_a.elements = a_els;
Matrix m_b;
m_b.height=3;
m_b.width=3;
m_b.elements = a_els;
float *c_els=new float[9];
Matrix m_c;
m_c.height = 3;
m_c.width = 3;
m_c.elements=c_els;
MatMul(m_a,m_b,m_c);
for(int i =0; i<9;i++)
printf("%f \n",m_c.elements[i]);
delete[] a_els;
delete[] b_els;
delete[] c_els;
return 0;
} | code for sm_80
Function : _Z12MatMulKernel6MatrixS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0080*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fe400078e0203 */
/*00a0*/ IMAD R3, R2, c[0x0][0x0], R5 ; /* 0x0000000002037a24 */
/* 0x002fc600078e0205 */
/*00b0*/ @!P0 BRA 0xc10 ; /* 0x00000b5000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R4.reuse, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x040fe40007ffe0ff */
/*00d0*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe400078ec0ff */
/*00e0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*00f0*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fe40000000f00 */
/*0100*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fd20000000f00 */
/*0110*/ @!P0 BRA 0xb00 ; /* 0x000009e000008947 */
/* 0x000fea0003800000 */
/*0120*/ IADD3 R5, -R4, c[0x0][0x160], RZ ; /* 0x0000580004057a10 */
/* 0x000fe20007ffe1ff */
/*0130*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0140*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0150*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe200000001ff */
/*0160*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f04270 */
/*0170*/ IMAD R6, R0, c[0x0][0x160], RZ ; /* 0x0000580000067a24 */
/* 0x000fe200078e02ff */
/*0180*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fca0000000f00 */
/*0190*/ IMAD.WIDE R8, R3, R8, c[0x0][0x178] ; /* 0x00005e0003087625 */
/* 0x000fcc00078e0208 */
/*01a0*/ @!P0 BRA 0x960 ; /* 0x000007b000008947 */
/* 0x000fea0003800000 */
/*01b0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01d0*/ @!P1 BRA 0x690 ; /* 0x000004b000009947 */
/* 0x000fea0003800000 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01f0*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0200*/ LDG.E R21, [R8.64] ; /* 0x0000000408157981 */
/* 0x0000a2000c1e1900 */
/*0210*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0220*/ IMAD.WIDE R12, R6, 0x4, R12 ; /* 0x00000004060c7825 */
/* 0x000fca00078e020c */
/*0230*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x000ea2000c1e1900 */
/*0240*/ MOV R7, c[0x0][0x170] ; /* 0x00005c0000077a02 */
/* 0x000fc60000000f00 */
/*0250*/ LDG.E R14, [R12.64+0x4] ; /* 0x000004040c0e7981 */
/* 0x000ee4000c1e1900 */
/*0260*/ IMAD.WIDE R10, R7.reuse, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x040fe400078e0208 */
/*0270*/ LDG.E R27, [R12.64+0x8] ; /* 0x000008040c1b7981 */
/* 0x000f28000c1e1900 */
/*0280*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x0002e2000c1e1900 */
/*0290*/ IMAD.WIDE R22, R7, 0x4, R10 ; /* 0x0000000407167825 */
/* 0x000fc600078e020a */
/*02a0*/ LDG.E R18, [R12.64+0xc] ; /* 0x00000c040c127981 */
/* 0x000f66000c1e1900 */
/*02b0*/ IMAD.WIDE R28, R7.reuse, 0x4, R22 ; /* 0x00000004071c7825 */
/* 0x040fe200078e0216 */
/*02c0*/ LDG.E R26, [R22.64] ; /* 0x00000004161a7981 */
/* 0x000328000c1e1900 */
/*02d0*/ LDG.E R19, [R28.64] ; /* 0x000000041c137981 */
/* 0x000362000c1e1900 */
/*02e0*/ IMAD.WIDE R16, R7, 0x4, R28 ; /* 0x0000000407107825 */
/* 0x000fc600078e021c */
/*02f0*/ LDG.E R8, [R12.64+0x10] ; /* 0x000010040c087981 */
/* 0x001f68000c1e1900 */
/*0300*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000168000c1e1900 */
/*0310*/ LDG.E R10, [R12.64+0x14] ; /* 0x000014040c0a7981 */
/* 0x002f68000c1e1900 */
/*0320*/ LDG.E R28, [R12.64+0x1c] ; /* 0x00001c040c1c7981 */
/* 0x000f62000c1e1900 */
/*0330*/ IMAD.WIDE R16, R7, 0x4, R16 ; /* 0x0000000407107825 */
/* 0x001fca00078e0210 */
/*0340*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x000562000c1e1900 */
/*0350*/ IMAD.WIDE R22, R7, 0x4, R16 ; /* 0x0000000407167825 */
/* 0x000fc800078e0210 */
/*0360*/ FFMA R16, R21, R20, R24 ; /* 0x0000001415107223 */
/* 0x004fe40000000018 */
/*0370*/ LDG.E R20, [R12.64+0x18] ; /* 0x000018040c147981 */
/* 0x000ea2000c1e1900 */
/*0380*/ IMAD.WIDE R24, R7, 0x4, R22 ; /* 0x0000000407187825 */
/* 0x000fc600078e0216 */
/*0390*/ LDG.E R21, [R22.64] ; /* 0x0000000416157981 */
/* 0x0000a8000c1e1900 */
/*03a0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0002a2000c1e1900 */
/*03b0*/ FFMA R16, R15, R14, R16 ; /* 0x0000000e0f107223 */
/* 0x008fe40000000010 */
/*03c0*/ IMAD.WIDE R14, R7.reuse, 0x4, R24 ; /* 0x00000004070e7825 */
/* 0x040fe200078e0218 */
/*03d0*/ LDG.E R23, [R12.64+0x20] ; /* 0x000020040c177981 */
/* 0x001ee6000c1e1900 */
/*03e0*/ FFMA R26, R26, R27, R16 ; /* 0x0000001b1a1a7223 */
/* 0x010fe20000000010 */
/*03f0*/ LDG.E R25, [R12.64+0x24] ; /* 0x000024040c197981 */
/* 0x002f22000c1e1900 */
/*0400*/ IMAD.WIDE R16, R7, 0x4, R14 ; /* 0x0000000407107825 */
/* 0x000fc600078e020e */
/*0410*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0000e2000c1e1900 */
/*0420*/ FFMA R26, R19, R18, R26 ; /* 0x00000012131a7223 */
/* 0x020fe4000000001a */
/*0430*/ IMAD.WIDE R18, R7, 0x4, R16 ; /* 0x0000000407127825 */
/* 0x000fe200078e0210 */
/*0440*/ LDG.E R22, [R12.64+0x28] ; /* 0x000028040c167981 */
/* 0x000f66000c1e1900 */
/*0450*/ FFMA R26, R9, R8, R26 ; /* 0x00000008091a7223 */
/* 0x000fe2000000001a */
/*0460*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000322000c1e1900 */
/*0470*/ IMAD.WIDE R8, R7, 0x4, R18 ; /* 0x0000000407087825 */
/* 0x000fc600078e0212 */
/*0480*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000368000c1e1900 */
/*0490*/ LDG.E R24, [R8.64] ; /* 0x0000000408187981 */
/* 0x000568000c1e1900 */
/*04a0*/ LDG.E R15, [R12.64+0x2c] ; /* 0x00002c040c0f7981 */
/* 0x001f62000c1e1900 */
/*04b0*/ FFMA R26, R11, R10, R26 ; /* 0x0000000a0b1a7223 */
/* 0x000fe4000000001a */
/*04c0*/ IMAD.WIDE R10, R7, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x000fe200078e0208 */
/*04d0*/ LDG.E R17, [R12.64+0x30] ; /* 0x000030040c117981 */
/* 0x002f66000c1e1900 */
/*04e0*/ FFMA R26, R21, R20, R26 ; /* 0x00000014151a7223 */
/* 0x004fc4000000001a */
/*04f0*/ IMAD.WIDE R20, R7, 0x4, R10 ; /* 0x0000000407147825 */
/* 0x000fe400078e020a */
/*0500*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x0000a4000c1e1900 */
/*0510*/ FFMA R28, R29, R28, R26 ; /* 0x0000001c1d1c7223 */
/* 0x000fe4000000001a */
/*0520*/ IMAD.WIDE R26, R7.reuse, 0x4, R20 ; /* 0x00000004071a7825 */
/* 0x040fe200078e0214 */
/*0530*/ LDG.E R29, [R12.64+0x34] ; /* 0x000034040c1d7981 */
/* 0x000ea8000c1e1900 */
/*0540*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x0002a2000c1e1900 */
/*0550*/ IMAD.WIDE R8, R7, 0x4, R26 ; /* 0x0000000407087825 */
/* 0x000fc600078e021a */
/*0560*/ LDG.E R19, [R26.64] ; /* 0x000000041a137981 */
/* 0x0006a8000c1e1900 */
/*0570*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0010a8000c1e1900 */
/*0580*/ LDG.E R21, [R12.64+0x38] ; /* 0x000038040c157981 */
/* 0x002ea8000c1e1900 */
/*0590*/ LDG.E R26, [R12.64+0x3c] ; /* 0x00003c040c1a7981 */
/* 0x008ee2000c1e1900 */
/*05a0*/ FFMA R14, R14, R23, R28 ; /* 0x000000170e0e7223 */
/* 0x000fc8000000001c */
/*05b0*/ FFMA R25, R16, R25, R14 ; /* 0x0000001910197223 */
/* 0x010fe2000000000e */
/*05c0*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fc60007ffe0ff */
/*05d0*/ FFMA R18, R18, R22, R25 ; /* 0x0000001612127223 */
/* 0x020fe20000000019 */
/*05e0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fc60003f24270 */
/*05f0*/ FFMA R15, R24, R15, R18 ; /* 0x0000000f180f7223 */
/* 0x000fe20000000012 */
/*0600*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0610*/ IMAD.WIDE R8, R7, 0x4, R8 ; /* 0x0000000407087825 */
/* 0x001fc600078e0208 */
/*0620*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0630*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe20007ffe0ff */
/*0640*/ FFMA R10, R10, R17, R15 ; /* 0x000000110a0a7223 */
/* 0x004fc8000000000f */
/*0650*/ FFMA R10, R20, R29, R10 ; /* 0x0000001d140a7223 */
/* 0x000fc8000000000a */
/*0660*/ FFMA R10, R19, R21, R10 ; /* 0x00000015130a7223 */
/* 0x000fc8000000000a */
/*0670*/ FFMA R24, R11, R26, R10 ; /* 0x0000001a0b187223 */
/* 0x008fe2000000000a */
/*0680*/ @P1 BRA 0x1f0 ; /* 0xfffffb6000001947 */
/* 0x000fea000383ffff */
/*0690*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*06a0*/ @!P1 BRA 0x940 ; /* 0x0000029000009947 */
/* 0x000fea0003800000 */
/*06b0*/ MOV R7, c[0x0][0x170] ; /* 0x00005c0000077a02 */
/* 0x000fe20000000f00 */
/*06c0*/ LDG.E R23, [R8.64] ; /* 0x0000000408177981 */
/* 0x0000a2000c1e1900 */
/*06d0*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*06e0*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe20008000f00 */
/*06f0*/ IMAD.WIDE R16, R7, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x000fc800078e0208 */
/*0700*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*0710*/ IMAD.WIDE R12, R7.reuse, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x040fe200078e0210 */
/*0720*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x000ea8000c1e1900 */
/*0730*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0002e2000c1e1900 */
/*0740*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0750*/ LDG.E R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000ee6000c1e1900 */
/*0760*/ IMAD.WIDE R18, R7.reuse, 0x4, R14 ; /* 0x0000000407127825 */
/* 0x040fe200078e020e */
/*0770*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000968000c1e1900 */
/*0780*/ LDG.E R27, [R10.64+0x8] ; /* 0x000008040a1b7981 */
/* 0x000f62000c1e1900 */
/*0790*/ IMAD.WIDE R20, R7, 0x4, R18 ; /* 0x0000000407147825 */
/* 0x000fc600078e0212 */
/*07a0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07b0*/ LDG.E R29, [R10.64+0xc] ; /* 0x00000c040a1d7981 */
/* 0x000f62000c1e1900 */
/*07c0*/ IMAD.WIDE R8, R7, 0x4, R20 ; /* 0x0000000407087825 */
/* 0x001fc600078e0214 */
/*07d0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000168000c1e1900 */
/*07e0*/ LDG.E R28, [R10.64+0x10] ; /* 0x000010040a1c7981 */
/* 0x000f62000c1e1900 */
/*07f0*/ IMAD.WIDE R12, R7, 0x4, R8 ; /* 0x00000004070c7825 */
/* 0x010fc600078e0208 */
/*0800*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000968000c1e1900 */
/*0810*/ LDG.E R15, [R10.64+0x14] ; /* 0x000014040a0f7981 */
/* 0x002f68000c1e1900 */
/*0820*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000368000c1e1900 */
/*0830*/ LDG.E R21, [R10.64+0x1c] ; /* 0x00001c040a157981 */
/* 0x010f28000c1e1900 */
/*0840*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x001f28000c1e1900 */
/*0850*/ LDG.E R8, [R10.64+0x18] ; /* 0x000018040a087981 */
/* 0x002f22000c1e1900 */
/*0860*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0870*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0880*/ IADD3 R2, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fe40007ffe0ff */
/*0890*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe20007ffe0ff */
/*08a0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08b0*/ FFMA R22, R23, R22, R24 ; /* 0x0000001617167223 */
/* 0x004fc80000000018 */
/*08c0*/ FFMA R16, R16, R25, R22 ; /* 0x0000001910107223 */
/* 0x008fc80000000016 */
/*08d0*/ FFMA R16, R26, R27, R16 ; /* 0x0000001b1a107223 */
/* 0x020fc80000000010 */
/*08e0*/ FFMA R29, R14, R29, R16 ; /* 0x0000001d0e1d7223 */
/* 0x000fc80000000010 */
/*08f0*/ FFMA R18, R18, R28, R29 ; /* 0x0000001c12127223 */
/* 0x000fc8000000001d */
/*0900*/ FFMA R15, R20, R15, R18 ; /* 0x0000000f140f7223 */
/* 0x000fc80000000012 */
/*0910*/ FFMA R24, R17, R8, R15 ; /* 0x0000000811187223 */
/* 0x010fe4000000000f */
/*0920*/ IMAD.WIDE R8, R7, 0x4, R12 ; /* 0x0000000407087825 */
/* 0x000fc800078e020c */
/*0930*/ FFMA R24, R19, R21, R24 ; /* 0x0000001513187223 */
/* 0x000fe40000000018 */
/*0940*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0950*/ @!P0 BRA 0xb00 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0960*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*0970*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe40008000f00 */
/*0980*/ MOV R7, c[0x0][0x170] ; /* 0x00005c0000077a02 */
/* 0x000fc60000000f00 */
/*0990*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*09a0*/ IMAD.WIDE R16, R7.reuse, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x040fe200078e0208 */
/*09b0*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000ea8000c1e1900 */
/*09c0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*09d0*/ IMAD.WIDE R12, R7, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x000fc600078e0210 */
/*09e0*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ee8000c1e1900 */
/*09f0*/ LDG.E R19, [R10.64+0x4] ; /* 0x000004040a137981 */
/* 0x000ee2000c1e1900 */
/*0a00*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0a10*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R20, [R10.64+0x8] ; /* 0x000008040a147981 */
/* 0x000f28000c1e1900 */
/*0a30*/ LDG.E R22, [R10.64+0xc] ; /* 0x00000c040a167981 */
/* 0x000f68000c1e1900 */
/*0a40*/ LDG.E R23, [R14.64] ; /* 0x000000040e177981 */
/* 0x000f62000c1e1900 */
/*0a50*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0a70*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a80*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fc60007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ FFMA R18, R9, R18, R24 ; /* 0x0000001209127223 */
/* 0x004fc80000000018 */
/*0ab0*/ FFMA R18, R17, R19, R18 ; /* 0x0000001311127223 */
/* 0x008fe40000000012 */
/*0ac0*/ IMAD.WIDE R8, R7, 0x4, R14 ; /* 0x0000000407087825 */
/* 0x000fc800078e020e */
/*0ad0*/ FFMA R18, R21, R20, R18 ; /* 0x0000001415127223 */
/* 0x010fc80000000012 */
/*0ae0*/ FFMA R24, R23, R22, R18 ; /* 0x0000001617187223 */
/* 0x020fe20000000012 */
/*0af0*/ @P0 BRA 0x960 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*0b00*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0b10*/ @!P0 BRA 0xc10 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0b20*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b30*/ IMAD R6, R0, c[0x0][0x160], R2 ; /* 0x0000580000067a24 */
/* 0x000fe400078e0202 */
/*0b40*/ IMAD R2, R2, c[0x0][0x170], R3 ; /* 0x00005c0002027a24 */
/* 0x000fce00078e0203 */
/*0b50*/ IMAD.WIDE R6, R6, R9, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc800078e0209 */
/*0b60*/ IMAD.WIDE R8, R2, R9, c[0x0][0x178] ; /* 0x00005e0002087625 */
/* 0x000fca00078e0209 */
/*0b70*/ LDG.E R5, [R8.64] ; /* 0x0000000408057981 */
/* 0x0000a8000c1e1900 */
/*0b80*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x0002a2000c1e1900 */
/*0b90*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0ba0*/ MOV R11, c[0x0][0x170] ; /* 0x00005c00000b7a02 */
/* 0x000fe40000000f00 */
/*0bb0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*0bc0*/ IMAD.WIDE R8, R11, 0x4, R8 ; /* 0x000000040b087825 */
/* 0x001fe200078e0208 */
/*0bd0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0be0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0bf0*/ FFMA R24, R5, R2, R24 ; /* 0x0000000205187223 */
/* 0x004fc80000000018 */
/*0c00*/ @P0 BRA 0xb70 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0c10*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0c20*/ IMAD R3, R0, c[0x0][0x180], R3 ; /* 0x0000600000037a24 */
/* 0x000fc800078e0203 */
/*0c30*/ IMAD.WIDE R2, R3, R2, c[0x0][0x188] ; /* 0x0000620003027625 */
/* 0x000fca00078e0202 */
/*0c40*/ STG.E [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x000fe2000c101904 */
/*0c50*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c60*/ BRA 0xc60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <numeric>
#include <stdlib.h>
#include <stdio.h>
typedef struct{
int width;
int height;
float* elements;
} Matrix;
#define BLOCK_SIZE 3
__global__ void MatMulKernel(const Matrix, const Matrix, Matrix);
void MatMul(const Matrix A, const Matrix B, Matrix C)
{
Matrix d_A;
d_A.width = A.width; d_A.height = A.height;
size_t size = A.width*A.height*sizeof(float);
//allocate memory for matrix A on device
cudaMalloc(&d_A.elements,size);
//copy matrix A elements to memory allocated on device
cudaMemcpy(d_A.elements, A.elements,size,cudaMemcpyHostToDevice);
//do the same thing for matrix B
Matrix d_B;
d_B.width = B.width; d_B.height = B.height;
//allocate memory for matrix B on device
cudaMalloc(&d_B.elements,size);
//copy matrix B elements to memory allocated on device
cudaMemcpy(d_B.elements, B.elements,size,cudaMemcpyHostToDevice);
//allocate memory for matrix C on device - obviously nothing to copy
Matrix d_C;
d_C.width = C.width; d_C.height = C.height;
cudaMalloc(&d_C.elements,size);
//define block size and grid size for kernel
dim3 dimBlock(1,3);
//dim3 dimGrid(B.width/dimBlock.x,A.height/dimBlock.y);
//invoke kernel
MatMulKernel<<<3, dimBlock>>>(d_A, d_B, d_C);
//read matrix multiplication result from device
cudaMemcpy(C.elements, d_C.elements, size, cudaMemcpyDeviceToHost);
//Free device memory
cudaFree(d_A.elements);
cudaFree(d_B.elements);
cudaFree(d_C.elements);
}
//The ACTUAL kernel that performs matrix multiplication in the GPU
__global__ void MatMulKernel(Matrix A, Matrix B, Matrix C)
{
//each kernel thread computes one element of C
float Cvalue=0;
//therefore, each thread is needs to read the row of A and column of B for its element of C.
//reading from global memory here - would be better if the row and column were stored in shared memory
int row = blockIdx.y*blockDim.y+threadIdx.y;
int col = blockIdx.x*blockDim.x+threadIdx.x;
for (int e = 0; e < A.width; ++e)
Cvalue += A.elements[row * A.width + e]* B.elements[e * B.width + col];
C.elements[row * C.width + col] = Cvalue;
}
int main(void)
{
float *a_els = new float[9];
for(int i = 0; i<9; ++i)
a_els[i]=2.0;
float *b_els = new float[9];
for(int i = 0; i<9; ++i)
b_els[i]=2.0;
Matrix m_a;
m_a.height=3;
m_a.width=3;
m_a.elements = a_els;
Matrix m_b;
m_b.height=3;
m_b.width=3;
m_b.elements = a_els;
float *c_els=new float[9];
Matrix m_c;
m_c.height = 3;
m_c.width = 3;
m_c.elements=c_els;
MatMul(m_a,m_b,m_c);
for(int i =0; i<9;i++)
printf("%f \n",m_c.elements[i]);
delete[] a_els;
delete[] b_els;
delete[] c_els;
return 0;
} | .file "tmpxft_0019d95c_00000000-6_cuda-linear-algebra.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3712:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3712:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_
.type _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_, @function
_Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_:
.LFB3734:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq %rdi, 64(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 80(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 120
pushq 8(%rsp)
.cfi_def_cfa_offset 128
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z12MatMulKernel6MatrixS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3734:
.size _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_, .-_Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_
.globl _Z12MatMulKernel6MatrixS_S_
.type _Z12MatMulKernel6MatrixS_S_, @function
_Z12MatMulKernel6MatrixS_S_:
.LFB3735:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %rdi, 32(%rsp)
movq %rsi, 40(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 24(%rsp)
movq %r8, (%rsp)
movq %r9, 8(%rsp)
movq %rsp, %rdx
leaq 16(%rsp), %rsi
leaq 32(%rsp), %rdi
call _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3735:
.size _Z12MatMulKernel6MatrixS_S_, .-_Z12MatMulKernel6MatrixS_S_
.globl _Z6MatMul6MatrixS_S_
.type _Z6MatMul6MatrixS_S_, @function
_Z6MatMul6MatrixS_S_:
.LFB3708:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %rsi, %r15
movq %rdx, %r12
movq %rcx, %r14
movq %r8, %rbp
movq %r9, %r13
movq %fs:40, %rdx
movq %rdx, 136(%rsp)
xorl %edx, %edx
movq %rdi, %rbx
sarq $32, %rbx
movl %edi, 32(%rsp)
movl %ebx, 36(%rsp)
imull %edi, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r15, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %r12d, 48(%rsp)
sarq $32, %r12
movl %r12d, 52(%rsp)
leaq 56(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl %ebp, 64(%rsp)
sarq $32, %rbp
movl %ebp, 68(%rsp)
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, 8(%rsp)
movl $3, 12(%rsp)
movl $3, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movq %rbx, %rdx
movq 72(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movdqa 32(%rsp), %xmm0
movaps %xmm0, 80(%rsp)
movdqa 48(%rsp), %xmm1
movaps %xmm1, 96(%rsp)
movdqa 64(%rsp), %xmm2
movaps %xmm2, 112(%rsp)
leaq 112(%rsp), %rdx
leaq 96(%rsp), %rsi
leaq 80(%rsp), %rdi
call _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3708:
.size _Z6MatMul6MatrixS_S_, .-_Z6MatMul6MatrixS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%f \n"
.text
.globl main
.type main, @function
main:
.LFB3709:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movl $36, %edi
call _Znam@PLT
movq %rax, %r13
leaq 36(%rax), %rdx
movss .LC0(%rip), %xmm0
.L18:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L18
movl $36, %edi
call _Znam@PLT
movq %rax, %r14
leaq 36(%rax), %rdx
movss .LC0(%rip), %xmm0
.L19:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L19
movabsq $12884901888, %rbx
movq %rbx, %rbp
orq $3, %rbp
movl $36, %edi
call _Znam@PLT
movq %rax, %r15
movq %rbp, %r8
movq %rax, %r9
movq %rbp, %rdx
movq %r13, %rcx
movq %rbp, %rdi
movq %r13, %rsi
call _Z6MatMul6MatrixS_S_
movq %r15, %rbx
leaq 36(%r15), %r12
leaq .LC1(%rip), %rbp
.L20:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L20
movq %r13, %rdi
call _ZdaPv@PLT
movq %r14, %rdi
call _ZdaPv@PLT
movq %r15, %rdi
call _ZdaPv@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3709:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z12MatMulKernel6MatrixS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3737:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z12MatMulKernel6MatrixS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3737:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <numeric>
#include <stdlib.h>
#include <stdio.h>
typedef struct{
int width;
int height;
float* elements;
} Matrix;
#define BLOCK_SIZE 3
__global__ void MatMulKernel(const Matrix, const Matrix, Matrix);
void MatMul(const Matrix A, const Matrix B, Matrix C)
{
Matrix d_A;
d_A.width = A.width; d_A.height = A.height;
size_t size = A.width*A.height*sizeof(float);
//allocate memory for matrix A on device
cudaMalloc(&d_A.elements,size);
//copy matrix A elements to memory allocated on device
cudaMemcpy(d_A.elements, A.elements,size,cudaMemcpyHostToDevice);
//do the same thing for matrix B
Matrix d_B;
d_B.width = B.width; d_B.height = B.height;
//allocate memory for matrix B on device
cudaMalloc(&d_B.elements,size);
//copy matrix B elements to memory allocated on device
cudaMemcpy(d_B.elements, B.elements,size,cudaMemcpyHostToDevice);
//allocate memory for matrix C on device - obviously nothing to copy
Matrix d_C;
d_C.width = C.width; d_C.height = C.height;
cudaMalloc(&d_C.elements,size);
//define block size and grid size for kernel
dim3 dimBlock(1,3);
//dim3 dimGrid(B.width/dimBlock.x,A.height/dimBlock.y);
//invoke kernel
MatMulKernel<<<3, dimBlock>>>(d_A, d_B, d_C);
//read matrix multiplication result from device
cudaMemcpy(C.elements, d_C.elements, size, cudaMemcpyDeviceToHost);
//Free device memory
cudaFree(d_A.elements);
cudaFree(d_B.elements);
cudaFree(d_C.elements);
}
//The ACTUAL kernel that performs matrix multiplication in the GPU
__global__ void MatMulKernel(Matrix A, Matrix B, Matrix C)
{
//each kernel thread computes one element of C
float Cvalue=0;
//therefore, each thread is needs to read the row of A and column of B for its element of C.
//reading from global memory here - would be better if the row and column were stored in shared memory
int row = blockIdx.y*blockDim.y+threadIdx.y;
int col = blockIdx.x*blockDim.x+threadIdx.x;
for (int e = 0; e < A.width; ++e)
Cvalue += A.elements[row * A.width + e]* B.elements[e * B.width + col];
C.elements[row * C.width + col] = Cvalue;
}
int main(void)
{
float *a_els = new float[9];
for(int i = 0; i<9; ++i)
a_els[i]=2.0;
float *b_els = new float[9];
for(int i = 0; i<9; ++i)
b_els[i]=2.0;
Matrix m_a;
m_a.height=3;
m_a.width=3;
m_a.elements = a_els;
Matrix m_b;
m_b.height=3;
m_b.width=3;
m_b.elements = a_els;
float *c_els=new float[9];
Matrix m_c;
m_c.height = 3;
m_c.width = 3;
m_c.elements=c_els;
MatMul(m_a,m_b,m_c);
for(int i =0; i<9;i++)
printf("%f \n",m_c.elements[i]);
delete[] a_els;
delete[] b_els;
delete[] c_els;
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <numeric>
#include <stdlib.h>
#include <stdio.h>
typedef struct{
int width;
int height;
float* elements;
} Matrix;
#define BLOCK_SIZE 3
__global__ void MatMulKernel(const Matrix, const Matrix, Matrix);
void MatMul(const Matrix A, const Matrix B, Matrix C)
{
Matrix d_A;
d_A.width = A.width; d_A.height = A.height;
size_t size = A.width*A.height*sizeof(float);
//allocate memory for matrix A on device
hipMalloc(&d_A.elements,size);
//copy matrix A elements to memory allocated on device
hipMemcpy(d_A.elements, A.elements,size,hipMemcpyHostToDevice);
//do the same thing for matrix B
Matrix d_B;
d_B.width = B.width; d_B.height = B.height;
//allocate memory for matrix B on device
hipMalloc(&d_B.elements,size);
//copy matrix B elements to memory allocated on device
hipMemcpy(d_B.elements, B.elements,size,hipMemcpyHostToDevice);
//allocate memory for matrix C on device - obviously nothing to copy
Matrix d_C;
d_C.width = C.width; d_C.height = C.height;
hipMalloc(&d_C.elements,size);
//define block size and grid size for kernel
dim3 dimBlock(1,3);
//dim3 dimGrid(B.width/dimBlock.x,A.height/dimBlock.y);
//invoke kernel
MatMulKernel<<<3, dimBlock>>>(d_A, d_B, d_C);
//read matrix multiplication result from device
hipMemcpy(C.elements, d_C.elements, size, hipMemcpyDeviceToHost);
//Free device memory
hipFree(d_A.elements);
hipFree(d_B.elements);
hipFree(d_C.elements);
}
//The ACTUAL kernel that performs matrix multiplication in the GPU
__global__ void MatMulKernel(Matrix A, Matrix B, Matrix C)
{
//each kernel thread computes one element of C
float Cvalue=0;
//therefore, each thread is needs to read the row of A and column of B for its element of C.
//reading from global memory here - would be better if the row and column were stored in shared memory
int row = blockIdx.y*blockDim.y+threadIdx.y;
int col = blockIdx.x*blockDim.x+threadIdx.x;
for (int e = 0; e < A.width; ++e)
Cvalue += A.elements[row * A.width + e]* B.elements[e * B.width + col];
C.elements[row * C.width + col] = Cvalue;
}
int main(void)
{
float *a_els = new float[9];
for(int i = 0; i<9; ++i)
a_els[i]=2.0;
float *b_els = new float[9];
for(int i = 0; i<9; ++i)
b_els[i]=2.0;
Matrix m_a;
m_a.height=3;
m_a.width=3;
m_a.elements = a_els;
Matrix m_b;
m_b.height=3;
m_b.width=3;
m_b.elements = a_els;
float *c_els=new float[9];
Matrix m_c;
m_c.height = 3;
m_c.width = 3;
m_c.elements=c_els;
MatMul(m_a,m_b,m_c);
for(int i =0; i<9;i++)
printf("%f \n",m_c.elements[i]);
delete[] a_els;
delete[] b_els;
delete[] c_els;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <numeric>
#include <stdlib.h>
#include <stdio.h>
typedef struct{
int width;
int height;
float* elements;
} Matrix;
#define BLOCK_SIZE 3
__global__ void MatMulKernel(const Matrix, const Matrix, Matrix);
void MatMul(const Matrix A, const Matrix B, Matrix C)
{
Matrix d_A;
d_A.width = A.width; d_A.height = A.height;
size_t size = A.width*A.height*sizeof(float);
//allocate memory for matrix A on device
hipMalloc(&d_A.elements,size);
//copy matrix A elements to memory allocated on device
hipMemcpy(d_A.elements, A.elements,size,hipMemcpyHostToDevice);
//do the same thing for matrix B
Matrix d_B;
d_B.width = B.width; d_B.height = B.height;
//allocate memory for matrix B on device
hipMalloc(&d_B.elements,size);
//copy matrix B elements to memory allocated on device
hipMemcpy(d_B.elements, B.elements,size,hipMemcpyHostToDevice);
//allocate memory for matrix C on device - obviously nothing to copy
Matrix d_C;
d_C.width = C.width; d_C.height = C.height;
hipMalloc(&d_C.elements,size);
//define block size and grid size for kernel
dim3 dimBlock(1,3);
//dim3 dimGrid(B.width/dimBlock.x,A.height/dimBlock.y);
//invoke kernel
MatMulKernel<<<3, dimBlock>>>(d_A, d_B, d_C);
//read matrix multiplication result from device
hipMemcpy(C.elements, d_C.elements, size, hipMemcpyDeviceToHost);
//Free device memory
hipFree(d_A.elements);
hipFree(d_B.elements);
hipFree(d_C.elements);
}
//The ACTUAL kernel that performs matrix multiplication in the GPU
__global__ void MatMulKernel(Matrix A, Matrix B, Matrix C)
{
//each kernel thread computes one element of C
float Cvalue=0;
//therefore, each thread is needs to read the row of A and column of B for its element of C.
//reading from global memory here - would be better if the row and column were stored in shared memory
int row = blockIdx.y*blockDim.y+threadIdx.y;
int col = blockIdx.x*blockDim.x+threadIdx.x;
for (int e = 0; e < A.width; ++e)
Cvalue += A.elements[row * A.width + e]* B.elements[e * B.width + col];
C.elements[row * C.width + col] = Cvalue;
}
int main(void)
{
float *a_els = new float[9];
for(int i = 0; i<9; ++i)
a_els[i]=2.0;
float *b_els = new float[9];
for(int i = 0; i<9; ++i)
b_els[i]=2.0;
Matrix m_a;
m_a.height=3;
m_a.width=3;
m_a.elements = a_els;
Matrix m_b;
m_b.height=3;
m_b.width=3;
m_b.elements = a_els;
float *c_els=new float[9];
Matrix m_c;
m_c.height = 3;
m_c.width = 3;
m_c.elements=c_els;
MatMul(m_a,m_b,m_c);
for(int i =0; i<9;i++)
printf("%f \n",m_c.elements[i]);
delete[] a_els;
delete[] b_els;
delete[] c_els;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12MatMulKernel6MatrixS_S_
.globl _Z12MatMulKernel6MatrixS_S_
.p2align 8
.type _Z12MatMulKernel6MatrixS_S_,@function
_Z12MatMulKernel6MatrixS_S_:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x3c
s_load_b32 s6, s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x28
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s4, 16
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s4, v[3:4]
s_cmp_lt_i32 s6, 1
s_cbranch_scc1 .LBB0_3
s_load_b64 s[8:9], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_2)
v_mul_lo_u32 v2, v0, s6
s_clause 0x1
s_load_b32 s7, s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x18
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s6, s6, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s6, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s7, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4:
s_load_b32 s0, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s0, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12MatMulKernel6MatrixS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12MatMulKernel6MatrixS_S_, .Lfunc_end0-_Z12MatMulKernel6MatrixS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 16
.value_kind: by_value
- .offset: 32
.size: 16
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12MatMulKernel6MatrixS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12MatMulKernel6MatrixS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <numeric>
#include <stdlib.h>
#include <stdio.h>
typedef struct{
int width;
int height;
float* elements;
} Matrix;
#define BLOCK_SIZE 3
__global__ void MatMulKernel(const Matrix, const Matrix, Matrix);
void MatMul(const Matrix A, const Matrix B, Matrix C)
{
Matrix d_A;
d_A.width = A.width; d_A.height = A.height;
size_t size = A.width*A.height*sizeof(float);
//allocate memory for matrix A on device
hipMalloc(&d_A.elements,size);
//copy matrix A elements to memory allocated on device
hipMemcpy(d_A.elements, A.elements,size,hipMemcpyHostToDevice);
//do the same thing for matrix B
Matrix d_B;
d_B.width = B.width; d_B.height = B.height;
//allocate memory for matrix B on device
hipMalloc(&d_B.elements,size);
//copy matrix B elements to memory allocated on device
hipMemcpy(d_B.elements, B.elements,size,hipMemcpyHostToDevice);
//allocate memory for matrix C on device - obviously nothing to copy
Matrix d_C;
d_C.width = C.width; d_C.height = C.height;
hipMalloc(&d_C.elements,size);
//define block size and grid size for kernel
dim3 dimBlock(1,3);
//dim3 dimGrid(B.width/dimBlock.x,A.height/dimBlock.y);
//invoke kernel
MatMulKernel<<<3, dimBlock>>>(d_A, d_B, d_C);
//read matrix multiplication result from device
hipMemcpy(C.elements, d_C.elements, size, hipMemcpyDeviceToHost);
//Free device memory
hipFree(d_A.elements);
hipFree(d_B.elements);
hipFree(d_C.elements);
}
//The ACTUAL kernel that performs matrix multiplication in the GPU
__global__ void MatMulKernel(Matrix A, Matrix B, Matrix C)
{
//each kernel thread computes one element of C
float Cvalue=0;
//therefore, each thread is needs to read the row of A and column of B for its element of C.
//reading from global memory here - would be better if the row and column were stored in shared memory
int row = blockIdx.y*blockDim.y+threadIdx.y;
int col = blockIdx.x*blockDim.x+threadIdx.x;
for (int e = 0; e < A.width; ++e)
Cvalue += A.elements[row * A.width + e]* B.elements[e * B.width + col];
C.elements[row * C.width + col] = Cvalue;
}
int main(void)
{
float *a_els = new float[9];
for(int i = 0; i<9; ++i)
a_els[i]=2.0;
float *b_els = new float[9];
for(int i = 0; i<9; ++i)
b_els[i]=2.0;
Matrix m_a;
m_a.height=3;
m_a.width=3;
m_a.elements = a_els;
Matrix m_b;
m_b.height=3;
m_b.width=3;
m_b.elements = a_els;
float *c_els=new float[9];
Matrix m_c;
m_c.height = 3;
m_c.width = 3;
m_c.elements=c_els;
MatMul(m_a,m_b,m_c);
for(int i =0; i<9;i++)
printf("%f \n",m_c.elements[i]);
delete[] a_els;
delete[] b_els;
delete[] c_els;
return 0;
} | .text
.file "cuda-linear-algebra.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z6MatMul6MatrixS_S_ # -- Begin function _Z6MatMul6MatrixS_S_
.p2align 4, 0x90
.type _Z6MatMul6MatrixS_S_,@function
_Z6MatMul6MatrixS_S_: # @_Z6MatMul6MatrixS_S_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movq %r8, %r15
movq %rcx, %r12
movq %rdx, %r13
movq %rsi, %rbp
movq %rdi, 32(%rsp)
movq %rdi, %rax
shrq $32, %rax
imull %edi, %eax
movslq %eax, %r14
shlq $2, %r14
leaq 40(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 40(%rsp), %rdi
movq %rbp, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq %r13, 16(%rsp)
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq %r15, (%rsp)
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movabsq $4294967299, %rdi # imm = 0x100000003
movabsq $12884901889, %rdx # imm = 0x300000001
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
movups 32(%rsp), %xmm0
movups 16(%rsp), %xmm1
movups (%rsp), %xmm2
movups %xmm0, 152(%rsp)
movups %xmm1, 136(%rsp)
movups %xmm2, 120(%rsp)
leaq 152(%rsp), %rax
movq %rax, 96(%rsp)
leaq 136(%rsp), %rax
movq %rax, 104(%rsp)
leaq 120(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12MatMulKernel6MatrixS_S_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_2:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z6MatMul6MatrixS_S_, .Lfunc_end0-_Z6MatMul6MatrixS_S_
.cfi_endproc
# -- End function
.globl _Z27__device_stub__MatMulKernel6MatrixS_S_ # -- Begin function _Z27__device_stub__MatMulKernel6MatrixS_S_
.p2align 4, 0x90
.type _Z27__device_stub__MatMulKernel6MatrixS_S_,@function
_Z27__device_stub__MatMulKernel6MatrixS_S_: # @_Z27__device_stub__MatMulKernel6MatrixS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 80(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 48(%rsp)
movq %r9, 56(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12MatMulKernel6MatrixS_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z27__device_stub__MatMulKernel6MatrixS_S_, .Lfunc_end1-_Z27__device_stub__MatMulKernel6MatrixS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $36, %edi
callq _Znam
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl $1073741824, (%rbx,%rax,4) # imm = 0x40000000
incq %rax
cmpq $9, %rax
jne .LBB2_1
# %bb.2: # %.preheader.preheader
movl $36, %edi
callq _Znam
movq %rax, %r14
movabsq $12884901891, %rdi # imm = 0x300000003
movq %rbx, %rsi
movq %rdi, %rdx
movq %rbx, %rcx
movq %rdi, %r8
movq %rax, %r9
callq _Z6MatMul6MatrixS_S_
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r15
cmpq $9, %r15
jne .LBB2_3
# %bb.4:
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12MatMulKernel6MatrixS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12MatMulKernel6MatrixS_S_,@object # @_Z12MatMulKernel6MatrixS_S_
.section .rodata,"a",@progbits
.globl _Z12MatMulKernel6MatrixS_S_
.p2align 3, 0x0
_Z12MatMulKernel6MatrixS_S_:
.quad _Z27__device_stub__MatMulKernel6MatrixS_S_
.size _Z12MatMulKernel6MatrixS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f \n"
.size .L.str, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12MatMulKernel6MatrixS_S_"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__MatMulKernel6MatrixS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12MatMulKernel6MatrixS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12MatMulKernel6MatrixS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0080*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fe400078e0203 */
/*00a0*/ IMAD R3, R2, c[0x0][0x0], R5 ; /* 0x0000000002037a24 */
/* 0x002fc600078e0205 */
/*00b0*/ @!P0 BRA 0xc10 ; /* 0x00000b5000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R4.reuse, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x040fe40007ffe0ff */
/*00d0*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe400078ec0ff */
/*00e0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*00f0*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fe40000000f00 */
/*0100*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fd20000000f00 */
/*0110*/ @!P0 BRA 0xb00 ; /* 0x000009e000008947 */
/* 0x000fea0003800000 */
/*0120*/ IADD3 R5, -R4, c[0x0][0x160], RZ ; /* 0x0000580004057a10 */
/* 0x000fe20007ffe1ff */
/*0130*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0140*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0150*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe200000001ff */
/*0160*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f04270 */
/*0170*/ IMAD R6, R0, c[0x0][0x160], RZ ; /* 0x0000580000067a24 */
/* 0x000fe200078e02ff */
/*0180*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fca0000000f00 */
/*0190*/ IMAD.WIDE R8, R3, R8, c[0x0][0x178] ; /* 0x00005e0003087625 */
/* 0x000fcc00078e0208 */
/*01a0*/ @!P0 BRA 0x960 ; /* 0x000007b000008947 */
/* 0x000fea0003800000 */
/*01b0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01d0*/ @!P1 BRA 0x690 ; /* 0x000004b000009947 */
/* 0x000fea0003800000 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01f0*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0200*/ LDG.E R21, [R8.64] ; /* 0x0000000408157981 */
/* 0x0000a2000c1e1900 */
/*0210*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0220*/ IMAD.WIDE R12, R6, 0x4, R12 ; /* 0x00000004060c7825 */
/* 0x000fca00078e020c */
/*0230*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x000ea2000c1e1900 */
/*0240*/ MOV R7, c[0x0][0x170] ; /* 0x00005c0000077a02 */
/* 0x000fc60000000f00 */
/*0250*/ LDG.E R14, [R12.64+0x4] ; /* 0x000004040c0e7981 */
/* 0x000ee4000c1e1900 */
/*0260*/ IMAD.WIDE R10, R7.reuse, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x040fe400078e0208 */
/*0270*/ LDG.E R27, [R12.64+0x8] ; /* 0x000008040c1b7981 */
/* 0x000f28000c1e1900 */
/*0280*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x0002e2000c1e1900 */
/*0290*/ IMAD.WIDE R22, R7, 0x4, R10 ; /* 0x0000000407167825 */
/* 0x000fc600078e020a */
/*02a0*/ LDG.E R18, [R12.64+0xc] ; /* 0x00000c040c127981 */
/* 0x000f66000c1e1900 */
/*02b0*/ IMAD.WIDE R28, R7.reuse, 0x4, R22 ; /* 0x00000004071c7825 */
/* 0x040fe200078e0216 */
/*02c0*/ LDG.E R26, [R22.64] ; /* 0x00000004161a7981 */
/* 0x000328000c1e1900 */
/*02d0*/ LDG.E R19, [R28.64] ; /* 0x000000041c137981 */
/* 0x000362000c1e1900 */
/*02e0*/ IMAD.WIDE R16, R7, 0x4, R28 ; /* 0x0000000407107825 */
/* 0x000fc600078e021c */
/*02f0*/ LDG.E R8, [R12.64+0x10] ; /* 0x000010040c087981 */
/* 0x001f68000c1e1900 */
/*0300*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000168000c1e1900 */
/*0310*/ LDG.E R10, [R12.64+0x14] ; /* 0x000014040c0a7981 */
/* 0x002f68000c1e1900 */
/*0320*/ LDG.E R28, [R12.64+0x1c] ; /* 0x00001c040c1c7981 */
/* 0x000f62000c1e1900 */
/*0330*/ IMAD.WIDE R16, R7, 0x4, R16 ; /* 0x0000000407107825 */
/* 0x001fca00078e0210 */
/*0340*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x000562000c1e1900 */
/*0350*/ IMAD.WIDE R22, R7, 0x4, R16 ; /* 0x0000000407167825 */
/* 0x000fc800078e0210 */
/*0360*/ FFMA R16, R21, R20, R24 ; /* 0x0000001415107223 */
/* 0x004fe40000000018 */
/*0370*/ LDG.E R20, [R12.64+0x18] ; /* 0x000018040c147981 */
/* 0x000ea2000c1e1900 */
/*0380*/ IMAD.WIDE R24, R7, 0x4, R22 ; /* 0x0000000407187825 */
/* 0x000fc600078e0216 */
/*0390*/ LDG.E R21, [R22.64] ; /* 0x0000000416157981 */
/* 0x0000a8000c1e1900 */
/*03a0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0002a2000c1e1900 */
/*03b0*/ FFMA R16, R15, R14, R16 ; /* 0x0000000e0f107223 */
/* 0x008fe40000000010 */
/*03c0*/ IMAD.WIDE R14, R7.reuse, 0x4, R24 ; /* 0x00000004070e7825 */
/* 0x040fe200078e0218 */
/*03d0*/ LDG.E R23, [R12.64+0x20] ; /* 0x000020040c177981 */
/* 0x001ee6000c1e1900 */
/*03e0*/ FFMA R26, R26, R27, R16 ; /* 0x0000001b1a1a7223 */
/* 0x010fe20000000010 */
/*03f0*/ LDG.E R25, [R12.64+0x24] ; /* 0x000024040c197981 */
/* 0x002f22000c1e1900 */
/*0400*/ IMAD.WIDE R16, R7, 0x4, R14 ; /* 0x0000000407107825 */
/* 0x000fc600078e020e */
/*0410*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0000e2000c1e1900 */
/*0420*/ FFMA R26, R19, R18, R26 ; /* 0x00000012131a7223 */
/* 0x020fe4000000001a */
/*0430*/ IMAD.WIDE R18, R7, 0x4, R16 ; /* 0x0000000407127825 */
/* 0x000fe200078e0210 */
/*0440*/ LDG.E R22, [R12.64+0x28] ; /* 0x000028040c167981 */
/* 0x000f66000c1e1900 */
/*0450*/ FFMA R26, R9, R8, R26 ; /* 0x00000008091a7223 */
/* 0x000fe2000000001a */
/*0460*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000322000c1e1900 */
/*0470*/ IMAD.WIDE R8, R7, 0x4, R18 ; /* 0x0000000407087825 */
/* 0x000fc600078e0212 */
/*0480*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000368000c1e1900 */
/*0490*/ LDG.E R24, [R8.64] ; /* 0x0000000408187981 */
/* 0x000568000c1e1900 */
/*04a0*/ LDG.E R15, [R12.64+0x2c] ; /* 0x00002c040c0f7981 */
/* 0x001f62000c1e1900 */
/*04b0*/ FFMA R26, R11, R10, R26 ; /* 0x0000000a0b1a7223 */
/* 0x000fe4000000001a */
/*04c0*/ IMAD.WIDE R10, R7, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x000fe200078e0208 */
/*04d0*/ LDG.E R17, [R12.64+0x30] ; /* 0x000030040c117981 */
/* 0x002f66000c1e1900 */
/*04e0*/ FFMA R26, R21, R20, R26 ; /* 0x00000014151a7223 */
/* 0x004fc4000000001a */
/*04f0*/ IMAD.WIDE R20, R7, 0x4, R10 ; /* 0x0000000407147825 */
/* 0x000fe400078e020a */
/*0500*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x0000a4000c1e1900 */
/*0510*/ FFMA R28, R29, R28, R26 ; /* 0x0000001c1d1c7223 */
/* 0x000fe4000000001a */
/*0520*/ IMAD.WIDE R26, R7.reuse, 0x4, R20 ; /* 0x00000004071a7825 */
/* 0x040fe200078e0214 */
/*0530*/ LDG.E R29, [R12.64+0x34] ; /* 0x000034040c1d7981 */
/* 0x000ea8000c1e1900 */
/*0540*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x0002a2000c1e1900 */
/*0550*/ IMAD.WIDE R8, R7, 0x4, R26 ; /* 0x0000000407087825 */
/* 0x000fc600078e021a */
/*0560*/ LDG.E R19, [R26.64] ; /* 0x000000041a137981 */
/* 0x0006a8000c1e1900 */
/*0570*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0010a8000c1e1900 */
/*0580*/ LDG.E R21, [R12.64+0x38] ; /* 0x000038040c157981 */
/* 0x002ea8000c1e1900 */
/*0590*/ LDG.E R26, [R12.64+0x3c] ; /* 0x00003c040c1a7981 */
/* 0x008ee2000c1e1900 */
/*05a0*/ FFMA R14, R14, R23, R28 ; /* 0x000000170e0e7223 */
/* 0x000fc8000000001c */
/*05b0*/ FFMA R25, R16, R25, R14 ; /* 0x0000001910197223 */
/* 0x010fe2000000000e */
/*05c0*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fc60007ffe0ff */
/*05d0*/ FFMA R18, R18, R22, R25 ; /* 0x0000001612127223 */
/* 0x020fe20000000019 */
/*05e0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fc60003f24270 */
/*05f0*/ FFMA R15, R24, R15, R18 ; /* 0x0000000f180f7223 */
/* 0x000fe20000000012 */
/*0600*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0610*/ IMAD.WIDE R8, R7, 0x4, R8 ; /* 0x0000000407087825 */
/* 0x001fc600078e0208 */
/*0620*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0630*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe20007ffe0ff */
/*0640*/ FFMA R10, R10, R17, R15 ; /* 0x000000110a0a7223 */
/* 0x004fc8000000000f */
/*0650*/ FFMA R10, R20, R29, R10 ; /* 0x0000001d140a7223 */
/* 0x000fc8000000000a */
/*0660*/ FFMA R10, R19, R21, R10 ; /* 0x00000015130a7223 */
/* 0x000fc8000000000a */
/*0670*/ FFMA R24, R11, R26, R10 ; /* 0x0000001a0b187223 */
/* 0x008fe2000000000a */
/*0680*/ @P1 BRA 0x1f0 ; /* 0xfffffb6000001947 */
/* 0x000fea000383ffff */
/*0690*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*06a0*/ @!P1 BRA 0x940 ; /* 0x0000029000009947 */
/* 0x000fea0003800000 */
/*06b0*/ MOV R7, c[0x0][0x170] ; /* 0x00005c0000077a02 */
/* 0x000fe20000000f00 */
/*06c0*/ LDG.E R23, [R8.64] ; /* 0x0000000408177981 */
/* 0x0000a2000c1e1900 */
/*06d0*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*06e0*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe20008000f00 */
/*06f0*/ IMAD.WIDE R16, R7, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x000fc800078e0208 */
/*0700*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*0710*/ IMAD.WIDE R12, R7.reuse, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x040fe200078e0210 */
/*0720*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x000ea8000c1e1900 */
/*0730*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0002e2000c1e1900 */
/*0740*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0750*/ LDG.E R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000ee6000c1e1900 */
/*0760*/ IMAD.WIDE R18, R7.reuse, 0x4, R14 ; /* 0x0000000407127825 */
/* 0x040fe200078e020e */
/*0770*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000968000c1e1900 */
/*0780*/ LDG.E R27, [R10.64+0x8] ; /* 0x000008040a1b7981 */
/* 0x000f62000c1e1900 */
/*0790*/ IMAD.WIDE R20, R7, 0x4, R18 ; /* 0x0000000407147825 */
/* 0x000fc600078e0212 */
/*07a0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07b0*/ LDG.E R29, [R10.64+0xc] ; /* 0x00000c040a1d7981 */
/* 0x000f62000c1e1900 */
/*07c0*/ IMAD.WIDE R8, R7, 0x4, R20 ; /* 0x0000000407087825 */
/* 0x001fc600078e0214 */
/*07d0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000168000c1e1900 */
/*07e0*/ LDG.E R28, [R10.64+0x10] ; /* 0x000010040a1c7981 */
/* 0x000f62000c1e1900 */
/*07f0*/ IMAD.WIDE R12, R7, 0x4, R8 ; /* 0x00000004070c7825 */
/* 0x010fc600078e0208 */
/*0800*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000968000c1e1900 */
/*0810*/ LDG.E R15, [R10.64+0x14] ; /* 0x000014040a0f7981 */
/* 0x002f68000c1e1900 */
/*0820*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000368000c1e1900 */
/*0830*/ LDG.E R21, [R10.64+0x1c] ; /* 0x00001c040a157981 */
/* 0x010f28000c1e1900 */
/*0840*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x001f28000c1e1900 */
/*0850*/ LDG.E R8, [R10.64+0x18] ; /* 0x000018040a087981 */
/* 0x002f22000c1e1900 */
/*0860*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0870*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0880*/ IADD3 R2, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fe40007ffe0ff */
/*0890*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe20007ffe0ff */
/*08a0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08b0*/ FFMA R22, R23, R22, R24 ; /* 0x0000001617167223 */
/* 0x004fc80000000018 */
/*08c0*/ FFMA R16, R16, R25, R22 ; /* 0x0000001910107223 */
/* 0x008fc80000000016 */
/*08d0*/ FFMA R16, R26, R27, R16 ; /* 0x0000001b1a107223 */
/* 0x020fc80000000010 */
/*08e0*/ FFMA R29, R14, R29, R16 ; /* 0x0000001d0e1d7223 */
/* 0x000fc80000000010 */
/*08f0*/ FFMA R18, R18, R28, R29 ; /* 0x0000001c12127223 */
/* 0x000fc8000000001d */
/*0900*/ FFMA R15, R20, R15, R18 ; /* 0x0000000f140f7223 */
/* 0x000fc80000000012 */
/*0910*/ FFMA R24, R17, R8, R15 ; /* 0x0000000811187223 */
/* 0x010fe4000000000f */
/*0920*/ IMAD.WIDE R8, R7, 0x4, R12 ; /* 0x0000000407087825 */
/* 0x000fc800078e020c */
/*0930*/ FFMA R24, R19, R21, R24 ; /* 0x0000001513187223 */
/* 0x000fe40000000018 */
/*0940*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0950*/ @!P0 BRA 0xb00 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0960*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*0970*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe40008000f00 */
/*0980*/ MOV R7, c[0x0][0x170] ; /* 0x00005c0000077a02 */
/* 0x000fc60000000f00 */
/*0990*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*09a0*/ IMAD.WIDE R16, R7.reuse, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x040fe200078e0208 */
/*09b0*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000ea8000c1e1900 */
/*09c0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*09d0*/ IMAD.WIDE R12, R7, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x000fc600078e0210 */
/*09e0*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ee8000c1e1900 */
/*09f0*/ LDG.E R19, [R10.64+0x4] ; /* 0x000004040a137981 */
/* 0x000ee2000c1e1900 */
/*0a00*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0a10*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R20, [R10.64+0x8] ; /* 0x000008040a147981 */
/* 0x000f28000c1e1900 */
/*0a30*/ LDG.E R22, [R10.64+0xc] ; /* 0x00000c040a167981 */
/* 0x000f68000c1e1900 */
/*0a40*/ LDG.E R23, [R14.64] ; /* 0x000000040e177981 */
/* 0x000f62000c1e1900 */
/*0a50*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0a70*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a80*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fc60007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ FFMA R18, R9, R18, R24 ; /* 0x0000001209127223 */
/* 0x004fc80000000018 */
/*0ab0*/ FFMA R18, R17, R19, R18 ; /* 0x0000001311127223 */
/* 0x008fe40000000012 */
/*0ac0*/ IMAD.WIDE R8, R7, 0x4, R14 ; /* 0x0000000407087825 */
/* 0x000fc800078e020e */
/*0ad0*/ FFMA R18, R21, R20, R18 ; /* 0x0000001415127223 */
/* 0x010fc80000000012 */
/*0ae0*/ FFMA R24, R23, R22, R18 ; /* 0x0000001617187223 */
/* 0x020fe20000000012 */
/*0af0*/ @P0 BRA 0x960 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*0b00*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0b10*/ @!P0 BRA 0xc10 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0b20*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b30*/ IMAD R6, R0, c[0x0][0x160], R2 ; /* 0x0000580000067a24 */
/* 0x000fe400078e0202 */
/*0b40*/ IMAD R2, R2, c[0x0][0x170], R3 ; /* 0x00005c0002027a24 */
/* 0x000fce00078e0203 */
/*0b50*/ IMAD.WIDE R6, R6, R9, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc800078e0209 */
/*0b60*/ IMAD.WIDE R8, R2, R9, c[0x0][0x178] ; /* 0x00005e0002087625 */
/* 0x000fca00078e0209 */
/*0b70*/ LDG.E R5, [R8.64] ; /* 0x0000000408057981 */
/* 0x0000a8000c1e1900 */
/*0b80*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x0002a2000c1e1900 */
/*0b90*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0ba0*/ MOV R11, c[0x0][0x170] ; /* 0x00005c00000b7a02 */
/* 0x000fe40000000f00 */
/*0bb0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*0bc0*/ IMAD.WIDE R8, R11, 0x4, R8 ; /* 0x000000040b087825 */
/* 0x001fe200078e0208 */
/*0bd0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0be0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0bf0*/ FFMA R24, R5, R2, R24 ; /* 0x0000000205187223 */
/* 0x004fc80000000018 */
/*0c00*/ @P0 BRA 0xb70 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0c10*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0c20*/ IMAD R3, R0, c[0x0][0x180], R3 ; /* 0x0000600000037a24 */
/* 0x000fc800078e0203 */
/*0c30*/ IMAD.WIDE R2, R3, R2, c[0x0][0x188] ; /* 0x0000620003027625 */
/* 0x000fca00078e0202 */
/*0c40*/ STG.E [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x000fe2000c101904 */
/*0c50*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c60*/ BRA 0xc60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12MatMulKernel6MatrixS_S_
.globl _Z12MatMulKernel6MatrixS_S_
.p2align 8
.type _Z12MatMulKernel6MatrixS_S_,@function
_Z12MatMulKernel6MatrixS_S_:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x3c
s_load_b32 s6, s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x28
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s4, 16
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s4, v[3:4]
s_cmp_lt_i32 s6, 1
s_cbranch_scc1 .LBB0_3
s_load_b64 s[8:9], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_2)
v_mul_lo_u32 v2, v0, s6
s_clause 0x1
s_load_b32 s7, s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x18
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s6, s6, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s6, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s7, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4:
s_load_b32 s0, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s0, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12MatMulKernel6MatrixS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12MatMulKernel6MatrixS_S_, .Lfunc_end0-_Z12MatMulKernel6MatrixS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 16
.value_kind: by_value
- .offset: 32
.size: 16
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12MatMulKernel6MatrixS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12MatMulKernel6MatrixS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0019d95c_00000000-6_cuda-linear-algebra.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3712:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3712:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_
.type _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_, @function
_Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_:
.LFB3734:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq %rdi, 64(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 80(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 120
pushq 8(%rsp)
.cfi_def_cfa_offset 128
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z12MatMulKernel6MatrixS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3734:
.size _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_, .-_Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_
.globl _Z12MatMulKernel6MatrixS_S_
.type _Z12MatMulKernel6MatrixS_S_, @function
_Z12MatMulKernel6MatrixS_S_:
.LFB3735:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %rdi, 32(%rsp)
movq %rsi, 40(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 24(%rsp)
movq %r8, (%rsp)
movq %r9, 8(%rsp)
movq %rsp, %rdx
leaq 16(%rsp), %rsi
leaq 32(%rsp), %rdi
call _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3735:
.size _Z12MatMulKernel6MatrixS_S_, .-_Z12MatMulKernel6MatrixS_S_
.globl _Z6MatMul6MatrixS_S_
.type _Z6MatMul6MatrixS_S_, @function
_Z6MatMul6MatrixS_S_:
.LFB3708:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %rsi, %r15
movq %rdx, %r12
movq %rcx, %r14
movq %r8, %rbp
movq %r9, %r13
movq %fs:40, %rdx
movq %rdx, 136(%rsp)
xorl %edx, %edx
movq %rdi, %rbx
sarq $32, %rbx
movl %edi, 32(%rsp)
movl %ebx, 36(%rsp)
imull %edi, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r15, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %r12d, 48(%rsp)
sarq $32, %r12
movl %r12d, 52(%rsp)
leaq 56(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl %ebp, 64(%rsp)
sarq $32, %rbp
movl %ebp, 68(%rsp)
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, 8(%rsp)
movl $3, 12(%rsp)
movl $3, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movq %rbx, %rdx
movq 72(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movdqa 32(%rsp), %xmm0
movaps %xmm0, 80(%rsp)
movdqa 48(%rsp), %xmm1
movaps %xmm1, 96(%rsp)
movdqa 64(%rsp), %xmm2
movaps %xmm2, 112(%rsp)
leaq 112(%rsp), %rdx
leaq 96(%rsp), %rsi
leaq 80(%rsp), %rdi
call _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3708:
.size _Z6MatMul6MatrixS_S_, .-_Z6MatMul6MatrixS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%f \n"
.text
.globl main
.type main, @function
main:
.LFB3709:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movl $36, %edi
call _Znam@PLT
movq %rax, %r13
leaq 36(%rax), %rdx
movss .LC0(%rip), %xmm0
.L18:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L18
movl $36, %edi
call _Znam@PLT
movq %rax, %r14
leaq 36(%rax), %rdx
movss .LC0(%rip), %xmm0
.L19:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L19
movabsq $12884901888, %rbx
movq %rbx, %rbp
orq $3, %rbp
movl $36, %edi
call _Znam@PLT
movq %rax, %r15
movq %rbp, %r8
movq %rax, %r9
movq %rbp, %rdx
movq %r13, %rcx
movq %rbp, %rdi
movq %r13, %rsi
call _Z6MatMul6MatrixS_S_
movq %r15, %rbx
leaq 36(%r15), %r12
leaq .LC1(%rip), %rbp
.L20:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L20
movq %r13, %rdi
call _ZdaPv@PLT
movq %r14, %rdi
call _ZdaPv@PLT
movq %r15, %rdi
call _ZdaPv@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3709:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z12MatMulKernel6MatrixS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3737:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z12MatMulKernel6MatrixS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3737:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda-linear-algebra.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z6MatMul6MatrixS_S_ # -- Begin function _Z6MatMul6MatrixS_S_
.p2align 4, 0x90
.type _Z6MatMul6MatrixS_S_,@function
_Z6MatMul6MatrixS_S_: # @_Z6MatMul6MatrixS_S_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movq %r8, %r15
movq %rcx, %r12
movq %rdx, %r13
movq %rsi, %rbp
movq %rdi, 32(%rsp)
movq %rdi, %rax
shrq $32, %rax
imull %edi, %eax
movslq %eax, %r14
shlq $2, %r14
leaq 40(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 40(%rsp), %rdi
movq %rbp, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq %r13, 16(%rsp)
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq %r15, (%rsp)
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movabsq $4294967299, %rdi # imm = 0x100000003
movabsq $12884901889, %rdx # imm = 0x300000001
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
movups 32(%rsp), %xmm0
movups 16(%rsp), %xmm1
movups (%rsp), %xmm2
movups %xmm0, 152(%rsp)
movups %xmm1, 136(%rsp)
movups %xmm2, 120(%rsp)
leaq 152(%rsp), %rax
movq %rax, 96(%rsp)
leaq 136(%rsp), %rax
movq %rax, 104(%rsp)
leaq 120(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12MatMulKernel6MatrixS_S_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_2:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z6MatMul6MatrixS_S_, .Lfunc_end0-_Z6MatMul6MatrixS_S_
.cfi_endproc
# -- End function
.globl _Z27__device_stub__MatMulKernel6MatrixS_S_ # -- Begin function _Z27__device_stub__MatMulKernel6MatrixS_S_
.p2align 4, 0x90
.type _Z27__device_stub__MatMulKernel6MatrixS_S_,@function
_Z27__device_stub__MatMulKernel6MatrixS_S_: # @_Z27__device_stub__MatMulKernel6MatrixS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 80(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 48(%rsp)
movq %r9, 56(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12MatMulKernel6MatrixS_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z27__device_stub__MatMulKernel6MatrixS_S_, .Lfunc_end1-_Z27__device_stub__MatMulKernel6MatrixS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $36, %edi
callq _Znam
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl $1073741824, (%rbx,%rax,4) # imm = 0x40000000
incq %rax
cmpq $9, %rax
jne .LBB2_1
# %bb.2: # %.preheader.preheader
movl $36, %edi
callq _Znam
movq %rax, %r14
movabsq $12884901891, %rdi # imm = 0x300000003
movq %rbx, %rsi
movq %rdi, %rdx
movq %rbx, %rcx
movq %rdi, %r8
movq %rax, %r9
callq _Z6MatMul6MatrixS_S_
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r15
cmpq $9, %r15
jne .LBB2_3
# %bb.4:
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12MatMulKernel6MatrixS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12MatMulKernel6MatrixS_S_,@object # @_Z12MatMulKernel6MatrixS_S_
.section .rodata,"a",@progbits
.globl _Z12MatMulKernel6MatrixS_S_
.p2align 3, 0x0
_Z12MatMulKernel6MatrixS_S_:
.quad _Z27__device_stub__MatMulKernel6MatrixS_S_
.size _Z12MatMulKernel6MatrixS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f \n"
.size .L.str, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12MatMulKernel6MatrixS_S_"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__MatMulKernel6MatrixS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12MatMulKernel6MatrixS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void Compute_psi_phi_Kernel(float* psi, float* phi, const float* gAbsIx, const float* gAbsIy, const float* gIx, const float* gIy, int nPixels, float norm_for_contrast_num, float norm_for_contrast_denom, float eps)
{
int bx = blockIdx.x;
int tx = threadIdx.x;
int x = bx*blockDim.x + tx;
if (x >= nPixels)
return;
float psi_num = 0, psi_denom = 0;
float phi_num = 0, phi_denom = 0;
if (norm_for_contrast_num == 0)
{
psi_num = 1;
phi_num = 1;
}
else if (norm_for_contrast_num == 1)
{
psi_num = gAbsIx[x];
phi_num = gAbsIy[x];
}
else if (norm_for_contrast_num == 2)
{
psi_num = gAbsIx[x] * gAbsIx[x];
phi_num = gAbsIy[x] * gAbsIy[x];
}
else
{
psi_num = pow(gAbsIx[x], norm_for_contrast_num);
phi_num = pow(gAbsIy[x], norm_for_contrast_num);
}
if (norm_for_contrast_denom == 0)
{
psi_denom = 1;
phi_denom = 1;
}
else if (norm_for_contrast_denom == 1)
{
psi_denom = fabs(gIx[x]) + eps;
phi_denom = fabs(gIy[x]) + eps;
}
else if (norm_for_contrast_denom == 2)
{
psi_denom = gIx[x] * gIx[x] + eps;
phi_denom = gIy[x] * gIy[x] + eps;
}
else
{
psi_denom = pow(fabs(gIx[x]), norm_for_contrast_denom) + eps;
phi_denom = pow(fabs(gIy[x]), norm_for_contrast_denom) + eps;
}
psi[x] = psi_num / psi_denom;
phi[x] = phi_num / phi_denom;
} | .file "tmpxft_001104b3_00000000-6_Compute_psi_phi_Kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z60__device_stub__Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifffPfS_PKfS1_S1_S1_ifff
.type _Z60__device_stub__Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifffPfS_PKfS1_S1_S1_ifff, @function
_Z60__device_stub__Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifffPfS_PKfS1_S1_S1_ifff:
.LFB2051:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm2, 4(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 12(%rsp), %rax
movq %rax, 184(%rsp)
leaq 8(%rsp), %rax
movq %rax, 192(%rsp)
leaq 4(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z60__device_stub__Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifffPfS_PKfS1_S1_S1_ifff, .-_Z60__device_stub__Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifffPfS_PKfS1_S1_S1_ifff
.globl _Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff
.type _Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff, @function
_Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z60__device_stub__Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifffPfS_PKfS1_S1_S1_ifff
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff, .-_Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void Compute_psi_phi_Kernel(float* psi, float* phi, const float* gAbsIx, const float* gAbsIy, const float* gIx, const float* gIy, int nPixels, float norm_for_contrast_num, float norm_for_contrast_denom, float eps)
{
int bx = blockIdx.x;
int tx = threadIdx.x;
int x = bx*blockDim.x + tx;
if (x >= nPixels)
return;
float psi_num = 0, psi_denom = 0;
float phi_num = 0, phi_denom = 0;
if (norm_for_contrast_num == 0)
{
psi_num = 1;
phi_num = 1;
}
else if (norm_for_contrast_num == 1)
{
psi_num = gAbsIx[x];
phi_num = gAbsIy[x];
}
else if (norm_for_contrast_num == 2)
{
psi_num = gAbsIx[x] * gAbsIx[x];
phi_num = gAbsIy[x] * gAbsIy[x];
}
else
{
psi_num = pow(gAbsIx[x], norm_for_contrast_num);
phi_num = pow(gAbsIy[x], norm_for_contrast_num);
}
if (norm_for_contrast_denom == 0)
{
psi_denom = 1;
phi_denom = 1;
}
else if (norm_for_contrast_denom == 1)
{
psi_denom = fabs(gIx[x]) + eps;
phi_denom = fabs(gIy[x]) + eps;
}
else if (norm_for_contrast_denom == 2)
{
psi_denom = gIx[x] * gIx[x] + eps;
phi_denom = gIy[x] * gIy[x] + eps;
}
else
{
psi_denom = pow(fabs(gIx[x]), norm_for_contrast_denom) + eps;
phi_denom = pow(fabs(gIy[x]), norm_for_contrast_denom) + eps;
}
psi[x] = psi_num / psi_denom;
phi[x] = phi_num / phi_denom;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Compute_psi_phi_Kernel(float* psi, float* phi, const float* gAbsIx, const float* gAbsIy, const float* gIx, const float* gIy, int nPixels, float norm_for_contrast_num, float norm_for_contrast_denom, float eps)
{
int bx = blockIdx.x;
int tx = threadIdx.x;
int x = bx*blockDim.x + tx;
if (x >= nPixels)
return;
float psi_num = 0, psi_denom = 0;
float phi_num = 0, phi_denom = 0;
if (norm_for_contrast_num == 0)
{
psi_num = 1;
phi_num = 1;
}
else if (norm_for_contrast_num == 1)
{
psi_num = gAbsIx[x];
phi_num = gAbsIy[x];
}
else if (norm_for_contrast_num == 2)
{
psi_num = gAbsIx[x] * gAbsIx[x];
phi_num = gAbsIy[x] * gAbsIy[x];
}
else
{
psi_num = pow(gAbsIx[x], norm_for_contrast_num);
phi_num = pow(gAbsIy[x], norm_for_contrast_num);
}
if (norm_for_contrast_denom == 0)
{
psi_denom = 1;
phi_denom = 1;
}
else if (norm_for_contrast_denom == 1)
{
psi_denom = fabs(gIx[x]) + eps;
phi_denom = fabs(gIy[x]) + eps;
}
else if (norm_for_contrast_denom == 2)
{
psi_denom = gIx[x] * gIx[x] + eps;
phi_denom = gIy[x] * gIy[x] + eps;
}
else
{
psi_denom = pow(fabs(gIx[x]), norm_for_contrast_denom) + eps;
phi_denom = pow(fabs(gIy[x]), norm_for_contrast_denom) + eps;
}
psi[x] = psi_num / psi_denom;
phi[x] = phi_num / phi_denom;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Compute_psi_phi_Kernel(float* psi, float* phi, const float* gAbsIx, const float* gAbsIy, const float* gIx, const float* gIy, int nPixels, float norm_for_contrast_num, float norm_for_contrast_denom, float eps)
{
int bx = blockIdx.x;
int tx = threadIdx.x;
int x = bx*blockDim.x + tx;
if (x >= nPixels)
return;
float psi_num = 0, psi_denom = 0;
float phi_num = 0, phi_denom = 0;
if (norm_for_contrast_num == 0)
{
psi_num = 1;
phi_num = 1;
}
else if (norm_for_contrast_num == 1)
{
psi_num = gAbsIx[x];
phi_num = gAbsIy[x];
}
else if (norm_for_contrast_num == 2)
{
psi_num = gAbsIx[x] * gAbsIx[x];
phi_num = gAbsIy[x] * gAbsIy[x];
}
else
{
psi_num = pow(gAbsIx[x], norm_for_contrast_num);
phi_num = pow(gAbsIy[x], norm_for_contrast_num);
}
if (norm_for_contrast_denom == 0)
{
psi_denom = 1;
phi_denom = 1;
}
else if (norm_for_contrast_denom == 1)
{
psi_denom = fabs(gIx[x]) + eps;
phi_denom = fabs(gIy[x]) + eps;
}
else if (norm_for_contrast_denom == 2)
{
psi_denom = gIx[x] * gIx[x] + eps;
phi_denom = gIy[x] * gIy[x] + eps;
}
else
{
psi_denom = pow(fabs(gIx[x]), norm_for_contrast_denom) + eps;
phi_denom = pow(fabs(gIy[x]), norm_for_contrast_denom) + eps;
}
psi[x] = psi_num / psi_denom;
phi[x] = phi_num / phi_denom;
} | .text
.file "Compute_psi_phi_Kernel.hip"
.globl _Z37__device_stub__Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff # -- Begin function _Z37__device_stub__Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff
.p2align 4, 0x90
.type _Z37__device_stub__Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff,@function
_Z37__device_stub__Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff: # @_Z37__device_stub__Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm2, 4(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 4(%rsp), %rax
movq %rax, 184(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end0:
.size _Z37__device_stub__Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff, .Lfunc_end0-_Z37__device_stub__Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff,@object # @_Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff
.section .rodata,"a",@progbits
.globl _Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff
.p2align 3, 0x0
_Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff:
.quad _Z37__device_stub__Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff
.size _Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff"
.size .L__unnamed_1, 47
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001104b3_00000000-6_Compute_psi_phi_Kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z60__device_stub__Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifffPfS_PKfS1_S1_S1_ifff
.type _Z60__device_stub__Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifffPfS_PKfS1_S1_S1_ifff, @function
_Z60__device_stub__Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifffPfS_PKfS1_S1_S1_ifff:
.LFB2051:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm2, 4(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 12(%rsp), %rax
movq %rax, 184(%rsp)
leaq 8(%rsp), %rax
movq %rax, 192(%rsp)
leaq 4(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z60__device_stub__Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifffPfS_PKfS1_S1_S1_ifff, .-_Z60__device_stub__Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifffPfS_PKfS1_S1_S1_ifff
.globl _Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff
.type _Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff, @function
_Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z60__device_stub__Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifffPfS_PKfS1_S1_S1_ifff
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff, .-_Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Compute_psi_phi_Kernel.hip"
.globl _Z37__device_stub__Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff # -- Begin function _Z37__device_stub__Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff
.p2align 4, 0x90
.type _Z37__device_stub__Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff,@function
_Z37__device_stub__Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff: # @_Z37__device_stub__Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm2, 4(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 4(%rsp), %rax
movq %rax, 184(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end0:
.size _Z37__device_stub__Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff, .Lfunc_end0-_Z37__device_stub__Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff,@object # @_Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff
.section .rodata,"a",@progbits
.globl _Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff
.p2align 3, 0x0
_Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff:
.quad _Z37__device_stub__Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff
.size _Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff"
.size .L__unnamed_1, 47
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void sgemvn_kernel1_fermi(int n, int m, int n1, float alpha, float* A, int lda, float *x, float *y)
{
int ind = blockIdx.x*num_threads + threadIdx.x;
A += ind;
float res = 0.f;
for(int i=0; i<n1; i += sgemv_bs ){
#pragma unroll
for(int j=0; j < sgemv_bs ; j++){
res += A[0] * x[j];
A += lda;
}
x += sgemv_bs;
}
#if 0
if (m>n1){
for(int j=0; j<(m-n1); j++){
res += A[0] * x[j];
A += lda;
}
}
#endif
if (ind<n)
y[ind] = alpha * res;
} | code for sm_80
Function : _Z20sgemvn_kernel1_fermiiiifPfiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R18, -RZ, RZ, 0, 0 ; /* 0x00000000ff127435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ ISETP.GE.AND P1, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe40003f26270 */
/*0070*/ LEA R0, R0, R3, 0x7 ; /* 0x0000000300007211 */
/* 0x001fc800078e38ff */
/*0080*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fe40003f06270 */
/*0090*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fca0000011400 */
/*00a0*/ @!P1 BRA 0x970 ; /* 0x000008c000009947 */
/* 0x000fec0003800000 */
/*00b0*/ LEA R10, P1, R0.reuse, c[0x0][0x170], 0x2 ; /* 0x00005c00000a7a11 */
/* 0x040fe400078210ff */
/*00c0*/ MOV R12, c[0x0][0x180] ; /* 0x00006000000c7a02 */
/* 0x000fe40000000f00 */
/*00d0*/ MOV R13, c[0x0][0x184] ; /* 0x00006100000d7a02 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R18, RZ ; /* 0x000000ff00127202 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fe40000000f00 */
/*0100*/ LEA.HI.X R11, R0, c[0x0][0x174], R3, 0x2, P1 ; /* 0x00005d00000b7a11 */
/* 0x000fc800008f1403 */
/*0110*/ MOV R7, c[0x0][0x178] ; /* 0x00005e0000077a02 */
/* 0x000fe20000000f00 */
/*0120*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x0000a8000c1e1900 */
/*0130*/ IMAD.WIDE R26, R7.reuse, 0x4, R10 ; /* 0x00000004071a7825 */
/* 0x040fe200078e020a */
/*0140*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x000ea8000c1e1900 */
/*0150*/ LDG.E R25, [R12.64+0x4] ; /* 0x000004040c197981 */
/* 0x000ee2000c1e1900 */
/*0160*/ IMAD.WIDE R14, R7, 0x4, R26 ; /* 0x00000004070e7825 */
/* 0x000fc600078e021a */
/*0170*/ LDG.E R16, [R26.64] ; /* 0x000000041a107981 */
/* 0x0002e8000c1e1900 */
/*0180*/ LDG.E R20, [R14.64] ; /* 0x000000040e147981 */
/* 0x000968000c1e1900 */
/*0190*/ LDG.E R5, [R12.64+0x8] ; /* 0x000008040c057981 */
/* 0x000f68000c1e1900 */
/*01a0*/ LDG.E R23, [R12.64+0xc] ; /* 0x00000c040c177981 */
/* 0x000f62000c1e1900 */
/*01b0*/ IMAD.WIDE R14, R7, 0x4, R14 ; /* 0x00000004070e7825 */
/* 0x010fc600078e020e */
/*01c0*/ LDG.E R21, [R12.64+0x10] ; /* 0x000010040c157981 */
/* 0x000f28000c1e1900 */
/*01d0*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000322000c1e1900 */
/*01e0*/ IMAD.WIDE R28, R7, 0x4, R14 ; /* 0x00000004071c7825 */
/* 0x000fc600078e020e */
/*01f0*/ LDG.E R6, [R12.64+0x14] ; /* 0x000014040c067981 */
/* 0x000f28000c1e1900 */
/*0200*/ LDG.E R10, [R28.64] ; /* 0x000000041c0a7981 */
/* 0x001128000c1e1900 */
/*0210*/ LDG.E R4, [R12.64+0x18] ; /* 0x000018040c047981 */
/* 0x000f28000c1e1900 */
/*0220*/ LDG.E R14, [R12.64+0x1c] ; /* 0x00001c040c0e7981 */
/* 0x002f22000c1e1900 */
/*0230*/ IMAD.WIDE R28, R7, 0x4, R28 ; /* 0x00000004071c7825 */
/* 0x001fc600078e021c */
/*0240*/ LDG.E R22, [R12.64+0x20] ; /* 0x000020040c167981 */
/* 0x000f28000c1e1900 */
/*0250*/ LDG.E R11, [R28.64] ; /* 0x000000041c0b7981 */
/* 0x000122000c1e1900 */
/*0260*/ IMAD.WIDE R26, R7, 0x4, R28 ; /* 0x00000004071a7825 */
/* 0x000fca00078e021c */
/*0270*/ LDG.E R9, [R26.64] ; /* 0x000000041a097981 */
/* 0x000324000c1e1900 */
/*0280*/ IMAD.WIDE R26, R7, 0x4, R26 ; /* 0x00000004071a7825 */
/* 0x002fca00078e021a */
/*0290*/ LDG.E R15, [R26.64] ; /* 0x000000041a0f7981 */
/* 0x000322000c1e1900 */
/*02a0*/ IMAD.WIDE R28, R7, 0x4, R26 ; /* 0x00000004071c7825 */
/* 0x001fc800078e021a */
/*02b0*/ FFMA R24, R19, R17, R18 ; /* 0x0000001113187223 */
/* 0x004fe40000000012 */
/*02c0*/ IMAD.WIDE R18, R7, 0x4, R28 ; /* 0x0000000407127825 */
/* 0x000fe200078e021c */
/*02d0*/ LDG.E R17, [R28.64] ; /* 0x000000041c117981 */
/* 0x0000a6000c1e1900 */
/*02e0*/ FFMA R24, R25, R16, R24 ; /* 0x0000001019187223 */
/* 0x008fe40000000018 */
/*02f0*/ LDG.E R16, [R12.64+0x24] ; /* 0x000024040c107981 */
/* 0x000ee8000c1e1900 */
/*0300*/ LDG.E R25, [R18.64] ; /* 0x0000000412197981 */
/* 0x0000e2000c1e1900 */
/*0310*/ FFMA R24, R5, R20, R24 ; /* 0x0000001405187223 */
/* 0x020fc60000000018 */
/*0320*/ LDG.E R20, [R12.64+0x28] ; /* 0x000028040c147981 */
/* 0x000f62000c1e1900 */
/*0330*/ IMAD.WIDE R18, R7, 0x4, R18 ; /* 0x0000000407127825 */
/* 0x001fca00078e0212 */
/*0340*/ LDG.E R5, [R18.64] ; /* 0x0000000412057981 */
/* 0x000162000c1e1900 */
/*0350*/ IMAD.WIDE R26, R7, 0x4, R18 ; /* 0x00000004071a7825 */
/* 0x002fc800078e0212 */
/*0360*/ FFMA R23, R23, R8, R24 ; /* 0x0000000817177223 */
/* 0x010fe20000000018 */
/*0370*/ LDG.E R29, [R26.64] ; /* 0x000000041a1d7981 */
/* 0x000328000c1e1900 */
/*0380*/ LDG.E R8, [R12.64+0x2c] ; /* 0x00002c040c087981 */
/* 0x000f22000c1e1900 */
/*0390*/ FFMA R23, R21, R10, R23 ; /* 0x0000000a15177223 */
/* 0x000fc60000000017 */
/*03a0*/ LDG.E R21, [R12.64+0x30] ; /* 0x000030040c157981 */
/* 0x000f22000c1e1900 */
/*03b0*/ IMAD.WIDE R26, R7, 0x4, R26 ; /* 0x00000004071a7825 */
/* 0x002fca00078e021a */
/*03c0*/ LDG.E R10, [R26.64] ; /* 0x000000041a0a7981 */
/* 0x000322000c1e1900 */
/*03d0*/ IMAD.WIDE R18, R7, 0x4, R26 ; /* 0x0000000407127825 */
/* 0x001fc800078e021a */
/*03e0*/ FFMA R23, R6, R11, R23 ; /* 0x0000000b06177223 */
/* 0x000fe40000000017 */
/*03f0*/ LDG.E R11, [R12.64+0x34] ; /* 0x000034040c0b7981 */
/* 0x000f28000c1e1900 */
/*0400*/ LDG.E R6, [R18.64] ; /* 0x0000000412067981 */
/* 0x000122000c1e1900 */
/*0410*/ FFMA R23, R4, R9, R23 ; /* 0x0000000904177223 */
/* 0x000fc60000000017 */
/*0420*/ LDG.E R9, [R12.64+0x38] ; /* 0x000038040c097981 */
/* 0x000f22000c1e1900 */
/*0430*/ IMAD.WIDE R18, R7, 0x4, R18 ; /* 0x0000000407127825 */
/* 0x001fca00078e0212 */
/*0440*/ LDG.E R4, [R18.64] ; /* 0x0000000412047981 */
/* 0x000122000c1e1900 */
/*0450*/ IMAD.WIDE R26, R7, 0x4, R18 ; /* 0x00000004071a7825 */
/* 0x002fc800078e0212 */
/*0460*/ FFMA R23, R14, R15, R23 ; /* 0x0000000f0e177223 */
/* 0x000fe40000000017 */
/*0470*/ LDG.E R15, [R12.64+0x3c] ; /* 0x00003c040c0f7981 */
/* 0x000f28000c1e1900 */
/*0480*/ LDG.E R14, [R26.64] ; /* 0x000000041a0e7981 */
/* 0x000328000c1e1900 */
/*0490*/ LDG.E R19, [R12.64+0x44] ; /* 0x000044040c137981 */
/* 0x001f22000c1e1900 */
/*04a0*/ IMAD.WIDE R26, R7, 0x4, R26 ; /* 0x00000004071a7825 */
/* 0x002fc800078e021a */
/*04b0*/ FFMA R24, R22, R17, R23 ; /* 0x0000001116187223 */
/* 0x004fe40000000017 */
/*04c0*/ LDG.E R17, [R26.64] ; /* 0x000000041a117981 */
/* 0x0000a2000c1e1900 */
/*04d0*/ IMAD.WIDE R22, R7, 0x4, R26 ; /* 0x0000000407167825 */
/* 0x000fca00078e021a */
/*04e0*/ LDG.E R18, [R22.64] ; /* 0x0000000416127981 */
/* 0x0008a2000c1e1900 */
/*04f0*/ FFMA R28, R16, R25, R24 ; /* 0x00000019101c7223 */
/* 0x008fc60000000018 */
/*0500*/ LDG.E R27, [R12.64+0x4c] ; /* 0x00004c040c1b7981 */
/* 0x001ee8000c1e1900 */
/*0510*/ LDG.E R16, [R12.64+0x40] ; /* 0x000040040c107981 */
/* 0x000ea2000c1e1900 */
/*0520*/ IMAD.WIDE R24, R7, 0x4, R22 ; /* 0x0000000407187825 */
/* 0x000fc800078e0216 */
/*0530*/ FFMA R20, R20, R5, R28 ; /* 0x0000000514147223 */
/* 0x020fe4000000001c */
/*0540*/ LDG.E R5, [R24.64] ; /* 0x0000000418057981 */
/* 0x000164000c1e1900 */
/*0550*/ FFMA R22, R8, R29, R20 ; /* 0x0000001d08167223 */
/* 0x010fe40000000014 */
/*0560*/ IMAD.WIDE R24, R7.reuse, 0x4, R24 ; /* 0x0000000407187825 */
/* 0x041fe200078e0218 */
/*0570*/ LDG.E R20, [R12.64+0x48] ; /* 0x000048040c147981 */
/* 0x000f68000c1e1900 */
/*0580*/ LDG.E R8, [R24.64] ; /* 0x0000000418087981 */
/* 0x0000e2000c1e1900 */
/*0590*/ IMAD.WIDE R28, R7, 0x4, R24 ; /* 0x00000004071c7825 */
/* 0x000fc800078e0218 */
/*05a0*/ FFMA R26, R21, R10, R22 ; /* 0x0000000a151a7223 */
/* 0x000fe40000000016 */
/*05b0*/ IMAD.WIDE R22, R7, 0x4, R28 ; /* 0x0000000407167825 */
/* 0x000fe200078e021c */
/*05c0*/ LDG.E R10, [R28.64] ; /* 0x000000041c0a7981 */
/* 0x0002a8000c1e1900 */
/*05d0*/ LDG.E R21, [R12.64+0x50] ; /* 0x000050040c157981 */
/* 0x000ea2000c1e1900 */
/*05e0*/ FFMA R26, R11, R6, R26 ; /* 0x000000060b1a7223 */
/* 0x000fc6000000001a */
/*05f0*/ LDG.E R6, [R22.64] ; /* 0x0000000416067981 */
/* 0x0000a8000c1e1900 */
/*0600*/ LDG.E R11, [R12.64+0x54] ; /* 0x000054040c0b7981 */
/* 0x000ea2000c1e1900 */
/*0610*/ IMAD.WIDE R22, R7, 0x4, R22 ; /* 0x0000000407167825 */
/* 0x001fc800078e0216 */
/*0620*/ FFMA R26, R9, R4, R26 ; /* 0x00000004091a7223 */
/* 0x000fe4000000001a */
/*0630*/ LDG.E R4, [R12.64+0x58] ; /* 0x000058040c047981 */
/* 0x000ea2000c1e1900 */
/*0640*/ IMAD.WIDE R24, R7, 0x4, R22 ; /* 0x0000000407187825 */
/* 0x000fc600078e0216 */
/*0650*/ LDG.E R9, [R22.64] ; /* 0x0000000416097981 */
/* 0x0000a2000c1e1900 */
/*0660*/ FFMA R28, R15, R14, R26 ; /* 0x0000000e0f1c7223 */
/* 0x002fc6000000001a */
/*0670*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0002a8000c1e1900 */
/*0680*/ LDG.E R26, [R12.64+0x5c] ; /* 0x00005c040c1a7981 */
/* 0x000ea2000c1e1900 */
/*0690*/ IMAD.WIDE R14, R7, 0x4, R24 ; /* 0x00000004070e7825 */
/* 0x000fc800078e0218 */
/*06a0*/ FFMA R28, R16, R17, R28 ; /* 0x00000011101c7223 */
/* 0x004fe4000000001c */
/*06b0*/ IMAD.WIDE R16, R7, 0x4, R14 ; /* 0x0000000407107825 */
/* 0x000fe400078e020e */
/*06c0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000524000c1e1900 */
/*06d0*/ FFMA R22, R19, R18, R28 ; /* 0x0000001213167223 */
/* 0x001fe4000000001c */
/*06e0*/ IMAD.WIDE R18, R7, 0x4, R16 ; /* 0x0000000407127825 */
/* 0x000fe200078e0210 */
/*06f0*/ LDG.E R28, [R16.64] ; /* 0x00000004101c7981 */
/* 0x000126000c1e1900 */
/*0700*/ FFMA R20, R20, R5, R22 ; /* 0x0000000514147223 */
/* 0x020fc40000000016 */
/*0710*/ IMAD.WIDE R22, R7, 0x4, R18 ; /* 0x0000000407167825 */
/* 0x000fe200078e0212 */
/*0720*/ LDG.E R5, [R12.64+0x60] ; /* 0x000060040c057981 */
/* 0x000b26000c1e1900 */
/*0730*/ FFMA R8, R27, R8, R20 ; /* 0x000000081b087223 */
/* 0x008fe20000000014 */
/*0740*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000722000c1e1900 */
/*0750*/ IMAD.WIDE R24, R7, 0x4, R22 ; /* 0x0000000407187825 */
/* 0x002fc600078e0216 */
/*0760*/ LDG.E R27, [R12.64+0x64] ; /* 0x000064040c1b7981 */
/* 0x000b28000c1e1900 */
/*0770*/ LDG.E R20, [R12.64+0x68] ; /* 0x000068040c147981 */
/* 0x000b22000c1e1900 */
/*0780*/ FFMA R8, R21, R10, R8 ; /* 0x0000000a15087223 */
/* 0x004fe40000000008 */
/*0790*/ IMAD.WIDE R16, R7, 0x4, R24 ; /* 0x0000000407107825 */
/* 0x001fe200078e0218 */
/*07a0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x0000a8000c1e1900 */
/*07b0*/ LDG.E R21, [R12.64+0x6c] ; /* 0x00006c040c157981 */
/* 0x000aa2000c1e1900 */
/*07c0*/ FFMA R8, R11, R6, R8 ; /* 0x000000060b087223 */
/* 0x000fc60000000008 */
/*07d0*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x0002a2000c1e1900 */
/*07e0*/ IMAD.WIDE R10, R7, 0x4, R16 ; /* 0x00000004070a7825 */
/* 0x000fc600078e0210 */
/*07f0*/ LDG.E R19, [R12.64+0x70] ; /* 0x000070040c137981 */
/* 0x008ae8000c1e1900 */
/*0800*/ LDG.E R6, [R16.64] ; /* 0x0000000410067981 */
/* 0x000ae8000c1e1900 */
/*0810*/ LDG.E R23, [R12.64+0x74] ; /* 0x000074040c177981 */
/* 0x0010e8000c1e1900 */
/*0820*/ LDG.E R25, [R12.64+0x78] ; /* 0x000078040c197981 */
/* 0x0020e2000c1e1900 */
/*0830*/ FFMA R16, R4, R9, R8 ; /* 0x0000000904107223 */
/* 0x020fc40000000008 */
/*0840*/ IMAD.WIDE R8, R7, 0x4, R10 ; /* 0x0000000407087825 */
/* 0x000fe200078e020a */
/*0850*/ LDG.E R4, [R10.64] ; /* 0x000000040a047981 */
/* 0x000366000c1e1900 */
/*0860*/ FFMA R26, R26, R29, R16 ; /* 0x0000001d1a1a7223 */
/* 0x000fe20000000010 */
/*0870*/ LDG.E R24, [R8.64] ; /* 0x0000000408187981 */
/* 0x000f68000c1e1900 */
/*0880*/ LDG.E R29, [R12.64+0x7c] ; /* 0x00007c040c1d7981 */
/* 0x000162000c1e1900 */
/*0890*/ IADD3 R2, R2, 0x20, RZ ; /* 0x0000002002027810 */
/* 0x000fc80007ffe0ff */
/*08a0*/ ISETP.GE.AND P1, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fe20003f26270 */
/*08b0*/ IMAD.WIDE R10, R7, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x002fe200078e0208 */
/*08c0*/ IADD3 R12, P2, R12, 0x80, RZ ; /* 0x000000800c0c7810 */
/* 0x001fc80007f5e0ff */
/*08d0*/ IADD3.X R13, RZ, R13, RZ, P2, !PT ; /* 0x0000000dff0d7210 */
/* 0x000fe200017fe4ff */
/*08e0*/ FFMA R5, R5, R14, R26 ; /* 0x0000000e05057223 */
/* 0x010fc8000000001a */
/*08f0*/ FFMA R5, R27, R28, R5 ; /* 0x0000001c1b057223 */
/* 0x000fc80000000005 */
/*0900*/ FFMA R5, R20, R18, R5 ; /* 0x0000001214057223 */
/* 0x000fc80000000005 */
/*0910*/ FFMA R22, R21, R22, R5 ; /* 0x0000001615167223 */
/* 0x004fc80000000005 */
/*0920*/ FFMA R15, R19, R15, R22 ; /* 0x0000000f130f7223 */
/* 0x008fc80000000016 */
/*0930*/ FFMA R6, R23, R6, R15 ; /* 0x0000000617067223 */
/* 0x000fc8000000000f */
/*0940*/ FFMA R4, R25, R4, R6 ; /* 0x0000000419047223 */
/* 0x020fc80000000006 */
/*0950*/ FFMA R18, R29, R24, R4 ; /* 0x000000181d127223 */
/* 0x000fe20000000004 */
/*0960*/ @!P1 BRA 0x110 ; /* 0xfffff7a000009947 */
/* 0x000fea000383ffff */
/*0970*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0980*/ LEA R2, P0, R0, c[0x0][0x188], 0x2 ; /* 0x0000620000027a11 */
/* 0x000fe200078010ff */
/*0990*/ FMUL R5, R18, c[0x0][0x16c] ; /* 0x00005b0012057a20 */
/* 0x000fc60000400000 */
/*09a0*/ LEA.HI.X R3, R0, c[0x0][0x18c], R3, 0x2, P0 ; /* 0x0000630000037a11 */
/* 0x000fca00000f1403 */
/*09b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*09c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*09d0*/ BRA 0x9d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void sgemvn_kernel1_fermi(int n, int m, int n1, float alpha, float* A, int lda, float *x, float *y)
{
int ind = blockIdx.x*num_threads + threadIdx.x;
A += ind;
float res = 0.f;
for(int i=0; i<n1; i += sgemv_bs ){
#pragma unroll
for(int j=0; j < sgemv_bs ; j++){
res += A[0] * x[j];
A += lda;
}
x += sgemv_bs;
}
#if 0
if (m>n1){
for(int j=0; j<(m-n1); j++){
res += A[0] * x[j];
A += lda;
}
}
#endif
if (ind<n)
y[ind] = alpha * res;
} | .file "tmpxft_001187e7_00000000-6_sgemvn_kernel1_fermi.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z20sgemvn_kernel1_fermiiiifPfiS_S_iiifPfiS_S_
.type _Z49__device_stub__Z20sgemvn_kernel1_fermiiiifPfiS_S_iiifPfiS_S_, @function
_Z49__device_stub__Z20sgemvn_kernel1_fermiiiifPfiS_S_iiifPfiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movss %xmm0, 32(%rsp)
movq %rcx, 24(%rsp)
movl %r8d, 20(%rsp)
movq %r9, 8(%rsp)
movq 208(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movq %rsp, %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z20sgemvn_kernel1_fermiiiifPfiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z20sgemvn_kernel1_fermiiiifPfiS_S_iiifPfiS_S_, .-_Z49__device_stub__Z20sgemvn_kernel1_fermiiiifPfiS_S_iiifPfiS_S_
.globl _Z20sgemvn_kernel1_fermiiiifPfiS_S_
.type _Z20sgemvn_kernel1_fermiiiifPfiS_S_, @function
_Z20sgemvn_kernel1_fermiiiifPfiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z49__device_stub__Z20sgemvn_kernel1_fermiiiifPfiS_S_iiifPfiS_S_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20sgemvn_kernel1_fermiiiifPfiS_S_, .-_Z20sgemvn_kernel1_fermiiiifPfiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20sgemvn_kernel1_fermiiiifPfiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20sgemvn_kernel1_fermiiiifPfiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void sgemvn_kernel1_fermi(int n, int m, int n1, float alpha, float* A, int lda, float *x, float *y)
{
int ind = blockIdx.x*num_threads + threadIdx.x;
A += ind;
float res = 0.f;
for(int i=0; i<n1; i += sgemv_bs ){
#pragma unroll
for(int j=0; j < sgemv_bs ; j++){
res += A[0] * x[j];
A += lda;
}
x += sgemv_bs;
}
#if 0
if (m>n1){
for(int j=0; j<(m-n1); j++){
res += A[0] * x[j];
A += lda;
}
}
#endif
if (ind<n)
y[ind] = alpha * res;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sgemvn_kernel1_fermi(int n, int m, int n1, float alpha, float* A, int lda, float *x, float *y)
{
int ind = blockIdx.x*num_threads + threadIdx.x;
A += ind;
float res = 0.f;
for(int i=0; i<n1; i += sgemv_bs ){
#pragma unroll
for(int j=0; j < sgemv_bs ; j++){
res += A[0] * x[j];
A += lda;
}
x += sgemv_bs;
}
#if 0
if (m>n1){
for(int j=0; j<(m-n1); j++){
res += A[0] * x[j];
A += lda;
}
}
#endif
if (ind<n)
y[ind] = alpha * res;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sgemvn_kernel1_fermi(int n, int m, int n1, float alpha, float* A, int lda, float *x, float *y)
{
int ind = blockIdx.x*num_threads + threadIdx.x;
A += ind;
float res = 0.f;
for(int i=0; i<n1; i += sgemv_bs ){
#pragma unroll
for(int j=0; j < sgemv_bs ; j++){
res += A[0] * x[j];
A += lda;
}
x += sgemv_bs;
}
#if 0
if (m>n1){
for(int j=0; j<(m-n1); j++){
res += A[0] * x[j];
A += lda;
}
}
#endif
if (ind<n)
y[ind] = alpha * res;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20sgemvn_kernel1_fermiiiifPfiS_S_
.globl _Z20sgemvn_kernel1_fermiiiifPfiS_S_
.p2align 8
.type _Z20sgemvn_kernel1_fermiiiifPfiS_S_,@function
_Z20sgemvn_kernel1_fermiiiifPfiS_S_:
s_load_b32 s6, s[0:1], 0x8
v_lshl_add_u32 v0, s15, 7, v0
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s6, 1
s_cbranch_scc1 .LBB0_3
s_clause 0x2
s_load_b32 s4, s[0:1], 0x18
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x20
v_lshlrev_b64 v[2:3], 2, v[0:1]
v_mov_b32_e32 v4, 0
s_mov_b32 s7, 0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s5, s4, 31
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_lshl_b64 s[4:5], s[4:5], 2
.LBB0_2:
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_add_co_u32 v5, vcc_lo, v2, s4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo
global_load_b32 v7, v[2:3], off
s_add_i32 s7, s7, 32
global_load_b32 v8, v[5:6], off
v_add_co_u32 v2, vcc_lo, v5, s4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo
s_clause 0x1
global_load_b32 v9, v[2:3], off
global_load_b32 v10, v[5:6], off
v_add_co_u32 v2, vcc_lo, v5, s4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo
s_clause 0x1
global_load_b32 v11, v[2:3], off
global_load_b32 v12, v[5:6], off
v_add_co_u32 v2, vcc_lo, v5, s4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo
global_load_b32 v13, v[2:3], off
v_add_co_u32 v2, vcc_lo, v5, s4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v6, vcc_lo
global_load_b32 v14, v[5:6], off
v_add_co_u32 v5, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo
global_load_b32 v15, v[2:3], off
v_add_co_u32 v2, vcc_lo, v5, s4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v6, vcc_lo
global_load_b32 v16, v[5:6], off
v_add_co_u32 v5, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo
global_load_b32 v17, v[2:3], off
v_add_co_u32 v2, vcc_lo, v5, s4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v6, vcc_lo
global_load_b32 v18, v[5:6], off
v_add_co_u32 v5, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo
global_load_b32 v19, v[2:3], off
v_add_co_u32 v2, vcc_lo, v5, s4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v6, vcc_lo
global_load_b32 v20, v[5:6], off
v_add_co_u32 v5, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo
global_load_b32 v21, v[2:3], off
v_add_co_u32 v2, vcc_lo, v5, s4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v6, vcc_lo
global_load_b32 v22, v[5:6], off
v_add_co_u32 v5, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo
global_load_b32 v23, v[2:3], off
v_add_co_u32 v2, vcc_lo, v5, s4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v6, vcc_lo
global_load_b32 v24, v[5:6], off
v_add_co_u32 v5, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo
global_load_b32 v25, v[2:3], off
v_add_co_u32 v2, vcc_lo, v5, s4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v6, vcc_lo
global_load_b32 v26, v[5:6], off
v_add_co_u32 v5, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo
global_load_b32 v27, v[2:3], off
v_add_co_u32 v2, vcc_lo, v5, s4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v6, vcc_lo
global_load_b32 v28, v[5:6], off
v_add_co_u32 v5, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo
global_load_b32 v29, v[2:3], off
v_add_co_u32 v2, vcc_lo, v5, s4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v6, vcc_lo
global_load_b32 v30, v[5:6], off
v_add_co_u32 v5, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo
global_load_b32 v31, v[2:3], off
v_add_co_u32 v2, vcc_lo, v5, s4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v6, vcc_lo
global_load_b32 v32, v[5:6], off
v_add_co_u32 v5, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo
global_load_b32 v33, v[2:3], off
v_add_co_u32 v2, vcc_lo, v5, s4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v6, vcc_lo
global_load_b32 v34, v[5:6], off
v_add_co_u32 v5, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo
global_load_b32 v35, v[2:3], off
v_add_co_u32 v2, vcc_lo, v5, s4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v6, vcc_lo
global_load_b32 v5, v[5:6], off
global_load_b32 v6, v[2:3], off
v_add_co_u32 v2, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_clause 0x1
s_load_b256 s[8:15], s[2:3], 0x0
s_load_b256 s[16:23], s[2:3], 0x20
global_load_b32 v36, v[2:3], off
v_add_co_u32 v2, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_waitcnt vmcnt(31) lgkmcnt(0)
v_fmac_f32_e32 v4, s8, v7
s_waitcnt vmcnt(30)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, s9, v8
s_waitcnt vmcnt(29)
v_fmac_f32_e32 v4, s10, v9
s_waitcnt vmcnt(28)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, s11, v10
s_waitcnt vmcnt(27)
v_fmac_f32_e32 v4, s12, v11
s_waitcnt vmcnt(26)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, s13, v12
s_waitcnt vmcnt(25)
v_fmac_f32_e32 v4, s14, v13
s_waitcnt vmcnt(24)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, s15, v14
s_load_b256 s[8:15], s[2:3], 0x40
s_waitcnt vmcnt(23)
v_fmac_f32_e32 v4, s16, v15
s_waitcnt vmcnt(22)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, s17, v16
s_waitcnt vmcnt(21)
v_fmac_f32_e32 v4, s18, v17
s_waitcnt vmcnt(20)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, s19, v18
s_waitcnt vmcnt(19)
v_fmac_f32_e32 v4, s20, v19
s_waitcnt vmcnt(18)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, s21, v20
s_waitcnt vmcnt(17)
v_fmac_f32_e32 v4, s22, v21
s_waitcnt vmcnt(16)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v4, s23, v22
s_load_b256 s[16:23], s[2:3], 0x60
s_add_u32 s2, s2, 0x80
s_addc_u32 s3, s3, 0
s_cmp_lt_i32 s7, s6
s_waitcnt vmcnt(15) lgkmcnt(0)
v_fmac_f32_e32 v4, s8, v23
s_waitcnt vmcnt(14)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, s9, v24
s_waitcnt vmcnt(13)
v_fmac_f32_e32 v4, s10, v25
s_waitcnt vmcnt(12)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, s11, v26
s_waitcnt vmcnt(11)
v_fmac_f32_e32 v4, s12, v27
s_waitcnt vmcnt(10)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, s13, v28
s_waitcnt vmcnt(9)
v_fmac_f32_e32 v4, s14, v29
s_waitcnt vmcnt(8)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, s15, v30
s_waitcnt vmcnt(7)
v_fmac_f32_e32 v4, s16, v31
s_waitcnt vmcnt(6)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, s17, v32
s_waitcnt vmcnt(5)
v_fmac_f32_e32 v4, s18, v33
s_waitcnt vmcnt(4)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, s19, v34
s_waitcnt vmcnt(3)
v_fmac_f32_e32 v4, s20, v35
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, s21, v5
s_waitcnt vmcnt(1)
v_fmac_f32_e32 v4, s22, v6
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v4, s23, v36
s_cbranch_scc1 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v4, 0
.LBB0_4:
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_6
s_clause 0x1
s_load_b32 s2, s[0:1], 0xc
s_load_b64 s[0:1], s[0:1], 0x28
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_mul_f32_e32 v2, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20sgemvn_kernel1_fermiiiifPfiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 48
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 37
.amdhsa_next_free_sgpr 24
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20sgemvn_kernel1_fermiiiifPfiS_S_, .Lfunc_end0-_Z20sgemvn_kernel1_fermiiiifPfiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 48
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20sgemvn_kernel1_fermiiiifPfiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: _Z20sgemvn_kernel1_fermiiiifPfiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 37
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sgemvn_kernel1_fermi(int n, int m, int n1, float alpha, float* A, int lda, float *x, float *y)
{
int ind = blockIdx.x*num_threads + threadIdx.x;
A += ind;
float res = 0.f;
for(int i=0; i<n1; i += sgemv_bs ){
#pragma unroll
for(int j=0; j < sgemv_bs ; j++){
res += A[0] * x[j];
A += lda;
}
x += sgemv_bs;
}
#if 0
if (m>n1){
for(int j=0; j<(m-n1); j++){
res += A[0] * x[j];
A += lda;
}
}
#endif
if (ind<n)
y[ind] = alpha * res;
} | .text
.file "sgemvn_kernel1_fermi.hip"
.globl _Z35__device_stub__sgemvn_kernel1_fermiiiifPfiS_S_ # -- Begin function _Z35__device_stub__sgemvn_kernel1_fermiiiifPfiS_S_
.p2align 4, 0x90
.type _Z35__device_stub__sgemvn_kernel1_fermiiiifPfiS_S_,@function
_Z35__device_stub__sgemvn_kernel1_fermiiiifPfiS_S_: # @_Z35__device_stub__sgemvn_kernel1_fermiiiifPfiS_S_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movss %xmm0, 16(%rsp)
movq %rcx, 88(%rsp)
movl %r8d, 12(%rsp)
movq %r9, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rax
movq %rax, 144(%rsp)
leaq 176(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20sgemvn_kernel1_fermiiiifPfiS_S_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z35__device_stub__sgemvn_kernel1_fermiiiifPfiS_S_, .Lfunc_end0-_Z35__device_stub__sgemvn_kernel1_fermiiiifPfiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20sgemvn_kernel1_fermiiiifPfiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20sgemvn_kernel1_fermiiiifPfiS_S_,@object # @_Z20sgemvn_kernel1_fermiiiifPfiS_S_
.section .rodata,"a",@progbits
.globl _Z20sgemvn_kernel1_fermiiiifPfiS_S_
.p2align 3, 0x0
_Z20sgemvn_kernel1_fermiiiifPfiS_S_:
.quad _Z35__device_stub__sgemvn_kernel1_fermiiiifPfiS_S_
.size _Z20sgemvn_kernel1_fermiiiifPfiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20sgemvn_kernel1_fermiiiifPfiS_S_"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__sgemvn_kernel1_fermiiiifPfiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20sgemvn_kernel1_fermiiiifPfiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z20sgemvn_kernel1_fermiiiifPfiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R18, -RZ, RZ, 0, 0 ; /* 0x00000000ff127435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ ISETP.GE.AND P1, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe40003f26270 */
/*0070*/ LEA R0, R0, R3, 0x7 ; /* 0x0000000300007211 */
/* 0x001fc800078e38ff */
/*0080*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fe40003f06270 */
/*0090*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fca0000011400 */
/*00a0*/ @!P1 BRA 0x970 ; /* 0x000008c000009947 */
/* 0x000fec0003800000 */
/*00b0*/ LEA R10, P1, R0.reuse, c[0x0][0x170], 0x2 ; /* 0x00005c00000a7a11 */
/* 0x040fe400078210ff */
/*00c0*/ MOV R12, c[0x0][0x180] ; /* 0x00006000000c7a02 */
/* 0x000fe40000000f00 */
/*00d0*/ MOV R13, c[0x0][0x184] ; /* 0x00006100000d7a02 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R18, RZ ; /* 0x000000ff00127202 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fe40000000f00 */
/*0100*/ LEA.HI.X R11, R0, c[0x0][0x174], R3, 0x2, P1 ; /* 0x00005d00000b7a11 */
/* 0x000fc800008f1403 */
/*0110*/ MOV R7, c[0x0][0x178] ; /* 0x00005e0000077a02 */
/* 0x000fe20000000f00 */
/*0120*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x0000a8000c1e1900 */
/*0130*/ IMAD.WIDE R26, R7.reuse, 0x4, R10 ; /* 0x00000004071a7825 */
/* 0x040fe200078e020a */
/*0140*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x000ea8000c1e1900 */
/*0150*/ LDG.E R25, [R12.64+0x4] ; /* 0x000004040c197981 */
/* 0x000ee2000c1e1900 */
/*0160*/ IMAD.WIDE R14, R7, 0x4, R26 ; /* 0x00000004070e7825 */
/* 0x000fc600078e021a */
/*0170*/ LDG.E R16, [R26.64] ; /* 0x000000041a107981 */
/* 0x0002e8000c1e1900 */
/*0180*/ LDG.E R20, [R14.64] ; /* 0x000000040e147981 */
/* 0x000968000c1e1900 */
/*0190*/ LDG.E R5, [R12.64+0x8] ; /* 0x000008040c057981 */
/* 0x000f68000c1e1900 */
/*01a0*/ LDG.E R23, [R12.64+0xc] ; /* 0x00000c040c177981 */
/* 0x000f62000c1e1900 */
/*01b0*/ IMAD.WIDE R14, R7, 0x4, R14 ; /* 0x00000004070e7825 */
/* 0x010fc600078e020e */
/*01c0*/ LDG.E R21, [R12.64+0x10] ; /* 0x000010040c157981 */
/* 0x000f28000c1e1900 */
/*01d0*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000322000c1e1900 */
/*01e0*/ IMAD.WIDE R28, R7, 0x4, R14 ; /* 0x00000004071c7825 */
/* 0x000fc600078e020e */
/*01f0*/ LDG.E R6, [R12.64+0x14] ; /* 0x000014040c067981 */
/* 0x000f28000c1e1900 */
/*0200*/ LDG.E R10, [R28.64] ; /* 0x000000041c0a7981 */
/* 0x001128000c1e1900 */
/*0210*/ LDG.E R4, [R12.64+0x18] ; /* 0x000018040c047981 */
/* 0x000f28000c1e1900 */
/*0220*/ LDG.E R14, [R12.64+0x1c] ; /* 0x00001c040c0e7981 */
/* 0x002f22000c1e1900 */
/*0230*/ IMAD.WIDE R28, R7, 0x4, R28 ; /* 0x00000004071c7825 */
/* 0x001fc600078e021c */
/*0240*/ LDG.E R22, [R12.64+0x20] ; /* 0x000020040c167981 */
/* 0x000f28000c1e1900 */
/*0250*/ LDG.E R11, [R28.64] ; /* 0x000000041c0b7981 */
/* 0x000122000c1e1900 */
/*0260*/ IMAD.WIDE R26, R7, 0x4, R28 ; /* 0x00000004071a7825 */
/* 0x000fca00078e021c */
/*0270*/ LDG.E R9, [R26.64] ; /* 0x000000041a097981 */
/* 0x000324000c1e1900 */
/*0280*/ IMAD.WIDE R26, R7, 0x4, R26 ; /* 0x00000004071a7825 */
/* 0x002fca00078e021a */
/*0290*/ LDG.E R15, [R26.64] ; /* 0x000000041a0f7981 */
/* 0x000322000c1e1900 */
/*02a0*/ IMAD.WIDE R28, R7, 0x4, R26 ; /* 0x00000004071c7825 */
/* 0x001fc800078e021a */
/*02b0*/ FFMA R24, R19, R17, R18 ; /* 0x0000001113187223 */
/* 0x004fe40000000012 */
/*02c0*/ IMAD.WIDE R18, R7, 0x4, R28 ; /* 0x0000000407127825 */
/* 0x000fe200078e021c */
/*02d0*/ LDG.E R17, [R28.64] ; /* 0x000000041c117981 */
/* 0x0000a6000c1e1900 */
/*02e0*/ FFMA R24, R25, R16, R24 ; /* 0x0000001019187223 */
/* 0x008fe40000000018 */
/*02f0*/ LDG.E R16, [R12.64+0x24] ; /* 0x000024040c107981 */
/* 0x000ee8000c1e1900 */
/*0300*/ LDG.E R25, [R18.64] ; /* 0x0000000412197981 */
/* 0x0000e2000c1e1900 */
/*0310*/ FFMA R24, R5, R20, R24 ; /* 0x0000001405187223 */
/* 0x020fc60000000018 */
/*0320*/ LDG.E R20, [R12.64+0x28] ; /* 0x000028040c147981 */
/* 0x000f62000c1e1900 */
/*0330*/ IMAD.WIDE R18, R7, 0x4, R18 ; /* 0x0000000407127825 */
/* 0x001fca00078e0212 */
/*0340*/ LDG.E R5, [R18.64] ; /* 0x0000000412057981 */
/* 0x000162000c1e1900 */
/*0350*/ IMAD.WIDE R26, R7, 0x4, R18 ; /* 0x00000004071a7825 */
/* 0x002fc800078e0212 */
/*0360*/ FFMA R23, R23, R8, R24 ; /* 0x0000000817177223 */
/* 0x010fe20000000018 */
/*0370*/ LDG.E R29, [R26.64] ; /* 0x000000041a1d7981 */
/* 0x000328000c1e1900 */
/*0380*/ LDG.E R8, [R12.64+0x2c] ; /* 0x00002c040c087981 */
/* 0x000f22000c1e1900 */
/*0390*/ FFMA R23, R21, R10, R23 ; /* 0x0000000a15177223 */
/* 0x000fc60000000017 */
/*03a0*/ LDG.E R21, [R12.64+0x30] ; /* 0x000030040c157981 */
/* 0x000f22000c1e1900 */
/*03b0*/ IMAD.WIDE R26, R7, 0x4, R26 ; /* 0x00000004071a7825 */
/* 0x002fca00078e021a */
/*03c0*/ LDG.E R10, [R26.64] ; /* 0x000000041a0a7981 */
/* 0x000322000c1e1900 */
/*03d0*/ IMAD.WIDE R18, R7, 0x4, R26 ; /* 0x0000000407127825 */
/* 0x001fc800078e021a */
/*03e0*/ FFMA R23, R6, R11, R23 ; /* 0x0000000b06177223 */
/* 0x000fe40000000017 */
/*03f0*/ LDG.E R11, [R12.64+0x34] ; /* 0x000034040c0b7981 */
/* 0x000f28000c1e1900 */
/*0400*/ LDG.E R6, [R18.64] ; /* 0x0000000412067981 */
/* 0x000122000c1e1900 */
/*0410*/ FFMA R23, R4, R9, R23 ; /* 0x0000000904177223 */
/* 0x000fc60000000017 */
/*0420*/ LDG.E R9, [R12.64+0x38] ; /* 0x000038040c097981 */
/* 0x000f22000c1e1900 */
/*0430*/ IMAD.WIDE R18, R7, 0x4, R18 ; /* 0x0000000407127825 */
/* 0x001fca00078e0212 */
/*0440*/ LDG.E R4, [R18.64] ; /* 0x0000000412047981 */
/* 0x000122000c1e1900 */
/*0450*/ IMAD.WIDE R26, R7, 0x4, R18 ; /* 0x00000004071a7825 */
/* 0x002fc800078e0212 */
/*0460*/ FFMA R23, R14, R15, R23 ; /* 0x0000000f0e177223 */
/* 0x000fe40000000017 */
/*0470*/ LDG.E R15, [R12.64+0x3c] ; /* 0x00003c040c0f7981 */
/* 0x000f28000c1e1900 */
/*0480*/ LDG.E R14, [R26.64] ; /* 0x000000041a0e7981 */
/* 0x000328000c1e1900 */
/*0490*/ LDG.E R19, [R12.64+0x44] ; /* 0x000044040c137981 */
/* 0x001f22000c1e1900 */
/*04a0*/ IMAD.WIDE R26, R7, 0x4, R26 ; /* 0x00000004071a7825 */
/* 0x002fc800078e021a */
/*04b0*/ FFMA R24, R22, R17, R23 ; /* 0x0000001116187223 */
/* 0x004fe40000000017 */
/*04c0*/ LDG.E R17, [R26.64] ; /* 0x000000041a117981 */
/* 0x0000a2000c1e1900 */
/*04d0*/ IMAD.WIDE R22, R7, 0x4, R26 ; /* 0x0000000407167825 */
/* 0x000fca00078e021a */
/*04e0*/ LDG.E R18, [R22.64] ; /* 0x0000000416127981 */
/* 0x0008a2000c1e1900 */
/*04f0*/ FFMA R28, R16, R25, R24 ; /* 0x00000019101c7223 */
/* 0x008fc60000000018 */
/*0500*/ LDG.E R27, [R12.64+0x4c] ; /* 0x00004c040c1b7981 */
/* 0x001ee8000c1e1900 */
/*0510*/ LDG.E R16, [R12.64+0x40] ; /* 0x000040040c107981 */
/* 0x000ea2000c1e1900 */
/*0520*/ IMAD.WIDE R24, R7, 0x4, R22 ; /* 0x0000000407187825 */
/* 0x000fc800078e0216 */
/*0530*/ FFMA R20, R20, R5, R28 ; /* 0x0000000514147223 */
/* 0x020fe4000000001c */
/*0540*/ LDG.E R5, [R24.64] ; /* 0x0000000418057981 */
/* 0x000164000c1e1900 */
/*0550*/ FFMA R22, R8, R29, R20 ; /* 0x0000001d08167223 */
/* 0x010fe40000000014 */
/*0560*/ IMAD.WIDE R24, R7.reuse, 0x4, R24 ; /* 0x0000000407187825 */
/* 0x041fe200078e0218 */
/*0570*/ LDG.E R20, [R12.64+0x48] ; /* 0x000048040c147981 */
/* 0x000f68000c1e1900 */
/*0580*/ LDG.E R8, [R24.64] ; /* 0x0000000418087981 */
/* 0x0000e2000c1e1900 */
/*0590*/ IMAD.WIDE R28, R7, 0x4, R24 ; /* 0x00000004071c7825 */
/* 0x000fc800078e0218 */
/*05a0*/ FFMA R26, R21, R10, R22 ; /* 0x0000000a151a7223 */
/* 0x000fe40000000016 */
/*05b0*/ IMAD.WIDE R22, R7, 0x4, R28 ; /* 0x0000000407167825 */
/* 0x000fe200078e021c */
/*05c0*/ LDG.E R10, [R28.64] ; /* 0x000000041c0a7981 */
/* 0x0002a8000c1e1900 */
/*05d0*/ LDG.E R21, [R12.64+0x50] ; /* 0x000050040c157981 */
/* 0x000ea2000c1e1900 */
/*05e0*/ FFMA R26, R11, R6, R26 ; /* 0x000000060b1a7223 */
/* 0x000fc6000000001a */
/*05f0*/ LDG.E R6, [R22.64] ; /* 0x0000000416067981 */
/* 0x0000a8000c1e1900 */
/*0600*/ LDG.E R11, [R12.64+0x54] ; /* 0x000054040c0b7981 */
/* 0x000ea2000c1e1900 */
/*0610*/ IMAD.WIDE R22, R7, 0x4, R22 ; /* 0x0000000407167825 */
/* 0x001fc800078e0216 */
/*0620*/ FFMA R26, R9, R4, R26 ; /* 0x00000004091a7223 */
/* 0x000fe4000000001a */
/*0630*/ LDG.E R4, [R12.64+0x58] ; /* 0x000058040c047981 */
/* 0x000ea2000c1e1900 */
/*0640*/ IMAD.WIDE R24, R7, 0x4, R22 ; /* 0x0000000407187825 */
/* 0x000fc600078e0216 */
/*0650*/ LDG.E R9, [R22.64] ; /* 0x0000000416097981 */
/* 0x0000a2000c1e1900 */
/*0660*/ FFMA R28, R15, R14, R26 ; /* 0x0000000e0f1c7223 */
/* 0x002fc6000000001a */
/*0670*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0002a8000c1e1900 */
/*0680*/ LDG.E R26, [R12.64+0x5c] ; /* 0x00005c040c1a7981 */
/* 0x000ea2000c1e1900 */
/*0690*/ IMAD.WIDE R14, R7, 0x4, R24 ; /* 0x00000004070e7825 */
/* 0x000fc800078e0218 */
/*06a0*/ FFMA R28, R16, R17, R28 ; /* 0x00000011101c7223 */
/* 0x004fe4000000001c */
/*06b0*/ IMAD.WIDE R16, R7, 0x4, R14 ; /* 0x0000000407107825 */
/* 0x000fe400078e020e */
/*06c0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000524000c1e1900 */
/*06d0*/ FFMA R22, R19, R18, R28 ; /* 0x0000001213167223 */
/* 0x001fe4000000001c */
/*06e0*/ IMAD.WIDE R18, R7, 0x4, R16 ; /* 0x0000000407127825 */
/* 0x000fe200078e0210 */
/*06f0*/ LDG.E R28, [R16.64] ; /* 0x00000004101c7981 */
/* 0x000126000c1e1900 */
/*0700*/ FFMA R20, R20, R5, R22 ; /* 0x0000000514147223 */
/* 0x020fc40000000016 */
/*0710*/ IMAD.WIDE R22, R7, 0x4, R18 ; /* 0x0000000407167825 */
/* 0x000fe200078e0212 */
/*0720*/ LDG.E R5, [R12.64+0x60] ; /* 0x000060040c057981 */
/* 0x000b26000c1e1900 */
/*0730*/ FFMA R8, R27, R8, R20 ; /* 0x000000081b087223 */
/* 0x008fe20000000014 */
/*0740*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000722000c1e1900 */
/*0750*/ IMAD.WIDE R24, R7, 0x4, R22 ; /* 0x0000000407187825 */
/* 0x002fc600078e0216 */
/*0760*/ LDG.E R27, [R12.64+0x64] ; /* 0x000064040c1b7981 */
/* 0x000b28000c1e1900 */
/*0770*/ LDG.E R20, [R12.64+0x68] ; /* 0x000068040c147981 */
/* 0x000b22000c1e1900 */
/*0780*/ FFMA R8, R21, R10, R8 ; /* 0x0000000a15087223 */
/* 0x004fe40000000008 */
/*0790*/ IMAD.WIDE R16, R7, 0x4, R24 ; /* 0x0000000407107825 */
/* 0x001fe200078e0218 */
/*07a0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x0000a8000c1e1900 */
/*07b0*/ LDG.E R21, [R12.64+0x6c] ; /* 0x00006c040c157981 */
/* 0x000aa2000c1e1900 */
/*07c0*/ FFMA R8, R11, R6, R8 ; /* 0x000000060b087223 */
/* 0x000fc60000000008 */
/*07d0*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x0002a2000c1e1900 */
/*07e0*/ IMAD.WIDE R10, R7, 0x4, R16 ; /* 0x00000004070a7825 */
/* 0x000fc600078e0210 */
/*07f0*/ LDG.E R19, [R12.64+0x70] ; /* 0x000070040c137981 */
/* 0x008ae8000c1e1900 */
/*0800*/ LDG.E R6, [R16.64] ; /* 0x0000000410067981 */
/* 0x000ae8000c1e1900 */
/*0810*/ LDG.E R23, [R12.64+0x74] ; /* 0x000074040c177981 */
/* 0x0010e8000c1e1900 */
/*0820*/ LDG.E R25, [R12.64+0x78] ; /* 0x000078040c197981 */
/* 0x0020e2000c1e1900 */
/*0830*/ FFMA R16, R4, R9, R8 ; /* 0x0000000904107223 */
/* 0x020fc40000000008 */
/*0840*/ IMAD.WIDE R8, R7, 0x4, R10 ; /* 0x0000000407087825 */
/* 0x000fe200078e020a */
/*0850*/ LDG.E R4, [R10.64] ; /* 0x000000040a047981 */
/* 0x000366000c1e1900 */
/*0860*/ FFMA R26, R26, R29, R16 ; /* 0x0000001d1a1a7223 */
/* 0x000fe20000000010 */
/*0870*/ LDG.E R24, [R8.64] ; /* 0x0000000408187981 */
/* 0x000f68000c1e1900 */
/*0880*/ LDG.E R29, [R12.64+0x7c] ; /* 0x00007c040c1d7981 */
/* 0x000162000c1e1900 */
/*0890*/ IADD3 R2, R2, 0x20, RZ ; /* 0x0000002002027810 */
/* 0x000fc80007ffe0ff */
/*08a0*/ ISETP.GE.AND P1, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fe20003f26270 */
/*08b0*/ IMAD.WIDE R10, R7, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x002fe200078e0208 */
/*08c0*/ IADD3 R12, P2, R12, 0x80, RZ ; /* 0x000000800c0c7810 */
/* 0x001fc80007f5e0ff */
/*08d0*/ IADD3.X R13, RZ, R13, RZ, P2, !PT ; /* 0x0000000dff0d7210 */
/* 0x000fe200017fe4ff */
/*08e0*/ FFMA R5, R5, R14, R26 ; /* 0x0000000e05057223 */
/* 0x010fc8000000001a */
/*08f0*/ FFMA R5, R27, R28, R5 ; /* 0x0000001c1b057223 */
/* 0x000fc80000000005 */
/*0900*/ FFMA R5, R20, R18, R5 ; /* 0x0000001214057223 */
/* 0x000fc80000000005 */
/*0910*/ FFMA R22, R21, R22, R5 ; /* 0x0000001615167223 */
/* 0x004fc80000000005 */
/*0920*/ FFMA R15, R19, R15, R22 ; /* 0x0000000f130f7223 */
/* 0x008fc80000000016 */
/*0930*/ FFMA R6, R23, R6, R15 ; /* 0x0000000617067223 */
/* 0x000fc8000000000f */
/*0940*/ FFMA R4, R25, R4, R6 ; /* 0x0000000419047223 */
/* 0x020fc80000000006 */
/*0950*/ FFMA R18, R29, R24, R4 ; /* 0x000000181d127223 */
/* 0x000fe20000000004 */
/*0960*/ @!P1 BRA 0x110 ; /* 0xfffff7a000009947 */
/* 0x000fea000383ffff */
/*0970*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0980*/ LEA R2, P0, R0, c[0x0][0x188], 0x2 ; /* 0x0000620000027a11 */
/* 0x000fe200078010ff */
/*0990*/ FMUL R5, R18, c[0x0][0x16c] ; /* 0x00005b0012057a20 */
/* 0x000fc60000400000 */
/*09a0*/ LEA.HI.X R3, R0, c[0x0][0x18c], R3, 0x2, P0 ; /* 0x0000630000037a11 */
/* 0x000fca00000f1403 */
/*09b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*09c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*09d0*/ BRA 0x9d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20sgemvn_kernel1_fermiiiifPfiS_S_
.globl _Z20sgemvn_kernel1_fermiiiifPfiS_S_
.p2align 8
.type _Z20sgemvn_kernel1_fermiiiifPfiS_S_,@function
_Z20sgemvn_kernel1_fermiiiifPfiS_S_:
s_load_b32 s6, s[0:1], 0x8
v_lshl_add_u32 v0, s15, 7, v0
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s6, 1
s_cbranch_scc1 .LBB0_3
s_clause 0x2
s_load_b32 s4, s[0:1], 0x18
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x20
v_lshlrev_b64 v[2:3], 2, v[0:1]
v_mov_b32_e32 v4, 0
s_mov_b32 s7, 0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s5, s4, 31
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_lshl_b64 s[4:5], s[4:5], 2
.LBB0_2:
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_add_co_u32 v5, vcc_lo, v2, s4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo
global_load_b32 v7, v[2:3], off
s_add_i32 s7, s7, 32
global_load_b32 v8, v[5:6], off
v_add_co_u32 v2, vcc_lo, v5, s4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo
s_clause 0x1
global_load_b32 v9, v[2:3], off
global_load_b32 v10, v[5:6], off
v_add_co_u32 v2, vcc_lo, v5, s4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo
s_clause 0x1
global_load_b32 v11, v[2:3], off
global_load_b32 v12, v[5:6], off
v_add_co_u32 v2, vcc_lo, v5, s4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo
global_load_b32 v13, v[2:3], off
v_add_co_u32 v2, vcc_lo, v5, s4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v6, vcc_lo
global_load_b32 v14, v[5:6], off
v_add_co_u32 v5, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo
global_load_b32 v15, v[2:3], off
v_add_co_u32 v2, vcc_lo, v5, s4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v6, vcc_lo
global_load_b32 v16, v[5:6], off
v_add_co_u32 v5, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo
global_load_b32 v17, v[2:3], off
v_add_co_u32 v2, vcc_lo, v5, s4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v6, vcc_lo
global_load_b32 v18, v[5:6], off
v_add_co_u32 v5, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo
global_load_b32 v19, v[2:3], off
v_add_co_u32 v2, vcc_lo, v5, s4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v6, vcc_lo
global_load_b32 v20, v[5:6], off
v_add_co_u32 v5, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo
global_load_b32 v21, v[2:3], off
v_add_co_u32 v2, vcc_lo, v5, s4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v6, vcc_lo
global_load_b32 v22, v[5:6], off
v_add_co_u32 v5, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo
global_load_b32 v23, v[2:3], off
v_add_co_u32 v2, vcc_lo, v5, s4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v6, vcc_lo
global_load_b32 v24, v[5:6], off
v_add_co_u32 v5, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo
global_load_b32 v25, v[2:3], off
v_add_co_u32 v2, vcc_lo, v5, s4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v6, vcc_lo
global_load_b32 v26, v[5:6], off
v_add_co_u32 v5, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo
global_load_b32 v27, v[2:3], off
v_add_co_u32 v2, vcc_lo, v5, s4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v6, vcc_lo
global_load_b32 v28, v[5:6], off
v_add_co_u32 v5, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo
global_load_b32 v29, v[2:3], off
v_add_co_u32 v2, vcc_lo, v5, s4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v6, vcc_lo
global_load_b32 v30, v[5:6], off
v_add_co_u32 v5, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo
global_load_b32 v31, v[2:3], off
v_add_co_u32 v2, vcc_lo, v5, s4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v6, vcc_lo
global_load_b32 v32, v[5:6], off
v_add_co_u32 v5, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo
global_load_b32 v33, v[2:3], off
v_add_co_u32 v2, vcc_lo, v5, s4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v6, vcc_lo
global_load_b32 v34, v[5:6], off
v_add_co_u32 v5, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo
global_load_b32 v35, v[2:3], off
v_add_co_u32 v2, vcc_lo, v5, s4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v6, vcc_lo
global_load_b32 v5, v[5:6], off
global_load_b32 v6, v[2:3], off
v_add_co_u32 v2, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_clause 0x1
s_load_b256 s[8:15], s[2:3], 0x0
s_load_b256 s[16:23], s[2:3], 0x20
global_load_b32 v36, v[2:3], off
v_add_co_u32 v2, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_waitcnt vmcnt(31) lgkmcnt(0)
v_fmac_f32_e32 v4, s8, v7
s_waitcnt vmcnt(30)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, s9, v8
s_waitcnt vmcnt(29)
v_fmac_f32_e32 v4, s10, v9
s_waitcnt vmcnt(28)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, s11, v10
s_waitcnt vmcnt(27)
v_fmac_f32_e32 v4, s12, v11
s_waitcnt vmcnt(26)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, s13, v12
s_waitcnt vmcnt(25)
v_fmac_f32_e32 v4, s14, v13
s_waitcnt vmcnt(24)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, s15, v14
s_load_b256 s[8:15], s[2:3], 0x40
s_waitcnt vmcnt(23)
v_fmac_f32_e32 v4, s16, v15
s_waitcnt vmcnt(22)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, s17, v16
s_waitcnt vmcnt(21)
v_fmac_f32_e32 v4, s18, v17
s_waitcnt vmcnt(20)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, s19, v18
s_waitcnt vmcnt(19)
v_fmac_f32_e32 v4, s20, v19
s_waitcnt vmcnt(18)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, s21, v20
s_waitcnt vmcnt(17)
v_fmac_f32_e32 v4, s22, v21
s_waitcnt vmcnt(16)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v4, s23, v22
s_load_b256 s[16:23], s[2:3], 0x60
s_add_u32 s2, s2, 0x80
s_addc_u32 s3, s3, 0
s_cmp_lt_i32 s7, s6
s_waitcnt vmcnt(15) lgkmcnt(0)
v_fmac_f32_e32 v4, s8, v23
s_waitcnt vmcnt(14)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, s9, v24
s_waitcnt vmcnt(13)
v_fmac_f32_e32 v4, s10, v25
s_waitcnt vmcnt(12)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, s11, v26
s_waitcnt vmcnt(11)
v_fmac_f32_e32 v4, s12, v27
s_waitcnt vmcnt(10)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, s13, v28
s_waitcnt vmcnt(9)
v_fmac_f32_e32 v4, s14, v29
s_waitcnt vmcnt(8)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, s15, v30
s_waitcnt vmcnt(7)
v_fmac_f32_e32 v4, s16, v31
s_waitcnt vmcnt(6)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, s17, v32
s_waitcnt vmcnt(5)
v_fmac_f32_e32 v4, s18, v33
s_waitcnt vmcnt(4)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, s19, v34
s_waitcnt vmcnt(3)
v_fmac_f32_e32 v4, s20, v35
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, s21, v5
s_waitcnt vmcnt(1)
v_fmac_f32_e32 v4, s22, v6
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v4, s23, v36
s_cbranch_scc1 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v4, 0
.LBB0_4:
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_6
s_clause 0x1
s_load_b32 s2, s[0:1], 0xc
s_load_b64 s[0:1], s[0:1], 0x28
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_mul_f32_e32 v2, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20sgemvn_kernel1_fermiiiifPfiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 48
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 37
.amdhsa_next_free_sgpr 24
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20sgemvn_kernel1_fermiiiifPfiS_S_, .Lfunc_end0-_Z20sgemvn_kernel1_fermiiiifPfiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 48
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20sgemvn_kernel1_fermiiiifPfiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: _Z20sgemvn_kernel1_fermiiiifPfiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 37
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001187e7_00000000-6_sgemvn_kernel1_fermi.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z20sgemvn_kernel1_fermiiiifPfiS_S_iiifPfiS_S_
.type _Z49__device_stub__Z20sgemvn_kernel1_fermiiiifPfiS_S_iiifPfiS_S_, @function
_Z49__device_stub__Z20sgemvn_kernel1_fermiiiifPfiS_S_iiifPfiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movss %xmm0, 32(%rsp)
movq %rcx, 24(%rsp)
movl %r8d, 20(%rsp)
movq %r9, 8(%rsp)
movq 208(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movq %rsp, %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z20sgemvn_kernel1_fermiiiifPfiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z20sgemvn_kernel1_fermiiiifPfiS_S_iiifPfiS_S_, .-_Z49__device_stub__Z20sgemvn_kernel1_fermiiiifPfiS_S_iiifPfiS_S_
.globl _Z20sgemvn_kernel1_fermiiiifPfiS_S_
.type _Z20sgemvn_kernel1_fermiiiifPfiS_S_, @function
_Z20sgemvn_kernel1_fermiiiifPfiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z49__device_stub__Z20sgemvn_kernel1_fermiiiifPfiS_S_iiifPfiS_S_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20sgemvn_kernel1_fermiiiifPfiS_S_, .-_Z20sgemvn_kernel1_fermiiiifPfiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20sgemvn_kernel1_fermiiiifPfiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20sgemvn_kernel1_fermiiiifPfiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sgemvn_kernel1_fermi.hip"
.globl _Z35__device_stub__sgemvn_kernel1_fermiiiifPfiS_S_ # -- Begin function _Z35__device_stub__sgemvn_kernel1_fermiiiifPfiS_S_
.p2align 4, 0x90
.type _Z35__device_stub__sgemvn_kernel1_fermiiiifPfiS_S_,@function
_Z35__device_stub__sgemvn_kernel1_fermiiiifPfiS_S_: # @_Z35__device_stub__sgemvn_kernel1_fermiiiifPfiS_S_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movss %xmm0, 16(%rsp)
movq %rcx, 88(%rsp)
movl %r8d, 12(%rsp)
movq %r9, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rax
movq %rax, 144(%rsp)
leaq 176(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20sgemvn_kernel1_fermiiiifPfiS_S_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z35__device_stub__sgemvn_kernel1_fermiiiifPfiS_S_, .Lfunc_end0-_Z35__device_stub__sgemvn_kernel1_fermiiiifPfiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20sgemvn_kernel1_fermiiiifPfiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20sgemvn_kernel1_fermiiiifPfiS_S_,@object # @_Z20sgemvn_kernel1_fermiiiifPfiS_S_
.section .rodata,"a",@progbits
.globl _Z20sgemvn_kernel1_fermiiiifPfiS_S_
.p2align 3, 0x0
_Z20sgemvn_kernel1_fermiiiifPfiS_S_:
.quad _Z35__device_stub__sgemvn_kernel1_fermiiiifPfiS_S_
.size _Z20sgemvn_kernel1_fermiiiifPfiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20sgemvn_kernel1_fermiiiifPfiS_S_"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__sgemvn_kernel1_fermiiiifPfiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20sgemvn_kernel1_fermiiiifPfiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <fstream>
#include <stdio.h>
#include <stdlib.h>
#include <vector>
#include <math.h>
using namespace std;
// CUDA KERNEL FUNCTIONS
__global__ void Hello()
{
//int globalidx = threadIdx.z * blockDim.x * blockDim.y + threadIdx.y * blockDim.x + threadIdx.x;
int globalidx = blockIdx.x * blockDim.x + threadIdx.x;
// printf("blockIdx.x %d\n",blockIdx.x);
printf("Hello from blockx = %d\t tx = %d\t ty=%d\t tz=%d\t gi=%d\n",blockIdx.x, threadIdx.x, threadIdx.y, threadIdx.z, globalidx);
}
__global__ void Histogram(int hist_array_1D_size,int array_1D_size, int *hist_array_1D_cuda, int *array_1D_cuda)
{
int globalidx = blockIdx.x * blockDim.x + threadIdx.x;
int N = hist_array_1D_size;
// printf("Hello from blockx = %d\t tx = %d\t ty=%d\t tz=%d\t gi=%d\n",blockIdx.x, threadIdx.x, threadIdx.y, threadIdx.z, globalidx);
if(globalidx<N)
{
int temp = 0;
for (int i = 0; i < array_1D_size; i++)
{
if (array_1D_cuda[i] == globalidx)
{
temp++;
}
}
hist_array_1D_cuda[globalidx] = temp;
}
}
// CPU FUNCTIONS
int ** malloc_matrix(int N)
{
int ** matrix = (int **)malloc(N * sizeof(int *));
for (int i = 0; i < N; ++i)
{
matrix[i] = (int *)malloc(N * sizeof(int));
}
return matrix;
}
float ** malloc_matrix_float(int N)
{
float ** matrix = (float **)malloc(N * sizeof(float *));
for (int i = 0; i < N; ++i)
{
matrix[i] = (float *)malloc(N * sizeof(float));
}
return matrix;
}
void print_matrix(int * matrix, int N)
{
for (int j = 0; j < N; j++)
{
cout << matrix[j] << " ";
}
cout << endl;
}
void print_matrix(int ** matrix, int N)
{
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
{
cout << matrix[i][j] << " ";
}
cout << endl;
}
cout << endl;
}
void print_matrix(float ** matrix, int N)
{
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
{
cout << matrix[i][j] << " ";
}
cout << endl;
}
cout << endl;
}
void print_matrix(float * matrix, int N)
{
for (int j = 0; j < N; j++)
{
cout << matrix[j] << " ";
}
cout << endl;
}
void convert_1d_to_2d (int array_size, int * array_1D)
{
int ** array_2D;
int array_2D_size = sqrt(array_size);
array_2D = malloc_matrix(array_2D_size);
for (int i = 0; i < array_2D_size; i++)
{
for (int j = 0; j < array_2D_size; j++)
{
array_2D[i][j] = array_1D[i*array_2D_size + j];
}
}
print_matrix(array_2D,array_2D_size);
}
void convert_1d_to_2d_float (int array_size, float * array_1D)
{
float ** array_2D;
int array_2D_size = sqrt(array_size);
array_2D = malloc_matrix_float(array_2D_size);
for (int i = 0; i < array_2D_size; i++)
{
for (int j = 0; j < array_2D_size; j++)
{
array_2D[i][j] = array_1D[i*array_2D_size + j];
}
}
print_matrix(array_2D,array_2D_size);
}
// MAIN FUNCTION
int main(int argc, char *argv[]){
// IMAGE TO ARRAY
ifstream file("image_array.txt");
vector<int> image;
if(file.is_open())
{
while (!file.eof())
{
int temp;
file >> temp;
image.push_back(temp);
}
}
file.close();
image.pop_back();
// ARRAY CREATION
int array_1D_size = image.size();
int *array_1D = (int*)malloc(sizeof(int)*array_1D_size);
for (int i = 0; i < array_1D_size; i++)
{
array_1D[i] = image[i];
}
// convert_1d_to_2d(array_1D_size, array_1D);
// HISTOGRAMM ARRAY CREATION
int hist_array_1D_size = 226;
int *hist_array_1D = (int*)malloc(sizeof(int)*hist_array_1D_size);
for (int i = 0; i < hist_array_1D_size; i++)
{
hist_array_1D[i] = 0;
}
// ---------- CUDA ZONE -------------
// printf("This is done by CPU before CUDA threads\n");
// ARRAY TO DEVICE
int *array_1D_cuda;
cudaMalloc(&array_1D_cuda, sizeof(int)*array_1D_size);
cudaMemcpy(array_1D_cuda, array_1D, array_1D_size * sizeof(int), cudaMemcpyHostToDevice);
// HSTOGRAMM ARRAY TO DEVICE
int *hist_array_1D_cuda;
cudaMalloc(&hist_array_1D_cuda, sizeof(int)*hist_array_1D_size);
cudaMemcpy(hist_array_1D_cuda, hist_array_1D, hist_array_1D_size * sizeof(int), cudaMemcpyHostToDevice);
// HISTOGRAM CREATION PROCESS
int blocksDim = 10;
int threadsDim = hist_array_1D_size /blocksDim;
//printf("array_1D_size = %d\n",hist_array_1D_size);
Histogram<<<blocksDim,threadsDim>>>(hist_array_1D_size,array_1D_size,hist_array_1D_cuda,array_1D_cuda);
cudaMemcpy(hist_array_1D, hist_array_1D_cuda, hist_array_1D_size*sizeof(int), cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
print_matrix(hist_array_1D,hist_array_1D_size);
//printf("End of program");
return 0;
} | code for sm_80
Function : _Z9HistogramiiPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff047624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fc600078e00ff */
/*0090*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*00a0*/ @!P0 BRA 0xb10 ; /* 0x00000a6000008947 */
/* 0x000fea0003800000 */
/*00b0*/ IADD3 R2, R4.reuse, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x040fe20007ffe0ff */
/*00c0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00d0*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe200078ec0ff */
/*00e0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0100*/ @!P0 BRA 0xa00 ; /* 0x000008f000008947 */
/* 0x000fea0003800000 */
/*0110*/ IADD3 R6, -R4, c[0x0][0x164], RZ ; /* 0x0000590004067a10 */
/* 0x000fe20007ffe1ff */
/*0120*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0130*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe400078e00ff */
/*0140*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f04270 */
/*0150*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fd800078e00ff */
/*0160*/ @!P0 BRA 0x8a0 ; /* 0x0000073000008947 */
/* 0x000fea0003800000 */
/*0170*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0180*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0190*/ @!P1 BRA 0x610 ; /* 0x0000047000009947 */
/* 0x000fea0003800000 */
/*01a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01b0*/ LDG.E R21, [R2.64] ; /* 0x0000000802157981 */
/* 0x000ea8000c1e1900 */
/*01c0*/ LDG.E R23, [R2.64+0x4] ; /* 0x0000040802177981 */
/* 0x000ee8000c1e1900 */
/*01d0*/ LDG.E R25, [R2.64+0x8] ; /* 0x0000080802197981 */
/* 0x000f28000c1e1900 */
/*01e0*/ LDG.E R27, [R2.64+0xc] ; /* 0x00000c08021b7981 */
/* 0x000f68000c1e1900 */
/*01f0*/ LDG.E R29, [R2.64+0x10] ; /* 0x00001008021d7981 */
/* 0x000f68000c1e1900 */
/*0200*/ LDG.E R10, [R2.64+0x14] ; /* 0x00001408020a7981 */
/* 0x000f68000c1e1900 */
/*0210*/ LDG.E R12, [R2.64+0x18] ; /* 0x00001808020c7981 */
/* 0x000f68000c1e1900 */
/*0220*/ LDG.E R14, [R2.64+0x1c] ; /* 0x00001c08020e7981 */
/* 0x000f68000c1e1900 */
/*0230*/ LDG.E R16, [R2.64+0x20] ; /* 0x0000200802107981 */
/* 0x000f68000c1e1900 */
/*0240*/ LDG.E R19, [R2.64+0x24] ; /* 0x0000240802137981 */
/* 0x000f68000c1e1900 */
/*0250*/ LDG.E R17, [R2.64+0x28] ; /* 0x0000280802117981 */
/* 0x000f68000c1e1900 */
/*0260*/ LDG.E R15, [R2.64+0x2c] ; /* 0x00002c08020f7981 */
/* 0x000f68000c1e1900 */
/*0270*/ LDG.E R13, [R2.64+0x30] ; /* 0x00003008020d7981 */
/* 0x000f68000c1e1900 */
/*0280*/ LDG.E R11, [R2.64+0x34] ; /* 0x00003408020b7981 */
/* 0x000f68000c1e1900 */
/*0290*/ LDG.E R9, [R2.64+0x38] ; /* 0x0000380802097981 */
/* 0x000f68000c1e1900 */
/*02a0*/ LDG.E R7, [R2.64+0x3c] ; /* 0x00003c0802077981 */
/* 0x000f62000c1e1900 */
/*02b0*/ IADD3 R8, R5, 0x1, RZ ; /* 0x0000000105087810 */
/* 0x000fe20007ffe0ff */
/*02c0*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe2000fffe03f */
/*02d0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc40007ffe0ff */
/*02e0*/ ISETP.NE.AND P1, PT, R21, R0.reuse, PT ; /* 0x000000001500720c */
/* 0x084fe40003f25270 */
/*02f0*/ ISETP.NE.AND P2, PT, R23, R0, PT ; /* 0x000000001700720c */
/* 0x008fd60003f45270 */
/*0300*/ @P1 IMAD.MOV R8, RZ, RZ, R5 ; /* 0x000000ffff081224 */
/* 0x000fe200078e0205 */
/*0310*/ ISETP.NE.AND P1, PT, R25, R0, PT ; /* 0x000000001900720c */
/* 0x010fc80003f25270 */
/*0320*/ IADD3 R5, R8, 0x1, RZ ; /* 0x0000000108057810 */
/* 0x000fe20007ffe0ff */
/*0330*/ @P2 IMAD.MOV R5, RZ, RZ, R8 ; /* 0x000000ffff052224 */
/* 0x000fe200078e0208 */
/*0340*/ ISETP.NE.AND P2, PT, R27, R0, PT ; /* 0x000000001b00720c */
/* 0x020fc80003f45270 */
/*0350*/ IADD3 R8, R5, 0x1, RZ ; /* 0x0000000105087810 */
/* 0x000fc60007ffe0ff */
/*0360*/ @P1 IMAD.MOV R8, RZ, RZ, R5 ; /* 0x000000ffff081224 */
/* 0x000fe200078e0205 */
/*0370*/ ISETP.NE.AND P1, PT, R29, R0, PT ; /* 0x000000001d00720c */
/* 0x000fc80003f25270 */
/*0380*/ IADD3 R5, R8, 0x1, RZ ; /* 0x0000000108057810 */
/* 0x000fe20007ffe0ff */
/*0390*/ @P2 IMAD.MOV R5, RZ, RZ, R8 ; /* 0x000000ffff052224 */
/* 0x000fe200078e0208 */
/*03a0*/ ISETP.NE.AND P2, PT, R10, R0, PT ; /* 0x000000000a00720c */
/* 0x000fc80003f45270 */
/*03b0*/ IADD3 R8, R5, 0x1, RZ ; /* 0x0000000105087810 */
/* 0x000fc60007ffe0ff */
/*03c0*/ @P1 IMAD.MOV R8, RZ, RZ, R5 ; /* 0x000000ffff081224 */
/* 0x000fe200078e0205 */
/*03d0*/ ISETP.NE.AND P1, PT, R12, R0, PT ; /* 0x000000000c00720c */
/* 0x000fc80003f25270 */
/*03e0*/ IADD3 R5, R8, 0x1, RZ ; /* 0x0000000108057810 */
/* 0x000fe20007ffe0ff */
/*03f0*/ @P2 IMAD.MOV R5, RZ, RZ, R8 ; /* 0x000000ffff052224 */
/* 0x000fe200078e0208 */
/*0400*/ ISETP.NE.AND P2, PT, R14, R0, PT ; /* 0x000000000e00720c */
/* 0x000fc80003f45270 */
/*0410*/ IADD3 R8, R5, 0x1, RZ ; /* 0x0000000105087810 */
/* 0x000fc60007ffe0ff */
/*0420*/ @P1 IMAD.MOV R8, RZ, RZ, R5 ; /* 0x000000ffff081224 */
/* 0x000fe200078e0205 */
/*0430*/ ISETP.NE.AND P1, PT, R16, R0.reuse, PT ; /* 0x000000001000720c */
/* 0x080fe40003f25270 */
/*0440*/ ISETP.NE.AND P3, PT, R9, R0.reuse, PT ; /* 0x000000000900720c */
/* 0x080fe40003f65270 */
/*0450*/ IADD3 R5, R8, 0x1, RZ ; /* 0x0000000108057810 */
/* 0x000fe20007ffe0ff */
/*0460*/ @P2 IMAD.MOV R5, RZ, RZ, R8 ; /* 0x000000ffff052224 */
/* 0x000fe200078e0208 */
/*0470*/ ISETP.NE.AND P2, PT, R19, R0, PT ; /* 0x000000001300720c */
/* 0x000fc80003f45270 */
/*0480*/ IADD3 R8, R5, 0x1, RZ ; /* 0x0000000105087810 */
/* 0x000fc60007ffe0ff */
/*0490*/ @P1 IMAD.MOV R8, RZ, RZ, R5 ; /* 0x000000ffff081224 */
/* 0x000fe200078e0205 */
/*04a0*/ ISETP.NE.AND P1, PT, R17, R0, PT ; /* 0x000000001100720c */
/* 0x000fc80003f25270 */
/*04b0*/ IADD3 R5, R8, 0x1, RZ ; /* 0x0000000108057810 */
/* 0x000fe20007ffe0ff */
/*04c0*/ @P2 IMAD.MOV R5, RZ, RZ, R8 ; /* 0x000000ffff052224 */
/* 0x000fe200078e0208 */
/*04d0*/ ISETP.NE.AND P2, PT, R15, R0, PT ; /* 0x000000000f00720c */
/* 0x000fc80003f45270 */
/*04e0*/ IADD3 R8, R5, 0x1, RZ ; /* 0x0000000105087810 */
/* 0x000fc60007ffe0ff */
/*04f0*/ @P1 IMAD.MOV R8, RZ, RZ, R5 ; /* 0x000000ffff081224 */
/* 0x000fe200078e0205 */
/*0500*/ ISETP.NE.AND P1, PT, R13, R0, PT ; /* 0x000000000d00720c */
/* 0x000fc80003f25270 */
/*0510*/ IADD3 R5, R8, 0x1, RZ ; /* 0x0000000108057810 */
/* 0x000fe20007ffe0ff */
/*0520*/ @P2 IMAD.MOV R5, RZ, RZ, R8 ; /* 0x000000ffff052224 */
/* 0x000fe200078e0208 */
/*0530*/ ISETP.NE.AND P2, PT, R11, R0, PT ; /* 0x000000000b00720c */
/* 0x000fc80003f45270 */
/*0540*/ IADD3 R8, R5, 0x1, RZ ; /* 0x0000000105087810 */
/* 0x000fc60007ffe0ff */
/*0550*/ @P1 IMAD.MOV R8, RZ, RZ, R5 ; /* 0x000000ffff081224 */
/* 0x000fe200078e0205 */
/*0560*/ ISETP.NE.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fc80003f25270 */
/*0570*/ IADD3 R5, R8, 0x1, RZ ; /* 0x0000000108057810 */
/* 0x000fe20007ffe0ff */
/*0580*/ @P2 IMAD.MOV R5, RZ, RZ, R8 ; /* 0x000000ffff052224 */
/* 0x000fe200078e0208 */
/*0590*/ ISETP.GT.AND P2, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fc80003f44270 */
/*05a0*/ IADD3 R7, R5, 0x1, RZ ; /* 0x0000000105077810 */
/* 0x000fe20007ffe0ff */
/*05b0*/ @P3 IMAD.MOV R7, RZ, RZ, R5 ; /* 0x000000ffff073224 */
/* 0x000fe200078e0205 */
/*05c0*/ IADD3 R2, P3, R2, 0x40, RZ ; /* 0x0000004002027810 */
/* 0x000fc80007f7e0ff */
/*05d0*/ IADD3 R5, R7, 0x1, RZ ; /* 0x0000000107057810 */
/* 0x000fe20007ffe0ff */
/*05e0*/ IMAD.X R3, RZ, RZ, R3, P3 ; /* 0x000000ffff037224 */
/* 0x000fe400018e0603 */
/*05f0*/ @P1 IMAD.MOV R5, RZ, RZ, R7 ; /* 0x000000ffff051224 */
/* 0x000fe200078e0207 */
/*0600*/ @P2 BRA 0x1b0 ; /* 0xfffffba000002947 */
/* 0x000fea000383ffff */
/*0610*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0620*/ @!P1 BRA 0x880 ; /* 0x0000025000009947 */
/* 0x000fea0003800000 */
/*0630*/ LDG.E R7, [R2.64] ; /* 0x0000000802077981 */
/* 0x0000a8000c1e1900 */
/*0640*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040802097981 */
/* 0x0000e8000c1e1900 */
/*0650*/ LDG.E R11, [R2.64+0x8] ; /* 0x00000808020b7981 */
/* 0x000128000c1e1900 */
/*0660*/ LDG.E R13, [R2.64+0xc] ; /* 0x00000c08020d7981 */
/* 0x000168000c1e1900 */
/*0670*/ LDG.E R15, [R2.64+0x10] ; /* 0x00001008020f7981 */
/* 0x000168000c1e1900 */
/*0680*/ LDG.E R17, [R2.64+0x14] ; /* 0x0000140802117981 */
/* 0x000168000c1e1900 */
/*0690*/ LDG.E R19, [R2.64+0x18] ; /* 0x0000180802137981 */
/* 0x000168000c1e1900 */
/*06a0*/ LDG.E R21, [R2.64+0x1c] ; /* 0x00001c0802157981 */
/* 0x000162000c1e1900 */
/*06b0*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*06c0*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*06d0*/ IADD3 R2, P2, R2, 0x20, RZ ; /* 0x0000002002027810 */
/* 0x001fca0007f5e0ff */
/*06e0*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*06f0*/ ISETP.NE.AND P0, PT, R7, R0.reuse, PT ; /* 0x000000000700720c */
/* 0x084fe40003f05270 */
/*0700*/ IADD3 R7, R5, 0x1, RZ ; /* 0x0000000105077810 */
/* 0x000fe40007ffe0ff */
/*0710*/ ISETP.NE.AND P1, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x008fd20003f25270 */
/*0720*/ @P0 IMAD.MOV R7, RZ, RZ, R5 ; /* 0x000000ffff070224 */
/* 0x000fe200078e0205 */
/*0730*/ ISETP.NE.AND P0, PT, R11, R0, PT ; /* 0x000000000b00720c */
/* 0x010fc80003f05270 */
/*0740*/ IADD3 R5, R7, 0x1, RZ ; /* 0x0000000107057810 */
/* 0x000fe20007ffe0ff */
/*0750*/ @P1 IMAD.MOV R5, RZ, RZ, R7 ; /* 0x000000ffff051224 */
/* 0x000fe200078e0207 */
/*0760*/ ISETP.NE.AND P1, PT, R13, R0, PT ; /* 0x000000000d00720c */
/* 0x020fc80003f25270 */
/*0770*/ IADD3 R7, R5, 0x1, RZ ; /* 0x0000000105077810 */
/* 0x000fc60007ffe0ff */
/*0780*/ @P0 IMAD.MOV R7, RZ, RZ, R5 ; /* 0x000000ffff070224 */
/* 0x000fe200078e0205 */
/*0790*/ ISETP.NE.AND P0, PT, R15, R0, PT ; /* 0x000000000f00720c */
/* 0x000fc80003f05270 */
/*07a0*/ IADD3 R5, R7, 0x1, RZ ; /* 0x0000000107057810 */
/* 0x000fe20007ffe0ff */
/*07b0*/ @P1 IMAD.MOV R5, RZ, RZ, R7 ; /* 0x000000ffff051224 */
/* 0x000fe200078e0207 */
/*07c0*/ ISETP.NE.AND P1, PT, R17, R0, PT ; /* 0x000000001100720c */
/* 0x000fc80003f25270 */
/*07d0*/ IADD3 R7, R5, 0x1, RZ ; /* 0x0000000105077810 */
/* 0x000fc60007ffe0ff */
/*07e0*/ @P0 IMAD.MOV R7, RZ, RZ, R5 ; /* 0x000000ffff070224 */
/* 0x000fe200078e0205 */
/*07f0*/ ISETP.NE.AND P0, PT, R19, R0, PT ; /* 0x000000001300720c */
/* 0x000fc80003f05270 */
/*0800*/ IADD3 R5, R7, 0x1, RZ ; /* 0x0000000107057810 */
/* 0x000fe20007ffe0ff */
/*0810*/ @P1 IMAD.MOV R5, RZ, RZ, R7 ; /* 0x000000ffff051224 */
/* 0x000fe200078e0207 */
/*0820*/ ISETP.NE.AND P1, PT, R21, R0, PT ; /* 0x000000001500720c */
/* 0x000fc80003f25270 */
/*0830*/ IADD3 R7, R5, 0x1, RZ ; /* 0x0000000105077810 */
/* 0x000fc60007ffe0ff */
/*0840*/ @P0 IMAD.MOV R7, RZ, RZ, R5 ; /* 0x000000ffff070224 */
/* 0x000fe200078e0205 */
/*0850*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc80003f0e170 */
/*0860*/ IADD3 R5, R7, 0x1, RZ ; /* 0x0000000107057810 */
/* 0x000fe20007ffe0ff */
/*0870*/ @P1 IMAD.MOV R5, RZ, RZ, R7 ; /* 0x000000ffff051224 */
/* 0x000fe400078e0207 */
/*0880*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0890*/ @!P0 BRA 0xa00 ; /* 0x0000016000008947 */
/* 0x000fea0003800000 */
/*08a0*/ LDG.E R7, [R2.64] ; /* 0x0000000802077981 */
/* 0x0000a8000c1e1900 */
/*08b0*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040802097981 */
/* 0x0000e8000c1e1900 */
/*08c0*/ LDG.E R11, [R2.64+0x8] ; /* 0x00000808020b7981 */
/* 0x000128000c1e1900 */
/*08d0*/ LDG.E R13, [R2.64+0xc] ; /* 0x00000c08020d7981 */
/* 0x000162000c1e1900 */
/*08e0*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fe20007ffe0ff */
/*08f0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0900*/ IADD3 R2, P2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x001fca0007f5e0ff */
/*0910*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*0920*/ ISETP.NE.AND P0, PT, R7, R0.reuse, PT ; /* 0x000000000700720c */
/* 0x084fe40003f05270 */
/*0930*/ IADD3 R7, R5, 0x1, RZ ; /* 0x0000000105077810 */
/* 0x000fe40007ffe0ff */
/*0940*/ ISETP.NE.AND P1, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x008fd20003f25270 */
/*0950*/ @P0 IMAD.MOV R7, RZ, RZ, R5 ; /* 0x000000ffff070224 */
/* 0x000fe200078e0205 */
/*0960*/ ISETP.NE.AND P0, PT, R11, R0, PT ; /* 0x000000000b00720c */
/* 0x010fc80003f05270 */
/*0970*/ IADD3 R5, R7, 0x1, RZ ; /* 0x0000000107057810 */
/* 0x000fe20007ffe0ff */
/*0980*/ @P1 IMAD.MOV R5, RZ, RZ, R7 ; /* 0x000000ffff051224 */
/* 0x000fe200078e0207 */
/*0990*/ ISETP.NE.AND P1, PT, R13, R0, PT ; /* 0x000000000d00720c */
/* 0x020fc80003f25270 */
/*09a0*/ IADD3 R7, R5, 0x1, RZ ; /* 0x0000000105077810 */
/* 0x000fc60007ffe0ff */
/*09b0*/ @P0 IMAD.MOV R7, RZ, RZ, R5 ; /* 0x000000ffff070224 */
/* 0x000fe200078e0205 */
/*09c0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc80003f05270 */
/*09d0*/ IADD3 R5, R7, 0x1, RZ ; /* 0x0000000107057810 */
/* 0x000fe20007ffe0ff */
/*09e0*/ @P1 IMAD.MOV R5, RZ, RZ, R7 ; /* 0x000000ffff051224 */
/* 0x000fd000078e0207 */
/*09f0*/ @P0 BRA 0x8a0 ; /* 0xfffffea000000947 */
/* 0x000fea000383ffff */
/*0a00*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0a10*/ @!P0 BRA 0xb10 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0a20*/ UMOV UR5, 0x4 ; /* 0x0000000400057882 */
/* 0x000fe40000000000 */
/*0a30*/ ULDC.64 UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe40000000a00 */
/*0a40*/ UIMAD.WIDE UR4, UR4, UR5, UR6 ; /* 0x00000005040472a5 */
/* 0x000fcc000f8e0206 */
/*0a50*/ IMAD.U32 R3, RZ, RZ, UR5 ; /* 0x00000005ff037e24 */
/* 0x000fe4000f8e00ff */
/*0a60*/ IMAD.U32 R2, RZ, RZ, UR4 ; /* 0x00000004ff027e24 */
/* 0x000fca000f8e00ff */
/*0a70*/ LDG.E R3, [R2.64] ; /* 0x0000000802037981 */
/* 0x000ea2000c1e1900 */
/*0a80*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe20007ffe0ff */
/*0a90*/ UIADD3 UR4, UP0, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000ff1e03f */
/*0aa0*/ IADD3 R6, R5, 0x1, RZ ; /* 0x0000000105067810 */
/* 0x000fe40007ffe0ff */
/*0ab0*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f25270 */
/*0ac0*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200087fe43f */
/*0ad0*/ ISETP.NE.AND P0, PT, R3, R0, PT ; /* 0x000000000300720c */
/* 0x004fda0003f05270 */
/*0ae0*/ @P0 IMAD.MOV R6, RZ, RZ, R5 ; /* 0x000000ffff060224 */
/* 0x000fc800078e0205 */
/*0af0*/ IMAD.MOV.U32 R5, RZ, RZ, R6 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0006 */
/*0b00*/ @P1 BRA 0xa50 ; /* 0xffffff4000001947 */
/* 0x000fea000383ffff */
/*0b10*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0b20*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0203 */
/*0b30*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101908 */
/*0b40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b50*/ BRA 0xb50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z5Hellov
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e220000002100 */
/*0020*/ MOV R2, 0x8 ; /* 0x0000000800027802 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x0] ; /* 0x01000000ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ IADD3 R1, R1, -0x18, RZ ; /* 0xffffffe801017810 */
/* 0x000fe20007ffe0ff */
/*0050*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x4] ; /* 0x01000100ff057624 */
/* 0x000fe400078e00ff */
/*0070*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000e620000000a00 */
/*0080*/ S2R R11, SR_TID.Z ; /* 0x00000000000b7919 */
/* 0x000ea20000002300 */
/*0090*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fc60007f1e0ff */
/*00a0*/ S2R R10, SR_TID.Y ; /* 0x00000000000a7919 */
/* 0x000ea40000002200 */
/*00b0*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe400000e06ff */
/*00c0*/ IMAD R0, R8, c[0x0][0x0], R9 ; /* 0x0000000008007a24 */
/* 0x001fe200078e0209 */
/*00d0*/ STL.64 [R1], R8 ; /* 0x0000000801007387 */
/* 0x0001e80000100a00 */
/*00e0*/ STL [R1+0x10], R0 ; /* 0x0000100001007387 */
/* 0x0001e80000100800 */
/*00f0*/ STL.64 [R1+0x8], R10 ; /* 0x0000080a01007387 */
/* 0x0041e40000100a00 */
/*0100*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x003fe40000000000 */
/*0110*/ MOV R11, 0x180 ; /* 0x00000180000b7802 */
/* 0x000fe40000000f00 */
/*0120*/ MOV R20, 0x100 ; /* 0x0000010000147802 */
/* 0x000fc40000000f00 */
/*0130*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0150*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0160*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0170*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x000fea0003c00000 */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ BRA 0x190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <fstream>
#include <stdio.h>
#include <stdlib.h>
#include <vector>
#include <math.h>
using namespace std;
// CUDA KERNEL FUNCTIONS
__global__ void Hello()
{
//int globalidx = threadIdx.z * blockDim.x * blockDim.y + threadIdx.y * blockDim.x + threadIdx.x;
int globalidx = blockIdx.x * blockDim.x + threadIdx.x;
// printf("blockIdx.x %d\n",blockIdx.x);
printf("Hello from blockx = %d\t tx = %d\t ty=%d\t tz=%d\t gi=%d\n",blockIdx.x, threadIdx.x, threadIdx.y, threadIdx.z, globalidx);
}
__global__ void Histogram(int hist_array_1D_size,int array_1D_size, int *hist_array_1D_cuda, int *array_1D_cuda)
{
int globalidx = blockIdx.x * blockDim.x + threadIdx.x;
int N = hist_array_1D_size;
// printf("Hello from blockx = %d\t tx = %d\t ty=%d\t tz=%d\t gi=%d\n",blockIdx.x, threadIdx.x, threadIdx.y, threadIdx.z, globalidx);
if(globalidx<N)
{
int temp = 0;
for (int i = 0; i < array_1D_size; i++)
{
if (array_1D_cuda[i] == globalidx)
{
temp++;
}
}
hist_array_1D_cuda[globalidx] = temp;
}
}
// CPU FUNCTIONS
int ** malloc_matrix(int N)
{
int ** matrix = (int **)malloc(N * sizeof(int *));
for (int i = 0; i < N; ++i)
{
matrix[i] = (int *)malloc(N * sizeof(int));
}
return matrix;
}
float ** malloc_matrix_float(int N)
{
float ** matrix = (float **)malloc(N * sizeof(float *));
for (int i = 0; i < N; ++i)
{
matrix[i] = (float *)malloc(N * sizeof(float));
}
return matrix;
}
void print_matrix(int * matrix, int N)
{
for (int j = 0; j < N; j++)
{
cout << matrix[j] << " ";
}
cout << endl;
}
void print_matrix(int ** matrix, int N)
{
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
{
cout << matrix[i][j] << " ";
}
cout << endl;
}
cout << endl;
}
void print_matrix(float ** matrix, int N)
{
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
{
cout << matrix[i][j] << " ";
}
cout << endl;
}
cout << endl;
}
void print_matrix(float * matrix, int N)
{
for (int j = 0; j < N; j++)
{
cout << matrix[j] << " ";
}
cout << endl;
}
void convert_1d_to_2d (int array_size, int * array_1D)
{
int ** array_2D;
int array_2D_size = sqrt(array_size);
array_2D = malloc_matrix(array_2D_size);
for (int i = 0; i < array_2D_size; i++)
{
for (int j = 0; j < array_2D_size; j++)
{
array_2D[i][j] = array_1D[i*array_2D_size + j];
}
}
print_matrix(array_2D,array_2D_size);
}
void convert_1d_to_2d_float (int array_size, float * array_1D)
{
float ** array_2D;
int array_2D_size = sqrt(array_size);
array_2D = malloc_matrix_float(array_2D_size);
for (int i = 0; i < array_2D_size; i++)
{
for (int j = 0; j < array_2D_size; j++)
{
array_2D[i][j] = array_1D[i*array_2D_size + j];
}
}
print_matrix(array_2D,array_2D_size);
}
// MAIN FUNCTION
int main(int argc, char *argv[]){
// IMAGE TO ARRAY
ifstream file("image_array.txt");
vector<int> image;
if(file.is_open())
{
while (!file.eof())
{
int temp;
file >> temp;
image.push_back(temp);
}
}
file.close();
image.pop_back();
// ARRAY CREATION
int array_1D_size = image.size();
int *array_1D = (int*)malloc(sizeof(int)*array_1D_size);
for (int i = 0; i < array_1D_size; i++)
{
array_1D[i] = image[i];
}
// convert_1d_to_2d(array_1D_size, array_1D);
// HISTOGRAMM ARRAY CREATION
int hist_array_1D_size = 226;
int *hist_array_1D = (int*)malloc(sizeof(int)*hist_array_1D_size);
for (int i = 0; i < hist_array_1D_size; i++)
{
hist_array_1D[i] = 0;
}
// ---------- CUDA ZONE -------------
// printf("This is done by CPU before CUDA threads\n");
// ARRAY TO DEVICE
int *array_1D_cuda;
cudaMalloc(&array_1D_cuda, sizeof(int)*array_1D_size);
cudaMemcpy(array_1D_cuda, array_1D, array_1D_size * sizeof(int), cudaMemcpyHostToDevice);
// HSTOGRAMM ARRAY TO DEVICE
int *hist_array_1D_cuda;
cudaMalloc(&hist_array_1D_cuda, sizeof(int)*hist_array_1D_size);
cudaMemcpy(hist_array_1D_cuda, hist_array_1D, hist_array_1D_size * sizeof(int), cudaMemcpyHostToDevice);
// HISTOGRAM CREATION PROCESS
int blocksDim = 10;
int threadsDim = hist_array_1D_size /blocksDim;
//printf("array_1D_size = %d\n",hist_array_1D_size);
Histogram<<<blocksDim,threadsDim>>>(hist_array_1D_size,array_1D_size,hist_array_1D_cuda,array_1D_cuda);
cudaMemcpy(hist_array_1D, hist_array_1D_cuda, hist_array_1D_size*sizeof(int), cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
print_matrix(hist_array_1D,hist_array_1D_size);
//printf("End of program");
return 0;
} | .file "tmpxft_00142bf2_00000000-6_cuda_histogram.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4184:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4184:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13malloc_matrixi
.type _Z13malloc_matrixi, @function
_Z13malloc_matrixi:
.LFB4163:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movslq %edi, %r12
leaq 0(,%r12,8), %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r13
testl %ebx, %ebx
jle .L3
salq $2, %r12
movq %rax, %rbx
addq %rax, %rbp
.L5:
movq %r12, %rdi
call malloc@PLT
movq %rax, (%rbx)
addq $8, %rbx
cmpq %rbp, %rbx
jne .L5
.L3:
movq %r13, %rax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4163:
.size _Z13malloc_matrixi, .-_Z13malloc_matrixi
.globl _Z19malloc_matrix_floati
.type _Z19malloc_matrix_floati, @function
_Z19malloc_matrix_floati:
.LFB4164:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movslq %edi, %r12
leaq 0(,%r12,8), %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r13
testl %ebx, %ebx
jle .L8
salq $2, %r12
movq %rax, %rbx
addq %rax, %rbp
.L10:
movq %r12, %rdi
call malloc@PLT
movq %rax, (%rbx)
addq $8, %rbx
cmpq %rbp, %rbx
jne .L10
.L8:
movq %r13, %rax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4164:
.size _Z19malloc_matrix_floati, .-_Z19malloc_matrix_floati
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " "
.text
.globl _Z12print_matrixPii
.type _Z12print_matrixPii, @function
_Z12print_matrixPii:
.LFB4165:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
testl %esi, %esi
jle .L14
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %r13
leaq _ZSt4cout(%rip), %r12
leaq .LC0(%rip), %rbp
.L15:
movl (%rbx), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %rbp, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbx, %r13
jne .L15
.L14:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %rbx
testq %rbx, %rbx
je .L21
cmpb $0, 56(%rbx)
je .L17
movzbl 67(%rbx), %esi
.L18:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L17:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L18
.cfi_endproc
.LFE4165:
.size _Z12print_matrixPii, .-_Z12print_matrixPii
.globl _Z12print_matrixPPii
.type _Z12print_matrixPPii, @function
_Z12print_matrixPPii:
.LFB4166:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
testl %esi, %esi
jle .L23
movq %rdi, %r12
movslq %esi, %rsi
leaq (%rdi,%rsi,8), %r15
leaq 0(,%rsi,4), %r13
leaq _ZSt4cout(%rip), %rbp
leaq .LC0(%rip), %r14
jmp .L24
.L34:
call _ZSt16__throw_bad_castv@PLT
.L27:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
.L28:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $8, %r12
cmpq %r12, %r15
je .L23
.L24:
movl $0, %ebx
.L25:
movq (%r12), %rax
movl (%rax,%rbx), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r14, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %r13, %rbx
jne .L25
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbx
testq %rbx, %rbx
je .L34
cmpb $0, 56(%rbx)
je .L27
movzbl 67(%rbx), %esi
jmp .L28
.L23:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %rbx
testq %rbx, %rbx
je .L35
cmpb $0, 56(%rbx)
je .L30
movzbl 67(%rbx), %eax
.L31:
movsbl %al, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L30:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
jmp .L31
.cfi_endproc
.LFE4166:
.size _Z12print_matrixPPii, .-_Z12print_matrixPPii
.globl _Z12print_matrixPPfi
.type _Z12print_matrixPPfi, @function
_Z12print_matrixPPfi:
.LFB4167:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
testl %esi, %esi
jle .L37
movq %rdi, %r12
movslq %esi, %rsi
leaq (%rdi,%rsi,8), %r15
leaq 0(,%rsi,4), %r13
leaq _ZSt4cout(%rip), %rbp
leaq .LC0(%rip), %r14
jmp .L38
.L48:
call _ZSt16__throw_bad_castv@PLT
.L41:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
.L42:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $8, %r12
cmpq %r12, %r15
je .L37
.L38:
movl $0, %ebx
.L39:
movq (%r12), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbx), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %r14, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %r13, %rbx
jne .L39
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbx
testq %rbx, %rbx
je .L48
cmpb $0, 56(%rbx)
je .L41
movzbl 67(%rbx), %esi
jmp .L42
.L37:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %rbx
testq %rbx, %rbx
je .L49
cmpb $0, 56(%rbx)
je .L44
movzbl 67(%rbx), %eax
.L45:
movsbl %al, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L44:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
jmp .L45
.cfi_endproc
.LFE4167:
.size _Z12print_matrixPPfi, .-_Z12print_matrixPPfi
.globl _Z12print_matrixPfi
.type _Z12print_matrixPfi, @function
_Z12print_matrixPfi:
.LFB4168:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
testl %esi, %esi
jle .L51
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %r13
leaq _ZSt4cout(%rip), %r12
leaq .LC0(%rip), %rbp
.L52:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %rbp, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbx, %r13
jne .L52
.L51:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %rbx
testq %rbx, %rbx
je .L58
cmpb $0, 56(%rbx)
je .L54
movzbl 67(%rbx), %esi
.L55:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L58:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L54:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L55
.cfi_endproc
.LFE4168:
.size _Z12print_matrixPfi, .-_Z12print_matrixPfi
.globl _Z16convert_1d_to_2diPi
.type _Z16convert_1d_to_2diPi, @function
_Z16convert_1d_to_2diPi:
.LFB4169:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbp
pxor %xmm0, %xmm0
cvtsi2sdl %edi, %xmm0
pxor %xmm1, %xmm1
ucomisd %xmm0, %xmm1
ja .L68
sqrtsd %xmm0, %xmm0
.L62:
cvttsd2sil %xmm0, %ebx
movl %ebx, %edi
call _Z13malloc_matrixi
testl %ebx, %ebx
jle .L63
movq %rax, %rdi
movslq %ebx, %rdx
leaq 0(,%rdx,4), %r9
movq %rbp, %r8
leaq (%rax,%rdx,8), %r10
.L64:
movl $0, %edx
.L65:
movl (%r8,%rdx), %esi
movq (%rdi), %rcx
movl %esi, (%rcx,%rdx)
addq $4, %rdx
cmpq %r9, %rdx
jne .L65
addq $8, %rdi
addq %r9, %r8
cmpq %r10, %rdi
jne .L64
.L63:
movl %ebx, %esi
movq %rax, %rdi
call _Z12print_matrixPPii
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L68:
.cfi_restore_state
call sqrt@PLT
jmp .L62
.cfi_endproc
.LFE4169:
.size _Z16convert_1d_to_2diPi, .-_Z16convert_1d_to_2diPi
.globl _Z22convert_1d_to_2d_floatiPf
.type _Z22convert_1d_to_2d_floatiPf, @function
_Z22convert_1d_to_2d_floatiPf:
.LFB4170:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbx
pxor %xmm0, %xmm0
cvtsi2sdl %edi, %xmm0
pxor %xmm1, %xmm1
ucomisd %xmm0, %xmm1
ja .L79
sqrtsd %xmm0, %xmm0
.L73:
cvttsd2sil %xmm0, %ebp
movl %ebp, %edi
call _Z19malloc_matrix_floati
testl %ebp, %ebp
jle .L74
movq %rax, %rsi
movslq %ebp, %rdx
leaq 0(,%rdx,4), %r8
movq %rbx, %rdi
leaq (%rax,%rdx,8), %r9
.L75:
movl $0, %edx
.L76:
movss (%rdi,%rdx), %xmm0
movq (%rsi), %rcx
movss %xmm0, (%rcx,%rdx)
addq $4, %rdx
cmpq %r8, %rdx
jne .L76
addq $8, %rsi
addq %r8, %rdi
cmpq %r9, %rsi
jne .L75
.L74:
movl %ebp, %esi
movq %rax, %rdi
call _Z12print_matrixPPfi
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L79:
.cfi_restore_state
call sqrt@PLT
jmp .L73
.cfi_endproc
.LFE4170:
.size _Z22convert_1d_to_2d_floatiPf, .-_Z22convert_1d_to_2d_floatiPf
.globl _Z23__device_stub__Z5Hellovv
.type _Z23__device_stub__Z5Hellovv, @function
_Z23__device_stub__Z5Hellovv:
.LFB4206:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L85
.L81:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L86
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L85:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z5Hellov(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L81
.L86:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4206:
.size _Z23__device_stub__Z5Hellovv, .-_Z23__device_stub__Z5Hellovv
.globl _Z5Hellov
.type _Z5Hellov, @function
_Z5Hellov:
.LFB4207:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z5Hellovv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4207:
.size _Z5Hellov, .-_Z5Hellov
.globl _Z32__device_stub__Z9HistogramiiPiS_iiPiS_
.type _Z32__device_stub__Z9HistogramiiPiS_iiPiS_, @function
_Z32__device_stub__Z9HistogramiiPiS_iiPiS_:
.LFB4208:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L93
.L89:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L94
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L93:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9HistogramiiPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L89
.L94:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4208:
.size _Z32__device_stub__Z9HistogramiiPiS_iiPiS_, .-_Z32__device_stub__Z9HistogramiiPiS_iiPiS_
.globl _Z9HistogramiiPiS_
.type _Z9HistogramiiPiS_, @function
_Z9HistogramiiPiS_:
.LFB4209:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9HistogramiiPiS_iiPiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4209:
.size _Z9HistogramiiPiS_, .-_Z9HistogramiiPiS_
.section .rodata.str1.1
.LC2:
.string "_Z9HistogramiiPiS_"
.LC3:
.string "_Z5Hellov"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4211:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z9HistogramiiPiS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z5Hellov(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4211:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIiSaIiEED2Ev,"axG",@progbits,_ZNSt6vectorIiSaIiEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEED2Ev
.type _ZNSt6vectorIiSaIiEED2Ev, @function
_ZNSt6vectorIiSaIiEED2Ev:
.LFB4549:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L102
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L102:
ret
.cfi_endproc
.LFE4549:
.size _ZNSt6vectorIiSaIiEED2Ev, .-_ZNSt6vectorIiSaIiEED2Ev
.weak _ZNSt6vectorIiSaIiEED1Ev
.set _ZNSt6vectorIiSaIiEED1Ev,_ZNSt6vectorIiSaIiEED2Ev
.section .rodata._ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_.str1.1,"aMS",@progbits,1
.LC4:
.string "vector::_M_realloc_insert"
.section .text._ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_,"axG",@progbits,_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_
.type _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_, @function
_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_:
.LFB4740:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, (%rsp)
movq %rdx, 8(%rsp)
movq 8(%rdi), %rbp
movq (%rdi), %r13
movq %rbp, %rax
subq %r13, %rax
sarq $2, %rax
movabsq $2305843009213693951, %rdx
cmpq %rdx, %rax
je .L122
movq %rdi, %rbx
cmpq %r13, %rbp
movl $1, %edx
cmovne %rax, %rdx
addq %rdx, %rax
jc .L108
movabsq $2305843009213693951, %r14
cmpq %r14, %rax
cmovbe %rax, %r14
movq (%rsp), %r15
subq %r13, %r15
movl $0, %r12d
testq %rax, %rax
je .L109
jmp .L116
.L122:
leaq .LC4(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L123:
movq %r15, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memmove@PLT
leaq 4(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jg .L111
addq %rbp, %r15
movq 16(%rbx), %rsi
subq %r13, %rsi
jmp .L115
.L108:
movq (%rsp), %r15
subq %r13, %r15
movabsq $2305843009213693951, %r14
.L116:
leaq 0(,%r14,4), %rdi
call _Znwm@PLT
movq %rax, %r12
.L109:
movq 8(%rsp), %rax
movl (%rax), %eax
movl %eax, (%r12,%r15)
testq %r15, %r15
jg .L123
leaq 4(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jle .L113
.L111:
movq %rbp, %rdx
movq (%rsp), %rsi
movq %r15, %rdi
call memcpy@PLT
.L113:
addq %rbp, %r15
testq %r13, %r13
je .L114
movq 16(%rbx), %rsi
subq %r13, %rsi
.L115:
movq %r13, %rdi
call _ZdlPvm@PLT
.L114:
movq %r12, (%rbx)
movq %r15, 8(%rbx)
leaq (%r12,%r14,4), %rax
movq %rax, 16(%rbx)
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4740:
.size _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_, .-_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_
.section .rodata.str1.1
.LC5:
.string "image_array.txt"
.text
.globl main
.type main, @function
main:
.LFB4171:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4171
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $608, %rsp
.cfi_def_cfa_offset 656
movq %fs:40, %rax
movq %rax, 600(%rsp)
xorl %eax, %eax
leaq 80(%rsp), %rdi
movl $8, %edx
leaq .LC5(%rip), %rsi
.LEHB0:
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
.LEHE0:
movq $0, 48(%rsp)
movq $0, 56(%rsp)
movq $0, 64(%rsp)
leaq 200(%rsp), %rdi
call _ZNKSt12__basic_fileIcE7is_openEv@PLT
testb %al, %al
je .L125
testb $2, 368(%rsp)
jne .L125
leaq 36(%rsp), %rbx
jmp .L128
.L142:
movq 56(%rsp), %rsi
cmpq 64(%rsp), %rsi
je .L126
movl 36(%rsp), %eax
movl %eax, (%rsi)
addq $4, %rsi
movq %rsi, 56(%rsp)
.L127:
testb $2, 368(%rsp)
jne .L125
.L128:
leaq 80(%rsp), %rdi
movq %rbx, %rsi
.LEHB1:
call _ZNSirsERi@PLT
jmp .L142
.L126:
leaq 48(%rsp), %rdi
movq %rbx, %rdx
call _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_
jmp .L127
.L125:
leaq 80(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv@PLT
movq 56(%rsp), %rax
leaq -4(%rax), %r14
movq %r14, 56(%rsp)
movq 48(%rsp), %r13
subq %r13, %r14
sarq $2, %r14
movl %r14d, %r12d
movslq %r14d, %rbp
salq $2, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbx
testl %r14d, %r14d
jle .L129
leal -1(%r14), %ecx
movl $0, %eax
.L130:
movl 0(%r13,%rax,4), %edx
movl %edx, (%rbx,%rax,4)
movq %rax, %rdx
addq $1, %rax
cmpq %rcx, %rdx
jne .L130
.L129:
movl $904, %edi
call malloc@PLT
movq %rax, %r13
leaq 904(%rax), %rdx
.L131:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L131
leaq 8(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
movl $904, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $904, %edx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $22, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $10, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L132
movq 8(%rsp), %rcx
movq 16(%rsp), %rdx
movl %r12d, %esi
movl $226, %edi
call _Z32__device_stub__Z9HistogramiiPiS_iiPiS_
.L132:
movl $2, %ecx
movl $904, %edx
movq 16(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
movl $226, %esi
movq %r13, %rdi
call _Z12print_matrixPii
.LEHE1:
leaq 48(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
leaq 80(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq 600(%rsp), %rax
subq %fs:40, %rax
jne .L143
movl $0, %eax
addq $608, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L136:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 48(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
leaq 80(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq 600(%rsp), %rax
subq %fs:40, %rax
je .L134
call __stack_chk_fail@PLT
.L134:
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.LEHE2:
.L143:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4171:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4171:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4171-.LLSDACSB4171
.LLSDACSB4171:
.uleb128 .LEHB0-.LFB4171
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4171
.uleb128 .LEHE1-.LEHB1
.uleb128 .L136-.LFB4171
.uleb128 0
.uleb128 .LEHB2-.LFB4171
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.LLSDACSE4171:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <fstream>
#include <stdio.h>
#include <stdlib.h>
#include <vector>
#include <math.h>
using namespace std;
// CUDA KERNEL FUNCTIONS
__global__ void Hello()
{
//int globalidx = threadIdx.z * blockDim.x * blockDim.y + threadIdx.y * blockDim.x + threadIdx.x;
int globalidx = blockIdx.x * blockDim.x + threadIdx.x;
// printf("blockIdx.x %d\n",blockIdx.x);
printf("Hello from blockx = %d\t tx = %d\t ty=%d\t tz=%d\t gi=%d\n",blockIdx.x, threadIdx.x, threadIdx.y, threadIdx.z, globalidx);
}
__global__ void Histogram(int hist_array_1D_size,int array_1D_size, int *hist_array_1D_cuda, int *array_1D_cuda)
{
int globalidx = blockIdx.x * blockDim.x + threadIdx.x;
int N = hist_array_1D_size;
// printf("Hello from blockx = %d\t tx = %d\t ty=%d\t tz=%d\t gi=%d\n",blockIdx.x, threadIdx.x, threadIdx.y, threadIdx.z, globalidx);
if(globalidx<N)
{
int temp = 0;
for (int i = 0; i < array_1D_size; i++)
{
if (array_1D_cuda[i] == globalidx)
{
temp++;
}
}
hist_array_1D_cuda[globalidx] = temp;
}
}
// CPU FUNCTIONS
int ** malloc_matrix(int N)
{
int ** matrix = (int **)malloc(N * sizeof(int *));
for (int i = 0; i < N; ++i)
{
matrix[i] = (int *)malloc(N * sizeof(int));
}
return matrix;
}
float ** malloc_matrix_float(int N)
{
float ** matrix = (float **)malloc(N * sizeof(float *));
for (int i = 0; i < N; ++i)
{
matrix[i] = (float *)malloc(N * sizeof(float));
}
return matrix;
}
void print_matrix(int * matrix, int N)
{
for (int j = 0; j < N; j++)
{
cout << matrix[j] << " ";
}
cout << endl;
}
void print_matrix(int ** matrix, int N)
{
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
{
cout << matrix[i][j] << " ";
}
cout << endl;
}
cout << endl;
}
void print_matrix(float ** matrix, int N)
{
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
{
cout << matrix[i][j] << " ";
}
cout << endl;
}
cout << endl;
}
void print_matrix(float * matrix, int N)
{
for (int j = 0; j < N; j++)
{
cout << matrix[j] << " ";
}
cout << endl;
}
void convert_1d_to_2d (int array_size, int * array_1D)
{
int ** array_2D;
int array_2D_size = sqrt(array_size);
array_2D = malloc_matrix(array_2D_size);
for (int i = 0; i < array_2D_size; i++)
{
for (int j = 0; j < array_2D_size; j++)
{
array_2D[i][j] = array_1D[i*array_2D_size + j];
}
}
print_matrix(array_2D,array_2D_size);
}
void convert_1d_to_2d_float (int array_size, float * array_1D)
{
float ** array_2D;
int array_2D_size = sqrt(array_size);
array_2D = malloc_matrix_float(array_2D_size);
for (int i = 0; i < array_2D_size; i++)
{
for (int j = 0; j < array_2D_size; j++)
{
array_2D[i][j] = array_1D[i*array_2D_size + j];
}
}
print_matrix(array_2D,array_2D_size);
}
// MAIN FUNCTION
int main(int argc, char *argv[]){
// IMAGE TO ARRAY
ifstream file("image_array.txt");
vector<int> image;
if(file.is_open())
{
while (!file.eof())
{
int temp;
file >> temp;
image.push_back(temp);
}
}
file.close();
image.pop_back();
// ARRAY CREATION
int array_1D_size = image.size();
int *array_1D = (int*)malloc(sizeof(int)*array_1D_size);
for (int i = 0; i < array_1D_size; i++)
{
array_1D[i] = image[i];
}
// convert_1d_to_2d(array_1D_size, array_1D);
// HISTOGRAMM ARRAY CREATION
int hist_array_1D_size = 226;
int *hist_array_1D = (int*)malloc(sizeof(int)*hist_array_1D_size);
for (int i = 0; i < hist_array_1D_size; i++)
{
hist_array_1D[i] = 0;
}
// ---------- CUDA ZONE -------------
// printf("This is done by CPU before CUDA threads\n");
// ARRAY TO DEVICE
int *array_1D_cuda;
cudaMalloc(&array_1D_cuda, sizeof(int)*array_1D_size);
cudaMemcpy(array_1D_cuda, array_1D, array_1D_size * sizeof(int), cudaMemcpyHostToDevice);
// HSTOGRAMM ARRAY TO DEVICE
int *hist_array_1D_cuda;
cudaMalloc(&hist_array_1D_cuda, sizeof(int)*hist_array_1D_size);
cudaMemcpy(hist_array_1D_cuda, hist_array_1D, hist_array_1D_size * sizeof(int), cudaMemcpyHostToDevice);
// HISTOGRAM CREATION PROCESS
int blocksDim = 10;
int threadsDim = hist_array_1D_size /blocksDim;
//printf("array_1D_size = %d\n",hist_array_1D_size);
Histogram<<<blocksDim,threadsDim>>>(hist_array_1D_size,array_1D_size,hist_array_1D_cuda,array_1D_cuda);
cudaMemcpy(hist_array_1D, hist_array_1D_cuda, hist_array_1D_size*sizeof(int), cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
print_matrix(hist_array_1D,hist_array_1D_size);
//printf("End of program");
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <fstream>
#include <stdio.h>
#include <stdlib.h>
#include <vector>
#include <math.h>
using namespace std;
// CUDA KERNEL FUNCTIONS
__global__ void Hello()
{
//int globalidx = threadIdx.z * blockDim.x * blockDim.y + threadIdx.y * blockDim.x + threadIdx.x;
int globalidx = blockIdx.x * blockDim.x + threadIdx.x;
// printf("blockIdx.x %d\n",blockIdx.x);
printf("Hello from blockx = %d\t tx = %d\t ty=%d\t tz=%d\t gi=%d\n",blockIdx.x, threadIdx.x, threadIdx.y, threadIdx.z, globalidx);
}
__global__ void Histogram(int hist_array_1D_size,int array_1D_size, int *hist_array_1D_cuda, int *array_1D_cuda)
{
int globalidx = blockIdx.x * blockDim.x + threadIdx.x;
int N = hist_array_1D_size;
// printf("Hello from blockx = %d\t tx = %d\t ty=%d\t tz=%d\t gi=%d\n",blockIdx.x, threadIdx.x, threadIdx.y, threadIdx.z, globalidx);
if(globalidx<N)
{
int temp = 0;
for (int i = 0; i < array_1D_size; i++)
{
if (array_1D_cuda[i] == globalidx)
{
temp++;
}
}
hist_array_1D_cuda[globalidx] = temp;
}
}
// CPU FUNCTIONS
int ** malloc_matrix(int N)
{
int ** matrix = (int **)malloc(N * sizeof(int *));
for (int i = 0; i < N; ++i)
{
matrix[i] = (int *)malloc(N * sizeof(int));
}
return matrix;
}
float ** malloc_matrix_float(int N)
{
float ** matrix = (float **)malloc(N * sizeof(float *));
for (int i = 0; i < N; ++i)
{
matrix[i] = (float *)malloc(N * sizeof(float));
}
return matrix;
}
void print_matrix(int * matrix, int N)
{
for (int j = 0; j < N; j++)
{
cout << matrix[j] << " ";
}
cout << endl;
}
void print_matrix(int ** matrix, int N)
{
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
{
cout << matrix[i][j] << " ";
}
cout << endl;
}
cout << endl;
}
void print_matrix(float ** matrix, int N)
{
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
{
cout << matrix[i][j] << " ";
}
cout << endl;
}
cout << endl;
}
void print_matrix(float * matrix, int N)
{
for (int j = 0; j < N; j++)
{
cout << matrix[j] << " ";
}
cout << endl;
}
void convert_1d_to_2d (int array_size, int * array_1D)
{
int ** array_2D;
int array_2D_size = sqrt(array_size);
array_2D = malloc_matrix(array_2D_size);
for (int i = 0; i < array_2D_size; i++)
{
for (int j = 0; j < array_2D_size; j++)
{
array_2D[i][j] = array_1D[i*array_2D_size + j];
}
}
print_matrix(array_2D,array_2D_size);
}
void convert_1d_to_2d_float (int array_size, float * array_1D)
{
float ** array_2D;
int array_2D_size = sqrt(array_size);
array_2D = malloc_matrix_float(array_2D_size);
for (int i = 0; i < array_2D_size; i++)
{
for (int j = 0; j < array_2D_size; j++)
{
array_2D[i][j] = array_1D[i*array_2D_size + j];
}
}
print_matrix(array_2D,array_2D_size);
}
// MAIN FUNCTION
int main(int argc, char *argv[]){
// IMAGE TO ARRAY
ifstream file("image_array.txt");
vector<int> image;
if(file.is_open())
{
while (!file.eof())
{
int temp;
file >> temp;
image.push_back(temp);
}
}
file.close();
image.pop_back();
// ARRAY CREATION
int array_1D_size = image.size();
int *array_1D = (int*)malloc(sizeof(int)*array_1D_size);
for (int i = 0; i < array_1D_size; i++)
{
array_1D[i] = image[i];
}
// convert_1d_to_2d(array_1D_size, array_1D);
// HISTOGRAMM ARRAY CREATION
int hist_array_1D_size = 226;
int *hist_array_1D = (int*)malloc(sizeof(int)*hist_array_1D_size);
for (int i = 0; i < hist_array_1D_size; i++)
{
hist_array_1D[i] = 0;
}
// ---------- CUDA ZONE -------------
// printf("This is done by CPU before CUDA threads\n");
// ARRAY TO DEVICE
int *array_1D_cuda;
hipMalloc(&array_1D_cuda, sizeof(int)*array_1D_size);
hipMemcpy(array_1D_cuda, array_1D, array_1D_size * sizeof(int), hipMemcpyHostToDevice);
// HSTOGRAMM ARRAY TO DEVICE
int *hist_array_1D_cuda;
hipMalloc(&hist_array_1D_cuda, sizeof(int)*hist_array_1D_size);
hipMemcpy(hist_array_1D_cuda, hist_array_1D, hist_array_1D_size * sizeof(int), hipMemcpyHostToDevice);
// HISTOGRAM CREATION PROCESS
int blocksDim = 10;
int threadsDim = hist_array_1D_size /blocksDim;
//printf("array_1D_size = %d\n",hist_array_1D_size);
Histogram<<<blocksDim,threadsDim>>>(hist_array_1D_size,array_1D_size,hist_array_1D_cuda,array_1D_cuda);
hipMemcpy(hist_array_1D, hist_array_1D_cuda, hist_array_1D_size*sizeof(int), hipMemcpyDeviceToHost);
hipDeviceSynchronize();
print_matrix(hist_array_1D,hist_array_1D_size);
//printf("End of program");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <fstream>
#include <stdio.h>
#include <stdlib.h>
#include <vector>
#include <math.h>
using namespace std;
// CUDA KERNEL FUNCTIONS
__global__ void Hello()
{
//int globalidx = threadIdx.z * blockDim.x * blockDim.y + threadIdx.y * blockDim.x + threadIdx.x;
int globalidx = blockIdx.x * blockDim.x + threadIdx.x;
// printf("blockIdx.x %d\n",blockIdx.x);
printf("Hello from blockx = %d\t tx = %d\t ty=%d\t tz=%d\t gi=%d\n",blockIdx.x, threadIdx.x, threadIdx.y, threadIdx.z, globalidx);
}
__global__ void Histogram(int hist_array_1D_size,int array_1D_size, int *hist_array_1D_cuda, int *array_1D_cuda)
{
int globalidx = blockIdx.x * blockDim.x + threadIdx.x;
int N = hist_array_1D_size;
// printf("Hello from blockx = %d\t tx = %d\t ty=%d\t tz=%d\t gi=%d\n",blockIdx.x, threadIdx.x, threadIdx.y, threadIdx.z, globalidx);
if(globalidx<N)
{
int temp = 0;
for (int i = 0; i < array_1D_size; i++)
{
if (array_1D_cuda[i] == globalidx)
{
temp++;
}
}
hist_array_1D_cuda[globalidx] = temp;
}
}
// CPU FUNCTIONS
int ** malloc_matrix(int N)
{
int ** matrix = (int **)malloc(N * sizeof(int *));
for (int i = 0; i < N; ++i)
{
matrix[i] = (int *)malloc(N * sizeof(int));
}
return matrix;
}
float ** malloc_matrix_float(int N)
{
float ** matrix = (float **)malloc(N * sizeof(float *));
for (int i = 0; i < N; ++i)
{
matrix[i] = (float *)malloc(N * sizeof(float));
}
return matrix;
}
void print_matrix(int * matrix, int N)
{
for (int j = 0; j < N; j++)
{
cout << matrix[j] << " ";
}
cout << endl;
}
void print_matrix(int ** matrix, int N)
{
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
{
cout << matrix[i][j] << " ";
}
cout << endl;
}
cout << endl;
}
void print_matrix(float ** matrix, int N)
{
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
{
cout << matrix[i][j] << " ";
}
cout << endl;
}
cout << endl;
}
void print_matrix(float * matrix, int N)
{
for (int j = 0; j < N; j++)
{
cout << matrix[j] << " ";
}
cout << endl;
}
void convert_1d_to_2d (int array_size, int * array_1D)
{
int ** array_2D;
int array_2D_size = sqrt(array_size);
array_2D = malloc_matrix(array_2D_size);
for (int i = 0; i < array_2D_size; i++)
{
for (int j = 0; j < array_2D_size; j++)
{
array_2D[i][j] = array_1D[i*array_2D_size + j];
}
}
print_matrix(array_2D,array_2D_size);
}
void convert_1d_to_2d_float (int array_size, float * array_1D)
{
float ** array_2D;
int array_2D_size = sqrt(array_size);
array_2D = malloc_matrix_float(array_2D_size);
for (int i = 0; i < array_2D_size; i++)
{
for (int j = 0; j < array_2D_size; j++)
{
array_2D[i][j] = array_1D[i*array_2D_size + j];
}
}
print_matrix(array_2D,array_2D_size);
}
// MAIN FUNCTION
int main(int argc, char *argv[]){
// IMAGE TO ARRAY
ifstream file("image_array.txt");
vector<int> image;
if(file.is_open())
{
while (!file.eof())
{
int temp;
file >> temp;
image.push_back(temp);
}
}
file.close();
image.pop_back();
// ARRAY CREATION
int array_1D_size = image.size();
int *array_1D = (int*)malloc(sizeof(int)*array_1D_size);
for (int i = 0; i < array_1D_size; i++)
{
array_1D[i] = image[i];
}
// convert_1d_to_2d(array_1D_size, array_1D);
// HISTOGRAMM ARRAY CREATION
int hist_array_1D_size = 226;
int *hist_array_1D = (int*)malloc(sizeof(int)*hist_array_1D_size);
for (int i = 0; i < hist_array_1D_size; i++)
{
hist_array_1D[i] = 0;
}
// ---------- CUDA ZONE -------------
// printf("This is done by CPU before CUDA threads\n");
// ARRAY TO DEVICE
int *array_1D_cuda;
hipMalloc(&array_1D_cuda, sizeof(int)*array_1D_size);
hipMemcpy(array_1D_cuda, array_1D, array_1D_size * sizeof(int), hipMemcpyHostToDevice);
// HSTOGRAMM ARRAY TO DEVICE
int *hist_array_1D_cuda;
hipMalloc(&hist_array_1D_cuda, sizeof(int)*hist_array_1D_size);
hipMemcpy(hist_array_1D_cuda, hist_array_1D, hist_array_1D_size * sizeof(int), hipMemcpyHostToDevice);
// HISTOGRAM CREATION PROCESS
int blocksDim = 10;
int threadsDim = hist_array_1D_size /blocksDim;
//printf("array_1D_size = %d\n",hist_array_1D_size);
Histogram<<<blocksDim,threadsDim>>>(hist_array_1D_size,array_1D_size,hist_array_1D_cuda,array_1D_cuda);
hipMemcpy(hist_array_1D, hist_array_1D_cuda, hist_array_1D_size*sizeof(int), hipMemcpyDeviceToHost);
hipDeviceSynchronize();
print_matrix(hist_array_1D,hist_array_1D_size);
//printf("End of program");
return 0;
} | .text
.file "cuda_histogram.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z20__device_stub__Hellov # -- Begin function _Z20__device_stub__Hellov
.p2align 4, 0x90
.type _Z20__device_stub__Hellov,@function
_Z20__device_stub__Hellov: # @_Z20__device_stub__Hellov
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5Hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z20__device_stub__Hellov, .Lfunc_end0-_Z20__device_stub__Hellov
.cfi_endproc
# -- End function
.globl _Z24__device_stub__HistogramiiPiS_ # -- Begin function _Z24__device_stub__HistogramiiPiS_
.p2align 4, 0x90
.type _Z24__device_stub__HistogramiiPiS_,@function
_Z24__device_stub__HistogramiiPiS_: # @_Z24__device_stub__HistogramiiPiS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9HistogramiiPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z24__device_stub__HistogramiiPiS_, .Lfunc_end1-_Z24__device_stub__HistogramiiPiS_
.cfi_endproc
# -- End function
.globl _Z13malloc_matrixi # -- Begin function _Z13malloc_matrixi
.p2align 4, 0x90
.type _Z13malloc_matrixi,@function
_Z13malloc_matrixi: # @_Z13malloc_matrixi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movslq %edi, %r15
leaq (,%r15,8), %rdi
callq malloc
movq %rax, %rbx
testl %r15d, %r15d
jle .LBB2_3
# %bb.1: # %.lr.ph
leaq (,%r15,4), %r14
movl %r15d, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_2: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
callq malloc
movq %rax, (%rbx,%r12,8)
incq %r12
cmpq %r12, %r15
jne .LBB2_2
.LBB2_3: # %._crit_edge
movq %rbx, %rax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z13malloc_matrixi, .Lfunc_end2-_Z13malloc_matrixi
.cfi_endproc
# -- End function
.globl _Z19malloc_matrix_floati # -- Begin function _Z19malloc_matrix_floati
.p2align 4, 0x90
.type _Z19malloc_matrix_floati,@function
_Z19malloc_matrix_floati: # @_Z19malloc_matrix_floati
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movslq %edi, %r15
leaq (,%r15,8), %rdi
callq malloc
movq %rax, %rbx
testl %r15d, %r15d
jle .LBB3_3
# %bb.1: # %.lr.ph
leaq (,%r15,4), %r14
movl %r15d, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_2: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
callq malloc
movq %rax, (%rbx,%r12,8)
incq %r12
cmpq %r12, %r15
jne .LBB3_2
.LBB3_3: # %._crit_edge
movq %rbx, %rax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z19malloc_matrix_floati, .Lfunc_end3-_Z19malloc_matrix_floati
.cfi_endproc
# -- End function
.globl _Z12print_matrixPii # -- Begin function _Z12print_matrixPii
.p2align 4, 0x90
.type _Z12print_matrixPii,@function
_Z12print_matrixPii: # @_Z12print_matrixPii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
testl %esi, %esi
jle .LBB4_3
# %bb.1: # %.lr.ph.preheader
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r15
cmpq %r15, %r14
jne .LBB4_2
.LBB4_3: # %._crit_edge
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB4_8
# %bb.4: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB4_6
# %bb.5:
movzbl 67(%rbx), %eax
jmp .LBB4_7
.LBB4_6:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_7: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp _ZNSo5flushEv # TAILCALL
.LBB4_8:
.cfi_def_cfa_offset 32
callq _ZSt16__throw_bad_castv
.Lfunc_end4:
.size _Z12print_matrixPii, .Lfunc_end4-_Z12print_matrixPii
.cfi_endproc
# -- End function
.globl _Z12print_matrixPPii # -- Begin function _Z12print_matrixPPii
.p2align 4, 0x90
.type _Z12print_matrixPPii,@function
_Z12print_matrixPPii: # @_Z12print_matrixPPii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
testl %esi, %esi
jle .LBB5_7
# %bb.1: # %.preheader.lr.ph
movq %rdi, %rbx
movl %esi, %r15d
xorl %r12d, %r12d
jmp .LBB5_2
.p2align 4, 0x90
.LBB5_12: # in Loop: Header=BB5_2 Depth=1
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB5_13: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit14
# in Loop: Header=BB5_2 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r12
cmpq %r15, %r12
je .LBB5_7
.LBB5_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB5_3 Depth 2
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB5_3: # Parent Loop BB5_2 Depth=1
# => This Inner Loop Header: Depth=2
movq (%rbx,%r12,8), %rax
movl (%rax,%r14,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r14
cmpq %r14, %r15
jne .LBB5_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB5_2 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB5_14
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i11
# in Loop: Header=BB5_2 Depth=1
cmpb $0, 56(%r14)
je .LBB5_12
# %bb.6: # in Loop: Header=BB5_2 Depth=1
movzbl 67(%r14), %eax
jmp .LBB5_13
.LBB5_7: # %._crit_edge17
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB5_14
# %bb.8: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB5_10
# %bb.9:
movzbl 67(%rbx), %eax
jmp .LBB5_11
.LBB5_10:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB5_11: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp _ZNSo5flushEv # TAILCALL
.LBB5_14:
.cfi_def_cfa_offset 48
callq _ZSt16__throw_bad_castv
.Lfunc_end5:
.size _Z12print_matrixPPii, .Lfunc_end5-_Z12print_matrixPPii
.cfi_endproc
# -- End function
.globl _Z12print_matrixPPfi # -- Begin function _Z12print_matrixPPfi
.p2align 4, 0x90
.type _Z12print_matrixPPfi,@function
_Z12print_matrixPPfi: # @_Z12print_matrixPPfi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
testl %esi, %esi
jle .LBB6_7
# %bb.1: # %.preheader.lr.ph
movq %rdi, %rbx
movl %esi, %r15d
xorl %r12d, %r12d
jmp .LBB6_2
.p2align 4, 0x90
.LBB6_12: # in Loop: Header=BB6_2 Depth=1
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB6_13: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit14
# in Loop: Header=BB6_2 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r12
cmpq %r15, %r12
je .LBB6_7
.LBB6_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB6_3 Depth 2
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB6_3: # Parent Loop BB6_2 Depth=1
# => This Inner Loop Header: Depth=2
movq (%rbx,%r12,8), %rax
movss (%rax,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r14
cmpq %r14, %r15
jne .LBB6_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB6_2 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB6_14
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i11
# in Loop: Header=BB6_2 Depth=1
cmpb $0, 56(%r14)
je .LBB6_12
# %bb.6: # in Loop: Header=BB6_2 Depth=1
movzbl 67(%r14), %eax
jmp .LBB6_13
.LBB6_7: # %._crit_edge17
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB6_14
# %bb.8: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB6_10
# %bb.9:
movzbl 67(%rbx), %eax
jmp .LBB6_11
.LBB6_10:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB6_11: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp _ZNSo5flushEv # TAILCALL
.LBB6_14:
.cfi_def_cfa_offset 48
callq _ZSt16__throw_bad_castv
.Lfunc_end6:
.size _Z12print_matrixPPfi, .Lfunc_end6-_Z12print_matrixPPfi
.cfi_endproc
# -- End function
.globl _Z12print_matrixPfi # -- Begin function _Z12print_matrixPfi
.p2align 4, 0x90
.type _Z12print_matrixPfi,@function
_Z12print_matrixPfi: # @_Z12print_matrixPfi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
testl %esi, %esi
jle .LBB7_3
# %bb.1: # %.lr.ph.preheader
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB7_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r15
cmpq %r15, %r14
jne .LBB7_2
.LBB7_3: # %._crit_edge
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB7_8
# %bb.4: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB7_6
# %bb.5:
movzbl 67(%rbx), %eax
jmp .LBB7_7
.LBB7_6:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB7_7: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp _ZNSo5flushEv # TAILCALL
.LBB7_8:
.cfi_def_cfa_offset 32
callq _ZSt16__throw_bad_castv
.Lfunc_end7:
.size _Z12print_matrixPfi, .Lfunc_end7-_Z12print_matrixPfi
.cfi_endproc
# -- End function
.globl _Z16convert_1d_to_2diPi # -- Begin function _Z16convert_1d_to_2diPi
.p2align 4, 0x90
.type _Z16convert_1d_to_2diPi,@function
_Z16convert_1d_to_2diPi: # @_Z16convert_1d_to_2diPi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cvtsi2sd %edi, %xmm0
movq %rsi, %rbx
xorpd %xmm1, %xmm1
ucomisd %xmm1, %xmm0
jb .LBB8_2
# %bb.1:
sqrtsd %xmm0, %xmm0
jmp .LBB8_3
.LBB8_2: # %call.sqrt
callq sqrt
.LBB8_3: # %.split
cvttsd2si %xmm0, %ebp
movslq %ebp, %r15
leaq (,%r15,8), %rdi
callq malloc
movq %rax, %r14
testl %r15d, %r15d
jle .LBB8_6
# %bb.4: # %.lr.ph.i
shlq $2, %r15
movl %ebp, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB8_5: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
callq malloc
movq %rax, (%r14,%r13,8)
incq %r13
cmpq %r13, %r12
jne .LBB8_5
.LBB8_6: # %_Z13malloc_matrixi.exit
testl %ebp, %ebp
jle .LBB8_11
# %bb.7: # %.preheader.lr.ph
movl %ebp, %eax
xorl %ecx, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB8_8: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB8_9 Depth 2
movl %ecx, %esi
leaq (%rbx,%rsi,4), %rsi
movq (%r14,%rdx,8), %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB8_9: # Parent Loop BB8_8 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rsi,%r8,4), %r9d
movl %r9d, (%rdi,%r8,4)
incq %r8
cmpq %r8, %rax
jne .LBB8_9
# %bb.10: # %._crit_edge
# in Loop: Header=BB8_8 Depth=1
incq %rdx
addl %ebp, %ecx
cmpq %rax, %rdx
jne .LBB8_8
.LBB8_11: # %._crit_edge20
movq %r14, %rdi
movl %ebp, %esi
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp _Z12print_matrixPPii # TAILCALL
.Lfunc_end8:
.size _Z16convert_1d_to_2diPi, .Lfunc_end8-_Z16convert_1d_to_2diPi
.cfi_endproc
# -- End function
.globl _Z22convert_1d_to_2d_floatiPf # -- Begin function _Z22convert_1d_to_2d_floatiPf
.p2align 4, 0x90
.type _Z22convert_1d_to_2d_floatiPf,@function
_Z22convert_1d_to_2d_floatiPf: # @_Z22convert_1d_to_2d_floatiPf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cvtsi2sd %edi, %xmm0
movq %rsi, %rbx
xorpd %xmm1, %xmm1
ucomisd %xmm1, %xmm0
jb .LBB9_2
# %bb.1:
sqrtsd %xmm0, %xmm0
jmp .LBB9_3
.LBB9_2: # %call.sqrt
callq sqrt
.LBB9_3: # %.split
cvttsd2si %xmm0, %ebp
movslq %ebp, %r15
leaq (,%r15,8), %rdi
callq malloc
movq %rax, %r14
testl %r15d, %r15d
jle .LBB9_6
# %bb.4: # %.lr.ph.i
shlq $2, %r15
movl %ebp, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB9_5: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
callq malloc
movq %rax, (%r14,%r13,8)
incq %r13
cmpq %r13, %r12
jne .LBB9_5
.LBB9_6: # %_Z19malloc_matrix_floati.exit
testl %ebp, %ebp
jle .LBB9_11
# %bb.7: # %.preheader.lr.ph
movl %ebp, %eax
xorl %ecx, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB9_8: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB9_9 Depth 2
movl %ecx, %esi
leaq (%rbx,%rsi,4), %rsi
movq (%r14,%rdx,8), %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB9_9: # Parent Loop BB9_8 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rsi,%r8,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%rdi,%r8,4)
incq %r8
cmpq %r8, %rax
jne .LBB9_9
# %bb.10: # %._crit_edge
# in Loop: Header=BB9_8 Depth=1
incq %rdx
addl %ebp, %ecx
cmpq %rax, %rdx
jne .LBB9_8
.LBB9_11: # %._crit_edge20
movq %r14, %rdi
movl %ebp, %esi
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp _Z12print_matrixPPfi # TAILCALL
.Lfunc_end9:
.size _Z22convert_1d_to_2d_floatiPf, .Lfunc_end9-_Z22convert_1d_to_2d_floatiPf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $648, %rsp # imm = 0x288
.cfi_def_cfa_offset 704
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
.cfi_escape 0x2e, 0x00
leaq 128(%rsp), %rdi
movl $.L.str.1, %esi
movl $8, %edx
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
leaq 248(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq _ZNKSt12__basic_fileIcE7is_openEv
testb %al, %al
je .LBB10_1
# %bb.2: # %.preheader
movq 128(%rsp), %rax
movq -24(%rax), %rax
testb $2, 160(%rsp,%rax)
jne .LBB10_1
# %bb.3: # %.lr.ph.preheader
xorl %r15d, %r15d
leaq 32(%rsp), %r13
xorl %r14d, %r14d
xorl %ebp, %ebp
jmp .LBB10_4
.p2align 4, 0x90
.LBB10_6: # in Loop: Header=BB10_4 Depth=1
movl 32(%rsp), %eax
movl %eax, (%r14)
movq %r15, %rbx
.LBB10_23: # %_ZNSt6vectorIiSaIiEE9push_backERKi.exit
# in Loop: Header=BB10_4 Depth=1
addq $4, %r14
movq 128(%rsp), %rax
movq -24(%rax), %rax
testb $2, 160(%rsp,%rax)
jne .LBB10_24
.LBB10_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
.Ltmp0:
.cfi_escape 0x2e, 0x00
leaq 128(%rsp), %rdi
movq %r13, %rsi
callq _ZNSirsERi
.Ltmp1:
# %bb.5: # in Loop: Header=BB10_4 Depth=1
cmpq %rbp, %r14
jne .LBB10_6
# %bb.7: # in Loop: Header=BB10_4 Depth=1
subq %r15, %r14
movabsq $9223372036854775804, %rax # imm = 0x7FFFFFFFFFFFFFFC
cmpq %rax, %r14
je .LBB10_8
# %bb.10: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i
# in Loop: Header=BB10_4 Depth=1
movq %r14, %r12
sarq $2, %r12
cmpq $1, %r12
movq %r12, %rax
adcq $0, %rax
leaq (%rax,%r12), %rcx
movabsq $2305843009213693951, %rbp # imm = 0x1FFFFFFFFFFFFFFF
cmpq %rbp, %rcx
jae .LBB10_11
# %bb.12: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i
# in Loop: Header=BB10_4 Depth=1
addq %r12, %rax
jae .LBB10_13
.LBB10_14: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i
# in Loop: Header=BB10_4 Depth=1
testq %rbp, %rbp
je .LBB10_15
.LBB10_16: # in Loop: Header=BB10_4 Depth=1
leaq (,%rbp,4), %rdi
.Ltmp2:
.cfi_escape 0x2e, 0x00
callq _Znwm
.Ltmp3:
# %bb.17: # in Loop: Header=BB10_4 Depth=1
movq %rax, %rbx
jmp .LBB10_18
.LBB10_11: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i
# in Loop: Header=BB10_4 Depth=1
movq %rbp, %rcx
addq %r12, %rax
jb .LBB10_14
.LBB10_13: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i
# in Loop: Header=BB10_4 Depth=1
movq %rcx, %rbp
testq %rbp, %rbp
jne .LBB10_16
.LBB10_15: # in Loop: Header=BB10_4 Depth=1
xorl %ebx, %ebx
.LBB10_18: # %_ZNSt12_Vector_baseIiSaIiEE11_M_allocateEm.exit.i.i
# in Loop: Header=BB10_4 Depth=1
movl 32(%rsp), %eax
movl %eax, (%rbx,%r12,4)
testq %r14, %r14
jle .LBB10_20
# %bb.19: # in Loop: Header=BB10_4 Depth=1
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movq %r15, %rsi
movq %r14, %rdx
callq memmove@PLT
.LBB10_20: # %_ZNSt6vectorIiSaIiEE11_S_relocateEPiS2_S2_RS0_.exit.i.i
# in Loop: Header=BB10_4 Depth=1
testq %r15, %r15
je .LBB10_22
# %bb.21: # in Loop: Header=BB10_4 Depth=1
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZdlPv
.LBB10_22: # %_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_.exit.i
# in Loop: Header=BB10_4 Depth=1
addq %rbx, %r14
leaq (%rbx,%rbp,4), %rbp
movq %rbx, %r15
jmp .LBB10_23
.LBB10_1:
xorl %r14d, %r14d
xorl %ebx, %ebx
.LBB10_24: # %.loopexit
leaq 144(%rsp), %rdi
.Ltmp5:
.cfi_escape 0x2e, 0x00
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp6:
# %bb.25: # %.noexc45
testq %rax, %rax
jne .LBB10_27
# %bb.26:
movq 128(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $128, %rdi
movl 160(%rsp,%rax), %esi
orl $4, %esi
.Ltmp7:
.cfi_escape 0x2e, 0x00
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp8:
.LBB10_27: # %_ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv.exit
subq %rbx, %r14
addq $-4, %r14
movq %r14, %r13
shrq $2, %r13
shlq $30, %r14
sarq $30, %r14
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq malloc
movq %rax, %r12
testl %r13d, %r13d
jle .LBB10_30
# %bb.28: # %.lr.ph80.preheader
movl %r13d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB10_29: # %.lr.ph80
# =>This Inner Loop Header: Depth=1
movl (%rbx,%rcx,4), %edx
movl %edx, (%r12,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB10_29
.LBB10_30: # %._crit_edge
.cfi_escape 0x2e, 0x00
movl $904, %edi # imm = 0x388
callq malloc
movq %rax, %r15
.cfi_escape 0x2e, 0x00
movl $904, %edx # imm = 0x388
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.Ltmp10:
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
.Ltmp11:
# %bb.31: # %_ZL9hipMallocIiE10hipError_tPPT_m.exit
movq 24(%rsp), %rdi
.Ltmp12:
.cfi_escape 0x2e, 0x00
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
.Ltmp13:
# %bb.32:
.Ltmp15:
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $904, %esi # imm = 0x388
callq hipMalloc
.Ltmp16:
# %bb.33: # %_ZL9hipMallocIiE10hipError_tPPT_m.exit49
movq 8(%rsp), %rdi
.Ltmp17:
.cfi_escape 0x2e, 0x00
movl $904, %edx # imm = 0x388
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp18:
# %bb.34:
.Ltmp20:
.cfi_escape 0x2e, 0x00
movabsq $4294967306, %rdi # imm = 0x10000000A
movabsq $4294967318, %rdx # imm = 0x100000016
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp21:
# %bb.35:
testl %eax, %eax
jne .LBB10_38
# %bb.36:
movq 8(%rsp), %rax
movq 24(%rsp), %rcx
movl $226, 20(%rsp)
movl %r13d, 16(%rsp)
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 32(%rsp)
leaq 16(%rsp), %rax
movq %rax, 40(%rsp)
leaq 120(%rsp), %rax
movq %rax, 48(%rsp)
leaq 112(%rsp), %rax
movq %rax, 56(%rsp)
.Ltmp22:
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp23:
# %bb.37: # %.noexc50
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
.Ltmp24:
.cfi_escape 0x2e, 0x10
leaq 32(%rsp), %r9
movl $_Z9HistogramiiPiS_, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp25:
.LBB10_38:
movq 8(%rsp), %rsi
.Ltmp26:
.cfi_escape 0x2e, 0x00
movl $904, %edx # imm = 0x388
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp27:
# %bb.39:
.Ltmp28:
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.Ltmp29:
# %bb.40:
.Ltmp30:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $226, %esi
callq _Z12print_matrixPii
.Ltmp31:
# %bb.41:
testq %rbx, %rbx
je .LBB10_43
# %bb.42:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.LBB10_43: # %_ZNSt6vectorIiSaIiEED2Ev.exit
.cfi_escape 0x2e, 0x00
leaq 128(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 384(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq _ZNSt8ios_baseD2Ev
xorl %eax, %eax
addq $648, %rsp # imm = 0x288
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB10_8:
.cfi_def_cfa_offset 704
.Ltmp33:
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp34:
# %bb.9: # %.noexc
.LBB10_44:
.Ltmp9:
jmp .LBB10_51
.LBB10_50:
.Ltmp19:
jmp .LBB10_51
.LBB10_48:
.Ltmp14:
jmp .LBB10_51
.LBB10_47: # %.loopexit.split-lp
.Ltmp35:
jmp .LBB10_46
.LBB10_49:
.Ltmp32:
.LBB10_51:
movq %rax, %r14
jmp .LBB10_52
.LBB10_45: # %.loopexit67
.Ltmp4:
.LBB10_46:
movq %rax, %r14
movq %r15, %rbx
.LBB10_52:
testq %rbx, %rbx
je .LBB10_54
# %bb.53:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.LBB10_54: # %_ZNSt6vectorIiSaIiEED2Ev.exit54
.cfi_escape 0x2e, 0x00
leaq 128(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 384(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq _ZNSt8ios_baseD2Ev
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end10:
.size main, .Lfunc_end10-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table10:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp3-.Ltmp0 # Call between .Ltmp0 and .Ltmp3
.uleb128 .Ltmp4-.Lfunc_begin0 # jumps to .Ltmp4
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp5-.Ltmp3 # Call between .Ltmp3 and .Ltmp5
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp5-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp8-.Ltmp5 # Call between .Ltmp5 and .Ltmp8
.uleb128 .Ltmp9-.Lfunc_begin0 # jumps to .Ltmp9
.byte 0 # On action: cleanup
.uleb128 .Ltmp8-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp10-.Ltmp8 # Call between .Ltmp8 and .Ltmp10
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp13-.Ltmp10 # Call between .Ltmp10 and .Ltmp13
.uleb128 .Ltmp14-.Lfunc_begin0 # jumps to .Ltmp14
.byte 0 # On action: cleanup
.uleb128 .Ltmp15-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp18-.Ltmp15 # Call between .Ltmp15 and .Ltmp18
.uleb128 .Ltmp19-.Lfunc_begin0 # jumps to .Ltmp19
.byte 0 # On action: cleanup
.uleb128 .Ltmp20-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp31-.Ltmp20 # Call between .Ltmp20 and .Ltmp31
.uleb128 .Ltmp32-.Lfunc_begin0 # jumps to .Ltmp32
.byte 0 # On action: cleanup
.uleb128 .Ltmp33-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp34-.Ltmp33 # Call between .Ltmp33 and .Ltmp34
.uleb128 .Ltmp35-.Lfunc_begin0 # jumps to .Ltmp35
.byte 0 # On action: cleanup
.uleb128 .Ltmp34-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Lfunc_end10-.Ltmp34 # Call between .Ltmp34 and .Lfunc_end10
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB11_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB11_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5Hellov, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9HistogramiiPiS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end11:
.size __hip_module_ctor, .Lfunc_end11-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB12_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB12_2:
retq
.Lfunc_end12:
.size __hip_module_dtor, .Lfunc_end12-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5Hellov,@object # @_Z5Hellov
.section .rodata,"a",@progbits
.globl _Z5Hellov
.p2align 3, 0x0
_Z5Hellov:
.quad _Z20__device_stub__Hellov
.size _Z5Hellov, 8
.type _Z9HistogramiiPiS_,@object # @_Z9HistogramiiPiS_
.globl _Z9HistogramiiPiS_
.p2align 3, 0x0
_Z9HistogramiiPiS_:
.quad _Z24__device_stub__HistogramiiPiS_
.size _Z9HistogramiiPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "image_array.txt"
.size .L.str.1, 16
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "vector::_M_realloc_insert"
.size .L.str.2, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5Hellov"
.size .L__unnamed_1, 10
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9HistogramiiPiS_"
.size .L__unnamed_2, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__Hellov
.addrsig_sym _Z24__device_stub__HistogramiiPiS_
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z5Hellov
.addrsig_sym _Z9HistogramiiPiS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#define T_PER_BLOCK 16
#define MINF __int_as_float(0xff800000)
__global__ void erodeDepthMapDevice(float* d_output, float* d_input, int structureSize, int width, int height, float dThresh, float fracReq)
{
const int x = blockIdx.x*blockDim.x + threadIdx.x;
const int y = blockIdx.y*blockDim.y + threadIdx.y;
if (x >= 0 && x < width && y >= 0 && y < height)
{
unsigned int count = 0;
float oldDepth = d_input[y*width + x];
for (int i = -structureSize; i <= structureSize; i++)
{
for (int j = -structureSize; j <= structureSize; j++)
{
if (x + j >= 0 && x + j < width && y + i >= 0 && y + i < height)
{
float depth = d_input[(y + i)*width + (x + j)];
if (depth == MINF || depth == 0.0f || fabs(depth - oldDepth) > dThresh)
{
count++;
//d_output[y*width+x] = MINF;
//return;
}
}
}
}
unsigned int sum = (2 * structureSize + 1)*(2 * structureSize + 1);
if ((float)count / (float)sum >= fracReq) {
d_output[y*width + x] = MINF;
}
else {
d_output[y*width + x] = d_input[y*width + x];
}
}
} | code for sm_80
Function : _Z19erodeDepthMapDevicePfS_iiiff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e680000002600 */
/*0040*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x174], PT ; /* 0x00005d0006007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R7, R7, c[0x0][0x4], R0 ; /* 0x0000010007077a24 */
/* 0x002fca00078e0200 */
/*0080*/ LOP3.LUT R0, R6, R7, RZ, 0xfc, !PT ; /* 0x0000000706007212 */
/* 0x000fc800078efcff */
/*0090*/ ISETP.LT.OR P0, PT, R0, RZ, P0 ; /* 0x000000ff0000720c */
/* 0x000fc80000701670 */
/*00a0*/ ISETP.GE.OR P0, PT, R7, c[0x0][0x178], P0 ; /* 0x00005e0007007a0c */
/* 0x000fda0000706670 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*00d0*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*00e0*/ IMAD R0, R7, c[0x0][0x174], R6 ; /* 0x00005d0007007a24 */
/* 0x000fc800078e0206 */
/*00f0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0203 */
/*0100*/ LDG.E R4, [R2.64] ; /* 0x0000000802047981 */
/* 0x000162000c1e1900 */
/*0110*/ IMAD.MOV R8, RZ, RZ, -c[0x0][0x170] ; /* 0x80005c00ff087624 */
/* 0x000fe200078e02ff */
/*0120*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x000fe20000011400 */
/*0130*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fc600078e00ff */
/*0140*/ ISETP.GT.AND P0, PT, R8, c[0x0][0x170], PT ; /* 0x00005c0008007a0c */
/* 0x000fda0003f04270 */
/*0150*/ @P0 BRA 0xa80 ; /* 0x0000092000000947 */
/* 0x000fea0003800000 */
/*0160*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x001fe20000000800 */
/*0170*/ IMNMX R10, R8, c[0x0][0x170], !PT ; /* 0x00005c00080a7a17 */
/* 0x000fe20007800200 */
/*0180*/ UIADD3 UR5, -UR4, 0x1, URZ ; /* 0x0000000104057890 */
/* 0x000fe2000fffe13f */
/*0190*/ IADD3 R9, R6, -c[0x0][0x170], RZ ; /* 0x80005c0006097a10 */
/* 0x000fe20007ffe0ff */
/*01a0*/ UIADD3 UR6, -UR4, 0x2, URZ ; /* 0x0000000204067890 */
/* 0x000fe2000fffe13f */
/*01b0*/ IADD3 R10, R10, c[0x0][0x170], RZ ; /* 0x00005c000a0a7a10 */
/* 0x000fe20007ffe0ff */
/*01c0*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e00ff */
/*01d0*/ ISETP.GE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f26270 */
/*01e0*/ IMAD.MOV.U32 R12, RZ, RZ, R8 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0008 */
/*01f0*/ IADD3 R2, R6.reuse, UR5, RZ ; /* 0x0000000506027c10 */
/* 0x040fe2000fffe0ff */
/*0200*/ UIADD3 UR4, -UR4, 0x3, URZ ; /* 0x0000000304047890 */
/* 0x000fe2000fffe13f */
/*0210*/ IADD3 R3, R6, UR6, RZ ; /* 0x0000000606037c10 */
/* 0x000fc4000fffe0ff */
/*0220*/ ISETP.GE.AND P3, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f66270 */
/*0230*/ ISETP.GE.AND P2, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720c */
/* 0x040fe40003f46270 */
/*0240*/ IADD3 R13, R10, 0x1, RZ ; /* 0x000000010a0d7810 */
/* 0x000fe40007ffe0ff */
/*0250*/ ISETP.GE.OR P3, PT, R2, c[0x0][0x174], !P3 ; /* 0x00005d0002007a0c */
/* 0x000fe40005f66670 */
/*0260*/ ISETP.GE.OR P2, PT, R3, c[0x0][0x174], !P2 ; /* 0x00005d0003007a0c */
/* 0x000fe40005746670 */
/*0270*/ ISETP.GE.OR P1, PT, R9, c[0x0][0x174], !P1 ; /* 0x00005d0009007a0c */
/* 0x000fc40004f26670 */
/*0280*/ LOP3.LUT R13, R13, 0x3, RZ, 0xc0, !PT ; /* 0x000000030d0d7812 */
/* 0x000fc800078ec0ff */
/*0290*/ ISETP.NE.AND P4, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe20003f85270 */
/*02a0*/ IMAD.IADD R14, R7, 0x1, R12 ; /* 0x00000001070e7824 */
/* 0x000fe200078e020c */
/*02b0*/ ISETP.GE.AND P6, PT, R12.reuse, c[0x0][0x170], PT ; /* 0x00005c000c007a0c */
/* 0x040fe20003fc6270 */
/*02c0*/ IMAD.MOV.U32 R15, RZ, RZ, R8 ; /* 0x000000ffff0f7224 */
/* 0x000fe200078e0008 */
/*02d0*/ IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0c7810 */
/* 0x000fe40007ffe0ff */
/*02e0*/ ISETP.GE.AND P0, PT, R14, c[0x0][0x178], PT ; /* 0x00005e000e007a0c */
/* 0x000fc80003f06270 */
/*02f0*/ ISETP.GT.AND P0, PT, R14, -0x1, !P0 ; /* 0xffffffff0e00780c */
/* 0x000fc60004704270 */
/*0300*/ @!P4 BRA 0x600 ; /* 0x000002f00000c947 */
/* 0x000fea0003800000 */
/*0310*/ PLOP3.LUT P4, PT, P1, P0, PT, 0xa2, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20000f81472 */
/*0320*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0330*/ BSSY B0, 0x410 ; /* 0x000000d000007945 */
/* 0x000fe20003800000 */
/*0340*/ IMAD R2, R14, c[0x0][0x174], R9 ; /* 0x00005d000e027a24 */
/* 0x000fe200078e0209 */
/*0350*/ ISETP.NE.AND P5, PT, R13, 0x1, PT ; /* 0x000000010d00780c */
/* 0x000fc60003fa5270 */
/*0360*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0203 */
/*0370*/ @P4 BRA 0x400 ; /* 0x0000008000004947 */
/* 0x000fea0003800000 */
/*0380*/ LDG.E R15, [R2.64] ; /* 0x00000008020f7981 */
/* 0x000ea4000c1e1900 */
/*0390*/ FSETP.NEU.AND P4, PT, R15, RZ, PT ; /* 0x000000ff0f00720b */
/* 0x004fc80003f8d000 */
/*03a0*/ FSETP.EQ.OR P4, PT, R15, -INF , !P4 ; /* 0xff8000000f00780b */
/* 0x000fda0006782400 */
/*03b0*/ @!P4 FADD R15, -R4, R15 ; /* 0x0000000f040fc221 */
/* 0x020fca0000000100 */
/*03c0*/ FSETP.GT.OR P4, PT, |R15|, c[0x0][0x17c], P4 ; /* 0x00005f000f007a0b */
/* 0x000fe40002784600 */
/*03d0*/ IADD3 R15, R11, 0x1, RZ ; /* 0x000000010b0f7810 */
/* 0x000fd60007ffe0ff */
/*03e0*/ @!P4 IMAD.MOV R15, RZ, RZ, R11 ; /* 0x000000ffff0fc224 */
/* 0x000fc800078e020b */
/*03f0*/ IMAD.MOV.U32 R11, RZ, RZ, R15 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e000f */
/*0400*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0410*/ IMAD.U32 R15, RZ, RZ, UR5 ; /* 0x00000005ff0f7e24 */
/* 0x000fe2000f8e00ff */
/*0420*/ @!P5 BRA 0x600 ; /* 0x000001d00000d947 */
/* 0x000fea0003800000 */
/*0430*/ PLOP3.LUT P4, PT, P3, P0, PT, 0xa2, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20001f81472 */
/*0440*/ BSSY B0, 0x500 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0450*/ ISETP.NE.AND P5, PT, R13, 0x2, PT ; /* 0x000000020d00780c */
/* 0x000fd60003fa5270 */
/*0460*/ @P4 BRA 0x4f0 ; /* 0x0000008000004947 */
/* 0x000fea0003800000 */
/*0470*/ LDG.E R15, [R2.64+0x4] ; /* 0x00000408020f7981 */
/* 0x000ea4000c1e1900 */
/*0480*/ FSETP.NEU.AND P4, PT, R15, RZ, PT ; /* 0x000000ff0f00720b */
/* 0x004fc80003f8d000 */
/*0490*/ FSETP.EQ.OR P4, PT, R15, -INF , !P4 ; /* 0xff8000000f00780b */
/* 0x000fda0006782400 */
/*04a0*/ @!P4 FADD R15, -R4, R15 ; /* 0x0000000f040fc221 */
/* 0x020fca0000000100 */
/*04b0*/ FSETP.GT.OR P4, PT, |R15|, c[0x0][0x17c], P4 ; /* 0x00005f000f007a0b */
/* 0x000fe40002784600 */
/*04c0*/ IADD3 R15, R11, 0x1, RZ ; /* 0x000000010b0f7810 */
/* 0x000fd60007ffe0ff */
/*04d0*/ @!P4 IMAD.MOV R15, RZ, RZ, R11 ; /* 0x000000ffff0fc224 */
/* 0x000fc800078e020b */
/*04e0*/ IMAD.MOV.U32 R11, RZ, RZ, R15 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e000f */
/*04f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0500*/ IMAD.U32 R15, RZ, RZ, UR6 ; /* 0x00000006ff0f7e24 */
/* 0x000fe2000f8e00ff */
/*0510*/ @!P5 BRA 0x600 ; /* 0x000000e00000d947 */
/* 0x000fea0003800000 */
/*0520*/ PLOP3.LUT P4, PT, P2, P0, PT, 0xa2, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20001781472 */
/*0530*/ BSSY B0, 0x600 ; /* 0x000000c000007945 */
/* 0x000fe20003800000 */
/*0540*/ IMAD.U32 R15, RZ, RZ, UR4 ; /* 0x00000004ff0f7e24 */
/* 0x000fd6000f8e00ff */
/*0550*/ @P4 BRA 0x5f0 ; /* 0x0000009000004947 */
/* 0x000fea0003800000 */
/*0560*/ LDG.E R3, [R2.64+0x8] ; /* 0x0000080802037981 */
/* 0x000ea2000c1e1900 */
/*0570*/ IADD3 R16, R11, 0x1, RZ ; /* 0x000000010b107810 */
/* 0x000fe40007ffe0ff */
/*0580*/ FSETP.NEU.AND P4, PT, R3, RZ, PT ; /* 0x000000ff0300720b */
/* 0x004fc80003f8d000 */
/*0590*/ FSETP.EQ.OR P4, PT, R3, -INF , !P4 ; /* 0xff8000000300780b */
/* 0x000fda0006782400 */
/*05a0*/ @!P4 FADD R15, -R4, R3 ; /* 0x00000003040fc221 */
/* 0x020fca0000000100 */
/*05b0*/ FSETP.GT.OR P4, PT, |R15|, c[0x0][0x17c], P4 ; /* 0x00005f000f007a0b */
/* 0x000fe20002784600 */
/*05c0*/ IMAD.U32 R15, RZ, RZ, UR4 ; /* 0x00000004ff0f7e24 */
/* 0x000fd8000f8e00ff */
/*05d0*/ @!P4 IMAD.MOV R16, RZ, RZ, R11 ; /* 0x000000ffff10c224 */
/* 0x000fc800078e020b */
/*05e0*/ IMAD.MOV.U32 R11, RZ, RZ, R16 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0010 */
/*05f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0600*/ ISETP.GE.U32.AND P4, PT, R10, 0x3, PT ; /* 0x000000030a00780c */
/* 0x000fda0003f86070 */
/*0610*/ @!P4 BRA 0xa70 ; /* 0x000004500000c947 */
/* 0x000fea0003800000 */
/*0620*/ BSSY B0, 0xa70 ; /* 0x0000044000007945 */
/* 0x000fe40003800000 */
/*0630*/ IMAD.IADD R17, R6, 0x1, R15 ; /* 0x0000000106117824 */
/* 0x000fe200078e020f */
/*0640*/ BSSY B1, 0x7a0 ; /* 0x0000015000017945 */
/* 0x000fe20003800000 */
/*0650*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc600078e00ff */
/*0660*/ ISETP.GE.AND P4, PT, R17.reuse, RZ, PT ; /* 0x000000ff1100720c */
/* 0x040fe40003f86270 */
/*0670*/ IADD3 R2, R17.reuse, 0x1, RZ ; /* 0x0000000111027810 */
/* 0x040fe40007ffe0ff */
/*0680*/ ISETP.GE.OR P4, PT, R17.reuse, c[0x0][0x174], !P4 ; /* 0x00005d0011007a0c */
/* 0x040fe40006786670 */
/*0690*/ ISETP.GE.AND P5, PT, R2.reuse, RZ, PT ; /* 0x000000ff0200720c */
/* 0x040fe40003fa6270 */
/*06a0*/ PLOP3.LUT P4, PT, P4, P0, PT, 0xa2, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40002781472 */
/*06b0*/ ISETP.GE.OR P5, PT, R2, c[0x0][0x174], !P5 ; /* 0x00005d0002007a0c */
/* 0x000fe20006fa6670 */
/*06c0*/ IMAD R2, R14, c[0x0][0x174], R17 ; /* 0x00005d000e027a24 */
/* 0x000fe200078e0211 */
/*06d0*/ IADD3 R17, R17, 0x2, RZ ; /* 0x0000000211117810 */
/* 0x000fc40007ffe0ff */
/*06e0*/ PLOP3.LUT P5, PT, P5, P0, PT, 0xa2, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20002fa1472 */
/*06f0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0203 */
/*0700*/ @P4 BRA 0x790 ; /* 0x0000008000004947 */
/* 0x000fea0003800000 */
/*0710*/ LDG.E R19, [R2.64] ; /* 0x0000000802137981 */
/* 0x000ea4000c1e1900 */
/*0720*/ FSETP.NEU.AND P4, PT, R19, RZ, PT ; /* 0x000000ff1300720b */
/* 0x004fc80003f8d000 */
/*0730*/ FSETP.EQ.OR P4, PT, R19, -INF , !P4 ; /* 0xff8000001300780b */
/* 0x000fda0006782400 */
/*0740*/ @!P4 FADD R16, -R4, R19 ; /* 0x000000130410c221 */
/* 0x020fca0000000100 */
/*0750*/ FSETP.GT.OR P4, PT, |R16|, c[0x0][0x17c], P4 ; /* 0x00005f0010007a0b */
/* 0x000fe40002784600 */
/*0760*/ IADD3 R16, R11, 0x1, RZ ; /* 0x000000010b107810 */
/* 0x000fd60007ffe0ff */
/*0770*/ @!P4 IMAD.MOV R16, RZ, RZ, R11 ; /* 0x000000ffff10c224 */
/* 0x000fc800078e020b */
/*0780*/ IMAD.MOV.U32 R11, RZ, RZ, R16 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0010 */
/*0790*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*07a0*/ IADD3 R21, R15, 0x3, RZ ; /* 0x000000030f157810 */
/* 0x000fe20007ffe0ff */
/*07b0*/ BSSY B1, 0x880 ; /* 0x000000c000017945 */
/* 0x000fe20003800000 */
/*07c0*/ ISETP.GE.AND P4, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fc60003f86270 */
/*07d0*/ IMAD.IADD R18, R6, 0x1, R21 ; /* 0x0000000106127824 */
/* 0x000fe200078e0215 */
/*07e0*/ @P5 BRA 0x870 ; /* 0x0000008000005947 */
/* 0x000fea0003800000 */
/*07f0*/ LDG.E R19, [R2.64+0x4] ; /* 0x0000040802137981 */
/* 0x000ea4000c1e1900 */
/*0800*/ FSETP.NEU.AND P5, PT, R19, RZ, PT ; /* 0x000000ff1300720b */
/* 0x004fc80003fad000 */
/*0810*/ FSETP.EQ.OR P5, PT, R19, -INF , !P5 ; /* 0xff8000001300780b */
/* 0x000fda0006fa2400 */
/*0820*/ @!P5 FADD R16, -R4, R19 ; /* 0x000000130410d221 */
/* 0x020fca0000000100 */
/*0830*/ FSETP.GT.OR P5, PT, |R16|, c[0x0][0x17c], P5 ; /* 0x00005f0010007a0b */
/* 0x000fe40002fa4600 */
/*0840*/ IADD3 R16, R11, 0x1, RZ ; /* 0x000000010b107810 */
/* 0x000fd60007ffe0ff */
/*0850*/ @!P5 IMAD.MOV R16, RZ, RZ, R11 ; /* 0x000000ffff10d224 */
/* 0x000fc800078e020b */
/*0860*/ IMAD.MOV.U32 R11, RZ, RZ, R16 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0010 */
/*0870*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0880*/ ISETP.GE.OR P4, PT, R17, c[0x0][0x174], !P4 ; /* 0x00005d0011007a0c */
/* 0x000fe20006786670 */
/*0890*/ BSSY B1, 0x980 ; /* 0x000000e000017945 */
/* 0x000fe20003800000 */
/*08a0*/ ISETP.GE.AND P5, PT, R18.reuse, RZ, PT ; /* 0x000000ff1200720c */
/* 0x040fe40003fa6270 */
/*08b0*/ PLOP3.LUT P4, PT, P4, P0, PT, 0xa2, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40002781472 */
/*08c0*/ ISETP.GE.OR P5, PT, R18, c[0x0][0x174], !P5 ; /* 0x00005d0012007a0c */
/* 0x000fc80006fa6670 */
/*08d0*/ PLOP3.LUT P5, PT, P5, P0, PT, 0xa2, 0x0 ; /* 0x000000000000781c */
/* 0x000fce0002fa1472 */
/*08e0*/ @P4 BRA 0x970 ; /* 0x0000008000004947 */
/* 0x000fea0003800000 */
/*08f0*/ LDG.E R17, [R2.64+0x8] ; /* 0x0000080802117981 */
/* 0x000ea4000c1e1900 */
/*0900*/ FSETP.NEU.AND P4, PT, R17, RZ, PT ; /* 0x000000ff1100720b */
/* 0x004fc80003f8d000 */
/*0910*/ FSETP.EQ.OR P4, PT, R17, -INF , !P4 ; /* 0xff8000001100780b */
/* 0x000fda0006782400 */
/*0920*/ @!P4 FADD R16, -R4, R17 ; /* 0x000000110410c221 */
/* 0x020fca0000000100 */
/*0930*/ FSETP.GT.OR P4, PT, |R16|, c[0x0][0x17c], P4 ; /* 0x00005f0010007a0b */
/* 0x000fe40002784600 */
/*0940*/ IADD3 R16, R11, 0x1, RZ ; /* 0x000000010b107810 */
/* 0x000fd60007ffe0ff */
/*0950*/ @!P4 IMAD.MOV R16, RZ, RZ, R11 ; /* 0x000000ffff10c224 */
/* 0x000fc800078e020b */
/*0960*/ IMAD.MOV.U32 R11, RZ, RZ, R16 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0010 */
/*0970*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0980*/ BSSY B1, 0xa30 ; /* 0x000000a000017945 */
/* 0x000fe20003800000 */
/*0990*/ @P5 BRA 0xa20 ; /* 0x0000008000005947 */
/* 0x000fea0003800000 */
/*09a0*/ LDG.E R3, [R2.64+0xc] ; /* 0x00000c0802037981 */
/* 0x000ea4000c1e1900 */
/*09b0*/ FSETP.NEU.AND P4, PT, R3, RZ, PT ; /* 0x000000ff0300720b */
/* 0x004fc80003f8d000 */
/*09c0*/ FSETP.EQ.OR P4, PT, R3, -INF , !P4 ; /* 0xff8000000300780b */
/* 0x000fda0006782400 */
/*09d0*/ @!P4 FADD R16, -R4, R3 ; /* 0x000000030410c221 */
/* 0x020fca0000000100 */
/*09e0*/ FSETP.GT.OR P4, PT, |R16|, c[0x0][0x17c], P4 ; /* 0x00005f0010007a0b */
/* 0x000fe40002784600 */
/*09f0*/ IADD3 R16, R11, 0x1, RZ ; /* 0x000000010b107810 */
/* 0x000fd60007ffe0ff */
/*0a00*/ @!P4 IMAD.MOV R16, RZ, RZ, R11 ; /* 0x000000ffff10c224 */
/* 0x000fc800078e020b */
/*0a10*/ IMAD.MOV.U32 R11, RZ, RZ, R16 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0010 */
/*0a20*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0a30*/ ISETP.GE.AND P4, PT, R21, c[0x0][0x170], PT ; /* 0x00005c0015007a0c */
/* 0x000fe40003f86270 */
/*0a40*/ IADD3 R15, R15, 0x4, RZ ; /* 0x000000040f0f7810 */
/* 0x000fd60007ffe0ff */
/*0a50*/ @!P4 BRA 0x630 ; /* 0xfffffbd00000c947 */
/* 0x000fea000383ffff */
/*0a60*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0a70*/ @!P6 BRA 0x290 ; /* 0xfffff8100000e947 */
/* 0x000fea000383ffff */
/*0a80*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x001fe20000000800 */
/*0a90*/ I2F.U32 R9, R11 ; /* 0x0000000b00097306 */
/* 0x000fe20000201000 */
/*0aa0*/ ULEA UR4, UR4, 0x1, 0x1 ; /* 0x0000000104047891 */
/* 0x000fe2000f8e083f */
/*0ab0*/ BSSY B0, 0xba0 ; /* 0x000000e000007945 */
/* 0x000fe60003800000 */
/*0ac0*/ UIMAD UR4, UR4, UR4, URZ ; /* 0x00000004040472a4 */
/* 0x000fd2000f8e023f */
/*0ad0*/ I2F.U32 R3, UR4 ; /* 0x0000000400037d06 */
/* 0x000e300008201000 */
/*0ae0*/ MUFU.RCP R2, R3 ; /* 0x0000000300027308 */
/* 0x001e300000001000 */
/*0af0*/ FCHK P0, R9, R3 ; /* 0x0000000309007302 */
/* 0x000e620000000000 */
/*0b00*/ FFMA R7, -R3, R2, 1 ; /* 0x3f80000003077423 */
/* 0x001fc80000000102 */
/*0b10*/ FFMA R7, R2, R7, R2 ; /* 0x0000000702077223 */
/* 0x000fc80000000002 */
/*0b20*/ FFMA R2, R9, R7, RZ ; /* 0x0000000709027223 */
/* 0x000fc800000000ff */
/*0b30*/ FFMA R6, -R3, R2, R9 ; /* 0x0000000203067223 */
/* 0x000fc80000000109 */
/*0b40*/ FFMA R2, R7, R6, R2 ; /* 0x0000000607027223 */
/* 0x000fe20000000002 */
/*0b50*/ @!P0 BRA 0xb90 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*0b60*/ MOV R2, 0xb80 ; /* 0x00000b8000027802 */
/* 0x000fe40000000f00 */
/*0b70*/ CALL.REL.NOINC 0xc20 ; /* 0x000000a000007944 */
/* 0x020fea0003c00000 */
/*0b80*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0006 */
/*0b90*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0ba0*/ FSETP.GE.AND P0, PT, R2, c[0x0][0x180], PT ; /* 0x0000600002007a0b */
/* 0x000fe40003f06000 */
/*0bb0*/ LEA R2, P1, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000027a11 */
/* 0x000fc800078210ff */
/*0bc0*/ LEA.HI.X R3, R0, c[0x0][0x164], R5, 0x2, P1 ; /* 0x0000590000037a11 */
/* 0x000fce00008f1405 */
/*0bd0*/ @P0 IMAD.MOV.U32 R5, RZ, RZ, -0x800000 ; /* 0xff800000ff050424 */
/* 0x000fca00078e00ff */
/*0be0*/ @P0 STG.E [R2.64], R5 ; /* 0x0000000502000986 */
/* 0x0001e2000c101908 */
/*0bf0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0c00*/ STG.E [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x020fe2000c101908 */
/*0c10*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c20*/ SHF.R.U32.HI R7, RZ, 0x17, R3 ; /* 0x00000017ff077819 */
/* 0x000fe20000011603 */
/*0c30*/ BSSY B1, 0x1280 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0c40*/ SHF.R.U32.HI R6, RZ, 0x17, R9 ; /* 0x00000017ff067819 */
/* 0x000fe20000011609 */
/*0c50*/ IMAD.MOV.U32 R10, RZ, RZ, R3 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0003 */
/*0c60*/ LOP3.LUT R8, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07087812 */
/* 0x000fe400078ec0ff */
/*0c70*/ LOP3.LUT R11, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff060b7812 */
/* 0x000fe400078ec0ff */
/*0c80*/ IADD3 R12, R8, -0x1, RZ ; /* 0xffffffff080c7810 */
/* 0x000fc40007ffe0ff */
/*0c90*/ IADD3 R13, R11, -0x1, RZ ; /* 0xffffffff0b0d7810 */
/* 0x000fe40007ffe0ff */
/*0ca0*/ ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ; /* 0x000000fd0c00780c */
/* 0x000fc80003f04070 */
/*0cb0*/ ISETP.GT.U32.OR P0, PT, R13, 0xfd, P0 ; /* 0x000000fd0d00780c */
/* 0x000fda0000704470 */
/*0cc0*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff068224 */
/* 0x000fe200078e00ff */
/*0cd0*/ @!P0 BRA 0xe60 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0ce0*/ FSETP.GTU.FTZ.AND P0, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fe20003f1c200 */
/*0cf0*/ IMAD.MOV.U32 R7, RZ, RZ, R9 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0009 */
/*0d00*/ FSETP.GTU.FTZ.AND P1, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fc80003f3c200 */
/*0d10*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0d20*/ @P0 BRA 0x1260 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0d30*/ LOP3.LUT P0, RZ, R10, 0x7fffffff, R9, 0xc8, !PT ; /* 0x7fffffff0aff7812 */
/* 0x000fda000780c809 */
/*0d40*/ @!P0 BRA 0x1240 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0d50*/ FSETP.NEU.FTZ.AND P1, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fe40003f3d200 */
/*0d60*/ FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fe40003f1d200 */
/*0d70*/ FSETP.NEU.FTZ.AND P2, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fd60003f5d200 */
/*0d80*/ @!P0 BRA !P1, 0x1240 ; /* 0x000004b000008947 */
/* 0x000fea0004800000 */
/*0d90*/ LOP3.LUT P1, RZ, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fc8000782c0ff */
/*0da0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0db0*/ @P0 BRA 0x1220 ; /* 0x0000046000000947 */
/* 0x000fea0003800000 */
/*0dc0*/ LOP3.LUT P0, RZ, R10, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0aff7812 */
/* 0x000fc8000780c0ff */
/*0dd0*/ PLOP3.LUT P0, PT, P2, P0, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0001700572 */
/*0de0*/ @P0 BRA 0x11f0 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0df0*/ ISETP.GE.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe40003f06270 */
/*0e00*/ ISETP.GE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fd60003f26270 */
/*0e10*/ @P0 IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff060224 */
/* 0x000fe400078e00ff */
/*0e20*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, -0x40 ; /* 0xffffffc0ff068424 */
/* 0x000fe400078e00ff */
/*0e30*/ @!P0 FFMA R9, R7, 1.84467440737095516160e+19, RZ ; /* 0x5f80000007098823 */
/* 0x000fe400000000ff */
/*0e40*/ @!P1 FFMA R10, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f800000030a9823 */
/* 0x000fe200000000ff */
/*0e50*/ @!P1 IADD3 R6, R6, 0x40, RZ ; /* 0x0000004006069810 */
/* 0x000fe40007ffe0ff */
/*0e60*/ LEA R3, R8, 0xc0800000, 0x17 ; /* 0xc080000008037811 */
/* 0x000fe200078eb8ff */
/*0e70*/ BSSY B2, 0x11e0 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*0e80*/ IADD3 R7, R11, -0x7f, RZ ; /* 0xffffff810b077810 */
/* 0x000fc60007ffe0ff */
/*0e90*/ IMAD.IADD R10, R10, 0x1, -R3 ; /* 0x000000010a0a7824 */
/* 0x000fe400078e0a03 */
/*0ea0*/ IMAD R9, R7, -0x800000, R9 ; /* 0xff80000007097824 */
/* 0x000fe400078e0209 */
/*0eb0*/ MUFU.RCP R3, R10 ; /* 0x0000000a00037308 */
/* 0x000e220000001000 */
/*0ec0*/ FADD.FTZ R12, -R10, -RZ ; /* 0x800000ff0a0c7221 */
/* 0x000fc80000010100 */
/*0ed0*/ FFMA R14, R3, R12, 1 ; /* 0x3f800000030e7423 */
/* 0x001fc8000000000c */
/*0ee0*/ FFMA R16, R3, R14, R3 ; /* 0x0000000e03107223 */
/* 0x000fc80000000003 */
/*0ef0*/ FFMA R3, R9, R16, RZ ; /* 0x0000001009037223 */
/* 0x000fc800000000ff */
/*0f00*/ FFMA R14, R12, R3, R9 ; /* 0x000000030c0e7223 */
/* 0x000fc80000000009 */
/*0f10*/ FFMA R11, R16, R14, R3 ; /* 0x0000000e100b7223 */
/* 0x000fc80000000003 */
/*0f20*/ FFMA R12, R12, R11, R9 ; /* 0x0000000b0c0c7223 */
/* 0x000fe20000000009 */
/*0f30*/ IADD3 R9, R7, 0x7f, -R8 ; /* 0x0000007f07097810 */
/* 0x000fc60007ffe808 */
/*0f40*/ FFMA R3, R16, R12, R11 ; /* 0x0000000c10037223 */
/* 0x000fe4000000000b */
/*0f50*/ IMAD.IADD R6, R9, 0x1, R6 ; /* 0x0000000109067824 */
/* 0x000fc600078e0206 */
/*0f60*/ SHF.R.U32.HI R7, RZ, 0x17, R3 ; /* 0x00000017ff077819 */
/* 0x000fc80000011603 */
/*0f70*/ LOP3.LUT R7, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07077812 */
/* 0x000fca00078ec0ff */
/*0f80*/ IMAD.IADD R10, R7, 0x1, R6 ; /* 0x00000001070a7824 */
/* 0x000fca00078e0206 */
/*0f90*/ IADD3 R7, R10, -0x1, RZ ; /* 0xffffffff0a077810 */
/* 0x000fc80007ffe0ff */
/*0fa0*/ ISETP.GE.U32.AND P0, PT, R7, 0xfe, PT ; /* 0x000000fe0700780c */
/* 0x000fda0003f06070 */
/*0fb0*/ @!P0 BRA 0x11c0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0fc0*/ ISETP.GT.AND P0, PT, R10, 0xfe, PT ; /* 0x000000fe0a00780c */
/* 0x000fda0003f04270 */
/*0fd0*/ @P0 BRA 0x1190 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0fe0*/ ISETP.GE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fda0003f06270 */
/*0ff0*/ @P0 BRA 0x11d0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*1000*/ ISETP.GE.AND P0, PT, R10, -0x18, PT ; /* 0xffffffe80a00780c */
/* 0x000fe40003f06270 */
/*1010*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*1020*/ @!P0 BRA 0x11d0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*1030*/ FFMA.RZ R6, R16, R12.reuse, R11.reuse ; /* 0x0000000c10067223 */
/* 0x180fe2000000c00b */
/*1040*/ IADD3 R9, R10, 0x20, RZ ; /* 0x000000200a097810 */
/* 0x000fe20007ffe0ff */
/*1050*/ FFMA.RM R7, R16, R12.reuse, R11.reuse ; /* 0x0000000c10077223 */
/* 0x180fe2000000400b */
/*1060*/ ISETP.NE.AND P2, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f45270 */
/*1070*/ LOP3.LUT R8, R6, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff06087812 */
/* 0x000fe200078ec0ff */
/*1080*/ FFMA.RP R6, R16, R12, R11 ; /* 0x0000000c10067223 */
/* 0x000fe2000000800b */
/*1090*/ ISETP.NE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f25270 */
/*10a0*/ IMAD.MOV R10, RZ, RZ, -R10 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0a0a */
/*10b0*/ LOP3.LUT R8, R8, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000008087812 */
/* 0x000fe400078efcff */
/*10c0*/ FSETP.NEU.FTZ.AND P0, PT, R6, R7, PT ; /* 0x000000070600720b */
/* 0x000fc40003f1d000 */
/*10d0*/ SHF.L.U32 R9, R8, R9, RZ ; /* 0x0000000908097219 */
/* 0x000fe400000006ff */
/*10e0*/ SEL R7, R10, RZ, P2 ; /* 0x000000ff0a077207 */
/* 0x000fe40001000000 */
/*10f0*/ ISETP.NE.AND P1, PT, R9, RZ, P1 ; /* 0x000000ff0900720c */
/* 0x000fe40000f25270 */
/*1100*/ SHF.R.U32.HI R7, RZ, R7, R8 ; /* 0x00000007ff077219 */
/* 0x000fe40000011608 */
/*1110*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*1120*/ SHF.R.U32.HI R9, RZ, 0x1, R7 ; /* 0x00000001ff097819 */
/* 0x000fc40000011607 */
/*1130*/ SEL R6, RZ, 0x1, !P0 ; /* 0x00000001ff067807 */
/* 0x000fc80004000000 */
/*1140*/ LOP3.LUT R6, R6, 0x1, R9, 0xf8, !PT ; /* 0x0000000106067812 */
/* 0x000fc800078ef809 */
/*1150*/ LOP3.LUT R6, R6, R7, RZ, 0xc0, !PT ; /* 0x0000000706067212 */
/* 0x000fca00078ec0ff */
/*1160*/ IMAD.IADD R6, R9, 0x1, R6 ; /* 0x0000000109067824 */
/* 0x000fca00078e0206 */
/*1170*/ LOP3.LUT R3, R6, R3, RZ, 0xfc, !PT ; /* 0x0000000306037212 */
/* 0x000fe200078efcff */
/*1180*/ BRA 0x11d0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*1190*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*11a0*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*11b0*/ BRA 0x11d0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*11c0*/ IMAD R3, R6, 0x800000, R3 ; /* 0x0080000006037824 */
/* 0x000fe400078e0203 */
/*11d0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*11e0*/ BRA 0x1270 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*11f0*/ LOP3.LUT R3, R10, 0x80000000, R9, 0x48, !PT ; /* 0x800000000a037812 */
/* 0x000fc800078e4809 */
/*1200*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*1210*/ BRA 0x1270 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*1220*/ LOP3.LUT R3, R10, 0x80000000, R9, 0x48, !PT ; /* 0x800000000a037812 */
/* 0x000fe200078e4809 */
/*1230*/ BRA 0x1270 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*1240*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*1250*/ BRA 0x1270 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*1260*/ FADD.FTZ R3, R7, R3 ; /* 0x0000000307037221 */
/* 0x000fe40000010000 */
/*1270*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*1280*/ IMAD.MOV.U32 R6, RZ, RZ, R3 ; /* 0x000000ffff067224 */
/* 0x001fe400078e0003 */
/*1290*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*12a0*/ RET.REL.NODEC R2 0x0 ; /* 0xffffed5002007950 */
/* 0x000fea0003c3ffff */
/*12b0*/ BRA 0x12b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*12c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define T_PER_BLOCK 16
#define MINF __int_as_float(0xff800000)
__global__ void erodeDepthMapDevice(float* d_output, float* d_input, int structureSize, int width, int height, float dThresh, float fracReq)
{
const int x = blockIdx.x*blockDim.x + threadIdx.x;
const int y = blockIdx.y*blockDim.y + threadIdx.y;
if (x >= 0 && x < width && y >= 0 && y < height)
{
unsigned int count = 0;
float oldDepth = d_input[y*width + x];
for (int i = -structureSize; i <= structureSize; i++)
{
for (int j = -structureSize; j <= structureSize; j++)
{
if (x + j >= 0 && x + j < width && y + i >= 0 && y + i < height)
{
float depth = d_input[(y + i)*width + (x + j)];
if (depth == MINF || depth == 0.0f || fabs(depth - oldDepth) > dThresh)
{
count++;
//d_output[y*width+x] = MINF;
//return;
}
}
}
}
unsigned int sum = (2 * structureSize + 1)*(2 * structureSize + 1);
if ((float)count / (float)sum >= fracReq) {
d_output[y*width + x] = MINF;
}
else {
d_output[y*width + x] = d_input[y*width + x];
}
}
} | .file "tmpxft_0000cea4_00000000-6_erodeDepthMapDevice.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z19erodeDepthMapDevicePfS_iiiffPfS_iiiff
.type _Z46__device_stub__Z19erodeDepthMapDevicePfS_iiiffPfS_iiiff, @function
_Z46__device_stub__Z19erodeDepthMapDevicePfS_iiiffPfS_iiiff:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movl %r8d, 20(%rsp)
movss %xmm0, 16(%rsp)
movss %xmm1, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z19erodeDepthMapDevicePfS_iiiff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z19erodeDepthMapDevicePfS_iiiffPfS_iiiff, .-_Z46__device_stub__Z19erodeDepthMapDevicePfS_iiiffPfS_iiiff
.globl _Z19erodeDepthMapDevicePfS_iiiff
.type _Z19erodeDepthMapDevicePfS_iiiff, @function
_Z19erodeDepthMapDevicePfS_iiiff:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z19erodeDepthMapDevicePfS_iiiffPfS_iiiff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19erodeDepthMapDevicePfS_iiiff, .-_Z19erodeDepthMapDevicePfS_iiiff
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19erodeDepthMapDevicePfS_iiiff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19erodeDepthMapDevicePfS_iiiff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define T_PER_BLOCK 16
#define MINF __int_as_float(0xff800000)
__global__ void erodeDepthMapDevice(float* d_output, float* d_input, int structureSize, int width, int height, float dThresh, float fracReq)
{
const int x = blockIdx.x*blockDim.x + threadIdx.x;
const int y = blockIdx.y*blockDim.y + threadIdx.y;
if (x >= 0 && x < width && y >= 0 && y < height)
{
unsigned int count = 0;
float oldDepth = d_input[y*width + x];
for (int i = -structureSize; i <= structureSize; i++)
{
for (int j = -structureSize; j <= structureSize; j++)
{
if (x + j >= 0 && x + j < width && y + i >= 0 && y + i < height)
{
float depth = d_input[(y + i)*width + (x + j)];
if (depth == MINF || depth == 0.0f || fabs(depth - oldDepth) > dThresh)
{
count++;
//d_output[y*width+x] = MINF;
//return;
}
}
}
}
unsigned int sum = (2 * structureSize + 1)*(2 * structureSize + 1);
if ((float)count / (float)sum >= fracReq) {
d_output[y*width + x] = MINF;
}
else {
d_output[y*width + x] = d_input[y*width + x];
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define T_PER_BLOCK 16
#define MINF __int_as_float(0xff800000)
__global__ void erodeDepthMapDevice(float* d_output, float* d_input, int structureSize, int width, int height, float dThresh, float fracReq)
{
const int x = blockIdx.x*blockDim.x + threadIdx.x;
const int y = blockIdx.y*blockDim.y + threadIdx.y;
if (x >= 0 && x < width && y >= 0 && y < height)
{
unsigned int count = 0;
float oldDepth = d_input[y*width + x];
for (int i = -structureSize; i <= structureSize; i++)
{
for (int j = -structureSize; j <= structureSize; j++)
{
if (x + j >= 0 && x + j < width && y + i >= 0 && y + i < height)
{
float depth = d_input[(y + i)*width + (x + j)];
if (depth == MINF || depth == 0.0f || fabs(depth - oldDepth) > dThresh)
{
count++;
//d_output[y*width+x] = MINF;
//return;
}
}
}
}
unsigned int sum = (2 * structureSize + 1)*(2 * structureSize + 1);
if ((float)count / (float)sum >= fracReq) {
d_output[y*width + x] = MINF;
}
else {
d_output[y*width + x] = d_input[y*width + x];
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define T_PER_BLOCK 16
#define MINF __int_as_float(0xff800000)
__global__ void erodeDepthMapDevice(float* d_output, float* d_input, int structureSize, int width, int height, float dThresh, float fracReq)
{
const int x = blockIdx.x*blockDim.x + threadIdx.x;
const int y = blockIdx.y*blockDim.y + threadIdx.y;
if (x >= 0 && x < width && y >= 0 && y < height)
{
unsigned int count = 0;
float oldDepth = d_input[y*width + x];
for (int i = -structureSize; i <= structureSize; i++)
{
for (int j = -structureSize; j <= structureSize; j++)
{
if (x + j >= 0 && x + j < width && y + i >= 0 && y + i < height)
{
float depth = d_input[(y + i)*width + (x + j)];
if (depth == MINF || depth == 0.0f || fabs(depth - oldDepth) > dThresh)
{
count++;
//d_output[y*width+x] = MINF;
//return;
}
}
}
}
unsigned int sum = (2 * structureSize + 1)*(2 * structureSize + 1);
if ((float)count / (float)sum >= fracReq) {
d_output[y*width + x] = MINF;
}
else {
d_output[y*width + x] = d_input[y*width + x];
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19erodeDepthMapDevicePfS_iiiff
.globl _Z19erodeDepthMapDevicePfS_iiiff
.p2align 8
.type _Z19erodeDepthMapDevicePfS_iiiff,@function
_Z19erodeDepthMapDevicePfS_iiiff:
s_load_b32 s4, s[0:1], 0x34
s_add_u32 s2, s0, 40
v_and_b32_e32 v1, 0x3ff, v0
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mul_i32 s14, s14, s4
s_mov_b32 s4, exec_lo
v_add_nc_u32_e32 v2, s14, v1
v_cmpx_lt_i32_e32 -1, v2
s_cbranch_execz .LBB0_12
s_load_b32 s2, s[2:3], 0xc
s_load_b64 s[4:5], s[0:1], 0x14
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s2, 16
v_cmp_gt_i32_e32 vcc_lo, s4, v2
s_mul_i32 s15, s15, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, s15, v0
v_cmp_gt_i32_e64 s2, s5, v4
v_cmp_lt_i32_e64 s3, -1, v4
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_12
s_clause 0x1
s_load_b64 s[6:7], s[0:1], 0x8
s_load_b32 s3, s[0:1], 0x10
v_mad_u64_u32 v[0:1], null, v4, s4, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[5:6], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
s_cmp_lt_i32 s3, 0
global_load_b32 v3, v[5:6], off
v_mov_b32_e32 v5, 0
s_cbranch_scc1 .LBB0_11
s_load_b32 s8, s[0:1], 0x1c
v_subrev_nc_u32_e32 v5, s3, v4
v_subrev_nc_u32_e32 v6, s3, v2
v_mov_b32_e32 v2, 0
s_lshl_b32 s2, s3, 1
s_sub_i32 s10, 0, s3
v_mul_lo_u32 v5, s4, v5
s_or_b32 s9, s2, 1
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_4:
v_add_nc_u32_e32 v7, s10, v4
s_mov_b32 s12, s9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, 0, v7
v_cmp_le_i32_e64 s2, s5, v7
v_mov_b32_e32 v7, v6
s_or_b32 s11, vcc_lo, s2
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v7, 1, v7
s_add_i32 s12, s12, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s12, 0
s_cbranch_scc1 .LBB0_8
.LBB0_6:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, 0, v7
v_cmp_le_i32_e64 s2, s4, v7
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, s2, s11
s_xor_b32 s13, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s13
s_cbranch_execz .LBB0_5
v_add_nc_u32_e32 v8, v5, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[8:9], 2, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, s6, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
global_load_b32 v8, v[8:9], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v9, v8, v3
v_cmp_class_f32_e64 s13, v8, 0x64
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_f32_e64 s14, |v9|, s8
s_or_b32 s13, s13, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v8, 0, 1, s13
v_add_nc_u32_e32 v2, v2, v8
s_branch .LBB0_5
.p2align 6
.LBB0_8:
v_add_nc_u32_e32 v5, s4, v5
s_add_i32 s2, s10, 1
s_cmp_eq_u32 s10, s3
s_cbranch_scc1 .LBB0_10
s_mov_b32 s10, s2
s_branch .LBB0_4
.LBB0_10:
s_set_inst_prefetch_distance 0x2
v_cvt_f32_u32_e32 v5, v2
.LBB0_11:
s_lshl_b32 s2, s3, 1
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_or_b32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s2, s2, s2
v_cvt_f32_u32_e32 v2, s2
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v4, null, v2, v2, v5
v_div_scale_f32 v8, vcc_lo, v5, v2, v5
v_rcp_f32_e32 v6, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v7, -v4, v6, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v7, v6
v_mul_f32_e32 v7, v8, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v9, -v4, v7, v8
v_fmac_f32_e32 v7, v9, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v7, v8
v_div_fmas_f32 v4, v4, v6, v7
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v2, v4, v2, v5
v_cmp_nle_f32_e32 vcc_lo, s0, v2
s_waitcnt vmcnt(0)
v_cndmask_b32_e32 v2, 0xff800000, v3, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19erodeDepthMapDevicePfS_iiiff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19erodeDepthMapDevicePfS_iiiff, .Lfunc_end0-_Z19erodeDepthMapDevicePfS_iiiff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19erodeDepthMapDevicePfS_iiiff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19erodeDepthMapDevicePfS_iiiff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define T_PER_BLOCK 16
#define MINF __int_as_float(0xff800000)
__global__ void erodeDepthMapDevice(float* d_output, float* d_input, int structureSize, int width, int height, float dThresh, float fracReq)
{
const int x = blockIdx.x*blockDim.x + threadIdx.x;
const int y = blockIdx.y*blockDim.y + threadIdx.y;
if (x >= 0 && x < width && y >= 0 && y < height)
{
unsigned int count = 0;
float oldDepth = d_input[y*width + x];
for (int i = -structureSize; i <= structureSize; i++)
{
for (int j = -structureSize; j <= structureSize; j++)
{
if (x + j >= 0 && x + j < width && y + i >= 0 && y + i < height)
{
float depth = d_input[(y + i)*width + (x + j)];
if (depth == MINF || depth == 0.0f || fabs(depth - oldDepth) > dThresh)
{
count++;
//d_output[y*width+x] = MINF;
//return;
}
}
}
}
unsigned int sum = (2 * structureSize + 1)*(2 * structureSize + 1);
if ((float)count / (float)sum >= fracReq) {
d_output[y*width + x] = MINF;
}
else {
d_output[y*width + x] = d_input[y*width + x];
}
}
} | .text
.file "erodeDepthMapDevice.hip"
.globl _Z34__device_stub__erodeDepthMapDevicePfS_iiiff # -- Begin function _Z34__device_stub__erodeDepthMapDevicePfS_iiiff
.p2align 4, 0x90
.type _Z34__device_stub__erodeDepthMapDevicePfS_iiiff,@function
_Z34__device_stub__erodeDepthMapDevicePfS_iiiff: # @_Z34__device_stub__erodeDepthMapDevicePfS_iiiff
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movl %r8d, 20(%rsp)
movss %xmm0, 16(%rsp)
movss %xmm1, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19erodeDepthMapDevicePfS_iiiff, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z34__device_stub__erodeDepthMapDevicePfS_iiiff, .Lfunc_end0-_Z34__device_stub__erodeDepthMapDevicePfS_iiiff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19erodeDepthMapDevicePfS_iiiff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19erodeDepthMapDevicePfS_iiiff,@object # @_Z19erodeDepthMapDevicePfS_iiiff
.section .rodata,"a",@progbits
.globl _Z19erodeDepthMapDevicePfS_iiiff
.p2align 3, 0x0
_Z19erodeDepthMapDevicePfS_iiiff:
.quad _Z34__device_stub__erodeDepthMapDevicePfS_iiiff
.size _Z19erodeDepthMapDevicePfS_iiiff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19erodeDepthMapDevicePfS_iiiff"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__erodeDepthMapDevicePfS_iiiff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19erodeDepthMapDevicePfS_iiiff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0000cea4_00000000-6_erodeDepthMapDevice.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z19erodeDepthMapDevicePfS_iiiffPfS_iiiff
.type _Z46__device_stub__Z19erodeDepthMapDevicePfS_iiiffPfS_iiiff, @function
_Z46__device_stub__Z19erodeDepthMapDevicePfS_iiiffPfS_iiiff:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movl %r8d, 20(%rsp)
movss %xmm0, 16(%rsp)
movss %xmm1, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z19erodeDepthMapDevicePfS_iiiff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z19erodeDepthMapDevicePfS_iiiffPfS_iiiff, .-_Z46__device_stub__Z19erodeDepthMapDevicePfS_iiiffPfS_iiiff
.globl _Z19erodeDepthMapDevicePfS_iiiff
.type _Z19erodeDepthMapDevicePfS_iiiff, @function
_Z19erodeDepthMapDevicePfS_iiiff:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z19erodeDepthMapDevicePfS_iiiffPfS_iiiff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19erodeDepthMapDevicePfS_iiiff, .-_Z19erodeDepthMapDevicePfS_iiiff
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19erodeDepthMapDevicePfS_iiiff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19erodeDepthMapDevicePfS_iiiff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "erodeDepthMapDevice.hip"
.globl _Z34__device_stub__erodeDepthMapDevicePfS_iiiff # -- Begin function _Z34__device_stub__erodeDepthMapDevicePfS_iiiff
.p2align 4, 0x90
.type _Z34__device_stub__erodeDepthMapDevicePfS_iiiff,@function
_Z34__device_stub__erodeDepthMapDevicePfS_iiiff: # @_Z34__device_stub__erodeDepthMapDevicePfS_iiiff
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movl %r8d, 20(%rsp)
movss %xmm0, 16(%rsp)
movss %xmm1, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19erodeDepthMapDevicePfS_iiiff, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z34__device_stub__erodeDepthMapDevicePfS_iiiff, .Lfunc_end0-_Z34__device_stub__erodeDepthMapDevicePfS_iiiff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19erodeDepthMapDevicePfS_iiiff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19erodeDepthMapDevicePfS_iiiff,@object # @_Z19erodeDepthMapDevicePfS_iiiff
.section .rodata,"a",@progbits
.globl _Z19erodeDepthMapDevicePfS_iiiff
.p2align 3, 0x0
_Z19erodeDepthMapDevicePfS_iiiff:
.quad _Z34__device_stub__erodeDepthMapDevicePfS_iiiff
.size _Z19erodeDepthMapDevicePfS_iiiff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19erodeDepthMapDevicePfS_iiiff"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__erodeDepthMapDevicePfS_iiiff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19erodeDepthMapDevicePfS_iiiff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*__global__ void getPointEvals(float* unknowns, float* mPoints, float* outs)
{
int mpidx = i * 3;
int cidx = i * 4;
Vector3f vk((*mPoints)[mpidx], (*mPoints)[mpidx + 1], (*mPoints)[mpidx + 2]);
float alpha = (*unknowns)(cidx);
Vector3f beta((*unknowns)(cidx + 1), (*unknowns)(cidx + 2), (*unknowns)(cidx + 3));
Vector3f diff = p - vk;
Vector3f grad(derivx(diff(0), diff(1), diff(2)), derivy(diff(0), diff(1), diff(2)), derivz(diff(0), diff(1), diff(2)));
//std::cout << alpha << std::endl;
//std::cout << beta(0) << "," << beta(1) << "," << beta(2) << " " << diff(0) << "," << diff(1) << "," << diff(2) << " " << grad(0) << "," << grad(1) << "," << grad(2) << std::endl;
out += alpha * smoothfunc(diff(0), diff(1), diff(2)) - beta.dot(grad);
//std::cout << out << std::endl;
}*/ | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*__global__ void getPointEvals(float* unknowns, float* mPoints, float* outs)
{
int mpidx = i * 3;
int cidx = i * 4;
Vector3f vk((*mPoints)[mpidx], (*mPoints)[mpidx + 1], (*mPoints)[mpidx + 2]);
float alpha = (*unknowns)(cidx);
Vector3f beta((*unknowns)(cidx + 1), (*unknowns)(cidx + 2), (*unknowns)(cidx + 3));
Vector3f diff = p - vk;
Vector3f grad(derivx(diff(0), diff(1), diff(2)), derivy(diff(0), diff(1), diff(2)), derivz(diff(0), diff(1), diff(2)));
//std::cout << alpha << std::endl;
//std::cout << beta(0) << "," << beta(1) << "," << beta(2) << " " << diff(0) << "," << diff(1) << "," << diff(2) << " " << grad(0) << "," << grad(1) << "," << grad(2) << std::endl;
out += alpha * smoothfunc(diff(0), diff(1), diff(2)) - beta.dot(grad);
//std::cout << out << std::endl;
}*/ | .file "tmpxft_0017ec9a_00000000-6_HRBFGeneratorDevice.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*__global__ void getPointEvals(float* unknowns, float* mPoints, float* outs)
{
int mpidx = i * 3;
int cidx = i * 4;
Vector3f vk((*mPoints)[mpidx], (*mPoints)[mpidx + 1], (*mPoints)[mpidx + 2]);
float alpha = (*unknowns)(cidx);
Vector3f beta((*unknowns)(cidx + 1), (*unknowns)(cidx + 2), (*unknowns)(cidx + 3));
Vector3f diff = p - vk;
Vector3f grad(derivx(diff(0), diff(1), diff(2)), derivy(diff(0), diff(1), diff(2)), derivz(diff(0), diff(1), diff(2)));
//std::cout << alpha << std::endl;
//std::cout << beta(0) << "," << beta(1) << "," << beta(2) << " " << diff(0) << "," << diff(1) << "," << diff(2) << " " << grad(0) << "," << grad(1) << "," << grad(2) << std::endl;
out += alpha * smoothfunc(diff(0), diff(1), diff(2)) - beta.dot(grad);
//std::cout << out << std::endl;
}*/ | #include <hip/hip_runtime.h>
/*__global__ void getPointEvals(float* unknowns, float* mPoints, float* outs)
{
int mpidx = i * 3;
int cidx = i * 4;
Vector3f vk((*mPoints)[mpidx], (*mPoints)[mpidx + 1], (*mPoints)[mpidx + 2]);
float alpha = (*unknowns)(cidx);
Vector3f beta((*unknowns)(cidx + 1), (*unknowns)(cidx + 2), (*unknowns)(cidx + 3));
Vector3f diff = p - vk;
Vector3f grad(derivx(diff(0), diff(1), diff(2)), derivy(diff(0), diff(1), diff(2)), derivz(diff(0), diff(1), diff(2)));
//std::cout << alpha << std::endl;
//std::cout << beta(0) << "," << beta(1) << "," << beta(2) << " " << diff(0) << "," << diff(1) << "," << diff(2) << " " << grad(0) << "," << grad(1) << "," << grad(2) << std::endl;
out += alpha * smoothfunc(diff(0), diff(1), diff(2)) - beta.dot(grad);
//std::cout << out << std::endl;
}*/ |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/*__global__ void getPointEvals(float* unknowns, float* mPoints, float* outs)
{
int mpidx = i * 3;
int cidx = i * 4;
Vector3f vk((*mPoints)[mpidx], (*mPoints)[mpidx + 1], (*mPoints)[mpidx + 2]);
float alpha = (*unknowns)(cidx);
Vector3f beta((*unknowns)(cidx + 1), (*unknowns)(cidx + 2), (*unknowns)(cidx + 3));
Vector3f diff = p - vk;
Vector3f grad(derivx(diff(0), diff(1), diff(2)), derivy(diff(0), diff(1), diff(2)), derivz(diff(0), diff(1), diff(2)));
//std::cout << alpha << std::endl;
//std::cout << beta(0) << "," << beta(1) << "," << beta(2) << " " << diff(0) << "," << diff(1) << "," << diff(2) << " " << grad(0) << "," << grad(1) << "," << grad(2) << std::endl;
out += alpha * smoothfunc(diff(0), diff(1), diff(2)) - beta.dot(grad);
//std::cout << out << std::endl;
}*/ | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/*__global__ void getPointEvals(float* unknowns, float* mPoints, float* outs)
{
int mpidx = i * 3;
int cidx = i * 4;
Vector3f vk((*mPoints)[mpidx], (*mPoints)[mpidx + 1], (*mPoints)[mpidx + 2]);
float alpha = (*unknowns)(cidx);
Vector3f beta((*unknowns)(cidx + 1), (*unknowns)(cidx + 2), (*unknowns)(cidx + 3));
Vector3f diff = p - vk;
Vector3f grad(derivx(diff(0), diff(1), diff(2)), derivy(diff(0), diff(1), diff(2)), derivz(diff(0), diff(1), diff(2)));
//std::cout << alpha << std::endl;
//std::cout << beta(0) << "," << beta(1) << "," << beta(2) << " " << diff(0) << "," << diff(1) << "," << diff(2) << " " << grad(0) << "," << grad(1) << "," << grad(2) << std::endl;
out += alpha * smoothfunc(diff(0), diff(1), diff(2)) - beta.dot(grad);
//std::cout << out << std::endl;
}*/ | .text
.file "HRBFGeneratorDevice.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0017ec9a_00000000-6_HRBFGeneratorDevice.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "HRBFGeneratorDevice.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Note this file isn't configured to automatically compile.
// Here's how:
// If you want to look at the ptx first:
// nvcc -arch sm_50 -m 32 -ptx sgemm.cu
// Manually compile your kernel to a cubin.
// You should only have to do this once, unless you change params or shared size or globals:
// nvcc -arch sm_50 -m 32 -cubin sgemm.cu
// If tweaking a kernel or writing a new one based on this shell code you would then do this:
// maxas.pl -e kernel.cubin kernel.sass
// I've already included a modified kernel (sgemm.sass) so the next step is..
// Splice the manually assembled code back into the cubin:
// maxas.pl -i sgemm.sass sgemm.cubin
#include <device_functions.h>
#include <device_launch_parameters.h>
// Use extern C so C++ doesn't mangle our kernel name
extern "C"
// This kernel requires 32x1x1 threads per block
__global__ void __launch_bounds__(128) conv_kernel_128(
float *H, float *X, float *Y)
{
// Declare any shared memory your kernel requires
// Or you could just pass the amount in as a param to cuLaunchKernel
__shared__ float share[4096];
int tid = threadIdx.x;
int bx = blockIdx.x;
share[tid] = 1.0f;
// output something so your setup isn't optimized away.
Y[tid] = share[tid + bx] ;
} | code for sm_80
Function : conv_kernel_128
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff077424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0050*/ SHF.L.U32 R0, R4, 0x2, RZ ; /* 0x0000000204007819 */
/* 0x001fc600000006ff */
/*0060*/ STS [R4.X4], R7 ; /* 0x0000000704007388 */
/* 0x000fe20000004800 */
/*0070*/ LEA R0, R3, R0, 0x2 ; /* 0x0000000003007211 */
/* 0x002fe200078e10ff */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0090*/ LDS R5, [R0] ; /* 0x0000000000057984 */
/* 0x000e220000000800 */
/*00a0*/ IMAD.WIDE R2, R4, R3, c[0x0][0x170] ; /* 0x00005c0004027625 */
/* 0x000fca00078e0203 */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Note this file isn't configured to automatically compile.
// Here's how:
// If you want to look at the ptx first:
// nvcc -arch sm_50 -m 32 -ptx sgemm.cu
// Manually compile your kernel to a cubin.
// You should only have to do this once, unless you change params or shared size or globals:
// nvcc -arch sm_50 -m 32 -cubin sgemm.cu
// If tweaking a kernel or writing a new one based on this shell code you would then do this:
// maxas.pl -e kernel.cubin kernel.sass
// I've already included a modified kernel (sgemm.sass) so the next step is..
// Splice the manually assembled code back into the cubin:
// maxas.pl -i sgemm.sass sgemm.cubin
#include <device_functions.h>
#include <device_launch_parameters.h>
// Use extern C so C++ doesn't mangle our kernel name
extern "C"
// This kernel requires 32x1x1 threads per block
__global__ void __launch_bounds__(128) conv_kernel_128(
float *H, float *X, float *Y)
{
// Declare any shared memory your kernel requires
// Or you could just pass the amount in as a param to cuLaunchKernel
__shared__ float share[4096];
int tid = threadIdx.x;
int bx = blockIdx.x;
share[tid] = 1.0f;
// output something so your setup isn't optimized away.
Y[tid] = share[tid + bx] ;
} | .file "tmpxft_00054aec_00000000-6_maxas.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z15conv_kernel_128PfS_S_PfS_S_
.type _Z39__device_stub__Z15conv_kernel_128PfS_S_PfS_S_, @function
_Z39__device_stub__Z15conv_kernel_128PfS_S_PfS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq conv_kernel_128(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z15conv_kernel_128PfS_S_PfS_S_, .-_Z39__device_stub__Z15conv_kernel_128PfS_S_PfS_S_
.globl conv_kernel_128
.type conv_kernel_128, @function
conv_kernel_128:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z15conv_kernel_128PfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size conv_kernel_128, .-conv_kernel_128
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "conv_kernel_128"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq conv_kernel_128(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Note this file isn't configured to automatically compile.
// Here's how:
// If you want to look at the ptx first:
// nvcc -arch sm_50 -m 32 -ptx sgemm.cu
// Manually compile your kernel to a cubin.
// You should only have to do this once, unless you change params or shared size or globals:
// nvcc -arch sm_50 -m 32 -cubin sgemm.cu
// If tweaking a kernel or writing a new one based on this shell code you would then do this:
// maxas.pl -e kernel.cubin kernel.sass
// I've already included a modified kernel (sgemm.sass) so the next step is..
// Splice the manually assembled code back into the cubin:
// maxas.pl -i sgemm.sass sgemm.cubin
#include <device_functions.h>
#include <device_launch_parameters.h>
// Use extern C so C++ doesn't mangle our kernel name
extern "C"
// This kernel requires 32x1x1 threads per block
__global__ void __launch_bounds__(128) conv_kernel_128(
float *H, float *X, float *Y)
{
// Declare any shared memory your kernel requires
// Or you could just pass the amount in as a param to cuLaunchKernel
__shared__ float share[4096];
int tid = threadIdx.x;
int bx = blockIdx.x;
share[tid] = 1.0f;
// output something so your setup isn't optimized away.
Y[tid] = share[tid + bx] ;
} | // Note this file isn't configured to automatically compile.
// Here's how:
// If you want to look at the ptx first:
// nvcc -arch sm_50 -m 32 -ptx sgemm.cu
// Manually compile your kernel to a cubin.
// You should only have to do this once, unless you change params or shared size or globals:
// nvcc -arch sm_50 -m 32 -cubin sgemm.cu
// If tweaking a kernel or writing a new one based on this shell code you would then do this:
// maxas.pl -e kernel.cubin kernel.sass
// I've already included a modified kernel (sgemm.sass) so the next step is..
// Splice the manually assembled code back into the cubin:
// maxas.pl -i sgemm.sass sgemm.cubin
#include <hip/hip_runtime.h>
#include <hip/device_functions.h>
// Use extern C so C++ doesn't mangle our kernel name
extern "C"
// This kernel requires 32x1x1 threads per block
__global__ void __launch_bounds__(128) conv_kernel_128(
float *H, float *X, float *Y)
{
// Declare any shared memory your kernel requires
// Or you could just pass the amount in as a param to cuLaunchKernel
__shared__ float share[4096];
int tid = threadIdx.x;
int bx = blockIdx.x;
share[tid] = 1.0f;
// output something so your setup isn't optimized away.
Y[tid] = share[tid + bx] ;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Note this file isn't configured to automatically compile.
// Here's how:
// If you want to look at the ptx first:
// nvcc -arch sm_50 -m 32 -ptx sgemm.cu
// Manually compile your kernel to a cubin.
// You should only have to do this once, unless you change params or shared size or globals:
// nvcc -arch sm_50 -m 32 -cubin sgemm.cu
// If tweaking a kernel or writing a new one based on this shell code you would then do this:
// maxas.pl -e kernel.cubin kernel.sass
// I've already included a modified kernel (sgemm.sass) so the next step is..
// Splice the manually assembled code back into the cubin:
// maxas.pl -i sgemm.sass sgemm.cubin
#include <hip/hip_runtime.h>
#include <hip/device_functions.h>
// Use extern C so C++ doesn't mangle our kernel name
extern "C"
// This kernel requires 32x1x1 threads per block
__global__ void __launch_bounds__(128) conv_kernel_128(
float *H, float *X, float *Y)
{
// Declare any shared memory your kernel requires
// Or you could just pass the amount in as a param to cuLaunchKernel
__shared__ float share[4096];
int tid = threadIdx.x;
int bx = blockIdx.x;
share[tid] = 1.0f;
// output something so your setup isn't optimized away.
Y[tid] = share[tid + bx] ;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected conv_kernel_128
.globl conv_kernel_128
.p2align 8
.type conv_kernel_128,@function
conv_kernel_128:
v_dual_mov_b32 v2, 1.0 :: v_dual_lshlrev_b32 v1, 2, v0
v_add_lshl_u32 v0, v0, s15, 2
s_load_b64 s[0:1], s[0:1], 0x10
ds_store_b32 v1, v2
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel conv_kernel_128
.amdhsa_group_segment_fixed_size 16384
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size conv_kernel_128, .Lfunc_end0-conv_kernel_128
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 16384
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 128
.name: conv_kernel_128
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: conv_kernel_128.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Note this file isn't configured to automatically compile.
// Here's how:
// If you want to look at the ptx first:
// nvcc -arch sm_50 -m 32 -ptx sgemm.cu
// Manually compile your kernel to a cubin.
// You should only have to do this once, unless you change params or shared size or globals:
// nvcc -arch sm_50 -m 32 -cubin sgemm.cu
// If tweaking a kernel or writing a new one based on this shell code you would then do this:
// maxas.pl -e kernel.cubin kernel.sass
// I've already included a modified kernel (sgemm.sass) so the next step is..
// Splice the manually assembled code back into the cubin:
// maxas.pl -i sgemm.sass sgemm.cubin
#include <hip/hip_runtime.h>
#include <hip/device_functions.h>
// Use extern C so C++ doesn't mangle our kernel name
extern "C"
// This kernel requires 32x1x1 threads per block
__global__ void __launch_bounds__(128) conv_kernel_128(
float *H, float *X, float *Y)
{
// Declare any shared memory your kernel requires
// Or you could just pass the amount in as a param to cuLaunchKernel
__shared__ float share[4096];
int tid = threadIdx.x;
int bx = blockIdx.x;
share[tid] = 1.0f;
// output something so your setup isn't optimized away.
Y[tid] = share[tid + bx] ;
} | .text
.file "maxas.hip"
.globl __device_stub__conv_kernel_128 # -- Begin function __device_stub__conv_kernel_128
.p2align 4, 0x90
.type __device_stub__conv_kernel_128,@function
__device_stub__conv_kernel_128: # @__device_stub__conv_kernel_128
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $conv_kernel_128, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size __device_stub__conv_kernel_128, .Lfunc_end0-__device_stub__conv_kernel_128
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $conv_kernel_128, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type conv_kernel_128,@object # @conv_kernel_128
.section .rodata,"a",@progbits
.globl conv_kernel_128
.p2align 3, 0x0
conv_kernel_128:
.quad __device_stub__conv_kernel_128
.size conv_kernel_128, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "conv_kernel_128"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__conv_kernel_128
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym conv_kernel_128
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : conv_kernel_128
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff077424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0050*/ SHF.L.U32 R0, R4, 0x2, RZ ; /* 0x0000000204007819 */
/* 0x001fc600000006ff */
/*0060*/ STS [R4.X4], R7 ; /* 0x0000000704007388 */
/* 0x000fe20000004800 */
/*0070*/ LEA R0, R3, R0, 0x2 ; /* 0x0000000003007211 */
/* 0x002fe200078e10ff */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0090*/ LDS R5, [R0] ; /* 0x0000000000057984 */
/* 0x000e220000000800 */
/*00a0*/ IMAD.WIDE R2, R4, R3, c[0x0][0x170] ; /* 0x00005c0004027625 */
/* 0x000fca00078e0203 */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected conv_kernel_128
.globl conv_kernel_128
.p2align 8
.type conv_kernel_128,@function
conv_kernel_128:
v_dual_mov_b32 v2, 1.0 :: v_dual_lshlrev_b32 v1, 2, v0
v_add_lshl_u32 v0, v0, s15, 2
s_load_b64 s[0:1], s[0:1], 0x10
ds_store_b32 v1, v2
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel conv_kernel_128
.amdhsa_group_segment_fixed_size 16384
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size conv_kernel_128, .Lfunc_end0-conv_kernel_128
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 16384
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 128
.name: conv_kernel_128
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: conv_kernel_128.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00054aec_00000000-6_maxas.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z15conv_kernel_128PfS_S_PfS_S_
.type _Z39__device_stub__Z15conv_kernel_128PfS_S_PfS_S_, @function
_Z39__device_stub__Z15conv_kernel_128PfS_S_PfS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq conv_kernel_128(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z15conv_kernel_128PfS_S_PfS_S_, .-_Z39__device_stub__Z15conv_kernel_128PfS_S_PfS_S_
.globl conv_kernel_128
.type conv_kernel_128, @function
conv_kernel_128:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z15conv_kernel_128PfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size conv_kernel_128, .-conv_kernel_128
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "conv_kernel_128"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq conv_kernel_128(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "maxas.hip"
.globl __device_stub__conv_kernel_128 # -- Begin function __device_stub__conv_kernel_128
.p2align 4, 0x90
.type __device_stub__conv_kernel_128,@function
__device_stub__conv_kernel_128: # @__device_stub__conv_kernel_128
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $conv_kernel_128, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size __device_stub__conv_kernel_128, .Lfunc_end0-__device_stub__conv_kernel_128
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $conv_kernel_128, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type conv_kernel_128,@object # @conv_kernel_128
.section .rodata,"a",@progbits
.globl conv_kernel_128
.p2align 3, 0x0
conv_kernel_128:
.quad __device_stub__conv_kernel_128
.size conv_kernel_128, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "conv_kernel_128"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__conv_kernel_128
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym conv_kernel_128
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void NN_DownSampling( float *target, const float *source, const int wt, const int ht, const int ws, const int hs )
{
int y = blockIdx.y * blockDim.y + threadIdx.y;
int x = blockIdx.x * blockDim.x + threadIdx.x;
const int curt = y*wt+x;
const int curs = (y*2)*ws+x*2;
if(y < ht and x < wt) {
target[curt*3+0] = source[curs*3+0];
target[curt*3+1] = source[curs*3+1];
target[curt*3+2] = source[curs*3+2];
}
} | code for sm_80
Function : _Z15NN_DownSamplingPfPKfiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R5, R5, c[0x0][0x0], R2 ; /* 0x0000000005057a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x170], P0 ; /* 0x00005c0005007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R2, R0, c[0x0][0x178], R5 ; /* 0x00005e0000027a24 */
/* 0x000fe200078e0205 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00d0*/ IMAD R2, R2, 0x6, RZ ; /* 0x0000000602027824 */
/* 0x000fca00078e02ff */
/*00e0*/ IMAD.WIDE R2, R2, R9, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0209 */
/*00f0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea2000c1e1900 */
/*0100*/ IMAD R0, R0, c[0x0][0x170], R5 ; /* 0x00005c0000007a24 */
/* 0x000fca00078e0205 */
/*0110*/ LEA R0, R0, R0, 0x1 ; /* 0x0000000000007211 */
/* 0x000fca00078e08ff */
/*0120*/ IMAD.WIDE R4, R0, R9, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fca00078e0209 */
/*0130*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x004fe8000c101904 */
/*0140*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040402097981 */
/* 0x000ea8000c1e1900 */
/*0150*/ STG.E [R4.64+0x4], R9 ; /* 0x0000040904007986 */
/* 0x004fe8000c101904 */
/*0160*/ LDG.E R11, [R2.64+0x8] ; /* 0x00000804020b7981 */
/* 0x000ea8000c1e1900 */
/*0170*/ STG.E [R4.64+0x8], R11 ; /* 0x0000080b04007986 */
/* 0x004fe2000c101904 */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ BRA 0x190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void NN_DownSampling( float *target, const float *source, const int wt, const int ht, const int ws, const int hs )
{
int y = blockIdx.y * blockDim.y + threadIdx.y;
int x = blockIdx.x * blockDim.x + threadIdx.x;
const int curt = y*wt+x;
const int curs = (y*2)*ws+x*2;
if(y < ht and x < wt) {
target[curt*3+0] = source[curs*3+0];
target[curt*3+1] = source[curs*3+1];
target[curt*3+2] = source[curs*3+2];
}
} | .file "tmpxft_000b15bf_00000000-6_NN_DownSampling.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z15NN_DownSamplingPfPKfiiiiPfPKfiiii
.type _Z42__device_stub__Z15NN_DownSamplingPfPKfiiiiPfPKfiiii, @function
_Z42__device_stub__Z15NN_DownSamplingPfPKfiiiiPfPKfiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15NN_DownSamplingPfPKfiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z15NN_DownSamplingPfPKfiiiiPfPKfiiii, .-_Z42__device_stub__Z15NN_DownSamplingPfPKfiiiiPfPKfiiii
.globl _Z15NN_DownSamplingPfPKfiiii
.type _Z15NN_DownSamplingPfPKfiiii, @function
_Z15NN_DownSamplingPfPKfiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z15NN_DownSamplingPfPKfiiiiPfPKfiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15NN_DownSamplingPfPKfiiii, .-_Z15NN_DownSamplingPfPKfiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15NN_DownSamplingPfPKfiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15NN_DownSamplingPfPKfiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void NN_DownSampling( float *target, const float *source, const int wt, const int ht, const int ws, const int hs )
{
int y = blockIdx.y * blockDim.y + threadIdx.y;
int x = blockIdx.x * blockDim.x + threadIdx.x;
const int curt = y*wt+x;
const int curs = (y*2)*ws+x*2;
if(y < ht and x < wt) {
target[curt*3+0] = source[curs*3+0];
target[curt*3+1] = source[curs*3+1];
target[curt*3+2] = source[curs*3+2];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void NN_DownSampling( float *target, const float *source, const int wt, const int ht, const int ws, const int hs )
{
int y = blockIdx.y * blockDim.y + threadIdx.y;
int x = blockIdx.x * blockDim.x + threadIdx.x;
const int curt = y*wt+x;
const int curs = (y*2)*ws+x*2;
if(y < ht and x < wt) {
target[curt*3+0] = source[curs*3+0];
target[curt*3+1] = source[curs*3+1];
target[curt*3+2] = source[curs*3+2];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void NN_DownSampling( float *target, const float *source, const int wt, const int ht, const int ws, const int hs )
{
int y = blockIdx.y * blockDim.y + threadIdx.y;
int x = blockIdx.x * blockDim.x + threadIdx.x;
const int curt = y*wt+x;
const int curs = (y*2)*ws+x*2;
if(y < ht and x < wt) {
target[curt*3+0] = source[curs*3+0];
target[curt*3+1] = source[curs*3+1];
target[curt*3+2] = source[curs*3+2];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15NN_DownSamplingPfPKfiiii
.globl _Z15NN_DownSamplingPfPKfiiii
.p2align 8
.type _Z15NN_DownSamplingPfPKfiiii,@function
_Z15NN_DownSamplingPfPKfiiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x10
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s4, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v2, 6
v_ashrrev_i32_e32 v3, 31, v2
v_mad_u64_u32 v[5:6], null, v0, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_lshl_add_u32 v0, v5, 1, v5
v_or_b32_e32 v5, 1, v2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v6, 31, v5
global_load_b32 v7, v[3:4], off
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v7, off
global_load_b32 v2, v[5:6], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off offset:4
global_load_b32 v2, v[3:4], off offset:8
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off offset:8
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15NN_DownSamplingPfPKfiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15NN_DownSamplingPfPKfiiii, .Lfunc_end0-_Z15NN_DownSamplingPfPKfiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15NN_DownSamplingPfPKfiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15NN_DownSamplingPfPKfiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void NN_DownSampling( float *target, const float *source, const int wt, const int ht, const int ws, const int hs )
{
int y = blockIdx.y * blockDim.y + threadIdx.y;
int x = blockIdx.x * blockDim.x + threadIdx.x;
const int curt = y*wt+x;
const int curs = (y*2)*ws+x*2;
if(y < ht and x < wt) {
target[curt*3+0] = source[curs*3+0];
target[curt*3+1] = source[curs*3+1];
target[curt*3+2] = source[curs*3+2];
}
} | .text
.file "NN_DownSampling.hip"
.globl _Z30__device_stub__NN_DownSamplingPfPKfiiii # -- Begin function _Z30__device_stub__NN_DownSamplingPfPKfiiii
.p2align 4, 0x90
.type _Z30__device_stub__NN_DownSamplingPfPKfiiii,@function
_Z30__device_stub__NN_DownSamplingPfPKfiiii: # @_Z30__device_stub__NN_DownSamplingPfPKfiiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15NN_DownSamplingPfPKfiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z30__device_stub__NN_DownSamplingPfPKfiiii, .Lfunc_end0-_Z30__device_stub__NN_DownSamplingPfPKfiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15NN_DownSamplingPfPKfiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15NN_DownSamplingPfPKfiiii,@object # @_Z15NN_DownSamplingPfPKfiiii
.section .rodata,"a",@progbits
.globl _Z15NN_DownSamplingPfPKfiiii
.p2align 3, 0x0
_Z15NN_DownSamplingPfPKfiiii:
.quad _Z30__device_stub__NN_DownSamplingPfPKfiiii
.size _Z15NN_DownSamplingPfPKfiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15NN_DownSamplingPfPKfiiii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__NN_DownSamplingPfPKfiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15NN_DownSamplingPfPKfiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15NN_DownSamplingPfPKfiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R5, R5, c[0x0][0x0], R2 ; /* 0x0000000005057a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x170], P0 ; /* 0x00005c0005007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R2, R0, c[0x0][0x178], R5 ; /* 0x00005e0000027a24 */
/* 0x000fe200078e0205 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00d0*/ IMAD R2, R2, 0x6, RZ ; /* 0x0000000602027824 */
/* 0x000fca00078e02ff */
/*00e0*/ IMAD.WIDE R2, R2, R9, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0209 */
/*00f0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea2000c1e1900 */
/*0100*/ IMAD R0, R0, c[0x0][0x170], R5 ; /* 0x00005c0000007a24 */
/* 0x000fca00078e0205 */
/*0110*/ LEA R0, R0, R0, 0x1 ; /* 0x0000000000007211 */
/* 0x000fca00078e08ff */
/*0120*/ IMAD.WIDE R4, R0, R9, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fca00078e0209 */
/*0130*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x004fe8000c101904 */
/*0140*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040402097981 */
/* 0x000ea8000c1e1900 */
/*0150*/ STG.E [R4.64+0x4], R9 ; /* 0x0000040904007986 */
/* 0x004fe8000c101904 */
/*0160*/ LDG.E R11, [R2.64+0x8] ; /* 0x00000804020b7981 */
/* 0x000ea8000c1e1900 */
/*0170*/ STG.E [R4.64+0x8], R11 ; /* 0x0000080b04007986 */
/* 0x004fe2000c101904 */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ BRA 0x190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15NN_DownSamplingPfPKfiiii
.globl _Z15NN_DownSamplingPfPKfiiii
.p2align 8
.type _Z15NN_DownSamplingPfPKfiiii,@function
_Z15NN_DownSamplingPfPKfiiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x10
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s4, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v2, 6
v_ashrrev_i32_e32 v3, 31, v2
v_mad_u64_u32 v[5:6], null, v0, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_lshl_add_u32 v0, v5, 1, v5
v_or_b32_e32 v5, 1, v2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v6, 31, v5
global_load_b32 v7, v[3:4], off
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v7, off
global_load_b32 v2, v[5:6], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off offset:4
global_load_b32 v2, v[3:4], off offset:8
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off offset:8
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15NN_DownSamplingPfPKfiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15NN_DownSamplingPfPKfiiii, .Lfunc_end0-_Z15NN_DownSamplingPfPKfiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15NN_DownSamplingPfPKfiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15NN_DownSamplingPfPKfiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b15bf_00000000-6_NN_DownSampling.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z15NN_DownSamplingPfPKfiiiiPfPKfiiii
.type _Z42__device_stub__Z15NN_DownSamplingPfPKfiiiiPfPKfiiii, @function
_Z42__device_stub__Z15NN_DownSamplingPfPKfiiiiPfPKfiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15NN_DownSamplingPfPKfiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z15NN_DownSamplingPfPKfiiiiPfPKfiiii, .-_Z42__device_stub__Z15NN_DownSamplingPfPKfiiiiPfPKfiiii
.globl _Z15NN_DownSamplingPfPKfiiii
.type _Z15NN_DownSamplingPfPKfiiii, @function
_Z15NN_DownSamplingPfPKfiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z15NN_DownSamplingPfPKfiiiiPfPKfiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15NN_DownSamplingPfPKfiiii, .-_Z15NN_DownSamplingPfPKfiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15NN_DownSamplingPfPKfiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15NN_DownSamplingPfPKfiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "NN_DownSampling.hip"
.globl _Z30__device_stub__NN_DownSamplingPfPKfiiii # -- Begin function _Z30__device_stub__NN_DownSamplingPfPKfiiii
.p2align 4, 0x90
.type _Z30__device_stub__NN_DownSamplingPfPKfiiii,@function
_Z30__device_stub__NN_DownSamplingPfPKfiiii: # @_Z30__device_stub__NN_DownSamplingPfPKfiiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15NN_DownSamplingPfPKfiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z30__device_stub__NN_DownSamplingPfPKfiiii, .Lfunc_end0-_Z30__device_stub__NN_DownSamplingPfPKfiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15NN_DownSamplingPfPKfiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15NN_DownSamplingPfPKfiiii,@object # @_Z15NN_DownSamplingPfPKfiiii
.section .rodata,"a",@progbits
.globl _Z15NN_DownSamplingPfPKfiiii
.p2align 3, 0x0
_Z15NN_DownSamplingPfPKfiiii:
.quad _Z30__device_stub__NN_DownSamplingPfPKfiiii
.size _Z15NN_DownSamplingPfPKfiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15NN_DownSamplingPfPKfiiii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__NN_DownSamplingPfPKfiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15NN_DownSamplingPfPKfiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#define LSIZE 31
#define MIN_LIM 12.0
#define MAX_LIM 30.0
void check_input(int argc,char* argv[]);
__global__ void examine(float *d_coordinates,int *d_coords_within,int d_lines);
long calc_lines(char *filename);
int main(int argc,char * argv[])
{
check_input(argc,argv); // Check cmd inputs
char *filename=argv[3]; // Variable initialization
int coll = atoi(argv[1]);
int exec_time=atoi(argv[2]);
int threads=atoi(argv[4]);
int BLOCKSIZE = atoi(argv[5]);
long loop_count;
loop_count =calc_lines(filename); // Count the lines of input file
FILE *input=fopen(filename,"r"); // Open file with file descriptor
struct cudaDeviceProp prop;
cudaGetDeviceProperties(&prop,0); // Get gpu's properties information
if(coll != -1) // Handle max_collisions argument
{
if(coll>loop_count)
{
printf("[!] Warning: Specified collisions to be tested exceed the ones in input file\n");
printf("[!] Setting the number of collisions to the maximum (taken from input file)\n");
}
else
{
if (coll<0) return 1;
loop_count = coll;
}
}
if (BLOCKSIZE==-1) // Handle blocksize argument
{
BLOCKSIZE=512; // A default value
}
else
{
if (BLOCKSIZE%prop.warpSize!=0 || BLOCKSIZE<=0)
{
printf("[-]Block_size must be a positive multiple of gpu's warp_size %d \n",prop.warpSize );
return 5;
}
}
if (threads!=-1) // Handle threads argument
{
if (threads<=0) return 4;
if (threads%BLOCKSIZE!=0)
{
threads=(threads/BLOCKSIZE)*BLOCKSIZE;
}
}
else
{
threads=prop.maxThreadsPerMultiProcessor*prop.multiProcessorCount;
}
// Print some information [ Usefull for debugging ]
printf("[+] GPU-model: %s\tTotal GPU memory %ld MB \n",prop.name,prop.totalGlobalMem/(1024*1024) );
printf("[!] You are trying to allocate %ld MBs of memmory on CPU-RAM and GPU-GlobalMem\n",threads*3*sizeof(float)/(1024*1024) );
printf("[+] Launching %d GPU-Threads with BlockSize %d\n",threads,BLOCKSIZE );
// Initialize CUDA WallClock-time counters as events
cudaEvent_t start,stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
dim3 blockSize(BLOCKSIZE); // Declare CUDA Block size explicitly
dim3 gridSize(threads/BLOCKSIZE); // Declare CUDA Grid size explicitly
float *h_coordinates=(float * )malloc(3*threads*sizeof(float)); // allocate Host memmory for elements to be read from file
float *d_coordinates;
int *d_coords_within,*h_coords_within=(int*)malloc(sizeof(int)); // allocate Host memmory for the counter of coordinates in area of interest
*h_coords_within=0;
// Allocate memmory on CUDA capable Device for:
cudaMalloc(&d_coordinates,3*threads*sizeof(float)); // input file's coordinates
cudaMalloc(&d_coords_within,sizeof(int)); // coordinates counter
cudaMemcpy(d_coords_within,h_coords_within,sizeof(int),cudaMemcpyHostToDevice); // Initialize the value of cuounter on Device
int i,j=0;
float time_elapsed = 0;
printf("[+] Working...\n" );
cudaEventRecord(start); // Starting time reference
while(j<loop_count && (exec_time==-1?1:time_elapsed<exec_time)) // Main loop of the programm
{
if (j+threads>loop_count)
{
threads=loop_count-j;
cudaFree(d_coordinates);
cudaMalloc(&d_coordinates,3*threads*sizeof(float));
}
for(i=0;i<threads;i++)
{
fscanf(input,"%f %f %f",&h_coordinates[i*3],&h_coordinates[i*3+1],&h_coordinates[i*3+2]); // Read cooordinates from file
}
cudaMemcpy(d_coordinates,h_coordinates,3*threads*sizeof(float),cudaMemcpyHostToDevice); // Copy read cooordinates on Device
examine<<<gridSize,blockSize>>>(d_coordinates,d_coords_within,3*threads); // Launch gpu kernel for calculations
cudaEventRecord(stop); // Stop time reference
cudaEventSynchronize(stop); // Block CPU until "stop" event is recorded
cudaEventElapsedTime(&time_elapsed, start, stop); // Calculate the time elapsed in milliseconds
time_elapsed=time_elapsed/1000; // Convert milliseconds to seconds
j+=threads;
}
// Destroy CUDA timers
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaMemcpy(h_coords_within,d_coords_within,sizeof(int),cudaMemcpyDeviceToHost); // Copy results from Device to Host
//Printing results
printf("[+] Main part of the program was being executed for :: %.3f :: sec)\n", time_elapsed);
printf("[+] %ld coordinates have been analyzed\n[+] %d cooordinates were inside the area of interest\n[+] %ld coordinates read per second\n", loop_count, *h_coords_within, (time_elapsed<1?loop_count:loop_count/(int)time_elapsed));
// Free Host and Device memory
cudaFree(d_coordinates);
cudaFree(d_coords_within);
fclose(input);
free(h_coordinates);
free(h_coords_within);
return 0;
}
__global__ void examine(float *d_coordinates,int *d_coords_within,int d_lines)
{
int index=blockIdx.x*3*blockDim.x+3*threadIdx.x; // find the index of starting element for each thread on each block
float coord1=d_coordinates[index],coord2=d_coordinates[index+1],coord3=d_coordinates[index+2]; // Copy cooordinates from GPU's global memory to thread's local memory
if(index>=d_lines) return;
if(coord1 >= MIN_LIM && coord1 <= MAX_LIM && coord2 >= MIN_LIM && coord2 <= MAX_LIM && coord3 >= MIN_LIM && coord3 <= MAX_LIM)
{
// If the current coordinate is within the accepted limits,
atomicAdd((unsigned int*)d_coords_within,1); // So as threads do not mess up the values
}
}
void check_input(int argc,char *argv[]) // Handle number of arguments errors and show usage
{
if (argc<6 || argc>6)
{
printf("[-] Usage: ./examine [max_collisions] [max_exec_time] [input_file] [Threads] [1D_blockSize]\nUse \"-1\": for no boundies \n");
if (argc==2) if (!strcmp(argv[1],"--help"))
{
printf("max_collisions: Maximum number of collisions\nmax_exec_time: Maximum execution time\ninput_file: Filename to examine\nThreads: Number of gpu-threads to use / # Rows in memmory\n1D_blocksize: gpu-blocksize to use" );
printf("\t ======Usefull info!======\n");
printf("1) 1D_blockSize must be a multiple of 32. (or whatever warp_size is supported by your GPU)\n2) Threads should be a multiple of blockSize\n 3)These 2 parameters are important for performance\n" );
}
exit(2);
}
}
long calc_lines(char *filename) // Calculates the lines of input file
{
FILE *file=fopen(filename,"r");
fseek(file,0L,SEEK_END); //set file position indicator right to the end-of-file
long lines=ftell(file); //store the number of bytes since the beginning of the file
fseek(file,0L,SEEK_SET);
fclose(file);
return lines/LSIZE; //return lines count of the file
} | code for sm_80
Function : _Z7examinePfPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0040*/ IMAD R0, R0, 0x3, RZ ; /* 0x0000000300007824 */
/* 0x000fca00078e02ff */
/*0050*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0090*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*00a0*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R0, [R2.64+0x4] ; /* 0x0000040402007981 */
/* 0x000ee8000c1e1900 */
/*00c0*/ LDG.E R4, [R2.64+0x8] ; /* 0x0000080402047981 */
/* 0x000f22000c1e1900 */
/*00d0*/ FSETP.GTU.AND P0, PT, R5, 30, PT ; /* 0x41f000000500780b */
/* 0x004fc80003f0c000 */
/*00e0*/ FSETP.LTU.OR P0, PT, R5, 12, P0 ; /* 0x414000000500780b */
/* 0x000fc80000709400 */
/*00f0*/ FSETP.LTU.OR P0, PT, R0, 12, P0 ; /* 0x414000000000780b */
/* 0x008fc80000709400 */
/*0100*/ FSETP.GTU.OR P0, PT, R0, 30, P0 ; /* 0x41f000000000780b */
/* 0x000fc8000070c400 */
/*0110*/ FSETP.LTU.OR P0, PT, R4, 12, P0 ; /* 0x414000000400780b */
/* 0x010fc80000709400 */
/*0120*/ FSETP.GTU.OR P0, PT, R4, 30, P0 ; /* 0x41f000000400780b */
/* 0x000fda000070c400 */
/*0130*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0140*/ S2R R0, SR_LANEID ; /* 0x0000000000007919 */
/* 0x000e220000000000 */
/*0150*/ VOTEU.ANY UR6, UPT, PT ; /* 0x0000000000067886 */
/* 0x000fe200038e0100 */
/*0160*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe200078e00ff */
/*0170*/ UFLO.U32 UR7, UR6 ; /* 0x00000006000772bd */
/* 0x000fe200080e0000 */
/*0180*/ POPC R5, UR6 ; /* 0x0000000600057d09 */
/* 0x000e620008000000 */
/*0190*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fc800078e00ff */
/*01a0*/ ISETP.EQ.U32.AND P0, PT, R0, UR7, PT ; /* 0x0000000700007c0c */
/* 0x001fda000bf02070 */
/*01b0*/ @P0 RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200098e */
/* 0x002fe2000c10e184 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#define LSIZE 31
#define MIN_LIM 12.0
#define MAX_LIM 30.0
void check_input(int argc,char* argv[]);
__global__ void examine(float *d_coordinates,int *d_coords_within,int d_lines);
long calc_lines(char *filename);
int main(int argc,char * argv[])
{
check_input(argc,argv); // Check cmd inputs
char *filename=argv[3]; // Variable initialization
int coll = atoi(argv[1]);
int exec_time=atoi(argv[2]);
int threads=atoi(argv[4]);
int BLOCKSIZE = atoi(argv[5]);
long loop_count;
loop_count =calc_lines(filename); // Count the lines of input file
FILE *input=fopen(filename,"r"); // Open file with file descriptor
struct cudaDeviceProp prop;
cudaGetDeviceProperties(&prop,0); // Get gpu's properties information
if(coll != -1) // Handle max_collisions argument
{
if(coll>loop_count)
{
printf("[!] Warning: Specified collisions to be tested exceed the ones in input file\n");
printf("[!] Setting the number of collisions to the maximum (taken from input file)\n");
}
else
{
if (coll<0) return 1;
loop_count = coll;
}
}
if (BLOCKSIZE==-1) // Handle blocksize argument
{
BLOCKSIZE=512; // A default value
}
else
{
if (BLOCKSIZE%prop.warpSize!=0 || BLOCKSIZE<=0)
{
printf("[-]Block_size must be a positive multiple of gpu's warp_size %d \n",prop.warpSize );
return 5;
}
}
if (threads!=-1) // Handle threads argument
{
if (threads<=0) return 4;
if (threads%BLOCKSIZE!=0)
{
threads=(threads/BLOCKSIZE)*BLOCKSIZE;
}
}
else
{
threads=prop.maxThreadsPerMultiProcessor*prop.multiProcessorCount;
}
// Print some information [ Usefull for debugging ]
printf("[+] GPU-model: %s\tTotal GPU memory %ld MB \n",prop.name,prop.totalGlobalMem/(1024*1024) );
printf("[!] You are trying to allocate %ld MBs of memmory on CPU-RAM and GPU-GlobalMem\n",threads*3*sizeof(float)/(1024*1024) );
printf("[+] Launching %d GPU-Threads with BlockSize %d\n",threads,BLOCKSIZE );
// Initialize CUDA WallClock-time counters as events
cudaEvent_t start,stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
dim3 blockSize(BLOCKSIZE); // Declare CUDA Block size explicitly
dim3 gridSize(threads/BLOCKSIZE); // Declare CUDA Grid size explicitly
float *h_coordinates=(float * )malloc(3*threads*sizeof(float)); // allocate Host memmory for elements to be read from file
float *d_coordinates;
int *d_coords_within,*h_coords_within=(int*)malloc(sizeof(int)); // allocate Host memmory for the counter of coordinates in area of interest
*h_coords_within=0;
// Allocate memmory on CUDA capable Device for:
cudaMalloc(&d_coordinates,3*threads*sizeof(float)); // input file's coordinates
cudaMalloc(&d_coords_within,sizeof(int)); // coordinates counter
cudaMemcpy(d_coords_within,h_coords_within,sizeof(int),cudaMemcpyHostToDevice); // Initialize the value of cuounter on Device
int i,j=0;
float time_elapsed = 0;
printf("[+] Working...\n" );
cudaEventRecord(start); // Starting time reference
while(j<loop_count && (exec_time==-1?1:time_elapsed<exec_time)) // Main loop of the programm
{
if (j+threads>loop_count)
{
threads=loop_count-j;
cudaFree(d_coordinates);
cudaMalloc(&d_coordinates,3*threads*sizeof(float));
}
for(i=0;i<threads;i++)
{
fscanf(input,"%f %f %f",&h_coordinates[i*3],&h_coordinates[i*3+1],&h_coordinates[i*3+2]); // Read cooordinates from file
}
cudaMemcpy(d_coordinates,h_coordinates,3*threads*sizeof(float),cudaMemcpyHostToDevice); // Copy read cooordinates on Device
examine<<<gridSize,blockSize>>>(d_coordinates,d_coords_within,3*threads); // Launch gpu kernel for calculations
cudaEventRecord(stop); // Stop time reference
cudaEventSynchronize(stop); // Block CPU until "stop" event is recorded
cudaEventElapsedTime(&time_elapsed, start, stop); // Calculate the time elapsed in milliseconds
time_elapsed=time_elapsed/1000; // Convert milliseconds to seconds
j+=threads;
}
// Destroy CUDA timers
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaMemcpy(h_coords_within,d_coords_within,sizeof(int),cudaMemcpyDeviceToHost); // Copy results from Device to Host
//Printing results
printf("[+] Main part of the program was being executed for :: %.3f :: sec)\n", time_elapsed);
printf("[+] %ld coordinates have been analyzed\n[+] %d cooordinates were inside the area of interest\n[+] %ld coordinates read per second\n", loop_count, *h_coords_within, (time_elapsed<1?loop_count:loop_count/(int)time_elapsed));
// Free Host and Device memory
cudaFree(d_coordinates);
cudaFree(d_coords_within);
fclose(input);
free(h_coordinates);
free(h_coords_within);
return 0;
}
__global__ void examine(float *d_coordinates,int *d_coords_within,int d_lines)
{
int index=blockIdx.x*3*blockDim.x+3*threadIdx.x; // find the index of starting element for each thread on each block
float coord1=d_coordinates[index],coord2=d_coordinates[index+1],coord3=d_coordinates[index+2]; // Copy cooordinates from GPU's global memory to thread's local memory
if(index>=d_lines) return;
if(coord1 >= MIN_LIM && coord1 <= MAX_LIM && coord2 >= MIN_LIM && coord2 <= MAX_LIM && coord3 >= MIN_LIM && coord3 <= MAX_LIM)
{
// If the current coordinate is within the accepted limits,
atomicAdd((unsigned int*)d_coords_within,1); // So as threads do not mess up the values
}
}
void check_input(int argc,char *argv[]) // Handle number of arguments errors and show usage
{
if (argc<6 || argc>6)
{
printf("[-] Usage: ./examine [max_collisions] [max_exec_time] [input_file] [Threads] [1D_blockSize]\nUse \"-1\": for no boundies \n");
if (argc==2) if (!strcmp(argv[1],"--help"))
{
printf("max_collisions: Maximum number of collisions\nmax_exec_time: Maximum execution time\ninput_file: Filename to examine\nThreads: Number of gpu-threads to use / # Rows in memmory\n1D_blocksize: gpu-blocksize to use" );
printf("\t ======Usefull info!======\n");
printf("1) 1D_blockSize must be a multiple of 32. (or whatever warp_size is supported by your GPU)\n2) Threads should be a multiple of blockSize\n 3)These 2 parameters are important for performance\n" );
}
exit(2);
}
}
long calc_lines(char *filename) // Calculates the lines of input file
{
FILE *file=fopen(filename,"r");
fseek(file,0L,SEEK_END); //set file position indicator right to the end-of-file
long lines=ftell(file); //store the number of bytes since the beginning of the file
fseek(file,0L,SEEK_SET);
fclose(file);
return lines/LSIZE; //return lines count of the file
} | .file "tmpxft_000936b8_00000000-6_examine.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "[-] Usage: ./examine [max_collisions] [max_exec_time] [input_file] [Threads] [1D_blockSize]\nUse \"-1\": for no boundies \n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "--help"
.section .rodata.str1.8
.align 8
.LC2:
.string "max_collisions: Maximum number of collisions\nmax_exec_time: Maximum execution time\ninput_file: Filename to examine\nThreads: Number of gpu-threads to use / # Rows in memmory\n1D_blocksize: gpu-blocksize to use"
.section .rodata.str1.1
.LC3:
.string "\t ======Usefull info!======\n"
.section .rodata.str1.8
.align 8
.LC4:
.string "1) 1D_blockSize must be a multiple of 32. (or whatever warp_size is supported by your GPU)\n2) Threads should be a multiple of blockSize\n 3)These 2 parameters are important for performance\n"
.text
.globl _Z11check_inputiPPc
.type _Z11check_inputiPPc, @function
_Z11check_inputiPPc:
.LFB2058:
.cfi_startproc
endbr64
cmpl $6, %edi
jne .L9
ret
.L9:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl %edi, %ebx
movq %rsi, %rbp
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $2, %ebx
je .L10
.L5:
movl $2, %edi
call exit@PLT
.L10:
movq 8(%rbp), %rdi
leaq .LC1(%rip), %rsi
call strcmp@PLT
testl %eax, %eax
jne .L5
leaq .LC2(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L5
.cfi_endproc
.LFE2058:
.size _Z11check_inputiPPc, .-_Z11check_inputiPPc
.section .rodata.str1.1
.LC5:
.string "r"
.text
.globl _Z10calc_linesPc
.type _Z10calc_linesPc, @function
_Z10calc_linesPc:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
leaq .LC5(%rip), %rsi
call fopen@PLT
movq %rax, %rbp
movl $2, %edx
movl $0, %esi
movq %rax, %rdi
call fseek@PLT
movq %rbp, %rdi
call ftell@PLT
movq %rax, %rbx
movl $0, %edx
movl $0, %esi
movq %rbp, %rdi
call fseek@PLT
movq %rbp, %rdi
call fclose@PLT
movabsq $-8925843906633654007, %rdx
movq %rbx, %rax
imulq %rdx
leaq (%rdx,%rbx), %rax
sarq $4, %rax
sarq $63, %rbx
subq %rbx, %rax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z10calc_linesPc, .-_Z10calc_linesPc
.globl _Z29__device_stub__Z7examinePfPiiPfPii
.type _Z29__device_stub__Z7examinePfPiiPfPii, @function
_Z29__device_stub__Z7examinePfPiiPfPii:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7examinePfPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z29__device_stub__Z7examinePfPiiPfPii, .-_Z29__device_stub__Z7examinePfPiiPfPii
.globl _Z7examinePfPii
.type _Z7examinePfPii, @function
_Z7examinePfPii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7examinePfPiiPfPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z7examinePfPii, .-_Z7examinePfPii
.section .rodata.str1.8
.align 8
.LC6:
.string "[!] Warning: Specified collisions to be tested exceed the ones in input file\n"
.align 8
.LC7:
.string "[!] Setting the number of collisions to the maximum (taken from input file)\n"
.align 8
.LC8:
.string "[-]Block_size must be a positive multiple of gpu's warp_size %d \n"
.align 8
.LC9:
.string "[+] GPU-model: %s\tTotal GPU memory %ld MB \n"
.align 8
.LC10:
.string "[!] You are trying to allocate %ld MBs of memmory on CPU-RAM and GPU-GlobalMem\n"
.align 8
.LC11:
.string "[+] Launching %d GPU-Threads with BlockSize %d\n"
.section .rodata.str1.1
.LC13:
.string "[+] Working...\n"
.LC14:
.string "%f %f %f"
.section .rodata.str1.8
.align 8
.LC16:
.string "[+] Main part of the program was being executed for :: %.3f :: sec)\n"
.align 8
.LC18:
.string "[+] %ld coordinates have been analyzed\n[+] %d cooordinates were inside the area of interest\n[+] %ld coordinates read per second\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1160, %rsp
.cfi_def_cfa_offset 1216
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 1144(%rsp)
xorl %eax, %eax
call _Z11check_inputiPPc
movq 24(%rbx), %r12
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r14
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
movq 32(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movq 40(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movl %eax, %ebx
movq %r12, %rdi
call _Z10calc_linesPc
movq %rax, (%rsp)
leaq .LC5(%rip), %rsi
movq %r12, %rdi
call fopen@PLT
movq %rax, %r12
leaq 112(%rsp), %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
cmpl $-1, %r14d
je .L22
movslq %r14d, %rax
movq (%rsp), %rsi
cmpq %rsi, %rax
jg .L46
testl %r14d, %r14d
js .L38
movq %rax, (%rsp)
.L22:
cmpl $-1, %ebp
je .L39
movl 420(%rsp), %ecx
movl %ebx, %eax
cltd
idivl %ecx
testl %edx, %edx
jne .L42
testl %ebp, %ebp
jle .L42
.L25:
movl %r13d, %r14d
cmpl $-1, %r13d
je .L27
testl %r13d, %r13d
jle .L40
movl %r13d, %eax
cltd
idivl %ebx
testl %edx, %edx
je .L28
movl %r13d, %eax
cltd
idivl %ebx
movl %eax, %r14d
imull %ebx, %r14d
jmp .L28
.L46:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L22
.L42:
movl %ecx, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $5, %eax
jmp .L21
.L39:
movl $512, %ebx
jmp .L25
.L27:
movl 736(%rsp), %r14d
imull 500(%rsp), %r14d
.L28:
movq 400(%rsp), %rcx
shrq $20, %rcx
leaq 112(%rsp), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
imull $3, %r14d, %ebp
movslq %ebp, %rbp
salq $2, %rbp
movq %rbp, %rdx
shrq $20, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %ecx
movl %r14d, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
movl %ebx, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl %r14d, %eax
cltd
idivl %ebx
movl %eax, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movq %rbp, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movl $4, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, (%rax)
leaq 72(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 80(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4, %edx
movq %rbx, %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl $0x00000000, 52(%rsp)
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
cmpq $0, (%rsp)
jle .L29
movl %r15d, 20(%rsp)
movl $0, %r15d
leaq 72(%rsp), %rax
movq %rax, 32(%rsp)
leaq .LC14(%rip), %r13
leaq 52(%rsp), %rax
movq %rax, 24(%rsp)
movq %rbx, 40(%rsp)
jmp .L30
.L35:
leal (%r14,%r15), %eax
cltq
movq (%rsp), %rsi
cmpq %rsi, %rax
jg .L47
.L31:
testl %r14d, %r14d
jle .L32
movq 8(%rsp), %rdx
movq %rdx, %rbx
movslq %r14d, %rax
leaq (%rax,%rax,2), %rax
leaq (%rdx,%rax,4), %rbp
.L33:
leaq 4(%rbx), %rcx
leaq 8(%rbx), %r8
movq %rbx, %rdx
movq %r13, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $12, %rbx
cmpq %rbp, %rbx
jne .L33
.L32:
leal (%r14,%r14,2), %ebx
movslq %ebx, %rdx
salq $2, %rdx
movl $1, %ecx
movq 8(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl 96(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 88(%rsp), %rdx
movq 100(%rsp), %rdi
movl 108(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L48
.L34:
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movq 64(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaEventElapsedTime@PLT
movss 52(%rsp), %xmm0
divss .LC15(%rip), %xmm0
movss %xmm0, 52(%rsp)
addl %r14d, %r15d
movslq %r15d, %rax
movq (%rsp), %rdi
cmpq %rdi, %rax
jge .L44
.L30:
movl 20(%rsp), %eax
cmpl $-1, %eax
je .L35
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
comiss 52(%rsp), %xmm0
ja .L35
movq 40(%rsp), %rbx
jmp .L29
.L47:
movl (%rsp), %r14d
subl %r15d, %r14d
movq 72(%rsp), %rdi
call cudaFree@PLT
leal (%r14,%r14,2), %esi
movslq %esi, %rsi
salq $2, %rsi
movq 32(%rsp), %rdi
call cudaMalloc@PLT
jmp .L31
.L48:
movl %ebx, %edx
movq 80(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z29__device_stub__Z7examinePfPiiPfPii
jmp .L34
.L44:
movq 40(%rsp), %rbx
.L29:
movq 56(%rsp), %rdi
call cudaEventDestroy@PLT
movq 64(%rsp), %rdi
call cudaEventDestroy@PLT
movl $2, %ecx
movl $4, %edx
movq 80(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtss2sd 52(%rsp), %xmm0
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 52(%rsp), %xmm0
movq (%rsp), %rax
movq %rax, %r8
movss .LC17(%rip), %xmm1
comiss %xmm0, %xmm1
ja .L36
cvttss2sil %xmm0, %ecx
movslq %ecx, %rcx
cqto
idivq %rcx
movq %rax, %r8
.L36:
movl (%rbx), %ecx
movq (%rsp), %rdx
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call fclose@PLT
movq 8(%rsp), %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movl $0, %eax
.L21:
movq 1144(%rsp), %rdx
subq %fs:40, %rdx
jne .L49
addq $1160, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
movl $1, %eax
jmp .L21
.L40:
movl $4, %eax
jmp .L21
.L49:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC19:
.string "_Z7examinePfPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z7examinePfPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC15:
.long 1148846080
.align 4
.LC17:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#define LSIZE 31
#define MIN_LIM 12.0
#define MAX_LIM 30.0
void check_input(int argc,char* argv[]);
__global__ void examine(float *d_coordinates,int *d_coords_within,int d_lines);
long calc_lines(char *filename);
int main(int argc,char * argv[])
{
check_input(argc,argv); // Check cmd inputs
char *filename=argv[3]; // Variable initialization
int coll = atoi(argv[1]);
int exec_time=atoi(argv[2]);
int threads=atoi(argv[4]);
int BLOCKSIZE = atoi(argv[5]);
long loop_count;
loop_count =calc_lines(filename); // Count the lines of input file
FILE *input=fopen(filename,"r"); // Open file with file descriptor
struct cudaDeviceProp prop;
cudaGetDeviceProperties(&prop,0); // Get gpu's properties information
if(coll != -1) // Handle max_collisions argument
{
if(coll>loop_count)
{
printf("[!] Warning: Specified collisions to be tested exceed the ones in input file\n");
printf("[!] Setting the number of collisions to the maximum (taken from input file)\n");
}
else
{
if (coll<0) return 1;
loop_count = coll;
}
}
if (BLOCKSIZE==-1) // Handle blocksize argument
{
BLOCKSIZE=512; // A default value
}
else
{
if (BLOCKSIZE%prop.warpSize!=0 || BLOCKSIZE<=0)
{
printf("[-]Block_size must be a positive multiple of gpu's warp_size %d \n",prop.warpSize );
return 5;
}
}
if (threads!=-1) // Handle threads argument
{
if (threads<=0) return 4;
if (threads%BLOCKSIZE!=0)
{
threads=(threads/BLOCKSIZE)*BLOCKSIZE;
}
}
else
{
threads=prop.maxThreadsPerMultiProcessor*prop.multiProcessorCount;
}
// Print some information [ Usefull for debugging ]
printf("[+] GPU-model: %s\tTotal GPU memory %ld MB \n",prop.name,prop.totalGlobalMem/(1024*1024) );
printf("[!] You are trying to allocate %ld MBs of memmory on CPU-RAM and GPU-GlobalMem\n",threads*3*sizeof(float)/(1024*1024) );
printf("[+] Launching %d GPU-Threads with BlockSize %d\n",threads,BLOCKSIZE );
// Initialize CUDA WallClock-time counters as events
cudaEvent_t start,stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
dim3 blockSize(BLOCKSIZE); // Declare CUDA Block size explicitly
dim3 gridSize(threads/BLOCKSIZE); // Declare CUDA Grid size explicitly
float *h_coordinates=(float * )malloc(3*threads*sizeof(float)); // allocate Host memmory for elements to be read from file
float *d_coordinates;
int *d_coords_within,*h_coords_within=(int*)malloc(sizeof(int)); // allocate Host memmory for the counter of coordinates in area of interest
*h_coords_within=0;
// Allocate memmory on CUDA capable Device for:
cudaMalloc(&d_coordinates,3*threads*sizeof(float)); // input file's coordinates
cudaMalloc(&d_coords_within,sizeof(int)); // coordinates counter
cudaMemcpy(d_coords_within,h_coords_within,sizeof(int),cudaMemcpyHostToDevice); // Initialize the value of cuounter on Device
int i,j=0;
float time_elapsed = 0;
printf("[+] Working...\n" );
cudaEventRecord(start); // Starting time reference
while(j<loop_count && (exec_time==-1?1:time_elapsed<exec_time)) // Main loop of the programm
{
if (j+threads>loop_count)
{
threads=loop_count-j;
cudaFree(d_coordinates);
cudaMalloc(&d_coordinates,3*threads*sizeof(float));
}
for(i=0;i<threads;i++)
{
fscanf(input,"%f %f %f",&h_coordinates[i*3],&h_coordinates[i*3+1],&h_coordinates[i*3+2]); // Read cooordinates from file
}
cudaMemcpy(d_coordinates,h_coordinates,3*threads*sizeof(float),cudaMemcpyHostToDevice); // Copy read cooordinates on Device
examine<<<gridSize,blockSize>>>(d_coordinates,d_coords_within,3*threads); // Launch gpu kernel for calculations
cudaEventRecord(stop); // Stop time reference
cudaEventSynchronize(stop); // Block CPU until "stop" event is recorded
cudaEventElapsedTime(&time_elapsed, start, stop); // Calculate the time elapsed in milliseconds
time_elapsed=time_elapsed/1000; // Convert milliseconds to seconds
j+=threads;
}
// Destroy CUDA timers
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaMemcpy(h_coords_within,d_coords_within,sizeof(int),cudaMemcpyDeviceToHost); // Copy results from Device to Host
//Printing results
printf("[+] Main part of the program was being executed for :: %.3f :: sec)\n", time_elapsed);
printf("[+] %ld coordinates have been analyzed\n[+] %d cooordinates were inside the area of interest\n[+] %ld coordinates read per second\n", loop_count, *h_coords_within, (time_elapsed<1?loop_count:loop_count/(int)time_elapsed));
// Free Host and Device memory
cudaFree(d_coordinates);
cudaFree(d_coords_within);
fclose(input);
free(h_coordinates);
free(h_coords_within);
return 0;
}
__global__ void examine(float *d_coordinates,int *d_coords_within,int d_lines)
{
int index=blockIdx.x*3*blockDim.x+3*threadIdx.x; // find the index of starting element for each thread on each block
float coord1=d_coordinates[index],coord2=d_coordinates[index+1],coord3=d_coordinates[index+2]; // Copy cooordinates from GPU's global memory to thread's local memory
if(index>=d_lines) return;
if(coord1 >= MIN_LIM && coord1 <= MAX_LIM && coord2 >= MIN_LIM && coord2 <= MAX_LIM && coord3 >= MIN_LIM && coord3 <= MAX_LIM)
{
// If the current coordinate is within the accepted limits,
atomicAdd((unsigned int*)d_coords_within,1); // So as threads do not mess up the values
}
}
void check_input(int argc,char *argv[]) // Handle number of arguments errors and show usage
{
if (argc<6 || argc>6)
{
printf("[-] Usage: ./examine [max_collisions] [max_exec_time] [input_file] [Threads] [1D_blockSize]\nUse \"-1\": for no boundies \n");
if (argc==2) if (!strcmp(argv[1],"--help"))
{
printf("max_collisions: Maximum number of collisions\nmax_exec_time: Maximum execution time\ninput_file: Filename to examine\nThreads: Number of gpu-threads to use / # Rows in memmory\n1D_blocksize: gpu-blocksize to use" );
printf("\t ======Usefull info!======\n");
printf("1) 1D_blockSize must be a multiple of 32. (or whatever warp_size is supported by your GPU)\n2) Threads should be a multiple of blockSize\n 3)These 2 parameters are important for performance\n" );
}
exit(2);
}
}
long calc_lines(char *filename) // Calculates the lines of input file
{
FILE *file=fopen(filename,"r");
fseek(file,0L,SEEK_END); //set file position indicator right to the end-of-file
long lines=ftell(file); //store the number of bytes since the beginning of the file
fseek(file,0L,SEEK_SET);
fclose(file);
return lines/LSIZE; //return lines count of the file
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#define LSIZE 31
#define MIN_LIM 12.0
#define MAX_LIM 30.0
void check_input(int argc,char* argv[]);
__global__ void examine(float *d_coordinates,int *d_coords_within,int d_lines);
long calc_lines(char *filename);
int main(int argc,char * argv[])
{
check_input(argc,argv); // Check cmd inputs
char *filename=argv[3]; // Variable initialization
int coll = atoi(argv[1]);
int exec_time=atoi(argv[2]);
int threads=atoi(argv[4]);
int BLOCKSIZE = atoi(argv[5]);
long loop_count;
loop_count =calc_lines(filename); // Count the lines of input file
FILE *input=fopen(filename,"r"); // Open file with file descriptor
struct hipDeviceProp_t prop;
hipGetDeviceProperties(&prop,0); // Get gpu's properties information
if(coll != -1) // Handle max_collisions argument
{
if(coll>loop_count)
{
printf("[!] Warning: Specified collisions to be tested exceed the ones in input file\n");
printf("[!] Setting the number of collisions to the maximum (taken from input file)\n");
}
else
{
if (coll<0) return 1;
loop_count = coll;
}
}
if (BLOCKSIZE==-1) // Handle blocksize argument
{
BLOCKSIZE=512; // A default value
}
else
{
if (BLOCKSIZE%prop.warpSize!=0 || BLOCKSIZE<=0)
{
printf("[-]Block_size must be a positive multiple of gpu's warp_size %d \n",prop.warpSize );
return 5;
}
}
if (threads!=-1) // Handle threads argument
{
if (threads<=0) return 4;
if (threads%BLOCKSIZE!=0)
{
threads=(threads/BLOCKSIZE)*BLOCKSIZE;
}
}
else
{
threads=prop.maxThreadsPerMultiProcessor*prop.multiProcessorCount;
}
// Print some information [ Usefull for debugging ]
printf("[+] GPU-model: %s\tTotal GPU memory %ld MB \n",prop.name,prop.totalGlobalMem/(1024*1024) );
printf("[!] You are trying to allocate %ld MBs of memmory on CPU-RAM and GPU-GlobalMem\n",threads*3*sizeof(float)/(1024*1024) );
printf("[+] Launching %d GPU-Threads with BlockSize %d\n",threads,BLOCKSIZE );
// Initialize CUDA WallClock-time counters as events
hipEvent_t start,stop;
hipEventCreate(&start);
hipEventCreate(&stop);
dim3 blockSize(BLOCKSIZE); // Declare CUDA Block size explicitly
dim3 gridSize(threads/BLOCKSIZE); // Declare CUDA Grid size explicitly
float *h_coordinates=(float * )malloc(3*threads*sizeof(float)); // allocate Host memmory for elements to be read from file
float *d_coordinates;
int *d_coords_within,*h_coords_within=(int*)malloc(sizeof(int)); // allocate Host memmory for the counter of coordinates in area of interest
*h_coords_within=0;
// Allocate memmory on CUDA capable Device for:
hipMalloc(&d_coordinates,3*threads*sizeof(float)); // input file's coordinates
hipMalloc(&d_coords_within,sizeof(int)); // coordinates counter
hipMemcpy(d_coords_within,h_coords_within,sizeof(int),hipMemcpyHostToDevice); // Initialize the value of cuounter on Device
int i,j=0;
float time_elapsed = 0;
printf("[+] Working...\n" );
hipEventRecord(start); // Starting time reference
while(j<loop_count && (exec_time==-1?1:time_elapsed<exec_time)) // Main loop of the programm
{
if (j+threads>loop_count)
{
threads=loop_count-j;
hipFree(d_coordinates);
hipMalloc(&d_coordinates,3*threads*sizeof(float));
}
for(i=0;i<threads;i++)
{
fscanf(input,"%f %f %f",&h_coordinates[i*3],&h_coordinates[i*3+1],&h_coordinates[i*3+2]); // Read cooordinates from file
}
hipMemcpy(d_coordinates,h_coordinates,3*threads*sizeof(float),hipMemcpyHostToDevice); // Copy read cooordinates on Device
examine<<<gridSize,blockSize>>>(d_coordinates,d_coords_within,3*threads); // Launch gpu kernel for calculations
hipEventRecord(stop); // Stop time reference
hipEventSynchronize(stop); // Block CPU until "stop" event is recorded
hipEventElapsedTime(&time_elapsed, start, stop); // Calculate the time elapsed in milliseconds
time_elapsed=time_elapsed/1000; // Convert milliseconds to seconds
j+=threads;
}
// Destroy CUDA timers
hipEventDestroy(start);
hipEventDestroy(stop);
hipMemcpy(h_coords_within,d_coords_within,sizeof(int),hipMemcpyDeviceToHost); // Copy results from Device to Host
//Printing results
printf("[+] Main part of the program was being executed for :: %.3f :: sec)\n", time_elapsed);
printf("[+] %ld coordinates have been analyzed\n[+] %d cooordinates were inside the area of interest\n[+] %ld coordinates read per second\n", loop_count, *h_coords_within, (time_elapsed<1?loop_count:loop_count/(int)time_elapsed));
// Free Host and Device memory
hipFree(d_coordinates);
hipFree(d_coords_within);
fclose(input);
free(h_coordinates);
free(h_coords_within);
return 0;
}
__global__ void examine(float *d_coordinates,int *d_coords_within,int d_lines)
{
int index=blockIdx.x*3*blockDim.x+3*threadIdx.x; // find the index of starting element for each thread on each block
float coord1=d_coordinates[index],coord2=d_coordinates[index+1],coord3=d_coordinates[index+2]; // Copy cooordinates from GPU's global memory to thread's local memory
if(index>=d_lines) return;
if(coord1 >= MIN_LIM && coord1 <= MAX_LIM && coord2 >= MIN_LIM && coord2 <= MAX_LIM && coord3 >= MIN_LIM && coord3 <= MAX_LIM)
{
// If the current coordinate is within the accepted limits,
atomicAdd((unsigned int*)d_coords_within,1); // So as threads do not mess up the values
}
}
void check_input(int argc,char *argv[]) // Handle number of arguments errors and show usage
{
if (argc<6 || argc>6)
{
printf("[-] Usage: ./examine [max_collisions] [max_exec_time] [input_file] [Threads] [1D_blockSize]\nUse \"-1\": for no boundies \n");
if (argc==2) if (!strcmp(argv[1],"--help"))
{
printf("max_collisions: Maximum number of collisions\nmax_exec_time: Maximum execution time\ninput_file: Filename to examine\nThreads: Number of gpu-threads to use / # Rows in memmory\n1D_blocksize: gpu-blocksize to use" );
printf("\t ======Usefull info!======\n");
printf("1) 1D_blockSize must be a multiple of 32. (or whatever warp_size is supported by your GPU)\n2) Threads should be a multiple of blockSize\n 3)These 2 parameters are important for performance\n" );
}
exit(2);
}
}
long calc_lines(char *filename) // Calculates the lines of input file
{
FILE *file=fopen(filename,"r");
fseek(file,0L,SEEK_END); //set file position indicator right to the end-of-file
long lines=ftell(file); //store the number of bytes since the beginning of the file
fseek(file,0L,SEEK_SET);
fclose(file);
return lines/LSIZE; //return lines count of the file
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#define LSIZE 31
#define MIN_LIM 12.0
#define MAX_LIM 30.0
void check_input(int argc,char* argv[]);
__global__ void examine(float *d_coordinates,int *d_coords_within,int d_lines);
long calc_lines(char *filename);
int main(int argc,char * argv[])
{
check_input(argc,argv); // Check cmd inputs
char *filename=argv[3]; // Variable initialization
int coll = atoi(argv[1]);
int exec_time=atoi(argv[2]);
int threads=atoi(argv[4]);
int BLOCKSIZE = atoi(argv[5]);
long loop_count;
loop_count =calc_lines(filename); // Count the lines of input file
FILE *input=fopen(filename,"r"); // Open file with file descriptor
struct hipDeviceProp_t prop;
hipGetDeviceProperties(&prop,0); // Get gpu's properties information
if(coll != -1) // Handle max_collisions argument
{
if(coll>loop_count)
{
printf("[!] Warning: Specified collisions to be tested exceed the ones in input file\n");
printf("[!] Setting the number of collisions to the maximum (taken from input file)\n");
}
else
{
if (coll<0) return 1;
loop_count = coll;
}
}
if (BLOCKSIZE==-1) // Handle blocksize argument
{
BLOCKSIZE=512; // A default value
}
else
{
if (BLOCKSIZE%prop.warpSize!=0 || BLOCKSIZE<=0)
{
printf("[-]Block_size must be a positive multiple of gpu's warp_size %d \n",prop.warpSize );
return 5;
}
}
if (threads!=-1) // Handle threads argument
{
if (threads<=0) return 4;
if (threads%BLOCKSIZE!=0)
{
threads=(threads/BLOCKSIZE)*BLOCKSIZE;
}
}
else
{
threads=prop.maxThreadsPerMultiProcessor*prop.multiProcessorCount;
}
// Print some information [ Usefull for debugging ]
printf("[+] GPU-model: %s\tTotal GPU memory %ld MB \n",prop.name,prop.totalGlobalMem/(1024*1024) );
printf("[!] You are trying to allocate %ld MBs of memmory on CPU-RAM and GPU-GlobalMem\n",threads*3*sizeof(float)/(1024*1024) );
printf("[+] Launching %d GPU-Threads with BlockSize %d\n",threads,BLOCKSIZE );
// Initialize CUDA WallClock-time counters as events
hipEvent_t start,stop;
hipEventCreate(&start);
hipEventCreate(&stop);
dim3 blockSize(BLOCKSIZE); // Declare CUDA Block size explicitly
dim3 gridSize(threads/BLOCKSIZE); // Declare CUDA Grid size explicitly
float *h_coordinates=(float * )malloc(3*threads*sizeof(float)); // allocate Host memmory for elements to be read from file
float *d_coordinates;
int *d_coords_within,*h_coords_within=(int*)malloc(sizeof(int)); // allocate Host memmory for the counter of coordinates in area of interest
*h_coords_within=0;
// Allocate memmory on CUDA capable Device for:
hipMalloc(&d_coordinates,3*threads*sizeof(float)); // input file's coordinates
hipMalloc(&d_coords_within,sizeof(int)); // coordinates counter
hipMemcpy(d_coords_within,h_coords_within,sizeof(int),hipMemcpyHostToDevice); // Initialize the value of cuounter on Device
int i,j=0;
float time_elapsed = 0;
printf("[+] Working...\n" );
hipEventRecord(start); // Starting time reference
while(j<loop_count && (exec_time==-1?1:time_elapsed<exec_time)) // Main loop of the programm
{
if (j+threads>loop_count)
{
threads=loop_count-j;
hipFree(d_coordinates);
hipMalloc(&d_coordinates,3*threads*sizeof(float));
}
for(i=0;i<threads;i++)
{
fscanf(input,"%f %f %f",&h_coordinates[i*3],&h_coordinates[i*3+1],&h_coordinates[i*3+2]); // Read cooordinates from file
}
hipMemcpy(d_coordinates,h_coordinates,3*threads*sizeof(float),hipMemcpyHostToDevice); // Copy read cooordinates on Device
examine<<<gridSize,blockSize>>>(d_coordinates,d_coords_within,3*threads); // Launch gpu kernel for calculations
hipEventRecord(stop); // Stop time reference
hipEventSynchronize(stop); // Block CPU until "stop" event is recorded
hipEventElapsedTime(&time_elapsed, start, stop); // Calculate the time elapsed in milliseconds
time_elapsed=time_elapsed/1000; // Convert milliseconds to seconds
j+=threads;
}
// Destroy CUDA timers
hipEventDestroy(start);
hipEventDestroy(stop);
hipMemcpy(h_coords_within,d_coords_within,sizeof(int),hipMemcpyDeviceToHost); // Copy results from Device to Host
//Printing results
printf("[+] Main part of the program was being executed for :: %.3f :: sec)\n", time_elapsed);
printf("[+] %ld coordinates have been analyzed\n[+] %d cooordinates were inside the area of interest\n[+] %ld coordinates read per second\n", loop_count, *h_coords_within, (time_elapsed<1?loop_count:loop_count/(int)time_elapsed));
// Free Host and Device memory
hipFree(d_coordinates);
hipFree(d_coords_within);
fclose(input);
free(h_coordinates);
free(h_coords_within);
return 0;
}
__global__ void examine(float *d_coordinates,int *d_coords_within,int d_lines)
{
int index=blockIdx.x*3*blockDim.x+3*threadIdx.x; // find the index of starting element for each thread on each block
float coord1=d_coordinates[index],coord2=d_coordinates[index+1],coord3=d_coordinates[index+2]; // Copy cooordinates from GPU's global memory to thread's local memory
if(index>=d_lines) return;
if(coord1 >= MIN_LIM && coord1 <= MAX_LIM && coord2 >= MIN_LIM && coord2 <= MAX_LIM && coord3 >= MIN_LIM && coord3 <= MAX_LIM)
{
// If the current coordinate is within the accepted limits,
atomicAdd((unsigned int*)d_coords_within,1); // So as threads do not mess up the values
}
}
void check_input(int argc,char *argv[]) // Handle number of arguments errors and show usage
{
if (argc<6 || argc>6)
{
printf("[-] Usage: ./examine [max_collisions] [max_exec_time] [input_file] [Threads] [1D_blockSize]\nUse \"-1\": for no boundies \n");
if (argc==2) if (!strcmp(argv[1],"--help"))
{
printf("max_collisions: Maximum number of collisions\nmax_exec_time: Maximum execution time\ninput_file: Filename to examine\nThreads: Number of gpu-threads to use / # Rows in memmory\n1D_blocksize: gpu-blocksize to use" );
printf("\t ======Usefull info!======\n");
printf("1) 1D_blockSize must be a multiple of 32. (or whatever warp_size is supported by your GPU)\n2) Threads should be a multiple of blockSize\n 3)These 2 parameters are important for performance\n" );
}
exit(2);
}
}
long calc_lines(char *filename) // Calculates the lines of input file
{
FILE *file=fopen(filename,"r");
fseek(file,0L,SEEK_END); //set file position indicator right to the end-of-file
long lines=ftell(file); //store the number of bytes since the beginning of the file
fseek(file,0L,SEEK_SET);
fclose(file);
return lines/LSIZE; //return lines count of the file
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7examinePfPii
.globl _Z7examinePfPii
.p2align 8
.type _Z7examinePfPii,@function
_Z7examinePfPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_lshl_add_u32 v0, v1, 1, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB0_4
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b96 v[0:2], v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_le_f32_e32 vcc_lo, 0x41400000, v0
v_cmp_le_f32_e64 s2, 0x41400000, v1
v_cmp_ge_f32_e64 s3, 0x41f00000, v0
v_cmp_ge_f32_e64 s4, 0x41f00000, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
s_and_b32 s2, vcc_lo, s2
v_cmp_le_f32_e32 vcc_lo, 0x41400000, v2
s_and_b32 s3, s2, s3
v_cmp_ge_f32_e64 s2, 0x41f00000, v2
s_and_b32 s3, s3, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s3, s3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_4
s_mov_b32 s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mbcnt_lo_u32_b32 v0, s2, 0
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_and_b32 s3, exec_lo, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 exec_lo, s3
s_cbranch_execz .LBB0_4
s_load_b64 s[0:1], s[0:1], 0x8
s_bcnt1_i32_b32 s2, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7examinePfPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7examinePfPii, .Lfunc_end0-_Z7examinePfPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7examinePfPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7examinePfPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#define LSIZE 31
#define MIN_LIM 12.0
#define MAX_LIM 30.0
void check_input(int argc,char* argv[]);
__global__ void examine(float *d_coordinates,int *d_coords_within,int d_lines);
long calc_lines(char *filename);
int main(int argc,char * argv[])
{
check_input(argc,argv); // Check cmd inputs
char *filename=argv[3]; // Variable initialization
int coll = atoi(argv[1]);
int exec_time=atoi(argv[2]);
int threads=atoi(argv[4]);
int BLOCKSIZE = atoi(argv[5]);
long loop_count;
loop_count =calc_lines(filename); // Count the lines of input file
FILE *input=fopen(filename,"r"); // Open file with file descriptor
struct hipDeviceProp_t prop;
hipGetDeviceProperties(&prop,0); // Get gpu's properties information
if(coll != -1) // Handle max_collisions argument
{
if(coll>loop_count)
{
printf("[!] Warning: Specified collisions to be tested exceed the ones in input file\n");
printf("[!] Setting the number of collisions to the maximum (taken from input file)\n");
}
else
{
if (coll<0) return 1;
loop_count = coll;
}
}
if (BLOCKSIZE==-1) // Handle blocksize argument
{
BLOCKSIZE=512; // A default value
}
else
{
if (BLOCKSIZE%prop.warpSize!=0 || BLOCKSIZE<=0)
{
printf("[-]Block_size must be a positive multiple of gpu's warp_size %d \n",prop.warpSize );
return 5;
}
}
if (threads!=-1) // Handle threads argument
{
if (threads<=0) return 4;
if (threads%BLOCKSIZE!=0)
{
threads=(threads/BLOCKSIZE)*BLOCKSIZE;
}
}
else
{
threads=prop.maxThreadsPerMultiProcessor*prop.multiProcessorCount;
}
// Print some information [ Usefull for debugging ]
printf("[+] GPU-model: %s\tTotal GPU memory %ld MB \n",prop.name,prop.totalGlobalMem/(1024*1024) );
printf("[!] You are trying to allocate %ld MBs of memmory on CPU-RAM and GPU-GlobalMem\n",threads*3*sizeof(float)/(1024*1024) );
printf("[+] Launching %d GPU-Threads with BlockSize %d\n",threads,BLOCKSIZE );
// Initialize CUDA WallClock-time counters as events
hipEvent_t start,stop;
hipEventCreate(&start);
hipEventCreate(&stop);
dim3 blockSize(BLOCKSIZE); // Declare CUDA Block size explicitly
dim3 gridSize(threads/BLOCKSIZE); // Declare CUDA Grid size explicitly
float *h_coordinates=(float * )malloc(3*threads*sizeof(float)); // allocate Host memmory for elements to be read from file
float *d_coordinates;
int *d_coords_within,*h_coords_within=(int*)malloc(sizeof(int)); // allocate Host memmory for the counter of coordinates in area of interest
*h_coords_within=0;
// Allocate memmory on CUDA capable Device for:
hipMalloc(&d_coordinates,3*threads*sizeof(float)); // input file's coordinates
hipMalloc(&d_coords_within,sizeof(int)); // coordinates counter
hipMemcpy(d_coords_within,h_coords_within,sizeof(int),hipMemcpyHostToDevice); // Initialize the value of cuounter on Device
int i,j=0;
float time_elapsed = 0;
printf("[+] Working...\n" );
hipEventRecord(start); // Starting time reference
while(j<loop_count && (exec_time==-1?1:time_elapsed<exec_time)) // Main loop of the programm
{
if (j+threads>loop_count)
{
threads=loop_count-j;
hipFree(d_coordinates);
hipMalloc(&d_coordinates,3*threads*sizeof(float));
}
for(i=0;i<threads;i++)
{
fscanf(input,"%f %f %f",&h_coordinates[i*3],&h_coordinates[i*3+1],&h_coordinates[i*3+2]); // Read cooordinates from file
}
hipMemcpy(d_coordinates,h_coordinates,3*threads*sizeof(float),hipMemcpyHostToDevice); // Copy read cooordinates on Device
examine<<<gridSize,blockSize>>>(d_coordinates,d_coords_within,3*threads); // Launch gpu kernel for calculations
hipEventRecord(stop); // Stop time reference
hipEventSynchronize(stop); // Block CPU until "stop" event is recorded
hipEventElapsedTime(&time_elapsed, start, stop); // Calculate the time elapsed in milliseconds
time_elapsed=time_elapsed/1000; // Convert milliseconds to seconds
j+=threads;
}
// Destroy CUDA timers
hipEventDestroy(start);
hipEventDestroy(stop);
hipMemcpy(h_coords_within,d_coords_within,sizeof(int),hipMemcpyDeviceToHost); // Copy results from Device to Host
//Printing results
printf("[+] Main part of the program was being executed for :: %.3f :: sec)\n", time_elapsed);
printf("[+] %ld coordinates have been analyzed\n[+] %d cooordinates were inside the area of interest\n[+] %ld coordinates read per second\n", loop_count, *h_coords_within, (time_elapsed<1?loop_count:loop_count/(int)time_elapsed));
// Free Host and Device memory
hipFree(d_coordinates);
hipFree(d_coords_within);
fclose(input);
free(h_coordinates);
free(h_coords_within);
return 0;
}
__global__ void examine(float *d_coordinates,int *d_coords_within,int d_lines)
{
int index=blockIdx.x*3*blockDim.x+3*threadIdx.x; // find the index of starting element for each thread on each block
float coord1=d_coordinates[index],coord2=d_coordinates[index+1],coord3=d_coordinates[index+2]; // Copy cooordinates from GPU's global memory to thread's local memory
if(index>=d_lines) return;
if(coord1 >= MIN_LIM && coord1 <= MAX_LIM && coord2 >= MIN_LIM && coord2 <= MAX_LIM && coord3 >= MIN_LIM && coord3 <= MAX_LIM)
{
// If the current coordinate is within the accepted limits,
atomicAdd((unsigned int*)d_coords_within,1); // So as threads do not mess up the values
}
}
void check_input(int argc,char *argv[]) // Handle number of arguments errors and show usage
{
if (argc<6 || argc>6)
{
printf("[-] Usage: ./examine [max_collisions] [max_exec_time] [input_file] [Threads] [1D_blockSize]\nUse \"-1\": for no boundies \n");
if (argc==2) if (!strcmp(argv[1],"--help"))
{
printf("max_collisions: Maximum number of collisions\nmax_exec_time: Maximum execution time\ninput_file: Filename to examine\nThreads: Number of gpu-threads to use / # Rows in memmory\n1D_blocksize: gpu-blocksize to use" );
printf("\t ======Usefull info!======\n");
printf("1) 1D_blockSize must be a multiple of 32. (or whatever warp_size is supported by your GPU)\n2) Threads should be a multiple of blockSize\n 3)These 2 parameters are important for performance\n" );
}
exit(2);
}
}
long calc_lines(char *filename) // Calculates the lines of input file
{
FILE *file=fopen(filename,"r");
fseek(file,0L,SEEK_END); //set file position indicator right to the end-of-file
long lines=ftell(file); //store the number of bytes since the beginning of the file
fseek(file,0L,SEEK_SET);
fclose(file);
return lines/LSIZE; //return lines count of the file
} | .text
.file "examine.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x447a0000 # float 1000
.LCPI0_1:
.long 0x3f800000 # float 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1656, %rsp # imm = 0x678
.cfi_def_cfa_offset 1712
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
cmpl $6, %edi
jne .LBB0_1
# %bb.5: # %_Z11check_inputiPPc.exit
movq 8(%r14), %rdi
movq 24(%r14), %rbx
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 72(%rsp) # 8-byte Spill
movq 32(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 40(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbp
movl $.L.str, %esi
movq %rbx, %rdi
callq fopen
movq %rax, %r14
movq %rax, %rdi
xorl %esi, %esi
movl $2, %edx
callq fseek
movq %r14, %rdi
callq ftell
movq %rax, %r12
movq %r14, %rdi
xorl %esi, %esi
xorl %edx, %edx
callq fseek
movq %r14, %rdi
callq fclose
movabsq $-8925843906633654007, %rcx # imm = 0x8421084210842109
movq %r12, %rax
imulq %rcx
movq %rdx, %r14
addq %r12, %r14
movq %r14, %rax
shrq $63, %rax
sarq $4, %r14
addq %rax, %r14
movl $.L.str, %esi
movq %rbx, %rdi
callq fopen
movq %rax, %rbx
leaq 184(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
cmpl $-1, %r13d
je .LBB0_8
# %bb.6:
movslq %r13d, %r12
cmpq %r12, %r14
jge .LBB0_14
# %bb.7:
movl $.Lstr, %edi
callq puts@PLT
movl $.Lstr.1, %edi
callq puts@PLT
.LBB0_8:
movq %r14, %r12
jmp .LBB0_9
.LBB0_14:
testl %r13d, %r13d
js .LBB0_15
.LBB0_9:
cmpl $-1, %ebp
je .LBB0_10
# %bb.16:
movl 492(%rsp), %esi
movl %ebp, %eax
cltd
idivl %esi
testl %ebp, %ebp
jle .LBB0_18
# %bb.17:
testl %edx, %edx
jne .LBB0_18
# %bb.11:
cmpl $-1, %r15d
je .LBB0_20
.LBB0_12:
testl %r15d, %r15d
jle .LBB0_13
# %bb.19:
movl %r15d, %eax
xorl %edx, %edx
divl %ebp
subl %edx, %r15d
jmp .LBB0_21
.LBB0_10:
movl $512, %ebp # imm = 0x200
cmpl $-1, %r15d
jne .LBB0_12
.LBB0_20:
movl 572(%rsp), %r15d
imull 808(%rsp), %r15d
.LBB0_21:
movq 472(%rsp), %rdx
shrq $20, %rdx
leaq 184(%rsp), %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
leal (%r15,%r15,2), %eax
movslq %eax, %r14
shlq $2, %r14
movq %r14, %rsi
shrq $20, %rsi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl $.L.str.6, %edi
movl %r15d, %esi
movl %ebp, %edx
xorl %eax, %eax
callq printf
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 32(%rsp), %rdi
callq hipEventCreate
movl %r15d, %eax
cltd
idivl %ebp
# kill: def $eax killed $eax def $rax
movq %rax, 64(%rsp) # 8-byte Spill
movq %r14, %rdi
callq malloc
movq %rax, 40(%rsp) # 8-byte Spill
movl $4, %edi
callq malloc
movq %rax, %r13
movl $0, (%rax)
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 24(%rsp), %rdi
movl $4, %edx
movq %r13, 80(%rsp) # 8-byte Spill
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
movl $0, 12(%rsp)
movl $.Lstr.2, %edi
callq puts@PLT
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testq %r12, %r12
jle .LBB0_33
# %bb.22: # %.lr.ph102
movl %ebp, %ecx
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rcx
movq %rcx, 88(%rsp) # 8-byte Spill
addq %rax, 64(%rsp) # 8-byte Folded Spill
cvtsi2ssl 72(%rsp), %xmm0 # 4-byte Folded Reload
movss %xmm0, 56(%rsp) # 4-byte Spill
xorl %ebp, %ebp
jmp .LBB0_23
.p2align 4, 0x90
.LBB0_32: # in Loop: Header=BB0_23 Depth=1
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rdi
callq hipEventSynchronize
movq 48(%rsp), %rsi
movq 32(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI0_0(%rip), %xmm0
movss %xmm0, 12(%rsp)
addl %r15d, %ebp
movslq %ebp, %rax
cmpq %rax, %r12
jle .LBB0_33
.LBB0_23: # =>This Loop Header: Depth=1
# Child Loop BB0_29 Depth 2
cmpl $-1, 72(%rsp) # 4-byte Folded Reload
je .LBB0_25
# %bb.24: # in Loop: Header=BB0_23 Depth=1
movss 56(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
ucomiss 12(%rsp), %xmm0
jbe .LBB0_33
.LBB0_25: # in Loop: Header=BB0_23 Depth=1
leal (%r15,%rbp), %eax
cltq
cmpq %rax, %r12
jge .LBB0_27
# %bb.26: # in Loop: Header=BB0_23 Depth=1
movl %r12d, %r15d
subl %ebp, %r15d
movq 16(%rsp), %rdi
callq hipFree
leal (%r15,%r15,2), %eax
movslq %eax, %rsi
shlq $2, %rsi
leaq 16(%rsp), %rdi
callq hipMalloc
.LBB0_27: # in Loop: Header=BB0_23 Depth=1
testl %r15d, %r15d
jle .LBB0_30
# %bb.28: # %.lr.ph.preheader
# in Loop: Header=BB0_23 Depth=1
movl %r15d, %r14d
movq 40(%rsp), %r13 # 8-byte Reload
.p2align 4, 0x90
.LBB0_29: # %.lr.ph
# Parent Loop BB0_23 Depth=1
# => This Inner Loop Header: Depth=2
leaq 4(%r13), %rcx
leaq 8(%r13), %r8
movl $.L.str.8, %esi
movq %rbx, %rdi
movq %r13, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
addq $12, %r13
decq %r14
jne .LBB0_29
.LBB0_30: # %._crit_edge
# in Loop: Header=BB0_23 Depth=1
movq 16(%rsp), %rdi
leal (%r15,%r15,2), %r13d
movslq %r13d, %rdx
shlq $2, %rdx
movq 40(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movq 64(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movq 88(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_32
# %bb.31: # in Loop: Header=BB0_23 Depth=1
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movl %r13d, 60(%rsp)
leaq 152(%rsp), %rax
movq %rax, 160(%rsp)
leaq 144(%rsp), %rax
movq %rax, 168(%rsp)
leaq 60(%rsp), %rax
movq %rax, 176(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
movl $_Z7examinePfPii, %edi
leaq 160(%rsp), %r9
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB0_32
.LBB0_33: # %.critedge
movq 48(%rsp), %rdi
callq hipEventDestroy
movq 32(%rsp), %rdi
callq hipEventDestroy
movq 24(%rsp), %rsi
movl $4, %edx
movq 80(%rsp), %r14 # 8-byte Reload
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.9, %edi
movb $1, %al
callq printf
movl (%r14), %ecx
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI0_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
movq %r12, %rax
ja .LBB0_35
# %bb.34:
cvttss2si %xmm0, %eax
movslq %eax, %rsi
movq %r12, %rax
cqto
idivq %rsi
.LBB0_35:
xorl %ebp, %ebp
movl $.L.str.10, %edi
movq %r12, %rsi
movl %ecx, %edx
movq %rax, %rcx
xorl %eax, %eax
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq fclose
movq 40(%rsp), %rdi # 8-byte Reload
callq free
movq %r14, %rdi
callq free
jmp .LBB0_36
.LBB0_18:
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl $5, %ebp
jmp .LBB0_36
.LBB0_13:
movl $4, %ebp
jmp .LBB0_36
.LBB0_15:
movl $1, %ebp
.LBB0_36:
movl %ebp, %eax
addq $1656, %rsp # imm = 0x678
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_1:
.cfi_def_cfa_offset 1712
movl %edi, %ebx
movl $.Lstr.3, %edi
callq puts@PLT
cmpl $2, %ebx
jne .LBB0_4
# %bb.2:
movq 8(%r14), %rdi
movl $.L.str.12, %esi
callq strcmp
testl %eax, %eax
jne .LBB0_4
# %bb.3:
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
movl $.Lstr.4, %edi
callq puts@PLT
movl $.Lstr.5, %edi
callq puts@PLT
.LBB0_4:
movl $2, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z11check_inputiPPc # -- Begin function _Z11check_inputiPPc
.p2align 4, 0x90
.type _Z11check_inputiPPc,@function
_Z11check_inputiPPc: # @_Z11check_inputiPPc
.cfi_startproc
# %bb.0:
cmpl $6, %edi
jne .LBB1_1
# %bb.5:
retq
.LBB1_1:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
movl $.Lstr.3, %edi
callq puts@PLT
cmpl $2, %ebp
jne .LBB1_4
# %bb.2:
movq 8(%rbx), %rdi
movl $.L.str.12, %esi
callq strcmp
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
movl $.Lstr.4, %edi
callq puts@PLT
movl $.Lstr.5, %edi
callq puts@PLT
.LBB1_4:
movl $2, %edi
callq exit
.Lfunc_end1:
.size _Z11check_inputiPPc, .Lfunc_end1-_Z11check_inputiPPc
.cfi_endproc
# -- End function
.globl _Z10calc_linesPc # -- Begin function _Z10calc_linesPc
.p2align 4, 0x90
.type _Z10calc_linesPc,@function
_Z10calc_linesPc: # @_Z10calc_linesPc
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $.L.str, %esi
callq fopen
movq %rax, %rbx
movq %rax, %rdi
xorl %esi, %esi
movl $2, %edx
callq fseek
movq %rbx, %rdi
callq ftell
movq %rax, %r14
movq %rbx, %rdi
xorl %esi, %esi
xorl %edx, %edx
callq fseek
movq %rbx, %rdi
callq fclose
movabsq $-8925843906633654007, %rcx # imm = 0x8421084210842109
movq %r14, %rax
imulq %rcx
addq %rdx, %r14
movq %r14, %rax
shrq $63, %rax
sarq $4, %r14
addq %rax, %r14
movq %r14, %rax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z10calc_linesPc, .Lfunc_end2-_Z10calc_linesPc
.cfi_endproc
# -- End function
.globl _Z22__device_stub__examinePfPii # -- Begin function _Z22__device_stub__examinePfPii
.p2align 4, 0x90
.type _Z22__device_stub__examinePfPii,@function
_Z22__device_stub__examinePfPii: # @_Z22__device_stub__examinePfPii
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7examinePfPii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z22__device_stub__examinePfPii, .Lfunc_end3-_Z22__device_stub__examinePfPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7examinePfPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r"
.size .L.str, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "[-]Block_size must be a positive multiple of gpu's warp_size %d \n"
.size .L.str.3, 66
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "[+] GPU-model: %s\tTotal GPU memory %ld MB \n"
.size .L.str.4, 44
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "[!] You are trying to allocate %ld MBs of memmory on CPU-RAM and GPU-GlobalMem\n"
.size .L.str.5, 80
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "[+] Launching %d GPU-Threads with BlockSize %d\n"
.size .L.str.6, 48
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%f %f %f"
.size .L.str.8, 9
.type _Z7examinePfPii,@object # @_Z7examinePfPii
.section .rodata,"a",@progbits
.globl _Z7examinePfPii
.p2align 3, 0x0
_Z7examinePfPii:
.quad _Z22__device_stub__examinePfPii
.size _Z7examinePfPii, 8
.type .L.str.9,@object # @.str.9
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.9:
.asciz "[+] Main part of the program was being executed for :: %.3f :: sec)\n"
.size .L.str.9, 69
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "[+] %ld coordinates have been analyzed\n[+] %d cooordinates were inside the area of interest\n[+] %ld coordinates read per second\n"
.size .L.str.10, 129
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "--help"
.size .L.str.12, 7
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "max_collisions: Maximum number of collisions\nmax_exec_time: Maximum execution time\ninput_file: Filename to examine\nThreads: Number of gpu-threads to use / # Rows in memmory\n1D_blocksize: gpu-blocksize to use"
.size .L.str.13, 208
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7examinePfPii"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "[!] Warning: Specified collisions to be tested exceed the ones in input file"
.size .Lstr, 77
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "[!] Setting the number of collisions to the maximum (taken from input file)"
.size .Lstr.1, 76
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "[+] Working..."
.size .Lstr.2, 15
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "[-] Usage: ./examine [max_collisions] [max_exec_time] [input_file] [Threads] [1D_blockSize]\nUse \"-1\": for no boundies "
.size .Lstr.3, 119
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "\t ======Usefull info!======"
.size .Lstr.4, 28
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "1) 1D_blockSize must be a multiple of 32. (or whatever warp_size is supported by your GPU)\n2) Threads should be a multiple of blockSize\n 3)These 2 parameters are important for performance"
.size .Lstr.5, 188
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__examinePfPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7examinePfPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7examinePfPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0040*/ IMAD R0, R0, 0x3, RZ ; /* 0x0000000300007824 */
/* 0x000fca00078e02ff */
/*0050*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0090*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*00a0*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R0, [R2.64+0x4] ; /* 0x0000040402007981 */
/* 0x000ee8000c1e1900 */
/*00c0*/ LDG.E R4, [R2.64+0x8] ; /* 0x0000080402047981 */
/* 0x000f22000c1e1900 */
/*00d0*/ FSETP.GTU.AND P0, PT, R5, 30, PT ; /* 0x41f000000500780b */
/* 0x004fc80003f0c000 */
/*00e0*/ FSETP.LTU.OR P0, PT, R5, 12, P0 ; /* 0x414000000500780b */
/* 0x000fc80000709400 */
/*00f0*/ FSETP.LTU.OR P0, PT, R0, 12, P0 ; /* 0x414000000000780b */
/* 0x008fc80000709400 */
/*0100*/ FSETP.GTU.OR P0, PT, R0, 30, P0 ; /* 0x41f000000000780b */
/* 0x000fc8000070c400 */
/*0110*/ FSETP.LTU.OR P0, PT, R4, 12, P0 ; /* 0x414000000400780b */
/* 0x010fc80000709400 */
/*0120*/ FSETP.GTU.OR P0, PT, R4, 30, P0 ; /* 0x41f000000400780b */
/* 0x000fda000070c400 */
/*0130*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0140*/ S2R R0, SR_LANEID ; /* 0x0000000000007919 */
/* 0x000e220000000000 */
/*0150*/ VOTEU.ANY UR6, UPT, PT ; /* 0x0000000000067886 */
/* 0x000fe200038e0100 */
/*0160*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe200078e00ff */
/*0170*/ UFLO.U32 UR7, UR6 ; /* 0x00000006000772bd */
/* 0x000fe200080e0000 */
/*0180*/ POPC R5, UR6 ; /* 0x0000000600057d09 */
/* 0x000e620008000000 */
/*0190*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fc800078e00ff */
/*01a0*/ ISETP.EQ.U32.AND P0, PT, R0, UR7, PT ; /* 0x0000000700007c0c */
/* 0x001fda000bf02070 */
/*01b0*/ @P0 RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200098e */
/* 0x002fe2000c10e184 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7examinePfPii
.globl _Z7examinePfPii
.p2align 8
.type _Z7examinePfPii,@function
_Z7examinePfPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_lshl_add_u32 v0, v1, 1, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB0_4
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b96 v[0:2], v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_le_f32_e32 vcc_lo, 0x41400000, v0
v_cmp_le_f32_e64 s2, 0x41400000, v1
v_cmp_ge_f32_e64 s3, 0x41f00000, v0
v_cmp_ge_f32_e64 s4, 0x41f00000, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
s_and_b32 s2, vcc_lo, s2
v_cmp_le_f32_e32 vcc_lo, 0x41400000, v2
s_and_b32 s3, s2, s3
v_cmp_ge_f32_e64 s2, 0x41f00000, v2
s_and_b32 s3, s3, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s3, s3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_4
s_mov_b32 s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mbcnt_lo_u32_b32 v0, s2, 0
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_and_b32 s3, exec_lo, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 exec_lo, s3
s_cbranch_execz .LBB0_4
s_load_b64 s[0:1], s[0:1], 0x8
s_bcnt1_i32_b32 s2, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7examinePfPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7examinePfPii, .Lfunc_end0-_Z7examinePfPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7examinePfPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7examinePfPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000936b8_00000000-6_examine.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "[-] Usage: ./examine [max_collisions] [max_exec_time] [input_file] [Threads] [1D_blockSize]\nUse \"-1\": for no boundies \n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "--help"
.section .rodata.str1.8
.align 8
.LC2:
.string "max_collisions: Maximum number of collisions\nmax_exec_time: Maximum execution time\ninput_file: Filename to examine\nThreads: Number of gpu-threads to use / # Rows in memmory\n1D_blocksize: gpu-blocksize to use"
.section .rodata.str1.1
.LC3:
.string "\t ======Usefull info!======\n"
.section .rodata.str1.8
.align 8
.LC4:
.string "1) 1D_blockSize must be a multiple of 32. (or whatever warp_size is supported by your GPU)\n2) Threads should be a multiple of blockSize\n 3)These 2 parameters are important for performance\n"
.text
.globl _Z11check_inputiPPc
.type _Z11check_inputiPPc, @function
_Z11check_inputiPPc:
.LFB2058:
.cfi_startproc
endbr64
cmpl $6, %edi
jne .L9
ret
.L9:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl %edi, %ebx
movq %rsi, %rbp
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $2, %ebx
je .L10
.L5:
movl $2, %edi
call exit@PLT
.L10:
movq 8(%rbp), %rdi
leaq .LC1(%rip), %rsi
call strcmp@PLT
testl %eax, %eax
jne .L5
leaq .LC2(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L5
.cfi_endproc
.LFE2058:
.size _Z11check_inputiPPc, .-_Z11check_inputiPPc
.section .rodata.str1.1
.LC5:
.string "r"
.text
.globl _Z10calc_linesPc
.type _Z10calc_linesPc, @function
_Z10calc_linesPc:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
leaq .LC5(%rip), %rsi
call fopen@PLT
movq %rax, %rbp
movl $2, %edx
movl $0, %esi
movq %rax, %rdi
call fseek@PLT
movq %rbp, %rdi
call ftell@PLT
movq %rax, %rbx
movl $0, %edx
movl $0, %esi
movq %rbp, %rdi
call fseek@PLT
movq %rbp, %rdi
call fclose@PLT
movabsq $-8925843906633654007, %rdx
movq %rbx, %rax
imulq %rdx
leaq (%rdx,%rbx), %rax
sarq $4, %rax
sarq $63, %rbx
subq %rbx, %rax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z10calc_linesPc, .-_Z10calc_linesPc
.globl _Z29__device_stub__Z7examinePfPiiPfPii
.type _Z29__device_stub__Z7examinePfPiiPfPii, @function
_Z29__device_stub__Z7examinePfPiiPfPii:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7examinePfPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z29__device_stub__Z7examinePfPiiPfPii, .-_Z29__device_stub__Z7examinePfPiiPfPii
.globl _Z7examinePfPii
.type _Z7examinePfPii, @function
_Z7examinePfPii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7examinePfPiiPfPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z7examinePfPii, .-_Z7examinePfPii
.section .rodata.str1.8
.align 8
.LC6:
.string "[!] Warning: Specified collisions to be tested exceed the ones in input file\n"
.align 8
.LC7:
.string "[!] Setting the number of collisions to the maximum (taken from input file)\n"
.align 8
.LC8:
.string "[-]Block_size must be a positive multiple of gpu's warp_size %d \n"
.align 8
.LC9:
.string "[+] GPU-model: %s\tTotal GPU memory %ld MB \n"
.align 8
.LC10:
.string "[!] You are trying to allocate %ld MBs of memmory on CPU-RAM and GPU-GlobalMem\n"
.align 8
.LC11:
.string "[+] Launching %d GPU-Threads with BlockSize %d\n"
.section .rodata.str1.1
.LC13:
.string "[+] Working...\n"
.LC14:
.string "%f %f %f"
.section .rodata.str1.8
.align 8
.LC16:
.string "[+] Main part of the program was being executed for :: %.3f :: sec)\n"
.align 8
.LC18:
.string "[+] %ld coordinates have been analyzed\n[+] %d cooordinates were inside the area of interest\n[+] %ld coordinates read per second\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1160, %rsp
.cfi_def_cfa_offset 1216
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 1144(%rsp)
xorl %eax, %eax
call _Z11check_inputiPPc
movq 24(%rbx), %r12
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r14
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
movq 32(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movq 40(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movl %eax, %ebx
movq %r12, %rdi
call _Z10calc_linesPc
movq %rax, (%rsp)
leaq .LC5(%rip), %rsi
movq %r12, %rdi
call fopen@PLT
movq %rax, %r12
leaq 112(%rsp), %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
cmpl $-1, %r14d
je .L22
movslq %r14d, %rax
movq (%rsp), %rsi
cmpq %rsi, %rax
jg .L46
testl %r14d, %r14d
js .L38
movq %rax, (%rsp)
.L22:
cmpl $-1, %ebp
je .L39
movl 420(%rsp), %ecx
movl %ebx, %eax
cltd
idivl %ecx
testl %edx, %edx
jne .L42
testl %ebp, %ebp
jle .L42
.L25:
movl %r13d, %r14d
cmpl $-1, %r13d
je .L27
testl %r13d, %r13d
jle .L40
movl %r13d, %eax
cltd
idivl %ebx
testl %edx, %edx
je .L28
movl %r13d, %eax
cltd
idivl %ebx
movl %eax, %r14d
imull %ebx, %r14d
jmp .L28
.L46:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L22
.L42:
movl %ecx, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $5, %eax
jmp .L21
.L39:
movl $512, %ebx
jmp .L25
.L27:
movl 736(%rsp), %r14d
imull 500(%rsp), %r14d
.L28:
movq 400(%rsp), %rcx
shrq $20, %rcx
leaq 112(%rsp), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
imull $3, %r14d, %ebp
movslq %ebp, %rbp
salq $2, %rbp
movq %rbp, %rdx
shrq $20, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %ecx
movl %r14d, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
movl %ebx, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl %r14d, %eax
cltd
idivl %ebx
movl %eax, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movq %rbp, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movl $4, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, (%rax)
leaq 72(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 80(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4, %edx
movq %rbx, %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl $0x00000000, 52(%rsp)
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
cmpq $0, (%rsp)
jle .L29
movl %r15d, 20(%rsp)
movl $0, %r15d
leaq 72(%rsp), %rax
movq %rax, 32(%rsp)
leaq .LC14(%rip), %r13
leaq 52(%rsp), %rax
movq %rax, 24(%rsp)
movq %rbx, 40(%rsp)
jmp .L30
.L35:
leal (%r14,%r15), %eax
cltq
movq (%rsp), %rsi
cmpq %rsi, %rax
jg .L47
.L31:
testl %r14d, %r14d
jle .L32
movq 8(%rsp), %rdx
movq %rdx, %rbx
movslq %r14d, %rax
leaq (%rax,%rax,2), %rax
leaq (%rdx,%rax,4), %rbp
.L33:
leaq 4(%rbx), %rcx
leaq 8(%rbx), %r8
movq %rbx, %rdx
movq %r13, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $12, %rbx
cmpq %rbp, %rbx
jne .L33
.L32:
leal (%r14,%r14,2), %ebx
movslq %ebx, %rdx
salq $2, %rdx
movl $1, %ecx
movq 8(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl 96(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 88(%rsp), %rdx
movq 100(%rsp), %rdi
movl 108(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L48
.L34:
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movq 64(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaEventElapsedTime@PLT
movss 52(%rsp), %xmm0
divss .LC15(%rip), %xmm0
movss %xmm0, 52(%rsp)
addl %r14d, %r15d
movslq %r15d, %rax
movq (%rsp), %rdi
cmpq %rdi, %rax
jge .L44
.L30:
movl 20(%rsp), %eax
cmpl $-1, %eax
je .L35
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
comiss 52(%rsp), %xmm0
ja .L35
movq 40(%rsp), %rbx
jmp .L29
.L47:
movl (%rsp), %r14d
subl %r15d, %r14d
movq 72(%rsp), %rdi
call cudaFree@PLT
leal (%r14,%r14,2), %esi
movslq %esi, %rsi
salq $2, %rsi
movq 32(%rsp), %rdi
call cudaMalloc@PLT
jmp .L31
.L48:
movl %ebx, %edx
movq 80(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z29__device_stub__Z7examinePfPiiPfPii
jmp .L34
.L44:
movq 40(%rsp), %rbx
.L29:
movq 56(%rsp), %rdi
call cudaEventDestroy@PLT
movq 64(%rsp), %rdi
call cudaEventDestroy@PLT
movl $2, %ecx
movl $4, %edx
movq 80(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtss2sd 52(%rsp), %xmm0
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 52(%rsp), %xmm0
movq (%rsp), %rax
movq %rax, %r8
movss .LC17(%rip), %xmm1
comiss %xmm0, %xmm1
ja .L36
cvttss2sil %xmm0, %ecx
movslq %ecx, %rcx
cqto
idivq %rcx
movq %rax, %r8
.L36:
movl (%rbx), %ecx
movq (%rsp), %rdx
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call fclose@PLT
movq 8(%rsp), %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movl $0, %eax
.L21:
movq 1144(%rsp), %rdx
subq %fs:40, %rdx
jne .L49
addq $1160, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
movl $1, %eax
jmp .L21
.L40:
movl $4, %eax
jmp .L21
.L49:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC19:
.string "_Z7examinePfPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z7examinePfPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC15:
.long 1148846080
.align 4
.LC17:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "examine.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x447a0000 # float 1000
.LCPI0_1:
.long 0x3f800000 # float 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1656, %rsp # imm = 0x678
.cfi_def_cfa_offset 1712
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
cmpl $6, %edi
jne .LBB0_1
# %bb.5: # %_Z11check_inputiPPc.exit
movq 8(%r14), %rdi
movq 24(%r14), %rbx
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 72(%rsp) # 8-byte Spill
movq 32(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 40(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbp
movl $.L.str, %esi
movq %rbx, %rdi
callq fopen
movq %rax, %r14
movq %rax, %rdi
xorl %esi, %esi
movl $2, %edx
callq fseek
movq %r14, %rdi
callq ftell
movq %rax, %r12
movq %r14, %rdi
xorl %esi, %esi
xorl %edx, %edx
callq fseek
movq %r14, %rdi
callq fclose
movabsq $-8925843906633654007, %rcx # imm = 0x8421084210842109
movq %r12, %rax
imulq %rcx
movq %rdx, %r14
addq %r12, %r14
movq %r14, %rax
shrq $63, %rax
sarq $4, %r14
addq %rax, %r14
movl $.L.str, %esi
movq %rbx, %rdi
callq fopen
movq %rax, %rbx
leaq 184(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
cmpl $-1, %r13d
je .LBB0_8
# %bb.6:
movslq %r13d, %r12
cmpq %r12, %r14
jge .LBB0_14
# %bb.7:
movl $.Lstr, %edi
callq puts@PLT
movl $.Lstr.1, %edi
callq puts@PLT
.LBB0_8:
movq %r14, %r12
jmp .LBB0_9
.LBB0_14:
testl %r13d, %r13d
js .LBB0_15
.LBB0_9:
cmpl $-1, %ebp
je .LBB0_10
# %bb.16:
movl 492(%rsp), %esi
movl %ebp, %eax
cltd
idivl %esi
testl %ebp, %ebp
jle .LBB0_18
# %bb.17:
testl %edx, %edx
jne .LBB0_18
# %bb.11:
cmpl $-1, %r15d
je .LBB0_20
.LBB0_12:
testl %r15d, %r15d
jle .LBB0_13
# %bb.19:
movl %r15d, %eax
xorl %edx, %edx
divl %ebp
subl %edx, %r15d
jmp .LBB0_21
.LBB0_10:
movl $512, %ebp # imm = 0x200
cmpl $-1, %r15d
jne .LBB0_12
.LBB0_20:
movl 572(%rsp), %r15d
imull 808(%rsp), %r15d
.LBB0_21:
movq 472(%rsp), %rdx
shrq $20, %rdx
leaq 184(%rsp), %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
leal (%r15,%r15,2), %eax
movslq %eax, %r14
shlq $2, %r14
movq %r14, %rsi
shrq $20, %rsi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl $.L.str.6, %edi
movl %r15d, %esi
movl %ebp, %edx
xorl %eax, %eax
callq printf
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 32(%rsp), %rdi
callq hipEventCreate
movl %r15d, %eax
cltd
idivl %ebp
# kill: def $eax killed $eax def $rax
movq %rax, 64(%rsp) # 8-byte Spill
movq %r14, %rdi
callq malloc
movq %rax, 40(%rsp) # 8-byte Spill
movl $4, %edi
callq malloc
movq %rax, %r13
movl $0, (%rax)
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 24(%rsp), %rdi
movl $4, %edx
movq %r13, 80(%rsp) # 8-byte Spill
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
movl $0, 12(%rsp)
movl $.Lstr.2, %edi
callq puts@PLT
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testq %r12, %r12
jle .LBB0_33
# %bb.22: # %.lr.ph102
movl %ebp, %ecx
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rcx
movq %rcx, 88(%rsp) # 8-byte Spill
addq %rax, 64(%rsp) # 8-byte Folded Spill
cvtsi2ssl 72(%rsp), %xmm0 # 4-byte Folded Reload
movss %xmm0, 56(%rsp) # 4-byte Spill
xorl %ebp, %ebp
jmp .LBB0_23
.p2align 4, 0x90
.LBB0_32: # in Loop: Header=BB0_23 Depth=1
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rdi
callq hipEventSynchronize
movq 48(%rsp), %rsi
movq 32(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI0_0(%rip), %xmm0
movss %xmm0, 12(%rsp)
addl %r15d, %ebp
movslq %ebp, %rax
cmpq %rax, %r12
jle .LBB0_33
.LBB0_23: # =>This Loop Header: Depth=1
# Child Loop BB0_29 Depth 2
cmpl $-1, 72(%rsp) # 4-byte Folded Reload
je .LBB0_25
# %bb.24: # in Loop: Header=BB0_23 Depth=1
movss 56(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
ucomiss 12(%rsp), %xmm0
jbe .LBB0_33
.LBB0_25: # in Loop: Header=BB0_23 Depth=1
leal (%r15,%rbp), %eax
cltq
cmpq %rax, %r12
jge .LBB0_27
# %bb.26: # in Loop: Header=BB0_23 Depth=1
movl %r12d, %r15d
subl %ebp, %r15d
movq 16(%rsp), %rdi
callq hipFree
leal (%r15,%r15,2), %eax
movslq %eax, %rsi
shlq $2, %rsi
leaq 16(%rsp), %rdi
callq hipMalloc
.LBB0_27: # in Loop: Header=BB0_23 Depth=1
testl %r15d, %r15d
jle .LBB0_30
# %bb.28: # %.lr.ph.preheader
# in Loop: Header=BB0_23 Depth=1
movl %r15d, %r14d
movq 40(%rsp), %r13 # 8-byte Reload
.p2align 4, 0x90
.LBB0_29: # %.lr.ph
# Parent Loop BB0_23 Depth=1
# => This Inner Loop Header: Depth=2
leaq 4(%r13), %rcx
leaq 8(%r13), %r8
movl $.L.str.8, %esi
movq %rbx, %rdi
movq %r13, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
addq $12, %r13
decq %r14
jne .LBB0_29
.LBB0_30: # %._crit_edge
# in Loop: Header=BB0_23 Depth=1
movq 16(%rsp), %rdi
leal (%r15,%r15,2), %r13d
movslq %r13d, %rdx
shlq $2, %rdx
movq 40(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movq 64(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movq 88(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_32
# %bb.31: # in Loop: Header=BB0_23 Depth=1
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movl %r13d, 60(%rsp)
leaq 152(%rsp), %rax
movq %rax, 160(%rsp)
leaq 144(%rsp), %rax
movq %rax, 168(%rsp)
leaq 60(%rsp), %rax
movq %rax, 176(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
movl $_Z7examinePfPii, %edi
leaq 160(%rsp), %r9
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB0_32
.LBB0_33: # %.critedge
movq 48(%rsp), %rdi
callq hipEventDestroy
movq 32(%rsp), %rdi
callq hipEventDestroy
movq 24(%rsp), %rsi
movl $4, %edx
movq 80(%rsp), %r14 # 8-byte Reload
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.9, %edi
movb $1, %al
callq printf
movl (%r14), %ecx
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI0_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
movq %r12, %rax
ja .LBB0_35
# %bb.34:
cvttss2si %xmm0, %eax
movslq %eax, %rsi
movq %r12, %rax
cqto
idivq %rsi
.LBB0_35:
xorl %ebp, %ebp
movl $.L.str.10, %edi
movq %r12, %rsi
movl %ecx, %edx
movq %rax, %rcx
xorl %eax, %eax
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq fclose
movq 40(%rsp), %rdi # 8-byte Reload
callq free
movq %r14, %rdi
callq free
jmp .LBB0_36
.LBB0_18:
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl $5, %ebp
jmp .LBB0_36
.LBB0_13:
movl $4, %ebp
jmp .LBB0_36
.LBB0_15:
movl $1, %ebp
.LBB0_36:
movl %ebp, %eax
addq $1656, %rsp # imm = 0x678
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_1:
.cfi_def_cfa_offset 1712
movl %edi, %ebx
movl $.Lstr.3, %edi
callq puts@PLT
cmpl $2, %ebx
jne .LBB0_4
# %bb.2:
movq 8(%r14), %rdi
movl $.L.str.12, %esi
callq strcmp
testl %eax, %eax
jne .LBB0_4
# %bb.3:
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
movl $.Lstr.4, %edi
callq puts@PLT
movl $.Lstr.5, %edi
callq puts@PLT
.LBB0_4:
movl $2, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z11check_inputiPPc # -- Begin function _Z11check_inputiPPc
.p2align 4, 0x90
.type _Z11check_inputiPPc,@function
_Z11check_inputiPPc: # @_Z11check_inputiPPc
.cfi_startproc
# %bb.0:
cmpl $6, %edi
jne .LBB1_1
# %bb.5:
retq
.LBB1_1:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
movl $.Lstr.3, %edi
callq puts@PLT
cmpl $2, %ebp
jne .LBB1_4
# %bb.2:
movq 8(%rbx), %rdi
movl $.L.str.12, %esi
callq strcmp
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
movl $.Lstr.4, %edi
callq puts@PLT
movl $.Lstr.5, %edi
callq puts@PLT
.LBB1_4:
movl $2, %edi
callq exit
.Lfunc_end1:
.size _Z11check_inputiPPc, .Lfunc_end1-_Z11check_inputiPPc
.cfi_endproc
# -- End function
.globl _Z10calc_linesPc # -- Begin function _Z10calc_linesPc
.p2align 4, 0x90
.type _Z10calc_linesPc,@function
_Z10calc_linesPc: # @_Z10calc_linesPc
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $.L.str, %esi
callq fopen
movq %rax, %rbx
movq %rax, %rdi
xorl %esi, %esi
movl $2, %edx
callq fseek
movq %rbx, %rdi
callq ftell
movq %rax, %r14
movq %rbx, %rdi
xorl %esi, %esi
xorl %edx, %edx
callq fseek
movq %rbx, %rdi
callq fclose
movabsq $-8925843906633654007, %rcx # imm = 0x8421084210842109
movq %r14, %rax
imulq %rcx
addq %rdx, %r14
movq %r14, %rax
shrq $63, %rax
sarq $4, %r14
addq %rax, %r14
movq %r14, %rax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z10calc_linesPc, .Lfunc_end2-_Z10calc_linesPc
.cfi_endproc
# -- End function
.globl _Z22__device_stub__examinePfPii # -- Begin function _Z22__device_stub__examinePfPii
.p2align 4, 0x90
.type _Z22__device_stub__examinePfPii,@function
_Z22__device_stub__examinePfPii: # @_Z22__device_stub__examinePfPii
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7examinePfPii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z22__device_stub__examinePfPii, .Lfunc_end3-_Z22__device_stub__examinePfPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7examinePfPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r"
.size .L.str, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "[-]Block_size must be a positive multiple of gpu's warp_size %d \n"
.size .L.str.3, 66
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "[+] GPU-model: %s\tTotal GPU memory %ld MB \n"
.size .L.str.4, 44
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "[!] You are trying to allocate %ld MBs of memmory on CPU-RAM and GPU-GlobalMem\n"
.size .L.str.5, 80
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "[+] Launching %d GPU-Threads with BlockSize %d\n"
.size .L.str.6, 48
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%f %f %f"
.size .L.str.8, 9
.type _Z7examinePfPii,@object # @_Z7examinePfPii
.section .rodata,"a",@progbits
.globl _Z7examinePfPii
.p2align 3, 0x0
_Z7examinePfPii:
.quad _Z22__device_stub__examinePfPii
.size _Z7examinePfPii, 8
.type .L.str.9,@object # @.str.9
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.9:
.asciz "[+] Main part of the program was being executed for :: %.3f :: sec)\n"
.size .L.str.9, 69
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "[+] %ld coordinates have been analyzed\n[+] %d cooordinates were inside the area of interest\n[+] %ld coordinates read per second\n"
.size .L.str.10, 129
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "--help"
.size .L.str.12, 7
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "max_collisions: Maximum number of collisions\nmax_exec_time: Maximum execution time\ninput_file: Filename to examine\nThreads: Number of gpu-threads to use / # Rows in memmory\n1D_blocksize: gpu-blocksize to use"
.size .L.str.13, 208
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7examinePfPii"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "[!] Warning: Specified collisions to be tested exceed the ones in input file"
.size .Lstr, 77
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "[!] Setting the number of collisions to the maximum (taken from input file)"
.size .Lstr.1, 76
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "[+] Working..."
.size .Lstr.2, 15
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "[-] Usage: ./examine [max_collisions] [max_exec_time] [input_file] [Threads] [1D_blockSize]\nUse \"-1\": for no boundies "
.size .Lstr.3, 119
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "\t ======Usefull info!======"
.size .Lstr.4, 28
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "1) 1D_blockSize must be a multiple of 32. (or whatever warp_size is supported by your GPU)\n2) Threads should be a multiple of blockSize\n 3)These 2 parameters are important for performance"
.size .Lstr.5, 188
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__examinePfPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7examinePfPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
__global__ void safty(int *a, int N,int arg)
{
int i = threadIdx.x + blockIdx.x*blockDim.x;
if(arg ==0)
{
if(i < N)
{
a[i] = 1;
}
}
else
{
if(i <N)
{
a[i]*=2;
printf("%d",a[i]);
}
}
}
int main()
{
int *a;
size_t size = 100;
int N = size*sizeof(int);
int thread = 32;
int block = (N-1)/thread +1;
cudaMallocManaged(&a,N);
safty<<<block,thread>>>(a,N,0);
safty<<<block,thread>>>(a,N,1);
cudaDeviceSynchronize();
cudaFree(a);
} | code for sm_80
Function : _Z5saftyPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x16c], PT ; /* 0x00005b00ff007a0c */
/* 0x000fe20003f05270 */
/*0030*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0080*/ IMAD.WIDE R8, R0, R9, c[0x0][0x160] ; /* 0x0000580000087625 */
/* 0x000fc800078e0209 */
/*0090*/ @!P0 BRA 0x1f0 ; /* 0x0000015000008947 */
/* 0x000fea0003800000 */
/*00a0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe40003f06270 */
/*00b0*/ IADD3 R6, P1, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fd60007f3e0ff */
/*00c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00d0*/ LDG.E R0, [R8.64] ; /* 0x0000000408007981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ MOV R2, 0x0 ; /* 0x0000000000027802 */
/* 0x000fe20000000f00 */
/*00f0*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P1 ; /* 0x00000900ff077624 */
/* 0x000fe400008e06ff */
/*0100*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe400078e00ff */
/*0110*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0120*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000e220000000a00 */
/*0130*/ IMAD.SHL.U32 R0, R0, 0x2, RZ ; /* 0x0000000200007824 */
/* 0x004fca00078e00ff */
/*0140*/ STG.E [R8.64], R0 ; /* 0x0000000008007986 */
/* 0x0003e8000c101904 */
/*0150*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0003e40000100800 */
/*0160*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x003fe40000000000 */
/*0170*/ MOV R11, 0x1e0 ; /* 0x000001e0000b7802 */
/* 0x000fe40000000f00 */
/*0180*/ MOV R20, 0x160 ; /* 0x0000016000147802 */
/* 0x000fe40000000f00 */
/*0190*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*01a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fc40000000f00 */
/*01b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*01c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*01d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x000fea0003c00000 */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0200*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0210*/ IMAD.MOV.U32 R3, RZ, RZ, 0x1 ; /* 0x00000001ff037424 */
/* 0x000fca00078e00ff */
/*0220*/ STG.E [R8.64], R3 ; /* 0x0000000308007986 */
/* 0x000fe2000c101904 */
/*0230*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0240*/ BRA 0x240; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
__global__ void safty(int *a, int N,int arg)
{
int i = threadIdx.x + blockIdx.x*blockDim.x;
if(arg ==0)
{
if(i < N)
{
a[i] = 1;
}
}
else
{
if(i <N)
{
a[i]*=2;
printf("%d",a[i]);
}
}
}
int main()
{
int *a;
size_t size = 100;
int N = size*sizeof(int);
int thread = 32;
int block = (N-1)/thread +1;
cudaMallocManaged(&a,N);
safty<<<block,thread>>>(a,N,0);
safty<<<block,thread>>>(a,N,1);
cudaDeviceSynchronize();
cudaFree(a);
} | .file "tmpxft_001930fc_00000000-6_instead_for.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z5saftyPiiiPiii
.type _Z26__device_stub__Z5saftyPiiiPiii, @function
_Z26__device_stub__Z5saftyPiiiPiii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z5saftyPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z5saftyPiiiPiii, .-_Z26__device_stub__Z5saftyPiiiPiii
.globl _Z5saftyPiii
.type _Z5saftyPiii, @function
_Z5saftyPiii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z5saftyPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5saftyPiii, .-_Z5saftyPiii
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $400, %esi
call cudaMallocManaged@PLT
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $13, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $13, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
call cudaDeviceSynchronize@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl $0, %edx
movl $400, %esi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z5saftyPiiiPiii
jmp .L12
.L17:
movl $1, %edx
movl $400, %esi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z5saftyPiiiPiii
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5saftyPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5saftyPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
__global__ void safty(int *a, int N,int arg)
{
int i = threadIdx.x + blockIdx.x*blockDim.x;
if(arg ==0)
{
if(i < N)
{
a[i] = 1;
}
}
else
{
if(i <N)
{
a[i]*=2;
printf("%d",a[i]);
}
}
}
int main()
{
int *a;
size_t size = 100;
int N = size*sizeof(int);
int thread = 32;
int block = (N-1)/thread +1;
cudaMallocManaged(&a,N);
safty<<<block,thread>>>(a,N,0);
safty<<<block,thread>>>(a,N,1);
cudaDeviceSynchronize();
cudaFree(a);
} | #include <hip/hip_runtime.h>
#include<stdio.h>
__global__ void safty(int *a, int N,int arg)
{
int i = threadIdx.x + blockIdx.x*blockDim.x;
if(arg ==0)
{
if(i < N)
{
a[i] = 1;
}
}
else
{
if(i <N)
{
a[i]*=2;
printf("%d",a[i]);
}
}
}
int main()
{
int *a;
size_t size = 100;
int N = size*sizeof(int);
int thread = 32;
int block = (N-1)/thread +1;
hipMallocManaged(&a,N);
safty<<<block,thread>>>(a,N,0);
safty<<<block,thread>>>(a,N,1);
hipDeviceSynchronize();
hipFree(a);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
__global__ void safty(int *a, int N,int arg)
{
int i = threadIdx.x + blockIdx.x*blockDim.x;
if(arg ==0)
{
if(i < N)
{
a[i] = 1;
}
}
else
{
if(i <N)
{
a[i]*=2;
printf("%d",a[i]);
}
}
}
int main()
{
int *a;
size_t size = 100;
int N = size*sizeof(int);
int thread = 32;
int block = (N-1)/thread +1;
hipMallocManaged(&a,N);
safty<<<block,thread>>>(a,N,0);
safty<<<block,thread>>>(a,N,1);
hipDeviceSynchronize();
hipFree(a);
} | .text
.file "instead_for.hip"
.globl _Z20__device_stub__saftyPiii # -- Begin function _Z20__device_stub__saftyPiii
.p2align 4, 0x90
.type _Z20__device_stub__saftyPiii,@function
_Z20__device_stub__saftyPiii: # @_Z20__device_stub__saftyPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z5saftyPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z20__device_stub__saftyPiii, .Lfunc_end0-_Z20__device_stub__saftyPiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movabsq $4294967309, %rbx # imm = 0x10000000D
leaq 16(%rsp), %rdi
movl $400, %esi # imm = 0x190
movl $1, %edx
callq hipMallocManaged
leaq 19(%rbx), %r14
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl $400, 12(%rsp) # imm = 0x190
movl $0, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5saftyPiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl $400, 12(%rsp) # imm = 0x190
movl $1, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5saftyPiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5saftyPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5saftyPiii,@object # @_Z5saftyPiii
.section .rodata,"a",@progbits
.globl _Z5saftyPiii
.p2align 3, 0x0
_Z5saftyPiii:
.quad _Z20__device_stub__saftyPiii
.size _Z5saftyPiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5saftyPiii"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__saftyPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5saftyPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001930fc_00000000-6_instead_for.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z5saftyPiiiPiii
.type _Z26__device_stub__Z5saftyPiiiPiii, @function
_Z26__device_stub__Z5saftyPiiiPiii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z5saftyPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z5saftyPiiiPiii, .-_Z26__device_stub__Z5saftyPiiiPiii
.globl _Z5saftyPiii
.type _Z5saftyPiii, @function
_Z5saftyPiii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z5saftyPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5saftyPiii, .-_Z5saftyPiii
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $400, %esi
call cudaMallocManaged@PLT
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $13, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $13, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
call cudaDeviceSynchronize@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl $0, %edx
movl $400, %esi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z5saftyPiiiPiii
jmp .L12
.L17:
movl $1, %edx
movl $400, %esi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z5saftyPiiiPiii
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5saftyPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5saftyPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "instead_for.hip"
.globl _Z20__device_stub__saftyPiii # -- Begin function _Z20__device_stub__saftyPiii
.p2align 4, 0x90
.type _Z20__device_stub__saftyPiii,@function
_Z20__device_stub__saftyPiii: # @_Z20__device_stub__saftyPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z5saftyPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z20__device_stub__saftyPiii, .Lfunc_end0-_Z20__device_stub__saftyPiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movabsq $4294967309, %rbx # imm = 0x10000000D
leaq 16(%rsp), %rdi
movl $400, %esi # imm = 0x190
movl $1, %edx
callq hipMallocManaged
leaq 19(%rbx), %r14
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl $400, 12(%rsp) # imm = 0x190
movl $0, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5saftyPiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl $400, 12(%rsp) # imm = 0x190
movl $1, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5saftyPiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5saftyPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5saftyPiii,@object # @_Z5saftyPiii
.section .rodata,"a",@progbits
.globl _Z5saftyPiii
.p2align 3, 0x0
_Z5saftyPiii:
.quad _Z20__device_stub__saftyPiii
.size _Z5saftyPiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5saftyPiii"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__saftyPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5saftyPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.