system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012b8a5_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z24multiplyNumbersByAScalarPffPff
.type _Z45__device_stub__Z24multiplyNumbersByAScalarPffPff, @function
_Z45__device_stub__Z24multiplyNumbersByAScalarPffPff:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z24multiplyNumbersByAScalarPff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z45__device_stub__Z24multiplyNumbersByAScalarPffPff, .-_Z45__device_stub__Z24multiplyNumbersByAScalarPffPff
.globl _Z24multiplyNumbersByAScalarPff
.type _Z24multiplyNumbersByAScalarPff, @function
_Z24multiplyNumbersByAScalarPff:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z24multiplyNumbersByAScalarPffPff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z24multiplyNumbersByAScalarPff, .-_Z24multiplyNumbersByAScalarPff
.section .rodata.str1.1,"aMS",@progbits,1
.LC10:
.string "%f "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $0x00000000, 32(%rsp)
movl $0x3f800000, 36(%rsp)
movl $0x40000000, 40(%rsp)
movl $0x40400000, 44(%rsp)
movl $0x40800000, 48(%rsp)
movl $0x40a00000, 52(%rsp)
movl $0x40c00000, 56(%rsp)
movl $0x40e00000, 60(%rsp)
movl $0x41000000, 64(%rsp)
movl $0x41100000, 68(%rsp)
movq %rsp, %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $10, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
leaq 32(%rsp), %rbx
movl $2, %ecx
movl $40, %edx
movq (%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
leaq 72(%rsp), %r12
leaq .LC10(%rip), %rbp
.L13:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L13
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $1, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movss .LC2(%rip), %xmm0
movq (%rsp), %rdi
call _Z45__device_stub__Z24multiplyNumbersByAScalarPffPff
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC11:
.string "_Z24multiplyNumbersByAScalarPff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z24multiplyNumbersByAScalarPff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z39__device_stub__multiplyNumbersByAScalarPff # -- Begin function _Z39__device_stub__multiplyNumbersByAScalarPff
.p2align 4, 0x90
.type _Z39__device_stub__multiplyNumbersByAScalarPff,@function
_Z39__device_stub__multiplyNumbersByAScalarPff: # @_Z39__device_stub__multiplyNumbersByAScalarPff
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movss %xmm0, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z24multiplyNumbersByAScalarPff, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z39__device_stub__multiplyNumbersByAScalarPff, .Lfunc_end0-_Z39__device_stub__multiplyNumbersByAScalarPff
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x00000000 # float 0
.long 0x3f800000 # float 1
.long 0x40000000 # float 2
.long 0x40400000 # float 3
.LCPI1_1:
.long 0x40800000 # float 4
.long 0x40a00000 # float 5
.long 0x40c00000 # float 6
.long 0x40e00000 # float 7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $144, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -16
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [0.0E+0,1.0E+0,2.0E+0,3.0E+0]
movaps %xmm0, 96(%rsp)
movaps .LCPI1_1(%rip), %xmm0 # xmm0 = [4.0E+0,5.0E+0,6.0E+0,7.0E+0]
movaps %xmm0, 112(%rsp)
movabsq $4688247213183205376, %rax # imm = 0x4110000041000000
movq %rax, 128(%rsp)
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 96(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 9(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $1073741824, 20(%rsp) # imm = 0x40000000
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z24multiplyNumbersByAScalarPff, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
leaq 96(%rsp), %rdi
movl $40, %edx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movss 96(%rsp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %rbx
cmpq $10, %rbx
jne .LBB1_3
# %bb.4:
movl $1, %eax
addq $144, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24multiplyNumbersByAScalarPff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24multiplyNumbersByAScalarPff,@object # @_Z24multiplyNumbersByAScalarPff
.section .rodata,"a",@progbits
.globl _Z24multiplyNumbersByAScalarPff
.p2align 3, 0x0
_Z24multiplyNumbersByAScalarPff:
.quad _Z39__device_stub__multiplyNumbersByAScalarPff
.size _Z24multiplyNumbersByAScalarPff, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z24multiplyNumbersByAScalarPff"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__multiplyNumbersByAScalarPff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24multiplyNumbersByAScalarPff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
void init(double **A, double **C1, double **C2, int dim) {
int i, j;
int size = dim * dim * sizeof(double);
*A = (double *) malloc(size);
srand(time(NULL));
for (i = 0; i < dim; i++) {
for (j = 0; j < dim; j++) {
(*A)[i * dim + j] = 1.0 + 1.0 * rand() / RAND_MAX;
}
}
*C1 = (double *) malloc(size);
memset(*C1, 0, size);
*C2 = (double *) malloc(size);
memset(*C2, 0, size);
}
void cleanup(double **A, double **C1, double **C2) {
free(*A);
free(*C1);
free(*C2);
}
double multiplyHost(double *A, double *C, int dim) {
int i, j, k;
clock_t clockStart;
clockStart = clock();
for (i = 0; i < dim; i++) {
for (j = 0; j < dim; j++) {
for (k = 0; k < dim; k++) {
C[i * dim + j] += A[k * dim + i] * A[k * dim + j];
}
}
}
double clockDiff = clock() - clockStart;
return clockDiff / 1000;
}
__global__ void multiplyKernel(double *A, double *C, int dim) {
int i, j, k;
i = blockIdx.x;
j = threadIdx.x;
for (k = 0; k < dim; k++) {
C[i * dim + j] += A[k * dim + i] * A[k * dim + j];
}
}
double multiplyDevice(double *A, double *C, int dim) {
double *dA, *dC;
int size = dim * dim * sizeof(double);
cudaMalloc((void **) &dA, size);
cudaMalloc((void **) &dC, size);
cudaMemcpy(dA, A, size, cudaMemcpyHostToDevice);
cudaMemcpy(dC, C, size, cudaMemcpyHostToDevice);
dim3 dimGrid(dim);
dim3 dimBlock(dim);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
multiplyKernel<<<dimGrid, dimBlock>>>(dA, dC, dim);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float diff = 0;
cudaEventElapsedTime(&diff, start, stop);
cudaMemcpy(C, dC, size, cudaMemcpyDeviceToHost);
cudaFree(dA);
cudaFree(dC);
return diff;
}
int match(double *C1, double *C2, int dim) {
int i, j, nError = 0;
for (i = 0; i < dim; i++) {
for (j = 0; j < dim; j++) {
if(fabs(C1[i * dim + j] - C2[i * dim + j]) > 0.000001) {
nError++;
}
}
}
return nError;
}
int main() {
int dim = 1024;
double *A, *CHost, *CDevice;
double nOp = 2.0 * dim * dim * dim;
init(&A, &CHost, &CDevice, dim);
double timeHost = multiplyHost(A, CHost, dim);
double flopsHost = 1000 * nOp / timeHost;
printf("Time taken on host (ms) = %lf\n", timeHost);
printf("FLOPS on host = %lf\n", flopsHost);
double timeDevice = multiplyDevice(A, CDevice, dim);
double flopsDevice = 1000 * nOp / timeDevice;
printf("Time taken on device (ms) = %lf\n", timeDevice);
printf("FLOPS on device = %lf\n", flopsDevice);
int err = match(CHost, CDevice, dim);
if(err > 0) {
printf("Results did not match. %d mismatches\n", err);
} else {
printf("Results matched.\n");
}
cleanup(&A, &CHost, &CDevice);
} | code for sm_80
Function : _Z14multiplyKernelPdS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R8, c[0x0][0x170] ; /* 0x00005c0000087a02 */
/* 0x000fc80000000f00 */
/*0020*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0050*/ IADD3 R0, R8, -0x1, RZ ; /* 0xffffffff08007810 */
/* 0x000fe20007ffe0ff */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0090*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe40003f06070 */
/*00a0*/ LOP3.LUT R8, R8, 0x3, RZ, 0xc0, !PT ; /* 0x0000000308087812 */
/* 0x000fe400078ec0ff */
/*00b0*/ MOV R0, RZ ; /* 0x000000ff00007202 */
/* 0x000fe20000000f00 */
/*00c0*/ IMAD R2, R5, c[0x0][0x170], R6 ; /* 0x00005c0005027a24 */
/* 0x001fc800078e0206 */
/*00d0*/ IMAD.WIDE R2, R2, R7, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fc800078e0207 */
/*00e0*/ @!P0 BRA 0xd10 ; /* 0x00000c2000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R4, -R8, c[0x0][0x170], RZ ; /* 0x00005c0008047a10 */
/* 0x000fe20007ffe1ff */
/*0100*/ LDG.E.64 R12, [R2.64] ; /* 0x00000004020c7981 */
/* 0x000162000c1e1b00 */
/*0110*/ MOV R0, RZ ; /* 0x000000ff00007202 */
/* 0x000fe20000000f00 */
/*0120*/ IMAD.WIDE R14, R5, R7, c[0x0][0x160] ; /* 0x00005800050e7625 */
/* 0x000fe200078e0207 */
/*0130*/ ISETP.GT.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f04270 */
/*0140*/ IMAD.WIDE R10, R6, R7, c[0x0][0x160] ; /* 0x00005800060a7625 */
/* 0x000fd400078e0207 */
/*0150*/ @!P0 BRA 0xb50 ; /* 0x000009f000008947 */
/* 0x001fea0003800000 */
/*0160*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe40003f24270 */
/*0170*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0180*/ @!P1 BRA 0x7e0 ; /* 0x0000065000009947 */
/* 0x000fea0003800000 */
/*0190*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01a0*/ LDG.E.64 R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x000ea8000c1e1b00 */
/*01b0*/ LDG.E.64 R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000ea2000c1e1b00 */
/*01c0*/ IMAD.WIDE R20, R7, c[0x0][0x170], R10 ; /* 0x00005c0007147a25 */
/* 0x002fe200078e020a */
/*01d0*/ DFMA R16, R16, R18, R12 ; /* 0x000000121010722b */
/* 0x024046000000000c */
/*01e0*/ IMAD.WIDE R18, R7, c[0x0][0x170], R14 ; /* 0x00005c0007127a25 */
/* 0x001fc800078e020e */
/*01f0*/ STG.E.64 [R2.64], R16 ; /* 0x0000001002007986 */
/* 0x0021e8000c101b04 */
/*0200*/ LDG.E.64 R12, [R20.64] ; /* 0x00000004140c7981 */
/* 0x000ea8000c1e1b00 */
/*0210*/ LDG.E.64 R22, [R18.64] ; /* 0x0000000412167981 */
/* 0x000ea2000c1e1b00 */
/*0220*/ IMAD.WIDE R24, R7, c[0x0][0x170], R18 ; /* 0x00005c0007187a25 */
/* 0x000fe200078e0212 */
/*0230*/ DFMA R22, R12, R22, R16 ; /* 0x000000160c16722b */
/* 0x0042860000000010 */
/*0240*/ IMAD.WIDE R12, R7, c[0x0][0x170], R20 ; /* 0x00005c00070c7a25 */
/* 0x002fc800078e0214 */
/*0250*/ STG.E.64 [R2.64], R22 ; /* 0x0000001602007986 */
/* 0x0043e8000c101b04 */
/*0260*/ LDG.E.64 R10, [R12.64] ; /* 0x000000040c0a7981 */
/* 0x000ea8000c1e1b00 */
/*0270*/ LDG.E.64 R14, [R24.64] ; /* 0x00000004180e7981 */
/* 0x000ea2000c1e1b00 */
/*0280*/ IMAD.WIDE R26, R7, c[0x0][0x170], R12 ; /* 0x00005c00071a7a25 */
/* 0x000fe200078e020c */
/*0290*/ DFMA R14, R10, R14, R22 ; /* 0x0000000e0a0e722b */
/* 0x0044c60000000016 */
/*02a0*/ IMAD.WIDE R10, R7, c[0x0][0x170], R24 ; /* 0x00005c00070a7a25 */
/* 0x004fc800078e0218 */
/*02b0*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0085e8000c101b04 */
/*02c0*/ LDG.E.64 R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000ee8000c1e1b00 */
/*02d0*/ LDG.E.64 R16, [R26.64] ; /* 0x000000041a107981 */
/* 0x001ee4000c1e1b00 */
/*02e0*/ DFMA R20, R16, R18, R14 ; /* 0x000000121014722b */
/* 0x0080c4000000000e */
/*02f0*/ IMAD.WIDE R18, R7, c[0x0][0x170], R26 ; /* 0x00005c0007127a25 */
/* 0x001fc800078e021a */
/*0300*/ IMAD.WIDE R16, R7.reuse, c[0x0][0x170], R10 ; /* 0x00005c0007107a25 */
/* 0x040fe200078e020a */
/*0310*/ STG.E.64 [R2.64], R20 ; /* 0x0000001402007986 */
/* 0x0081e8000c101b04 */
/*0320*/ LDG.E.64 R12, [R18.64] ; /* 0x00000004120c7981 */
/* 0x000ee8000c1e1b00 */
/*0330*/ LDG.E.64 R22, [R16.64] ; /* 0x0000000410167981 */
/* 0x002ee2000c1e1b00 */
/*0340*/ IMAD.WIDE R24, R7, c[0x0][0x170], R18 ; /* 0x00005c0007187a25 */
/* 0x000fc800078e0212 */
/*0350*/ IMAD.WIDE R14, R7, c[0x0][0x170], R16 ; /* 0x00005c00070e7a25 */
/* 0x004fe200078e0210 */
/*0360*/ DFMA R22, R12, R22, R20 ; /* 0x000000160c16722b */
/* 0x008e4e0000000014 */
/*0370*/ STG.E.64 [R2.64], R22 ; /* 0x0000001602007986 */
/* 0x0023e8000c101b04 */
/*0380*/ LDG.E.64 R10, [R24.64] ; /* 0x00000004180a7981 */
/* 0x000ea8000c1e1b00 */
/*0390*/ LDG.E.64 R12, [R14.64] ; /* 0x000000040e0c7981 */
/* 0x000ea2000c1e1b00 */
/*03a0*/ IMAD.WIDE R20, R7, c[0x0][0x170], R14 ; /* 0x00005c0007147a25 */
/* 0x001fe200078e020e */
/*03b0*/ DFMA R26, R10, R12, R22 ; /* 0x0000000c0a1a722b */
/* 0x0040860000000016 */
/*03c0*/ IMAD.WIDE R10, R7, c[0x0][0x170], R24 ; /* 0x00005c00070a7a25 */
/* 0x001fc800078e0218 */
/*03d0*/ STG.E.64 [R2.64], R26 ; /* 0x0000001a02007986 */
/* 0x0041e8000c101b04 */
/*03e0*/ LDG.E.64 R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x000ea8000c1e1b00 */
/*03f0*/ LDG.E.64 R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x000ea2000c1e1b00 */
/*0400*/ IMAD.WIDE R18, R7, c[0x0][0x170], R10 ; /* 0x00005c0007127a25 */
/* 0x000fe200078e020a */
/*0410*/ DFMA R16, R12, R16, R26 ; /* 0x000000100c10722b */
/* 0x0044c6000000001a */
/*0420*/ IMAD.WIDE R12, R7, c[0x0][0x170], R20 ; /* 0x00005c00070c7a25 */
/* 0x004fc800078e0214 */
/*0430*/ STG.E.64 [R2.64], R16 ; /* 0x0000001002007986 */
/* 0x0085e8000c101b04 */
/*0440*/ LDG.E.64 R22, [R12.64] ; /* 0x000000040c167981 */
/* 0x002ee8000c1e1b00 */
/*0450*/ LDG.E.64 R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x000ee4000c1e1b00 */
/*0460*/ DFMA R24, R14, R22, R16 ; /* 0x000000160e18722b */
/* 0x0082c40000000010 */
/*0470*/ IMAD.WIDE R22, R7, c[0x0][0x170], R18 ; /* 0x00005c0007167a25 */
/* 0x002fc800078e0212 */
/*0480*/ IMAD.WIDE R14, R7.reuse, c[0x0][0x170], R12 ; /* 0x00005c00070e7a25 */
/* 0x040fe200078e020c */
/*0490*/ STG.E.64 [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x0083e8000c101b04 */
/*04a0*/ LDG.E.64 R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000ee8000c1e1b00 */
/*04b0*/ LDG.E.64 R20, [R14.64] ; /* 0x000000040e147981 */
/* 0x000ee2000c1e1b00 */
/*04c0*/ IMAD.WIDE R26, R7, c[0x0][0x170], R22 ; /* 0x00005c00071a7a25 */
/* 0x001fc800078e0216 */
/*04d0*/ IMAD.WIDE R16, R7, c[0x0][0x170], R14 ; /* 0x00005c0007107a25 */
/* 0x004fe200078e020e */
/*04e0*/ DFMA R20, R10, R20, R24 ; /* 0x000000140a14722b */
/* 0x008e0e0000000018 */
/*04f0*/ STG.E.64 [R2.64], R20 ; /* 0x0000001402007986 */
/* 0x0011e8000c101b04 */
/*0500*/ LDG.E.64 R10, [R26.64] ; /* 0x000000041a0a7981 */
/* 0x000ea8000c1e1b00 */
/*0510*/ LDG.E.64 R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x000ea2000c1e1b00 */
/*0520*/ IMAD.WIDE R24, R7, c[0x0][0x170], R16 ; /* 0x00005c0007187a25 */
/* 0x002fe200078e0210 */
/*0530*/ DFMA R18, R10, R12, R20 ; /* 0x0000000c0a12722b */
/* 0x0042860000000014 */
/*0540*/ IMAD.WIDE R10, R7, c[0x0][0x170], R26 ; /* 0x00005c00070a7a25 */
/* 0x002fc800078e021a */
/*0550*/ STG.E.64 [R2.64], R18 ; /* 0x0000001202007986 */
/* 0x0043e8000c101b04 */
/*0560*/ LDG.E.64 R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x000ea8000c1e1b00 */
/*0570*/ LDG.E.64 R14, [R24.64] ; /* 0x00000004180e7981 */
/* 0x000ea2000c1e1b00 */
/*0580*/ IMAD.WIDE R20, R7, c[0x0][0x170], R10 ; /* 0x00005c0007147a25 */
/* 0x001fe200078e020a */
/*0590*/ DFMA R14, R12, R14, R18 ; /* 0x0000000e0c0e722b */
/* 0x0040860000000012 */
/*05a0*/ IMAD.WIDE R12, R7, c[0x0][0x170], R24 ; /* 0x00005c00070c7a25 */
/* 0x001fc800078e0218 */
/*05b0*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0041e8000c101b04 */
/*05c0*/ LDG.E.64 R22, [R12.64] ; /* 0x000000040c167981 */
/* 0x000ea8000c1e1b00 */
/*05d0*/ LDG.E.64 R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x000ea4000c1e1b00 */
/*05e0*/ DFMA R26, R16, R22, R14 ; /* 0x00000016101a722b */
/* 0x0044c4000000000e */
/*05f0*/ IMAD.WIDE R22, R7, c[0x0][0x170], R20 ; /* 0x00005c0007167a25 */
/* 0x004fc800078e0214 */
/*0600*/ IMAD.WIDE R16, R7.reuse, c[0x0][0x170], R12 ; /* 0x00005c0007107a25 */
/* 0x040fe200078e020c */
/*0610*/ STG.E.64 [R2.64], R26 ; /* 0x0000001a02007986 */
/* 0x0085e8000c101b04 */
/*0620*/ LDG.E.64 R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000ee8000c1e1b00 */
/*0630*/ LDG.E.64 R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x002ee2000c1e1b00 */
/*0640*/ IMAD.WIDE R24, R7, c[0x0][0x170], R22 ; /* 0x00005c0007187a25 */
/* 0x000fc800078e0216 */
/*0650*/ IMAD.WIDE R14, R7, c[0x0][0x170], R16 ; /* 0x00005c00070e7a25 */
/* 0x001fe200078e0210 */
/*0660*/ DFMA R18, R10, R18, R26 ; /* 0x000000120a12722b */
/* 0x008e0e000000001a */
/*0670*/ STG.E.64 [R2.64], R18 ; /* 0x0000001202007986 */
/* 0x0011e8000c101b04 */
/*0680*/ LDG.E.64 R10, [R24.64] ; /* 0x00000004180a7981 */
/* 0x000ee8000c1e1b00 */
/*0690*/ LDG.E.64 R12, [R14.64] ; /* 0x000000040e0c7981 */
/* 0x000ee2000c1e1b00 */
/*06a0*/ IMAD.WIDE R26, R7, c[0x0][0x170], R14 ; /* 0x00005c00071a7a25 */
/* 0x004fe200078e020e */
/*06b0*/ DFMA R20, R10, R12, R18 ; /* 0x0000000c0a14722b */
/* 0x0082860000000012 */
/*06c0*/ IMAD.WIDE R10, R7, c[0x0][0x170], R24 ; /* 0x00005c00070a7a25 */
/* 0x002fc800078e0218 */
/*06d0*/ STG.E.64 [R2.64], R20 ; /* 0x0000001402007986 */
/* 0x0043e8000c101b04 */
/*06e0*/ LDG.E.64 R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x000ea8000c1e1b00 */
/*06f0*/ LDG.E.64 R16, [R26.64] ; /* 0x000000041a107981 */
/* 0x000ea2000c1e1b00 */
/*0700*/ IMAD.WIDE R18, R7, c[0x0][0x170], R10 ; /* 0x00005c0007127a25 */
/* 0x001fe200078e020a */
/*0710*/ DFMA R22, R12, R16, R20 ; /* 0x000000100c16722b */
/* 0x0040860000000014 */
/*0720*/ IMAD.WIDE R16, R7, c[0x0][0x170], R26 ; /* 0x00005c0007107a25 */
/* 0x001fc800078e021a */
/*0730*/ STG.E.64 [R2.64], R22 ; /* 0x0000001602007986 */
/* 0x0043e8000c101b04 */
/*0740*/ LDG.E.64 R14, [R16.64] ; /* 0x00000004100e7981 */
/* 0x000ea8000c1e1b00 */
/*0750*/ LDG.E.64 R12, [R18.64] ; /* 0x00000004120c7981 */
/* 0x000ea2000c1e1b00 */
/*0760*/ IADD3 R4, R4, -0x10, RZ ; /* 0xfffffff004047810 */
/* 0x000fe20007ffe0ff */
/*0770*/ IMAD.WIDE R10, R7, c[0x0][0x170], R18 ; /* 0x00005c00070a7a25 */
/* 0x000fe200078e0212 */
/*0780*/ IADD3 R0, R0, 0x10, RZ ; /* 0x0000001000007810 */
/* 0x000fc40007ffe0ff */
/*0790*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe20003f24270 */
/*07a0*/ DFMA R12, R12, R14, R22 ; /* 0x0000000e0c0c722b */
/* 0x0040a40000000016 */
/*07b0*/ IMAD.WIDE R14, R7, c[0x0][0x170], R16 ; /* 0x00005c00070e7a25 */
/* 0x001fca00078e0210 */
/*07c0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0043ea000c101b04 */
/*07d0*/ @P1 BRA 0x1a0 ; /* 0xfffff9c000001947 */
/* 0x000fea000383ffff */
/*07e0*/ ISETP.GT.AND P1, PT, R4, 0x4, PT ; /* 0x000000040400780c */
/* 0x000fda0003f24270 */
/*07f0*/ @!P1 BRA 0xb30 ; /* 0x0000033000009947 */
/* 0x000fea0003800000 */
/*0800*/ LDG.E.64 R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x000ea8000c1e1b00 */
/*0810*/ LDG.E.64 R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000ea2000c1e1b00 */
/*0820*/ IMAD.WIDE R20, R7, c[0x0][0x170], R10 ; /* 0x00005c0007147a25 */
/* 0x002fe200078e020a */
/*0830*/ DFMA R16, R16, R18, R12 ; /* 0x000000121010722b */
/* 0x024046000000000c */
/*0840*/ IMAD.WIDE R18, R7, c[0x0][0x170], R14 ; /* 0x00005c0007127a25 */
/* 0x001fc800078e020e */
/*0850*/ STG.E.64 [R2.64], R16 ; /* 0x0000001002007986 */
/* 0x0021e8000c101b04 */
/*0860*/ LDG.E.64 R12, [R20.64] ; /* 0x00000004140c7981 */
/* 0x000ea8000c1e1b00 */
/*0870*/ LDG.E.64 R22, [R18.64] ; /* 0x0000000412167981 */
/* 0x000ea2000c1e1b00 */
/*0880*/ IMAD.WIDE R24, R7, c[0x0][0x170], R18 ; /* 0x00005c0007187a25 */
/* 0x000fe200078e0212 */
/*0890*/ DFMA R22, R12, R22, R16 ; /* 0x000000160c16722b */
/* 0x0042860000000010 */
/*08a0*/ IMAD.WIDE R12, R7, c[0x0][0x170], R20 ; /* 0x00005c00070c7a25 */
/* 0x002fc800078e0214 */
/*08b0*/ STG.E.64 [R2.64], R22 ; /* 0x0000001602007986 */
/* 0x0043e8000c101b04 */
/*08c0*/ LDG.E.64 R10, [R12.64] ; /* 0x000000040c0a7981 */
/* 0x000ea8000c1e1b00 */
/*08d0*/ LDG.E.64 R14, [R24.64] ; /* 0x00000004180e7981 */
/* 0x000ea2000c1e1b00 */
/*08e0*/ IMAD.WIDE R26, R7, c[0x0][0x170], R12 ; /* 0x00005c00071a7a25 */
/* 0x000fe200078e020c */
/*08f0*/ DFMA R14, R10, R14, R22 ; /* 0x0000000e0a0e722b */
/* 0x0044c60000000016 */
/*0900*/ IMAD.WIDE R10, R7, c[0x0][0x170], R24 ; /* 0x00005c00070a7a25 */
/* 0x004fc800078e0218 */
/*0910*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0085e8000c101b04 */
/*0920*/ LDG.E.64 R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000ee8000c1e1b00 */
/*0930*/ LDG.E.64 R16, [R26.64] ; /* 0x000000041a107981 */
/* 0x001ee4000c1e1b00 */
/*0940*/ DFMA R20, R16, R18, R14 ; /* 0x000000121014722b */
/* 0x0080c4000000000e */
/*0950*/ IMAD.WIDE R18, R7, c[0x0][0x170], R26 ; /* 0x00005c0007127a25 */
/* 0x001fc800078e021a */
/*0960*/ IMAD.WIDE R16, R7.reuse, c[0x0][0x170], R10 ; /* 0x00005c0007107a25 */
/* 0x040fe200078e020a */
/*0970*/ STG.E.64 [R2.64], R20 ; /* 0x0000001402007986 */
/* 0x0081e8000c101b04 */
/*0980*/ LDG.E.64 R12, [R18.64] ; /* 0x00000004120c7981 */
/* 0x000ee8000c1e1b00 */
/*0990*/ LDG.E.64 R22, [R16.64] ; /* 0x0000000410167981 */
/* 0x002ee2000c1e1b00 */
/*09a0*/ IMAD.WIDE R14, R7, c[0x0][0x170], R16 ; /* 0x00005c00070e7a25 */
/* 0x004fe200078e0210 */
/*09b0*/ DFMA R12, R12, R22, R20 ; /* 0x000000160c0c722b */
/* 0x0082860000000014 */
/*09c0*/ IMAD.WIDE R22, R7, c[0x0][0x170], R18 ; /* 0x00005c0007167a25 */
/* 0x002fc800078e0212 */
/*09d0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0043e8000c101b04 */
/*09e0*/ LDG.E.64 R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000ea8000c1e1b00 */
/*09f0*/ LDG.E.64 R24, [R14.64] ; /* 0x000000040e187981 */
/* 0x000ea2000c1e1b00 */
/*0a00*/ IMAD.WIDE R20, R7, c[0x0][0x170], R14 ; /* 0x00005c0007147a25 */
/* 0x001fe200078e020e */
/*0a10*/ DFMA R24, R10, R24, R12 ; /* 0x000000180a18722b */
/* 0x004086000000000c */
/*0a20*/ IMAD.WIDE R10, R7, c[0x0][0x170], R22 ; /* 0x00005c00070a7a25 */
/* 0x001fc800078e0216 */
/*0a30*/ STG.E.64 [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x0041e8000c101b04 */
/*0a40*/ LDG.E.64 R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x000ea8000c1e1b00 */
/*0a50*/ LDG.E.64 R18, [R20.64] ; /* 0x0000000414127981 */
/* 0x000ea2000c1e1b00 */
/*0a60*/ IMAD.WIDE R26, R7, c[0x0][0x170], R10 ; /* 0x00005c00071a7a25 */
/* 0x000fe200078e020a */
/*0a70*/ DFMA R18, R16, R18, R24 ; /* 0x000000121012722b */
/* 0x0044c60000000018 */
/*0a80*/ IMAD.WIDE R16, R7, c[0x0][0x170], R20 ; /* 0x00005c0007107a25 */
/* 0x004fc800078e0214 */
/*0a90*/ STG.E.64 [R2.64], R18 ; /* 0x0000001202007986 */
/* 0x0081e8000c101b04 */
/*0aa0*/ LDG.E.64 R14, [R16.64] ; /* 0x00000004100e7981 */
/* 0x000ea8000c1e1b00 */
/*0ab0*/ LDG.E.64 R12, [R26.64] ; /* 0x000000041a0c7981 */
/* 0x002ea2000c1e1b00 */
/*0ac0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0ad0*/ IMAD.WIDE R10, R7, c[0x0][0x170], R26 ; /* 0x00005c00070a7a25 */
/* 0x000fe200078e021a */
/*0ae0*/ IADD3 R0, R0, 0x8, RZ ; /* 0x0000000800007810 */
/* 0x000fc40007ffe0ff */
/*0af0*/ IADD3 R4, R4, -0x8, RZ ; /* 0xfffffff804047810 */
/* 0x000fe20007ffe0ff */
/*0b00*/ DFMA R12, R12, R14, R18 ; /* 0x0000000e0c0c722b */
/* 0x0042a40000000012 */
/*0b10*/ IMAD.WIDE R14, R7, c[0x0][0x170], R16 ; /* 0x00005c00070e7a25 */
/* 0x002fca00078e0210 */
/*0b20*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0041e8000c101b04 */
/*0b30*/ ISETP.NE.OR P0, PT, R4, RZ, P0 ; /* 0x000000ff0400720c */
/* 0x000fda0000705670 */
/*0b40*/ @!P0 BRA 0xd10 ; /* 0x000001c000008947 */
/* 0x000fea0003800000 */
/*0b50*/ LDG.E.64 R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x000ea8000c1e1b00 */
/*0b60*/ LDG.E.64 R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x001ea2000c1e1b00 */
/*0b70*/ IMAD.WIDE R26, R7, c[0x0][0x170], R10 ; /* 0x00005c00071a7a25 */
/* 0x000fc800078e020a */
/*0b80*/ IMAD.WIDE R24, R7, c[0x0][0x170], R14 ; /* 0x00005c0007187a25 */
/* 0x000fe200078e020e */
/*0b90*/ DFMA R12, R16, R18, R12 ; /* 0x00000012100c722b */
/* 0x026e0e000000000c */
/*0ba0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b04 */
/*0bb0*/ LDG.E.64 R16, [R26.64] ; /* 0x000000041a107981 */
/* 0x000ea8000c1e1b00 */
/*0bc0*/ LDG.E.64 R18, [R24.64] ; /* 0x0000000418127981 */
/* 0x000ea2000c1e1b00 */
/*0bd0*/ IMAD.WIDE R28, R7, c[0x0][0x170], R24 ; /* 0x00005c00071c7a25 */
/* 0x000fe200078e0218 */
/*0be0*/ DFMA R20, R16, R18, R12 ; /* 0x000000121014722b */
/* 0x004286000000000c */
/*0bf0*/ IMAD.WIDE R16, R7, c[0x0][0x170], R26 ; /* 0x00005c0007107a25 */
/* 0x002fc800078e021a */
/*0c00*/ STG.E.64 [R2.64], R20 ; /* 0x0000001402007986 */
/* 0x0043e8000c101b04 */
/*0c10*/ LDG.E.64 R10, [R16.64] ; /* 0x00000004100a7981 */
/* 0x0004e8000c1e1b00 */
/*0c20*/ LDG.E.64 R14, [R28.64] ; /* 0x000000041c0e7981 */
/* 0x000ee2000c1e1b00 */
/*0c30*/ IMAD.WIDE R18, R7, c[0x0][0x170], R28 ; /* 0x00005c0007127a25 */
/* 0x000fc800078e021c */
/*0c40*/ IMAD.WIDE R16, R7, c[0x0][0x170], R16 ; /* 0x00005c0007107a25 */
/* 0x004fe200078e0210 */
/*0c50*/ DFMA R22, R10, R14, R20 ; /* 0x0000000e0a16722b */
/* 0x008e8e0000000014 */
/*0c60*/ STG.E.64 [R2.64], R22 ; /* 0x0000001602007986 */
/* 0x0043e8000c101b04 */
/*0c70*/ LDG.E.64 R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x000ea8000c1e1b00 */
/*0c80*/ LDG.E.64 R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x001ea2000c1e1b00 */
/*0c90*/ IADD3 R4, R4, -0x4, RZ ; /* 0xfffffffc04047810 */
/* 0x000fe20007ffe0ff */
/*0ca0*/ IMAD.WIDE R14, R7, c[0x0][0x170], R18 ; /* 0x00005c00070e7a25 */
/* 0x000fe200078e0212 */
/*0cb0*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x000fc40007ffe0ff */
/*0cc0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*0cd0*/ DFMA R12, R12, R10, R22 ; /* 0x0000000a0c0c722b */
/* 0x0040a40000000016 */
/*0ce0*/ IMAD.WIDE R10, R7, c[0x0][0x170], R16 ; /* 0x00005c00070a7a25 */
/* 0x001fca00078e0210 */
/*0cf0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0043ea000c101b04 */
/*0d00*/ @P0 BRA 0xb50 ; /* 0xfffffe4000000947 */
/* 0x002fea000383ffff */
/*0d10*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f05270 */
/*0d20*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0d30*/ LDG.E.64 R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000562000c1e1b00 */
/*0d40*/ IMAD R4, R0.reuse, c[0x0][0x170], R6 ; /* 0x00005c0000047a24 */
/* 0x040fe400078e0206 */
/*0d50*/ IMAD R0, R0, c[0x0][0x170], R5 ; /* 0x00005c0000007a24 */
/* 0x000fe400078e0205 */
/*0d60*/ IMAD.WIDE R4, R4, R7, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0207 */
/*0d70*/ IMAD.WIDE R12, R0, R7, c[0x0][0x160] ; /* 0x00005800000c7625 */
/* 0x023fc800078e0207 */
/*0d80*/ LDG.E.64 R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x0010e8000c1e1b00 */
/*0d90*/ LDG.E.64 R16, [R12.64] ; /* 0x000000040c107981 */
/* 0x0002e2000c1e1b00 */
/*0da0*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */
/* 0x000fc80007ffe0ff */
/*0db0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*0dc0*/ IMAD.WIDE R4, R7, c[0x0][0x170], R4 ; /* 0x00005c0007047a25 */
/* 0x001fc800078e0204 */
/*0dd0*/ IMAD.WIDE R12, R7, c[0x0][0x170], R12 ; /* 0x00005c00070c7a25 */
/* 0x002fe200078e020c */
/*0de0*/ DFMA R10, R14, R16, R10 ; /* 0x000000100e0a722b */
/* 0x008e0e000000000a */
/*0df0*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0011e2000c101b04 */
/*0e00*/ @P0 BRA 0xd80 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0e10*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0e20*/ BRA 0xe20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
void init(double **A, double **C1, double **C2, int dim) {
int i, j;
int size = dim * dim * sizeof(double);
*A = (double *) malloc(size);
srand(time(NULL));
for (i = 0; i < dim; i++) {
for (j = 0; j < dim; j++) {
(*A)[i * dim + j] = 1.0 + 1.0 * rand() / RAND_MAX;
}
}
*C1 = (double *) malloc(size);
memset(*C1, 0, size);
*C2 = (double *) malloc(size);
memset(*C2, 0, size);
}
void cleanup(double **A, double **C1, double **C2) {
free(*A);
free(*C1);
free(*C2);
}
double multiplyHost(double *A, double *C, int dim) {
int i, j, k;
clock_t clockStart;
clockStart = clock();
for (i = 0; i < dim; i++) {
for (j = 0; j < dim; j++) {
for (k = 0; k < dim; k++) {
C[i * dim + j] += A[k * dim + i] * A[k * dim + j];
}
}
}
double clockDiff = clock() - clockStart;
return clockDiff / 1000;
}
__global__ void multiplyKernel(double *A, double *C, int dim) {
int i, j, k;
i = blockIdx.x;
j = threadIdx.x;
for (k = 0; k < dim; k++) {
C[i * dim + j] += A[k * dim + i] * A[k * dim + j];
}
}
double multiplyDevice(double *A, double *C, int dim) {
double *dA, *dC;
int size = dim * dim * sizeof(double);
cudaMalloc((void **) &dA, size);
cudaMalloc((void **) &dC, size);
cudaMemcpy(dA, A, size, cudaMemcpyHostToDevice);
cudaMemcpy(dC, C, size, cudaMemcpyHostToDevice);
dim3 dimGrid(dim);
dim3 dimBlock(dim);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
multiplyKernel<<<dimGrid, dimBlock>>>(dA, dC, dim);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float diff = 0;
cudaEventElapsedTime(&diff, start, stop);
cudaMemcpy(C, dC, size, cudaMemcpyDeviceToHost);
cudaFree(dA);
cudaFree(dC);
return diff;
}
int match(double *C1, double *C2, int dim) {
int i, j, nError = 0;
for (i = 0; i < dim; i++) {
for (j = 0; j < dim; j++) {
if(fabs(C1[i * dim + j] - C2[i * dim + j]) > 0.000001) {
nError++;
}
}
}
return nError;
}
int main() {
int dim = 1024;
double *A, *CHost, *CDevice;
double nOp = 2.0 * dim * dim * dim;
init(&A, &CHost, &CDevice, dim);
double timeHost = multiplyHost(A, CHost, dim);
double flopsHost = 1000 * nOp / timeHost;
printf("Time taken on host (ms) = %lf\n", timeHost);
printf("FLOPS on host = %lf\n", flopsHost);
double timeDevice = multiplyDevice(A, CDevice, dim);
double flopsDevice = 1000 * nOp / timeDevice;
printf("Time taken on device (ms) = %lf\n", timeDevice);
printf("FLOPS on device = %lf\n", flopsDevice);
int err = match(CHost, CDevice, dim);
if(err > 0) {
printf("Results did not match. %d mismatches\n", err);
} else {
printf("Results matched.\n");
}
cleanup(&A, &CHost, &CDevice);
} | .file "tmpxft_00066e6a_00000000-6_matrix_mult.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4initPPdS0_S0_i
.type _Z4initPPdS0_S0_i, @function
_Z4initPPdS0_S0_i:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r12
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, %r14d
movl %ecx, %eax
imull %ecx, %eax
sall $3, %eax
cltq
movq %rax, 8(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, (%r12)
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
testl %r14d, %r14d
jle .L4
movslq %r14d, %rax
leaq 0(,%rax,8), %r15
negq %rax
salq $3, %rax
movq %rax, (%rsp)
movq %r15, %rbp
movl $0, %r13d
.L5:
movq (%rsp), %rax
leaq 0(%rbp,%rax), %rbx
.L6:
call rand@PLT
movq (%r12), %rdx
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC0(%rip), %xmm0
addsd .LC1(%rip), %xmm0
movsd %xmm0, (%rdx,%rbx)
addq $8, %rbx
cmpq %rbp, %rbx
jne .L6
addl $1, %r13d
addq %r15, %rbp
cmpl %r13d, %r14d
jne .L5
.L4:
movq 8(%rsp), %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rdi
movq 16(%rsp), %rax
movq %rdi, (%rax)
movq %rbx, %rcx
movq %rbx, %rdx
movl $0, %esi
call __memset_chk@PLT
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rdi
movq 24(%rsp), %rax
movq %rdi, (%rax)
movq %rbx, %rcx
movq %rbx, %rdx
movl $0, %esi
call __memset_chk@PLT
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z4initPPdS0_S0_i, .-_Z4initPPdS0_S0_i
.globl _Z7cleanupPPdS0_S0_
.type _Z7cleanupPPdS0_S0_, @function
_Z7cleanupPPdS0_S0_:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbp
movq %rdx, %rbx
movq (%rdi), %rdi
call free@PLT
movq 0(%rbp), %rdi
call free@PLT
movq (%rbx), %rdi
call free@PLT
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z7cleanupPPdS0_S0_, .-_Z7cleanupPPdS0_S0_
.globl _Z12multiplyHostPdS_i
.type _Z12multiplyHostPdS_i, @function
_Z12multiplyHostPdS_i:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r13
movq %rsi, %rbp
movl %edx, %ebx
call clock@PLT
movq %rax, %r12
testl %ebx, %ebx
jle .L12
movslq %ebx, %r11
movq %r13, %r8
leaq 0(,%r11,8), %rdi
movq %r11, %r9
movl $0, %r10d
.L13:
movq %r10, %rsi
negq %rsi
movq %rbp, %rcx
.L16:
movq %r8, %rax
movl $0, %edx
.L14:
movsd (%rax), %xmm0
mulsd (%rax,%rsi,8), %xmm0
addsd (%rcx), %xmm0
movsd %xmm0, (%rcx)
addl $1, %edx
addq %rdi, %rax
cmpl %edx, %ebx
jne .L14
addq $8, %rcx
addq $1, %rsi
cmpq %r9, %rsi
jne .L16
addq $1, %r10
subq $1, %r9
addq $8, %r8
addq %rdi, %rbp
cmpq %r11, %r10
jne .L13
.L12:
call clock@PLT
subq %r12, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC2(%rip), %xmm0
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z12multiplyHostPdS_i, .-_Z12multiplyHostPdS_i
.globl _Z5matchPdS_i
.type _Z5matchPdS_i, @function
_Z5matchPdS_i:
.LFB2061:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L25
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %r8
movq %rsi, %r9
movslq %edx, %r11
leaq 0(,%r11,8), %rbx
negq %r11
salq $3, %r11
movq %rbx, %rdi
movl $0, %ecx
movl $0, %r10d
movq .LC3(%rip), %xmm2
movsd .LC4(%rip), %xmm1
.L21:
leaq (%rdi,%r11), %rax
.L24:
movsd (%r8,%rax), %xmm0
subsd (%r9,%rax), %xmm0
andpd %xmm2, %xmm0
comisd %xmm1, %xmm0
seta %sil
movzbl %sil, %esi
addl %esi, %ecx
addq $8, %rax
cmpq %rdi, %rax
jne .L24
addl $1, %r10d
addq %rbx, %rdi
cmpl %r10d, %edx
jne .L21
movl %ecx, %eax
popq %rbx
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore 3
movl $0, %ecx
movl %ecx, %eax
ret
.cfi_endproc
.LFE2061:
.size _Z5matchPdS_i, .-_Z5matchPdS_i
.globl _Z37__device_stub__Z14multiplyKernelPdS_iPdS_i
.type _Z37__device_stub__Z14multiplyKernelPdS_iPdS_i, @function
_Z37__device_stub__Z14multiplyKernelPdS_iPdS_i:
.LFB2087:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L36
.L32:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L37
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14multiplyKernelPdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L32
.L37:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z37__device_stub__Z14multiplyKernelPdS_iPdS_i, .-_Z37__device_stub__Z14multiplyKernelPdS_iPdS_i
.globl _Z14multiplyKernelPdS_i
.type _Z14multiplyKernelPdS_i, @function
_Z14multiplyKernelPdS_i:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z14multiplyKernelPdS_iPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z14multiplyKernelPdS_i, .-_Z14multiplyKernelPdS_i
.globl _Z14multiplyDevicePdS_i
.type _Z14multiplyDevicePdS_i, @function
_Z14multiplyDevicePdS_i:
.LFB2060:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $88, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %rbp
movq %rsi, %r13
movl %edx, %r12d
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl %edx, %ebx
imull %edx, %ebx
sall $3, %ebx
movslq %ebx, %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %r12d, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl %r12d, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L44
.L41:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 12(%rsp)
leaq 12(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L45
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
movl %r12d, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z37__device_stub__Z14multiplyKernelPdS_iPdS_i
jmp .L41
.L45:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z14multiplyDevicePdS_i, .-_Z14multiplyDevicePdS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "Time taken on host (ms) = %lf\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC8:
.string "FLOPS on host = %lf\n"
.section .rodata.str1.8
.align 8
.LC9:
.string "Time taken on device (ms) = %lf\n"
.section .rodata.str1.1
.LC10:
.string "FLOPS on device = %lf\n"
.section .rodata.str1.8
.align 8
.LC11:
.string "Results did not match. %d mismatches\n"
.section .rodata.str1.1
.LC12:
.string "Results matched.\n"
.text
.globl main
.type main, @function
main:
.LFB2062:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdi
movl $1024, %ecx
call _Z4initPPdS0_S0_i
movq 24(%rsp), %rbx
movq 16(%rsp), %r12
movl $1024, %edx
movq %rbx, %rsi
movq %r12, %rdi
call _Z12multiplyHostPdS_i
movsd .LC6(%rip), %xmm1
divsd %xmm0, %xmm1
movq %xmm1, %rbp
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbp, %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 32(%rsp), %rbp
movl $1024, %edx
movq %rbp, %rsi
movq %r12, %rdi
call _Z14multiplyDevicePdS_i
movsd .LC6(%rip), %xmm2
divsd %xmm0, %xmm2
movsd %xmm2, 8(%rsp)
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $1024, %edx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z5matchPdS_i
testl %eax, %eax
jle .L47
movl %eax, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L48:
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdi
call _Z7cleanupPPdS0_S0_
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L51
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L48
.L51:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z14multiplyKernelPdS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z14multiplyKernelPdS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -4194304
.long 1105199103
.align 8
.LC1:
.long 0
.long 1072693248
.align 8
.LC2:
.long 0
.long 1083129856
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC3:
.long -1
.long 2147483647
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC4:
.long -1598689907
.long 1051772663
.align 8
.LC6:
.long 0
.long 1115635712
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
void init(double **A, double **C1, double **C2, int dim) {
int i, j;
int size = dim * dim * sizeof(double);
*A = (double *) malloc(size);
srand(time(NULL));
for (i = 0; i < dim; i++) {
for (j = 0; j < dim; j++) {
(*A)[i * dim + j] = 1.0 + 1.0 * rand() / RAND_MAX;
}
}
*C1 = (double *) malloc(size);
memset(*C1, 0, size);
*C2 = (double *) malloc(size);
memset(*C2, 0, size);
}
void cleanup(double **A, double **C1, double **C2) {
free(*A);
free(*C1);
free(*C2);
}
double multiplyHost(double *A, double *C, int dim) {
int i, j, k;
clock_t clockStart;
clockStart = clock();
for (i = 0; i < dim; i++) {
for (j = 0; j < dim; j++) {
for (k = 0; k < dim; k++) {
C[i * dim + j] += A[k * dim + i] * A[k * dim + j];
}
}
}
double clockDiff = clock() - clockStart;
return clockDiff / 1000;
}
__global__ void multiplyKernel(double *A, double *C, int dim) {
int i, j, k;
i = blockIdx.x;
j = threadIdx.x;
for (k = 0; k < dim; k++) {
C[i * dim + j] += A[k * dim + i] * A[k * dim + j];
}
}
double multiplyDevice(double *A, double *C, int dim) {
double *dA, *dC;
int size = dim * dim * sizeof(double);
cudaMalloc((void **) &dA, size);
cudaMalloc((void **) &dC, size);
cudaMemcpy(dA, A, size, cudaMemcpyHostToDevice);
cudaMemcpy(dC, C, size, cudaMemcpyHostToDevice);
dim3 dimGrid(dim);
dim3 dimBlock(dim);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
multiplyKernel<<<dimGrid, dimBlock>>>(dA, dC, dim);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float diff = 0;
cudaEventElapsedTime(&diff, start, stop);
cudaMemcpy(C, dC, size, cudaMemcpyDeviceToHost);
cudaFree(dA);
cudaFree(dC);
return diff;
}
int match(double *C1, double *C2, int dim) {
int i, j, nError = 0;
for (i = 0; i < dim; i++) {
for (j = 0; j < dim; j++) {
if(fabs(C1[i * dim + j] - C2[i * dim + j]) > 0.000001) {
nError++;
}
}
}
return nError;
}
int main() {
int dim = 1024;
double *A, *CHost, *CDevice;
double nOp = 2.0 * dim * dim * dim;
init(&A, &CHost, &CDevice, dim);
double timeHost = multiplyHost(A, CHost, dim);
double flopsHost = 1000 * nOp / timeHost;
printf("Time taken on host (ms) = %lf\n", timeHost);
printf("FLOPS on host = %lf\n", flopsHost);
double timeDevice = multiplyDevice(A, CDevice, dim);
double flopsDevice = 1000 * nOp / timeDevice;
printf("Time taken on device (ms) = %lf\n", timeDevice);
printf("FLOPS on device = %lf\n", flopsDevice);
int err = match(CHost, CDevice, dim);
if(err > 0) {
printf("Results did not match. %d mismatches\n", err);
} else {
printf("Results matched.\n");
}
cleanup(&A, &CHost, &CDevice);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
void init(double **A, double **C1, double **C2, int dim) {
int i, j;
int size = dim * dim * sizeof(double);
*A = (double *) malloc(size);
srand(time(NULL));
for (i = 0; i < dim; i++) {
for (j = 0; j < dim; j++) {
(*A)[i * dim + j] = 1.0 + 1.0 * rand() / RAND_MAX;
}
}
*C1 = (double *) malloc(size);
memset(*C1, 0, size);
*C2 = (double *) malloc(size);
memset(*C2, 0, size);
}
void cleanup(double **A, double **C1, double **C2) {
free(*A);
free(*C1);
free(*C2);
}
double multiplyHost(double *A, double *C, int dim) {
int i, j, k;
clock_t clockStart;
clockStart = clock();
for (i = 0; i < dim; i++) {
for (j = 0; j < dim; j++) {
for (k = 0; k < dim; k++) {
C[i * dim + j] += A[k * dim + i] * A[k * dim + j];
}
}
}
double clockDiff = clock() - clockStart;
return clockDiff / 1000;
}
__global__ void multiplyKernel(double *A, double *C, int dim) {
int i, j, k;
i = blockIdx.x;
j = threadIdx.x;
for (k = 0; k < dim; k++) {
C[i * dim + j] += A[k * dim + i] * A[k * dim + j];
}
}
double multiplyDevice(double *A, double *C, int dim) {
double *dA, *dC;
int size = dim * dim * sizeof(double);
hipMalloc((void **) &dA, size);
hipMalloc((void **) &dC, size);
hipMemcpy(dA, A, size, hipMemcpyHostToDevice);
hipMemcpy(dC, C, size, hipMemcpyHostToDevice);
dim3 dimGrid(dim);
dim3 dimBlock(dim);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
multiplyKernel<<<dimGrid, dimBlock>>>(dA, dC, dim);
hipEventRecord(stop);
hipEventSynchronize(stop);
float diff = 0;
hipEventElapsedTime(&diff, start, stop);
hipMemcpy(C, dC, size, hipMemcpyDeviceToHost);
hipFree(dA);
hipFree(dC);
return diff;
}
int match(double *C1, double *C2, int dim) {
int i, j, nError = 0;
for (i = 0; i < dim; i++) {
for (j = 0; j < dim; j++) {
if(fabs(C1[i * dim + j] - C2[i * dim + j]) > 0.000001) {
nError++;
}
}
}
return nError;
}
int main() {
int dim = 1024;
double *A, *CHost, *CDevice;
double nOp = 2.0 * dim * dim * dim;
init(&A, &CHost, &CDevice, dim);
double timeHost = multiplyHost(A, CHost, dim);
double flopsHost = 1000 * nOp / timeHost;
printf("Time taken on host (ms) = %lf\n", timeHost);
printf("FLOPS on host = %lf\n", flopsHost);
double timeDevice = multiplyDevice(A, CDevice, dim);
double flopsDevice = 1000 * nOp / timeDevice;
printf("Time taken on device (ms) = %lf\n", timeDevice);
printf("FLOPS on device = %lf\n", flopsDevice);
int err = match(CHost, CDevice, dim);
if(err > 0) {
printf("Results did not match. %d mismatches\n", err);
} else {
printf("Results matched.\n");
}
cleanup(&A, &CHost, &CDevice);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
void init(double **A, double **C1, double **C2, int dim) {
int i, j;
int size = dim * dim * sizeof(double);
*A = (double *) malloc(size);
srand(time(NULL));
for (i = 0; i < dim; i++) {
for (j = 0; j < dim; j++) {
(*A)[i * dim + j] = 1.0 + 1.0 * rand() / RAND_MAX;
}
}
*C1 = (double *) malloc(size);
memset(*C1, 0, size);
*C2 = (double *) malloc(size);
memset(*C2, 0, size);
}
void cleanup(double **A, double **C1, double **C2) {
free(*A);
free(*C1);
free(*C2);
}
double multiplyHost(double *A, double *C, int dim) {
int i, j, k;
clock_t clockStart;
clockStart = clock();
for (i = 0; i < dim; i++) {
for (j = 0; j < dim; j++) {
for (k = 0; k < dim; k++) {
C[i * dim + j] += A[k * dim + i] * A[k * dim + j];
}
}
}
double clockDiff = clock() - clockStart;
return clockDiff / 1000;
}
__global__ void multiplyKernel(double *A, double *C, int dim) {
int i, j, k;
i = blockIdx.x;
j = threadIdx.x;
for (k = 0; k < dim; k++) {
C[i * dim + j] += A[k * dim + i] * A[k * dim + j];
}
}
double multiplyDevice(double *A, double *C, int dim) {
double *dA, *dC;
int size = dim * dim * sizeof(double);
hipMalloc((void **) &dA, size);
hipMalloc((void **) &dC, size);
hipMemcpy(dA, A, size, hipMemcpyHostToDevice);
hipMemcpy(dC, C, size, hipMemcpyHostToDevice);
dim3 dimGrid(dim);
dim3 dimBlock(dim);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
multiplyKernel<<<dimGrid, dimBlock>>>(dA, dC, dim);
hipEventRecord(stop);
hipEventSynchronize(stop);
float diff = 0;
hipEventElapsedTime(&diff, start, stop);
hipMemcpy(C, dC, size, hipMemcpyDeviceToHost);
hipFree(dA);
hipFree(dC);
return diff;
}
int match(double *C1, double *C2, int dim) {
int i, j, nError = 0;
for (i = 0; i < dim; i++) {
for (j = 0; j < dim; j++) {
if(fabs(C1[i * dim + j] - C2[i * dim + j]) > 0.000001) {
nError++;
}
}
}
return nError;
}
int main() {
int dim = 1024;
double *A, *CHost, *CDevice;
double nOp = 2.0 * dim * dim * dim;
init(&A, &CHost, &CDevice, dim);
double timeHost = multiplyHost(A, CHost, dim);
double flopsHost = 1000 * nOp / timeHost;
printf("Time taken on host (ms) = %lf\n", timeHost);
printf("FLOPS on host = %lf\n", flopsHost);
double timeDevice = multiplyDevice(A, CDevice, dim);
double flopsDevice = 1000 * nOp / timeDevice;
printf("Time taken on device (ms) = %lf\n", timeDevice);
printf("FLOPS on device = %lf\n", flopsDevice);
int err = match(CHost, CDevice, dim);
if(err > 0) {
printf("Results did not match. %d mismatches\n", err);
} else {
printf("Results matched.\n");
}
cleanup(&A, &CHost, &CDevice);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14multiplyKernelPdS_i
.globl _Z14multiplyKernelPdS_i
.p2align 8
.type _Z14multiplyKernelPdS_i,@function
_Z14multiplyKernelPdS_i:
s_load_b32 s4, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_3
s_mov_b32 s6, s15
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, s6, s4, v[0:1]
s_ashr_i32 s7, s15, 31
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[2:3], 3, v[1:2]
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_lshl_b64 s[2:3], s[6:7], 3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_add_u32 s2, s0, s2
global_load_b64 v[4:5], v[2:3], off
s_addc_u32 s3, s1, s3
s_ashr_i32 s5, s4, 31
s_lshl_b64 s[6:7], s[4:5], 3
s_mov_b32 s5, s4
.p2align 6
.LBB0_2:
v_lshlrev_b64 v[6:7], 3, v[0:1]
s_add_i32 s5, s5, -1
v_add_nc_u32_e32 v0, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
global_load_b64 v[8:9], v1, s[2:3]
global_load_b64 v[6:7], v[6:7], off
s_add_u32 s2, s2, s6
s_addc_u32 s3, s3, s7
s_cmp_lg_u32 s5, 0
s_waitcnt vmcnt(0)
v_fma_f64 v[4:5], v[8:9], v[6:7], v[4:5]
global_store_b64 v[2:3], v[4:5], off
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14multiplyKernelPdS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14multiplyKernelPdS_i, .Lfunc_end0-_Z14multiplyKernelPdS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14multiplyKernelPdS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14multiplyKernelPdS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
void init(double **A, double **C1, double **C2, int dim) {
int i, j;
int size = dim * dim * sizeof(double);
*A = (double *) malloc(size);
srand(time(NULL));
for (i = 0; i < dim; i++) {
for (j = 0; j < dim; j++) {
(*A)[i * dim + j] = 1.0 + 1.0 * rand() / RAND_MAX;
}
}
*C1 = (double *) malloc(size);
memset(*C1, 0, size);
*C2 = (double *) malloc(size);
memset(*C2, 0, size);
}
void cleanup(double **A, double **C1, double **C2) {
free(*A);
free(*C1);
free(*C2);
}
double multiplyHost(double *A, double *C, int dim) {
int i, j, k;
clock_t clockStart;
clockStart = clock();
for (i = 0; i < dim; i++) {
for (j = 0; j < dim; j++) {
for (k = 0; k < dim; k++) {
C[i * dim + j] += A[k * dim + i] * A[k * dim + j];
}
}
}
double clockDiff = clock() - clockStart;
return clockDiff / 1000;
}
__global__ void multiplyKernel(double *A, double *C, int dim) {
int i, j, k;
i = blockIdx.x;
j = threadIdx.x;
for (k = 0; k < dim; k++) {
C[i * dim + j] += A[k * dim + i] * A[k * dim + j];
}
}
double multiplyDevice(double *A, double *C, int dim) {
double *dA, *dC;
int size = dim * dim * sizeof(double);
hipMalloc((void **) &dA, size);
hipMalloc((void **) &dC, size);
hipMemcpy(dA, A, size, hipMemcpyHostToDevice);
hipMemcpy(dC, C, size, hipMemcpyHostToDevice);
dim3 dimGrid(dim);
dim3 dimBlock(dim);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
multiplyKernel<<<dimGrid, dimBlock>>>(dA, dC, dim);
hipEventRecord(stop);
hipEventSynchronize(stop);
float diff = 0;
hipEventElapsedTime(&diff, start, stop);
hipMemcpy(C, dC, size, hipMemcpyDeviceToHost);
hipFree(dA);
hipFree(dC);
return diff;
}
int match(double *C1, double *C2, int dim) {
int i, j, nError = 0;
for (i = 0; i < dim; i++) {
for (j = 0; j < dim; j++) {
if(fabs(C1[i * dim + j] - C2[i * dim + j]) > 0.000001) {
nError++;
}
}
}
return nError;
}
int main() {
int dim = 1024;
double *A, *CHost, *CDevice;
double nOp = 2.0 * dim * dim * dim;
init(&A, &CHost, &CDevice, dim);
double timeHost = multiplyHost(A, CHost, dim);
double flopsHost = 1000 * nOp / timeHost;
printf("Time taken on host (ms) = %lf\n", timeHost);
printf("FLOPS on host = %lf\n", flopsHost);
double timeDevice = multiplyDevice(A, CDevice, dim);
double flopsDevice = 1000 * nOp / timeDevice;
printf("Time taken on device (ms) = %lf\n", timeDevice);
printf("FLOPS on device = %lf\n", flopsDevice);
int err = match(CHost, CDevice, dim);
if(err > 0) {
printf("Results did not match. %d mismatches\n", err);
} else {
printf("Results matched.\n");
}
cleanup(&A, &CHost, &CDevice);
} | .text
.file "matrix_mult.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z4initPPdS0_S0_i
.LCPI0_0:
.quad 0x41dfffffffc00000 # double 2147483647
.LCPI0_1:
.quad 0x3ff0000000000000 # double 1
.text
.globl _Z4initPPdS0_S0_i
.p2align 4, 0x90
.type _Z4initPPdS0_S0_i,@function
_Z4initPPdS0_S0_i: # @_Z4initPPdS0_S0_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebx
movq %rdx, 32(%rsp) # 8-byte Spill
movq %rsi, 16(%rsp) # 8-byte Spill
movq %rdi, %r12
movl %ecx, %eax
imull %ecx, %eax
shll $3, %eax
movslq %eax, %rdi
movq %rdi, 24(%rsp) # 8-byte Spill
callq malloc
movq %rax, (%r12)
xorl %ebp, %ebp
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl %ebx, 12(%rsp) # 4-byte Spill
testl %ebx, %ebx
jle .LBB0_5
# %bb.1: # %.preheader.lr.ph
movl 12(%rsp), %r14d # 4-byte Reload
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_3 Depth 2
movl %ebp, %ebp
movq %r14, %rbx
movq %rbp, %r13
.p2align 4, 0x90
.LBB0_3: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movsd .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd %xmm1, %xmm0
movsd .LCPI0_1(%rip), %xmm1 # xmm1 = mem[0],zero
addsd %xmm1, %xmm0
movq (%r12), %rax
movsd %xmm0, (%rax,%r13,8)
incq %r13
decq %rbx
jne .LBB0_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
incq %r15
addl 12(%rsp), %ebp # 4-byte Folded Reload
cmpq %r14, %r15
jne .LBB0_2
.LBB0_5: # %._crit_edge25
movq 24(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
callq malloc
movq 16(%rsp), %rcx # 8-byte Reload
movq %rax, (%rcx)
movq %rax, %rdi
xorl %esi, %esi
movq %rbx, %rdx
callq memset@PLT
movq %rbx, %rdi
callq malloc
movq 32(%rsp), %rcx # 8-byte Reload
movq %rax, (%rcx)
movq %rax, %rdi
xorl %esi, %esi
movq %rbx, %rdx
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp memset@PLT # TAILCALL
.Lfunc_end0:
.size _Z4initPPdS0_S0_i, .Lfunc_end0-_Z4initPPdS0_S0_i
.cfi_endproc
# -- End function
.globl _Z7cleanupPPdS0_S0_ # -- Begin function _Z7cleanupPPdS0_S0_
.p2align 4, 0x90
.type _Z7cleanupPPdS0_S0_,@function
_Z7cleanupPPdS0_S0_: # @_Z7cleanupPPdS0_S0_
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdx, %rbx
movq %rsi, %r14
movq (%rdi), %rdi
callq free
movq (%r14), %rdi
callq free
movq (%rbx), %rdi
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp free # TAILCALL
.Lfunc_end1:
.size _Z7cleanupPPdS0_S0_, .Lfunc_end1-_Z7cleanupPPdS0_S0_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z12multiplyHostPdS_i
.LCPI2_0:
.quad 0x408f400000000000 # double 1000
.text
.globl _Z12multiplyHostPdS_i
.p2align 4, 0x90
.type _Z12multiplyHostPdS_i,@function
_Z12multiplyHostPdS_i: # @_Z12multiplyHostPdS_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movq %rsi, %r14
movq %rdi, %r15
callq clock
movq %rax, %rbx
testl %ebp, %ebp
jle .LBB2_7
# %bb.1: # %.preheader25.lr.ph
movl %ebp, %eax
leaq (,%rax,8), %rcx
xorl %edx, %edx
xorl %esi, %esi
.p2align 4, 0x90
.LBB2_2: # %.preheader25
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
# Child Loop BB2_4 Depth 3
movq %rsi, %rdi
imulq %rax, %rdi
leaq (%r14,%rdi,8), %rdi
xorl %r8d, %r8d
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB2_3: # %.preheader
# Parent Loop BB2_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_4 Depth 3
movsd (%rdi,%r9,8), %xmm0 # xmm0 = mem[0],zero
movq %rax, %r10
movq %r15, %r11
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_2 Depth=1
# Parent Loop BB2_3 Depth=2
# => This Inner Loop Header: Depth=3
movsd (%r11,%rdx), %xmm1 # xmm1 = mem[0],zero
mulsd (%r11,%r8), %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, (%rdi,%r9,8)
addq %rcx, %r11
decq %r10
jne .LBB2_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB2_3 Depth=2
incq %r9
addq $8, %r8
cmpq %rax, %r9
jne .LBB2_3
# %bb.6: # %._crit_edge28
# in Loop: Header=BB2_2 Depth=1
incq %rsi
addq $8, %rdx
cmpq %rax, %rsi
jne .LBB2_2
.LBB2_7: # %._crit_edge30
callq clock
subq %rbx, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI2_0(%rip), %xmm0
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z12multiplyHostPdS_i, .Lfunc_end2-_Z12multiplyHostPdS_i
.cfi_endproc
# -- End function
.globl _Z29__device_stub__multiplyKernelPdS_i # -- Begin function _Z29__device_stub__multiplyKernelPdS_i
.p2align 4, 0x90
.type _Z29__device_stub__multiplyKernelPdS_i,@function
_Z29__device_stub__multiplyKernelPdS_i: # @_Z29__device_stub__multiplyKernelPdS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14multiplyKernelPdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z29__device_stub__multiplyKernelPdS_i, .Lfunc_end3-_Z29__device_stub__multiplyKernelPdS_i
.cfi_endproc
# -- End function
.globl _Z14multiplyDevicePdS_i # -- Begin function _Z14multiplyDevicePdS_i
.p2align 4, 0x90
.type _Z14multiplyDevicePdS_i,@function
_Z14multiplyDevicePdS_i: # @_Z14multiplyDevicePdS_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $136, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movq %rsi, %rbx
movq %rdi, %r15
movl %edx, %eax
imull %edx, %eax
shll $3, %eax
movslq %eax, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl %ebp, %eax
movabsq $4294967296, %r15 # imm = 0x100000000
orq %rax, %r15
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_2
# %bb.1:
movq 24(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movl %ebp, 36(%rsp)
leaq 128(%rsp), %rax
movq %rax, 48(%rsp)
leaq 120(%rsp), %rax
movq %rax, 56(%rsp)
leaq 36(%rsp), %rax
movq %rax, 64(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z14multiplyKernelPdS_i, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_2:
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movl $0, 48(%rsp)
movq 40(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
addq $136, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z14multiplyDevicePdS_i, .Lfunc_end4-_Z14multiplyDevicePdS_i
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z5matchPdS_i
.LCPI5_0:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI5_1:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z5matchPdS_i
.p2align 4, 0x90
.type _Z5matchPdS_i,@function
_Z5matchPdS_i: # @_Z5matchPdS_i
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB5_1
# %bb.3: # %.preheader.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl %edx, %ecx
xorl %r8d, %r8d
movapd .LCPI5_0(%rip), %xmm0 # xmm0 = [NaN,NaN]
movsd .LCPI5_1(%rip), %xmm1 # xmm1 = mem[0],zero
xorl %r9d, %r9d
xorl %eax, %eax
.p2align 4, 0x90
.LBB5_4: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB5_5 Depth 2
movl %r8d, %r11d
leaq (%rsi,%r11,8), %r10
leaq (%rdi,%r11,8), %r11
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB5_5: # Parent Loop BB5_4 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r11,%rbx,8), %xmm2 # xmm2 = mem[0],zero
subsd (%r10,%rbx,8), %xmm2
andpd %xmm0, %xmm2
xorl %ebp, %ebp
ucomisd %xmm1, %xmm2
seta %bpl
addl %ebp, %eax
incq %rbx
cmpq %rbx, %rcx
jne .LBB5_5
# %bb.6: # %._crit_edge
# in Loop: Header=BB5_4 Depth=1
incq %r9
addl %edx, %r8d
cmpq %rcx, %r9
jne .LBB5_4
# %bb.7:
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %rbp
retq
.LBB5_1:
xorl %eax, %eax
retq
.Lfunc_end5:
.size _Z5matchPdS_i, .Lfunc_end5-_Z5matchPdS_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI6_0:
.quad 0x41dfffffffc00000 # double 2147483647
.LCPI6_1:
.quad 0x3ff0000000000000 # double 1
.LCPI6_2:
.quad 0x408f400000000000 # double 1000
.LCPI6_3:
.quad 0x427f400000000000 # double 2147483648000
.LCPI6_5:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI6_4:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $8388608, %edi # imm = 0x800000
callq malloc
movq %rax, %rbx
xorl %r14d, %r14d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movq %rbx, %r15
.p2align 4, 0x90
.LBB6_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB6_2 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB6_2: # Parent Loop BB6_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movsd .LCPI6_0(%rip), %xmm1 # xmm1 = mem[0],zero
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd %xmm1, %xmm0
movsd .LCPI6_1(%rip), %xmm1 # xmm1 = mem[0],zero
addsd %xmm1, %xmm0
movsd %xmm0, (%r15,%r12,8)
incq %r12
cmpq $1024, %r12 # imm = 0x400
jne .LBB6_2
# %bb.3: # %._crit_edge.i
# in Loop: Header=BB6_1 Depth=1
incq %r14
addq $8192, %r15 # imm = 0x2000
cmpq $1024, %r14 # imm = 0x400
jne .LBB6_1
# %bb.4: # %_Z4initPPdS0_S0_i.exit
movl $8388608, %edi # imm = 0x800000
callq malloc
movq %rax, %r14
xorl %r13d, %r13d
movl $8388608, %edx # imm = 0x800000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
movl $8388608, %edi # imm = 0x800000
callq malloc
movq %rax, %r15
movl $8388608, %edx # imm = 0x800000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
callq clock
movq %rax, %r12
movq %rbx, %rax
.p2align 4, 0x90
.LBB6_5: # %.preheader25.i
# =>This Loop Header: Depth=1
# Child Loop BB6_6 Depth 2
# Child Loop BB6_7 Depth 3
movq %r13, %rcx
shlq $13, %rcx
addq %r14, %rcx
movq %rbx, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB6_6: # %.preheader.i17
# Parent Loop BB6_5 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB6_7 Depth 3
movsd (%rcx,%rsi,8), %xmm0 # xmm0 = mem[0],zero
xorl %edi, %edi
.p2align 4, 0x90
.LBB6_7: # Parent Loop BB6_5 Depth=1
# Parent Loop BB6_6 Depth=2
# => This Inner Loop Header: Depth=3
movsd (%rax,%rdi), %xmm1 # xmm1 = mem[0],zero
mulsd (%rdx,%rdi), %xmm1
addsd %xmm1, %xmm0
addq $8192, %rdi # imm = 0x2000
cmpq $8388608, %rdi # imm = 0x800000
jne .LBB6_7
# %bb.8: # %._crit_edge.i21
# in Loop: Header=BB6_6 Depth=2
movsd %xmm0, (%rcx,%rsi,8)
incq %rsi
addq $8, %rdx
cmpq $1024, %rsi # imm = 0x400
jne .LBB6_6
# %bb.9: # %._crit_edge28.i
# in Loop: Header=BB6_5 Depth=1
incq %r13
addq $8, %rax
cmpq $1024, %r13 # imm = 0x400
jne .LBB6_5
# %bb.10: # %_Z12multiplyHostPdS_i.exit
callq clock
subq %r12, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI6_2(%rip), %xmm0
movsd .LCPI6_3(%rip), %xmm1 # xmm1 = mem[0],zero
movsd %xmm1, (%rsp) # 8-byte Spill
divsd %xmm0, %xmm1
movsd %xmm1, 8(%rsp) # 8-byte Spill
movl $.L.str, %edi
movb $1, %al
callq printf
movl $.L.str.1, %edi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movq %rbx, %rdi
movq %r15, %rsi
movl $1024, %edx # imm = 0x400
callq _Z14multiplyDevicePdS_i
movsd (%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movsd %xmm1, (%rsp) # 8-byte Spill
movl $.L.str.2, %edi
movb $1, %al
callq printf
movl $.L.str.3, %edi
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
xorl %eax, %eax
movapd .LCPI6_4(%rip), %xmm0 # xmm0 = [NaN,NaN]
movsd .LCPI6_5(%rip), %xmm1 # xmm1 = mem[0],zero
movq %r14, %rcx
movq %r15, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB6_11: # %.preheader.i22
# =>This Loop Header: Depth=1
# Child Loop BB6_12 Depth 2
xorl %edi, %edi
.p2align 4, 0x90
.LBB6_12: # Parent Loop BB6_11 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rcx,%rdi,8), %xmm2 # xmm2 = mem[0],zero
subsd (%rdx,%rdi,8), %xmm2
andpd %xmm0, %xmm2
xorl %r8d, %r8d
ucomisd %xmm1, %xmm2
seta %r8b
addl %r8d, %esi
incq %rdi
cmpq $1024, %rdi # imm = 0x400
jne .LBB6_12
# %bb.13: # %._crit_edge.i26
# in Loop: Header=BB6_11 Depth=1
incq %rax
addq $8192, %rdx # imm = 0x2000
addq $8192, %rcx # imm = 0x2000
cmpq $1024, %rax # imm = 0x400
jne .LBB6_11
# %bb.14: # %_Z5matchPdS_i.exit
testl %esi, %esi
jle .LBB6_16
# %bb.15:
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
jmp .LBB6_17
.LBB6_16:
movl $.Lstr, %edi
callq puts@PLT
.LBB6_17:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14multiplyKernelPdS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14multiplyKernelPdS_i,@object # @_Z14multiplyKernelPdS_i
.section .rodata,"a",@progbits
.globl _Z14multiplyKernelPdS_i
.p2align 3, 0x0
_Z14multiplyKernelPdS_i:
.quad _Z29__device_stub__multiplyKernelPdS_i
.size _Z14multiplyKernelPdS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Time taken on host (ms) = %lf\n"
.size .L.str, 31
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "FLOPS on host = %lf\n"
.size .L.str.1, 21
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Time taken on device (ms) = %lf\n"
.size .L.str.2, 33
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "FLOPS on device = %lf\n"
.size .L.str.3, 23
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Results did not match. %d mismatches\n"
.size .L.str.4, 38
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14multiplyKernelPdS_i"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Results matched."
.size .Lstr, 17
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__multiplyKernelPdS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14multiplyKernelPdS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14multiplyKernelPdS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R8, c[0x0][0x170] ; /* 0x00005c0000087a02 */
/* 0x000fc80000000f00 */
/*0020*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0050*/ IADD3 R0, R8, -0x1, RZ ; /* 0xffffffff08007810 */
/* 0x000fe20007ffe0ff */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0090*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe40003f06070 */
/*00a0*/ LOP3.LUT R8, R8, 0x3, RZ, 0xc0, !PT ; /* 0x0000000308087812 */
/* 0x000fe400078ec0ff */
/*00b0*/ MOV R0, RZ ; /* 0x000000ff00007202 */
/* 0x000fe20000000f00 */
/*00c0*/ IMAD R2, R5, c[0x0][0x170], R6 ; /* 0x00005c0005027a24 */
/* 0x001fc800078e0206 */
/*00d0*/ IMAD.WIDE R2, R2, R7, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fc800078e0207 */
/*00e0*/ @!P0 BRA 0xd10 ; /* 0x00000c2000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R4, -R8, c[0x0][0x170], RZ ; /* 0x00005c0008047a10 */
/* 0x000fe20007ffe1ff */
/*0100*/ LDG.E.64 R12, [R2.64] ; /* 0x00000004020c7981 */
/* 0x000162000c1e1b00 */
/*0110*/ MOV R0, RZ ; /* 0x000000ff00007202 */
/* 0x000fe20000000f00 */
/*0120*/ IMAD.WIDE R14, R5, R7, c[0x0][0x160] ; /* 0x00005800050e7625 */
/* 0x000fe200078e0207 */
/*0130*/ ISETP.GT.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f04270 */
/*0140*/ IMAD.WIDE R10, R6, R7, c[0x0][0x160] ; /* 0x00005800060a7625 */
/* 0x000fd400078e0207 */
/*0150*/ @!P0 BRA 0xb50 ; /* 0x000009f000008947 */
/* 0x001fea0003800000 */
/*0160*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe40003f24270 */
/*0170*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0180*/ @!P1 BRA 0x7e0 ; /* 0x0000065000009947 */
/* 0x000fea0003800000 */
/*0190*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01a0*/ LDG.E.64 R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x000ea8000c1e1b00 */
/*01b0*/ LDG.E.64 R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000ea2000c1e1b00 */
/*01c0*/ IMAD.WIDE R20, R7, c[0x0][0x170], R10 ; /* 0x00005c0007147a25 */
/* 0x002fe200078e020a */
/*01d0*/ DFMA R16, R16, R18, R12 ; /* 0x000000121010722b */
/* 0x024046000000000c */
/*01e0*/ IMAD.WIDE R18, R7, c[0x0][0x170], R14 ; /* 0x00005c0007127a25 */
/* 0x001fc800078e020e */
/*01f0*/ STG.E.64 [R2.64], R16 ; /* 0x0000001002007986 */
/* 0x0021e8000c101b04 */
/*0200*/ LDG.E.64 R12, [R20.64] ; /* 0x00000004140c7981 */
/* 0x000ea8000c1e1b00 */
/*0210*/ LDG.E.64 R22, [R18.64] ; /* 0x0000000412167981 */
/* 0x000ea2000c1e1b00 */
/*0220*/ IMAD.WIDE R24, R7, c[0x0][0x170], R18 ; /* 0x00005c0007187a25 */
/* 0x000fe200078e0212 */
/*0230*/ DFMA R22, R12, R22, R16 ; /* 0x000000160c16722b */
/* 0x0042860000000010 */
/*0240*/ IMAD.WIDE R12, R7, c[0x0][0x170], R20 ; /* 0x00005c00070c7a25 */
/* 0x002fc800078e0214 */
/*0250*/ STG.E.64 [R2.64], R22 ; /* 0x0000001602007986 */
/* 0x0043e8000c101b04 */
/*0260*/ LDG.E.64 R10, [R12.64] ; /* 0x000000040c0a7981 */
/* 0x000ea8000c1e1b00 */
/*0270*/ LDG.E.64 R14, [R24.64] ; /* 0x00000004180e7981 */
/* 0x000ea2000c1e1b00 */
/*0280*/ IMAD.WIDE R26, R7, c[0x0][0x170], R12 ; /* 0x00005c00071a7a25 */
/* 0x000fe200078e020c */
/*0290*/ DFMA R14, R10, R14, R22 ; /* 0x0000000e0a0e722b */
/* 0x0044c60000000016 */
/*02a0*/ IMAD.WIDE R10, R7, c[0x0][0x170], R24 ; /* 0x00005c00070a7a25 */
/* 0x004fc800078e0218 */
/*02b0*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0085e8000c101b04 */
/*02c0*/ LDG.E.64 R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000ee8000c1e1b00 */
/*02d0*/ LDG.E.64 R16, [R26.64] ; /* 0x000000041a107981 */
/* 0x001ee4000c1e1b00 */
/*02e0*/ DFMA R20, R16, R18, R14 ; /* 0x000000121014722b */
/* 0x0080c4000000000e */
/*02f0*/ IMAD.WIDE R18, R7, c[0x0][0x170], R26 ; /* 0x00005c0007127a25 */
/* 0x001fc800078e021a */
/*0300*/ IMAD.WIDE R16, R7.reuse, c[0x0][0x170], R10 ; /* 0x00005c0007107a25 */
/* 0x040fe200078e020a */
/*0310*/ STG.E.64 [R2.64], R20 ; /* 0x0000001402007986 */
/* 0x0081e8000c101b04 */
/*0320*/ LDG.E.64 R12, [R18.64] ; /* 0x00000004120c7981 */
/* 0x000ee8000c1e1b00 */
/*0330*/ LDG.E.64 R22, [R16.64] ; /* 0x0000000410167981 */
/* 0x002ee2000c1e1b00 */
/*0340*/ IMAD.WIDE R24, R7, c[0x0][0x170], R18 ; /* 0x00005c0007187a25 */
/* 0x000fc800078e0212 */
/*0350*/ IMAD.WIDE R14, R7, c[0x0][0x170], R16 ; /* 0x00005c00070e7a25 */
/* 0x004fe200078e0210 */
/*0360*/ DFMA R22, R12, R22, R20 ; /* 0x000000160c16722b */
/* 0x008e4e0000000014 */
/*0370*/ STG.E.64 [R2.64], R22 ; /* 0x0000001602007986 */
/* 0x0023e8000c101b04 */
/*0380*/ LDG.E.64 R10, [R24.64] ; /* 0x00000004180a7981 */
/* 0x000ea8000c1e1b00 */
/*0390*/ LDG.E.64 R12, [R14.64] ; /* 0x000000040e0c7981 */
/* 0x000ea2000c1e1b00 */
/*03a0*/ IMAD.WIDE R20, R7, c[0x0][0x170], R14 ; /* 0x00005c0007147a25 */
/* 0x001fe200078e020e */
/*03b0*/ DFMA R26, R10, R12, R22 ; /* 0x0000000c0a1a722b */
/* 0x0040860000000016 */
/*03c0*/ IMAD.WIDE R10, R7, c[0x0][0x170], R24 ; /* 0x00005c00070a7a25 */
/* 0x001fc800078e0218 */
/*03d0*/ STG.E.64 [R2.64], R26 ; /* 0x0000001a02007986 */
/* 0x0041e8000c101b04 */
/*03e0*/ LDG.E.64 R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x000ea8000c1e1b00 */
/*03f0*/ LDG.E.64 R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x000ea2000c1e1b00 */
/*0400*/ IMAD.WIDE R18, R7, c[0x0][0x170], R10 ; /* 0x00005c0007127a25 */
/* 0x000fe200078e020a */
/*0410*/ DFMA R16, R12, R16, R26 ; /* 0x000000100c10722b */
/* 0x0044c6000000001a */
/*0420*/ IMAD.WIDE R12, R7, c[0x0][0x170], R20 ; /* 0x00005c00070c7a25 */
/* 0x004fc800078e0214 */
/*0430*/ STG.E.64 [R2.64], R16 ; /* 0x0000001002007986 */
/* 0x0085e8000c101b04 */
/*0440*/ LDG.E.64 R22, [R12.64] ; /* 0x000000040c167981 */
/* 0x002ee8000c1e1b00 */
/*0450*/ LDG.E.64 R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x000ee4000c1e1b00 */
/*0460*/ DFMA R24, R14, R22, R16 ; /* 0x000000160e18722b */
/* 0x0082c40000000010 */
/*0470*/ IMAD.WIDE R22, R7, c[0x0][0x170], R18 ; /* 0x00005c0007167a25 */
/* 0x002fc800078e0212 */
/*0480*/ IMAD.WIDE R14, R7.reuse, c[0x0][0x170], R12 ; /* 0x00005c00070e7a25 */
/* 0x040fe200078e020c */
/*0490*/ STG.E.64 [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x0083e8000c101b04 */
/*04a0*/ LDG.E.64 R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000ee8000c1e1b00 */
/*04b0*/ LDG.E.64 R20, [R14.64] ; /* 0x000000040e147981 */
/* 0x000ee2000c1e1b00 */
/*04c0*/ IMAD.WIDE R26, R7, c[0x0][0x170], R22 ; /* 0x00005c00071a7a25 */
/* 0x001fc800078e0216 */
/*04d0*/ IMAD.WIDE R16, R7, c[0x0][0x170], R14 ; /* 0x00005c0007107a25 */
/* 0x004fe200078e020e */
/*04e0*/ DFMA R20, R10, R20, R24 ; /* 0x000000140a14722b */
/* 0x008e0e0000000018 */
/*04f0*/ STG.E.64 [R2.64], R20 ; /* 0x0000001402007986 */
/* 0x0011e8000c101b04 */
/*0500*/ LDG.E.64 R10, [R26.64] ; /* 0x000000041a0a7981 */
/* 0x000ea8000c1e1b00 */
/*0510*/ LDG.E.64 R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x000ea2000c1e1b00 */
/*0520*/ IMAD.WIDE R24, R7, c[0x0][0x170], R16 ; /* 0x00005c0007187a25 */
/* 0x002fe200078e0210 */
/*0530*/ DFMA R18, R10, R12, R20 ; /* 0x0000000c0a12722b */
/* 0x0042860000000014 */
/*0540*/ IMAD.WIDE R10, R7, c[0x0][0x170], R26 ; /* 0x00005c00070a7a25 */
/* 0x002fc800078e021a */
/*0550*/ STG.E.64 [R2.64], R18 ; /* 0x0000001202007986 */
/* 0x0043e8000c101b04 */
/*0560*/ LDG.E.64 R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x000ea8000c1e1b00 */
/*0570*/ LDG.E.64 R14, [R24.64] ; /* 0x00000004180e7981 */
/* 0x000ea2000c1e1b00 */
/*0580*/ IMAD.WIDE R20, R7, c[0x0][0x170], R10 ; /* 0x00005c0007147a25 */
/* 0x001fe200078e020a */
/*0590*/ DFMA R14, R12, R14, R18 ; /* 0x0000000e0c0e722b */
/* 0x0040860000000012 */
/*05a0*/ IMAD.WIDE R12, R7, c[0x0][0x170], R24 ; /* 0x00005c00070c7a25 */
/* 0x001fc800078e0218 */
/*05b0*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0041e8000c101b04 */
/*05c0*/ LDG.E.64 R22, [R12.64] ; /* 0x000000040c167981 */
/* 0x000ea8000c1e1b00 */
/*05d0*/ LDG.E.64 R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x000ea4000c1e1b00 */
/*05e0*/ DFMA R26, R16, R22, R14 ; /* 0x00000016101a722b */
/* 0x0044c4000000000e */
/*05f0*/ IMAD.WIDE R22, R7, c[0x0][0x170], R20 ; /* 0x00005c0007167a25 */
/* 0x004fc800078e0214 */
/*0600*/ IMAD.WIDE R16, R7.reuse, c[0x0][0x170], R12 ; /* 0x00005c0007107a25 */
/* 0x040fe200078e020c */
/*0610*/ STG.E.64 [R2.64], R26 ; /* 0x0000001a02007986 */
/* 0x0085e8000c101b04 */
/*0620*/ LDG.E.64 R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000ee8000c1e1b00 */
/*0630*/ LDG.E.64 R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x002ee2000c1e1b00 */
/*0640*/ IMAD.WIDE R24, R7, c[0x0][0x170], R22 ; /* 0x00005c0007187a25 */
/* 0x000fc800078e0216 */
/*0650*/ IMAD.WIDE R14, R7, c[0x0][0x170], R16 ; /* 0x00005c00070e7a25 */
/* 0x001fe200078e0210 */
/*0660*/ DFMA R18, R10, R18, R26 ; /* 0x000000120a12722b */
/* 0x008e0e000000001a */
/*0670*/ STG.E.64 [R2.64], R18 ; /* 0x0000001202007986 */
/* 0x0011e8000c101b04 */
/*0680*/ LDG.E.64 R10, [R24.64] ; /* 0x00000004180a7981 */
/* 0x000ee8000c1e1b00 */
/*0690*/ LDG.E.64 R12, [R14.64] ; /* 0x000000040e0c7981 */
/* 0x000ee2000c1e1b00 */
/*06a0*/ IMAD.WIDE R26, R7, c[0x0][0x170], R14 ; /* 0x00005c00071a7a25 */
/* 0x004fe200078e020e */
/*06b0*/ DFMA R20, R10, R12, R18 ; /* 0x0000000c0a14722b */
/* 0x0082860000000012 */
/*06c0*/ IMAD.WIDE R10, R7, c[0x0][0x170], R24 ; /* 0x00005c00070a7a25 */
/* 0x002fc800078e0218 */
/*06d0*/ STG.E.64 [R2.64], R20 ; /* 0x0000001402007986 */
/* 0x0043e8000c101b04 */
/*06e0*/ LDG.E.64 R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x000ea8000c1e1b00 */
/*06f0*/ LDG.E.64 R16, [R26.64] ; /* 0x000000041a107981 */
/* 0x000ea2000c1e1b00 */
/*0700*/ IMAD.WIDE R18, R7, c[0x0][0x170], R10 ; /* 0x00005c0007127a25 */
/* 0x001fe200078e020a */
/*0710*/ DFMA R22, R12, R16, R20 ; /* 0x000000100c16722b */
/* 0x0040860000000014 */
/*0720*/ IMAD.WIDE R16, R7, c[0x0][0x170], R26 ; /* 0x00005c0007107a25 */
/* 0x001fc800078e021a */
/*0730*/ STG.E.64 [R2.64], R22 ; /* 0x0000001602007986 */
/* 0x0043e8000c101b04 */
/*0740*/ LDG.E.64 R14, [R16.64] ; /* 0x00000004100e7981 */
/* 0x000ea8000c1e1b00 */
/*0750*/ LDG.E.64 R12, [R18.64] ; /* 0x00000004120c7981 */
/* 0x000ea2000c1e1b00 */
/*0760*/ IADD3 R4, R4, -0x10, RZ ; /* 0xfffffff004047810 */
/* 0x000fe20007ffe0ff */
/*0770*/ IMAD.WIDE R10, R7, c[0x0][0x170], R18 ; /* 0x00005c00070a7a25 */
/* 0x000fe200078e0212 */
/*0780*/ IADD3 R0, R0, 0x10, RZ ; /* 0x0000001000007810 */
/* 0x000fc40007ffe0ff */
/*0790*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe20003f24270 */
/*07a0*/ DFMA R12, R12, R14, R22 ; /* 0x0000000e0c0c722b */
/* 0x0040a40000000016 */
/*07b0*/ IMAD.WIDE R14, R7, c[0x0][0x170], R16 ; /* 0x00005c00070e7a25 */
/* 0x001fca00078e0210 */
/*07c0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0043ea000c101b04 */
/*07d0*/ @P1 BRA 0x1a0 ; /* 0xfffff9c000001947 */
/* 0x000fea000383ffff */
/*07e0*/ ISETP.GT.AND P1, PT, R4, 0x4, PT ; /* 0x000000040400780c */
/* 0x000fda0003f24270 */
/*07f0*/ @!P1 BRA 0xb30 ; /* 0x0000033000009947 */
/* 0x000fea0003800000 */
/*0800*/ LDG.E.64 R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x000ea8000c1e1b00 */
/*0810*/ LDG.E.64 R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000ea2000c1e1b00 */
/*0820*/ IMAD.WIDE R20, R7, c[0x0][0x170], R10 ; /* 0x00005c0007147a25 */
/* 0x002fe200078e020a */
/*0830*/ DFMA R16, R16, R18, R12 ; /* 0x000000121010722b */
/* 0x024046000000000c */
/*0840*/ IMAD.WIDE R18, R7, c[0x0][0x170], R14 ; /* 0x00005c0007127a25 */
/* 0x001fc800078e020e */
/*0850*/ STG.E.64 [R2.64], R16 ; /* 0x0000001002007986 */
/* 0x0021e8000c101b04 */
/*0860*/ LDG.E.64 R12, [R20.64] ; /* 0x00000004140c7981 */
/* 0x000ea8000c1e1b00 */
/*0870*/ LDG.E.64 R22, [R18.64] ; /* 0x0000000412167981 */
/* 0x000ea2000c1e1b00 */
/*0880*/ IMAD.WIDE R24, R7, c[0x0][0x170], R18 ; /* 0x00005c0007187a25 */
/* 0x000fe200078e0212 */
/*0890*/ DFMA R22, R12, R22, R16 ; /* 0x000000160c16722b */
/* 0x0042860000000010 */
/*08a0*/ IMAD.WIDE R12, R7, c[0x0][0x170], R20 ; /* 0x00005c00070c7a25 */
/* 0x002fc800078e0214 */
/*08b0*/ STG.E.64 [R2.64], R22 ; /* 0x0000001602007986 */
/* 0x0043e8000c101b04 */
/*08c0*/ LDG.E.64 R10, [R12.64] ; /* 0x000000040c0a7981 */
/* 0x000ea8000c1e1b00 */
/*08d0*/ LDG.E.64 R14, [R24.64] ; /* 0x00000004180e7981 */
/* 0x000ea2000c1e1b00 */
/*08e0*/ IMAD.WIDE R26, R7, c[0x0][0x170], R12 ; /* 0x00005c00071a7a25 */
/* 0x000fe200078e020c */
/*08f0*/ DFMA R14, R10, R14, R22 ; /* 0x0000000e0a0e722b */
/* 0x0044c60000000016 */
/*0900*/ IMAD.WIDE R10, R7, c[0x0][0x170], R24 ; /* 0x00005c00070a7a25 */
/* 0x004fc800078e0218 */
/*0910*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0085e8000c101b04 */
/*0920*/ LDG.E.64 R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000ee8000c1e1b00 */
/*0930*/ LDG.E.64 R16, [R26.64] ; /* 0x000000041a107981 */
/* 0x001ee4000c1e1b00 */
/*0940*/ DFMA R20, R16, R18, R14 ; /* 0x000000121014722b */
/* 0x0080c4000000000e */
/*0950*/ IMAD.WIDE R18, R7, c[0x0][0x170], R26 ; /* 0x00005c0007127a25 */
/* 0x001fc800078e021a */
/*0960*/ IMAD.WIDE R16, R7.reuse, c[0x0][0x170], R10 ; /* 0x00005c0007107a25 */
/* 0x040fe200078e020a */
/*0970*/ STG.E.64 [R2.64], R20 ; /* 0x0000001402007986 */
/* 0x0081e8000c101b04 */
/*0980*/ LDG.E.64 R12, [R18.64] ; /* 0x00000004120c7981 */
/* 0x000ee8000c1e1b00 */
/*0990*/ LDG.E.64 R22, [R16.64] ; /* 0x0000000410167981 */
/* 0x002ee2000c1e1b00 */
/*09a0*/ IMAD.WIDE R14, R7, c[0x0][0x170], R16 ; /* 0x00005c00070e7a25 */
/* 0x004fe200078e0210 */
/*09b0*/ DFMA R12, R12, R22, R20 ; /* 0x000000160c0c722b */
/* 0x0082860000000014 */
/*09c0*/ IMAD.WIDE R22, R7, c[0x0][0x170], R18 ; /* 0x00005c0007167a25 */
/* 0x002fc800078e0212 */
/*09d0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0043e8000c101b04 */
/*09e0*/ LDG.E.64 R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000ea8000c1e1b00 */
/*09f0*/ LDG.E.64 R24, [R14.64] ; /* 0x000000040e187981 */
/* 0x000ea2000c1e1b00 */
/*0a00*/ IMAD.WIDE R20, R7, c[0x0][0x170], R14 ; /* 0x00005c0007147a25 */
/* 0x001fe200078e020e */
/*0a10*/ DFMA R24, R10, R24, R12 ; /* 0x000000180a18722b */
/* 0x004086000000000c */
/*0a20*/ IMAD.WIDE R10, R7, c[0x0][0x170], R22 ; /* 0x00005c00070a7a25 */
/* 0x001fc800078e0216 */
/*0a30*/ STG.E.64 [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x0041e8000c101b04 */
/*0a40*/ LDG.E.64 R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x000ea8000c1e1b00 */
/*0a50*/ LDG.E.64 R18, [R20.64] ; /* 0x0000000414127981 */
/* 0x000ea2000c1e1b00 */
/*0a60*/ IMAD.WIDE R26, R7, c[0x0][0x170], R10 ; /* 0x00005c00071a7a25 */
/* 0x000fe200078e020a */
/*0a70*/ DFMA R18, R16, R18, R24 ; /* 0x000000121012722b */
/* 0x0044c60000000018 */
/*0a80*/ IMAD.WIDE R16, R7, c[0x0][0x170], R20 ; /* 0x00005c0007107a25 */
/* 0x004fc800078e0214 */
/*0a90*/ STG.E.64 [R2.64], R18 ; /* 0x0000001202007986 */
/* 0x0081e8000c101b04 */
/*0aa0*/ LDG.E.64 R14, [R16.64] ; /* 0x00000004100e7981 */
/* 0x000ea8000c1e1b00 */
/*0ab0*/ LDG.E.64 R12, [R26.64] ; /* 0x000000041a0c7981 */
/* 0x002ea2000c1e1b00 */
/*0ac0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0ad0*/ IMAD.WIDE R10, R7, c[0x0][0x170], R26 ; /* 0x00005c00070a7a25 */
/* 0x000fe200078e021a */
/*0ae0*/ IADD3 R0, R0, 0x8, RZ ; /* 0x0000000800007810 */
/* 0x000fc40007ffe0ff */
/*0af0*/ IADD3 R4, R4, -0x8, RZ ; /* 0xfffffff804047810 */
/* 0x000fe20007ffe0ff */
/*0b00*/ DFMA R12, R12, R14, R18 ; /* 0x0000000e0c0c722b */
/* 0x0042a40000000012 */
/*0b10*/ IMAD.WIDE R14, R7, c[0x0][0x170], R16 ; /* 0x00005c00070e7a25 */
/* 0x002fca00078e0210 */
/*0b20*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0041e8000c101b04 */
/*0b30*/ ISETP.NE.OR P0, PT, R4, RZ, P0 ; /* 0x000000ff0400720c */
/* 0x000fda0000705670 */
/*0b40*/ @!P0 BRA 0xd10 ; /* 0x000001c000008947 */
/* 0x000fea0003800000 */
/*0b50*/ LDG.E.64 R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x000ea8000c1e1b00 */
/*0b60*/ LDG.E.64 R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x001ea2000c1e1b00 */
/*0b70*/ IMAD.WIDE R26, R7, c[0x0][0x170], R10 ; /* 0x00005c00071a7a25 */
/* 0x000fc800078e020a */
/*0b80*/ IMAD.WIDE R24, R7, c[0x0][0x170], R14 ; /* 0x00005c0007187a25 */
/* 0x000fe200078e020e */
/*0b90*/ DFMA R12, R16, R18, R12 ; /* 0x00000012100c722b */
/* 0x026e0e000000000c */
/*0ba0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b04 */
/*0bb0*/ LDG.E.64 R16, [R26.64] ; /* 0x000000041a107981 */
/* 0x000ea8000c1e1b00 */
/*0bc0*/ LDG.E.64 R18, [R24.64] ; /* 0x0000000418127981 */
/* 0x000ea2000c1e1b00 */
/*0bd0*/ IMAD.WIDE R28, R7, c[0x0][0x170], R24 ; /* 0x00005c00071c7a25 */
/* 0x000fe200078e0218 */
/*0be0*/ DFMA R20, R16, R18, R12 ; /* 0x000000121014722b */
/* 0x004286000000000c */
/*0bf0*/ IMAD.WIDE R16, R7, c[0x0][0x170], R26 ; /* 0x00005c0007107a25 */
/* 0x002fc800078e021a */
/*0c00*/ STG.E.64 [R2.64], R20 ; /* 0x0000001402007986 */
/* 0x0043e8000c101b04 */
/*0c10*/ LDG.E.64 R10, [R16.64] ; /* 0x00000004100a7981 */
/* 0x0004e8000c1e1b00 */
/*0c20*/ LDG.E.64 R14, [R28.64] ; /* 0x000000041c0e7981 */
/* 0x000ee2000c1e1b00 */
/*0c30*/ IMAD.WIDE R18, R7, c[0x0][0x170], R28 ; /* 0x00005c0007127a25 */
/* 0x000fc800078e021c */
/*0c40*/ IMAD.WIDE R16, R7, c[0x0][0x170], R16 ; /* 0x00005c0007107a25 */
/* 0x004fe200078e0210 */
/*0c50*/ DFMA R22, R10, R14, R20 ; /* 0x0000000e0a16722b */
/* 0x008e8e0000000014 */
/*0c60*/ STG.E.64 [R2.64], R22 ; /* 0x0000001602007986 */
/* 0x0043e8000c101b04 */
/*0c70*/ LDG.E.64 R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x000ea8000c1e1b00 */
/*0c80*/ LDG.E.64 R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x001ea2000c1e1b00 */
/*0c90*/ IADD3 R4, R4, -0x4, RZ ; /* 0xfffffffc04047810 */
/* 0x000fe20007ffe0ff */
/*0ca0*/ IMAD.WIDE R14, R7, c[0x0][0x170], R18 ; /* 0x00005c00070e7a25 */
/* 0x000fe200078e0212 */
/*0cb0*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x000fc40007ffe0ff */
/*0cc0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*0cd0*/ DFMA R12, R12, R10, R22 ; /* 0x0000000a0c0c722b */
/* 0x0040a40000000016 */
/*0ce0*/ IMAD.WIDE R10, R7, c[0x0][0x170], R16 ; /* 0x00005c00070a7a25 */
/* 0x001fca00078e0210 */
/*0cf0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0043ea000c101b04 */
/*0d00*/ @P0 BRA 0xb50 ; /* 0xfffffe4000000947 */
/* 0x002fea000383ffff */
/*0d10*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f05270 */
/*0d20*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0d30*/ LDG.E.64 R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000562000c1e1b00 */
/*0d40*/ IMAD R4, R0.reuse, c[0x0][0x170], R6 ; /* 0x00005c0000047a24 */
/* 0x040fe400078e0206 */
/*0d50*/ IMAD R0, R0, c[0x0][0x170], R5 ; /* 0x00005c0000007a24 */
/* 0x000fe400078e0205 */
/*0d60*/ IMAD.WIDE R4, R4, R7, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0207 */
/*0d70*/ IMAD.WIDE R12, R0, R7, c[0x0][0x160] ; /* 0x00005800000c7625 */
/* 0x023fc800078e0207 */
/*0d80*/ LDG.E.64 R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x0010e8000c1e1b00 */
/*0d90*/ LDG.E.64 R16, [R12.64] ; /* 0x000000040c107981 */
/* 0x0002e2000c1e1b00 */
/*0da0*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */
/* 0x000fc80007ffe0ff */
/*0db0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*0dc0*/ IMAD.WIDE R4, R7, c[0x0][0x170], R4 ; /* 0x00005c0007047a25 */
/* 0x001fc800078e0204 */
/*0dd0*/ IMAD.WIDE R12, R7, c[0x0][0x170], R12 ; /* 0x00005c00070c7a25 */
/* 0x002fe200078e020c */
/*0de0*/ DFMA R10, R14, R16, R10 ; /* 0x000000100e0a722b */
/* 0x008e0e000000000a */
/*0df0*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0011e2000c101b04 */
/*0e00*/ @P0 BRA 0xd80 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0e10*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0e20*/ BRA 0xe20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14multiplyKernelPdS_i
.globl _Z14multiplyKernelPdS_i
.p2align 8
.type _Z14multiplyKernelPdS_i,@function
_Z14multiplyKernelPdS_i:
s_load_b32 s4, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_3
s_mov_b32 s6, s15
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, s6, s4, v[0:1]
s_ashr_i32 s7, s15, 31
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[2:3], 3, v[1:2]
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_lshl_b64 s[2:3], s[6:7], 3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_add_u32 s2, s0, s2
global_load_b64 v[4:5], v[2:3], off
s_addc_u32 s3, s1, s3
s_ashr_i32 s5, s4, 31
s_lshl_b64 s[6:7], s[4:5], 3
s_mov_b32 s5, s4
.p2align 6
.LBB0_2:
v_lshlrev_b64 v[6:7], 3, v[0:1]
s_add_i32 s5, s5, -1
v_add_nc_u32_e32 v0, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
global_load_b64 v[8:9], v1, s[2:3]
global_load_b64 v[6:7], v[6:7], off
s_add_u32 s2, s2, s6
s_addc_u32 s3, s3, s7
s_cmp_lg_u32 s5, 0
s_waitcnt vmcnt(0)
v_fma_f64 v[4:5], v[8:9], v[6:7], v[4:5]
global_store_b64 v[2:3], v[4:5], off
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14multiplyKernelPdS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14multiplyKernelPdS_i, .Lfunc_end0-_Z14multiplyKernelPdS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14multiplyKernelPdS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14multiplyKernelPdS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00066e6a_00000000-6_matrix_mult.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4initPPdS0_S0_i
.type _Z4initPPdS0_S0_i, @function
_Z4initPPdS0_S0_i:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r12
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, %r14d
movl %ecx, %eax
imull %ecx, %eax
sall $3, %eax
cltq
movq %rax, 8(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, (%r12)
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
testl %r14d, %r14d
jle .L4
movslq %r14d, %rax
leaq 0(,%rax,8), %r15
negq %rax
salq $3, %rax
movq %rax, (%rsp)
movq %r15, %rbp
movl $0, %r13d
.L5:
movq (%rsp), %rax
leaq 0(%rbp,%rax), %rbx
.L6:
call rand@PLT
movq (%r12), %rdx
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC0(%rip), %xmm0
addsd .LC1(%rip), %xmm0
movsd %xmm0, (%rdx,%rbx)
addq $8, %rbx
cmpq %rbp, %rbx
jne .L6
addl $1, %r13d
addq %r15, %rbp
cmpl %r13d, %r14d
jne .L5
.L4:
movq 8(%rsp), %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rdi
movq 16(%rsp), %rax
movq %rdi, (%rax)
movq %rbx, %rcx
movq %rbx, %rdx
movl $0, %esi
call __memset_chk@PLT
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rdi
movq 24(%rsp), %rax
movq %rdi, (%rax)
movq %rbx, %rcx
movq %rbx, %rdx
movl $0, %esi
call __memset_chk@PLT
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z4initPPdS0_S0_i, .-_Z4initPPdS0_S0_i
.globl _Z7cleanupPPdS0_S0_
.type _Z7cleanupPPdS0_S0_, @function
_Z7cleanupPPdS0_S0_:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbp
movq %rdx, %rbx
movq (%rdi), %rdi
call free@PLT
movq 0(%rbp), %rdi
call free@PLT
movq (%rbx), %rdi
call free@PLT
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z7cleanupPPdS0_S0_, .-_Z7cleanupPPdS0_S0_
.globl _Z12multiplyHostPdS_i
.type _Z12multiplyHostPdS_i, @function
_Z12multiplyHostPdS_i:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r13
movq %rsi, %rbp
movl %edx, %ebx
call clock@PLT
movq %rax, %r12
testl %ebx, %ebx
jle .L12
movslq %ebx, %r11
movq %r13, %r8
leaq 0(,%r11,8), %rdi
movq %r11, %r9
movl $0, %r10d
.L13:
movq %r10, %rsi
negq %rsi
movq %rbp, %rcx
.L16:
movq %r8, %rax
movl $0, %edx
.L14:
movsd (%rax), %xmm0
mulsd (%rax,%rsi,8), %xmm0
addsd (%rcx), %xmm0
movsd %xmm0, (%rcx)
addl $1, %edx
addq %rdi, %rax
cmpl %edx, %ebx
jne .L14
addq $8, %rcx
addq $1, %rsi
cmpq %r9, %rsi
jne .L16
addq $1, %r10
subq $1, %r9
addq $8, %r8
addq %rdi, %rbp
cmpq %r11, %r10
jne .L13
.L12:
call clock@PLT
subq %r12, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC2(%rip), %xmm0
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z12multiplyHostPdS_i, .-_Z12multiplyHostPdS_i
.globl _Z5matchPdS_i
.type _Z5matchPdS_i, @function
_Z5matchPdS_i:
.LFB2061:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L25
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %r8
movq %rsi, %r9
movslq %edx, %r11
leaq 0(,%r11,8), %rbx
negq %r11
salq $3, %r11
movq %rbx, %rdi
movl $0, %ecx
movl $0, %r10d
movq .LC3(%rip), %xmm2
movsd .LC4(%rip), %xmm1
.L21:
leaq (%rdi,%r11), %rax
.L24:
movsd (%r8,%rax), %xmm0
subsd (%r9,%rax), %xmm0
andpd %xmm2, %xmm0
comisd %xmm1, %xmm0
seta %sil
movzbl %sil, %esi
addl %esi, %ecx
addq $8, %rax
cmpq %rdi, %rax
jne .L24
addl $1, %r10d
addq %rbx, %rdi
cmpl %r10d, %edx
jne .L21
movl %ecx, %eax
popq %rbx
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore 3
movl $0, %ecx
movl %ecx, %eax
ret
.cfi_endproc
.LFE2061:
.size _Z5matchPdS_i, .-_Z5matchPdS_i
.globl _Z37__device_stub__Z14multiplyKernelPdS_iPdS_i
.type _Z37__device_stub__Z14multiplyKernelPdS_iPdS_i, @function
_Z37__device_stub__Z14multiplyKernelPdS_iPdS_i:
.LFB2087:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L36
.L32:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L37
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14multiplyKernelPdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L32
.L37:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z37__device_stub__Z14multiplyKernelPdS_iPdS_i, .-_Z37__device_stub__Z14multiplyKernelPdS_iPdS_i
.globl _Z14multiplyKernelPdS_i
.type _Z14multiplyKernelPdS_i, @function
_Z14multiplyKernelPdS_i:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z14multiplyKernelPdS_iPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z14multiplyKernelPdS_i, .-_Z14multiplyKernelPdS_i
.globl _Z14multiplyDevicePdS_i
.type _Z14multiplyDevicePdS_i, @function
_Z14multiplyDevicePdS_i:
.LFB2060:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $88, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %rbp
movq %rsi, %r13
movl %edx, %r12d
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl %edx, %ebx
imull %edx, %ebx
sall $3, %ebx
movslq %ebx, %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %r12d, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl %r12d, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L44
.L41:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 12(%rsp)
leaq 12(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L45
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
movl %r12d, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z37__device_stub__Z14multiplyKernelPdS_iPdS_i
jmp .L41
.L45:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z14multiplyDevicePdS_i, .-_Z14multiplyDevicePdS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "Time taken on host (ms) = %lf\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC8:
.string "FLOPS on host = %lf\n"
.section .rodata.str1.8
.align 8
.LC9:
.string "Time taken on device (ms) = %lf\n"
.section .rodata.str1.1
.LC10:
.string "FLOPS on device = %lf\n"
.section .rodata.str1.8
.align 8
.LC11:
.string "Results did not match. %d mismatches\n"
.section .rodata.str1.1
.LC12:
.string "Results matched.\n"
.text
.globl main
.type main, @function
main:
.LFB2062:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdi
movl $1024, %ecx
call _Z4initPPdS0_S0_i
movq 24(%rsp), %rbx
movq 16(%rsp), %r12
movl $1024, %edx
movq %rbx, %rsi
movq %r12, %rdi
call _Z12multiplyHostPdS_i
movsd .LC6(%rip), %xmm1
divsd %xmm0, %xmm1
movq %xmm1, %rbp
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbp, %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 32(%rsp), %rbp
movl $1024, %edx
movq %rbp, %rsi
movq %r12, %rdi
call _Z14multiplyDevicePdS_i
movsd .LC6(%rip), %xmm2
divsd %xmm0, %xmm2
movsd %xmm2, 8(%rsp)
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $1024, %edx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z5matchPdS_i
testl %eax, %eax
jle .L47
movl %eax, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L48:
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdi
call _Z7cleanupPPdS0_S0_
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L51
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L48
.L51:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z14multiplyKernelPdS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z14multiplyKernelPdS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -4194304
.long 1105199103
.align 8
.LC1:
.long 0
.long 1072693248
.align 8
.LC2:
.long 0
.long 1083129856
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC3:
.long -1
.long 2147483647
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC4:
.long -1598689907
.long 1051772663
.align 8
.LC6:
.long 0
.long 1115635712
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrix_mult.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z4initPPdS0_S0_i
.LCPI0_0:
.quad 0x41dfffffffc00000 # double 2147483647
.LCPI0_1:
.quad 0x3ff0000000000000 # double 1
.text
.globl _Z4initPPdS0_S0_i
.p2align 4, 0x90
.type _Z4initPPdS0_S0_i,@function
_Z4initPPdS0_S0_i: # @_Z4initPPdS0_S0_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebx
movq %rdx, 32(%rsp) # 8-byte Spill
movq %rsi, 16(%rsp) # 8-byte Spill
movq %rdi, %r12
movl %ecx, %eax
imull %ecx, %eax
shll $3, %eax
movslq %eax, %rdi
movq %rdi, 24(%rsp) # 8-byte Spill
callq malloc
movq %rax, (%r12)
xorl %ebp, %ebp
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl %ebx, 12(%rsp) # 4-byte Spill
testl %ebx, %ebx
jle .LBB0_5
# %bb.1: # %.preheader.lr.ph
movl 12(%rsp), %r14d # 4-byte Reload
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_3 Depth 2
movl %ebp, %ebp
movq %r14, %rbx
movq %rbp, %r13
.p2align 4, 0x90
.LBB0_3: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movsd .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd %xmm1, %xmm0
movsd .LCPI0_1(%rip), %xmm1 # xmm1 = mem[0],zero
addsd %xmm1, %xmm0
movq (%r12), %rax
movsd %xmm0, (%rax,%r13,8)
incq %r13
decq %rbx
jne .LBB0_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
incq %r15
addl 12(%rsp), %ebp # 4-byte Folded Reload
cmpq %r14, %r15
jne .LBB0_2
.LBB0_5: # %._crit_edge25
movq 24(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
callq malloc
movq 16(%rsp), %rcx # 8-byte Reload
movq %rax, (%rcx)
movq %rax, %rdi
xorl %esi, %esi
movq %rbx, %rdx
callq memset@PLT
movq %rbx, %rdi
callq malloc
movq 32(%rsp), %rcx # 8-byte Reload
movq %rax, (%rcx)
movq %rax, %rdi
xorl %esi, %esi
movq %rbx, %rdx
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp memset@PLT # TAILCALL
.Lfunc_end0:
.size _Z4initPPdS0_S0_i, .Lfunc_end0-_Z4initPPdS0_S0_i
.cfi_endproc
# -- End function
.globl _Z7cleanupPPdS0_S0_ # -- Begin function _Z7cleanupPPdS0_S0_
.p2align 4, 0x90
.type _Z7cleanupPPdS0_S0_,@function
_Z7cleanupPPdS0_S0_: # @_Z7cleanupPPdS0_S0_
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdx, %rbx
movq %rsi, %r14
movq (%rdi), %rdi
callq free
movq (%r14), %rdi
callq free
movq (%rbx), %rdi
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp free # TAILCALL
.Lfunc_end1:
.size _Z7cleanupPPdS0_S0_, .Lfunc_end1-_Z7cleanupPPdS0_S0_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z12multiplyHostPdS_i
.LCPI2_0:
.quad 0x408f400000000000 # double 1000
.text
.globl _Z12multiplyHostPdS_i
.p2align 4, 0x90
.type _Z12multiplyHostPdS_i,@function
_Z12multiplyHostPdS_i: # @_Z12multiplyHostPdS_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movq %rsi, %r14
movq %rdi, %r15
callq clock
movq %rax, %rbx
testl %ebp, %ebp
jle .LBB2_7
# %bb.1: # %.preheader25.lr.ph
movl %ebp, %eax
leaq (,%rax,8), %rcx
xorl %edx, %edx
xorl %esi, %esi
.p2align 4, 0x90
.LBB2_2: # %.preheader25
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
# Child Loop BB2_4 Depth 3
movq %rsi, %rdi
imulq %rax, %rdi
leaq (%r14,%rdi,8), %rdi
xorl %r8d, %r8d
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB2_3: # %.preheader
# Parent Loop BB2_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_4 Depth 3
movsd (%rdi,%r9,8), %xmm0 # xmm0 = mem[0],zero
movq %rax, %r10
movq %r15, %r11
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_2 Depth=1
# Parent Loop BB2_3 Depth=2
# => This Inner Loop Header: Depth=3
movsd (%r11,%rdx), %xmm1 # xmm1 = mem[0],zero
mulsd (%r11,%r8), %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, (%rdi,%r9,8)
addq %rcx, %r11
decq %r10
jne .LBB2_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB2_3 Depth=2
incq %r9
addq $8, %r8
cmpq %rax, %r9
jne .LBB2_3
# %bb.6: # %._crit_edge28
# in Loop: Header=BB2_2 Depth=1
incq %rsi
addq $8, %rdx
cmpq %rax, %rsi
jne .LBB2_2
.LBB2_7: # %._crit_edge30
callq clock
subq %rbx, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI2_0(%rip), %xmm0
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z12multiplyHostPdS_i, .Lfunc_end2-_Z12multiplyHostPdS_i
.cfi_endproc
# -- End function
.globl _Z29__device_stub__multiplyKernelPdS_i # -- Begin function _Z29__device_stub__multiplyKernelPdS_i
.p2align 4, 0x90
.type _Z29__device_stub__multiplyKernelPdS_i,@function
_Z29__device_stub__multiplyKernelPdS_i: # @_Z29__device_stub__multiplyKernelPdS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14multiplyKernelPdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z29__device_stub__multiplyKernelPdS_i, .Lfunc_end3-_Z29__device_stub__multiplyKernelPdS_i
.cfi_endproc
# -- End function
.globl _Z14multiplyDevicePdS_i # -- Begin function _Z14multiplyDevicePdS_i
.p2align 4, 0x90
.type _Z14multiplyDevicePdS_i,@function
_Z14multiplyDevicePdS_i: # @_Z14multiplyDevicePdS_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $136, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movq %rsi, %rbx
movq %rdi, %r15
movl %edx, %eax
imull %edx, %eax
shll $3, %eax
movslq %eax, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl %ebp, %eax
movabsq $4294967296, %r15 # imm = 0x100000000
orq %rax, %r15
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_2
# %bb.1:
movq 24(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movl %ebp, 36(%rsp)
leaq 128(%rsp), %rax
movq %rax, 48(%rsp)
leaq 120(%rsp), %rax
movq %rax, 56(%rsp)
leaq 36(%rsp), %rax
movq %rax, 64(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z14multiplyKernelPdS_i, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_2:
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movl $0, 48(%rsp)
movq 40(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
addq $136, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z14multiplyDevicePdS_i, .Lfunc_end4-_Z14multiplyDevicePdS_i
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z5matchPdS_i
.LCPI5_0:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI5_1:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z5matchPdS_i
.p2align 4, 0x90
.type _Z5matchPdS_i,@function
_Z5matchPdS_i: # @_Z5matchPdS_i
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB5_1
# %bb.3: # %.preheader.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl %edx, %ecx
xorl %r8d, %r8d
movapd .LCPI5_0(%rip), %xmm0 # xmm0 = [NaN,NaN]
movsd .LCPI5_1(%rip), %xmm1 # xmm1 = mem[0],zero
xorl %r9d, %r9d
xorl %eax, %eax
.p2align 4, 0x90
.LBB5_4: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB5_5 Depth 2
movl %r8d, %r11d
leaq (%rsi,%r11,8), %r10
leaq (%rdi,%r11,8), %r11
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB5_5: # Parent Loop BB5_4 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r11,%rbx,8), %xmm2 # xmm2 = mem[0],zero
subsd (%r10,%rbx,8), %xmm2
andpd %xmm0, %xmm2
xorl %ebp, %ebp
ucomisd %xmm1, %xmm2
seta %bpl
addl %ebp, %eax
incq %rbx
cmpq %rbx, %rcx
jne .LBB5_5
# %bb.6: # %._crit_edge
# in Loop: Header=BB5_4 Depth=1
incq %r9
addl %edx, %r8d
cmpq %rcx, %r9
jne .LBB5_4
# %bb.7:
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %rbp
retq
.LBB5_1:
xorl %eax, %eax
retq
.Lfunc_end5:
.size _Z5matchPdS_i, .Lfunc_end5-_Z5matchPdS_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI6_0:
.quad 0x41dfffffffc00000 # double 2147483647
.LCPI6_1:
.quad 0x3ff0000000000000 # double 1
.LCPI6_2:
.quad 0x408f400000000000 # double 1000
.LCPI6_3:
.quad 0x427f400000000000 # double 2147483648000
.LCPI6_5:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI6_4:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $8388608, %edi # imm = 0x800000
callq malloc
movq %rax, %rbx
xorl %r14d, %r14d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movq %rbx, %r15
.p2align 4, 0x90
.LBB6_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB6_2 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB6_2: # Parent Loop BB6_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movsd .LCPI6_0(%rip), %xmm1 # xmm1 = mem[0],zero
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd %xmm1, %xmm0
movsd .LCPI6_1(%rip), %xmm1 # xmm1 = mem[0],zero
addsd %xmm1, %xmm0
movsd %xmm0, (%r15,%r12,8)
incq %r12
cmpq $1024, %r12 # imm = 0x400
jne .LBB6_2
# %bb.3: # %._crit_edge.i
# in Loop: Header=BB6_1 Depth=1
incq %r14
addq $8192, %r15 # imm = 0x2000
cmpq $1024, %r14 # imm = 0x400
jne .LBB6_1
# %bb.4: # %_Z4initPPdS0_S0_i.exit
movl $8388608, %edi # imm = 0x800000
callq malloc
movq %rax, %r14
xorl %r13d, %r13d
movl $8388608, %edx # imm = 0x800000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
movl $8388608, %edi # imm = 0x800000
callq malloc
movq %rax, %r15
movl $8388608, %edx # imm = 0x800000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
callq clock
movq %rax, %r12
movq %rbx, %rax
.p2align 4, 0x90
.LBB6_5: # %.preheader25.i
# =>This Loop Header: Depth=1
# Child Loop BB6_6 Depth 2
# Child Loop BB6_7 Depth 3
movq %r13, %rcx
shlq $13, %rcx
addq %r14, %rcx
movq %rbx, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB6_6: # %.preheader.i17
# Parent Loop BB6_5 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB6_7 Depth 3
movsd (%rcx,%rsi,8), %xmm0 # xmm0 = mem[0],zero
xorl %edi, %edi
.p2align 4, 0x90
.LBB6_7: # Parent Loop BB6_5 Depth=1
# Parent Loop BB6_6 Depth=2
# => This Inner Loop Header: Depth=3
movsd (%rax,%rdi), %xmm1 # xmm1 = mem[0],zero
mulsd (%rdx,%rdi), %xmm1
addsd %xmm1, %xmm0
addq $8192, %rdi # imm = 0x2000
cmpq $8388608, %rdi # imm = 0x800000
jne .LBB6_7
# %bb.8: # %._crit_edge.i21
# in Loop: Header=BB6_6 Depth=2
movsd %xmm0, (%rcx,%rsi,8)
incq %rsi
addq $8, %rdx
cmpq $1024, %rsi # imm = 0x400
jne .LBB6_6
# %bb.9: # %._crit_edge28.i
# in Loop: Header=BB6_5 Depth=1
incq %r13
addq $8, %rax
cmpq $1024, %r13 # imm = 0x400
jne .LBB6_5
# %bb.10: # %_Z12multiplyHostPdS_i.exit
callq clock
subq %r12, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI6_2(%rip), %xmm0
movsd .LCPI6_3(%rip), %xmm1 # xmm1 = mem[0],zero
movsd %xmm1, (%rsp) # 8-byte Spill
divsd %xmm0, %xmm1
movsd %xmm1, 8(%rsp) # 8-byte Spill
movl $.L.str, %edi
movb $1, %al
callq printf
movl $.L.str.1, %edi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movq %rbx, %rdi
movq %r15, %rsi
movl $1024, %edx # imm = 0x400
callq _Z14multiplyDevicePdS_i
movsd (%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movsd %xmm1, (%rsp) # 8-byte Spill
movl $.L.str.2, %edi
movb $1, %al
callq printf
movl $.L.str.3, %edi
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
xorl %eax, %eax
movapd .LCPI6_4(%rip), %xmm0 # xmm0 = [NaN,NaN]
movsd .LCPI6_5(%rip), %xmm1 # xmm1 = mem[0],zero
movq %r14, %rcx
movq %r15, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB6_11: # %.preheader.i22
# =>This Loop Header: Depth=1
# Child Loop BB6_12 Depth 2
xorl %edi, %edi
.p2align 4, 0x90
.LBB6_12: # Parent Loop BB6_11 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rcx,%rdi,8), %xmm2 # xmm2 = mem[0],zero
subsd (%rdx,%rdi,8), %xmm2
andpd %xmm0, %xmm2
xorl %r8d, %r8d
ucomisd %xmm1, %xmm2
seta %r8b
addl %r8d, %esi
incq %rdi
cmpq $1024, %rdi # imm = 0x400
jne .LBB6_12
# %bb.13: # %._crit_edge.i26
# in Loop: Header=BB6_11 Depth=1
incq %rax
addq $8192, %rdx # imm = 0x2000
addq $8192, %rcx # imm = 0x2000
cmpq $1024, %rax # imm = 0x400
jne .LBB6_11
# %bb.14: # %_Z5matchPdS_i.exit
testl %esi, %esi
jle .LBB6_16
# %bb.15:
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
jmp .LBB6_17
.LBB6_16:
movl $.Lstr, %edi
callq puts@PLT
.LBB6_17:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14multiplyKernelPdS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14multiplyKernelPdS_i,@object # @_Z14multiplyKernelPdS_i
.section .rodata,"a",@progbits
.globl _Z14multiplyKernelPdS_i
.p2align 3, 0x0
_Z14multiplyKernelPdS_i:
.quad _Z29__device_stub__multiplyKernelPdS_i
.size _Z14multiplyKernelPdS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Time taken on host (ms) = %lf\n"
.size .L.str, 31
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "FLOPS on host = %lf\n"
.size .L.str.1, 21
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Time taken on device (ms) = %lf\n"
.size .L.str.2, 33
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "FLOPS on device = %lf\n"
.size .L.str.3, 23
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Results did not match. %d mismatches\n"
.size .L.str.4, 38
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14multiplyKernelPdS_i"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Results matched."
.size .Lstr, 17
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__multiplyKernelPdS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14multiplyKernelPdS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // From CUDA for engineers
// Listing 6.5: centroid_2d/kernel.cu
// 2d: reduction
#include <cuda_runtime.h>
#include <iostream>
#include <stdio.h>
__global__
void centroidKernel()
{
}
void centroidParallel()
{
}
int main()
{
return 0;
} | code for sm_80
Function : _Z14centroidKernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // From CUDA for engineers
// Listing 6.5: centroid_2d/kernel.cu
// 2d: reduction
#include <cuda_runtime.h>
#include <iostream>
#include <stdio.h>
__global__
void centroidKernel()
{
}
void centroidParallel()
{
}
int main()
{
return 0;
} | .file "tmpxft_000f9cb6_00000000-6_centroid_2d.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z16centroidParallelv
.type _Z16centroidParallelv, @function
_Z16centroidParallelv:
.LFB3669:
.cfi_startproc
endbr64
ret
.cfi_endproc
.LFE3669:
.size _Z16centroidParallelv, .-_Z16centroidParallelv
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
movl $0, %eax
ret
.cfi_endproc
.LFE3670:
.size main, .-main
.globl _Z33__device_stub__Z14centroidKernelvv
.type _Z33__device_stub__Z14centroidKernelvv, @function
_Z33__device_stub__Z14centroidKernelvv:
.LFB3695:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z14centroidKernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z33__device_stub__Z14centroidKernelvv, .-_Z33__device_stub__Z14centroidKernelvv
.globl _Z14centroidKernelv
.type _Z14centroidKernelv, @function
_Z14centroidKernelv:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z14centroidKernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z14centroidKernelv, .-_Z14centroidKernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14centroidKernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14centroidKernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // From CUDA for engineers
// Listing 6.5: centroid_2d/kernel.cu
// 2d: reduction
#include <cuda_runtime.h>
#include <iostream>
#include <stdio.h>
__global__
void centroidKernel()
{
}
void centroidParallel()
{
}
int main()
{
return 0;
} | // From CUDA for engineers
// Listing 6.5: centroid_2d/kernel.cu
// 2d: reduction
#include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
__global__
void centroidKernel()
{
}
void centroidParallel()
{
}
int main()
{
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // From CUDA for engineers
// Listing 6.5: centroid_2d/kernel.cu
// 2d: reduction
#include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
__global__
void centroidKernel()
{
}
void centroidParallel()
{
}
int main()
{
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14centroidKernelv
.globl _Z14centroidKernelv
.p2align 8
.type _Z14centroidKernelv,@function
_Z14centroidKernelv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14centroidKernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14centroidKernelv, .Lfunc_end0-_Z14centroidKernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14centroidKernelv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z14centroidKernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // From CUDA for engineers
// Listing 6.5: centroid_2d/kernel.cu
// 2d: reduction
#include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
__global__
void centroidKernel()
{
}
void centroidParallel()
{
}
int main()
{
return 0;
} | .text
.file "centroid_2d.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z29__device_stub__centroidKernelv # -- Begin function _Z29__device_stub__centroidKernelv
.p2align 4, 0x90
.type _Z29__device_stub__centroidKernelv,@function
_Z29__device_stub__centroidKernelv: # @_Z29__device_stub__centroidKernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z14centroidKernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z29__device_stub__centroidKernelv, .Lfunc_end0-_Z29__device_stub__centroidKernelv
.cfi_endproc
# -- End function
.globl _Z16centroidParallelv # -- Begin function _Z16centroidParallelv
.p2align 4, 0x90
.type _Z16centroidParallelv,@function
_Z16centroidParallelv: # @_Z16centroidParallelv
.cfi_startproc
# %bb.0:
retq
.Lfunc_end1:
.size _Z16centroidParallelv, .Lfunc_end1-_Z16centroidParallelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
xorl %eax, %eax
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14centroidKernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14centroidKernelv,@object # @_Z14centroidKernelv
.section .rodata,"a",@progbits
.globl _Z14centroidKernelv
.p2align 3, 0x0
_Z14centroidKernelv:
.quad _Z29__device_stub__centroidKernelv
.size _Z14centroidKernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14centroidKernelv"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__centroidKernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14centroidKernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14centroidKernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14centroidKernelv
.globl _Z14centroidKernelv
.p2align 8
.type _Z14centroidKernelv,@function
_Z14centroidKernelv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14centroidKernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14centroidKernelv, .Lfunc_end0-_Z14centroidKernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14centroidKernelv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z14centroidKernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f9cb6_00000000-6_centroid_2d.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z16centroidParallelv
.type _Z16centroidParallelv, @function
_Z16centroidParallelv:
.LFB3669:
.cfi_startproc
endbr64
ret
.cfi_endproc
.LFE3669:
.size _Z16centroidParallelv, .-_Z16centroidParallelv
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
movl $0, %eax
ret
.cfi_endproc
.LFE3670:
.size main, .-main
.globl _Z33__device_stub__Z14centroidKernelvv
.type _Z33__device_stub__Z14centroidKernelvv, @function
_Z33__device_stub__Z14centroidKernelvv:
.LFB3695:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z14centroidKernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z33__device_stub__Z14centroidKernelvv, .-_Z33__device_stub__Z14centroidKernelvv
.globl _Z14centroidKernelv
.type _Z14centroidKernelv, @function
_Z14centroidKernelv:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z14centroidKernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z14centroidKernelv, .-_Z14centroidKernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14centroidKernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14centroidKernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "centroid_2d.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z29__device_stub__centroidKernelv # -- Begin function _Z29__device_stub__centroidKernelv
.p2align 4, 0x90
.type _Z29__device_stub__centroidKernelv,@function
_Z29__device_stub__centroidKernelv: # @_Z29__device_stub__centroidKernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z14centroidKernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z29__device_stub__centroidKernelv, .Lfunc_end0-_Z29__device_stub__centroidKernelv
.cfi_endproc
# -- End function
.globl _Z16centroidParallelv # -- Begin function _Z16centroidParallelv
.p2align 4, 0x90
.type _Z16centroidParallelv,@function
_Z16centroidParallelv: # @_Z16centroidParallelv
.cfi_startproc
# %bb.0:
retq
.Lfunc_end1:
.size _Z16centroidParallelv, .Lfunc_end1-_Z16centroidParallelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
xorl %eax, %eax
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14centroidKernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14centroidKernelv,@object # @_Z14centroidKernelv
.section .rodata,"a",@progbits
.globl _Z14centroidKernelv
.p2align 3, 0x0
_Z14centroidKernelv:
.quad _Z29__device_stub__centroidKernelv
.size _Z14centroidKernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14centroidKernelv"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__centroidKernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14centroidKernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "stdio.h"
#include "stdlib.h"
#define MAX_NC 32
#define ERROR_HANDLING(call) { \
cudaError error = call; \
if(error != cudaSuccess) { \
fprintf(stderr, "ERROR: in file '%s' in line %i: %s.\n", \
__FILE__, __LINE__, cudaGetErrorString(error)); \
exit(1); \
} \
} while (0)
typedef struct double24 {double x; double y; double z;} double24;
__device__
double24 rgb_sub(uchar4 *a, double24 *b) {
double24 res = {a->x - b->x, a->y - b->y, a->z - b->z};
return res;
}
__device__
double rgb_mul(double24 *a, double24 *b) {
return a->x * b->x + a->y * b->y + a->z * b->z;
}
__constant__ double24 cavg_const[MAX_NC];
__constant__ int nc_const;
void copy_from_ram2dev_const(double24* cavg, int *nc) {
ERROR_HANDLING(cudaMemcpyToSymbol(nc_const, nc, sizeof(int)));
ERROR_HANDLING(cudaMemcpyToSymbol(cavg_const, cavg, (*nc)*sizeof(double24)));
}
__global__
void min_dist_method_kernel(uchar4* image, size_t width, size_t height) {
size_t idx = threadIdx.x + blockIdx.x * blockDim.x;
size_t idy = threadIdx.y + blockIdx.y * blockDim.y;
size_t offsetx = blockDim.x * gridDim.x;
size_t offsety = blockDim.y * gridDim.y;
for (size_t x = idx; x < width; x+=offsetx) {
for (size_t y = idy; y < height; y+=offsety) {
uchar4* pixel = &image[x*height + y];
int cur_max_class_idx = 0;
double24 sub_res = rgb_sub(pixel, &cavg_const[cur_max_class_idx]);
double cur_max_value = -rgb_mul(&sub_res, &sub_res);
for (int i = 1; i < nc_const; i++) {
double24 sub_res = rgb_sub(pixel, &cavg_const[i]);
double res = - rgb_mul(&sub_res, &sub_res);
if (res > cur_max_value) {
cur_max_value = res;
cur_max_class_idx = i;
}
}
pixel->w = cur_max_class_idx;
}
}
}
int main() {
int width, height;
char inputFilename[256];
char outputFilename[256];
scanf("%s", inputFilename);
scanf("%s", outputFilename);
FILE* file = fopen(inputFilename, "rb");
fread(&width, sizeof(int), 1, file);
fread(&height, sizeof(int), 1, file);
uchar4* image = (uchar4*)malloc(sizeof(uchar4)*height*width);
fread(image, sizeof(uchar4), width*height, file);
fclose(file);
int nc;
scanf("%d", &nc);
double24 cavg[MAX_NC];
int np_i;
for (int i = 0; i < nc; i++) {
scanf("%d", &np_i);
double24 tmp_sum = {0., 0., 0.};
int x, y;
for (int j = 0; j < np_i; j++) {
scanf("%d %d", &x, &y);
tmp_sum.x += image[y*width+x].x;
tmp_sum.y += image[y*width+x].y;
tmp_sum.z += image[y*width+x].z;
}
cavg[i].x = tmp_sum.x/np_i;
cavg[i].y = tmp_sum.y/np_i;
cavg[i].z = tmp_sum.z/np_i;
}
copy_from_ram2dev_const(cavg, &nc);
uchar4* dimage;
ERROR_HANDLING(cudaMalloc((void**)&dimage, sizeof(uchar4)*width*height));
ERROR_HANDLING(cudaMemcpy(dimage, image, sizeof(uchar4)*width*height, cudaMemcpyHostToDevice));
min_dist_method_kernel<<<dim3(16, 16), dim3(16, 16)>>>(dimage, width, height);
ERROR_HANDLING(cudaGetLastError());
ERROR_HANDLING(cudaMemcpy(image, dimage, sizeof(uchar4)*width*height, cudaMemcpyDeviceToHost));
ERROR_HANDLING(cudaFree(dimage));
file = fopen(outputFilename, "wb");
fwrite(&width, sizeof(int), 1, file);
fwrite(&height, sizeof(int), 1, file);
fwrite(image, sizeof(uchar4), width * height, file);
fclose(file);
free(image);
return 0;
} | code for sm_80
Function : _Z22min_dist_method_kernelP6uchar4mm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e620000002600 */
/*0040*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fc600078e0203 */
/*0050*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002200 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fc80003f06070 */
/*0070*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x16c], PT, P0 ; /* 0x00005b00ff007a0c */
/* 0x000fda0003f06100 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x3][0x300] ; /* 0x00c0c000ff057624 */
/* 0x002fe200078e00ff */
/*00a0*/ ULDC UR6, c[0x0][0xc] ; /* 0x0000030000067ab9 */
/* 0x000fe20000000800 */
/*00b0*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fe200078e0203 */
/*00c0*/ ULDC UR7, c[0x0][0x10] ; /* 0x0000040000077ab9 */
/* 0x000fe20000000800 */
/*00d0*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe200078e00ff */
/*00e0*/ ISETP.GT.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe20003f04270 */
/*00f0*/ ULDC.64 UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000a00 */
/*0100*/ UIMAD UR4, UR4, UR6, URZ ; /* 0x00000006040472a4 */
/* 0x000fe4000f8e023f */
/*0110*/ UIMAD UR5, UR5, UR7, URZ ; /* 0x00000007050572a4 */
/* 0x000fc6000f8e023f */
/*0120*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fca0000000a00 */
/*0130*/ @P0 BRA 0x2f0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0140*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f06070 */
/*0150*/ BSSY B0, 0x290 ; /* 0x0000013000007945 */
/* 0x000fe60003800000 */
/*0160*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x174], PT, P0 ; /* 0x00005d00ff007a0c */
/* 0x000fda0003f06100 */
/*0170*/ @P0 BRA 0x280 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*0180*/ IMAD R5, R3, c[0x0][0x170], RZ ; /* 0x00005c0003057a24 */
/* 0x000fe400078e02ff */
/*0190*/ IMAD.MOV.U32 R8, RZ, RZ, R0 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0000 */
/*01a0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe400078e00ff */
/*01b0*/ IMAD R11, R2, c[0x0][0x174], R5 ; /* 0x00005d00020b7a24 */
/* 0x000fe400078e0205 */
/*01c0*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0008 */
/*01d0*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0009 */
/*01e0*/ IMAD.WIDE.U32 R4, R2, c[0x0][0x170], R4 ; /* 0x00005c0002047a25 */
/* 0x000fc800078e0004 */
/*01f0*/ IMAD.IADD R5, R5, 0x1, R11 ; /* 0x0000000105057824 */
/* 0x000fe200078e020b */
/*0200*/ LEA R6, P0, R4, c[0x0][0x160], 0x2 ; /* 0x0000580004067a11 */
/* 0x000fc800078010ff */
/*0210*/ LEA.HI.X R7, R4, c[0x0][0x164], R5, 0x2, P0 ; /* 0x0000590004077a11 */
/* 0x000fe400000f1405 */
/*0220*/ IADD3 R8, P0, R8, UR5, RZ ; /* 0x0000000508087c10 */
/* 0x000fc6000ff1e0ff */
/*0230*/ STG.E.U8 [R6.64+0x3], RZ ; /* 0x000003ff06007986 */
/* 0x0001e4000c101106 */
/*0240*/ IMAD.X R9, RZ, RZ, R9, P0 ; /* 0x000000ffff097224 */
/* 0x000fe200000e0609 */
/*0250*/ ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x170], PT ; /* 0x00005c0008007a0c */
/* 0x000fc80003f06070 */
/*0260*/ ISETP.GE.U32.AND.EX P0, PT, R9, c[0x0][0x174], PT, P0 ; /* 0x00005d0009007a0c */
/* 0x000fda0003f06100 */
/*0270*/ @!P0 BRA 0x1c0 ; /* 0xffffff4000008947 */
/* 0x001fea000383ffff */
/*0280*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0290*/ IADD3 R2, P0, R2, UR4, RZ ; /* 0x0000000402027c10 */
/* 0x000fca000ff1e0ff */
/*02a0*/ IMAD.X R3, RZ, RZ, R3, P0 ; /* 0x000000ffff037224 */
/* 0x000fe200000e0603 */
/*02b0*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fc80003f06070 */
/*02c0*/ ISETP.GE.U32.AND.EX P0, PT, R3, c[0x0][0x16c], PT, P0 ; /* 0x00005b0003007a0c */
/* 0x000fda0003f06100 */
/*02d0*/ @!P0 BRA 0x140 ; /* 0xfffffe6000008947 */
/* 0x000fea000383ffff */
/*02e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02f0*/ IADD3 R4, R5.reuse, -0x1, RZ ; /* 0xffffffff05047810 */
/* 0x040fe40007ffe0ff */
/*0300*/ IADD3 R5, R5, -0x2, RZ ; /* 0xfffffffe05057810 */
/* 0x000fe40007ffe0ff */
/*0310*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fc800078ec0ff */
/*0320*/ IADD3 R6, -R4, c[0x3][0x300], RZ ; /* 0x00c0c00004067a10 */
/* 0x000fe40007ffe1ff */
/*0330*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f06070 */
/*0340*/ BSSY B0, 0xca0 ; /* 0x0000095000007945 */
/* 0x000fe60003800000 */
/*0350*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x174], PT, P0 ; /* 0x00005d00ff007a0c */
/* 0x000fda0003f06100 */
/*0360*/ @P0 BRA 0xc90 ; /* 0x0000092000000947 */
/* 0x001fea0003800000 */
/*0370*/ IMAD.MOV.U32 R8, RZ, RZ, R0 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0000 */
/*0380*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe400078e00ff */
/*0390*/ IMAD R7, R3, c[0x0][0x170], RZ ; /* 0x00005c0003077a24 */
/* 0x000fe400078e02ff */
/*03a0*/ IMAD.WIDE.U32 R10, R2, c[0x0][0x170], R8 ; /* 0x00005c00020a7a25 */
/* 0x000fc800078e0008 */
/*03b0*/ IMAD R7, R2, c[0x0][0x174], R7 ; /* 0x00005d0002077a24 */
/* 0x000fe200078e0207 */
/*03c0*/ LEA R22, P0, R10, c[0x0][0x160], 0x2 ; /* 0x000058000a167a11 */
/* 0x000fc600078010ff */
/*03d0*/ IMAD.IADD R7, R11, 0x1, R7 ; /* 0x000000010b077824 */
/* 0x000fca00078e0207 */
/*03e0*/ LEA.HI.X R23, R10, c[0x0][0x164], R7, 0x2, P0 ; /* 0x000059000a177a11 */
/* 0x000fca00000f1407 */
/*03f0*/ LDG.E R22, [R22.64] ; /* 0x0000000616167981 */
/* 0x000ea2000c1e1900 */
/*0400*/ ISETP.GE.U32.AND P1, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fe20003f26070 */
/*0410*/ IMAD.MOV.U32 R26, RZ, RZ, RZ ; /* 0x000000ffff1a7224 */
/* 0x000fe200078e00ff */
/*0420*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*0430*/ IMAD.MOV.U32 R25, RZ, RZ, 0x1 ; /* 0x00000001ff197424 */
/* 0x000fe200078e00ff */
/*0440*/ I2F.F64.U8 R10, R22.B1 ; /* 0x10000016000a7312 */
/* 0x005e300000001800 */
/*0450*/ I2F.F64.U8 R12, R22 ; /* 0x00000016000c7312 */
/* 0x000e700000001800 */
/*0460*/ I2F.F64.U8 R14, R22.B2 ; /* 0x20000016000e7312 */
/* 0x000ea20000001800 */
/*0470*/ DADD R18, R10, -c[0x3][0x8] ; /* 0x80c002000a127629 */
/* 0x001e0c0000000000 */
/*0480*/ DMUL R20, R18, R18 ; /* 0x0000001212147228 */
/* 0x001fc80000000000 */
/*0490*/ DADD R16, R12, -c[0x3][0x0] ; /* 0x80c000000c107629 */
/* 0x002e080000000000 */
/*04a0*/ DADD R18, R14, -c[0x3][0x10] ; /* 0x80c004000e127629 */
/* 0x004fc80000000000 */
/*04b0*/ DFMA R20, R16, R16, R20 ; /* 0x000000101014722b */
/* 0x001e0c0000000014 */
/*04c0*/ DFMA R18, R18, R18, R20 ; /* 0x000000121212722b */
/* 0x001e0c0000000014 */
/*04d0*/ DADD R18, -RZ, -R18 ; /* 0x00000000ff127229 */
/* 0x001e220000000912 */
/*04e0*/ @!P1 BRA 0x900 ; /* 0x0000041000009947 */
/* 0x000fea0003800000 */
/*04f0*/ IMAD.MOV.U32 R26, RZ, RZ, RZ ; /* 0x000000ffff1a7224 */
/* 0x000fe400078e00ff */
/*0500*/ IMAD.MOV.U32 R25, RZ, RZ, 0x1 ; /* 0x00000001ff197424 */
/* 0x000fe400078e00ff */
/*0510*/ IMAD.MOV.U32 R24, RZ, RZ, RZ ; /* 0x000000ffff187224 */
/* 0x000fe400078e00ff */
/*0520*/ IMAD.MOV.U32 R7, RZ, RZ, R6 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0006 */
/*0530*/ LDC.64 R16, c[0x3][R24+0x20] ; /* 0x00c0080018107b82 */
/* 0x000e620000000a00 */
/*0540*/ IADD3 R7, R7, -0x4, RZ ; /* 0xfffffffc07077810 */
/* 0x000fce0007ffe0ff */
/*0550*/ LDC.64 R22, c[0x3][R24+0x18] ; /* 0x00c0060018167b82 */
/* 0x000eb00000000a00 */
/*0560*/ LDC.64 R20, c[0x3][R24+0x28] ; /* 0x00c00a0018147b82 */
/* 0x000ee20000000a00 */
/*0570*/ DADD R16, R10, -R16 ; /* 0x000000000a107229 */
/* 0x002e4c0000000810 */
/*0580*/ DMUL R16, R16, R16 ; /* 0x0000001010107228 */
/* 0x002fc80000000000 */
/*0590*/ DADD R22, R12, -R22 ; /* 0x000000000c167229 */
/* 0x004e4c0000000816 */
/*05a0*/ DFMA R16, R22, R22, R16 ; /* 0x000000161610722b */
/* 0x0023c80000000010 */
/*05b0*/ DADD R20, R14, -R20 ; /* 0x000000000e147229 */
/* 0x008ea20000000814 */
/*05c0*/ LDC.64 R22, c[0x3][R24+0x30] ; /* 0x00c00c0018167b82 */
/* 0x002e6a0000000a00 */
/*05d0*/ DFMA R16, R20, R20, R16 ; /* 0x000000141410722b */
/* 0x004e8c0000000010 */
/*05e0*/ DADD R20, -RZ, -R16 ; /* 0x00000000ff147229 */
/* 0x004fc80000000910 */
/*05f0*/ DSETP.GEU.AND P2, PT, R18, -R16, PT ; /* 0x800000101200722a */
/* 0x0010a40003f4e000 */
/*0600*/ LDC.64 R16, c[0x3][R24+0x38] ; /* 0x00c00e0018107b82 */
/* 0x001e280000000a00 */
/*0610*/ FSEL R20, R20, R18, !P2 ; /* 0x0000001214147208 */
/* 0x004fe40005000000 */
/*0620*/ FSEL R21, R21, R19, !P2 ; /* 0x0000001315157208 */
/* 0x000fe20005000000 */
/*0630*/ DADD R22, R12, -R22 ; /* 0x000000000c167229 */
/* 0x002fe20000000816 */
/*0640*/ LDC.64 R18, c[0x3][R24+0x40] ; /* 0x00c0100018127b82 */
/* 0x000e620000000a00 */
/*0650*/ SEL R26, R25, R26, !P2 ; /* 0x0000001a191a7207 */
/* 0x000fc40005000000 */
/*0660*/ ISETP.NE.AND P2, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fe20003f45270 */
/*0670*/ DADD R16, R10, -R16 ; /* 0x000000000a107229 */
/* 0x001e0c0000000810 */
/*0680*/ DMUL R16, R16, R16 ; /* 0x0000001010107228 */
/* 0x001e080000000000 */
/*0690*/ DADD R18, R14, -R18 ; /* 0x000000000e127229 */
/* 0x002fc80000000812 */
/*06a0*/ DFMA R16, R22, R22, R16 ; /* 0x000000161610722b */
/* 0x0010640000000010 */
/*06b0*/ LDC.64 R22, c[0x3][R24+0x48] ; /* 0x00c0120018167b82 */
/* 0x001e280000000a00 */
/*06c0*/ DFMA R18, R18, R18, R16 ; /* 0x000000121212722b */
/* 0x0022880000000010 */
/*06d0*/ LDC.64 R16, c[0x3][R24+0x50] ; /* 0x00c0140018107b82 */
/* 0x002e640000000a00 */
/*06e0*/ DSETP.GEU.AND P3, PT, R20, -R18, PT ; /* 0x800000121400722a */
/* 0x004fc80003f6e000 */
/*06f0*/ DADD R18, -RZ, -R18 ; /* 0x00000000ff127229 */
/* 0x000e880000000912 */
/*0700*/ DADD R22, R12, -R22 ; /* 0x000000000c167229 */
/* 0x001fcc0000000816 */
/*0710*/ FSEL R18, R18, R20, !P3 ; /* 0x0000001412127208 */
/* 0x004fe40005800000 */
/*0720*/ FSEL R19, R19, R21, !P3 ; /* 0x0000001513137208 */
/* 0x000fe40005800000 */
/*0730*/ LDC.64 R20, c[0x3][R24+0x68] ; /* 0x00c01a0018147b82 */
/* 0x000e220000000a00 */
/*0740*/ @!P3 IADD3 R26, R25, 0x1, RZ ; /* 0x00000001191ab810 */
/* 0x000fe20007ffe0ff */
/*0750*/ DADD R16, R10, -R16 ; /* 0x000000000a107229 */
/* 0x002e4c0000000810 */
/*0760*/ DMUL R16, R16, R16 ; /* 0x0000001010107228 */
/* 0x002e4c0000000000 */
/*0770*/ DFMA R16, R22, R22, R16 ; /* 0x000000161610722b */
/* 0x0023e40000000010 */
/*0780*/ LDC.64 R22, c[0x3][R24+0x58] ; /* 0x00c0160018167b82 */
/* 0x002e640000000a00 */
/*0790*/ DADD R20, R10, -R20 ; /* 0x000000000a147229 */
/* 0x001e0c0000000814 */
/*07a0*/ DMUL R20, R20, R20 ; /* 0x0000001414147228 */
/* 0x001fc80000000000 */
/*07b0*/ DADD R22, R14, -R22 ; /* 0x000000000e167229 */
/* 0x002e0c0000000816 */
/*07c0*/ DFMA R16, R22, R22, R16 ; /* 0x000000161610722b */
/* 0x0010480000000010 */
/*07d0*/ LDC.64 R22, c[0x3][R24+0x60] ; /* 0x00c0180018167b82 */
/* 0x001e240000000a00 */
/*07e0*/ DSETP.GEU.AND P4, PT, R18, -R16, PT ; /* 0x800000101200722a */
/* 0x002fc80003f8e000 */
/*07f0*/ DADD R16, -RZ, -R16 ; /* 0x00000000ff107229 */
/* 0x000e540000000910 */
/*0800*/ FSEL R16, R16, R18, !P4 ; /* 0x0000001210107208 */
/* 0x002fe40006000000 */
/*0810*/ FSEL R17, R17, R19, !P4 ; /* 0x0000001311117208 */
/* 0x000fe40006000000 */
/*0820*/ @!P4 IADD3 R26, R25, 0x2, RZ ; /* 0x00000002191ac810 */
/* 0x000fe20007ffe0ff */
/*0830*/ DADD R22, R12, -R22 ; /* 0x000000000c167229 */
/* 0x001e0c0000000816 */
/*0840*/ DFMA R20, R22, R22, R20 ; /* 0x000000161614722b */
/* 0x0011c80000000014 */
/*0850*/ LDC.64 R22, c[0x3][R24+0x70] ; /* 0x00c01c0018167b82 */
/* 0x0010640000000a00 */
/*0860*/ IADD3 R24, R24, 0x60, RZ ; /* 0x0000006018187810 */
/* 0x001fe20007ffe0ff */
/*0870*/ DADD R22, R14, -R22 ; /* 0x000000000e167229 */
/* 0x002e0c0000000816 */
/*0880*/ DFMA R20, R22, R22, R20 ; /* 0x000000161614722b */
/* 0x001e0c0000000014 */
/*0890*/ DSETP.GEU.AND P1, PT, R16, -R20, PT ; /* 0x800000141000722a */
/* 0x001e080003f2e000 */
/*08a0*/ DADD R20, -RZ, -R20 ; /* 0x00000000ff147229 */
/* 0x000e540000000914 */
/*08b0*/ @!P1 IADD3 R26, R25, 0x3, RZ ; /* 0x00000003191a9810 */
/* 0x001fe40007ffe0ff */
/*08c0*/ FSEL R18, R20, R16, !P1 ; /* 0x0000001014127208 */
/* 0x002fe40004800000 */
/*08d0*/ FSEL R19, R21, R17, !P1 ; /* 0x0000001115137208 */
/* 0x000fe40004800000 */
/*08e0*/ IADD3 R25, R25, 0x4, RZ ; /* 0x0000000419197810 */
/* 0x000fe20007ffe0ff */
/*08f0*/ @P2 BRA 0x530 ; /* 0xfffffc3000002947 */
/* 0x000fea000383ffff */
/*0900*/ @!P0 BRA 0xbd0 ; /* 0x000002c000008947 */
/* 0x000fea0003800000 */
/*0910*/ IMAD R7, R25, 0x18, RZ ; /* 0x0000001819077824 */
/* 0x000fe200078e02ff */
/*0920*/ ISETP.NE.AND P1, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fc60003f25270 */
/*0930*/ LDC.64 R16, c[0x3][R7+0x8] ; /* 0x00c0020007107b82 */
/* 0x000e700000000a00 */
/*0940*/ LDC.64 R22, c[0x3][R7] ; /* 0x00c0000007167b82 */
/* 0x000eb00000000a00 */
/*0950*/ LDC.64 R20, c[0x3][R7+0x10] ; /* 0x00c0040007147b82 */
/* 0x000ee20000000a00 */
/*0960*/ DADD R16, R10, -R16 ; /* 0x000000000a107229 */
/* 0x002e4c0000000810 */
/*0970*/ DMUL R16, R16, R16 ; /* 0x0000001010107228 */
/* 0x002fc80000000000 */
/*0980*/ DADD R22, R12, -R22 ; /* 0x000000000c167229 */
/* 0x004e4c0000000816 */
/*0990*/ DFMA R16, R22, R22, R16 ; /* 0x000000161610722b */
/* 0x002fc80000000010 */
/*09a0*/ DADD R20, R14, -R20 ; /* 0x000000000e147229 */
/* 0x008e4c0000000814 */
/*09b0*/ DFMA R20, R20, R20, R16 ; /* 0x000000141414722b */
/* 0x002e4c0000000010 */
/*09c0*/ DADD R16, -RZ, -R20 ; /* 0x00000000ff107229 */
/* 0x002fc80000000914 */
/*09d0*/ DSETP.GEU.AND P0, PT, R18, -R20, PT ; /* 0x800000141200722a */
/* 0x001e0c0003f0e000 */
/*09e0*/ FSEL R16, R16, R18, !P0 ; /* 0x0000001210107208 */
/* 0x001fe40004000000 */
/*09f0*/ FSEL R17, R17, R19, !P0 ; /* 0x0000001311117208 */
/* 0x000fe40004000000 */
/*0a00*/ SEL R26, R25, R26, !P0 ; /* 0x0000001a191a7207 */
/* 0x000fe20004000000 */
/*0a10*/ @!P1 BRA 0xbd0 ; /* 0x000001b000009947 */
/* 0x000fea0003800000 */
/*0a20*/ LDC.64 R18, c[0x3][R7+0x20] ; /* 0x00c0080007127b82 */
/* 0x000e220000000a00 */
/*0a30*/ ISETP.NE.AND P1, PT, R4, 0x2, PT ; /* 0x000000020400780c */
/* 0x000fce0003f25270 */
/*0a40*/ LDC.64 R22, c[0x3][R7+0x18] ; /* 0x00c0060007167b82 */
/* 0x000e700000000a00 */
/*0a50*/ LDC.64 R20, c[0x3][R7+0x28] ; /* 0x00c00a0007147b82 */
/* 0x000ea20000000a00 */
/*0a60*/ DADD R18, R10, -R18 ; /* 0x000000000a127229 */
/* 0x001e0c0000000812 */
/*0a70*/ DMUL R18, R18, R18 ; /* 0x0000001212127228 */
/* 0x001fc80000000000 */
/*0a80*/ DADD R22, R12, -R22 ; /* 0x000000000c167229 */
/* 0x002e0c0000000816 */
/*0a90*/ DFMA R18, R22, R22, R18 ; /* 0x000000161612722b */
/* 0x001fc80000000012 */
/*0aa0*/ DADD R20, R14, -R20 ; /* 0x000000000e147229 */
/* 0x004e0c0000000814 */
/*0ab0*/ DFMA R18, R20, R20, R18 ; /* 0x000000141412722b */
/* 0x001e0c0000000012 */
/*0ac0*/ DSETP.GEU.AND P0, PT, R16, -R18, PT ; /* 0x800000121000722a */
/* 0x001fc80003f0e000 */
/*0ad0*/ DADD R18, -RZ, -R18 ; /* 0x00000000ff127229 */
/* 0x000e140000000912 */
/*0ae0*/ FSEL R16, R18, R16, !P0 ; /* 0x0000001012107208 */
/* 0x001fe40004000000 */
/*0af0*/ FSEL R17, R19, R17, !P0 ; /* 0x0000001113117208 */
/* 0x000fe40004000000 */
/*0b00*/ @!P0 IADD3 R26, R25, 0x1, RZ ; /* 0x00000001191a8810 */
/* 0x000fe20007ffe0ff */
/*0b10*/ @!P1 BRA 0xbd0 ; /* 0x000000b000009947 */
/* 0x000fea0003800000 */
/*0b20*/ LDC.64 R18, c[0x3][R7+0x38] ; /* 0x00c00e0007127b82 */
/* 0x000e300000000a00 */
/*0b30*/ LDC.64 R20, c[0x3][R7+0x30] ; /* 0x00c00c0007147b82 */
/* 0x000e700000000a00 */
/*0b40*/ LDC.64 R22, c[0x3][R7+0x40] ; /* 0x00c0100007167b82 */
/* 0x000ea20000000a00 */
/*0b50*/ DADD R18, R10, -R18 ; /* 0x000000000a127229 */
/* 0x001e0c0000000812 */
/*0b60*/ DMUL R18, R18, R18 ; /* 0x0000001212127228 */
/* 0x001fc80000000000 */
/*0b70*/ DADD R20, R12, -R20 ; /* 0x000000000c147229 */
/* 0x002e080000000814 */
/*0b80*/ DADD R22, R14, -R22 ; /* 0x000000000e167229 */
/* 0x004fc80000000816 */
/*0b90*/ DFMA R18, R20, R20, R18 ; /* 0x000000141412722b */
/* 0x001e0c0000000012 */
/*0ba0*/ DFMA R18, R22, R22, R18 ; /* 0x000000161612722b */
/* 0x001e0c0000000012 */
/*0bb0*/ DSETP.GEU.AND P0, PT, R16, -R18, PT ; /* 0x800000121000722a */
/* 0x001e1c0003f0e000 */
/*0bc0*/ @!P0 IADD3 R26, R25, 0x2, RZ ; /* 0x00000002191a8810 */
/* 0x001fe40007ffe0ff */
/*0bd0*/ IMAD R7, R3, c[0x0][0x170], RZ ; /* 0x00005c0003077a24 */
/* 0x000fe400078e02ff */
/*0be0*/ IMAD.WIDE.U32 R10, R2, c[0x0][0x170], R8 ; /* 0x00005c00020a7a25 */
/* 0x000fc800078e0008 */
/*0bf0*/ IMAD R7, R2, c[0x0][0x174], R7 ; /* 0x00005d0002077a24 */
/* 0x000fe200078e0207 */
/*0c00*/ LEA R12, P0, R10, c[0x0][0x160], 0x2 ; /* 0x000058000a0c7a11 */
/* 0x000fc600078010ff */
/*0c10*/ IMAD.IADD R7, R11, 0x1, R7 ; /* 0x000000010b077824 */
/* 0x000fca00078e0207 */
/*0c20*/ LEA.HI.X R13, R10, c[0x0][0x164], R7, 0x2, P0 ; /* 0x000059000a0d7a11 */
/* 0x000fe400000f1407 */
/*0c30*/ IADD3 R8, P0, R8, UR5, RZ ; /* 0x0000000508087c10 */
/* 0x000fc6000ff1e0ff */
/*0c40*/ STG.E.U8 [R12.64+0x3], R26 ; /* 0x0000031a0c007986 */
/* 0x0003e4000c101106 */
/*0c50*/ IMAD.X R9, RZ, RZ, R9, P0 ; /* 0x000000ffff097224 */
/* 0x000fe200000e0609 */
/*0c60*/ ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x170], PT ; /* 0x00005c0008007a0c */
/* 0x000fc80003f06070 */
/*0c70*/ ISETP.GE.U32.AND.EX P0, PT, R9, c[0x0][0x174], PT, P0 ; /* 0x00005d0009007a0c */
/* 0x000fda0003f06100 */
/*0c80*/ @!P0 BRA 0x390 ; /* 0xfffff70000008947 */
/* 0x002fea000383ffff */
/*0c90*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0ca0*/ IADD3 R2, P0, R2, UR4, RZ ; /* 0x0000000402027c10 */
/* 0x000fca000ff1e0ff */
/*0cb0*/ IMAD.X R3, RZ, RZ, R3, P0 ; /* 0x000000ffff037224 */
/* 0x000fe200000e0603 */
/*0cc0*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fc80003f06070 */
/*0cd0*/ ISETP.GE.U32.AND.EX P0, PT, R3, c[0x0][0x16c], PT, P0 ; /* 0x00005b0003007a0c */
/* 0x000fda0003f06100 */
/*0ce0*/ @!P0 BRA 0x330 ; /* 0xfffff64000008947 */
/* 0x000fea000383ffff */
/*0cf0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d00*/ BRA 0xd00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "stdio.h"
#include "stdlib.h"
#define MAX_NC 32
#define ERROR_HANDLING(call) { \
cudaError error = call; \
if(error != cudaSuccess) { \
fprintf(stderr, "ERROR: in file '%s' in line %i: %s.\n", \
__FILE__, __LINE__, cudaGetErrorString(error)); \
exit(1); \
} \
} while (0)
typedef struct double24 {double x; double y; double z;} double24;
__device__
double24 rgb_sub(uchar4 *a, double24 *b) {
double24 res = {a->x - b->x, a->y - b->y, a->z - b->z};
return res;
}
__device__
double rgb_mul(double24 *a, double24 *b) {
return a->x * b->x + a->y * b->y + a->z * b->z;
}
__constant__ double24 cavg_const[MAX_NC];
__constant__ int nc_const;
void copy_from_ram2dev_const(double24* cavg, int *nc) {
ERROR_HANDLING(cudaMemcpyToSymbol(nc_const, nc, sizeof(int)));
ERROR_HANDLING(cudaMemcpyToSymbol(cavg_const, cavg, (*nc)*sizeof(double24)));
}
__global__
void min_dist_method_kernel(uchar4* image, size_t width, size_t height) {
size_t idx = threadIdx.x + blockIdx.x * blockDim.x;
size_t idy = threadIdx.y + blockIdx.y * blockDim.y;
size_t offsetx = blockDim.x * gridDim.x;
size_t offsety = blockDim.y * gridDim.y;
for (size_t x = idx; x < width; x+=offsetx) {
for (size_t y = idy; y < height; y+=offsety) {
uchar4* pixel = &image[x*height + y];
int cur_max_class_idx = 0;
double24 sub_res = rgb_sub(pixel, &cavg_const[cur_max_class_idx]);
double cur_max_value = -rgb_mul(&sub_res, &sub_res);
for (int i = 1; i < nc_const; i++) {
double24 sub_res = rgb_sub(pixel, &cavg_const[i]);
double res = - rgb_mul(&sub_res, &sub_res);
if (res > cur_max_value) {
cur_max_value = res;
cur_max_class_idx = i;
}
}
pixel->w = cur_max_class_idx;
}
}
}
int main() {
int width, height;
char inputFilename[256];
char outputFilename[256];
scanf("%s", inputFilename);
scanf("%s", outputFilename);
FILE* file = fopen(inputFilename, "rb");
fread(&width, sizeof(int), 1, file);
fread(&height, sizeof(int), 1, file);
uchar4* image = (uchar4*)malloc(sizeof(uchar4)*height*width);
fread(image, sizeof(uchar4), width*height, file);
fclose(file);
int nc;
scanf("%d", &nc);
double24 cavg[MAX_NC];
int np_i;
for (int i = 0; i < nc; i++) {
scanf("%d", &np_i);
double24 tmp_sum = {0., 0., 0.};
int x, y;
for (int j = 0; j < np_i; j++) {
scanf("%d %d", &x, &y);
tmp_sum.x += image[y*width+x].x;
tmp_sum.y += image[y*width+x].y;
tmp_sum.z += image[y*width+x].z;
}
cavg[i].x = tmp_sum.x/np_i;
cavg[i].y = tmp_sum.y/np_i;
cavg[i].z = tmp_sum.z/np_i;
}
copy_from_ram2dev_const(cavg, &nc);
uchar4* dimage;
ERROR_HANDLING(cudaMalloc((void**)&dimage, sizeof(uchar4)*width*height));
ERROR_HANDLING(cudaMemcpy(dimage, image, sizeof(uchar4)*width*height, cudaMemcpyHostToDevice));
min_dist_method_kernel<<<dim3(16, 16), dim3(16, 16)>>>(dimage, width, height);
ERROR_HANDLING(cudaGetLastError());
ERROR_HANDLING(cudaMemcpy(image, dimage, sizeof(uchar4)*width*height, cudaMemcpyDeviceToHost));
ERROR_HANDLING(cudaFree(dimage));
file = fopen(outputFilename, "wb");
fwrite(&width, sizeof(int), 1, file);
fwrite(&height, sizeof(int), 1, file);
fwrite(image, sizeof(uchar4), width * height, file);
fclose(file);
free(image);
return 0;
} | .file "tmpxft_000d84b5_00000000-6_pgp3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7rgb_subP6uchar4P8double24
.type _Z7rgb_subP6uchar4P8double24, @function
_Z7rgb_subP6uchar4P8double24:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z7rgb_subP6uchar4P8double24, .-_Z7rgb_subP6uchar4P8double24
.globl _Z7rgb_mulP8double24S0_
.type _Z7rgb_mulP8double24S0_, @function
_Z7rgb_mulP8double24S0_:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z7rgb_mulP8double24S0_, .-_Z7rgb_mulP8double24S0_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/Mikhail-Z/MAI/master/sem8/pgp/pgp3/pgp3.cu"
.align 8
.LC1:
.string "ERROR: in file '%s' in line %i: %s.\n"
.text
.globl _Z23copy_from_ram2dev_constP8double24Pi
.type _Z23copy_from_ram2dev_constP8double24Pi, @function
_Z23copy_from_ram2dev_constP8double24Pi:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbp
movq %rsi, %rbx
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL8nc_const(%rip), %rdi
call cudaMemcpyToSymbol@PLT
testl %eax, %eax
jne .L11
movslq (%rbx), %rax
leaq (%rax,%rax,2), %rdx
salq $3, %rdx
movl $1, %r8d
movl $0, %ecx
movq %rbp, %rsi
leaq _ZL10cavg_const(%rip), %rdi
call cudaMemcpyToSymbol@PLT
testl %eax, %eax
jne .L12
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $30, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L12:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $31, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z23copy_from_ram2dev_constP8double24Pi, .-_Z23copy_from_ram2dev_constP8double24Pi
.globl _Z50__device_stub__Z22min_dist_method_kernelP6uchar4mmP6uchar4mm
.type _Z50__device_stub__Z22min_dist_method_kernelP6uchar4mmP6uchar4mm, @function
_Z50__device_stub__Z22min_dist_method_kernelP6uchar4mmP6uchar4mm:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22min_dist_method_kernelP6uchar4mm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z50__device_stub__Z22min_dist_method_kernelP6uchar4mmP6uchar4mm, .-_Z50__device_stub__Z22min_dist_method_kernelP6uchar4mmP6uchar4mm
.globl _Z22min_dist_method_kernelP6uchar4mm
.type _Z22min_dist_method_kernelP6uchar4mm, @function
_Z22min_dist_method_kernelP6uchar4mm:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z22min_dist_method_kernelP6uchar4mmP6uchar4mm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z22min_dist_method_kernelP6uchar4mm, .-_Z22min_dist_method_kernelP6uchar4mm
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "%s"
.LC4:
.string "rb"
.LC5:
.string "%d"
.LC6:
.string "%d %d"
.LC7:
.string "wb"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1384, %rsp
.cfi_def_cfa_offset 1440
movq %fs:40, %rax
movq %rax, 1368(%rsp)
xorl %eax, %eax
leaq 848(%rsp), %rbx
movq %rbx, %rsi
leaq .LC3(%rip), %rbp
movq %rbp, %rdi
call __isoc23_scanf@PLT
leaq 1104(%rsp), %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC4(%rip), %rsi
movq %rbx, %rdi
call fopen@PLT
movq %rax, %rbx
leaq 32(%rsp), %rdi
movq %rax, %r8
movl $1, %ecx
movl $4, %edx
movl $4, %esi
call __fread_chk@PLT
leaq 36(%rsp), %rdi
movq %rbx, %r8
movl $1, %ecx
movl $4, %edx
movl $4, %esi
call __fread_chk@PLT
movslq 36(%rsp), %r12
movslq 32(%rsp), %rax
imulq %rax, %r12
leaq 0(,%r12,4), %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rbx, %r8
movq %r12, %rcx
movl $4, %edx
movq %r13, %rsi
movq %rax, %rdi
call __fread_chk@PLT
movq %rbx, %rdi
call fclose@PLT
leaq 40(%rsp), %rsi
leaq .LC5(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
cmpl $0, 40(%rsp)
jle .L22
leaq 80(%rsp), %r14
movl $0, %r15d
leaq 44(%rsp), %rax
movq %rax, 24(%rsp)
leaq .LC6(%rip), %r13
leaq 68(%rsp), %r12
.L25:
movq 24(%rsp), %rsi
leaq .LC5(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 44(%rsp), %eax
testl %eax, %eax
jle .L33
movq $0x000000000, 16(%rsp)
movq $0x000000000, 8(%rsp)
movq $0x000000000, (%rsp)
movl $0, %ebx
.L24:
leaq 56(%rsp), %rsi
movq %r12, %rdx
movq %r13, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 68(%rsp), %eax
imull 32(%rsp), %eax
addl 56(%rsp), %eax
cltq
leaq 0(%rbp,%rax,4), %rax
movzbl (%rax), %edx
pxor %xmm0, %xmm0
cvtsi2sdl %edx, %xmm0
addsd (%rsp), %xmm0
movsd %xmm0, (%rsp)
movzbl 1(%rax), %edx
pxor %xmm0, %xmm0
cvtsi2sdl %edx, %xmm0
addsd 8(%rsp), %xmm0
movsd %xmm0, 8(%rsp)
movzbl 2(%rax), %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
addsd 16(%rsp), %xmm0
movsd %xmm0, 16(%rsp)
addl $1, %ebx
movl 44(%rsp), %eax
cmpl %ebx, %eax
jg .L24
.L23:
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
movsd (%rsp), %xmm0
divsd %xmm1, %xmm0
movsd %xmm0, (%r14)
movsd 8(%rsp), %xmm0
divsd %xmm1, %xmm0
movsd %xmm0, 8(%r14)
movsd 16(%rsp), %xmm0
divsd %xmm1, %xmm0
movsd %xmm0, 16(%r14)
addl $1, %r15d
addq $24, %r14
cmpl %r15d, 40(%rsp)
jg .L25
.L22:
leaq 40(%rsp), %rsi
leaq 80(%rsp), %rdi
call _Z23copy_from_ram2dev_constP8double24Pi
movslq 32(%rsp), %rsi
movslq 36(%rsp), %rax
imulq %rax, %rsi
salq $2, %rsi
leaq 48(%rsp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L37
movslq 32(%rsp), %rdx
movslq 36(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $1, %ecx
movq %rbp, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L38
movl $16, 68(%rsp)
movl $16, 72(%rsp)
movl $1, 76(%rsp)
movl $16, 56(%rsp)
movl $16, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L28:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L40
movslq 32(%rsp), %rdx
movslq 36(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $2, %ecx
movq 48(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L41
movq 48(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L42
leaq 1104(%rsp), %rdi
leaq .LC7(%rip), %rsi
call fopen@PLT
movq %rax, %rbx
leaq 32(%rsp), %rdi
movq %rax, %rcx
movl $1, %edx
movl $4, %esi
call fwrite@PLT
leaq 36(%rsp), %rdi
movq %rbx, %rcx
movl $1, %edx
movl $4, %esi
call fwrite@PLT
movl 32(%rsp), %edx
imull 36(%rsp), %edx
movslq %edx, %rdx
movq %rbx, %rcx
movl $4, %esi
movq %rbp, %rdi
call fwrite@PLT
movq %rbx, %rdi
call fclose@PLT
movq %rbp, %rdi
call free@PLT
movq 1368(%rsp), %rax
subq %fs:40, %rax
jne .L43
movl $0, %eax
addq $1384, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
movq $0x000000000, 16(%rsp)
movq $0x000000000, 8(%rsp)
movq $0x000000000, (%rsp)
jmp .L23
.L37:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $97, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L38:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $98, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L39:
movslq 36(%rsp), %rdx
movslq 32(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z50__device_stub__Z22min_dist_method_kernelP6uchar4mmP6uchar4mm
jmp .L28
.L40:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $100, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L41:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $101, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L42:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $102, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L43:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC8:
.string "_Z22min_dist_method_kernelP6uchar4mm"
.section .rodata.str1.1
.LC9:
.string "cavg_const"
.LC10:
.string "nc_const"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z22min_dist_method_kernelP6uchar4mm(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $768, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10cavg_const(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8nc_const(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL8nc_const
.comm _ZL8nc_const,4,4
.local _ZL10cavg_const
.comm _ZL10cavg_const,768,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "stdio.h"
#include "stdlib.h"
#define MAX_NC 32
#define ERROR_HANDLING(call) { \
cudaError error = call; \
if(error != cudaSuccess) { \
fprintf(stderr, "ERROR: in file '%s' in line %i: %s.\n", \
__FILE__, __LINE__, cudaGetErrorString(error)); \
exit(1); \
} \
} while (0)
typedef struct double24 {double x; double y; double z;} double24;
__device__
double24 rgb_sub(uchar4 *a, double24 *b) {
double24 res = {a->x - b->x, a->y - b->y, a->z - b->z};
return res;
}
__device__
double rgb_mul(double24 *a, double24 *b) {
return a->x * b->x + a->y * b->y + a->z * b->z;
}
__constant__ double24 cavg_const[MAX_NC];
__constant__ int nc_const;
void copy_from_ram2dev_const(double24* cavg, int *nc) {
ERROR_HANDLING(cudaMemcpyToSymbol(nc_const, nc, sizeof(int)));
ERROR_HANDLING(cudaMemcpyToSymbol(cavg_const, cavg, (*nc)*sizeof(double24)));
}
__global__
void min_dist_method_kernel(uchar4* image, size_t width, size_t height) {
size_t idx = threadIdx.x + blockIdx.x * blockDim.x;
size_t idy = threadIdx.y + blockIdx.y * blockDim.y;
size_t offsetx = blockDim.x * gridDim.x;
size_t offsety = blockDim.y * gridDim.y;
for (size_t x = idx; x < width; x+=offsetx) {
for (size_t y = idy; y < height; y+=offsety) {
uchar4* pixel = &image[x*height + y];
int cur_max_class_idx = 0;
double24 sub_res = rgb_sub(pixel, &cavg_const[cur_max_class_idx]);
double cur_max_value = -rgb_mul(&sub_res, &sub_res);
for (int i = 1; i < nc_const; i++) {
double24 sub_res = rgb_sub(pixel, &cavg_const[i]);
double res = - rgb_mul(&sub_res, &sub_res);
if (res > cur_max_value) {
cur_max_value = res;
cur_max_class_idx = i;
}
}
pixel->w = cur_max_class_idx;
}
}
}
int main() {
int width, height;
char inputFilename[256];
char outputFilename[256];
scanf("%s", inputFilename);
scanf("%s", outputFilename);
FILE* file = fopen(inputFilename, "rb");
fread(&width, sizeof(int), 1, file);
fread(&height, sizeof(int), 1, file);
uchar4* image = (uchar4*)malloc(sizeof(uchar4)*height*width);
fread(image, sizeof(uchar4), width*height, file);
fclose(file);
int nc;
scanf("%d", &nc);
double24 cavg[MAX_NC];
int np_i;
for (int i = 0; i < nc; i++) {
scanf("%d", &np_i);
double24 tmp_sum = {0., 0., 0.};
int x, y;
for (int j = 0; j < np_i; j++) {
scanf("%d %d", &x, &y);
tmp_sum.x += image[y*width+x].x;
tmp_sum.y += image[y*width+x].y;
tmp_sum.z += image[y*width+x].z;
}
cavg[i].x = tmp_sum.x/np_i;
cavg[i].y = tmp_sum.y/np_i;
cavg[i].z = tmp_sum.z/np_i;
}
copy_from_ram2dev_const(cavg, &nc);
uchar4* dimage;
ERROR_HANDLING(cudaMalloc((void**)&dimage, sizeof(uchar4)*width*height));
ERROR_HANDLING(cudaMemcpy(dimage, image, sizeof(uchar4)*width*height, cudaMemcpyHostToDevice));
min_dist_method_kernel<<<dim3(16, 16), dim3(16, 16)>>>(dimage, width, height);
ERROR_HANDLING(cudaGetLastError());
ERROR_HANDLING(cudaMemcpy(image, dimage, sizeof(uchar4)*width*height, cudaMemcpyDeviceToHost));
ERROR_HANDLING(cudaFree(dimage));
file = fopen(outputFilename, "wb");
fwrite(&width, sizeof(int), 1, file);
fwrite(&height, sizeof(int), 1, file);
fwrite(image, sizeof(uchar4), width * height, file);
fclose(file);
free(image);
return 0;
} | #include <hip/hip_runtime.h>
#include "stdio.h"
#include "stdlib.h"
#define MAX_NC 32
#define ERROR_HANDLING(call) { \
hipError_t error = call; \
if(error != hipSuccess) { \
fprintf(stderr, "ERROR: in file '%s' in line %i: %s.\n", \
__FILE__, __LINE__, hipGetErrorString(error)); \
exit(1); \
} \
} while (0)
typedef struct double24 {double x; double y; double z;} double24;
__device__
double24 rgb_sub(uchar4 *a, double24 *b) {
double24 res = {a->x - b->x, a->y - b->y, a->z - b->z};
return res;
}
__device__
double rgb_mul(double24 *a, double24 *b) {
return a->x * b->x + a->y * b->y + a->z * b->z;
}
__constant__ double24 cavg_const[MAX_NC];
__constant__ int nc_const;
void copy_from_ram2dev_const(double24* cavg, int *nc) {
ERROR_HANDLING(hipMemcpyToSymbol(HIP_SYMBOL(nc_const), nc, sizeof(int)));
ERROR_HANDLING(hipMemcpyToSymbol(HIP_SYMBOL(cavg_const), cavg, (*nc)*sizeof(double24)));
}
__global__
void min_dist_method_kernel(uchar4* image, size_t width, size_t height) {
size_t idx = threadIdx.x + blockIdx.x * blockDim.x;
size_t idy = threadIdx.y + blockIdx.y * blockDim.y;
size_t offsetx = blockDim.x * gridDim.x;
size_t offsety = blockDim.y * gridDim.y;
for (size_t x = idx; x < width; x+=offsetx) {
for (size_t y = idy; y < height; y+=offsety) {
uchar4* pixel = &image[x*height + y];
int cur_max_class_idx = 0;
double24 sub_res = rgb_sub(pixel, &cavg_const[cur_max_class_idx]);
double cur_max_value = -rgb_mul(&sub_res, &sub_res);
for (int i = 1; i < nc_const; i++) {
double24 sub_res = rgb_sub(pixel, &cavg_const[i]);
double res = - rgb_mul(&sub_res, &sub_res);
if (res > cur_max_value) {
cur_max_value = res;
cur_max_class_idx = i;
}
}
pixel->w = cur_max_class_idx;
}
}
}
int main() {
int width, height;
char inputFilename[256];
char outputFilename[256];
scanf("%s", inputFilename);
scanf("%s", outputFilename);
FILE* file = fopen(inputFilename, "rb");
fread(&width, sizeof(int), 1, file);
fread(&height, sizeof(int), 1, file);
uchar4* image = (uchar4*)malloc(sizeof(uchar4)*height*width);
fread(image, sizeof(uchar4), width*height, file);
fclose(file);
int nc;
scanf("%d", &nc);
double24 cavg[MAX_NC];
int np_i;
for (int i = 0; i < nc; i++) {
scanf("%d", &np_i);
double24 tmp_sum = {0., 0., 0.};
int x, y;
for (int j = 0; j < np_i; j++) {
scanf("%d %d", &x, &y);
tmp_sum.x += image[y*width+x].x;
tmp_sum.y += image[y*width+x].y;
tmp_sum.z += image[y*width+x].z;
}
cavg[i].x = tmp_sum.x/np_i;
cavg[i].y = tmp_sum.y/np_i;
cavg[i].z = tmp_sum.z/np_i;
}
copy_from_ram2dev_const(cavg, &nc);
uchar4* dimage;
ERROR_HANDLING(hipMalloc((void**)&dimage, sizeof(uchar4)*width*height));
ERROR_HANDLING(hipMemcpy(dimage, image, sizeof(uchar4)*width*height, hipMemcpyHostToDevice));
min_dist_method_kernel<<<dim3(16, 16), dim3(16, 16)>>>(dimage, width, height);
ERROR_HANDLING(hipGetLastError());
ERROR_HANDLING(hipMemcpy(image, dimage, sizeof(uchar4)*width*height, hipMemcpyDeviceToHost));
ERROR_HANDLING(hipFree(dimage));
file = fopen(outputFilename, "wb");
fwrite(&width, sizeof(int), 1, file);
fwrite(&height, sizeof(int), 1, file);
fwrite(image, sizeof(uchar4), width * height, file);
fclose(file);
free(image);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "stdio.h"
#include "stdlib.h"
#define MAX_NC 32
#define ERROR_HANDLING(call) { \
hipError_t error = call; \
if(error != hipSuccess) { \
fprintf(stderr, "ERROR: in file '%s' in line %i: %s.\n", \
__FILE__, __LINE__, hipGetErrorString(error)); \
exit(1); \
} \
} while (0)
typedef struct double24 {double x; double y; double z;} double24;
__device__
double24 rgb_sub(uchar4 *a, double24 *b) {
double24 res = {a->x - b->x, a->y - b->y, a->z - b->z};
return res;
}
__device__
double rgb_mul(double24 *a, double24 *b) {
return a->x * b->x + a->y * b->y + a->z * b->z;
}
__constant__ double24 cavg_const[MAX_NC];
__constant__ int nc_const;
void copy_from_ram2dev_const(double24* cavg, int *nc) {
ERROR_HANDLING(hipMemcpyToSymbol(HIP_SYMBOL(nc_const), nc, sizeof(int)));
ERROR_HANDLING(hipMemcpyToSymbol(HIP_SYMBOL(cavg_const), cavg, (*nc)*sizeof(double24)));
}
__global__
void min_dist_method_kernel(uchar4* image, size_t width, size_t height) {
size_t idx = threadIdx.x + blockIdx.x * blockDim.x;
size_t idy = threadIdx.y + blockIdx.y * blockDim.y;
size_t offsetx = blockDim.x * gridDim.x;
size_t offsety = blockDim.y * gridDim.y;
for (size_t x = idx; x < width; x+=offsetx) {
for (size_t y = idy; y < height; y+=offsety) {
uchar4* pixel = &image[x*height + y];
int cur_max_class_idx = 0;
double24 sub_res = rgb_sub(pixel, &cavg_const[cur_max_class_idx]);
double cur_max_value = -rgb_mul(&sub_res, &sub_res);
for (int i = 1; i < nc_const; i++) {
double24 sub_res = rgb_sub(pixel, &cavg_const[i]);
double res = - rgb_mul(&sub_res, &sub_res);
if (res > cur_max_value) {
cur_max_value = res;
cur_max_class_idx = i;
}
}
pixel->w = cur_max_class_idx;
}
}
}
int main() {
int width, height;
char inputFilename[256];
char outputFilename[256];
scanf("%s", inputFilename);
scanf("%s", outputFilename);
FILE* file = fopen(inputFilename, "rb");
fread(&width, sizeof(int), 1, file);
fread(&height, sizeof(int), 1, file);
uchar4* image = (uchar4*)malloc(sizeof(uchar4)*height*width);
fread(image, sizeof(uchar4), width*height, file);
fclose(file);
int nc;
scanf("%d", &nc);
double24 cavg[MAX_NC];
int np_i;
for (int i = 0; i < nc; i++) {
scanf("%d", &np_i);
double24 tmp_sum = {0., 0., 0.};
int x, y;
for (int j = 0; j < np_i; j++) {
scanf("%d %d", &x, &y);
tmp_sum.x += image[y*width+x].x;
tmp_sum.y += image[y*width+x].y;
tmp_sum.z += image[y*width+x].z;
}
cavg[i].x = tmp_sum.x/np_i;
cavg[i].y = tmp_sum.y/np_i;
cavg[i].z = tmp_sum.z/np_i;
}
copy_from_ram2dev_const(cavg, &nc);
uchar4* dimage;
ERROR_HANDLING(hipMalloc((void**)&dimage, sizeof(uchar4)*width*height));
ERROR_HANDLING(hipMemcpy(dimage, image, sizeof(uchar4)*width*height, hipMemcpyHostToDevice));
min_dist_method_kernel<<<dim3(16, 16), dim3(16, 16)>>>(dimage, width, height);
ERROR_HANDLING(hipGetLastError());
ERROR_HANDLING(hipMemcpy(image, dimage, sizeof(uchar4)*width*height, hipMemcpyDeviceToHost));
ERROR_HANDLING(hipFree(dimage));
file = fopen(outputFilename, "wb");
fwrite(&width, sizeof(int), 1, file);
fwrite(&height, sizeof(int), 1, file);
fwrite(image, sizeof(uchar4), width * height, file);
fclose(file);
free(image);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm
.globl _Z22min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm
.p2align 8
.type _Z22min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm,@function
_Z22min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x8
v_and_b32_e32 v3, 0x3ff, v0
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s17, s6, 0xffff
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[1:2], null, s14, s17, v[3:4]
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_9
s_load_b32 s14, s[4:5], 0xc
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, nc_const@rel32@lo+4
s_addc_u32 s7, s7, nc_const@rel32@hi+12
s_load_b64 s[18:19], s[4:5], 0x0
s_load_b64 s[4:5], s[0:1], 0x10
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, cavg_const@rel32@lo+4
s_addc_u32 s9, s9, cavg_const@rel32@hi+12
s_getpc_b64 s[10:11]
s_add_u32 s10, s10, cavg_const@rel32@lo+12
s_addc_u32 s11, s11, cavg_const@rel32@hi+20
s_load_b32 s16, s[6:7], 0x0
s_getpc_b64 s[12:13]
s_add_u32 s12, s12, cavg_const@rel32@lo+20
s_addc_u32 s13, s13, cavg_const@rel32@hi+28
s_load_b64 s[6:7], s[0:1], 0x0
s_clause 0x2
s_load_b64 s[8:9], s[8:9], 0x0
s_load_b64 s[10:11], s[10:11], 0x0
s_load_b64 s[12:13], s[12:13], 0x0
v_bfe_u32 v0, v0, 10, 10
s_mov_b32 s1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s20, s1
s_mov_b32 s21, s1
s_waitcnt lgkmcnt(0)
s_lshr_b32 s14, s14, 16
s_mul_i32 s17, s18, s17
v_mad_u64_u32 v[3:4], null, s15, s14, v[0:1]
v_mov_b32_e32 v4, 0
s_cmp_gt_i32 s16, 1
s_mul_i32 s19, s19, s14
s_cselect_b32 s18, -1, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u64_e64 s0, s[4:5], v[3:4]
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s22
v_add_co_u32 v1, vcc_lo, v1, s17
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[1:2]
s_or_b32 s21, vcc_lo, s21
s_and_not1_b32 exec_lo, exec_lo, s21
s_cbranch_execz .LBB0_9
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s22, s0
s_cbranch_execz .LBB0_2
v_mul_lo_u32 v0, v2, s4
v_mul_lo_u32 v7, v1, s5
v_mad_u64_u32 v[5:6], null, v1, s4, 0
s_mov_b32 s23, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v6, v6, v7, v0
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v17, vcc_lo, s7, v6, vcc_lo
v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
s_branch .LBB0_6
.LBB0_5:
s_set_inst_prefetch_distance 0x2
v_add_co_u32 v5, vcc_lo, v5, s19
v_add_co_ci_u32_e32 v6, vcc_lo, s20, v6, vcc_lo
global_store_b8 v[7:8], v18, off offset:3
v_cmp_le_u64_e32 vcc_lo, s[4:5], v[5:6]
s_or_b32 s23, vcc_lo, s23
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s23
s_cbranch_execz .LBB0_2
.LBB0_6:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[5:6]
v_mov_b32_e32 v18, 0
v_add_co_u32 v7, vcc_lo, v0, v7
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, v17, v8, vcc_lo
s_and_not1_b32 vcc_lo, exec_lo, s18
s_cbranch_vccnz .LBB0_5
s_clause 0x2
global_load_u8 v9, v[7:8], off offset:1
global_load_u8 v11, v[7:8], off
global_load_u8 v13, v[7:8], off offset:2
s_mov_b32 s24, 1
s_getpc_b64 s[14:15]
s_add_u32 s14, s14, cavg_const@rel32@lo+44
s_addc_u32 s15, s15, cavg_const@rel32@hi+52
s_waitcnt vmcnt(2)
v_cvt_f64_u32_e32 v[9:10], v9
s_waitcnt vmcnt(1)
v_cvt_f64_u32_e32 v[11:12], v11
s_waitcnt vmcnt(0)
v_cvt_f64_u32_e32 v[13:14], v13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[15:16], v[9:10], -s[10:11]
v_add_f64 v[18:19], v[11:12], -s[8:9]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[20:21], v[13:14], -s[12:13]
v_mul_f64 v[15:16], v[15:16], v[15:16]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[15:16], v[18:19], v[18:19], v[15:16]
v_mov_b32_e32 v18, 0
v_fma_f64 v[15:16], v[20:21], v[20:21], v[15:16]
s_delay_alu instid0(VALU_DEP_1)
v_xor_b32_e32 v16, 0x80000000, v16
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_8:
s_add_u32 s26, s14, -16
s_addc_u32 s27, s15, -1
s_add_u32 s28, s14, -8
s_addc_u32 s29, s15, -1
s_clause 0x2
s_load_b64 s[26:27], s[26:27], 0x0
s_load_b64 s[28:29], s[28:29], 0x0
s_load_b64 s[30:31], s[14:15], 0x0
s_waitcnt lgkmcnt(0)
v_add_f64 v[21:22], v[11:12], -s[26:27]
v_add_f64 v[19:20], v[9:10], -s[28:29]
v_add_f64 v[23:24], v[13:14], -s[30:31]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[19:20], v[19:20], v[19:20]
v_fma_f64 v[19:20], v[21:22], v[21:22], v[19:20]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[19:20], v[23:24], v[23:24], v[19:20]
v_cmp_lt_f64_e64 vcc_lo, v[15:16], -v[19:20]
v_xor_b32_e32 v20, 0x80000000, v20
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v18, v18, s24, vcc_lo
s_add_i32 s24, s24, 1
v_dual_cndmask_b32 v16, v16, v20 :: v_dual_cndmask_b32 v15, v15, v19
s_add_u32 s14, s14, 24
s_addc_u32 s15, s15, 0
s_cmp_eq_u32 s16, s24
s_cbranch_scc0 .LBB0_8
s_branch .LBB0_5
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 25
.amdhsa_next_free_sgpr 32
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z22min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm, .Lfunc_end0-_Z22min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected cavg_const
.type cavg_const,@object
.section .bss,"aw",@nobits
.globl cavg_const
.p2align 4, 0x0
cavg_const:
.zero 768
.size cavg_const, 768
.protected nc_const
.type nc_const,@object
.globl nc_const
.p2align 2, 0x0
nc_const:
.long 0
.size nc_const, 4
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym cavg_const
.addrsig_sym nc_const
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm
.private_segment_fixed_size: 0
.sgpr_count: 34
.sgpr_spill_count: 0
.symbol: _Z22min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 25
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "stdio.h"
#include "stdlib.h"
#define MAX_NC 32
#define ERROR_HANDLING(call) { \
hipError_t error = call; \
if(error != hipSuccess) { \
fprintf(stderr, "ERROR: in file '%s' in line %i: %s.\n", \
__FILE__, __LINE__, hipGetErrorString(error)); \
exit(1); \
} \
} while (0)
typedef struct double24 {double x; double y; double z;} double24;
__device__
double24 rgb_sub(uchar4 *a, double24 *b) {
double24 res = {a->x - b->x, a->y - b->y, a->z - b->z};
return res;
}
__device__
double rgb_mul(double24 *a, double24 *b) {
return a->x * b->x + a->y * b->y + a->z * b->z;
}
__constant__ double24 cavg_const[MAX_NC];
__constant__ int nc_const;
void copy_from_ram2dev_const(double24* cavg, int *nc) {
ERROR_HANDLING(hipMemcpyToSymbol(HIP_SYMBOL(nc_const), nc, sizeof(int)));
ERROR_HANDLING(hipMemcpyToSymbol(HIP_SYMBOL(cavg_const), cavg, (*nc)*sizeof(double24)));
}
__global__
void min_dist_method_kernel(uchar4* image, size_t width, size_t height) {
size_t idx = threadIdx.x + blockIdx.x * blockDim.x;
size_t idy = threadIdx.y + blockIdx.y * blockDim.y;
size_t offsetx = blockDim.x * gridDim.x;
size_t offsety = blockDim.y * gridDim.y;
for (size_t x = idx; x < width; x+=offsetx) {
for (size_t y = idy; y < height; y+=offsety) {
uchar4* pixel = &image[x*height + y];
int cur_max_class_idx = 0;
double24 sub_res = rgb_sub(pixel, &cavg_const[cur_max_class_idx]);
double cur_max_value = -rgb_mul(&sub_res, &sub_res);
for (int i = 1; i < nc_const; i++) {
double24 sub_res = rgb_sub(pixel, &cavg_const[i]);
double res = - rgb_mul(&sub_res, &sub_res);
if (res > cur_max_value) {
cur_max_value = res;
cur_max_class_idx = i;
}
}
pixel->w = cur_max_class_idx;
}
}
}
int main() {
int width, height;
char inputFilename[256];
char outputFilename[256];
scanf("%s", inputFilename);
scanf("%s", outputFilename);
FILE* file = fopen(inputFilename, "rb");
fread(&width, sizeof(int), 1, file);
fread(&height, sizeof(int), 1, file);
uchar4* image = (uchar4*)malloc(sizeof(uchar4)*height*width);
fread(image, sizeof(uchar4), width*height, file);
fclose(file);
int nc;
scanf("%d", &nc);
double24 cavg[MAX_NC];
int np_i;
for (int i = 0; i < nc; i++) {
scanf("%d", &np_i);
double24 tmp_sum = {0., 0., 0.};
int x, y;
for (int j = 0; j < np_i; j++) {
scanf("%d %d", &x, &y);
tmp_sum.x += image[y*width+x].x;
tmp_sum.y += image[y*width+x].y;
tmp_sum.z += image[y*width+x].z;
}
cavg[i].x = tmp_sum.x/np_i;
cavg[i].y = tmp_sum.y/np_i;
cavg[i].z = tmp_sum.z/np_i;
}
copy_from_ram2dev_const(cavg, &nc);
uchar4* dimage;
ERROR_HANDLING(hipMalloc((void**)&dimage, sizeof(uchar4)*width*height));
ERROR_HANDLING(hipMemcpy(dimage, image, sizeof(uchar4)*width*height, hipMemcpyHostToDevice));
min_dist_method_kernel<<<dim3(16, 16), dim3(16, 16)>>>(dimage, width, height);
ERROR_HANDLING(hipGetLastError());
ERROR_HANDLING(hipMemcpy(image, dimage, sizeof(uchar4)*width*height, hipMemcpyDeviceToHost));
ERROR_HANDLING(hipFree(dimage));
file = fopen(outputFilename, "wb");
fwrite(&width, sizeof(int), 1, file);
fwrite(&height, sizeof(int), 1, file);
fwrite(image, sizeof(uchar4), width * height, file);
fclose(file);
free(image);
return 0;
} | .text
.file "pgp3.hip"
.globl _Z23copy_from_ram2dev_constP8double24Pi # -- Begin function _Z23copy_from_ram2dev_constP8double24Pi
.p2align 4, 0x90
.type _Z23copy_from_ram2dev_constP8double24Pi,@function
_Z23copy_from_ram2dev_constP8double24Pi: # @_Z23copy_from_ram2dev_constP8double24Pi
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %r14
movq %rdi, %rbx
movl $nc_const, %edi
movl $4, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
testl %eax, %eax
jne .LBB0_1
# %bb.3:
movslq (%r14), %rax
shlq $3, %rax
leaq (%rax,%rax,2), %rdx
movl $cavg_const, %edi
movq %rbx, %rsi
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
testl %eax, %eax
jne .LBB0_4
# %bb.5:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_1:
.cfi_def_cfa_offset 32
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movq %rbx, %rdi
movl $32, %ecx
jmp .LBB0_2
.LBB0_4:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movq %rbx, %rdi
movl $33, %ecx
.LBB0_2:
movq %rax, %r8
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z23copy_from_ram2dev_constP8double24Pi, .Lfunc_end0-_Z23copy_from_ram2dev_constP8double24Pi
.cfi_endproc
# -- End function
.globl _Z37__device_stub__min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm # -- Begin function _Z37__device_stub__min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm
.p2align 4, 0x90
.type _Z37__device_stub__min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm,@function
_Z37__device_stub__min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm: # @_Z37__device_stub__min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z37__device_stub__min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm, .Lfunc_end1-_Z37__device_stub__min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1464, %rsp # imm = 0x5B8
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 1200(%rsp), %rbx
movl $.L.str.2, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
leaq 176(%rsp), %rsi
movl $.L.str.2, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.L.str.3, %esi
movq %rbx, %rdi
callq fopen
movq %rax, %r15
leaq 16(%rsp), %rdi
movl $4, %esi
movl $1, %edx
movq %rax, %rcx
callq fread
leaq 12(%rsp), %rdi
movl $4, %esi
movl $1, %edx
movq %r15, %rcx
callq fread
movslq 12(%rsp), %rax
movslq 16(%rsp), %r12
movq %r12, %r13
movq %rax, 80(%rsp) # 8-byte Spill
imulq %rax, %r13
leaq (,%r13,4), %rdi
movq %rdi, 88(%rsp) # 8-byte Spill
callq malloc
movq %rax, %rbx
movl $4, %esi
movq %rax, %rdi
movq %r13, %rdx
movq %r15, %rcx
callq fread
movq %r15, %rdi
callq fclose
leaq 8(%rsp), %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
callq __isoc23_scanf
cmpl $0, 8(%rsp)
jle .LBB2_5
# %bb.1: # %.lr.ph63.preheader
leaq 48(%rsp), %rbp
leaq 32(%rsp), %r13
xorl %r14d, %r14d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_3: # in Loop: Header=BB2_2 Depth=1
xorpd %xmm1, %xmm1
xorpd %xmm2, %xmm2
xorpd %xmm3, %xmm3
.LBB2_4: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd %xmm0, %xmm3
leaq (%r14,%r14,2), %rax
movsd %xmm3, 432(%rsp,%rax,8)
divsd %xmm0, %xmm2
movsd %xmm2, 440(%rsp,%rax,8)
divsd %xmm0, %xmm1
movsd %xmm1, 448(%rsp,%rax,8)
incq %r14
movslq 8(%rsp), %rax
cmpq %rax, %r14
jge .LBB2_5
.LBB2_2: # %.lr.ph63
# =>This Loop Header: Depth=1
# Child Loop BB2_9 Depth 2
movl $.L.str.4, %edi
leaq 20(%rsp), %rsi
xorl %eax, %eax
callq __isoc23_scanf
movl 20(%rsp), %eax
testl %eax, %eax
jle .LBB2_3
# %bb.8: # %.lr.ph.preheader
# in Loop: Header=BB2_2 Depth=1
xorl %r15d, %r15d
xorps %xmm3, %xmm3
xorps %xmm2, %xmm2
xorps %xmm1, %xmm1
.p2align 4, 0x90
.LBB2_9: # %.lr.ph
# Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movsd %xmm3, 96(%rsp) # 8-byte Spill
movsd %xmm2, 104(%rsp) # 8-byte Spill
movsd %xmm1, 112(%rsp) # 8-byte Spill
movl $.L.str.5, %edi
movq %rbp, %rsi
movq %r13, %rdx
xorl %eax, %eax
callq __isoc23_scanf
movsd 96(%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
movsd 104(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
movsd 112(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
movslq 32(%rsp), %rax
imulq %r12, %rax
movslq 48(%rsp), %rcx
addq %rax, %rcx
movzbl (%rbx,%rcx,4), %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
addsd %xmm0, %xmm3
movzbl 1(%rbx,%rcx,4), %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
addsd %xmm0, %xmm2
movzbl 2(%rbx,%rcx,4), %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
addsd %xmm0, %xmm1
incl %r15d
movl 20(%rsp), %eax
cmpl %eax, %r15d
jl .LBB2_9
jmp .LBB2_4
.LBB2_5: # %._crit_edge64
leaq 432(%rsp), %rdi
leaq 8(%rsp), %rsi
callq _Z23copy_from_ram2dev_constP8double24Pi
leaq 24(%rsp), %rdi
movq 88(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_6
# %bb.10:
movq 24(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_11
# %bb.12:
movabsq $68719476752, %rdi # imm = 0x1000000010
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_14
# %bb.13:
movq 24(%rsp), %rax
movq %rax, 168(%rsp)
movq %r12, 160(%rsp)
movq 80(%rsp), %rax # 8-byte Reload
movq %rax, 152(%rsp)
leaq 168(%rsp), %rax
movq %rax, 48(%rsp)
leaq 160(%rsp), %rax
movq %rax, 56(%rsp)
leaq 152(%rsp), %rax
movq %rax, 64(%rsp)
leaq 32(%rsp), %rdi
leaq 136(%rsp), %rsi
leaq 128(%rsp), %rdx
leaq 120(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 136(%rsp), %rcx
movl 144(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z22min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm, %edi
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_14:
callq hipGetLastError
testl %eax, %eax
jne .LBB2_15
# %bb.16:
movq 24(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_17
# %bb.18:
movq 24(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_19
# %bb.20:
leaq 176(%rsp), %rdi
movl $.L.str.6, %esi
callq fopen
movq %rax, %r14
leaq 16(%rsp), %rdi
movl $4, %esi
movl $1, %edx
movq %rax, %rcx
callq fwrite
leaq 12(%rsp), %rdi
movl $4, %esi
movl $1, %edx
movq %r14, %rcx
callq fwrite
movslq 16(%rsp), %rax
movslq 12(%rsp), %rdx
imulq %rax, %rdx
movl $4, %esi
movq %rbx, %rdi
movq %r14, %rcx
callq fwrite
movq %r14, %rdi
callq fclose
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $1464, %rsp # imm = 0x5B8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_6:
.cfi_def_cfa_offset 1520
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movq %rbx, %rdi
movl $99, %ecx
jmp .LBB2_7
.LBB2_11:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movq %rbx, %rdi
movl $100, %ecx
jmp .LBB2_7
.LBB2_15:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movq %rbx, %rdi
movl $102, %ecx
jmp .LBB2_7
.LBB2_17:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movq %rbx, %rdi
movl $103, %ecx
jmp .LBB2_7
.LBB2_19:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movq %rbx, %rdi
movl $104, %ecx
.LBB2_7:
movq %rax, %r8
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $cavg_const, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $768, %r9d # imm = 0x300
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $nc_const, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type cavg_const,@object # @cavg_const
.local cavg_const
.comm cavg_const,768,16
.type nc_const,@object # @nc_const
.local nc_const
.comm nc_const,4,4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "ERROR: in file '%s' in line %i: %s.\n"
.size .L.str, 37
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/Mikhail-Z/MAI/master/sem8/pgp/pgp3/pgp3.hip"
.size .L.str.1, 101
.type _Z22min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm,@object # @_Z22min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm
.section .rodata,"a",@progbits
.globl _Z22min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm
.p2align 3, 0x0
_Z22min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm:
.quad _Z37__device_stub__min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm
.size _Z22min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "%s"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "rb"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d"
.size .L.str.4, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d %d"
.size .L.str.5, 6
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "wb"
.size .L.str.6, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z22min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm"
.size .L__unnamed_1, 54
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "cavg_const"
.size .L__unnamed_2, 11
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "nc_const"
.size .L__unnamed_3, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym cavg_const
.addrsig_sym nc_const
.addrsig_sym _Z22min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z22min_dist_method_kernelP6uchar4mm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e620000002600 */
/*0040*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fc600078e0203 */
/*0050*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002200 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fc80003f06070 */
/*0070*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x16c], PT, P0 ; /* 0x00005b00ff007a0c */
/* 0x000fda0003f06100 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x3][0x300] ; /* 0x00c0c000ff057624 */
/* 0x002fe200078e00ff */
/*00a0*/ ULDC UR6, c[0x0][0xc] ; /* 0x0000030000067ab9 */
/* 0x000fe20000000800 */
/*00b0*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fe200078e0203 */
/*00c0*/ ULDC UR7, c[0x0][0x10] ; /* 0x0000040000077ab9 */
/* 0x000fe20000000800 */
/*00d0*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe200078e00ff */
/*00e0*/ ISETP.GT.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe20003f04270 */
/*00f0*/ ULDC.64 UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000a00 */
/*0100*/ UIMAD UR4, UR4, UR6, URZ ; /* 0x00000006040472a4 */
/* 0x000fe4000f8e023f */
/*0110*/ UIMAD UR5, UR5, UR7, URZ ; /* 0x00000007050572a4 */
/* 0x000fc6000f8e023f */
/*0120*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fca0000000a00 */
/*0130*/ @P0 BRA 0x2f0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0140*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f06070 */
/*0150*/ BSSY B0, 0x290 ; /* 0x0000013000007945 */
/* 0x000fe60003800000 */
/*0160*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x174], PT, P0 ; /* 0x00005d00ff007a0c */
/* 0x000fda0003f06100 */
/*0170*/ @P0 BRA 0x280 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*0180*/ IMAD R5, R3, c[0x0][0x170], RZ ; /* 0x00005c0003057a24 */
/* 0x000fe400078e02ff */
/*0190*/ IMAD.MOV.U32 R8, RZ, RZ, R0 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0000 */
/*01a0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe400078e00ff */
/*01b0*/ IMAD R11, R2, c[0x0][0x174], R5 ; /* 0x00005d00020b7a24 */
/* 0x000fe400078e0205 */
/*01c0*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0008 */
/*01d0*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0009 */
/*01e0*/ IMAD.WIDE.U32 R4, R2, c[0x0][0x170], R4 ; /* 0x00005c0002047a25 */
/* 0x000fc800078e0004 */
/*01f0*/ IMAD.IADD R5, R5, 0x1, R11 ; /* 0x0000000105057824 */
/* 0x000fe200078e020b */
/*0200*/ LEA R6, P0, R4, c[0x0][0x160], 0x2 ; /* 0x0000580004067a11 */
/* 0x000fc800078010ff */
/*0210*/ LEA.HI.X R7, R4, c[0x0][0x164], R5, 0x2, P0 ; /* 0x0000590004077a11 */
/* 0x000fe400000f1405 */
/*0220*/ IADD3 R8, P0, R8, UR5, RZ ; /* 0x0000000508087c10 */
/* 0x000fc6000ff1e0ff */
/*0230*/ STG.E.U8 [R6.64+0x3], RZ ; /* 0x000003ff06007986 */
/* 0x0001e4000c101106 */
/*0240*/ IMAD.X R9, RZ, RZ, R9, P0 ; /* 0x000000ffff097224 */
/* 0x000fe200000e0609 */
/*0250*/ ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x170], PT ; /* 0x00005c0008007a0c */
/* 0x000fc80003f06070 */
/*0260*/ ISETP.GE.U32.AND.EX P0, PT, R9, c[0x0][0x174], PT, P0 ; /* 0x00005d0009007a0c */
/* 0x000fda0003f06100 */
/*0270*/ @!P0 BRA 0x1c0 ; /* 0xffffff4000008947 */
/* 0x001fea000383ffff */
/*0280*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0290*/ IADD3 R2, P0, R2, UR4, RZ ; /* 0x0000000402027c10 */
/* 0x000fca000ff1e0ff */
/*02a0*/ IMAD.X R3, RZ, RZ, R3, P0 ; /* 0x000000ffff037224 */
/* 0x000fe200000e0603 */
/*02b0*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fc80003f06070 */
/*02c0*/ ISETP.GE.U32.AND.EX P0, PT, R3, c[0x0][0x16c], PT, P0 ; /* 0x00005b0003007a0c */
/* 0x000fda0003f06100 */
/*02d0*/ @!P0 BRA 0x140 ; /* 0xfffffe6000008947 */
/* 0x000fea000383ffff */
/*02e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02f0*/ IADD3 R4, R5.reuse, -0x1, RZ ; /* 0xffffffff05047810 */
/* 0x040fe40007ffe0ff */
/*0300*/ IADD3 R5, R5, -0x2, RZ ; /* 0xfffffffe05057810 */
/* 0x000fe40007ffe0ff */
/*0310*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fc800078ec0ff */
/*0320*/ IADD3 R6, -R4, c[0x3][0x300], RZ ; /* 0x00c0c00004067a10 */
/* 0x000fe40007ffe1ff */
/*0330*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f06070 */
/*0340*/ BSSY B0, 0xca0 ; /* 0x0000095000007945 */
/* 0x000fe60003800000 */
/*0350*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x174], PT, P0 ; /* 0x00005d00ff007a0c */
/* 0x000fda0003f06100 */
/*0360*/ @P0 BRA 0xc90 ; /* 0x0000092000000947 */
/* 0x001fea0003800000 */
/*0370*/ IMAD.MOV.U32 R8, RZ, RZ, R0 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0000 */
/*0380*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe400078e00ff */
/*0390*/ IMAD R7, R3, c[0x0][0x170], RZ ; /* 0x00005c0003077a24 */
/* 0x000fe400078e02ff */
/*03a0*/ IMAD.WIDE.U32 R10, R2, c[0x0][0x170], R8 ; /* 0x00005c00020a7a25 */
/* 0x000fc800078e0008 */
/*03b0*/ IMAD R7, R2, c[0x0][0x174], R7 ; /* 0x00005d0002077a24 */
/* 0x000fe200078e0207 */
/*03c0*/ LEA R22, P0, R10, c[0x0][0x160], 0x2 ; /* 0x000058000a167a11 */
/* 0x000fc600078010ff */
/*03d0*/ IMAD.IADD R7, R11, 0x1, R7 ; /* 0x000000010b077824 */
/* 0x000fca00078e0207 */
/*03e0*/ LEA.HI.X R23, R10, c[0x0][0x164], R7, 0x2, P0 ; /* 0x000059000a177a11 */
/* 0x000fca00000f1407 */
/*03f0*/ LDG.E R22, [R22.64] ; /* 0x0000000616167981 */
/* 0x000ea2000c1e1900 */
/*0400*/ ISETP.GE.U32.AND P1, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fe20003f26070 */
/*0410*/ IMAD.MOV.U32 R26, RZ, RZ, RZ ; /* 0x000000ffff1a7224 */
/* 0x000fe200078e00ff */
/*0420*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*0430*/ IMAD.MOV.U32 R25, RZ, RZ, 0x1 ; /* 0x00000001ff197424 */
/* 0x000fe200078e00ff */
/*0440*/ I2F.F64.U8 R10, R22.B1 ; /* 0x10000016000a7312 */
/* 0x005e300000001800 */
/*0450*/ I2F.F64.U8 R12, R22 ; /* 0x00000016000c7312 */
/* 0x000e700000001800 */
/*0460*/ I2F.F64.U8 R14, R22.B2 ; /* 0x20000016000e7312 */
/* 0x000ea20000001800 */
/*0470*/ DADD R18, R10, -c[0x3][0x8] ; /* 0x80c002000a127629 */
/* 0x001e0c0000000000 */
/*0480*/ DMUL R20, R18, R18 ; /* 0x0000001212147228 */
/* 0x001fc80000000000 */
/*0490*/ DADD R16, R12, -c[0x3][0x0] ; /* 0x80c000000c107629 */
/* 0x002e080000000000 */
/*04a0*/ DADD R18, R14, -c[0x3][0x10] ; /* 0x80c004000e127629 */
/* 0x004fc80000000000 */
/*04b0*/ DFMA R20, R16, R16, R20 ; /* 0x000000101014722b */
/* 0x001e0c0000000014 */
/*04c0*/ DFMA R18, R18, R18, R20 ; /* 0x000000121212722b */
/* 0x001e0c0000000014 */
/*04d0*/ DADD R18, -RZ, -R18 ; /* 0x00000000ff127229 */
/* 0x001e220000000912 */
/*04e0*/ @!P1 BRA 0x900 ; /* 0x0000041000009947 */
/* 0x000fea0003800000 */
/*04f0*/ IMAD.MOV.U32 R26, RZ, RZ, RZ ; /* 0x000000ffff1a7224 */
/* 0x000fe400078e00ff */
/*0500*/ IMAD.MOV.U32 R25, RZ, RZ, 0x1 ; /* 0x00000001ff197424 */
/* 0x000fe400078e00ff */
/*0510*/ IMAD.MOV.U32 R24, RZ, RZ, RZ ; /* 0x000000ffff187224 */
/* 0x000fe400078e00ff */
/*0520*/ IMAD.MOV.U32 R7, RZ, RZ, R6 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0006 */
/*0530*/ LDC.64 R16, c[0x3][R24+0x20] ; /* 0x00c0080018107b82 */
/* 0x000e620000000a00 */
/*0540*/ IADD3 R7, R7, -0x4, RZ ; /* 0xfffffffc07077810 */
/* 0x000fce0007ffe0ff */
/*0550*/ LDC.64 R22, c[0x3][R24+0x18] ; /* 0x00c0060018167b82 */
/* 0x000eb00000000a00 */
/*0560*/ LDC.64 R20, c[0x3][R24+0x28] ; /* 0x00c00a0018147b82 */
/* 0x000ee20000000a00 */
/*0570*/ DADD R16, R10, -R16 ; /* 0x000000000a107229 */
/* 0x002e4c0000000810 */
/*0580*/ DMUL R16, R16, R16 ; /* 0x0000001010107228 */
/* 0x002fc80000000000 */
/*0590*/ DADD R22, R12, -R22 ; /* 0x000000000c167229 */
/* 0x004e4c0000000816 */
/*05a0*/ DFMA R16, R22, R22, R16 ; /* 0x000000161610722b */
/* 0x0023c80000000010 */
/*05b0*/ DADD R20, R14, -R20 ; /* 0x000000000e147229 */
/* 0x008ea20000000814 */
/*05c0*/ LDC.64 R22, c[0x3][R24+0x30] ; /* 0x00c00c0018167b82 */
/* 0x002e6a0000000a00 */
/*05d0*/ DFMA R16, R20, R20, R16 ; /* 0x000000141410722b */
/* 0x004e8c0000000010 */
/*05e0*/ DADD R20, -RZ, -R16 ; /* 0x00000000ff147229 */
/* 0x004fc80000000910 */
/*05f0*/ DSETP.GEU.AND P2, PT, R18, -R16, PT ; /* 0x800000101200722a */
/* 0x0010a40003f4e000 */
/*0600*/ LDC.64 R16, c[0x3][R24+0x38] ; /* 0x00c00e0018107b82 */
/* 0x001e280000000a00 */
/*0610*/ FSEL R20, R20, R18, !P2 ; /* 0x0000001214147208 */
/* 0x004fe40005000000 */
/*0620*/ FSEL R21, R21, R19, !P2 ; /* 0x0000001315157208 */
/* 0x000fe20005000000 */
/*0630*/ DADD R22, R12, -R22 ; /* 0x000000000c167229 */
/* 0x002fe20000000816 */
/*0640*/ LDC.64 R18, c[0x3][R24+0x40] ; /* 0x00c0100018127b82 */
/* 0x000e620000000a00 */
/*0650*/ SEL R26, R25, R26, !P2 ; /* 0x0000001a191a7207 */
/* 0x000fc40005000000 */
/*0660*/ ISETP.NE.AND P2, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fe20003f45270 */
/*0670*/ DADD R16, R10, -R16 ; /* 0x000000000a107229 */
/* 0x001e0c0000000810 */
/*0680*/ DMUL R16, R16, R16 ; /* 0x0000001010107228 */
/* 0x001e080000000000 */
/*0690*/ DADD R18, R14, -R18 ; /* 0x000000000e127229 */
/* 0x002fc80000000812 */
/*06a0*/ DFMA R16, R22, R22, R16 ; /* 0x000000161610722b */
/* 0x0010640000000010 */
/*06b0*/ LDC.64 R22, c[0x3][R24+0x48] ; /* 0x00c0120018167b82 */
/* 0x001e280000000a00 */
/*06c0*/ DFMA R18, R18, R18, R16 ; /* 0x000000121212722b */
/* 0x0022880000000010 */
/*06d0*/ LDC.64 R16, c[0x3][R24+0x50] ; /* 0x00c0140018107b82 */
/* 0x002e640000000a00 */
/*06e0*/ DSETP.GEU.AND P3, PT, R20, -R18, PT ; /* 0x800000121400722a */
/* 0x004fc80003f6e000 */
/*06f0*/ DADD R18, -RZ, -R18 ; /* 0x00000000ff127229 */
/* 0x000e880000000912 */
/*0700*/ DADD R22, R12, -R22 ; /* 0x000000000c167229 */
/* 0x001fcc0000000816 */
/*0710*/ FSEL R18, R18, R20, !P3 ; /* 0x0000001412127208 */
/* 0x004fe40005800000 */
/*0720*/ FSEL R19, R19, R21, !P3 ; /* 0x0000001513137208 */
/* 0x000fe40005800000 */
/*0730*/ LDC.64 R20, c[0x3][R24+0x68] ; /* 0x00c01a0018147b82 */
/* 0x000e220000000a00 */
/*0740*/ @!P3 IADD3 R26, R25, 0x1, RZ ; /* 0x00000001191ab810 */
/* 0x000fe20007ffe0ff */
/*0750*/ DADD R16, R10, -R16 ; /* 0x000000000a107229 */
/* 0x002e4c0000000810 */
/*0760*/ DMUL R16, R16, R16 ; /* 0x0000001010107228 */
/* 0x002e4c0000000000 */
/*0770*/ DFMA R16, R22, R22, R16 ; /* 0x000000161610722b */
/* 0x0023e40000000010 */
/*0780*/ LDC.64 R22, c[0x3][R24+0x58] ; /* 0x00c0160018167b82 */
/* 0x002e640000000a00 */
/*0790*/ DADD R20, R10, -R20 ; /* 0x000000000a147229 */
/* 0x001e0c0000000814 */
/*07a0*/ DMUL R20, R20, R20 ; /* 0x0000001414147228 */
/* 0x001fc80000000000 */
/*07b0*/ DADD R22, R14, -R22 ; /* 0x000000000e167229 */
/* 0x002e0c0000000816 */
/*07c0*/ DFMA R16, R22, R22, R16 ; /* 0x000000161610722b */
/* 0x0010480000000010 */
/*07d0*/ LDC.64 R22, c[0x3][R24+0x60] ; /* 0x00c0180018167b82 */
/* 0x001e240000000a00 */
/*07e0*/ DSETP.GEU.AND P4, PT, R18, -R16, PT ; /* 0x800000101200722a */
/* 0x002fc80003f8e000 */
/*07f0*/ DADD R16, -RZ, -R16 ; /* 0x00000000ff107229 */
/* 0x000e540000000910 */
/*0800*/ FSEL R16, R16, R18, !P4 ; /* 0x0000001210107208 */
/* 0x002fe40006000000 */
/*0810*/ FSEL R17, R17, R19, !P4 ; /* 0x0000001311117208 */
/* 0x000fe40006000000 */
/*0820*/ @!P4 IADD3 R26, R25, 0x2, RZ ; /* 0x00000002191ac810 */
/* 0x000fe20007ffe0ff */
/*0830*/ DADD R22, R12, -R22 ; /* 0x000000000c167229 */
/* 0x001e0c0000000816 */
/*0840*/ DFMA R20, R22, R22, R20 ; /* 0x000000161614722b */
/* 0x0011c80000000014 */
/*0850*/ LDC.64 R22, c[0x3][R24+0x70] ; /* 0x00c01c0018167b82 */
/* 0x0010640000000a00 */
/*0860*/ IADD3 R24, R24, 0x60, RZ ; /* 0x0000006018187810 */
/* 0x001fe20007ffe0ff */
/*0870*/ DADD R22, R14, -R22 ; /* 0x000000000e167229 */
/* 0x002e0c0000000816 */
/*0880*/ DFMA R20, R22, R22, R20 ; /* 0x000000161614722b */
/* 0x001e0c0000000014 */
/*0890*/ DSETP.GEU.AND P1, PT, R16, -R20, PT ; /* 0x800000141000722a */
/* 0x001e080003f2e000 */
/*08a0*/ DADD R20, -RZ, -R20 ; /* 0x00000000ff147229 */
/* 0x000e540000000914 */
/*08b0*/ @!P1 IADD3 R26, R25, 0x3, RZ ; /* 0x00000003191a9810 */
/* 0x001fe40007ffe0ff */
/*08c0*/ FSEL R18, R20, R16, !P1 ; /* 0x0000001014127208 */
/* 0x002fe40004800000 */
/*08d0*/ FSEL R19, R21, R17, !P1 ; /* 0x0000001115137208 */
/* 0x000fe40004800000 */
/*08e0*/ IADD3 R25, R25, 0x4, RZ ; /* 0x0000000419197810 */
/* 0x000fe20007ffe0ff */
/*08f0*/ @P2 BRA 0x530 ; /* 0xfffffc3000002947 */
/* 0x000fea000383ffff */
/*0900*/ @!P0 BRA 0xbd0 ; /* 0x000002c000008947 */
/* 0x000fea0003800000 */
/*0910*/ IMAD R7, R25, 0x18, RZ ; /* 0x0000001819077824 */
/* 0x000fe200078e02ff */
/*0920*/ ISETP.NE.AND P1, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fc60003f25270 */
/*0930*/ LDC.64 R16, c[0x3][R7+0x8] ; /* 0x00c0020007107b82 */
/* 0x000e700000000a00 */
/*0940*/ LDC.64 R22, c[0x3][R7] ; /* 0x00c0000007167b82 */
/* 0x000eb00000000a00 */
/*0950*/ LDC.64 R20, c[0x3][R7+0x10] ; /* 0x00c0040007147b82 */
/* 0x000ee20000000a00 */
/*0960*/ DADD R16, R10, -R16 ; /* 0x000000000a107229 */
/* 0x002e4c0000000810 */
/*0970*/ DMUL R16, R16, R16 ; /* 0x0000001010107228 */
/* 0x002fc80000000000 */
/*0980*/ DADD R22, R12, -R22 ; /* 0x000000000c167229 */
/* 0x004e4c0000000816 */
/*0990*/ DFMA R16, R22, R22, R16 ; /* 0x000000161610722b */
/* 0x002fc80000000010 */
/*09a0*/ DADD R20, R14, -R20 ; /* 0x000000000e147229 */
/* 0x008e4c0000000814 */
/*09b0*/ DFMA R20, R20, R20, R16 ; /* 0x000000141414722b */
/* 0x002e4c0000000010 */
/*09c0*/ DADD R16, -RZ, -R20 ; /* 0x00000000ff107229 */
/* 0x002fc80000000914 */
/*09d0*/ DSETP.GEU.AND P0, PT, R18, -R20, PT ; /* 0x800000141200722a */
/* 0x001e0c0003f0e000 */
/*09e0*/ FSEL R16, R16, R18, !P0 ; /* 0x0000001210107208 */
/* 0x001fe40004000000 */
/*09f0*/ FSEL R17, R17, R19, !P0 ; /* 0x0000001311117208 */
/* 0x000fe40004000000 */
/*0a00*/ SEL R26, R25, R26, !P0 ; /* 0x0000001a191a7207 */
/* 0x000fe20004000000 */
/*0a10*/ @!P1 BRA 0xbd0 ; /* 0x000001b000009947 */
/* 0x000fea0003800000 */
/*0a20*/ LDC.64 R18, c[0x3][R7+0x20] ; /* 0x00c0080007127b82 */
/* 0x000e220000000a00 */
/*0a30*/ ISETP.NE.AND P1, PT, R4, 0x2, PT ; /* 0x000000020400780c */
/* 0x000fce0003f25270 */
/*0a40*/ LDC.64 R22, c[0x3][R7+0x18] ; /* 0x00c0060007167b82 */
/* 0x000e700000000a00 */
/*0a50*/ LDC.64 R20, c[0x3][R7+0x28] ; /* 0x00c00a0007147b82 */
/* 0x000ea20000000a00 */
/*0a60*/ DADD R18, R10, -R18 ; /* 0x000000000a127229 */
/* 0x001e0c0000000812 */
/*0a70*/ DMUL R18, R18, R18 ; /* 0x0000001212127228 */
/* 0x001fc80000000000 */
/*0a80*/ DADD R22, R12, -R22 ; /* 0x000000000c167229 */
/* 0x002e0c0000000816 */
/*0a90*/ DFMA R18, R22, R22, R18 ; /* 0x000000161612722b */
/* 0x001fc80000000012 */
/*0aa0*/ DADD R20, R14, -R20 ; /* 0x000000000e147229 */
/* 0x004e0c0000000814 */
/*0ab0*/ DFMA R18, R20, R20, R18 ; /* 0x000000141412722b */
/* 0x001e0c0000000012 */
/*0ac0*/ DSETP.GEU.AND P0, PT, R16, -R18, PT ; /* 0x800000121000722a */
/* 0x001fc80003f0e000 */
/*0ad0*/ DADD R18, -RZ, -R18 ; /* 0x00000000ff127229 */
/* 0x000e140000000912 */
/*0ae0*/ FSEL R16, R18, R16, !P0 ; /* 0x0000001012107208 */
/* 0x001fe40004000000 */
/*0af0*/ FSEL R17, R19, R17, !P0 ; /* 0x0000001113117208 */
/* 0x000fe40004000000 */
/*0b00*/ @!P0 IADD3 R26, R25, 0x1, RZ ; /* 0x00000001191a8810 */
/* 0x000fe20007ffe0ff */
/*0b10*/ @!P1 BRA 0xbd0 ; /* 0x000000b000009947 */
/* 0x000fea0003800000 */
/*0b20*/ LDC.64 R18, c[0x3][R7+0x38] ; /* 0x00c00e0007127b82 */
/* 0x000e300000000a00 */
/*0b30*/ LDC.64 R20, c[0x3][R7+0x30] ; /* 0x00c00c0007147b82 */
/* 0x000e700000000a00 */
/*0b40*/ LDC.64 R22, c[0x3][R7+0x40] ; /* 0x00c0100007167b82 */
/* 0x000ea20000000a00 */
/*0b50*/ DADD R18, R10, -R18 ; /* 0x000000000a127229 */
/* 0x001e0c0000000812 */
/*0b60*/ DMUL R18, R18, R18 ; /* 0x0000001212127228 */
/* 0x001fc80000000000 */
/*0b70*/ DADD R20, R12, -R20 ; /* 0x000000000c147229 */
/* 0x002e080000000814 */
/*0b80*/ DADD R22, R14, -R22 ; /* 0x000000000e167229 */
/* 0x004fc80000000816 */
/*0b90*/ DFMA R18, R20, R20, R18 ; /* 0x000000141412722b */
/* 0x001e0c0000000012 */
/*0ba0*/ DFMA R18, R22, R22, R18 ; /* 0x000000161612722b */
/* 0x001e0c0000000012 */
/*0bb0*/ DSETP.GEU.AND P0, PT, R16, -R18, PT ; /* 0x800000121000722a */
/* 0x001e1c0003f0e000 */
/*0bc0*/ @!P0 IADD3 R26, R25, 0x2, RZ ; /* 0x00000002191a8810 */
/* 0x001fe40007ffe0ff */
/*0bd0*/ IMAD R7, R3, c[0x0][0x170], RZ ; /* 0x00005c0003077a24 */
/* 0x000fe400078e02ff */
/*0be0*/ IMAD.WIDE.U32 R10, R2, c[0x0][0x170], R8 ; /* 0x00005c00020a7a25 */
/* 0x000fc800078e0008 */
/*0bf0*/ IMAD R7, R2, c[0x0][0x174], R7 ; /* 0x00005d0002077a24 */
/* 0x000fe200078e0207 */
/*0c00*/ LEA R12, P0, R10, c[0x0][0x160], 0x2 ; /* 0x000058000a0c7a11 */
/* 0x000fc600078010ff */
/*0c10*/ IMAD.IADD R7, R11, 0x1, R7 ; /* 0x000000010b077824 */
/* 0x000fca00078e0207 */
/*0c20*/ LEA.HI.X R13, R10, c[0x0][0x164], R7, 0x2, P0 ; /* 0x000059000a0d7a11 */
/* 0x000fe400000f1407 */
/*0c30*/ IADD3 R8, P0, R8, UR5, RZ ; /* 0x0000000508087c10 */
/* 0x000fc6000ff1e0ff */
/*0c40*/ STG.E.U8 [R12.64+0x3], R26 ; /* 0x0000031a0c007986 */
/* 0x0003e4000c101106 */
/*0c50*/ IMAD.X R9, RZ, RZ, R9, P0 ; /* 0x000000ffff097224 */
/* 0x000fe200000e0609 */
/*0c60*/ ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x170], PT ; /* 0x00005c0008007a0c */
/* 0x000fc80003f06070 */
/*0c70*/ ISETP.GE.U32.AND.EX P0, PT, R9, c[0x0][0x174], PT, P0 ; /* 0x00005d0009007a0c */
/* 0x000fda0003f06100 */
/*0c80*/ @!P0 BRA 0x390 ; /* 0xfffff70000008947 */
/* 0x002fea000383ffff */
/*0c90*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0ca0*/ IADD3 R2, P0, R2, UR4, RZ ; /* 0x0000000402027c10 */
/* 0x000fca000ff1e0ff */
/*0cb0*/ IMAD.X R3, RZ, RZ, R3, P0 ; /* 0x000000ffff037224 */
/* 0x000fe200000e0603 */
/*0cc0*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fc80003f06070 */
/*0cd0*/ ISETP.GE.U32.AND.EX P0, PT, R3, c[0x0][0x16c], PT, P0 ; /* 0x00005b0003007a0c */
/* 0x000fda0003f06100 */
/*0ce0*/ @!P0 BRA 0x330 ; /* 0xfffff64000008947 */
/* 0x000fea000383ffff */
/*0cf0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d00*/ BRA 0xd00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm
.globl _Z22min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm
.p2align 8
.type _Z22min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm,@function
_Z22min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x8
v_and_b32_e32 v3, 0x3ff, v0
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s17, s6, 0xffff
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[1:2], null, s14, s17, v[3:4]
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_9
s_load_b32 s14, s[4:5], 0xc
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, nc_const@rel32@lo+4
s_addc_u32 s7, s7, nc_const@rel32@hi+12
s_load_b64 s[18:19], s[4:5], 0x0
s_load_b64 s[4:5], s[0:1], 0x10
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, cavg_const@rel32@lo+4
s_addc_u32 s9, s9, cavg_const@rel32@hi+12
s_getpc_b64 s[10:11]
s_add_u32 s10, s10, cavg_const@rel32@lo+12
s_addc_u32 s11, s11, cavg_const@rel32@hi+20
s_load_b32 s16, s[6:7], 0x0
s_getpc_b64 s[12:13]
s_add_u32 s12, s12, cavg_const@rel32@lo+20
s_addc_u32 s13, s13, cavg_const@rel32@hi+28
s_load_b64 s[6:7], s[0:1], 0x0
s_clause 0x2
s_load_b64 s[8:9], s[8:9], 0x0
s_load_b64 s[10:11], s[10:11], 0x0
s_load_b64 s[12:13], s[12:13], 0x0
v_bfe_u32 v0, v0, 10, 10
s_mov_b32 s1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s20, s1
s_mov_b32 s21, s1
s_waitcnt lgkmcnt(0)
s_lshr_b32 s14, s14, 16
s_mul_i32 s17, s18, s17
v_mad_u64_u32 v[3:4], null, s15, s14, v[0:1]
v_mov_b32_e32 v4, 0
s_cmp_gt_i32 s16, 1
s_mul_i32 s19, s19, s14
s_cselect_b32 s18, -1, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u64_e64 s0, s[4:5], v[3:4]
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s22
v_add_co_u32 v1, vcc_lo, v1, s17
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[1:2]
s_or_b32 s21, vcc_lo, s21
s_and_not1_b32 exec_lo, exec_lo, s21
s_cbranch_execz .LBB0_9
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s22, s0
s_cbranch_execz .LBB0_2
v_mul_lo_u32 v0, v2, s4
v_mul_lo_u32 v7, v1, s5
v_mad_u64_u32 v[5:6], null, v1, s4, 0
s_mov_b32 s23, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v6, v6, v7, v0
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v17, vcc_lo, s7, v6, vcc_lo
v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
s_branch .LBB0_6
.LBB0_5:
s_set_inst_prefetch_distance 0x2
v_add_co_u32 v5, vcc_lo, v5, s19
v_add_co_ci_u32_e32 v6, vcc_lo, s20, v6, vcc_lo
global_store_b8 v[7:8], v18, off offset:3
v_cmp_le_u64_e32 vcc_lo, s[4:5], v[5:6]
s_or_b32 s23, vcc_lo, s23
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s23
s_cbranch_execz .LBB0_2
.LBB0_6:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[5:6]
v_mov_b32_e32 v18, 0
v_add_co_u32 v7, vcc_lo, v0, v7
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, v17, v8, vcc_lo
s_and_not1_b32 vcc_lo, exec_lo, s18
s_cbranch_vccnz .LBB0_5
s_clause 0x2
global_load_u8 v9, v[7:8], off offset:1
global_load_u8 v11, v[7:8], off
global_load_u8 v13, v[7:8], off offset:2
s_mov_b32 s24, 1
s_getpc_b64 s[14:15]
s_add_u32 s14, s14, cavg_const@rel32@lo+44
s_addc_u32 s15, s15, cavg_const@rel32@hi+52
s_waitcnt vmcnt(2)
v_cvt_f64_u32_e32 v[9:10], v9
s_waitcnt vmcnt(1)
v_cvt_f64_u32_e32 v[11:12], v11
s_waitcnt vmcnt(0)
v_cvt_f64_u32_e32 v[13:14], v13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[15:16], v[9:10], -s[10:11]
v_add_f64 v[18:19], v[11:12], -s[8:9]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[20:21], v[13:14], -s[12:13]
v_mul_f64 v[15:16], v[15:16], v[15:16]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[15:16], v[18:19], v[18:19], v[15:16]
v_mov_b32_e32 v18, 0
v_fma_f64 v[15:16], v[20:21], v[20:21], v[15:16]
s_delay_alu instid0(VALU_DEP_1)
v_xor_b32_e32 v16, 0x80000000, v16
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_8:
s_add_u32 s26, s14, -16
s_addc_u32 s27, s15, -1
s_add_u32 s28, s14, -8
s_addc_u32 s29, s15, -1
s_clause 0x2
s_load_b64 s[26:27], s[26:27], 0x0
s_load_b64 s[28:29], s[28:29], 0x0
s_load_b64 s[30:31], s[14:15], 0x0
s_waitcnt lgkmcnt(0)
v_add_f64 v[21:22], v[11:12], -s[26:27]
v_add_f64 v[19:20], v[9:10], -s[28:29]
v_add_f64 v[23:24], v[13:14], -s[30:31]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[19:20], v[19:20], v[19:20]
v_fma_f64 v[19:20], v[21:22], v[21:22], v[19:20]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[19:20], v[23:24], v[23:24], v[19:20]
v_cmp_lt_f64_e64 vcc_lo, v[15:16], -v[19:20]
v_xor_b32_e32 v20, 0x80000000, v20
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v18, v18, s24, vcc_lo
s_add_i32 s24, s24, 1
v_dual_cndmask_b32 v16, v16, v20 :: v_dual_cndmask_b32 v15, v15, v19
s_add_u32 s14, s14, 24
s_addc_u32 s15, s15, 0
s_cmp_eq_u32 s16, s24
s_cbranch_scc0 .LBB0_8
s_branch .LBB0_5
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 25
.amdhsa_next_free_sgpr 32
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z22min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm, .Lfunc_end0-_Z22min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected cavg_const
.type cavg_const,@object
.section .bss,"aw",@nobits
.globl cavg_const
.p2align 4, 0x0
cavg_const:
.zero 768
.size cavg_const, 768
.protected nc_const
.type nc_const,@object
.globl nc_const
.p2align 2, 0x0
nc_const:
.long 0
.size nc_const, 4
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym cavg_const
.addrsig_sym nc_const
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm
.private_segment_fixed_size: 0
.sgpr_count: 34
.sgpr_spill_count: 0
.symbol: _Z22min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 25
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d84b5_00000000-6_pgp3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7rgb_subP6uchar4P8double24
.type _Z7rgb_subP6uchar4P8double24, @function
_Z7rgb_subP6uchar4P8double24:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z7rgb_subP6uchar4P8double24, .-_Z7rgb_subP6uchar4P8double24
.globl _Z7rgb_mulP8double24S0_
.type _Z7rgb_mulP8double24S0_, @function
_Z7rgb_mulP8double24S0_:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z7rgb_mulP8double24S0_, .-_Z7rgb_mulP8double24S0_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/Mikhail-Z/MAI/master/sem8/pgp/pgp3/pgp3.cu"
.align 8
.LC1:
.string "ERROR: in file '%s' in line %i: %s.\n"
.text
.globl _Z23copy_from_ram2dev_constP8double24Pi
.type _Z23copy_from_ram2dev_constP8double24Pi, @function
_Z23copy_from_ram2dev_constP8double24Pi:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbp
movq %rsi, %rbx
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL8nc_const(%rip), %rdi
call cudaMemcpyToSymbol@PLT
testl %eax, %eax
jne .L11
movslq (%rbx), %rax
leaq (%rax,%rax,2), %rdx
salq $3, %rdx
movl $1, %r8d
movl $0, %ecx
movq %rbp, %rsi
leaq _ZL10cavg_const(%rip), %rdi
call cudaMemcpyToSymbol@PLT
testl %eax, %eax
jne .L12
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $30, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L12:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $31, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z23copy_from_ram2dev_constP8double24Pi, .-_Z23copy_from_ram2dev_constP8double24Pi
.globl _Z50__device_stub__Z22min_dist_method_kernelP6uchar4mmP6uchar4mm
.type _Z50__device_stub__Z22min_dist_method_kernelP6uchar4mmP6uchar4mm, @function
_Z50__device_stub__Z22min_dist_method_kernelP6uchar4mmP6uchar4mm:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22min_dist_method_kernelP6uchar4mm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z50__device_stub__Z22min_dist_method_kernelP6uchar4mmP6uchar4mm, .-_Z50__device_stub__Z22min_dist_method_kernelP6uchar4mmP6uchar4mm
.globl _Z22min_dist_method_kernelP6uchar4mm
.type _Z22min_dist_method_kernelP6uchar4mm, @function
_Z22min_dist_method_kernelP6uchar4mm:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z22min_dist_method_kernelP6uchar4mmP6uchar4mm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z22min_dist_method_kernelP6uchar4mm, .-_Z22min_dist_method_kernelP6uchar4mm
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "%s"
.LC4:
.string "rb"
.LC5:
.string "%d"
.LC6:
.string "%d %d"
.LC7:
.string "wb"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1384, %rsp
.cfi_def_cfa_offset 1440
movq %fs:40, %rax
movq %rax, 1368(%rsp)
xorl %eax, %eax
leaq 848(%rsp), %rbx
movq %rbx, %rsi
leaq .LC3(%rip), %rbp
movq %rbp, %rdi
call __isoc23_scanf@PLT
leaq 1104(%rsp), %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC4(%rip), %rsi
movq %rbx, %rdi
call fopen@PLT
movq %rax, %rbx
leaq 32(%rsp), %rdi
movq %rax, %r8
movl $1, %ecx
movl $4, %edx
movl $4, %esi
call __fread_chk@PLT
leaq 36(%rsp), %rdi
movq %rbx, %r8
movl $1, %ecx
movl $4, %edx
movl $4, %esi
call __fread_chk@PLT
movslq 36(%rsp), %r12
movslq 32(%rsp), %rax
imulq %rax, %r12
leaq 0(,%r12,4), %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rbx, %r8
movq %r12, %rcx
movl $4, %edx
movq %r13, %rsi
movq %rax, %rdi
call __fread_chk@PLT
movq %rbx, %rdi
call fclose@PLT
leaq 40(%rsp), %rsi
leaq .LC5(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
cmpl $0, 40(%rsp)
jle .L22
leaq 80(%rsp), %r14
movl $0, %r15d
leaq 44(%rsp), %rax
movq %rax, 24(%rsp)
leaq .LC6(%rip), %r13
leaq 68(%rsp), %r12
.L25:
movq 24(%rsp), %rsi
leaq .LC5(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 44(%rsp), %eax
testl %eax, %eax
jle .L33
movq $0x000000000, 16(%rsp)
movq $0x000000000, 8(%rsp)
movq $0x000000000, (%rsp)
movl $0, %ebx
.L24:
leaq 56(%rsp), %rsi
movq %r12, %rdx
movq %r13, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 68(%rsp), %eax
imull 32(%rsp), %eax
addl 56(%rsp), %eax
cltq
leaq 0(%rbp,%rax,4), %rax
movzbl (%rax), %edx
pxor %xmm0, %xmm0
cvtsi2sdl %edx, %xmm0
addsd (%rsp), %xmm0
movsd %xmm0, (%rsp)
movzbl 1(%rax), %edx
pxor %xmm0, %xmm0
cvtsi2sdl %edx, %xmm0
addsd 8(%rsp), %xmm0
movsd %xmm0, 8(%rsp)
movzbl 2(%rax), %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
addsd 16(%rsp), %xmm0
movsd %xmm0, 16(%rsp)
addl $1, %ebx
movl 44(%rsp), %eax
cmpl %ebx, %eax
jg .L24
.L23:
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
movsd (%rsp), %xmm0
divsd %xmm1, %xmm0
movsd %xmm0, (%r14)
movsd 8(%rsp), %xmm0
divsd %xmm1, %xmm0
movsd %xmm0, 8(%r14)
movsd 16(%rsp), %xmm0
divsd %xmm1, %xmm0
movsd %xmm0, 16(%r14)
addl $1, %r15d
addq $24, %r14
cmpl %r15d, 40(%rsp)
jg .L25
.L22:
leaq 40(%rsp), %rsi
leaq 80(%rsp), %rdi
call _Z23copy_from_ram2dev_constP8double24Pi
movslq 32(%rsp), %rsi
movslq 36(%rsp), %rax
imulq %rax, %rsi
salq $2, %rsi
leaq 48(%rsp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L37
movslq 32(%rsp), %rdx
movslq 36(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $1, %ecx
movq %rbp, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L38
movl $16, 68(%rsp)
movl $16, 72(%rsp)
movl $1, 76(%rsp)
movl $16, 56(%rsp)
movl $16, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L28:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L40
movslq 32(%rsp), %rdx
movslq 36(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $2, %ecx
movq 48(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L41
movq 48(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L42
leaq 1104(%rsp), %rdi
leaq .LC7(%rip), %rsi
call fopen@PLT
movq %rax, %rbx
leaq 32(%rsp), %rdi
movq %rax, %rcx
movl $1, %edx
movl $4, %esi
call fwrite@PLT
leaq 36(%rsp), %rdi
movq %rbx, %rcx
movl $1, %edx
movl $4, %esi
call fwrite@PLT
movl 32(%rsp), %edx
imull 36(%rsp), %edx
movslq %edx, %rdx
movq %rbx, %rcx
movl $4, %esi
movq %rbp, %rdi
call fwrite@PLT
movq %rbx, %rdi
call fclose@PLT
movq %rbp, %rdi
call free@PLT
movq 1368(%rsp), %rax
subq %fs:40, %rax
jne .L43
movl $0, %eax
addq $1384, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
movq $0x000000000, 16(%rsp)
movq $0x000000000, 8(%rsp)
movq $0x000000000, (%rsp)
jmp .L23
.L37:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $97, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L38:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $98, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L39:
movslq 36(%rsp), %rdx
movslq 32(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z50__device_stub__Z22min_dist_method_kernelP6uchar4mmP6uchar4mm
jmp .L28
.L40:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $100, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L41:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $101, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L42:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $102, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L43:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC8:
.string "_Z22min_dist_method_kernelP6uchar4mm"
.section .rodata.str1.1
.LC9:
.string "cavg_const"
.LC10:
.string "nc_const"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z22min_dist_method_kernelP6uchar4mm(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $768, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10cavg_const(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8nc_const(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL8nc_const
.comm _ZL8nc_const,4,4
.local _ZL10cavg_const
.comm _ZL10cavg_const,768,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "pgp3.hip"
.globl _Z23copy_from_ram2dev_constP8double24Pi # -- Begin function _Z23copy_from_ram2dev_constP8double24Pi
.p2align 4, 0x90
.type _Z23copy_from_ram2dev_constP8double24Pi,@function
_Z23copy_from_ram2dev_constP8double24Pi: # @_Z23copy_from_ram2dev_constP8double24Pi
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %r14
movq %rdi, %rbx
movl $nc_const, %edi
movl $4, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
testl %eax, %eax
jne .LBB0_1
# %bb.3:
movslq (%r14), %rax
shlq $3, %rax
leaq (%rax,%rax,2), %rdx
movl $cavg_const, %edi
movq %rbx, %rsi
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
testl %eax, %eax
jne .LBB0_4
# %bb.5:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_1:
.cfi_def_cfa_offset 32
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movq %rbx, %rdi
movl $32, %ecx
jmp .LBB0_2
.LBB0_4:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movq %rbx, %rdi
movl $33, %ecx
.LBB0_2:
movq %rax, %r8
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z23copy_from_ram2dev_constP8double24Pi, .Lfunc_end0-_Z23copy_from_ram2dev_constP8double24Pi
.cfi_endproc
# -- End function
.globl _Z37__device_stub__min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm # -- Begin function _Z37__device_stub__min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm
.p2align 4, 0x90
.type _Z37__device_stub__min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm,@function
_Z37__device_stub__min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm: # @_Z37__device_stub__min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z37__device_stub__min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm, .Lfunc_end1-_Z37__device_stub__min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1464, %rsp # imm = 0x5B8
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 1200(%rsp), %rbx
movl $.L.str.2, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
leaq 176(%rsp), %rsi
movl $.L.str.2, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.L.str.3, %esi
movq %rbx, %rdi
callq fopen
movq %rax, %r15
leaq 16(%rsp), %rdi
movl $4, %esi
movl $1, %edx
movq %rax, %rcx
callq fread
leaq 12(%rsp), %rdi
movl $4, %esi
movl $1, %edx
movq %r15, %rcx
callq fread
movslq 12(%rsp), %rax
movslq 16(%rsp), %r12
movq %r12, %r13
movq %rax, 80(%rsp) # 8-byte Spill
imulq %rax, %r13
leaq (,%r13,4), %rdi
movq %rdi, 88(%rsp) # 8-byte Spill
callq malloc
movq %rax, %rbx
movl $4, %esi
movq %rax, %rdi
movq %r13, %rdx
movq %r15, %rcx
callq fread
movq %r15, %rdi
callq fclose
leaq 8(%rsp), %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
callq __isoc23_scanf
cmpl $0, 8(%rsp)
jle .LBB2_5
# %bb.1: # %.lr.ph63.preheader
leaq 48(%rsp), %rbp
leaq 32(%rsp), %r13
xorl %r14d, %r14d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_3: # in Loop: Header=BB2_2 Depth=1
xorpd %xmm1, %xmm1
xorpd %xmm2, %xmm2
xorpd %xmm3, %xmm3
.LBB2_4: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd %xmm0, %xmm3
leaq (%r14,%r14,2), %rax
movsd %xmm3, 432(%rsp,%rax,8)
divsd %xmm0, %xmm2
movsd %xmm2, 440(%rsp,%rax,8)
divsd %xmm0, %xmm1
movsd %xmm1, 448(%rsp,%rax,8)
incq %r14
movslq 8(%rsp), %rax
cmpq %rax, %r14
jge .LBB2_5
.LBB2_2: # %.lr.ph63
# =>This Loop Header: Depth=1
# Child Loop BB2_9 Depth 2
movl $.L.str.4, %edi
leaq 20(%rsp), %rsi
xorl %eax, %eax
callq __isoc23_scanf
movl 20(%rsp), %eax
testl %eax, %eax
jle .LBB2_3
# %bb.8: # %.lr.ph.preheader
# in Loop: Header=BB2_2 Depth=1
xorl %r15d, %r15d
xorps %xmm3, %xmm3
xorps %xmm2, %xmm2
xorps %xmm1, %xmm1
.p2align 4, 0x90
.LBB2_9: # %.lr.ph
# Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movsd %xmm3, 96(%rsp) # 8-byte Spill
movsd %xmm2, 104(%rsp) # 8-byte Spill
movsd %xmm1, 112(%rsp) # 8-byte Spill
movl $.L.str.5, %edi
movq %rbp, %rsi
movq %r13, %rdx
xorl %eax, %eax
callq __isoc23_scanf
movsd 96(%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
movsd 104(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
movsd 112(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
movslq 32(%rsp), %rax
imulq %r12, %rax
movslq 48(%rsp), %rcx
addq %rax, %rcx
movzbl (%rbx,%rcx,4), %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
addsd %xmm0, %xmm3
movzbl 1(%rbx,%rcx,4), %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
addsd %xmm0, %xmm2
movzbl 2(%rbx,%rcx,4), %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
addsd %xmm0, %xmm1
incl %r15d
movl 20(%rsp), %eax
cmpl %eax, %r15d
jl .LBB2_9
jmp .LBB2_4
.LBB2_5: # %._crit_edge64
leaq 432(%rsp), %rdi
leaq 8(%rsp), %rsi
callq _Z23copy_from_ram2dev_constP8double24Pi
leaq 24(%rsp), %rdi
movq 88(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_6
# %bb.10:
movq 24(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_11
# %bb.12:
movabsq $68719476752, %rdi # imm = 0x1000000010
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_14
# %bb.13:
movq 24(%rsp), %rax
movq %rax, 168(%rsp)
movq %r12, 160(%rsp)
movq 80(%rsp), %rax # 8-byte Reload
movq %rax, 152(%rsp)
leaq 168(%rsp), %rax
movq %rax, 48(%rsp)
leaq 160(%rsp), %rax
movq %rax, 56(%rsp)
leaq 152(%rsp), %rax
movq %rax, 64(%rsp)
leaq 32(%rsp), %rdi
leaq 136(%rsp), %rsi
leaq 128(%rsp), %rdx
leaq 120(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 136(%rsp), %rcx
movl 144(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z22min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm, %edi
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_14:
callq hipGetLastError
testl %eax, %eax
jne .LBB2_15
# %bb.16:
movq 24(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_17
# %bb.18:
movq 24(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_19
# %bb.20:
leaq 176(%rsp), %rdi
movl $.L.str.6, %esi
callq fopen
movq %rax, %r14
leaq 16(%rsp), %rdi
movl $4, %esi
movl $1, %edx
movq %rax, %rcx
callq fwrite
leaq 12(%rsp), %rdi
movl $4, %esi
movl $1, %edx
movq %r14, %rcx
callq fwrite
movslq 16(%rsp), %rax
movslq 12(%rsp), %rdx
imulq %rax, %rdx
movl $4, %esi
movq %rbx, %rdi
movq %r14, %rcx
callq fwrite
movq %r14, %rdi
callq fclose
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $1464, %rsp # imm = 0x5B8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_6:
.cfi_def_cfa_offset 1520
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movq %rbx, %rdi
movl $99, %ecx
jmp .LBB2_7
.LBB2_11:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movq %rbx, %rdi
movl $100, %ecx
jmp .LBB2_7
.LBB2_15:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movq %rbx, %rdi
movl $102, %ecx
jmp .LBB2_7
.LBB2_17:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movq %rbx, %rdi
movl $103, %ecx
jmp .LBB2_7
.LBB2_19:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movq %rbx, %rdi
movl $104, %ecx
.LBB2_7:
movq %rax, %r8
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $cavg_const, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $768, %r9d # imm = 0x300
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $nc_const, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type cavg_const,@object # @cavg_const
.local cavg_const
.comm cavg_const,768,16
.type nc_const,@object # @nc_const
.local nc_const
.comm nc_const,4,4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "ERROR: in file '%s' in line %i: %s.\n"
.size .L.str, 37
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/Mikhail-Z/MAI/master/sem8/pgp/pgp3/pgp3.hip"
.size .L.str.1, 101
.type _Z22min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm,@object # @_Z22min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm
.section .rodata,"a",@progbits
.globl _Z22min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm
.p2align 3, 0x0
_Z22min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm:
.quad _Z37__device_stub__min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm
.size _Z22min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "%s"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "rb"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d"
.size .L.str.4, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d %d"
.size .L.str.5, 6
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "wb"
.size .L.str.6, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z22min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm"
.size .L__unnamed_1, 54
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "cavg_const"
.size .L__unnamed_2, 11
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "nc_const"
.size .L__unnamed_3, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym cavg_const
.addrsig_sym nc_const
.addrsig_sym _Z22min_dist_method_kernelP15HIP_vector_typeIhLj4EEmm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #ifdef D_CUDA
#include "ParticleKernel.cuh"
#include "Dot/Core.h"
#include <GL/glew.h>
#include <cuda_gl_interop.h>
#include <iostream>
namespace Dot {
__global__ void _Init(float3* pos, float3* vel, int count,curandState * state)
{
int id = blockDim.x * blockIdx.x + threadIdx.x;
if (id < count)
{
pos[id] = make_float3(0, 0, 0);
curand_init(1234, id, 0, &state[id]);
float rand = curand_uniform(&(state[id]));
vel[id].x = rand/5;
float rand1 = curand_uniform(&(state[id]));
vel[id].y = -rand1/5;
float rand2 = curand_uniform(&(state[id]));
vel[id].z = rand2/5;
}
}
__global__ void _UpdateKernel(float3* pos, float3* vel, int count,float dt)
{
int id = blockDim.x * blockIdx.x + threadIdx.x;
if (id < count)
{
pos[id].x += vel[id].x * dt;
pos[id].y += vel[id].y * dt;
pos[id].z += vel[id].z * dt;
if (abs(pos[id].x) >= 30 || abs(pos[id].y) >= 30 || abs(pos[id].z) >= 30)
{
pos[id].x = 0;
pos[id].y = 0;
pos[id].z = 0;
}
}
}
DefaultParticleEffect::DefaultParticleEffect(unsigned int count)
: m_count(count), m_positions(NULL), m_velocities(NULL)
{
CudaErrChk(cudaMallocManaged(&m_positions, sizeof(float3) * m_count));
CudaErrChk(cudaMallocManaged(&m_velocities, sizeof(float3) * m_count));
curandState* d_state;
CudaErrChk(cudaMalloc(&d_state, sizeof(curandState)));
_Init << <m_count / 256 + 1,256 >> > (m_positions, m_velocities, m_count,d_state);
CudaErrChk(cudaDeviceSynchronize());
CudaErrChk(cudaFree(d_state));
}
DefaultParticleEffect::~DefaultParticleEffect()
{
CudaErrChk(cudaDeviceSynchronize());
CudaErrChk(cudaFree(m_positions));
CudaErrChk(cudaFree(m_velocities));
cudaDeviceReset();
}
void DefaultParticleEffect::Launch(float dt)
{
_UpdateKernel << <m_count / 256 + 1, 256 >> > (m_positions, m_velocities, m_count, dt);
CudaErrChk(cudaDeviceSynchronize());
}
__global__ void _TestInit(float3* pos,float3* vel, int count, curandState* state)
{
int id = blockDim.x * blockIdx.x + threadIdx.x;
if (id < count)
{
curand_init(1234, id, 0, &state[id]);
pos[id] = make_float3(0,0,0);
float rand = curand_uniform(&(state[id]));
vel[id].x = rand / 5;
float rand1 = curand_uniform(&(state[id]));
vel[id].y = -rand1 / 5;
float rand2 = curand_uniform(&(state[id]));
vel[id].z = rand2 / 5;
}
}
__global__ void _TestUpdateKernel(float3* pos, float3* vel, int count, float dt)
{
int id = blockDim.x * blockIdx.x + threadIdx.x;
if (id < count)
{
pos[id].x += vel[id].x * dt;
pos[id].y += vel[id].y * dt;
pos[id].z += vel[id].z * dt;
}
}
TestParticleEffect::TestParticleEffect(unsigned int count)
: m_count(count)
{
glGenVertexArrays(1, &m_VAO);
glBindVertexArray(m_VAO);
glGenBuffers(1, &m_VBO);
glBindBuffer(GL_ARRAY_BUFFER, m_VBO);
glBufferData(GL_ARRAY_BUFFER, count * sizeof(float3), NULL, GL_DYNAMIC_DRAW);
glEnableVertexAttribArray(0);
glVertexAttribPointer(0, 3, GL_FLOAT, GL_FALSE, 0, 0);
glVertexAttribDivisor(0, 1);
glBindBuffer(GL_ARRAY_BUFFER, 0);
CudaErrChk(cudaGLRegisterBufferObject(m_VBO));
curandState* d_state;
cudaMalloc(&m_velocities, m_count * sizeof(float3));
CudaErrChk(cudaMalloc(&d_state, sizeof(curandState)));
CudaErrChk(cudaMalloc(&m_positions, m_count * sizeof(float3)));
CudaErrChk(cudaGLMapBufferObject((void**)& m_positions, m_VBO));
_TestInit << <m_count / 256 + 1, 256 >> > (m_positions,m_velocities, m_count,d_state);
CudaErrChk(cudaGLUnmapBufferObject(m_VBO));
cudaFree(d_state);
glBindVertexArray(0);
cudaDeviceSynchronize();
}
TestParticleEffect::~TestParticleEffect()
{
CudaErrChk(cudaDeviceSynchronize());
CudaErrChk(cudaGLUnregisterBufferObject(m_VBO));
CudaErrChk(cudaFree(m_positions));
CudaErrChk(cudaFree(m_velocities));
glDeleteBuffers(1, &m_VBO);
glDeleteBuffers(1, &m_VAO);
}
void TestParticleEffect::Render(float dt)
{
cudaDeviceSynchronize();
CudaErrChk(cudaGLMapBufferObject((void**)& m_positions, m_VBO));
_TestUpdateKernel << <m_count/256+1, 256 >> > (m_positions,m_velocities, m_count, dt);
CudaErrChk(cudaGLUnmapBufferObject(m_VBO));
cudaDeviceSynchronize();
glBindVertexArray(m_VAO);
glDrawArraysInstanced(GL_POINTS, 0,1,m_count);
glBindVertexArray(0);
}
void TestParticleEffect::Launch(float dt)
{
}
}
#endif | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #ifdef D_CUDA
#include "ParticleKernel.cuh"
#include "Dot/Core.h"
#include <GL/glew.h>
#include <cuda_gl_interop.h>
#include <iostream>
namespace Dot {
__global__ void _Init(float3* pos, float3* vel, int count,curandState * state)
{
int id = blockDim.x * blockIdx.x + threadIdx.x;
if (id < count)
{
pos[id] = make_float3(0, 0, 0);
curand_init(1234, id, 0, &state[id]);
float rand = curand_uniform(&(state[id]));
vel[id].x = rand/5;
float rand1 = curand_uniform(&(state[id]));
vel[id].y = -rand1/5;
float rand2 = curand_uniform(&(state[id]));
vel[id].z = rand2/5;
}
}
__global__ void _UpdateKernel(float3* pos, float3* vel, int count,float dt)
{
int id = blockDim.x * blockIdx.x + threadIdx.x;
if (id < count)
{
pos[id].x += vel[id].x * dt;
pos[id].y += vel[id].y * dt;
pos[id].z += vel[id].z * dt;
if (abs(pos[id].x) >= 30 || abs(pos[id].y) >= 30 || abs(pos[id].z) >= 30)
{
pos[id].x = 0;
pos[id].y = 0;
pos[id].z = 0;
}
}
}
DefaultParticleEffect::DefaultParticleEffect(unsigned int count)
: m_count(count), m_positions(NULL), m_velocities(NULL)
{
CudaErrChk(cudaMallocManaged(&m_positions, sizeof(float3) * m_count));
CudaErrChk(cudaMallocManaged(&m_velocities, sizeof(float3) * m_count));
curandState* d_state;
CudaErrChk(cudaMalloc(&d_state, sizeof(curandState)));
_Init << <m_count / 256 + 1,256 >> > (m_positions, m_velocities, m_count,d_state);
CudaErrChk(cudaDeviceSynchronize());
CudaErrChk(cudaFree(d_state));
}
DefaultParticleEffect::~DefaultParticleEffect()
{
CudaErrChk(cudaDeviceSynchronize());
CudaErrChk(cudaFree(m_positions));
CudaErrChk(cudaFree(m_velocities));
cudaDeviceReset();
}
void DefaultParticleEffect::Launch(float dt)
{
_UpdateKernel << <m_count / 256 + 1, 256 >> > (m_positions, m_velocities, m_count, dt);
CudaErrChk(cudaDeviceSynchronize());
}
__global__ void _TestInit(float3* pos,float3* vel, int count, curandState* state)
{
int id = blockDim.x * blockIdx.x + threadIdx.x;
if (id < count)
{
curand_init(1234, id, 0, &state[id]);
pos[id] = make_float3(0,0,0);
float rand = curand_uniform(&(state[id]));
vel[id].x = rand / 5;
float rand1 = curand_uniform(&(state[id]));
vel[id].y = -rand1 / 5;
float rand2 = curand_uniform(&(state[id]));
vel[id].z = rand2 / 5;
}
}
__global__ void _TestUpdateKernel(float3* pos, float3* vel, int count, float dt)
{
int id = blockDim.x * blockIdx.x + threadIdx.x;
if (id < count)
{
pos[id].x += vel[id].x * dt;
pos[id].y += vel[id].y * dt;
pos[id].z += vel[id].z * dt;
}
}
TestParticleEffect::TestParticleEffect(unsigned int count)
: m_count(count)
{
glGenVertexArrays(1, &m_VAO);
glBindVertexArray(m_VAO);
glGenBuffers(1, &m_VBO);
glBindBuffer(GL_ARRAY_BUFFER, m_VBO);
glBufferData(GL_ARRAY_BUFFER, count * sizeof(float3), NULL, GL_DYNAMIC_DRAW);
glEnableVertexAttribArray(0);
glVertexAttribPointer(0, 3, GL_FLOAT, GL_FALSE, 0, 0);
glVertexAttribDivisor(0, 1);
glBindBuffer(GL_ARRAY_BUFFER, 0);
CudaErrChk(cudaGLRegisterBufferObject(m_VBO));
curandState* d_state;
cudaMalloc(&m_velocities, m_count * sizeof(float3));
CudaErrChk(cudaMalloc(&d_state, sizeof(curandState)));
CudaErrChk(cudaMalloc(&m_positions, m_count * sizeof(float3)));
CudaErrChk(cudaGLMapBufferObject((void**)& m_positions, m_VBO));
_TestInit << <m_count / 256 + 1, 256 >> > (m_positions,m_velocities, m_count,d_state);
CudaErrChk(cudaGLUnmapBufferObject(m_VBO));
cudaFree(d_state);
glBindVertexArray(0);
cudaDeviceSynchronize();
}
TestParticleEffect::~TestParticleEffect()
{
CudaErrChk(cudaDeviceSynchronize());
CudaErrChk(cudaGLUnregisterBufferObject(m_VBO));
CudaErrChk(cudaFree(m_positions));
CudaErrChk(cudaFree(m_velocities));
glDeleteBuffers(1, &m_VBO);
glDeleteBuffers(1, &m_VAO);
}
void TestParticleEffect::Render(float dt)
{
cudaDeviceSynchronize();
CudaErrChk(cudaGLMapBufferObject((void**)& m_positions, m_VBO));
_TestUpdateKernel << <m_count/256+1, 256 >> > (m_positions,m_velocities, m_count, dt);
CudaErrChk(cudaGLUnmapBufferObject(m_VBO));
cudaDeviceSynchronize();
glBindVertexArray(m_VAO);
glDrawArraysInstanced(GL_POINTS, 0,1,m_count);
glBindVertexArray(0);
}
void TestParticleEffect::Launch(float dt)
{
}
}
#endif | .file "tmpxft_0001b981_00000000-6_ParticleKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #ifdef D_CUDA
#include "ParticleKernel.cuh"
#include "Dot/Core.h"
#include <GL/glew.h>
#include <cuda_gl_interop.h>
#include <iostream>
namespace Dot {
__global__ void _Init(float3* pos, float3* vel, int count,curandState * state)
{
int id = blockDim.x * blockIdx.x + threadIdx.x;
if (id < count)
{
pos[id] = make_float3(0, 0, 0);
curand_init(1234, id, 0, &state[id]);
float rand = curand_uniform(&(state[id]));
vel[id].x = rand/5;
float rand1 = curand_uniform(&(state[id]));
vel[id].y = -rand1/5;
float rand2 = curand_uniform(&(state[id]));
vel[id].z = rand2/5;
}
}
__global__ void _UpdateKernel(float3* pos, float3* vel, int count,float dt)
{
int id = blockDim.x * blockIdx.x + threadIdx.x;
if (id < count)
{
pos[id].x += vel[id].x * dt;
pos[id].y += vel[id].y * dt;
pos[id].z += vel[id].z * dt;
if (abs(pos[id].x) >= 30 || abs(pos[id].y) >= 30 || abs(pos[id].z) >= 30)
{
pos[id].x = 0;
pos[id].y = 0;
pos[id].z = 0;
}
}
}
DefaultParticleEffect::DefaultParticleEffect(unsigned int count)
: m_count(count), m_positions(NULL), m_velocities(NULL)
{
CudaErrChk(cudaMallocManaged(&m_positions, sizeof(float3) * m_count));
CudaErrChk(cudaMallocManaged(&m_velocities, sizeof(float3) * m_count));
curandState* d_state;
CudaErrChk(cudaMalloc(&d_state, sizeof(curandState)));
_Init << <m_count / 256 + 1,256 >> > (m_positions, m_velocities, m_count,d_state);
CudaErrChk(cudaDeviceSynchronize());
CudaErrChk(cudaFree(d_state));
}
DefaultParticleEffect::~DefaultParticleEffect()
{
CudaErrChk(cudaDeviceSynchronize());
CudaErrChk(cudaFree(m_positions));
CudaErrChk(cudaFree(m_velocities));
cudaDeviceReset();
}
void DefaultParticleEffect::Launch(float dt)
{
_UpdateKernel << <m_count / 256 + 1, 256 >> > (m_positions, m_velocities, m_count, dt);
CudaErrChk(cudaDeviceSynchronize());
}
__global__ void _TestInit(float3* pos,float3* vel, int count, curandState* state)
{
int id = blockDim.x * blockIdx.x + threadIdx.x;
if (id < count)
{
curand_init(1234, id, 0, &state[id]);
pos[id] = make_float3(0,0,0);
float rand = curand_uniform(&(state[id]));
vel[id].x = rand / 5;
float rand1 = curand_uniform(&(state[id]));
vel[id].y = -rand1 / 5;
float rand2 = curand_uniform(&(state[id]));
vel[id].z = rand2 / 5;
}
}
__global__ void _TestUpdateKernel(float3* pos, float3* vel, int count, float dt)
{
int id = blockDim.x * blockIdx.x + threadIdx.x;
if (id < count)
{
pos[id].x += vel[id].x * dt;
pos[id].y += vel[id].y * dt;
pos[id].z += vel[id].z * dt;
}
}
TestParticleEffect::TestParticleEffect(unsigned int count)
: m_count(count)
{
glGenVertexArrays(1, &m_VAO);
glBindVertexArray(m_VAO);
glGenBuffers(1, &m_VBO);
glBindBuffer(GL_ARRAY_BUFFER, m_VBO);
glBufferData(GL_ARRAY_BUFFER, count * sizeof(float3), NULL, GL_DYNAMIC_DRAW);
glEnableVertexAttribArray(0);
glVertexAttribPointer(0, 3, GL_FLOAT, GL_FALSE, 0, 0);
glVertexAttribDivisor(0, 1);
glBindBuffer(GL_ARRAY_BUFFER, 0);
CudaErrChk(cudaGLRegisterBufferObject(m_VBO));
curandState* d_state;
cudaMalloc(&m_velocities, m_count * sizeof(float3));
CudaErrChk(cudaMalloc(&d_state, sizeof(curandState)));
CudaErrChk(cudaMalloc(&m_positions, m_count * sizeof(float3)));
CudaErrChk(cudaGLMapBufferObject((void**)& m_positions, m_VBO));
_TestInit << <m_count / 256 + 1, 256 >> > (m_positions,m_velocities, m_count,d_state);
CudaErrChk(cudaGLUnmapBufferObject(m_VBO));
cudaFree(d_state);
glBindVertexArray(0);
cudaDeviceSynchronize();
}
TestParticleEffect::~TestParticleEffect()
{
CudaErrChk(cudaDeviceSynchronize());
CudaErrChk(cudaGLUnregisterBufferObject(m_VBO));
CudaErrChk(cudaFree(m_positions));
CudaErrChk(cudaFree(m_velocities));
glDeleteBuffers(1, &m_VBO);
glDeleteBuffers(1, &m_VAO);
}
void TestParticleEffect::Render(float dt)
{
cudaDeviceSynchronize();
CudaErrChk(cudaGLMapBufferObject((void**)& m_positions, m_VBO));
_TestUpdateKernel << <m_count/256+1, 256 >> > (m_positions,m_velocities, m_count, dt);
CudaErrChk(cudaGLUnmapBufferObject(m_VBO));
cudaDeviceSynchronize();
glBindVertexArray(m_VAO);
glDrawArraysInstanced(GL_POINTS, 0,1,m_count);
glBindVertexArray(0);
}
void TestParticleEffect::Launch(float dt)
{
}
}
#endif | #pragma once
#ifdef D_CUDA
#include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
namespace Dot {
class ParticleEffect
{
public:
ParticleEffect() {}
ParticleEffect(unsigned int count) {};
virtual ~ParticleEffect() = default;
virtual void Launch(float dt) = 0;
};
class DefaultParticleEffect : public ParticleEffect
{
public:
DefaultParticleEffect(unsigned int count);
virtual ~DefaultParticleEffect();
virtual void Launch(float dt) override;
public:
unsigned int m_count;
float3* m_positions;
float3* m_velocities;
};
class TestParticleEffect
{
public:
TestParticleEffect(unsigned int count);
~TestParticleEffect();
void Render(float dt);
void Launch(float dt);
private:
unsigned int m_VAO;
unsigned int m_VBO;
unsigned int m_count;
void* d_vbo_buffer = NULL;
float3* m_positions;
float3* m_velocities;
};
}
#endif |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #pragma once
#ifdef D_CUDA
#include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
namespace Dot {
class ParticleEffect
{
public:
ParticleEffect() {}
ParticleEffect(unsigned int count) {};
virtual ~ParticleEffect() = default;
virtual void Launch(float dt) = 0;
};
class DefaultParticleEffect : public ParticleEffect
{
public:
DefaultParticleEffect(unsigned int count);
virtual ~DefaultParticleEffect();
virtual void Launch(float dt) override;
public:
unsigned int m_count;
float3* m_positions;
float3* m_velocities;
};
class TestParticleEffect
{
public:
TestParticleEffect(unsigned int count);
~TestParticleEffect();
void Render(float dt);
void Launch(float dt);
private:
unsigned int m_VAO;
unsigned int m_VBO;
unsigned int m_count;
void* d_vbo_buffer = NULL;
float3* m_positions;
float3* m_velocities;
};
}
#endif | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #pragma once
#ifdef D_CUDA
#include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
namespace Dot {
class ParticleEffect
{
public:
ParticleEffect() {}
ParticleEffect(unsigned int count) {};
virtual ~ParticleEffect() = default;
virtual void Launch(float dt) = 0;
};
class DefaultParticleEffect : public ParticleEffect
{
public:
DefaultParticleEffect(unsigned int count);
virtual ~DefaultParticleEffect();
virtual void Launch(float dt) override;
public:
unsigned int m_count;
float3* m_positions;
float3* m_velocities;
};
class TestParticleEffect
{
public:
TestParticleEffect(unsigned int count);
~TestParticleEffect();
void Render(float dt);
void Launch(float dt);
private:
unsigned int m_VAO;
unsigned int m_VBO;
unsigned int m_count;
void* d_vbo_buffer = NULL;
float3* m_positions;
float3* m_velocities;
};
}
#endif | .text
.file "ParticleKernel.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001b981_00000000-6_ParticleKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ParticleKernel.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0000aadf_00000000-6_aobench.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2041:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2041:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z12lambda_71814PmPhPmPh
.type _Z34__device_stub__Z12lambda_71814PmPhPmPh, @function
_Z34__device_stub__Z12lambda_71814PmPhPmPh:
.LFB2063:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq lambda_71814(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size _Z34__device_stub__Z12lambda_71814PmPhPmPh, .-_Z34__device_stub__Z12lambda_71814PmPhPmPh
.globl lambda_71814
.type lambda_71814, @function
lambda_71814:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z12lambda_71814PmPhPmPh
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size lambda_71814, .-lambda_71814
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "lambda_71814"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq lambda_71814(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "aobench.hip"
.globl __device_stub__lambda_71814 # -- Begin function __device_stub__lambda_71814
.p2align 4, 0x90
.type __device_stub__lambda_71814,@function
__device_stub__lambda_71814: # @__device_stub__lambda_71814
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $lambda_71814, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size __device_stub__lambda_71814, .Lfunc_end0-__device_stub__lambda_71814
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $lambda_71814, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type lambda_71814,@object # @lambda_71814
.section .rodata,"a",@progbits
.globl lambda_71814
.p2align 3, 0x0
lambda_71814:
.quad __device_stub__lambda_71814
.size lambda_71814, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "lambda_71814"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__lambda_71814
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym lambda_71814
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <math.h>
#ifndef ARRAY_SIZE
#define ARRAY_SIZE 256
#endif // !ARRAY_SIZE
#define ARRAY_SIZE_IN_BYTES (sizeof(unsigned int) * (ARRAY_SIZE))
#ifndef BLOCK_SIZE
#define BLOCK_SIZE 16
#endif // !BLOCK_SIZE
/* Declare statically two arrays of ARRAY_SIZE each */
unsigned int cpu_block[ARRAY_SIZE];
unsigned int cpu_thread[ARRAY_SIZE];
__global__
void what_is_my_id(unsigned int* block, unsigned int* thread)
{
const unsigned int thread_idx = (blockIdx.x * blockDim.x) + threadIdx.x;
block[thread_idx] = blockIdx.x;
thread[thread_idx] = threadIdx.x;
}
void main_sub0()
{
/* Declare pointers for GPU based params */
unsigned int* gpu_block;
unsigned int* gpu_thread;
cudaMalloc((void**)&gpu_block, ARRAY_SIZE_IN_BYTES);
cudaMalloc((void**)&gpu_thread, ARRAY_SIZE_IN_BYTES);
cudaMemcpy(cpu_block, gpu_block, ARRAY_SIZE_IN_BYTES, cudaMemcpyHostToDevice);
cudaMemcpy(cpu_thread, gpu_thread, ARRAY_SIZE_IN_BYTES, cudaMemcpyHostToDevice);
const unsigned int threads_per_block = BLOCK_SIZE;
const unsigned int num_blocks = ceil((double) ARRAY_SIZE / threads_per_block);
/* Execute our kernel */
what_is_my_id<<<num_blocks, threads_per_block>>>(gpu_block, gpu_thread);
/* Free the arrays on the GPU as now we're done with them */
cudaMemcpy(cpu_block, gpu_block, ARRAY_SIZE_IN_BYTES, cudaMemcpyDeviceToHost);
cudaMemcpy(cpu_thread, gpu_thread, ARRAY_SIZE_IN_BYTES, cudaMemcpyDeviceToHost);
cudaFree(gpu_block);
cudaFree(gpu_thread);
/* Iterate through the arrays and print */
for (unsigned int i = 0; i < ARRAY_SIZE; i++)
{
printf("i: %4u, Thread: %2u - Block: %2u\n", i, cpu_thread[i], cpu_block[i]);
}
}
int main()
{
main_sub0();
return EXIT_SUCCESS;
} | code for sm_80
Function : _Z13what_is_my_idPjS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R7, c[0x0][0x0], R0 ; /* 0x0000000007047a24 */
/* 0x001fca00078e0200 */
/*0060*/ IMAD.WIDE.U32 R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fc800078e0005 */
/*0070*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe200078e0005 */
/*0080*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101904 */
/*0090*/ STG.E [R4.64], R0 ; /* 0x0000000004007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <math.h>
#ifndef ARRAY_SIZE
#define ARRAY_SIZE 256
#endif // !ARRAY_SIZE
#define ARRAY_SIZE_IN_BYTES (sizeof(unsigned int) * (ARRAY_SIZE))
#ifndef BLOCK_SIZE
#define BLOCK_SIZE 16
#endif // !BLOCK_SIZE
/* Declare statically two arrays of ARRAY_SIZE each */
unsigned int cpu_block[ARRAY_SIZE];
unsigned int cpu_thread[ARRAY_SIZE];
__global__
void what_is_my_id(unsigned int* block, unsigned int* thread)
{
const unsigned int thread_idx = (blockIdx.x * blockDim.x) + threadIdx.x;
block[thread_idx] = blockIdx.x;
thread[thread_idx] = threadIdx.x;
}
void main_sub0()
{
/* Declare pointers for GPU based params */
unsigned int* gpu_block;
unsigned int* gpu_thread;
cudaMalloc((void**)&gpu_block, ARRAY_SIZE_IN_BYTES);
cudaMalloc((void**)&gpu_thread, ARRAY_SIZE_IN_BYTES);
cudaMemcpy(cpu_block, gpu_block, ARRAY_SIZE_IN_BYTES, cudaMemcpyHostToDevice);
cudaMemcpy(cpu_thread, gpu_thread, ARRAY_SIZE_IN_BYTES, cudaMemcpyHostToDevice);
const unsigned int threads_per_block = BLOCK_SIZE;
const unsigned int num_blocks = ceil((double) ARRAY_SIZE / threads_per_block);
/* Execute our kernel */
what_is_my_id<<<num_blocks, threads_per_block>>>(gpu_block, gpu_thread);
/* Free the arrays on the GPU as now we're done with them */
cudaMemcpy(cpu_block, gpu_block, ARRAY_SIZE_IN_BYTES, cudaMemcpyDeviceToHost);
cudaMemcpy(cpu_thread, gpu_thread, ARRAY_SIZE_IN_BYTES, cudaMemcpyDeviceToHost);
cudaFree(gpu_block);
cudaFree(gpu_thread);
/* Iterate through the arrays and print */
for (unsigned int i = 0; i < ARRAY_SIZE; i++)
{
printf("i: %4u, Thread: %2u - Block: %2u\n", i, cpu_thread[i], cpu_block[i]);
}
}
int main()
{
main_sub0();
return EXIT_SUCCESS;
} | .file "tmpxft_0007bd03_00000000-6_blocks.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z13what_is_my_idPjS_PjS_
.type _Z35__device_stub__Z13what_is_my_idPjS_PjS_, @function
_Z35__device_stub__Z13what_is_my_idPjS_PjS_:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13what_is_my_idPjS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z35__device_stub__Z13what_is_my_idPjS_PjS_, .-_Z35__device_stub__Z13what_is_my_idPjS_PjS_
.globl _Z13what_is_my_idPjS_
.type _Z13what_is_my_idPjS_, @function
_Z13what_is_my_idPjS_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z13what_is_my_idPjS_PjS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z13what_is_my_idPjS_, .-_Z13what_is_my_idPjS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "i: %4u, Thread: %2u - Block: %2u\n"
.text
.globl _Z9main_sub0v
.type _Z9main_sub0v, @function
_Z9main_sub0v:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $1024, %edx
movq (%rsp), %rsi
leaq cpu_block(%rip), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $1024, %edx
movq 8(%rsp), %rsi
leaq cpu_thread(%rip), %rdi
call cudaMemcpy@PLT
movl $16, 28(%rsp)
movl $1, 32(%rsp)
movl $16, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
movl $2, %ecx
movl $1024, %edx
movq (%rsp), %rsi
leaq cpu_block(%rip), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $1024, %edx
movq 8(%rsp), %rsi
leaq cpu_thread(%rip), %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl $0, %ebx
leaq cpu_block(%rip), %r13
leaq cpu_thread(%rip), %r12
leaq .LC0(%rip), %rbp
.L13:
movl (%r12,%rbx,4), %ecx
movl 0(%r13,%rbx,4), %r8d
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $256, %rbx
jne .L13
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z35__device_stub__Z13what_is_my_idPjS_PjS_
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z9main_sub0v, .-_Z9main_sub0v
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z9main_sub0v
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z13what_is_my_idPjS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z13what_is_my_idPjS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl cpu_thread
.bss
.align 32
.type cpu_thread, @object
.size cpu_thread, 1024
cpu_thread:
.zero 1024
.globl cpu_block
.align 32
.type cpu_block, @object
.size cpu_block, 1024
cpu_block:
.zero 1024
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <math.h>
#ifndef ARRAY_SIZE
#define ARRAY_SIZE 256
#endif // !ARRAY_SIZE
#define ARRAY_SIZE_IN_BYTES (sizeof(unsigned int) * (ARRAY_SIZE))
#ifndef BLOCK_SIZE
#define BLOCK_SIZE 16
#endif // !BLOCK_SIZE
/* Declare statically two arrays of ARRAY_SIZE each */
unsigned int cpu_block[ARRAY_SIZE];
unsigned int cpu_thread[ARRAY_SIZE];
__global__
void what_is_my_id(unsigned int* block, unsigned int* thread)
{
const unsigned int thread_idx = (blockIdx.x * blockDim.x) + threadIdx.x;
block[thread_idx] = blockIdx.x;
thread[thread_idx] = threadIdx.x;
}
void main_sub0()
{
/* Declare pointers for GPU based params */
unsigned int* gpu_block;
unsigned int* gpu_thread;
cudaMalloc((void**)&gpu_block, ARRAY_SIZE_IN_BYTES);
cudaMalloc((void**)&gpu_thread, ARRAY_SIZE_IN_BYTES);
cudaMemcpy(cpu_block, gpu_block, ARRAY_SIZE_IN_BYTES, cudaMemcpyHostToDevice);
cudaMemcpy(cpu_thread, gpu_thread, ARRAY_SIZE_IN_BYTES, cudaMemcpyHostToDevice);
const unsigned int threads_per_block = BLOCK_SIZE;
const unsigned int num_blocks = ceil((double) ARRAY_SIZE / threads_per_block);
/* Execute our kernel */
what_is_my_id<<<num_blocks, threads_per_block>>>(gpu_block, gpu_thread);
/* Free the arrays on the GPU as now we're done with them */
cudaMemcpy(cpu_block, gpu_block, ARRAY_SIZE_IN_BYTES, cudaMemcpyDeviceToHost);
cudaMemcpy(cpu_thread, gpu_thread, ARRAY_SIZE_IN_BYTES, cudaMemcpyDeviceToHost);
cudaFree(gpu_block);
cudaFree(gpu_thread);
/* Iterate through the arrays and print */
for (unsigned int i = 0; i < ARRAY_SIZE; i++)
{
printf("i: %4u, Thread: %2u - Block: %2u\n", i, cpu_thread[i], cpu_block[i]);
}
}
int main()
{
main_sub0();
return EXIT_SUCCESS;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#ifndef ARRAY_SIZE
#define ARRAY_SIZE 256
#endif // !ARRAY_SIZE
#define ARRAY_SIZE_IN_BYTES (sizeof(unsigned int) * (ARRAY_SIZE))
#ifndef BLOCK_SIZE
#define BLOCK_SIZE 16
#endif // !BLOCK_SIZE
/* Declare statically two arrays of ARRAY_SIZE each */
unsigned int cpu_block[ARRAY_SIZE];
unsigned int cpu_thread[ARRAY_SIZE];
__global__
void what_is_my_id(unsigned int* block, unsigned int* thread)
{
const unsigned int thread_idx = (blockIdx.x * blockDim.x) + threadIdx.x;
block[thread_idx] = blockIdx.x;
thread[thread_idx] = threadIdx.x;
}
void main_sub0()
{
/* Declare pointers for GPU based params */
unsigned int* gpu_block;
unsigned int* gpu_thread;
hipMalloc((void**)&gpu_block, ARRAY_SIZE_IN_BYTES);
hipMalloc((void**)&gpu_thread, ARRAY_SIZE_IN_BYTES);
hipMemcpy(cpu_block, gpu_block, ARRAY_SIZE_IN_BYTES, hipMemcpyHostToDevice);
hipMemcpy(cpu_thread, gpu_thread, ARRAY_SIZE_IN_BYTES, hipMemcpyHostToDevice);
const unsigned int threads_per_block = BLOCK_SIZE;
const unsigned int num_blocks = ceil((double) ARRAY_SIZE / threads_per_block);
/* Execute our kernel */
what_is_my_id<<<num_blocks, threads_per_block>>>(gpu_block, gpu_thread);
/* Free the arrays on the GPU as now we're done with them */
hipMemcpy(cpu_block, gpu_block, ARRAY_SIZE_IN_BYTES, hipMemcpyDeviceToHost);
hipMemcpy(cpu_thread, gpu_thread, ARRAY_SIZE_IN_BYTES, hipMemcpyDeviceToHost);
hipFree(gpu_block);
hipFree(gpu_thread);
/* Iterate through the arrays and print */
for (unsigned int i = 0; i < ARRAY_SIZE; i++)
{
printf("i: %4u, Thread: %2u - Block: %2u\n", i, cpu_thread[i], cpu_block[i]);
}
}
int main()
{
main_sub0();
return EXIT_SUCCESS;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#ifndef ARRAY_SIZE
#define ARRAY_SIZE 256
#endif // !ARRAY_SIZE
#define ARRAY_SIZE_IN_BYTES (sizeof(unsigned int) * (ARRAY_SIZE))
#ifndef BLOCK_SIZE
#define BLOCK_SIZE 16
#endif // !BLOCK_SIZE
/* Declare statically two arrays of ARRAY_SIZE each */
unsigned int cpu_block[ARRAY_SIZE];
unsigned int cpu_thread[ARRAY_SIZE];
__global__
void what_is_my_id(unsigned int* block, unsigned int* thread)
{
const unsigned int thread_idx = (blockIdx.x * blockDim.x) + threadIdx.x;
block[thread_idx] = blockIdx.x;
thread[thread_idx] = threadIdx.x;
}
void main_sub0()
{
/* Declare pointers for GPU based params */
unsigned int* gpu_block;
unsigned int* gpu_thread;
hipMalloc((void**)&gpu_block, ARRAY_SIZE_IN_BYTES);
hipMalloc((void**)&gpu_thread, ARRAY_SIZE_IN_BYTES);
hipMemcpy(cpu_block, gpu_block, ARRAY_SIZE_IN_BYTES, hipMemcpyHostToDevice);
hipMemcpy(cpu_thread, gpu_thread, ARRAY_SIZE_IN_BYTES, hipMemcpyHostToDevice);
const unsigned int threads_per_block = BLOCK_SIZE;
const unsigned int num_blocks = ceil((double) ARRAY_SIZE / threads_per_block);
/* Execute our kernel */
what_is_my_id<<<num_blocks, threads_per_block>>>(gpu_block, gpu_thread);
/* Free the arrays on the GPU as now we're done with them */
hipMemcpy(cpu_block, gpu_block, ARRAY_SIZE_IN_BYTES, hipMemcpyDeviceToHost);
hipMemcpy(cpu_thread, gpu_thread, ARRAY_SIZE_IN_BYTES, hipMemcpyDeviceToHost);
hipFree(gpu_block);
hipFree(gpu_thread);
/* Iterate through the arrays and print */
for (unsigned int i = 0; i < ARRAY_SIZE; i++)
{
printf("i: %4u, Thread: %2u - Block: %2u\n", i, cpu_thread[i], cpu_block[i]);
}
}
int main()
{
main_sub0();
return EXIT_SUCCESS;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13what_is_my_idPjS_
.globl _Z13what_is_my_idPjS_
.p2align 8
.type _Z13what_is_my_idPjS_,@function
_Z13what_is_my_idPjS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v5, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_store_b32 v[3:4], v5, off
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13what_is_my_idPjS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13what_is_my_idPjS_, .Lfunc_end0-_Z13what_is_my_idPjS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13what_is_my_idPjS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13what_is_my_idPjS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#ifndef ARRAY_SIZE
#define ARRAY_SIZE 256
#endif // !ARRAY_SIZE
#define ARRAY_SIZE_IN_BYTES (sizeof(unsigned int) * (ARRAY_SIZE))
#ifndef BLOCK_SIZE
#define BLOCK_SIZE 16
#endif // !BLOCK_SIZE
/* Declare statically two arrays of ARRAY_SIZE each */
unsigned int cpu_block[ARRAY_SIZE];
unsigned int cpu_thread[ARRAY_SIZE];
__global__
void what_is_my_id(unsigned int* block, unsigned int* thread)
{
const unsigned int thread_idx = (blockIdx.x * blockDim.x) + threadIdx.x;
block[thread_idx] = blockIdx.x;
thread[thread_idx] = threadIdx.x;
}
void main_sub0()
{
/* Declare pointers for GPU based params */
unsigned int* gpu_block;
unsigned int* gpu_thread;
hipMalloc((void**)&gpu_block, ARRAY_SIZE_IN_BYTES);
hipMalloc((void**)&gpu_thread, ARRAY_SIZE_IN_BYTES);
hipMemcpy(cpu_block, gpu_block, ARRAY_SIZE_IN_BYTES, hipMemcpyHostToDevice);
hipMemcpy(cpu_thread, gpu_thread, ARRAY_SIZE_IN_BYTES, hipMemcpyHostToDevice);
const unsigned int threads_per_block = BLOCK_SIZE;
const unsigned int num_blocks = ceil((double) ARRAY_SIZE / threads_per_block);
/* Execute our kernel */
what_is_my_id<<<num_blocks, threads_per_block>>>(gpu_block, gpu_thread);
/* Free the arrays on the GPU as now we're done with them */
hipMemcpy(cpu_block, gpu_block, ARRAY_SIZE_IN_BYTES, hipMemcpyDeviceToHost);
hipMemcpy(cpu_thread, gpu_thread, ARRAY_SIZE_IN_BYTES, hipMemcpyDeviceToHost);
hipFree(gpu_block);
hipFree(gpu_thread);
/* Iterate through the arrays and print */
for (unsigned int i = 0; i < ARRAY_SIZE; i++)
{
printf("i: %4u, Thread: %2u - Block: %2u\n", i, cpu_thread[i], cpu_block[i]);
}
}
int main()
{
main_sub0();
return EXIT_SUCCESS;
} | .text
.file "blocks.hip"
.globl _Z28__device_stub__what_is_my_idPjS_ # -- Begin function _Z28__device_stub__what_is_my_idPjS_
.p2align 4, 0x90
.type _Z28__device_stub__what_is_my_idPjS_,@function
_Z28__device_stub__what_is_my_idPjS_: # @_Z28__device_stub__what_is_my_idPjS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13what_is_my_idPjS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z28__device_stub__what_is_my_idPjS_, .Lfunc_end0-_Z28__device_stub__what_is_my_idPjS_
.cfi_endproc
# -- End function
.globl _Z9main_sub0v # -- Begin function _Z9main_sub0v
.p2align 4, 0x90
.type _Z9main_sub0v,@function
_Z9main_sub0v: # @_Z9main_sub0v
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $96, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -16
leaq 8(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movq %rsp, %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movq 8(%rsp), %rsi
movl $cpu_block, %edi
movl $1024, %edx # imm = 0x400
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rsi
movl $cpu_thread, %edi
movl $1024, %edx # imm = 0x400
movl $1, %ecx
callq hipMemcpy
movabsq $4294967312, %rdi # imm = 0x100000010
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13what_is_my_idPjS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movl $cpu_block, %edi
movl $1024, %edx # imm = 0x400
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rsi
movl $cpu_thread, %edi
movl $1024, %edx # imm = 0x400
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movl cpu_thread(,%rbx,4), %edx
movl cpu_block(,%rbx,4), %ecx
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $256, %rbx # imm = 0x100
jne .LBB1_3
# %bb.4:
addq $96, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z9main_sub0v, .Lfunc_end1-_Z9main_sub0v
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq _Z9main_sub0v
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13what_is_my_idPjS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type cpu_block,@object # @cpu_block
.bss
.globl cpu_block
.p2align 4, 0x0
cpu_block:
.zero 1024
.size cpu_block, 1024
.type cpu_thread,@object # @cpu_thread
.globl cpu_thread
.p2align 4, 0x0
cpu_thread:
.zero 1024
.size cpu_thread, 1024
.type _Z13what_is_my_idPjS_,@object # @_Z13what_is_my_idPjS_
.section .rodata,"a",@progbits
.globl _Z13what_is_my_idPjS_
.p2align 3, 0x0
_Z13what_is_my_idPjS_:
.quad _Z28__device_stub__what_is_my_idPjS_
.size _Z13what_is_my_idPjS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "i: %4u, Thread: %2u - Block: %2u\n"
.size .L.str, 34
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13what_is_my_idPjS_"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__what_is_my_idPjS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym cpu_block
.addrsig_sym cpu_thread
.addrsig_sym _Z13what_is_my_idPjS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13what_is_my_idPjS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R7, c[0x0][0x0], R0 ; /* 0x0000000007047a24 */
/* 0x001fca00078e0200 */
/*0060*/ IMAD.WIDE.U32 R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fc800078e0005 */
/*0070*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe200078e0005 */
/*0080*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101904 */
/*0090*/ STG.E [R4.64], R0 ; /* 0x0000000004007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13what_is_my_idPjS_
.globl _Z13what_is_my_idPjS_
.p2align 8
.type _Z13what_is_my_idPjS_,@function
_Z13what_is_my_idPjS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v5, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_store_b32 v[3:4], v5, off
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13what_is_my_idPjS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13what_is_my_idPjS_, .Lfunc_end0-_Z13what_is_my_idPjS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13what_is_my_idPjS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13what_is_my_idPjS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007bd03_00000000-6_blocks.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z13what_is_my_idPjS_PjS_
.type _Z35__device_stub__Z13what_is_my_idPjS_PjS_, @function
_Z35__device_stub__Z13what_is_my_idPjS_PjS_:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13what_is_my_idPjS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z35__device_stub__Z13what_is_my_idPjS_PjS_, .-_Z35__device_stub__Z13what_is_my_idPjS_PjS_
.globl _Z13what_is_my_idPjS_
.type _Z13what_is_my_idPjS_, @function
_Z13what_is_my_idPjS_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z13what_is_my_idPjS_PjS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z13what_is_my_idPjS_, .-_Z13what_is_my_idPjS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "i: %4u, Thread: %2u - Block: %2u\n"
.text
.globl _Z9main_sub0v
.type _Z9main_sub0v, @function
_Z9main_sub0v:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $1024, %edx
movq (%rsp), %rsi
leaq cpu_block(%rip), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $1024, %edx
movq 8(%rsp), %rsi
leaq cpu_thread(%rip), %rdi
call cudaMemcpy@PLT
movl $16, 28(%rsp)
movl $1, 32(%rsp)
movl $16, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
movl $2, %ecx
movl $1024, %edx
movq (%rsp), %rsi
leaq cpu_block(%rip), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $1024, %edx
movq 8(%rsp), %rsi
leaq cpu_thread(%rip), %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl $0, %ebx
leaq cpu_block(%rip), %r13
leaq cpu_thread(%rip), %r12
leaq .LC0(%rip), %rbp
.L13:
movl (%r12,%rbx,4), %ecx
movl 0(%r13,%rbx,4), %r8d
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $256, %rbx
jne .L13
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z35__device_stub__Z13what_is_my_idPjS_PjS_
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z9main_sub0v, .-_Z9main_sub0v
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z9main_sub0v
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z13what_is_my_idPjS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z13what_is_my_idPjS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl cpu_thread
.bss
.align 32
.type cpu_thread, @object
.size cpu_thread, 1024
cpu_thread:
.zero 1024
.globl cpu_block
.align 32
.type cpu_block, @object
.size cpu_block, 1024
cpu_block:
.zero 1024
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "blocks.hip"
.globl _Z28__device_stub__what_is_my_idPjS_ # -- Begin function _Z28__device_stub__what_is_my_idPjS_
.p2align 4, 0x90
.type _Z28__device_stub__what_is_my_idPjS_,@function
_Z28__device_stub__what_is_my_idPjS_: # @_Z28__device_stub__what_is_my_idPjS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13what_is_my_idPjS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z28__device_stub__what_is_my_idPjS_, .Lfunc_end0-_Z28__device_stub__what_is_my_idPjS_
.cfi_endproc
# -- End function
.globl _Z9main_sub0v # -- Begin function _Z9main_sub0v
.p2align 4, 0x90
.type _Z9main_sub0v,@function
_Z9main_sub0v: # @_Z9main_sub0v
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $96, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -16
leaq 8(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movq %rsp, %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movq 8(%rsp), %rsi
movl $cpu_block, %edi
movl $1024, %edx # imm = 0x400
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rsi
movl $cpu_thread, %edi
movl $1024, %edx # imm = 0x400
movl $1, %ecx
callq hipMemcpy
movabsq $4294967312, %rdi # imm = 0x100000010
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13what_is_my_idPjS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movl $cpu_block, %edi
movl $1024, %edx # imm = 0x400
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rsi
movl $cpu_thread, %edi
movl $1024, %edx # imm = 0x400
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movl cpu_thread(,%rbx,4), %edx
movl cpu_block(,%rbx,4), %ecx
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $256, %rbx # imm = 0x100
jne .LBB1_3
# %bb.4:
addq $96, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z9main_sub0v, .Lfunc_end1-_Z9main_sub0v
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq _Z9main_sub0v
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13what_is_my_idPjS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type cpu_block,@object # @cpu_block
.bss
.globl cpu_block
.p2align 4, 0x0
cpu_block:
.zero 1024
.size cpu_block, 1024
.type cpu_thread,@object # @cpu_thread
.globl cpu_thread
.p2align 4, 0x0
cpu_thread:
.zero 1024
.size cpu_thread, 1024
.type _Z13what_is_my_idPjS_,@object # @_Z13what_is_my_idPjS_
.section .rodata,"a",@progbits
.globl _Z13what_is_my_idPjS_
.p2align 3, 0x0
_Z13what_is_my_idPjS_:
.quad _Z28__device_stub__what_is_my_idPjS_
.size _Z13what_is_my_idPjS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "i: %4u, Thread: %2u - Block: %2u\n"
.size .L.str, 34
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13what_is_my_idPjS_"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__what_is_my_idPjS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym cpu_block
.addrsig_sym cpu_thread
.addrsig_sym _Z13what_is_my_idPjS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda_runtime.h>
#define CHECK(call) { \
const cudaError_t error = call; \
if (error != cudaSuccess) { \
printf("Error: %s:%d, ", __FILE__, __LINE__); \
printf("code: %d, reason: %s\n", error, cudaGetErrorString(error)); \
exit(1); \
} \
} \
#define RADIUS 4
#define BLOCKSIZE 128
// coeffecient
#define a0 0.00000f
#define a1 0.80000f
#define a2 -0.20000f
#define a3 0.03809f
#define a4 -0.00357f
// constant memory
__constant__ float coef[RADIUS + 1];
void initialData(float *ip, const int size);
void stencilHost(float *in, float *out, int isize);
void checkResult(float *hostRef, float *gpuRef, const int size);
__global__ void stencilGPU(float *in, float *out, const int n);
int main(int argc, char **argv) {
// set up device
int dev = 0;
cudaDeviceProp deviceProp;
CHECK(cudaGetDeviceProperties(&deviceProp, dev));
printf("Using Device %d: %s\n", dev, deviceProp.name);
CHECK(cudaSetDevice(dev));
// set up data size
int isize = 1 << 24;
size_t nBytes = (isize + 2 * RADIUS) * sizeof(float);
printf("array size: %d\n", isize);
// allocate host memory
float *h_in = (float *)malloc(nBytes);
float *h_out = (float *)malloc(nBytes);
float *h_out_gpu = (float *)malloc(nBytes);
initialData(h_in, isize + 2 * RADIUS);
// compute on CPU
stencilHost(h_in, h_out, isize);
// allocate device memory
float *d_in, *d_out;
CHECK(cudaMalloc((float**)&d_in, nBytes));
CHECK(cudaMalloc((float**)&d_out, nBytes));
CHECK(cudaMemcpy(d_in, h_in, nBytes, cudaMemcpyHostToDevice));
// set up constant memory
const float h_coef[] = {a0, a1, a2, a3, a4};
CHECK(cudaMemcpyToSymbol(coef, h_coef, (RADIUS + 1) * sizeof(float)));
// launch CUDA kernel
cudaDeviceProp info;
CHECK(cudaGetDeviceProperties(&info, 0));
dim3 block(BLOCKSIZE);
dim3 grid(info.maxGridSize[0] < isize / block.x ? info.maxGridSize[0] : isize / block.x);
printf("(grid, block) %d,%d \n", grid.x, block.x);
stencilGPU<<<grid, block>>>(d_in + RADIUS, d_out + RADIUS, isize);
CHECK(cudaMemcpy(h_out_gpu, d_out, nBytes, cudaMemcpyDeviceToHost));
checkResult(h_out, h_out_gpu, isize);
// free memory
CHECK(cudaFree(d_in));
CHECK(cudaFree(d_out));
free(h_in);
free(h_out);
free(h_out_gpu);
// reset device
CHECK(cudaDeviceReset());
return 0;
}
/**********CUDA kernels**********/
__global__ void stencilGPU(float *in, float *out, const int n) {
// shared memory
__shared__ float smem[BLOCKSIZE + 2 * RADIUS];
// index to global memory
int idx = blockIdx.x * blockDim.x + threadIdx.x;
while (idx < n) {
int sidx = threadIdx.x + RADIUS; // index to shared memory for stencil calculatioin
smem[sidx] = in[idx]; // read data from global memory into shared memory
if (threadIdx.x < RADIUS) { // read halo part to shared memory
smem[sidx - RADIUS] = in[idx - RADIUS];
smem[sidx + BLOCKSIZE] = in[idx + BLOCKSIZE];
}
__syncthreads();
float tmp = coef[0];
#pragma unroll
for (int i = 1; i <= RADIUS; i++) {
tmp += coef[i] * (smem[sidx + i] - smem[sidx - i]);
}
out[idx] = tmp;
idx += gridDim.x * blockDim.x;
}
}
/**********host functions**********/
void initialData(float *ip, const int size) {
for (int i = 0; i < size; i++) {
ip[i] = (float)(rand() & 0xFF) / 100.0f;
}
}
void stencilHost(float *in, float *out, int isize)
{
for (int i = RADIUS; i <= isize; i++) {
out[i] = a0 + a1 * (in[i + 1] - in[i - 1])
+ a2 * (in[i + 2] - in[i - 2])
+ a3 * (in[i + 3] - in[i - 3])
+ a4 * (in[i + 4] - in[i - 4]);
}
}
void checkResult(float *hostRef, float *gpuRef, const int size) {
double epsilon = 1.0E-6;
for (int i = RADIUS; i < size; i++) {
if (abs(hostRef[i] - gpuRef[i]) > epsilon) {
printf("different on %dth element: host %f gpu %f\n", i, hostRef[i], gpuRef[i]);
break;
}
}
} | code for sm_80
Function : _Z10stencilGPUPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R3, c[0x0][0x0], R0 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ISETP.GT.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe20003f04070 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ MOV R4, R2 ; /* 0x0000000200047202 */
/* 0x000fe40000000f00 */
/*0090*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x001fd400000001ff */
/*00a0*/ IMAD.WIDE R2, R4, R3, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fca00078e0203 */
/*00b0*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x0000a8000c1e1900 */
/*00c0*/ @!P0 LDG.E R7, [R2.64+-0x10] ; /* 0xfffff00402078981 */
/* 0x0000e8000c1e1900 */
/*00d0*/ @!P0 LDG.E R9, [R2.64+0x200] ; /* 0x0002000402098981 */
/* 0x000122000c1e1900 */
/*00e0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*00f0*/ LEA R2, P1, R4, c[0x0][0x168], 0x2 ; /* 0x00005a0004027a11 */
/* 0x001fc400078210ff */
/*0100*/ STS [R0.X4+0x10], R5 ; /* 0x0000100500007388 */
/* 0x004fe80000004800 */
/*0110*/ @!P0 STS [R0.X4], R7 ; /* 0x0000000700008388 */
/* 0x0081e80000004800 */
/*0120*/ @!P0 STS [R0.X4+0x210], R9 ; /* 0x0002100900008388 */
/* 0x010fe80000004800 */
/*0130*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0140*/ MOV R7, c[0x3][0x4] ; /* 0x00c0010000077a02 */
/* 0x001fca0000000f00 */
/*0150*/ LDS R6, [R0.X4+0xc] ; /* 0x00000c0000067984 */
/* 0x000fe80000004800 */
/*0160*/ LDS R11, [R0.X4+0x14] ; /* 0x00001400000b7984 */
/* 0x000e280000004800 */
/*0170*/ LDS R8, [R0.X4+0x8] ; /* 0x0000080000087984 */
/* 0x000fe80000004800 */
/*0180*/ LDS R13, [R0.X4+0x18] ; /* 0x00001800000d7984 */
/* 0x000e680000004800 */
/*0190*/ LDS R10, [R0.X4+0x4] ; /* 0x00000400000a7984 */
/* 0x000fe80000004800 */
/*01a0*/ LDS R3, [R0.X4+0x1c] ; /* 0x00001c0000037984 */
/* 0x000ea80000004800 */
/*01b0*/ LDS R5, [R0.X4] ; /* 0x0000000000057984 */
/* 0x000fe80000004800 */
/*01c0*/ LDS R12, [R0.X4+0x20] ; /* 0x00002000000c7984 */
/* 0x000ee20000004800 */
/*01d0*/ FADD R6, -R6, R11 ; /* 0x0000000b06067221 */
/* 0x001fc80000000100 */
/*01e0*/ FFMA R6, R6, R7, c[0x3][0x0] ; /* 0x00c0000006067623 */
/* 0x000fe20000000007 */
/*01f0*/ MOV R7, c[0x0][0xc] ; /* 0x0000030000077a02 */
/* 0x000fe20000000f00 */
/*0200*/ FADD R13, -R8, R13 ; /* 0x0000000d080d7221 */
/* 0x002fc80000000100 */
/*0210*/ FFMA R6, R13, c[0x3][0x8], R6 ; /* 0x00c002000d067a23 */
/* 0x000fe40000000006 */
/*0220*/ FADD R3, -R10, R3 ; /* 0x000000030a037221 */
/* 0x004fc80000000100 */
/*0230*/ FFMA R6, R3, c[0x3][0xc], R6 ; /* 0x00c0030003067a23 */
/* 0x000fe20000000006 */
/*0240*/ SHF.R.S32.HI R3, RZ, 0x1f, R4 ; /* 0x0000001fff037819 */
/* 0x000fe20000011404 */
/*0250*/ FADD R5, -R5, R12 ; /* 0x0000000c05057221 */
/* 0x008fc60000000100 */
/*0260*/ LEA.HI.X R3, R4, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0004037a11 */
/* 0x000fe200008f1403 */
/*0270*/ IMAD R4, R7, c[0x0][0x0], R4 ; /* 0x0000000007047a24 */
/* 0x000fe400078e0204 */
/*0280*/ FFMA R5, R5, c[0x3][0x10], R6 ; /* 0x00c0040005057a23 */
/* 0x000fc60000000006 */
/*0290*/ ISETP.GE.AND P1, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fe40003f26270 */
/*02a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001f6000c101904 */
/*02b0*/ @!P1 BRA 0x90 ; /* 0xfffffdd000009947 */
/* 0x000fea000383ffff */
/*02c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02d0*/ BRA 0x2d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda_runtime.h>
#define CHECK(call) { \
const cudaError_t error = call; \
if (error != cudaSuccess) { \
printf("Error: %s:%d, ", __FILE__, __LINE__); \
printf("code: %d, reason: %s\n", error, cudaGetErrorString(error)); \
exit(1); \
} \
} \
#define RADIUS 4
#define BLOCKSIZE 128
// coeffecient
#define a0 0.00000f
#define a1 0.80000f
#define a2 -0.20000f
#define a3 0.03809f
#define a4 -0.00357f
// constant memory
__constant__ float coef[RADIUS + 1];
void initialData(float *ip, const int size);
void stencilHost(float *in, float *out, int isize);
void checkResult(float *hostRef, float *gpuRef, const int size);
__global__ void stencilGPU(float *in, float *out, const int n);
int main(int argc, char **argv) {
// set up device
int dev = 0;
cudaDeviceProp deviceProp;
CHECK(cudaGetDeviceProperties(&deviceProp, dev));
printf("Using Device %d: %s\n", dev, deviceProp.name);
CHECK(cudaSetDevice(dev));
// set up data size
int isize = 1 << 24;
size_t nBytes = (isize + 2 * RADIUS) * sizeof(float);
printf("array size: %d\n", isize);
// allocate host memory
float *h_in = (float *)malloc(nBytes);
float *h_out = (float *)malloc(nBytes);
float *h_out_gpu = (float *)malloc(nBytes);
initialData(h_in, isize + 2 * RADIUS);
// compute on CPU
stencilHost(h_in, h_out, isize);
// allocate device memory
float *d_in, *d_out;
CHECK(cudaMalloc((float**)&d_in, nBytes));
CHECK(cudaMalloc((float**)&d_out, nBytes));
CHECK(cudaMemcpy(d_in, h_in, nBytes, cudaMemcpyHostToDevice));
// set up constant memory
const float h_coef[] = {a0, a1, a2, a3, a4};
CHECK(cudaMemcpyToSymbol(coef, h_coef, (RADIUS + 1) * sizeof(float)));
// launch CUDA kernel
cudaDeviceProp info;
CHECK(cudaGetDeviceProperties(&info, 0));
dim3 block(BLOCKSIZE);
dim3 grid(info.maxGridSize[0] < isize / block.x ? info.maxGridSize[0] : isize / block.x);
printf("(grid, block) %d,%d \n", grid.x, block.x);
stencilGPU<<<grid, block>>>(d_in + RADIUS, d_out + RADIUS, isize);
CHECK(cudaMemcpy(h_out_gpu, d_out, nBytes, cudaMemcpyDeviceToHost));
checkResult(h_out, h_out_gpu, isize);
// free memory
CHECK(cudaFree(d_in));
CHECK(cudaFree(d_out));
free(h_in);
free(h_out);
free(h_out_gpu);
// reset device
CHECK(cudaDeviceReset());
return 0;
}
/**********CUDA kernels**********/
__global__ void stencilGPU(float *in, float *out, const int n) {
// shared memory
__shared__ float smem[BLOCKSIZE + 2 * RADIUS];
// index to global memory
int idx = blockIdx.x * blockDim.x + threadIdx.x;
while (idx < n) {
int sidx = threadIdx.x + RADIUS; // index to shared memory for stencil calculatioin
smem[sidx] = in[idx]; // read data from global memory into shared memory
if (threadIdx.x < RADIUS) { // read halo part to shared memory
smem[sidx - RADIUS] = in[idx - RADIUS];
smem[sidx + BLOCKSIZE] = in[idx + BLOCKSIZE];
}
__syncthreads();
float tmp = coef[0];
#pragma unroll
for (int i = 1; i <= RADIUS; i++) {
tmp += coef[i] * (smem[sidx + i] - smem[sidx - i]);
}
out[idx] = tmp;
idx += gridDim.x * blockDim.x;
}
}
/**********host functions**********/
void initialData(float *ip, const int size) {
for (int i = 0; i < size; i++) {
ip[i] = (float)(rand() & 0xFF) / 100.0f;
}
}
void stencilHost(float *in, float *out, int isize)
{
for (int i = RADIUS; i <= isize; i++) {
out[i] = a0 + a1 * (in[i + 1] - in[i - 1])
+ a2 * (in[i + 2] - in[i - 2])
+ a3 * (in[i + 3] - in[i - 3])
+ a4 * (in[i + 4] - in[i - 4]);
}
}
void checkResult(float *hostRef, float *gpuRef, const int size) {
double epsilon = 1.0E-6;
for (int i = RADIUS; i < size; i++) {
if (abs(hostRef[i] - gpuRef[i]) > epsilon) {
printf("different on %dth element: host %f gpu %f\n", i, hostRef[i], gpuRef[i]);
break;
}
}
} | .file "tmpxft_000f7894_00000000-6_stencilConstantMem.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initialDataPfi
.type _Z11initialDataPfi, @function
_Z11initialDataPfi:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
movzbl %al, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
divss .LC0(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2058:
.size _Z11initialDataPfi, .-_Z11initialDataPfi
.globl _Z11stencilHostPfS_i
.type _Z11stencilHostPfS_i, @function
_Z11stencilHostPfS_i:
.LFB2059:
.cfi_startproc
endbr64
cmpl $3, %edx
jle .L11
movq %rdi, %rax
addq $16, %rsi
leal -4(%rdx), %edx
leaq 4(%rdi,%rdx,4), %rdx
movss .LC1(%rip), %xmm6
pxor %xmm5, %xmm5
movss .LC3(%rip), %xmm4
movss .LC4(%rip), %xmm3
movss .LC5(%rip), %xmm2
.L13:
movss 20(%rax), %xmm0
subss 12(%rax), %xmm0
mulss %xmm6, %xmm0
addss %xmm5, %xmm0
movss 24(%rax), %xmm1
subss 8(%rax), %xmm1
mulss %xmm4, %xmm1
addss %xmm1, %xmm0
movss 28(%rax), %xmm1
subss 4(%rax), %xmm1
mulss %xmm3, %xmm1
addss %xmm1, %xmm0
movss 32(%rax), %xmm1
subss (%rax), %xmm1
mulss %xmm2, %xmm1
addss %xmm1, %xmm0
movss %xmm0, (%rsi)
addq $4, %rax
addq $4, %rsi
cmpq %rdx, %rax
jne .L13
.L11:
ret
.cfi_endproc
.LFE2059:
.size _Z11stencilHostPfS_i, .-_Z11stencilHostPfS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC8:
.string "different on %dth element: host %f gpu %f\n"
.text
.globl _Z11checkResultPfS_i
.type _Z11checkResultPfS_i, @function
_Z11checkResultPfS_i:
.LFB2060:
.cfi_startproc
endbr64
cmpl $4, %edx
jle .L24
movl %edx, %eax
movl $4, %edx
movss .LC6(%rip), %xmm4
movsd .LC7(%rip), %xmm3
.L19:
movss (%rdi,%rdx,4), %xmm0
movss (%rsi,%rdx,4), %xmm1
movaps %xmm0, %xmm2
subss %xmm1, %xmm2
andps %xmm4, %xmm2
cvtss2sd %xmm2, %xmm2
comisd %xmm3, %xmm2
ja .L27
addq $1, %rdx
cmpq %rax, %rdx
jne .L19
ret
.L27:
subq $8, %rsp
.cfi_def_cfa_offset 16
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L24:
ret
.cfi_endproc
.LFE2060:
.size _Z11checkResultPfS_i, .-_Z11checkResultPfS_i
.globl _Z33__device_stub__Z10stencilGPUPfS_iPfS_i
.type _Z33__device_stub__Z10stencilGPUPfS_iPfS_i, @function
_Z33__device_stub__Z10stencilGPUPfS_iPfS_i:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L32
.L28:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L33
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10stencilGPUPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L28
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z33__device_stub__Z10stencilGPUPfS_iPfS_i, .-_Z33__device_stub__Z10stencilGPUPfS_iPfS_i
.globl _Z10stencilGPUPfS_i
.type _Z10stencilGPUPfS_i, @function
_Z10stencilGPUPfS_i:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10stencilGPUPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z10stencilGPUPfS_i, .-_Z10stencilGPUPfS_i
.section .rodata.str1.8
.align 8
.LC9:
.string "/home/ubuntu/Datasets/stackv2/train-structured/SaoYan/Learning_CUDA/master/Ch5/stencilConstantMem.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC10:
.string "Error: %s:%d, "
.LC11:
.string "code: %d, reason: %s\n"
.LC12:
.string "Using Device %d: %s\n"
.LC13:
.string "array size: %d\n"
.LC14:
.string "(grid, block) %d,%d \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $2168, %rsp
.cfi_def_cfa_offset 2208
movq %fs:40, %rax
movq %rax, 2152(%rsp)
xorl %eax, %eax
leaq 80(%rsp), %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
testl %eax, %eax
jne .L51
leaq 80(%rsp), %rcx
movl $0, %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call cudaSetDevice@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L52
movl $16777216, %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $67108896, %edi
call malloc@PLT
movq %rax, %rbx
movl $67108896, %edi
call malloc@PLT
movq %rax, %rbp
movl $67108896, %edi
call malloc@PLT
movq %rax, %r12
movl $16777224, %esi
movq %rbx, %rdi
call _Z11initialDataPfi
movl $16777216, %edx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z11stencilHostPfS_i
leaq 8(%rsp), %rdi
movl $67108896, %esi
call cudaMalloc@PLT
movl %eax, %r13d
testl %eax, %eax
jne .L53
leaq 16(%rsp), %rdi
movl $67108896, %esi
call cudaMalloc@PLT
movl %eax, %r13d
testl %eax, %eax
jne .L54
movl $1, %ecx
movl $67108896, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %r13d
testl %eax, %eax
jne .L55
movl $0x00000000, 48(%rsp)
movl $0x3f4ccccd, 52(%rsp)
movl $0xbe4ccccd, 56(%rsp)
movl $0x3d1c0443, 60(%rsp)
movl $0xbb69f6a9, 64(%rsp)
leaq 48(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $20, %edx
leaq _ZL4coef(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl %eax, %r13d
testl %eax, %eax
jne .L56
leaq 1120(%rsp), %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
movl %eax, %r13d
testl %eax, %eax
jne .L57
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl 1456(%rsp), %r13d
movl $131072, %eax
cmpl %eax, %r13d
cmova %eax, %r13d
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $128, %ecx
movl %r13d, %edx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, 36(%rsp)
movl $128, 24(%rsp)
movl 32(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movq 36(%rsp), %rdi
movl 44(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L58
.L44:
movl $2, %ecx
movl $67108896, %edx
movq 16(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl %eax, %r13d
testl %eax, %eax
jne .L59
movl $16777216, %edx
movq %r12, %rsi
movq %rbp, %rdi
call _Z11checkResultPfS_i
movq 8(%rsp), %rdi
call cudaFree@PLT
movl %eax, %r13d
testl %eax, %eax
jne .L60
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, %r13d
testl %eax, %eax
jne .L61
movq %rbx, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
call cudaDeviceReset@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L62
movq 2152(%rsp), %rax
subq %fs:40, %rax
jne .L63
movl $0, %eax
addq $2168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L51:
.cfi_restore_state
movl %eax, %ebx
movl $36, %ecx
leaq .LC9(%rip), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L52:
movl $38, %ecx
leaq .LC9(%rip), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L53:
movl $57, %ecx
leaq .LC9(%rip), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r13d, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L54:
movl $58, %ecx
leaq .LC9(%rip), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r13d, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L55:
movl $59, %ecx
leaq .LC9(%rip), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r13d, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L56:
movl $63, %ecx
leaq .LC9(%rip), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r13d, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L57:
movl $67, %ecx
leaq .LC9(%rip), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r13d, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L58:
movq 16(%rsp), %rax
leaq 16(%rax), %rsi
movq 8(%rsp), %rax
leaq 16(%rax), %rdi
movl $16777216, %edx
call _Z33__device_stub__Z10stencilGPUPfS_iPfS_i
jmp .L44
.L59:
movl $73, %ecx
leaq .LC9(%rip), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r13d, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L60:
movl $77, %ecx
leaq .LC9(%rip), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r13d, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L61:
movl $78, %ecx
leaq .LC9(%rip), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r13d, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L62:
movl $84, %ecx
leaq .LC9(%rip), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L63:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC15:
.string "_Z10stencilGPUPfS_i"
.LC16:
.string "coef"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z10stencilGPUPfS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $20, %r9d
movl $0, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _ZL4coef(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL4coef
.comm _ZL4coef,20,16
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1120403456
.align 4
.LC1:
.long 1061997773
.align 4
.LC3:
.long -1102263091
.align 4
.LC4:
.long 1025246275
.align 4
.LC5:
.long -1150683479
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC6:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC7:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda_runtime.h>
#define CHECK(call) { \
const cudaError_t error = call; \
if (error != cudaSuccess) { \
printf("Error: %s:%d, ", __FILE__, __LINE__); \
printf("code: %d, reason: %s\n", error, cudaGetErrorString(error)); \
exit(1); \
} \
} \
#define RADIUS 4
#define BLOCKSIZE 128
// coeffecient
#define a0 0.00000f
#define a1 0.80000f
#define a2 -0.20000f
#define a3 0.03809f
#define a4 -0.00357f
// constant memory
__constant__ float coef[RADIUS + 1];
void initialData(float *ip, const int size);
void stencilHost(float *in, float *out, int isize);
void checkResult(float *hostRef, float *gpuRef, const int size);
__global__ void stencilGPU(float *in, float *out, const int n);
int main(int argc, char **argv) {
// set up device
int dev = 0;
cudaDeviceProp deviceProp;
CHECK(cudaGetDeviceProperties(&deviceProp, dev));
printf("Using Device %d: %s\n", dev, deviceProp.name);
CHECK(cudaSetDevice(dev));
// set up data size
int isize = 1 << 24;
size_t nBytes = (isize + 2 * RADIUS) * sizeof(float);
printf("array size: %d\n", isize);
// allocate host memory
float *h_in = (float *)malloc(nBytes);
float *h_out = (float *)malloc(nBytes);
float *h_out_gpu = (float *)malloc(nBytes);
initialData(h_in, isize + 2 * RADIUS);
// compute on CPU
stencilHost(h_in, h_out, isize);
// allocate device memory
float *d_in, *d_out;
CHECK(cudaMalloc((float**)&d_in, nBytes));
CHECK(cudaMalloc((float**)&d_out, nBytes));
CHECK(cudaMemcpy(d_in, h_in, nBytes, cudaMemcpyHostToDevice));
// set up constant memory
const float h_coef[] = {a0, a1, a2, a3, a4};
CHECK(cudaMemcpyToSymbol(coef, h_coef, (RADIUS + 1) * sizeof(float)));
// launch CUDA kernel
cudaDeviceProp info;
CHECK(cudaGetDeviceProperties(&info, 0));
dim3 block(BLOCKSIZE);
dim3 grid(info.maxGridSize[0] < isize / block.x ? info.maxGridSize[0] : isize / block.x);
printf("(grid, block) %d,%d \n", grid.x, block.x);
stencilGPU<<<grid, block>>>(d_in + RADIUS, d_out + RADIUS, isize);
CHECK(cudaMemcpy(h_out_gpu, d_out, nBytes, cudaMemcpyDeviceToHost));
checkResult(h_out, h_out_gpu, isize);
// free memory
CHECK(cudaFree(d_in));
CHECK(cudaFree(d_out));
free(h_in);
free(h_out);
free(h_out_gpu);
// reset device
CHECK(cudaDeviceReset());
return 0;
}
/**********CUDA kernels**********/
__global__ void stencilGPU(float *in, float *out, const int n) {
// shared memory
__shared__ float smem[BLOCKSIZE + 2 * RADIUS];
// index to global memory
int idx = blockIdx.x * blockDim.x + threadIdx.x;
while (idx < n) {
int sidx = threadIdx.x + RADIUS; // index to shared memory for stencil calculatioin
smem[sidx] = in[idx]; // read data from global memory into shared memory
if (threadIdx.x < RADIUS) { // read halo part to shared memory
smem[sidx - RADIUS] = in[idx - RADIUS];
smem[sidx + BLOCKSIZE] = in[idx + BLOCKSIZE];
}
__syncthreads();
float tmp = coef[0];
#pragma unroll
for (int i = 1; i <= RADIUS; i++) {
tmp += coef[i] * (smem[sidx + i] - smem[sidx - i]);
}
out[idx] = tmp;
idx += gridDim.x * blockDim.x;
}
}
/**********host functions**********/
void initialData(float *ip, const int size) {
for (int i = 0; i < size; i++) {
ip[i] = (float)(rand() & 0xFF) / 100.0f;
}
}
void stencilHost(float *in, float *out, int isize)
{
for (int i = RADIUS; i <= isize; i++) {
out[i] = a0 + a1 * (in[i + 1] - in[i - 1])
+ a2 * (in[i + 2] - in[i - 2])
+ a3 * (in[i + 3] - in[i - 3])
+ a4 * (in[i + 4] - in[i - 4]);
}
}
void checkResult(float *hostRef, float *gpuRef, const int size) {
double epsilon = 1.0E-6;
for (int i = RADIUS; i < size; i++) {
if (abs(hostRef[i] - gpuRef[i]) > epsilon) {
printf("different on %dth element: host %f gpu %f\n", i, hostRef[i], gpuRef[i]);
break;
}
}
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#define CHECK(call) { \
const hipError_t error = call; \
if (error != hipSuccess) { \
printf("Error: %s:%d, ", __FILE__, __LINE__); \
printf("code: %d, reason: %s\n", error, hipGetErrorString(error)); \
exit(1); \
} \
} \
#define RADIUS 4
#define BLOCKSIZE 128
// coeffecient
#define a0 0.00000f
#define a1 0.80000f
#define a2 -0.20000f
#define a3 0.03809f
#define a4 -0.00357f
// constant memory
__constant__ float coef[RADIUS + 1];
void initialData(float *ip, const int size);
void stencilHost(float *in, float *out, int isize);
void checkResult(float *hostRef, float *gpuRef, const int size);
__global__ void stencilGPU(float *in, float *out, const int n);
int main(int argc, char **argv) {
// set up device
int dev = 0;
hipDeviceProp_t deviceProp;
CHECK(hipGetDeviceProperties(&deviceProp, dev));
printf("Using Device %d: %s\n", dev, deviceProp.name);
CHECK(hipSetDevice(dev));
// set up data size
int isize = 1 << 24;
size_t nBytes = (isize + 2 * RADIUS) * sizeof(float);
printf("array size: %d\n", isize);
// allocate host memory
float *h_in = (float *)malloc(nBytes);
float *h_out = (float *)malloc(nBytes);
float *h_out_gpu = (float *)malloc(nBytes);
initialData(h_in, isize + 2 * RADIUS);
// compute on CPU
stencilHost(h_in, h_out, isize);
// allocate device memory
float *d_in, *d_out;
CHECK(hipMalloc((float**)&d_in, nBytes));
CHECK(hipMalloc((float**)&d_out, nBytes));
CHECK(hipMemcpy(d_in, h_in, nBytes, hipMemcpyHostToDevice));
// set up constant memory
const float h_coef[] = {a0, a1, a2, a3, a4};
CHECK(hipMemcpyToSymbol(HIP_SYMBOL(coef), h_coef, (RADIUS + 1) * sizeof(float)));
// launch CUDA kernel
hipDeviceProp_t info;
CHECK(hipGetDeviceProperties(&info, 0));
dim3 block(BLOCKSIZE);
dim3 grid(info.maxGridSize[0] < isize / block.x ? info.maxGridSize[0] : isize / block.x);
printf("(grid, block) %d,%d \n", grid.x, block.x);
stencilGPU<<<grid, block>>>(d_in + RADIUS, d_out + RADIUS, isize);
CHECK(hipMemcpy(h_out_gpu, d_out, nBytes, hipMemcpyDeviceToHost));
checkResult(h_out, h_out_gpu, isize);
// free memory
CHECK(hipFree(d_in));
CHECK(hipFree(d_out));
free(h_in);
free(h_out);
free(h_out_gpu);
// reset device
CHECK(hipDeviceReset());
return 0;
}
/**********CUDA kernels**********/
__global__ void stencilGPU(float *in, float *out, const int n) {
// shared memory
__shared__ float smem[BLOCKSIZE + 2 * RADIUS];
// index to global memory
int idx = blockIdx.x * blockDim.x + threadIdx.x;
while (idx < n) {
int sidx = threadIdx.x + RADIUS; // index to shared memory for stencil calculatioin
smem[sidx] = in[idx]; // read data from global memory into shared memory
if (threadIdx.x < RADIUS) { // read halo part to shared memory
smem[sidx - RADIUS] = in[idx - RADIUS];
smem[sidx + BLOCKSIZE] = in[idx + BLOCKSIZE];
}
__syncthreads();
float tmp = coef[0];
#pragma unroll
for (int i = 1; i <= RADIUS; i++) {
tmp += coef[i] * (smem[sidx + i] - smem[sidx - i]);
}
out[idx] = tmp;
idx += gridDim.x * blockDim.x;
}
}
/**********host functions**********/
void initialData(float *ip, const int size) {
for (int i = 0; i < size; i++) {
ip[i] = (float)(rand() & 0xFF) / 100.0f;
}
}
void stencilHost(float *in, float *out, int isize)
{
for (int i = RADIUS; i <= isize; i++) {
out[i] = a0 + a1 * (in[i + 1] - in[i - 1])
+ a2 * (in[i + 2] - in[i - 2])
+ a3 * (in[i + 3] - in[i - 3])
+ a4 * (in[i + 4] - in[i - 4]);
}
}
void checkResult(float *hostRef, float *gpuRef, const int size) {
double epsilon = 1.0E-6;
for (int i = RADIUS; i < size; i++) {
if (abs(hostRef[i] - gpuRef[i]) > epsilon) {
printf("different on %dth element: host %f gpu %f\n", i, hostRef[i], gpuRef[i]);
break;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#define CHECK(call) { \
const hipError_t error = call; \
if (error != hipSuccess) { \
printf("Error: %s:%d, ", __FILE__, __LINE__); \
printf("code: %d, reason: %s\n", error, hipGetErrorString(error)); \
exit(1); \
} \
} \
#define RADIUS 4
#define BLOCKSIZE 128
// coeffecient
#define a0 0.00000f
#define a1 0.80000f
#define a2 -0.20000f
#define a3 0.03809f
#define a4 -0.00357f
// constant memory
__constant__ float coef[RADIUS + 1];
void initialData(float *ip, const int size);
void stencilHost(float *in, float *out, int isize);
void checkResult(float *hostRef, float *gpuRef, const int size);
__global__ void stencilGPU(float *in, float *out, const int n);
int main(int argc, char **argv) {
// set up device
int dev = 0;
hipDeviceProp_t deviceProp;
CHECK(hipGetDeviceProperties(&deviceProp, dev));
printf("Using Device %d: %s\n", dev, deviceProp.name);
CHECK(hipSetDevice(dev));
// set up data size
int isize = 1 << 24;
size_t nBytes = (isize + 2 * RADIUS) * sizeof(float);
printf("array size: %d\n", isize);
// allocate host memory
float *h_in = (float *)malloc(nBytes);
float *h_out = (float *)malloc(nBytes);
float *h_out_gpu = (float *)malloc(nBytes);
initialData(h_in, isize + 2 * RADIUS);
// compute on CPU
stencilHost(h_in, h_out, isize);
// allocate device memory
float *d_in, *d_out;
CHECK(hipMalloc((float**)&d_in, nBytes));
CHECK(hipMalloc((float**)&d_out, nBytes));
CHECK(hipMemcpy(d_in, h_in, nBytes, hipMemcpyHostToDevice));
// set up constant memory
const float h_coef[] = {a0, a1, a2, a3, a4};
CHECK(hipMemcpyToSymbol(HIP_SYMBOL(coef), h_coef, (RADIUS + 1) * sizeof(float)));
// launch CUDA kernel
hipDeviceProp_t info;
CHECK(hipGetDeviceProperties(&info, 0));
dim3 block(BLOCKSIZE);
dim3 grid(info.maxGridSize[0] < isize / block.x ? info.maxGridSize[0] : isize / block.x);
printf("(grid, block) %d,%d \n", grid.x, block.x);
stencilGPU<<<grid, block>>>(d_in + RADIUS, d_out + RADIUS, isize);
CHECK(hipMemcpy(h_out_gpu, d_out, nBytes, hipMemcpyDeviceToHost));
checkResult(h_out, h_out_gpu, isize);
// free memory
CHECK(hipFree(d_in));
CHECK(hipFree(d_out));
free(h_in);
free(h_out);
free(h_out_gpu);
// reset device
CHECK(hipDeviceReset());
return 0;
}
/**********CUDA kernels**********/
__global__ void stencilGPU(float *in, float *out, const int n) {
// shared memory
__shared__ float smem[BLOCKSIZE + 2 * RADIUS];
// index to global memory
int idx = blockIdx.x * blockDim.x + threadIdx.x;
while (idx < n) {
int sidx = threadIdx.x + RADIUS; // index to shared memory for stencil calculatioin
smem[sidx] = in[idx]; // read data from global memory into shared memory
if (threadIdx.x < RADIUS) { // read halo part to shared memory
smem[sidx - RADIUS] = in[idx - RADIUS];
smem[sidx + BLOCKSIZE] = in[idx + BLOCKSIZE];
}
__syncthreads();
float tmp = coef[0];
#pragma unroll
for (int i = 1; i <= RADIUS; i++) {
tmp += coef[i] * (smem[sidx + i] - smem[sidx - i]);
}
out[idx] = tmp;
idx += gridDim.x * blockDim.x;
}
}
/**********host functions**********/
void initialData(float *ip, const int size) {
for (int i = 0; i < size; i++) {
ip[i] = (float)(rand() & 0xFF) / 100.0f;
}
}
void stencilHost(float *in, float *out, int isize)
{
for (int i = RADIUS; i <= isize; i++) {
out[i] = a0 + a1 * (in[i + 1] - in[i - 1])
+ a2 * (in[i + 2] - in[i - 2])
+ a3 * (in[i + 3] - in[i - 3])
+ a4 * (in[i + 4] - in[i - 4]);
}
}
void checkResult(float *hostRef, float *gpuRef, const int size) {
double epsilon = 1.0E-6;
for (int i = RADIUS; i < size; i++) {
if (abs(hostRef[i] - gpuRef[i]) > epsilon) {
printf("different on %dth element: host %f gpu %f\n", i, hostRef[i], gpuRef[i]);
break;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10stencilGPUPfS_i
.globl _Z10stencilGPUPfS_i
.p2align 8
.type _Z10stencilGPUPfS_i,@function
_Z10stencilGPUPfS_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s8, s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s12, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s12, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s13, s[2:3], 0x0
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, coef@rel32@lo+4
s_addc_u32 s1, s1, coef@rel32@hi+12
s_getpc_b64 s[10:11]
s_add_u32 s10, s10, coef@rel32@lo+8
s_addc_u32 s11, s11, coef@rel32@hi+16
s_getpc_b64 s[14:15]
s_add_u32 s14, s14, coef@rel32@lo+12
s_addc_u32 s15, s15, coef@rel32@hi+20
s_getpc_b64 s[16:17]
s_add_u32 s16, s16, coef@rel32@lo+16
s_addc_u32 s17, s17, coef@rel32@hi+24
s_getpc_b64 s[18:19]
s_add_u32 s18, s18, coef@rel32@lo+20
s_addc_u32 s19, s19, coef@rel32@hi+28
s_clause 0x4
s_load_b32 s2, s[0:1], 0x0
s_load_b32 s3, s[10:11], 0x0
s_load_b32 s9, s[14:15], 0x0
s_load_b32 s10, s[16:17], 0x0
s_load_b32 s11, s[18:19], 0x0
v_lshlrev_b32_e32 v6, 2, v0
v_cmp_gt_u32_e32 vcc_lo, 4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v7, 16, v6
v_add_nc_u32_e32 v0, 0x210, v6
v_add_nc_u32_e32 v8, 20, v6
v_add_nc_u32_e32 v9, 12, v6
v_add_nc_u32_e32 v10, 24, v6
v_add_nc_u32_e32 v11, 8, v6
v_add_nc_u32_e32 v12, 28, v6
v_add_nc_u32_e32 v13, 4, v6
v_add_nc_u32_e32 v14, 32, v6
s_waitcnt lgkmcnt(0)
s_mul_i32 s12, s13, s12
s_mov_b32 s13, 0
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
ds_load_b32 v4, v8
ds_load_b32 v5, v9
ds_load_b32 v15, v10
ds_load_b32 v16, v11
ds_load_b32 v17, v12
ds_load_b32 v18, v13
ds_load_b32 v19, v14
ds_load_b32 v20, v6
v_add_co_u32 v2, s1, s6, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s1, s7, v3, s1
s_waitcnt lgkmcnt(4)
v_dual_sub_f32 v4, v4, v5 :: v_dual_sub_f32 v5, v15, v16
v_fma_f32 v4, s3, v4, s2
s_waitcnt lgkmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_dual_sub_f32 v15, v17, v18 :: v_dual_fmac_f32 v4, s9, v5
v_add_nc_u32_e32 v1, s12, v1
s_waitcnt lgkmcnt(0)
v_dual_sub_f32 v5, v19, v20 :: v_dual_fmac_f32 v4, s10, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_i32_e64 s0, s8, v1
v_fmac_f32_e32 v4, s11, v5
s_delay_alu instid0(VALU_DEP_2)
s_or_b32 s13, s0, s13
global_store_b32 v[2:3], v4, off
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execz .LBB0_5
.LBB0_3:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v4, s0, s4, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s0, s5, v3, s0
global_load_b32 v15, v[4:5], off
s_waitcnt vmcnt(0)
ds_store_b32 v7, v15
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_2
s_clause 0x1
global_load_b32 v15, v[4:5], off offset:-16
global_load_b32 v4, v[4:5], off offset:512
s_waitcnt vmcnt(1)
ds_store_b32 v6, v15
s_waitcnt vmcnt(0)
ds_store_b32 v0, v4
s_branch .LBB0_2
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10stencilGPUPfS_i
.amdhsa_group_segment_fixed_size 544
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10stencilGPUPfS_i, .Lfunc_end0-_Z10stencilGPUPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected coef
.type coef,@object
.section .bss,"aw",@nobits
.globl coef
.p2align 4, 0x0
coef:
.zero 20
.size coef, 20
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym coef
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 544
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10stencilGPUPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z10stencilGPUPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#define CHECK(call) { \
const hipError_t error = call; \
if (error != hipSuccess) { \
printf("Error: %s:%d, ", __FILE__, __LINE__); \
printf("code: %d, reason: %s\n", error, hipGetErrorString(error)); \
exit(1); \
} \
} \
#define RADIUS 4
#define BLOCKSIZE 128
// coeffecient
#define a0 0.00000f
#define a1 0.80000f
#define a2 -0.20000f
#define a3 0.03809f
#define a4 -0.00357f
// constant memory
__constant__ float coef[RADIUS + 1];
void initialData(float *ip, const int size);
void stencilHost(float *in, float *out, int isize);
void checkResult(float *hostRef, float *gpuRef, const int size);
__global__ void stencilGPU(float *in, float *out, const int n);
int main(int argc, char **argv) {
// set up device
int dev = 0;
hipDeviceProp_t deviceProp;
CHECK(hipGetDeviceProperties(&deviceProp, dev));
printf("Using Device %d: %s\n", dev, deviceProp.name);
CHECK(hipSetDevice(dev));
// set up data size
int isize = 1 << 24;
size_t nBytes = (isize + 2 * RADIUS) * sizeof(float);
printf("array size: %d\n", isize);
// allocate host memory
float *h_in = (float *)malloc(nBytes);
float *h_out = (float *)malloc(nBytes);
float *h_out_gpu = (float *)malloc(nBytes);
initialData(h_in, isize + 2 * RADIUS);
// compute on CPU
stencilHost(h_in, h_out, isize);
// allocate device memory
float *d_in, *d_out;
CHECK(hipMalloc((float**)&d_in, nBytes));
CHECK(hipMalloc((float**)&d_out, nBytes));
CHECK(hipMemcpy(d_in, h_in, nBytes, hipMemcpyHostToDevice));
// set up constant memory
const float h_coef[] = {a0, a1, a2, a3, a4};
CHECK(hipMemcpyToSymbol(HIP_SYMBOL(coef), h_coef, (RADIUS + 1) * sizeof(float)));
// launch CUDA kernel
hipDeviceProp_t info;
CHECK(hipGetDeviceProperties(&info, 0));
dim3 block(BLOCKSIZE);
dim3 grid(info.maxGridSize[0] < isize / block.x ? info.maxGridSize[0] : isize / block.x);
printf("(grid, block) %d,%d \n", grid.x, block.x);
stencilGPU<<<grid, block>>>(d_in + RADIUS, d_out + RADIUS, isize);
CHECK(hipMemcpy(h_out_gpu, d_out, nBytes, hipMemcpyDeviceToHost));
checkResult(h_out, h_out_gpu, isize);
// free memory
CHECK(hipFree(d_in));
CHECK(hipFree(d_out));
free(h_in);
free(h_out);
free(h_out_gpu);
// reset device
CHECK(hipDeviceReset());
return 0;
}
/**********CUDA kernels**********/
__global__ void stencilGPU(float *in, float *out, const int n) {
// shared memory
__shared__ float smem[BLOCKSIZE + 2 * RADIUS];
// index to global memory
int idx = blockIdx.x * blockDim.x + threadIdx.x;
while (idx < n) {
int sidx = threadIdx.x + RADIUS; // index to shared memory for stencil calculatioin
smem[sidx] = in[idx]; // read data from global memory into shared memory
if (threadIdx.x < RADIUS) { // read halo part to shared memory
smem[sidx - RADIUS] = in[idx - RADIUS];
smem[sidx + BLOCKSIZE] = in[idx + BLOCKSIZE];
}
__syncthreads();
float tmp = coef[0];
#pragma unroll
for (int i = 1; i <= RADIUS; i++) {
tmp += coef[i] * (smem[sidx + i] - smem[sidx - i]);
}
out[idx] = tmp;
idx += gridDim.x * blockDim.x;
}
}
/**********host functions**********/
void initialData(float *ip, const int size) {
for (int i = 0; i < size; i++) {
ip[i] = (float)(rand() & 0xFF) / 100.0f;
}
}
void stencilHost(float *in, float *out, int isize)
{
for (int i = RADIUS; i <= isize; i++) {
out[i] = a0 + a1 * (in[i + 1] - in[i - 1])
+ a2 * (in[i + 2] - in[i - 2])
+ a3 * (in[i + 3] - in[i - 3])
+ a4 * (in[i + 4] - in[i - 4]);
}
}
void checkResult(float *hostRef, float *gpuRef, const int size) {
double epsilon = 1.0E-6;
for (int i = RADIUS; i < size; i++) {
if (abs(hostRef[i] - gpuRef[i]) > epsilon) {
printf("different on %dth element: host %f gpu %f\n", i, hostRef[i], gpuRef[i]);
break;
}
}
} | .text
.file "stencilConstantMem.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x42c80000 # float 100
.LCPI0_1:
.long 0x3f4ccccd # float 0.800000011
.LCPI0_2:
.long 0xbe4ccccd # float -0.200000003
.LCPI0_3:
.long 0x3d1c0443 # float 0.0380900018
.LCPI0_4:
.long 0xbb69f6a9 # float -0.00356999994
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI0_5:
.long 0x00000000 # float 0
.long 0x3f4ccccd # float 0.800000011
.long 0xbe4ccccd # float -0.200000003
.long 0x3d1c0443 # float 0.0380900018
.LCPI0_6:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI0_7:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $3104, %rsp # imm = 0xC20
.cfi_def_cfa_offset 3152
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 1632(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
jne .LBB0_1
# %bb.3:
leaq 1632(%rsp), %rdx
movl $.L.str.3, %edi
xorl %esi, %esi
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB0_4
# %bb.5:
xorl %r12d, %r12d
movl $.L.str.4, %edi
movl $16777216, %esi # imm = 0x1000000
xorl %eax, %eax
callq printf
movl $67108896, %edi # imm = 0x4000020
callq malloc
movq %rax, %rbx
movl $67108896, %edi # imm = 0x4000020
callq malloc
movq %rax, %r14
movl $67108896, %edi # imm = 0x4000020
callq malloc
movq %rax, %r15
.p2align 4, 0x90
.LBB0_6: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
divss .LCPI0_0(%rip), %xmm0
movss %xmm0, (%rbx,%r12,4)
incq %r12
cmpq $16777224, %r12 # imm = 0x1000008
jne .LBB0_6
# %bb.7: # %.lr.ph.i89.preheader
movl $8, %eax
movss .LCPI0_1(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorps %xmm1, %xmm1
movss .LCPI0_2(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss .LCPI0_3(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero
movss .LCPI0_4(%rip), %xmm4 # xmm4 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB0_8: # %.lr.ph.i89
# =>This Inner Loop Header: Depth=1
movss -12(%rbx,%rax,4), %xmm5 # xmm5 = mem[0],zero,zero,zero
subss -20(%rbx,%rax,4), %xmm5
movss -8(%rbx,%rax,4), %xmm6 # xmm6 = mem[0],zero,zero,zero
mulss %xmm0, %xmm5
subss -24(%rbx,%rax,4), %xmm6
addss %xmm1, %xmm5
mulss %xmm2, %xmm6
addss %xmm5, %xmm6
movss -4(%rbx,%rax,4), %xmm5 # xmm5 = mem[0],zero,zero,zero
subss -28(%rbx,%rax,4), %xmm5
mulss %xmm3, %xmm5
addss %xmm6, %xmm5
movss (%rbx,%rax,4), %xmm6 # xmm6 = mem[0],zero,zero,zero
subss -32(%rbx,%rax,4), %xmm6
mulss %xmm4, %xmm6
addss %xmm5, %xmm6
movss %xmm6, -16(%r14,%rax,4)
incq %rax
cmpq $16777221, %rax # imm = 0x1000005
jne .LBB0_8
# %bb.9: # %_Z11stencilHostPfS_i.exit
leaq 16(%rsp), %rdi
movl $67108896, %esi # imm = 0x4000020
callq hipMalloc
testl %eax, %eax
jne .LBB0_10
# %bb.11:
leaq 8(%rsp), %rdi
movl $67108896, %esi # imm = 0x4000020
callq hipMalloc
testl %eax, %eax
jne .LBB0_12
# %bb.13:
movq 16(%rsp), %rdi
movl $67108896, %edx # imm = 0x4000020
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_14
# %bb.15:
movaps .LCPI0_5(%rip), %xmm0 # xmm0 = [0.0E+0,8.00000011E-1,-2.00000003E-1,3.80900018E-2]
movaps %xmm0, 128(%rsp)
movl $-1150683479, 144(%rsp) # imm = 0xBB69F6A9
leaq 128(%rsp), %rsi
movl $coef, %edi
movl $20, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
testl %eax, %eax
jne .LBB0_16
# %bb.17:
leaq 160(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
jne .LBB0_18
# %bb.19:
movl 496(%rsp), %eax
cmpl $131072, %eax # imm = 0x20000
movl $131072, %esi # imm = 0x20000
cmovbl %eax, %esi
movabsq $4294967296, %r12 # imm = 0x100000000
leaq (%rsi,%r12), %r13
movl $.L.str.5, %edi
# kill: def $esi killed $esi killed $rsi
movl $128, %edx
xorl %eax, %eax
callq printf
orq $128, %r12
movq %r13, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_21
# %bb.20:
movq 16(%rsp), %rax
addq $16, %rax
movq 8(%rsp), %rcx
addq $16, %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $16777216, 28(%rsp) # imm = 0x1000000
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10stencilGPUPfS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_21:
movq 8(%rsp), %rsi
movl $67108896, %edx # imm = 0x4000020
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_33
# %bb.22: # %.lr.ph.i93.preheader
movl $4, %esi
movaps .LCPI0_6(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN]
movsd .LCPI0_7(%rip), %xmm1 # xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB0_23: # %.lr.ph.i93
# =>This Inner Loop Header: Depth=1
movss (%r14,%rsi,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss (%r15,%rsi,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
movaps %xmm2, %xmm4
subss %xmm3, %xmm4
andps %xmm0, %xmm4
cvtss2sd %xmm4, %xmm4
ucomisd %xmm1, %xmm4
ja .LBB0_24
# %bb.25: # in Loop: Header=BB0_23 Depth=1
incq %rsi
cmpq $16777216, %rsi # imm = 0x1000000
jne .LBB0_23
jmp .LBB0_26
.LBB0_24:
xorps %xmm0, %xmm0
cvtss2sd %xmm2, %xmm0
xorps %xmm1, %xmm1
cvtss2sd %xmm3, %xmm1
movl $.L.str.6, %edi
# kill: def $esi killed $esi killed $rsi
movb $2, %al
callq printf
.LBB0_26: # %_Z11checkResultPfS_i.exit
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB0_27
# %bb.28:
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB0_29
# %bb.30:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
callq hipDeviceReset
testl %eax, %eax
jne .LBB0_31
# %bb.32:
xorl %eax, %eax
addq $3104, %rsp # imm = 0xC20
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_1:
.cfi_def_cfa_offset 3152
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $36, %edx
jmp .LBB0_2
.LBB0_4:
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $38, %edx
jmp .LBB0_2
.LBB0_10:
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $57, %edx
jmp .LBB0_2
.LBB0_12:
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $58, %edx
jmp .LBB0_2
.LBB0_14:
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $59, %edx
jmp .LBB0_2
.LBB0_16:
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $63, %edx
jmp .LBB0_2
.LBB0_18:
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $67, %edx
jmp .LBB0_2
.LBB0_33:
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $73, %edx
jmp .LBB0_2
.LBB0_27:
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $77, %edx
jmp .LBB0_2
.LBB0_29:
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $78, %edx
jmp .LBB0_2
.LBB0_31:
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $84, %edx
.LBB0_2:
movl %eax, %ebx
xorl %eax, %eax
callq printf
movl %ebx, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z11initialDataPfi
.LCPI1_0:
.long 0x42c80000 # float 100
.text
.globl _Z11initialDataPfi
.p2align 4, 0x90
.type _Z11initialDataPfi,@function
_Z11initialDataPfi: # @_Z11initialDataPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
divss .LCPI1_0(%rip), %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z11initialDataPfi, .Lfunc_end1-_Z11initialDataPfi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z11stencilHostPfS_i
.LCPI2_0:
.long 0x3f4ccccd # float 0.800000011
.LCPI2_1:
.long 0xbe4ccccd # float -0.200000003
.LCPI2_2:
.long 0x3d1c0443 # float 0.0380900018
.LCPI2_3:
.long 0xbb69f6a9 # float -0.00356999994
.text
.globl _Z11stencilHostPfS_i
.p2align 4, 0x90
.type _Z11stencilHostPfS_i,@function
_Z11stencilHostPfS_i: # @_Z11stencilHostPfS_i
.cfi_startproc
# %bb.0:
cmpl $4, %edx
jl .LBB2_3
# %bb.1: # %.lr.ph.preheader
movl %edx, %eax
addq $-3, %rax
xorl %ecx, %ecx
movss .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorps %xmm1, %xmm1
movss .LCPI2_1(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss .LCPI2_2(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero
movss .LCPI2_3(%rip), %xmm4 # xmm4 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss 20(%rdi,%rcx,4), %xmm5 # xmm5 = mem[0],zero,zero,zero
subss 12(%rdi,%rcx,4), %xmm5
movss 24(%rdi,%rcx,4), %xmm6 # xmm6 = mem[0],zero,zero,zero
mulss %xmm0, %xmm5
subss 8(%rdi,%rcx,4), %xmm6
addss %xmm1, %xmm5
mulss %xmm2, %xmm6
addss %xmm5, %xmm6
movss 28(%rdi,%rcx,4), %xmm5 # xmm5 = mem[0],zero,zero,zero
subss 4(%rdi,%rcx,4), %xmm5
mulss %xmm3, %xmm5
addss %xmm6, %xmm5
movss 32(%rdi,%rcx,4), %xmm6 # xmm6 = mem[0],zero,zero,zero
subss (%rdi,%rcx,4), %xmm6
mulss %xmm4, %xmm6
addss %xmm5, %xmm6
movss %xmm6, 16(%rsi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB2_2
.LBB2_3: # %._crit_edge
retq
.Lfunc_end2:
.size _Z11stencilHostPfS_i, .Lfunc_end2-_Z11stencilHostPfS_i
.cfi_endproc
# -- End function
.globl _Z25__device_stub__stencilGPUPfS_i # -- Begin function _Z25__device_stub__stencilGPUPfS_i
.p2align 4, 0x90
.type _Z25__device_stub__stencilGPUPfS_i,@function
_Z25__device_stub__stencilGPUPfS_i: # @_Z25__device_stub__stencilGPUPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10stencilGPUPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z25__device_stub__stencilGPUPfS_i, .Lfunc_end3-_Z25__device_stub__stencilGPUPfS_i
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z11checkResultPfS_i
.LCPI4_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI4_1:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z11checkResultPfS_i
.p2align 4, 0x90
.type _Z11checkResultPfS_i,@function
_Z11checkResultPfS_i: # @_Z11checkResultPfS_i
.cfi_startproc
# %bb.0:
cmpl $5, %edx
jl .LBB4_4
# %bb.1: # %.lr.ph.preheader
movl %edx, %ecx
movl $4, %eax
movaps .LCPI4_0(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN]
movsd .LCPI4_1(%rip), %xmm1 # xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rdi,%rax,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss (%rsi,%rax,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
movaps %xmm2, %xmm4
subss %xmm3, %xmm4
andps %xmm0, %xmm4
cvtss2sd %xmm4, %xmm4
ucomisd %xmm1, %xmm4
ja .LBB4_5
# %bb.3: # in Loop: Header=BB4_2 Depth=1
incq %rax
cmpq %rax, %rcx
jne .LBB4_2
.LBB4_4: # %.loopexit
retq
.LBB4_5:
xorps %xmm0, %xmm0
cvtss2sd %xmm2, %xmm0
xorps %xmm1, %xmm1
cvtss2sd %xmm3, %xmm1
movl $.L.str.6, %edi
movl %eax, %esi
movb $2, %al
jmp printf # TAILCALL
.Lfunc_end4:
.size _Z11checkResultPfS_i, .Lfunc_end4-_Z11checkResultPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10stencilGPUPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $coef, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $20, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type coef,@object # @coef
.local coef
.comm coef,20,16
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error: %s:%d, "
.size .L.str, 15
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/SaoYan/Learning_CUDA/master/Ch5/stencilConstantMem.hip"
.size .L.str.1, 112
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "code: %d, reason: %s\n"
.size .L.str.2, 22
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Using Device %d: %s\n"
.size .L.str.3, 21
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "array size: %d\n"
.size .L.str.4, 16
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "(grid, block) %d,%d \n"
.size .L.str.5, 22
.type _Z10stencilGPUPfS_i,@object # @_Z10stencilGPUPfS_i
.section .rodata,"a",@progbits
.globl _Z10stencilGPUPfS_i
.p2align 3, 0x0
_Z10stencilGPUPfS_i:
.quad _Z25__device_stub__stencilGPUPfS_i
.size _Z10stencilGPUPfS_i, 8
.type .L.str.6,@object # @.str.6
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.6:
.asciz "different on %dth element: host %f gpu %f\n"
.size .L.str.6, 43
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10stencilGPUPfS_i"
.size .L__unnamed_1, 20
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "coef"
.size .L__unnamed_2, 5
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__stencilGPUPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym coef
.addrsig_sym _Z10stencilGPUPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10stencilGPUPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R3, c[0x0][0x0], R0 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ISETP.GT.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe20003f04070 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ MOV R4, R2 ; /* 0x0000000200047202 */
/* 0x000fe40000000f00 */
/*0090*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x001fd400000001ff */
/*00a0*/ IMAD.WIDE R2, R4, R3, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fca00078e0203 */
/*00b0*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x0000a8000c1e1900 */
/*00c0*/ @!P0 LDG.E R7, [R2.64+-0x10] ; /* 0xfffff00402078981 */
/* 0x0000e8000c1e1900 */
/*00d0*/ @!P0 LDG.E R9, [R2.64+0x200] ; /* 0x0002000402098981 */
/* 0x000122000c1e1900 */
/*00e0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*00f0*/ LEA R2, P1, R4, c[0x0][0x168], 0x2 ; /* 0x00005a0004027a11 */
/* 0x001fc400078210ff */
/*0100*/ STS [R0.X4+0x10], R5 ; /* 0x0000100500007388 */
/* 0x004fe80000004800 */
/*0110*/ @!P0 STS [R0.X4], R7 ; /* 0x0000000700008388 */
/* 0x0081e80000004800 */
/*0120*/ @!P0 STS [R0.X4+0x210], R9 ; /* 0x0002100900008388 */
/* 0x010fe80000004800 */
/*0130*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0140*/ MOV R7, c[0x3][0x4] ; /* 0x00c0010000077a02 */
/* 0x001fca0000000f00 */
/*0150*/ LDS R6, [R0.X4+0xc] ; /* 0x00000c0000067984 */
/* 0x000fe80000004800 */
/*0160*/ LDS R11, [R0.X4+0x14] ; /* 0x00001400000b7984 */
/* 0x000e280000004800 */
/*0170*/ LDS R8, [R0.X4+0x8] ; /* 0x0000080000087984 */
/* 0x000fe80000004800 */
/*0180*/ LDS R13, [R0.X4+0x18] ; /* 0x00001800000d7984 */
/* 0x000e680000004800 */
/*0190*/ LDS R10, [R0.X4+0x4] ; /* 0x00000400000a7984 */
/* 0x000fe80000004800 */
/*01a0*/ LDS R3, [R0.X4+0x1c] ; /* 0x00001c0000037984 */
/* 0x000ea80000004800 */
/*01b0*/ LDS R5, [R0.X4] ; /* 0x0000000000057984 */
/* 0x000fe80000004800 */
/*01c0*/ LDS R12, [R0.X4+0x20] ; /* 0x00002000000c7984 */
/* 0x000ee20000004800 */
/*01d0*/ FADD R6, -R6, R11 ; /* 0x0000000b06067221 */
/* 0x001fc80000000100 */
/*01e0*/ FFMA R6, R6, R7, c[0x3][0x0] ; /* 0x00c0000006067623 */
/* 0x000fe20000000007 */
/*01f0*/ MOV R7, c[0x0][0xc] ; /* 0x0000030000077a02 */
/* 0x000fe20000000f00 */
/*0200*/ FADD R13, -R8, R13 ; /* 0x0000000d080d7221 */
/* 0x002fc80000000100 */
/*0210*/ FFMA R6, R13, c[0x3][0x8], R6 ; /* 0x00c002000d067a23 */
/* 0x000fe40000000006 */
/*0220*/ FADD R3, -R10, R3 ; /* 0x000000030a037221 */
/* 0x004fc80000000100 */
/*0230*/ FFMA R6, R3, c[0x3][0xc], R6 ; /* 0x00c0030003067a23 */
/* 0x000fe20000000006 */
/*0240*/ SHF.R.S32.HI R3, RZ, 0x1f, R4 ; /* 0x0000001fff037819 */
/* 0x000fe20000011404 */
/*0250*/ FADD R5, -R5, R12 ; /* 0x0000000c05057221 */
/* 0x008fc60000000100 */
/*0260*/ LEA.HI.X R3, R4, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0004037a11 */
/* 0x000fe200008f1403 */
/*0270*/ IMAD R4, R7, c[0x0][0x0], R4 ; /* 0x0000000007047a24 */
/* 0x000fe400078e0204 */
/*0280*/ FFMA R5, R5, c[0x3][0x10], R6 ; /* 0x00c0040005057a23 */
/* 0x000fc60000000006 */
/*0290*/ ISETP.GE.AND P1, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fe40003f26270 */
/*02a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001f6000c101904 */
/*02b0*/ @!P1 BRA 0x90 ; /* 0xfffffdd000009947 */
/* 0x000fea000383ffff */
/*02c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02d0*/ BRA 0x2d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10stencilGPUPfS_i
.globl _Z10stencilGPUPfS_i
.p2align 8
.type _Z10stencilGPUPfS_i,@function
_Z10stencilGPUPfS_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s8, s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s12, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s12, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s13, s[2:3], 0x0
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, coef@rel32@lo+4
s_addc_u32 s1, s1, coef@rel32@hi+12
s_getpc_b64 s[10:11]
s_add_u32 s10, s10, coef@rel32@lo+8
s_addc_u32 s11, s11, coef@rel32@hi+16
s_getpc_b64 s[14:15]
s_add_u32 s14, s14, coef@rel32@lo+12
s_addc_u32 s15, s15, coef@rel32@hi+20
s_getpc_b64 s[16:17]
s_add_u32 s16, s16, coef@rel32@lo+16
s_addc_u32 s17, s17, coef@rel32@hi+24
s_getpc_b64 s[18:19]
s_add_u32 s18, s18, coef@rel32@lo+20
s_addc_u32 s19, s19, coef@rel32@hi+28
s_clause 0x4
s_load_b32 s2, s[0:1], 0x0
s_load_b32 s3, s[10:11], 0x0
s_load_b32 s9, s[14:15], 0x0
s_load_b32 s10, s[16:17], 0x0
s_load_b32 s11, s[18:19], 0x0
v_lshlrev_b32_e32 v6, 2, v0
v_cmp_gt_u32_e32 vcc_lo, 4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v7, 16, v6
v_add_nc_u32_e32 v0, 0x210, v6
v_add_nc_u32_e32 v8, 20, v6
v_add_nc_u32_e32 v9, 12, v6
v_add_nc_u32_e32 v10, 24, v6
v_add_nc_u32_e32 v11, 8, v6
v_add_nc_u32_e32 v12, 28, v6
v_add_nc_u32_e32 v13, 4, v6
v_add_nc_u32_e32 v14, 32, v6
s_waitcnt lgkmcnt(0)
s_mul_i32 s12, s13, s12
s_mov_b32 s13, 0
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
ds_load_b32 v4, v8
ds_load_b32 v5, v9
ds_load_b32 v15, v10
ds_load_b32 v16, v11
ds_load_b32 v17, v12
ds_load_b32 v18, v13
ds_load_b32 v19, v14
ds_load_b32 v20, v6
v_add_co_u32 v2, s1, s6, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s1, s7, v3, s1
s_waitcnt lgkmcnt(4)
v_dual_sub_f32 v4, v4, v5 :: v_dual_sub_f32 v5, v15, v16
v_fma_f32 v4, s3, v4, s2
s_waitcnt lgkmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_dual_sub_f32 v15, v17, v18 :: v_dual_fmac_f32 v4, s9, v5
v_add_nc_u32_e32 v1, s12, v1
s_waitcnt lgkmcnt(0)
v_dual_sub_f32 v5, v19, v20 :: v_dual_fmac_f32 v4, s10, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_i32_e64 s0, s8, v1
v_fmac_f32_e32 v4, s11, v5
s_delay_alu instid0(VALU_DEP_2)
s_or_b32 s13, s0, s13
global_store_b32 v[2:3], v4, off
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execz .LBB0_5
.LBB0_3:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v4, s0, s4, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s0, s5, v3, s0
global_load_b32 v15, v[4:5], off
s_waitcnt vmcnt(0)
ds_store_b32 v7, v15
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_2
s_clause 0x1
global_load_b32 v15, v[4:5], off offset:-16
global_load_b32 v4, v[4:5], off offset:512
s_waitcnt vmcnt(1)
ds_store_b32 v6, v15
s_waitcnt vmcnt(0)
ds_store_b32 v0, v4
s_branch .LBB0_2
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10stencilGPUPfS_i
.amdhsa_group_segment_fixed_size 544
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10stencilGPUPfS_i, .Lfunc_end0-_Z10stencilGPUPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected coef
.type coef,@object
.section .bss,"aw",@nobits
.globl coef
.p2align 4, 0x0
coef:
.zero 20
.size coef, 20
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym coef
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 544
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10stencilGPUPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z10stencilGPUPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f7894_00000000-6_stencilConstantMem.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initialDataPfi
.type _Z11initialDataPfi, @function
_Z11initialDataPfi:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
movzbl %al, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
divss .LC0(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2058:
.size _Z11initialDataPfi, .-_Z11initialDataPfi
.globl _Z11stencilHostPfS_i
.type _Z11stencilHostPfS_i, @function
_Z11stencilHostPfS_i:
.LFB2059:
.cfi_startproc
endbr64
cmpl $3, %edx
jle .L11
movq %rdi, %rax
addq $16, %rsi
leal -4(%rdx), %edx
leaq 4(%rdi,%rdx,4), %rdx
movss .LC1(%rip), %xmm6
pxor %xmm5, %xmm5
movss .LC3(%rip), %xmm4
movss .LC4(%rip), %xmm3
movss .LC5(%rip), %xmm2
.L13:
movss 20(%rax), %xmm0
subss 12(%rax), %xmm0
mulss %xmm6, %xmm0
addss %xmm5, %xmm0
movss 24(%rax), %xmm1
subss 8(%rax), %xmm1
mulss %xmm4, %xmm1
addss %xmm1, %xmm0
movss 28(%rax), %xmm1
subss 4(%rax), %xmm1
mulss %xmm3, %xmm1
addss %xmm1, %xmm0
movss 32(%rax), %xmm1
subss (%rax), %xmm1
mulss %xmm2, %xmm1
addss %xmm1, %xmm0
movss %xmm0, (%rsi)
addq $4, %rax
addq $4, %rsi
cmpq %rdx, %rax
jne .L13
.L11:
ret
.cfi_endproc
.LFE2059:
.size _Z11stencilHostPfS_i, .-_Z11stencilHostPfS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC8:
.string "different on %dth element: host %f gpu %f\n"
.text
.globl _Z11checkResultPfS_i
.type _Z11checkResultPfS_i, @function
_Z11checkResultPfS_i:
.LFB2060:
.cfi_startproc
endbr64
cmpl $4, %edx
jle .L24
movl %edx, %eax
movl $4, %edx
movss .LC6(%rip), %xmm4
movsd .LC7(%rip), %xmm3
.L19:
movss (%rdi,%rdx,4), %xmm0
movss (%rsi,%rdx,4), %xmm1
movaps %xmm0, %xmm2
subss %xmm1, %xmm2
andps %xmm4, %xmm2
cvtss2sd %xmm2, %xmm2
comisd %xmm3, %xmm2
ja .L27
addq $1, %rdx
cmpq %rax, %rdx
jne .L19
ret
.L27:
subq $8, %rsp
.cfi_def_cfa_offset 16
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L24:
ret
.cfi_endproc
.LFE2060:
.size _Z11checkResultPfS_i, .-_Z11checkResultPfS_i
.globl _Z33__device_stub__Z10stencilGPUPfS_iPfS_i
.type _Z33__device_stub__Z10stencilGPUPfS_iPfS_i, @function
_Z33__device_stub__Z10stencilGPUPfS_iPfS_i:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L32
.L28:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L33
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10stencilGPUPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L28
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z33__device_stub__Z10stencilGPUPfS_iPfS_i, .-_Z33__device_stub__Z10stencilGPUPfS_iPfS_i
.globl _Z10stencilGPUPfS_i
.type _Z10stencilGPUPfS_i, @function
_Z10stencilGPUPfS_i:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10stencilGPUPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z10stencilGPUPfS_i, .-_Z10stencilGPUPfS_i
.section .rodata.str1.8
.align 8
.LC9:
.string "/home/ubuntu/Datasets/stackv2/train-structured/SaoYan/Learning_CUDA/master/Ch5/stencilConstantMem.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC10:
.string "Error: %s:%d, "
.LC11:
.string "code: %d, reason: %s\n"
.LC12:
.string "Using Device %d: %s\n"
.LC13:
.string "array size: %d\n"
.LC14:
.string "(grid, block) %d,%d \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $2168, %rsp
.cfi_def_cfa_offset 2208
movq %fs:40, %rax
movq %rax, 2152(%rsp)
xorl %eax, %eax
leaq 80(%rsp), %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
testl %eax, %eax
jne .L51
leaq 80(%rsp), %rcx
movl $0, %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call cudaSetDevice@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L52
movl $16777216, %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $67108896, %edi
call malloc@PLT
movq %rax, %rbx
movl $67108896, %edi
call malloc@PLT
movq %rax, %rbp
movl $67108896, %edi
call malloc@PLT
movq %rax, %r12
movl $16777224, %esi
movq %rbx, %rdi
call _Z11initialDataPfi
movl $16777216, %edx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z11stencilHostPfS_i
leaq 8(%rsp), %rdi
movl $67108896, %esi
call cudaMalloc@PLT
movl %eax, %r13d
testl %eax, %eax
jne .L53
leaq 16(%rsp), %rdi
movl $67108896, %esi
call cudaMalloc@PLT
movl %eax, %r13d
testl %eax, %eax
jne .L54
movl $1, %ecx
movl $67108896, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %r13d
testl %eax, %eax
jne .L55
movl $0x00000000, 48(%rsp)
movl $0x3f4ccccd, 52(%rsp)
movl $0xbe4ccccd, 56(%rsp)
movl $0x3d1c0443, 60(%rsp)
movl $0xbb69f6a9, 64(%rsp)
leaq 48(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $20, %edx
leaq _ZL4coef(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl %eax, %r13d
testl %eax, %eax
jne .L56
leaq 1120(%rsp), %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
movl %eax, %r13d
testl %eax, %eax
jne .L57
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl 1456(%rsp), %r13d
movl $131072, %eax
cmpl %eax, %r13d
cmova %eax, %r13d
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $128, %ecx
movl %r13d, %edx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, 36(%rsp)
movl $128, 24(%rsp)
movl 32(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movq 36(%rsp), %rdi
movl 44(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L58
.L44:
movl $2, %ecx
movl $67108896, %edx
movq 16(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl %eax, %r13d
testl %eax, %eax
jne .L59
movl $16777216, %edx
movq %r12, %rsi
movq %rbp, %rdi
call _Z11checkResultPfS_i
movq 8(%rsp), %rdi
call cudaFree@PLT
movl %eax, %r13d
testl %eax, %eax
jne .L60
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, %r13d
testl %eax, %eax
jne .L61
movq %rbx, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
call cudaDeviceReset@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L62
movq 2152(%rsp), %rax
subq %fs:40, %rax
jne .L63
movl $0, %eax
addq $2168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L51:
.cfi_restore_state
movl %eax, %ebx
movl $36, %ecx
leaq .LC9(%rip), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L52:
movl $38, %ecx
leaq .LC9(%rip), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L53:
movl $57, %ecx
leaq .LC9(%rip), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r13d, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L54:
movl $58, %ecx
leaq .LC9(%rip), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r13d, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L55:
movl $59, %ecx
leaq .LC9(%rip), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r13d, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L56:
movl $63, %ecx
leaq .LC9(%rip), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r13d, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L57:
movl $67, %ecx
leaq .LC9(%rip), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r13d, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L58:
movq 16(%rsp), %rax
leaq 16(%rax), %rsi
movq 8(%rsp), %rax
leaq 16(%rax), %rdi
movl $16777216, %edx
call _Z33__device_stub__Z10stencilGPUPfS_iPfS_i
jmp .L44
.L59:
movl $73, %ecx
leaq .LC9(%rip), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r13d, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L60:
movl $77, %ecx
leaq .LC9(%rip), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r13d, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L61:
movl $78, %ecx
leaq .LC9(%rip), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r13d, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L62:
movl $84, %ecx
leaq .LC9(%rip), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L63:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC15:
.string "_Z10stencilGPUPfS_i"
.LC16:
.string "coef"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z10stencilGPUPfS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $20, %r9d
movl $0, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _ZL4coef(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL4coef
.comm _ZL4coef,20,16
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1120403456
.align 4
.LC1:
.long 1061997773
.align 4
.LC3:
.long -1102263091
.align 4
.LC4:
.long 1025246275
.align 4
.LC5:
.long -1150683479
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC6:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC7:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "stencilConstantMem.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x42c80000 # float 100
.LCPI0_1:
.long 0x3f4ccccd # float 0.800000011
.LCPI0_2:
.long 0xbe4ccccd # float -0.200000003
.LCPI0_3:
.long 0x3d1c0443 # float 0.0380900018
.LCPI0_4:
.long 0xbb69f6a9 # float -0.00356999994
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI0_5:
.long 0x00000000 # float 0
.long 0x3f4ccccd # float 0.800000011
.long 0xbe4ccccd # float -0.200000003
.long 0x3d1c0443 # float 0.0380900018
.LCPI0_6:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI0_7:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $3104, %rsp # imm = 0xC20
.cfi_def_cfa_offset 3152
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 1632(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
jne .LBB0_1
# %bb.3:
leaq 1632(%rsp), %rdx
movl $.L.str.3, %edi
xorl %esi, %esi
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB0_4
# %bb.5:
xorl %r12d, %r12d
movl $.L.str.4, %edi
movl $16777216, %esi # imm = 0x1000000
xorl %eax, %eax
callq printf
movl $67108896, %edi # imm = 0x4000020
callq malloc
movq %rax, %rbx
movl $67108896, %edi # imm = 0x4000020
callq malloc
movq %rax, %r14
movl $67108896, %edi # imm = 0x4000020
callq malloc
movq %rax, %r15
.p2align 4, 0x90
.LBB0_6: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
divss .LCPI0_0(%rip), %xmm0
movss %xmm0, (%rbx,%r12,4)
incq %r12
cmpq $16777224, %r12 # imm = 0x1000008
jne .LBB0_6
# %bb.7: # %.lr.ph.i89.preheader
movl $8, %eax
movss .LCPI0_1(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorps %xmm1, %xmm1
movss .LCPI0_2(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss .LCPI0_3(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero
movss .LCPI0_4(%rip), %xmm4 # xmm4 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB0_8: # %.lr.ph.i89
# =>This Inner Loop Header: Depth=1
movss -12(%rbx,%rax,4), %xmm5 # xmm5 = mem[0],zero,zero,zero
subss -20(%rbx,%rax,4), %xmm5
movss -8(%rbx,%rax,4), %xmm6 # xmm6 = mem[0],zero,zero,zero
mulss %xmm0, %xmm5
subss -24(%rbx,%rax,4), %xmm6
addss %xmm1, %xmm5
mulss %xmm2, %xmm6
addss %xmm5, %xmm6
movss -4(%rbx,%rax,4), %xmm5 # xmm5 = mem[0],zero,zero,zero
subss -28(%rbx,%rax,4), %xmm5
mulss %xmm3, %xmm5
addss %xmm6, %xmm5
movss (%rbx,%rax,4), %xmm6 # xmm6 = mem[0],zero,zero,zero
subss -32(%rbx,%rax,4), %xmm6
mulss %xmm4, %xmm6
addss %xmm5, %xmm6
movss %xmm6, -16(%r14,%rax,4)
incq %rax
cmpq $16777221, %rax # imm = 0x1000005
jne .LBB0_8
# %bb.9: # %_Z11stencilHostPfS_i.exit
leaq 16(%rsp), %rdi
movl $67108896, %esi # imm = 0x4000020
callq hipMalloc
testl %eax, %eax
jne .LBB0_10
# %bb.11:
leaq 8(%rsp), %rdi
movl $67108896, %esi # imm = 0x4000020
callq hipMalloc
testl %eax, %eax
jne .LBB0_12
# %bb.13:
movq 16(%rsp), %rdi
movl $67108896, %edx # imm = 0x4000020
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_14
# %bb.15:
movaps .LCPI0_5(%rip), %xmm0 # xmm0 = [0.0E+0,8.00000011E-1,-2.00000003E-1,3.80900018E-2]
movaps %xmm0, 128(%rsp)
movl $-1150683479, 144(%rsp) # imm = 0xBB69F6A9
leaq 128(%rsp), %rsi
movl $coef, %edi
movl $20, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
testl %eax, %eax
jne .LBB0_16
# %bb.17:
leaq 160(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
jne .LBB0_18
# %bb.19:
movl 496(%rsp), %eax
cmpl $131072, %eax # imm = 0x20000
movl $131072, %esi # imm = 0x20000
cmovbl %eax, %esi
movabsq $4294967296, %r12 # imm = 0x100000000
leaq (%rsi,%r12), %r13
movl $.L.str.5, %edi
# kill: def $esi killed $esi killed $rsi
movl $128, %edx
xorl %eax, %eax
callq printf
orq $128, %r12
movq %r13, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_21
# %bb.20:
movq 16(%rsp), %rax
addq $16, %rax
movq 8(%rsp), %rcx
addq $16, %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $16777216, 28(%rsp) # imm = 0x1000000
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10stencilGPUPfS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_21:
movq 8(%rsp), %rsi
movl $67108896, %edx # imm = 0x4000020
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_33
# %bb.22: # %.lr.ph.i93.preheader
movl $4, %esi
movaps .LCPI0_6(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN]
movsd .LCPI0_7(%rip), %xmm1 # xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB0_23: # %.lr.ph.i93
# =>This Inner Loop Header: Depth=1
movss (%r14,%rsi,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss (%r15,%rsi,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
movaps %xmm2, %xmm4
subss %xmm3, %xmm4
andps %xmm0, %xmm4
cvtss2sd %xmm4, %xmm4
ucomisd %xmm1, %xmm4
ja .LBB0_24
# %bb.25: # in Loop: Header=BB0_23 Depth=1
incq %rsi
cmpq $16777216, %rsi # imm = 0x1000000
jne .LBB0_23
jmp .LBB0_26
.LBB0_24:
xorps %xmm0, %xmm0
cvtss2sd %xmm2, %xmm0
xorps %xmm1, %xmm1
cvtss2sd %xmm3, %xmm1
movl $.L.str.6, %edi
# kill: def $esi killed $esi killed $rsi
movb $2, %al
callq printf
.LBB0_26: # %_Z11checkResultPfS_i.exit
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB0_27
# %bb.28:
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB0_29
# %bb.30:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
callq hipDeviceReset
testl %eax, %eax
jne .LBB0_31
# %bb.32:
xorl %eax, %eax
addq $3104, %rsp # imm = 0xC20
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_1:
.cfi_def_cfa_offset 3152
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $36, %edx
jmp .LBB0_2
.LBB0_4:
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $38, %edx
jmp .LBB0_2
.LBB0_10:
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $57, %edx
jmp .LBB0_2
.LBB0_12:
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $58, %edx
jmp .LBB0_2
.LBB0_14:
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $59, %edx
jmp .LBB0_2
.LBB0_16:
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $63, %edx
jmp .LBB0_2
.LBB0_18:
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $67, %edx
jmp .LBB0_2
.LBB0_33:
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $73, %edx
jmp .LBB0_2
.LBB0_27:
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $77, %edx
jmp .LBB0_2
.LBB0_29:
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $78, %edx
jmp .LBB0_2
.LBB0_31:
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $84, %edx
.LBB0_2:
movl %eax, %ebx
xorl %eax, %eax
callq printf
movl %ebx, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z11initialDataPfi
.LCPI1_0:
.long 0x42c80000 # float 100
.text
.globl _Z11initialDataPfi
.p2align 4, 0x90
.type _Z11initialDataPfi,@function
_Z11initialDataPfi: # @_Z11initialDataPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
divss .LCPI1_0(%rip), %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z11initialDataPfi, .Lfunc_end1-_Z11initialDataPfi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z11stencilHostPfS_i
.LCPI2_0:
.long 0x3f4ccccd # float 0.800000011
.LCPI2_1:
.long 0xbe4ccccd # float -0.200000003
.LCPI2_2:
.long 0x3d1c0443 # float 0.0380900018
.LCPI2_3:
.long 0xbb69f6a9 # float -0.00356999994
.text
.globl _Z11stencilHostPfS_i
.p2align 4, 0x90
.type _Z11stencilHostPfS_i,@function
_Z11stencilHostPfS_i: # @_Z11stencilHostPfS_i
.cfi_startproc
# %bb.0:
cmpl $4, %edx
jl .LBB2_3
# %bb.1: # %.lr.ph.preheader
movl %edx, %eax
addq $-3, %rax
xorl %ecx, %ecx
movss .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorps %xmm1, %xmm1
movss .LCPI2_1(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss .LCPI2_2(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero
movss .LCPI2_3(%rip), %xmm4 # xmm4 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss 20(%rdi,%rcx,4), %xmm5 # xmm5 = mem[0],zero,zero,zero
subss 12(%rdi,%rcx,4), %xmm5
movss 24(%rdi,%rcx,4), %xmm6 # xmm6 = mem[0],zero,zero,zero
mulss %xmm0, %xmm5
subss 8(%rdi,%rcx,4), %xmm6
addss %xmm1, %xmm5
mulss %xmm2, %xmm6
addss %xmm5, %xmm6
movss 28(%rdi,%rcx,4), %xmm5 # xmm5 = mem[0],zero,zero,zero
subss 4(%rdi,%rcx,4), %xmm5
mulss %xmm3, %xmm5
addss %xmm6, %xmm5
movss 32(%rdi,%rcx,4), %xmm6 # xmm6 = mem[0],zero,zero,zero
subss (%rdi,%rcx,4), %xmm6
mulss %xmm4, %xmm6
addss %xmm5, %xmm6
movss %xmm6, 16(%rsi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB2_2
.LBB2_3: # %._crit_edge
retq
.Lfunc_end2:
.size _Z11stencilHostPfS_i, .Lfunc_end2-_Z11stencilHostPfS_i
.cfi_endproc
# -- End function
.globl _Z25__device_stub__stencilGPUPfS_i # -- Begin function _Z25__device_stub__stencilGPUPfS_i
.p2align 4, 0x90
.type _Z25__device_stub__stencilGPUPfS_i,@function
_Z25__device_stub__stencilGPUPfS_i: # @_Z25__device_stub__stencilGPUPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10stencilGPUPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z25__device_stub__stencilGPUPfS_i, .Lfunc_end3-_Z25__device_stub__stencilGPUPfS_i
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z11checkResultPfS_i
.LCPI4_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI4_1:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z11checkResultPfS_i
.p2align 4, 0x90
.type _Z11checkResultPfS_i,@function
_Z11checkResultPfS_i: # @_Z11checkResultPfS_i
.cfi_startproc
# %bb.0:
cmpl $5, %edx
jl .LBB4_4
# %bb.1: # %.lr.ph.preheader
movl %edx, %ecx
movl $4, %eax
movaps .LCPI4_0(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN]
movsd .LCPI4_1(%rip), %xmm1 # xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rdi,%rax,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss (%rsi,%rax,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
movaps %xmm2, %xmm4
subss %xmm3, %xmm4
andps %xmm0, %xmm4
cvtss2sd %xmm4, %xmm4
ucomisd %xmm1, %xmm4
ja .LBB4_5
# %bb.3: # in Loop: Header=BB4_2 Depth=1
incq %rax
cmpq %rax, %rcx
jne .LBB4_2
.LBB4_4: # %.loopexit
retq
.LBB4_5:
xorps %xmm0, %xmm0
cvtss2sd %xmm2, %xmm0
xorps %xmm1, %xmm1
cvtss2sd %xmm3, %xmm1
movl $.L.str.6, %edi
movl %eax, %esi
movb $2, %al
jmp printf # TAILCALL
.Lfunc_end4:
.size _Z11checkResultPfS_i, .Lfunc_end4-_Z11checkResultPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10stencilGPUPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $coef, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $20, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type coef,@object # @coef
.local coef
.comm coef,20,16
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error: %s:%d, "
.size .L.str, 15
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/SaoYan/Learning_CUDA/master/Ch5/stencilConstantMem.hip"
.size .L.str.1, 112
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "code: %d, reason: %s\n"
.size .L.str.2, 22
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Using Device %d: %s\n"
.size .L.str.3, 21
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "array size: %d\n"
.size .L.str.4, 16
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "(grid, block) %d,%d \n"
.size .L.str.5, 22
.type _Z10stencilGPUPfS_i,@object # @_Z10stencilGPUPfS_i
.section .rodata,"a",@progbits
.globl _Z10stencilGPUPfS_i
.p2align 3, 0x0
_Z10stencilGPUPfS_i:
.quad _Z25__device_stub__stencilGPUPfS_i
.size _Z10stencilGPUPfS_i, 8
.type .L.str.6,@object # @.str.6
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.6:
.asciz "different on %dth element: host %f gpu %f\n"
.size .L.str.6, 43
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10stencilGPUPfS_i"
.size .L__unnamed_1, 20
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "coef"
.size .L__unnamed_2, 5
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__stencilGPUPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym coef
.addrsig_sym _Z10stencilGPUPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void rgb2binaryKernel(unsigned char *imgr,unsigned char *imgg,unsigned char *imgb,unsigned char *img_binary, int n, int umbral) {
int r, g, b;
int index = threadIdx.x + blockIdx.x * blockDim.x;
if (index < n){
r = imgr[index];
g = imgg[index];
b = imgb[index];
img_binary[index] = (unsigned char)( 0.299*r + 0.587*g + 0.114*b)>umbral?255:0;
}
} | code for sm_80
Function : _Z16rgb2binaryKernelPhS_S_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ SHF.R.S32.HI R14, RZ, 0x1f, R0 ; /* 0x0000001fff0e7819 */
/* 0x000fe20000011400 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IADD3 R10, P1, R0.reuse, c[0x0][0x168], RZ ; /* 0x00005a00000a7a10 */
/* 0x040fe40007f3e0ff */
/*0090*/ IADD3 R8, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000087a10 */
/* 0x000fe40007f1e0ff */
/*00a0*/ IADD3.X R11, R14.reuse, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b000e0b7a10 */
/* 0x040fe40000ffe4ff */
/*00b0*/ IADD3.X R9, R14, c[0x0][0x164], RZ, P0, !PT ; /* 0x000059000e097a10 */
/* 0x000fe400007fe4ff */
/*00c0*/ IADD3 R12, P1, R0, c[0x0][0x170], RZ ; /* 0x00005c00000c7a10 */
/* 0x000fe20007f3e0ff */
/*00d0*/ LDG.E.U8 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea6000c1e1100 */
/*00e0*/ IADD3.X R13, R14, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d000e0d7a10 */
/* 0x000fe20000ffe4ff */
/*00f0*/ LDG.E.U8 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee8000c1e1100 */
/*0100*/ LDG.E.U8 R6, [R12.64] ; /* 0x000000040c067981 */
/* 0x000f22000c1e1100 */
/*0110*/ I2F.F64.U16 R4, R10 ; /* 0x0000000a00047312 */
/* 0x004e300000101800 */
/*0120*/ I2F.F64.U16 R2, R8 ; /* 0x0000000800027312 */
/* 0x008e700000101800 */
/*0130*/ I2F.F64.U16 R6, R6 ; /* 0x0000000600067312 */
/* 0x010ea20000101800 */
/*0140*/ DMUL R4, R4, c[0x2][0x0] ; /* 0x0080000004047a28 */
/* 0x001e4c0000000000 */
/*0150*/ DFMA R2, R2, c[0x2][0x8], R4 ; /* 0x0080020002027a2b */
/* 0x0020a40000000004 */
/*0160*/ IADD3 R4, P1, R0, c[0x0][0x178], RZ ; /* 0x00005e0000047a10 */
/* 0x001fc80007f3e0ff */
/*0170*/ DFMA R2, R6, c[0x2][0x10], R2 ; /* 0x0080040006027a2b */
/* 0x004e140000000002 */
/*0180*/ F2I.U32.F64.TRUNC R2, R2 ; /* 0x0000000200027311 */
/* 0x001e24000030d000 */
/*0190*/ LOP3.LUT R5, R2, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff02057812 */
/* 0x001fc800078ec0ff */
/*01a0*/ ISETP.GT.AND P0, PT, R5, c[0x0][0x184], PT ; /* 0x0000610005007a0c */
/* 0x000fe40003f04270 */
/*01b0*/ IADD3.X R5, R14, c[0x0][0x17c], RZ, P1, !PT ; /* 0x00005f000e057a10 */
/* 0x000fe40000ffe4ff */
/*01c0*/ SEL R7, RZ, 0xff, !P0 ; /* 0x000000ffff077807 */
/* 0x000fca0004000000 */
/*01d0*/ STG.E.U8 [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101104 */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void rgb2binaryKernel(unsigned char *imgr,unsigned char *imgg,unsigned char *imgb,unsigned char *img_binary, int n, int umbral) {
int r, g, b;
int index = threadIdx.x + blockIdx.x * blockDim.x;
if (index < n){
r = imgr[index];
g = imgg[index];
b = imgb[index];
img_binary[index] = (unsigned char)( 0.299*r + 0.587*g + 0.114*b)>umbral?255:0;
}
} | .file "tmpxft_0011308e_00000000-6_rgb2binaryKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z16rgb2binaryKernelPhS_S_S_iiPhS_S_S_ii
.type _Z44__device_stub__Z16rgb2binaryKernelPhS_S_S_iiPhS_S_S_ii, @function
_Z44__device_stub__Z16rgb2binaryKernelPhS_S_S_iiPhS_S_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16rgb2binaryKernelPhS_S_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z16rgb2binaryKernelPhS_S_S_iiPhS_S_S_ii, .-_Z44__device_stub__Z16rgb2binaryKernelPhS_S_S_iiPhS_S_S_ii
.globl _Z16rgb2binaryKernelPhS_S_S_ii
.type _Z16rgb2binaryKernelPhS_S_S_ii, @function
_Z16rgb2binaryKernelPhS_S_S_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z16rgb2binaryKernelPhS_S_S_iiPhS_S_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16rgb2binaryKernelPhS_S_S_ii, .-_Z16rgb2binaryKernelPhS_S_S_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z16rgb2binaryKernelPhS_S_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16rgb2binaryKernelPhS_S_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void rgb2binaryKernel(unsigned char *imgr,unsigned char *imgg,unsigned char *imgb,unsigned char *img_binary, int n, int umbral) {
int r, g, b;
int index = threadIdx.x + blockIdx.x * blockDim.x;
if (index < n){
r = imgr[index];
g = imgg[index];
b = imgb[index];
img_binary[index] = (unsigned char)( 0.299*r + 0.587*g + 0.114*b)>umbral?255:0;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void rgb2binaryKernel(unsigned char *imgr,unsigned char *imgg,unsigned char *imgb,unsigned char *img_binary, int n, int umbral) {
int r, g, b;
int index = threadIdx.x + blockIdx.x * blockDim.x;
if (index < n){
r = imgr[index];
g = imgg[index];
b = imgb[index];
img_binary[index] = (unsigned char)( 0.299*r + 0.587*g + 0.114*b)>umbral?255:0;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void rgb2binaryKernel(unsigned char *imgr,unsigned char *imgg,unsigned char *imgb,unsigned char *img_binary, int n, int umbral) {
int r, g, b;
int index = threadIdx.x + blockIdx.x * blockDim.x;
if (index < n){
r = imgr[index];
g = imgg[index];
b = imgb[index];
img_binary[index] = (unsigned char)( 0.299*r + 0.587*g + 0.114*b)>umbral?255:0;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16rgb2binaryKernelPhS_S_S_ii
.globl _Z16rgb2binaryKernelPhS_S_S_ii
.p2align 8
.type _Z16rgb2binaryKernelPhS_S_S_ii,@function
_Z16rgb2binaryKernelPhS_S_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b256 s[4:11], s[0:1], 0x0
v_ashrrev_i32_e32 v8, 31, v1
s_mov_b32 s3, 0x3fe2c8b4
s_mov_b32 s2, 0x39581062
s_load_b32 s0, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v8, vcc_lo
global_load_u8 v0, v[2:3], off
v_add_co_u32 v2, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v8, vcc_lo
global_load_u8 v4, v[2:3], off
v_add_co_u32 v2, vcc_lo, s8, v1
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v8, vcc_lo
global_load_u8 v6, v[2:3], off
s_waitcnt vmcnt(2)
v_cvt_f64_u32_e32 v[2:3], v0
s_waitcnt vmcnt(1)
v_cvt_f64_u32_e32 v[4:5], v4
s_waitcnt vmcnt(0)
v_cvt_f64_u32_e32 v[6:7], v6
s_delay_alu instid0(VALU_DEP_3)
v_mul_f64 v[2:3], v[2:3], s[2:3]
s_mov_b32 s3, 0x3fd322d0
s_mov_b32 s2, 0xe5604189
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[2:3], v[4:5], s[2:3], v[2:3]
s_mov_b32 s3, 0x3fbd2f1a
s_mov_b32 s2, 0x9fbe76c9
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[2:3], v[6:7], s[2:3], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_i32_f64_e32 v0, v[2:3]
v_cmp_lt_i32_e32 vcc_lo, s0, v0
v_cndmask_b32_e64 v2, 0, -1, vcc_lo
v_add_co_u32 v0, vcc_lo, s10, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s11, v8, vcc_lo
global_store_b8 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16rgb2binaryKernelPhS_S_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16rgb2binaryKernelPhS_S_S_ii, .Lfunc_end0-_Z16rgb2binaryKernelPhS_S_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16rgb2binaryKernelPhS_S_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16rgb2binaryKernelPhS_S_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void rgb2binaryKernel(unsigned char *imgr,unsigned char *imgg,unsigned char *imgb,unsigned char *img_binary, int n, int umbral) {
int r, g, b;
int index = threadIdx.x + blockIdx.x * blockDim.x;
if (index < n){
r = imgr[index];
g = imgg[index];
b = imgb[index];
img_binary[index] = (unsigned char)( 0.299*r + 0.587*g + 0.114*b)>umbral?255:0;
}
} | .text
.file "rgb2binaryKernel.hip"
.globl _Z31__device_stub__rgb2binaryKernelPhS_S_S_ii # -- Begin function _Z31__device_stub__rgb2binaryKernelPhS_S_S_ii
.p2align 4, 0x90
.type _Z31__device_stub__rgb2binaryKernelPhS_S_S_ii,@function
_Z31__device_stub__rgb2binaryKernelPhS_S_S_ii: # @_Z31__device_stub__rgb2binaryKernelPhS_S_S_ii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16rgb2binaryKernelPhS_S_S_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z31__device_stub__rgb2binaryKernelPhS_S_S_ii, .Lfunc_end0-_Z31__device_stub__rgb2binaryKernelPhS_S_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16rgb2binaryKernelPhS_S_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16rgb2binaryKernelPhS_S_S_ii,@object # @_Z16rgb2binaryKernelPhS_S_S_ii
.section .rodata,"a",@progbits
.globl _Z16rgb2binaryKernelPhS_S_S_ii
.p2align 3, 0x0
_Z16rgb2binaryKernelPhS_S_S_ii:
.quad _Z31__device_stub__rgb2binaryKernelPhS_S_S_ii
.size _Z16rgb2binaryKernelPhS_S_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16rgb2binaryKernelPhS_S_S_ii"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__rgb2binaryKernelPhS_S_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16rgb2binaryKernelPhS_S_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16rgb2binaryKernelPhS_S_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ SHF.R.S32.HI R14, RZ, 0x1f, R0 ; /* 0x0000001fff0e7819 */
/* 0x000fe20000011400 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IADD3 R10, P1, R0.reuse, c[0x0][0x168], RZ ; /* 0x00005a00000a7a10 */
/* 0x040fe40007f3e0ff */
/*0090*/ IADD3 R8, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000087a10 */
/* 0x000fe40007f1e0ff */
/*00a0*/ IADD3.X R11, R14.reuse, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b000e0b7a10 */
/* 0x040fe40000ffe4ff */
/*00b0*/ IADD3.X R9, R14, c[0x0][0x164], RZ, P0, !PT ; /* 0x000059000e097a10 */
/* 0x000fe400007fe4ff */
/*00c0*/ IADD3 R12, P1, R0, c[0x0][0x170], RZ ; /* 0x00005c00000c7a10 */
/* 0x000fe20007f3e0ff */
/*00d0*/ LDG.E.U8 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea6000c1e1100 */
/*00e0*/ IADD3.X R13, R14, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d000e0d7a10 */
/* 0x000fe20000ffe4ff */
/*00f0*/ LDG.E.U8 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee8000c1e1100 */
/*0100*/ LDG.E.U8 R6, [R12.64] ; /* 0x000000040c067981 */
/* 0x000f22000c1e1100 */
/*0110*/ I2F.F64.U16 R4, R10 ; /* 0x0000000a00047312 */
/* 0x004e300000101800 */
/*0120*/ I2F.F64.U16 R2, R8 ; /* 0x0000000800027312 */
/* 0x008e700000101800 */
/*0130*/ I2F.F64.U16 R6, R6 ; /* 0x0000000600067312 */
/* 0x010ea20000101800 */
/*0140*/ DMUL R4, R4, c[0x2][0x0] ; /* 0x0080000004047a28 */
/* 0x001e4c0000000000 */
/*0150*/ DFMA R2, R2, c[0x2][0x8], R4 ; /* 0x0080020002027a2b */
/* 0x0020a40000000004 */
/*0160*/ IADD3 R4, P1, R0, c[0x0][0x178], RZ ; /* 0x00005e0000047a10 */
/* 0x001fc80007f3e0ff */
/*0170*/ DFMA R2, R6, c[0x2][0x10], R2 ; /* 0x0080040006027a2b */
/* 0x004e140000000002 */
/*0180*/ F2I.U32.F64.TRUNC R2, R2 ; /* 0x0000000200027311 */
/* 0x001e24000030d000 */
/*0190*/ LOP3.LUT R5, R2, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff02057812 */
/* 0x001fc800078ec0ff */
/*01a0*/ ISETP.GT.AND P0, PT, R5, c[0x0][0x184], PT ; /* 0x0000610005007a0c */
/* 0x000fe40003f04270 */
/*01b0*/ IADD3.X R5, R14, c[0x0][0x17c], RZ, P1, !PT ; /* 0x00005f000e057a10 */
/* 0x000fe40000ffe4ff */
/*01c0*/ SEL R7, RZ, 0xff, !P0 ; /* 0x000000ffff077807 */
/* 0x000fca0004000000 */
/*01d0*/ STG.E.U8 [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101104 */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16rgb2binaryKernelPhS_S_S_ii
.globl _Z16rgb2binaryKernelPhS_S_S_ii
.p2align 8
.type _Z16rgb2binaryKernelPhS_S_S_ii,@function
_Z16rgb2binaryKernelPhS_S_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b256 s[4:11], s[0:1], 0x0
v_ashrrev_i32_e32 v8, 31, v1
s_mov_b32 s3, 0x3fe2c8b4
s_mov_b32 s2, 0x39581062
s_load_b32 s0, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v8, vcc_lo
global_load_u8 v0, v[2:3], off
v_add_co_u32 v2, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v8, vcc_lo
global_load_u8 v4, v[2:3], off
v_add_co_u32 v2, vcc_lo, s8, v1
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v8, vcc_lo
global_load_u8 v6, v[2:3], off
s_waitcnt vmcnt(2)
v_cvt_f64_u32_e32 v[2:3], v0
s_waitcnt vmcnt(1)
v_cvt_f64_u32_e32 v[4:5], v4
s_waitcnt vmcnt(0)
v_cvt_f64_u32_e32 v[6:7], v6
s_delay_alu instid0(VALU_DEP_3)
v_mul_f64 v[2:3], v[2:3], s[2:3]
s_mov_b32 s3, 0x3fd322d0
s_mov_b32 s2, 0xe5604189
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[2:3], v[4:5], s[2:3], v[2:3]
s_mov_b32 s3, 0x3fbd2f1a
s_mov_b32 s2, 0x9fbe76c9
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[2:3], v[6:7], s[2:3], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_i32_f64_e32 v0, v[2:3]
v_cmp_lt_i32_e32 vcc_lo, s0, v0
v_cndmask_b32_e64 v2, 0, -1, vcc_lo
v_add_co_u32 v0, vcc_lo, s10, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s11, v8, vcc_lo
global_store_b8 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16rgb2binaryKernelPhS_S_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16rgb2binaryKernelPhS_S_S_ii, .Lfunc_end0-_Z16rgb2binaryKernelPhS_S_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16rgb2binaryKernelPhS_S_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16rgb2binaryKernelPhS_S_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0011308e_00000000-6_rgb2binaryKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z16rgb2binaryKernelPhS_S_S_iiPhS_S_S_ii
.type _Z44__device_stub__Z16rgb2binaryKernelPhS_S_S_iiPhS_S_S_ii, @function
_Z44__device_stub__Z16rgb2binaryKernelPhS_S_S_iiPhS_S_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16rgb2binaryKernelPhS_S_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z16rgb2binaryKernelPhS_S_S_iiPhS_S_S_ii, .-_Z44__device_stub__Z16rgb2binaryKernelPhS_S_S_iiPhS_S_S_ii
.globl _Z16rgb2binaryKernelPhS_S_S_ii
.type _Z16rgb2binaryKernelPhS_S_S_ii, @function
_Z16rgb2binaryKernelPhS_S_S_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z16rgb2binaryKernelPhS_S_S_iiPhS_S_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16rgb2binaryKernelPhS_S_S_ii, .-_Z16rgb2binaryKernelPhS_S_S_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z16rgb2binaryKernelPhS_S_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16rgb2binaryKernelPhS_S_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "rgb2binaryKernel.hip"
.globl _Z31__device_stub__rgb2binaryKernelPhS_S_S_ii # -- Begin function _Z31__device_stub__rgb2binaryKernelPhS_S_S_ii
.p2align 4, 0x90
.type _Z31__device_stub__rgb2binaryKernelPhS_S_S_ii,@function
_Z31__device_stub__rgb2binaryKernelPhS_S_S_ii: # @_Z31__device_stub__rgb2binaryKernelPhS_S_S_ii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16rgb2binaryKernelPhS_S_S_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z31__device_stub__rgb2binaryKernelPhS_S_S_ii, .Lfunc_end0-_Z31__device_stub__rgb2binaryKernelPhS_S_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16rgb2binaryKernelPhS_S_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16rgb2binaryKernelPhS_S_S_ii,@object # @_Z16rgb2binaryKernelPhS_S_S_ii
.section .rodata,"a",@progbits
.globl _Z16rgb2binaryKernelPhS_S_S_ii
.p2align 3, 0x0
_Z16rgb2binaryKernelPhS_S_S_ii:
.quad _Z31__device_stub__rgb2binaryKernelPhS_S_S_ii
.size _Z16rgb2binaryKernelPhS_S_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16rgb2binaryKernelPhS_S_S_ii"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__rgb2binaryKernelPhS_S_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16rgb2binaryKernelPhS_S_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <ctime>
#include <stdlib.h>
#include <sys/time.h>
// Thread block size
#define BLOCK_SIZE 16
#define TILE_SIZE 32
#define ROW 1024
#define COL 1024
// GPU Functions
void MM_Basic(float *a, float *b, float *c, int row, int col, int k);
__global__ void MM_Basic_kernel( float *devA, float *devB, float *devC, int row, int col, int k);
void MM_Improved(float *a, float *b, float *c, int row, int col, int k);
__global__ void MM_Improved_kernel( float *devA, float *devB, float *devC, int row, int col, int k);
/*
* Main function
*/
int main(int argC, char** argV) {
//
// Setup
//////////////////
// Time Variables
float time;
cudaEvent_t start, stop;
cudaEventCreate (&start);
cudaEventCreate (&stop);
// Matrices
float *a, *b;
float *c_cpu, *c_gpu_basic, *c_gpu_improved;
//Setting matrix parameters.
int row = ROW;
int col = COL;
int k = COL;
int sum = 0;
// Process input arguments (if specified)
switch (argC) {
case 2: {
row = atoi(argV[1]);
col = row;
k = col;
break;
}
case 3: {
row = atoi(argV[1]);
col = atoi(argV[2]);
k = col;
break;
}
default: {
//Nothing
}
}
//Setting host memory space.
a = (float *) malloc(row*k*sizeof(float));
b = (float *) malloc(k*col*sizeof(float));
c_cpu = (float *) malloc(row*col*sizeof(float));
c_gpu_basic = (float *) malloc(row*col*sizeof(float));
c_gpu_improved = (float *) malloc(row*col*sizeof(float));
//Initializing [A] and [B] with random values from 1 to 10, and C to 0
printf ("Initializing Matricies, could take some time...\n");
for(int i = 0 ; i < row ; i++ ){
for(int j = 0 ; j < k ; j++ ){
a[i*k+j] = rand()%10;
}
}
for(int i = 0 ; i < k ; i++ ){
for(int j = 0 ; j < col ; j++ ){
b[i*col+j] = rand()%10;
}
}
for(int i = 0 ; i < k ; i++ ){
for(int j = 0 ; j < col ; j++ ){
c_cpu [i*col+j] = 0;
c_gpu_basic [i*col+j] = 0;
c_gpu_improved [i*col+j] = 0;
}
}
//
// CPU Calculation
//////////////////
printf("Running sequential job.\n");
cudaEventRecord(start,0);
for(int i = 0 ; i < row ; i++ ){
for(int j = 0 ; j < col ; j++ ){
sum = 0;
for(int w = 0 ; w < k ; w++ ){
sum += a[i*k+w] * b[w*col+j];
}
c_cpu[i*col+j] = sum;
}
}
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
printf("\tSequential Job Time: %.2f ms\n", time);
//
// Basic GPU Calculation
////////////////////////
printf("Running Basic parallel job.\n");
cudaEventRecord(start,0);
MM_Basic(a, b, c_gpu_basic, row, col, k);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
printf("\tBasic Parallel Job Time: %.2f ms\n", time);
// Compares matrices to make sure answer is correct, initializes c for next kernel.
bool error = false;
for(int i = 0 ; i < k ; i++ ){
for(int j = 0 ; j < col ; j++ ){
if (c_cpu[i*col+j] != c_gpu_basic[i*col+j]) {
printf("\tError: Starting at [%d][%d]\n", i, j);
error = true;
}
if (error) break;
}
if (error) break;
}
if (!error) printf("\tNo errors found.\n");
//
// Improved GPU Calculation
////////////////////////
printf("Running Improved parallel job.\n");
cudaEventRecord(start,0);
MM_Improved(a, b, c_gpu_improved, row, col, k);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
printf("\tImproved Parallel Job Time: %.2f ms\n", time);
// Compares matrices to make sure answer is correct, initializes c for next kernel.
error = false;
for(int i = 0 ; i < k ; i++ ){
for(int j = 0 ; j < col ; j++ ){
if (c_cpu[i*col+j] != c_gpu_improved[i*col+j]) {
printf("\tError: Starting at [%d][%d]\n", i, j);
error = true;
}
if (error) break;
}
if (error) break;
}
if (!error) printf("\tNo errors found.\n");
free (a);
free (b);
free (c_cpu);
free (c_gpu_basic);
free (c_gpu_improved);
}
void MM_Basic(float *a, float *b, float *c, int row, int col, int k) {
cudaEvent_t kernelstart, kernelstop;
float time;
cudaEventCreate (&kernelstart);
cudaEventCreate (&kernelstop);
int sizeA = row*k*sizeof(float);
int sizeB = k*col*sizeof(float);
int sizeC = row*col*sizeof(float);
float *devA, *devB, *devC;
cudaMalloc((void**)&devA, sizeA);
cudaMalloc((void**)&devB, sizeB);
cudaMalloc((void**)&devC, sizeC);
cudaMemcpy(devA, a, sizeA, cudaMemcpyHostToDevice);
cudaMemcpy(devB, b, sizeB, cudaMemcpyHostToDevice);
dim3 dimBlock(16, 16, 1);
dim3 dimGrid((COL+dimBlock.x-1)/dimBlock.x, (ROW+dimBlock.y-1)/dimBlock.y, 1);
cudaEventRecord(kernelstart,0);
MM_Basic_kernel<<<dimGrid, dimBlock>>>(devA, devB, devC, row, col, k);
cudaEventRecord(kernelstop,0);
cudaEventSynchronize(kernelstop);
cudaEventElapsedTime(&time, kernelstart, kernelstop);
printf("\tKernel Job Time: %.2f ms\n", time);
cudaMemcpy(c, devC, sizeC, cudaMemcpyDeviceToHost);
//Freeing device matrices.
cudaFree(devA); cudaFree(devB); cudaFree(devC);
}
__global__ void MM_Basic_kernel( float *devA, float *devB, float *devC, int row, int col, int k) {
int txID = blockIdx.x * blockDim.x + threadIdx.x;
int tyID = blockIdx.y * blockDim.y + threadIdx.y;
if ((txID < col) && (tyID < row)) {
float Pvalue = 0;
for(int w = 0 ; w < k ; w++) {
Pvalue += devA[tyID*k+w] * devB[w*k+txID];
}
devC[tyID*k+txID] = Pvalue;
}
}
void MM_Improved(float *a, float *b, float *c, int row, int col, int k){
// Write Code here
cudaEvent_t kernelstart, kernelstop;
float time;
cudaEventCreate (&kernelstart);
cudaEventCreate (&kernelstop);
int sizeA = row*k*sizeof(float);
int sizeB = k*col*sizeof(float);
int sizeC = row*col*sizeof(float);
float *devA, *devB, *devC;
cudaMalloc((void**)&devA, sizeA);
cudaMalloc((void**)&devB, sizeB);
cudaMalloc((void**)&devC, sizeC);
cudaMemcpy(devA, a, sizeA, cudaMemcpyHostToDevice);
cudaMemcpy(devB, b, sizeB, cudaMemcpyHostToDevice);
dim3 dimBlock(32, 32, 1);
dim3 dimGrid((COL+dimBlock.x-1)/dimBlock.x, (ROW+dimBlock.y-1)/dimBlock.y, 1);
cudaEventRecord(kernelstart,0);
MM_Basic_kernel<<<dimGrid, dimBlock>>>(devA, devB, devC, row, col, k);
cudaEventRecord(kernelstop,0);
cudaEventSynchronize(kernelstop);
cudaEventElapsedTime(&time, kernelstart, kernelstop);
printf("\tKernel Job Time: %.2f ms\n", time);
cudaMemcpy(c, devC, sizeC, cudaMemcpyDeviceToHost);
//Freeing device matrices.
cudaFree(devA); cudaFree(devB); cudaFree(devC);
}
__global__ void MM_Improved_kernel( float *devA, float *devB, float *devC, int row, int col, int k){
// Write Code here
__shared__ int shareBlockA[TILE_SIZE][TILE_SIZE];
__shared__ int shareBlockB[TILE_SIZE][TILE_SIZE];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int Row = by * TILE_SIZE + ty;
int Col = bx * TILE_SIZE + tx;
float Cvalue = 0;
for (int m = 0; m < row/TILE_SIZE; ++m) {
shareBlockA[ty][tx] = devA[Row * row + (m*TILE_SIZE + tx)];
shareBlockB[ty][tx] = devB[Col + (m * TILE_SIZE + ty) * row];
__syncthreads();
for (int k = 0; k < TILE_SIZE; ++k)
Cvalue += shareBlockA[ty][k] * shareBlockB[k][tx];
__syncthreads();
}
devC[Row*row+Col] = Cvalue;
} | .file "tmpxft_001b0088_00000000-6_MatrixMul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z15MM_Basic_kernelPfS_S_iiiPfS_S_iii
.type _Z42__device_stub__Z15MM_Basic_kernelPfS_S_iiiPfS_S_iii, @function
_Z42__device_stub__Z15MM_Basic_kernelPfS_S_iiiPfS_S_iii:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15MM_Basic_kernelPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z42__device_stub__Z15MM_Basic_kernelPfS_S_iiiPfS_S_iii, .-_Z42__device_stub__Z15MM_Basic_kernelPfS_S_iiiPfS_S_iii
.globl _Z15MM_Basic_kernelPfS_S_iii
.type _Z15MM_Basic_kernelPfS_S_iii, @function
_Z15MM_Basic_kernelPfS_S_iii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z15MM_Basic_kernelPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z15MM_Basic_kernelPfS_S_iii, .-_Z15MM_Basic_kernelPfS_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\tKernel Job Time: %.2f ms\n"
.text
.globl _Z11MM_ImprovedPfS_S_iii
.type _Z11MM_ImprovedPfS_S_iii, @function
_Z11MM_ImprovedPfS_S_iii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, %r13d
movl %r8d, %r14d
movl %r9d, %r15d
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movl %r13d, %r12d
imull %r15d, %r12d
sall $2, %r12d
movslq %r12d, %r12
leaq 56(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl %r15d, %ebp
imull %r14d, %ebp
sall $2, %ebp
movslq %ebp, %rbp
leaq 64(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl %r13d, %ebx
imull %r14d, %ebx
sall $2, %ebx
movslq %ebx, %rbx
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq 8(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbp, %rdx
movq 16(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 88(%rsp)
movl $32, 92(%rsp)
movl $32, 96(%rsp)
movl $1, 100(%rsp)
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $32, 80(%rsp)
movl $32, 84(%rsp)
movl 88(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movq 92(%rsp), %rdi
movl 100(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 36(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 36(%rsp), %xmm0
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 72(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl %r15d, %r9d
movl %r14d, %r8d
movl %r13d, %ecx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z42__device_stub__Z15MM_Basic_kernelPfS_S_iiiPfS_S_iii
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z11MM_ImprovedPfS_S_iii, .-_Z11MM_ImprovedPfS_S_iii
.globl _Z8MM_BasicPfS_S_iii
.type _Z8MM_BasicPfS_S_iii, @function
_Z8MM_BasicPfS_S_iii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, %r13d
movl %r8d, %r14d
movl %r9d, %r15d
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movl %r13d, %r12d
imull %r15d, %r12d
sall $2, %r12d
movslq %r12d, %r12
leaq 56(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl %r15d, %ebp
imull %r14d, %ebp
sall $2, %ebp
movslq %ebp, %rbp
leaq 64(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl %r13d, %ebx
imull %r14d, %ebx
sall $2, %ebx
movslq %ebx, %rbx
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq 8(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbp, %rdx
movq 16(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 88(%rsp)
movl $64, 92(%rsp)
movl $64, 96(%rsp)
movl $1, 100(%rsp)
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $16, 80(%rsp)
movl $16, 84(%rsp)
movl 88(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movq 92(%rsp), %rdi
movl 100(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L18:
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 36(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 36(%rsp), %xmm0
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 72(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl %r15d, %r9d
movl %r14d, %r8d
movl %r13d, %ecx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z42__device_stub__Z15MM_Basic_kernelPfS_S_iiiPfS_S_iii
jmp .L18
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z8MM_BasicPfS_S_iii, .-_Z8MM_BasicPfS_S_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Initializing Matricies, could take some time...\n"
.section .rodata.str1.1
.LC3:
.string "Running sequential job.\n"
.section .rodata.str1.8
.align 8
.LC4:
.string "\tSequential Job Time: %.2f ms\n"
.section .rodata.str1.1
.LC5:
.string "Running Basic parallel job.\n"
.section .rodata.str1.8
.align 8
.LC6:
.string "\tBasic Parallel Job Time: %.2f ms\n"
.section .rodata.str1.1
.LC7:
.string "\tError: Starting at [%d][%d]\n"
.section .rodata.str1.8
.align 8
.LC8:
.string "Running Improved parallel job.\n"
.align 8
.LC9:
.string "\tImproved Parallel Job Time: %.2f ms\n"
.section .rodata.str1.1
.LC10:
.string "\tNo errors found.\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movl %edi, %ebp
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
leaq 80(%rsp), %rdi
call cudaEventCreate@PLT
cmpl $2, %ebp
je .L24
cmpl $3, %ebp
je .L25
movl $4194304, %edi
call malloc@PLT
movq %rax, 8(%rsp)
movl $4194304, %edi
call malloc@PLT
movq %rax, 16(%rsp)
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
movl $4194304, %edi
call malloc@PLT
movq %rax, %r12
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1024, %r15d
movl $1024, 4(%rsp)
jmp .L60
.L24:
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 4(%rsp)
movl %eax, %r15d
.L27:
movl 4(%rsp), %r14d
movl %r14d, %r12d
imull %r15d, %r12d
movslq %r12d, %r12
salq $2, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movl %r15d, %edi
imull %r15d, %edi
movslq %edi, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, 16(%rsp)
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbx
movq %r12, %rdi
call malloc@PLT
movq %rax, %r12
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %r14d, %r14d
jle .L28
.L60:
movl %r15d, 24(%rsp)
movl $0, %esi
movl $0, %r14d
movslq %r15d, %rax
movq %rax, 32(%rsp)
movq %rbp, 40(%rsp)
movq %rbx, 48(%rsp)
movq %r12, 56(%rsp)
movq 8(%rsp), %r12
movl %esi, %r13d
jmp .L29
.L25:
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 4(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %r15d
jmp .L27
.L32:
movslq %r13d, %rax
leaq (%r12,%rax,4), %rbx
movq 32(%rsp), %rsi
addq %rsi, %rax
leaq (%r12,%rax,4), %rbp
.L30:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L30
.L33:
addl $1, %r14d
movl 24(%rsp), %eax
addl %eax, %r13d
cmpl %r14d, 4(%rsp)
je .L31
.L29:
testl %r15d, %r15d
jg .L32
jmp .L33
.L62:
movl %ebp, %r8d
movq 24(%rsp), %rbp
movq 32(%rsp), %rbx
movq %r12, %rsi
movq 40(%rsp), %r12
movq %r13, %rcx
movq %rsi, %rdx
movl $0, %edi
.L36:
leaq (%rdx,%rcx), %rax
.L37:
movl $0x00000000, 0(%rbp,%rax)
movl $0x00000000, (%rbx,%rax)
movl $0x00000000, (%r12,%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L37
leal 1(%rdi), %eax
addq %rsi, %rdx
cmpl %edi, %r8d
je .L38
movl %eax, %edi
jmp .L36
.L38:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
cmpl $0, 4(%rsp)
jle .L39
.L56:
movl %r15d, %r13d
movslq %r15d, %r11
leaq 0(,%r11,4), %rdi
movl $0, %edx
movl $0, %eax
movl $0, %r14d
movl %r15d, 24(%rsp)
movq %rbp, %rsi
movq %rbx, 32(%rsp)
movq %r12, 40(%rsp)
jmp .L40
.L43:
movq %rbx, %r8
movq %r12, %rcx
movl %r14d, %r15d
.L41:
movss (%rcx), %xmm0
mulss (%r8), %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl %r15d, %xmm1
addss %xmm1, %xmm0
cvttss2sil %xmm0, %r15d
addq $4, %rcx
addq %rdi, %r8
cmpq %r9, %rcx
jne .L41
pxor %xmm0, %xmm0
cvtsi2ssl %r15d, %xmm0
movss %xmm0, 0(%rbp,%r10,4)
addq $1, %r10
addq $4, %rbx
cmpq %r10, %r11
jne .L43
.L42:
addl $1, %eax
addl %r13d, %edx
cmpl %eax, 4(%rsp)
je .L76
.L40:
cmpl $0, 24(%rsp)
jle .L42
movq 16(%rsp), %rbx
movslq %edx, %r8
leaq 0(,%r8,4), %rbp
movq 8(%rsp), %rcx
leaq (%rcx,%rbp), %r12
addq %r11, %r8
leaq (%rcx,%r8,4), %r9
addq %rsi, %rbp
movl $0, %r10d
jmp .L43
.L76:
movl 24(%rsp), %r15d
movq %rsi, %rbp
movq 32(%rsp), %rbx
movq 40(%rsp), %r12
.L39:
movl $0, %esi
movq 80(%rsp), %rdi
call cudaEventRecord@PLT
movq 80(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 68(%rsp), %r13
movq 80(%rsp), %rdx
movq 72(%rsp), %rsi
movq %r13, %rdi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 68(%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
movl %r15d, %r9d
movl %r15d, %r8d
movl 4(%rsp), %ecx
movq %rbx, %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z8MM_BasicPfS_S_iii
movl $0, %esi
movq 80(%rsp), %rdi
call cudaEventRecord@PLT
movq 80(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 80(%rsp), %rdx
movq 72(%rsp), %rsi
movq %r13, %rdi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 68(%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
testl %r15d, %r15d
jle .L44
movslq %r15d, %rsi
leaq 0(,%rsi,4), %r8
movq %rbp, %rdx
movq %rbx, %rax
movl $0, %edi
jmp .L45
.L63:
movl %edi, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
movl %r15d, %r9d
movl %r15d, %r8d
movl 4(%rsp), %ecx
movq %r12, %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z11MM_ImprovedPfS_S_iii
movl $0, %esi
movq 80(%rsp), %rdi
call cudaEventRecord@PLT
movq 80(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 68(%rsp), %rdi
movq 80(%rsp), %rdx
movq 72(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 68(%rsp), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
.L48:
movslq %r15d, %rsi
leaq 0(,%rsi,4), %r8
movq %rbp, %rdx
movq %r12, %rax
movl $0, %edi
jmp .L51
.L80:
addl $1, %edi
addq %r8, %rdx
addq %r8, %rax
cmpl %edi, %r15d
je .L44
.L45:
movl $0, %ecx
.L49:
movss (%rdx,%rcx,4), %xmm0
ucomiss (%rax,%rcx,4), %xmm0
jp .L63
jne .L63
addq $1, %rcx
cmpq %rsi, %rcx
jne .L49
jmp .L80
.L44:
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
movl %r15d, %r9d
movl %r15d, %r8d
movl 4(%rsp), %ecx
movq %r12, %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z11MM_ImprovedPfS_S_iii
movl $0, %esi
movq 80(%rsp), %rdi
call cudaEventRecord@PLT
movq 80(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 68(%rsp), %rdi
movq 80(%rsp), %rdx
movq 72(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 68(%rsp), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
testl %r15d, %r15d
jg .L48
.L50:
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L54
.L64:
movl %edi, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L54:
movq 8(%rsp), %rdi
call free@PLT
movq 16(%rsp), %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L81
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L82:
.cfi_restore_state
addl $1, %edi
addq %r8, %rdx
addq %r8, %rax
cmpl %edi, %r15d
je .L50
.L51:
movl $0, %ecx
.L55:
movss (%rdx,%rcx,4), %xmm0
ucomiss (%rax,%rcx,4), %xmm0
jp .L64
jne .L64
addq $1, %rcx
cmpq %rcx, %rsi
jne .L55
jmp .L82
.L83:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
jmp .L56
.L31:
movq 40(%rsp), %rbp
movq 48(%rsp), %rbx
movq 56(%rsp), %r12
testl %r15d, %r15d
jle .L83
.L57:
movslq %r15d, %rax
leaq 0(,%rax,4), %rsi
movq 16(%rsp), %rdi
leaq (%rdi,%rsi), %r14
negq %rax
leaq 0(,%rax,4), %rcx
movl $0, %r8d
movq %rbp, 24(%rsp)
movl %r8d, %ebp
movq %rbx, 32(%rsp)
movq %r12, 40(%rsp)
movq %rsi, %r12
movq %rcx, %r13
.L34:
leaq (%r14,%r13), %rbx
.L35:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %r14, %rbx
jne .L35
leal 1(%rbp), %eax
addq %r12, %r14
cmpl %eax, %r15d
je .L62
movl %eax, %ebp
jmp .L34
.L28:
testl %r15d, %r15d
jg .L57
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
jmp .L39
.L81:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.globl _Z45__device_stub__Z18MM_Improved_kernelPfS_S_iiiPfS_S_iii
.type _Z45__device_stub__Z18MM_Improved_kernelPfS_S_iiiPfS_S_iii, @function
_Z45__device_stub__Z18MM_Improved_kernelPfS_S_iiiPfS_S_iii:
.LFB2086:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L88
.L84:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L89
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L88:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z18MM_Improved_kernelPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L84
.L89:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z45__device_stub__Z18MM_Improved_kernelPfS_S_iiiPfS_S_iii, .-_Z45__device_stub__Z18MM_Improved_kernelPfS_S_iiiPfS_S_iii
.globl _Z18MM_Improved_kernelPfS_S_iii
.type _Z18MM_Improved_kernelPfS_S_iii, @function
_Z18MM_Improved_kernelPfS_S_iii:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z18MM_Improved_kernelPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z18MM_Improved_kernelPfS_S_iii, .-_Z18MM_Improved_kernelPfS_S_iii
.section .rodata.str1.8
.align 8
.LC11:
.string "_Z18MM_Improved_kernelPfS_S_iii"
.section .rodata.str1.1
.LC12:
.string "_Z15MM_Basic_kernelPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z18MM_Improved_kernelPfS_S_iii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z15MM_Basic_kernelPfS_S_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <ctime>
#include <stdlib.h>
#include <sys/time.h>
// Thread block size
#define BLOCK_SIZE 16
#define TILE_SIZE 32
#define ROW 1024
#define COL 1024
// GPU Functions
void MM_Basic(float *a, float *b, float *c, int row, int col, int k);
__global__ void MM_Basic_kernel( float *devA, float *devB, float *devC, int row, int col, int k);
void MM_Improved(float *a, float *b, float *c, int row, int col, int k);
__global__ void MM_Improved_kernel( float *devA, float *devB, float *devC, int row, int col, int k);
/*
* Main function
*/
int main(int argC, char** argV) {
//
// Setup
//////////////////
// Time Variables
float time;
cudaEvent_t start, stop;
cudaEventCreate (&start);
cudaEventCreate (&stop);
// Matrices
float *a, *b;
float *c_cpu, *c_gpu_basic, *c_gpu_improved;
//Setting matrix parameters.
int row = ROW;
int col = COL;
int k = COL;
int sum = 0;
// Process input arguments (if specified)
switch (argC) {
case 2: {
row = atoi(argV[1]);
col = row;
k = col;
break;
}
case 3: {
row = atoi(argV[1]);
col = atoi(argV[2]);
k = col;
break;
}
default: {
//Nothing
}
}
//Setting host memory space.
a = (float *) malloc(row*k*sizeof(float));
b = (float *) malloc(k*col*sizeof(float));
c_cpu = (float *) malloc(row*col*sizeof(float));
c_gpu_basic = (float *) malloc(row*col*sizeof(float));
c_gpu_improved = (float *) malloc(row*col*sizeof(float));
//Initializing [A] and [B] with random values from 1 to 10, and C to 0
printf ("Initializing Matricies, could take some time...\n");
for(int i = 0 ; i < row ; i++ ){
for(int j = 0 ; j < k ; j++ ){
a[i*k+j] = rand()%10;
}
}
for(int i = 0 ; i < k ; i++ ){
for(int j = 0 ; j < col ; j++ ){
b[i*col+j] = rand()%10;
}
}
for(int i = 0 ; i < k ; i++ ){
for(int j = 0 ; j < col ; j++ ){
c_cpu [i*col+j] = 0;
c_gpu_basic [i*col+j] = 0;
c_gpu_improved [i*col+j] = 0;
}
}
//
// CPU Calculation
//////////////////
printf("Running sequential job.\n");
cudaEventRecord(start,0);
for(int i = 0 ; i < row ; i++ ){
for(int j = 0 ; j < col ; j++ ){
sum = 0;
for(int w = 0 ; w < k ; w++ ){
sum += a[i*k+w] * b[w*col+j];
}
c_cpu[i*col+j] = sum;
}
}
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
printf("\tSequential Job Time: %.2f ms\n", time);
//
// Basic GPU Calculation
////////////////////////
printf("Running Basic parallel job.\n");
cudaEventRecord(start,0);
MM_Basic(a, b, c_gpu_basic, row, col, k);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
printf("\tBasic Parallel Job Time: %.2f ms\n", time);
// Compares matrices to make sure answer is correct, initializes c for next kernel.
bool error = false;
for(int i = 0 ; i < k ; i++ ){
for(int j = 0 ; j < col ; j++ ){
if (c_cpu[i*col+j] != c_gpu_basic[i*col+j]) {
printf("\tError: Starting at [%d][%d]\n", i, j);
error = true;
}
if (error) break;
}
if (error) break;
}
if (!error) printf("\tNo errors found.\n");
//
// Improved GPU Calculation
////////////////////////
printf("Running Improved parallel job.\n");
cudaEventRecord(start,0);
MM_Improved(a, b, c_gpu_improved, row, col, k);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
printf("\tImproved Parallel Job Time: %.2f ms\n", time);
// Compares matrices to make sure answer is correct, initializes c for next kernel.
error = false;
for(int i = 0 ; i < k ; i++ ){
for(int j = 0 ; j < col ; j++ ){
if (c_cpu[i*col+j] != c_gpu_improved[i*col+j]) {
printf("\tError: Starting at [%d][%d]\n", i, j);
error = true;
}
if (error) break;
}
if (error) break;
}
if (!error) printf("\tNo errors found.\n");
free (a);
free (b);
free (c_cpu);
free (c_gpu_basic);
free (c_gpu_improved);
}
void MM_Basic(float *a, float *b, float *c, int row, int col, int k) {
cudaEvent_t kernelstart, kernelstop;
float time;
cudaEventCreate (&kernelstart);
cudaEventCreate (&kernelstop);
int sizeA = row*k*sizeof(float);
int sizeB = k*col*sizeof(float);
int sizeC = row*col*sizeof(float);
float *devA, *devB, *devC;
cudaMalloc((void**)&devA, sizeA);
cudaMalloc((void**)&devB, sizeB);
cudaMalloc((void**)&devC, sizeC);
cudaMemcpy(devA, a, sizeA, cudaMemcpyHostToDevice);
cudaMemcpy(devB, b, sizeB, cudaMemcpyHostToDevice);
dim3 dimBlock(16, 16, 1);
dim3 dimGrid((COL+dimBlock.x-1)/dimBlock.x, (ROW+dimBlock.y-1)/dimBlock.y, 1);
cudaEventRecord(kernelstart,0);
MM_Basic_kernel<<<dimGrid, dimBlock>>>(devA, devB, devC, row, col, k);
cudaEventRecord(kernelstop,0);
cudaEventSynchronize(kernelstop);
cudaEventElapsedTime(&time, kernelstart, kernelstop);
printf("\tKernel Job Time: %.2f ms\n", time);
cudaMemcpy(c, devC, sizeC, cudaMemcpyDeviceToHost);
//Freeing device matrices.
cudaFree(devA); cudaFree(devB); cudaFree(devC);
}
__global__ void MM_Basic_kernel( float *devA, float *devB, float *devC, int row, int col, int k) {
int txID = blockIdx.x * blockDim.x + threadIdx.x;
int tyID = blockIdx.y * blockDim.y + threadIdx.y;
if ((txID < col) && (tyID < row)) {
float Pvalue = 0;
for(int w = 0 ; w < k ; w++) {
Pvalue += devA[tyID*k+w] * devB[w*k+txID];
}
devC[tyID*k+txID] = Pvalue;
}
}
void MM_Improved(float *a, float *b, float *c, int row, int col, int k){
// Write Code here
cudaEvent_t kernelstart, kernelstop;
float time;
cudaEventCreate (&kernelstart);
cudaEventCreate (&kernelstop);
int sizeA = row*k*sizeof(float);
int sizeB = k*col*sizeof(float);
int sizeC = row*col*sizeof(float);
float *devA, *devB, *devC;
cudaMalloc((void**)&devA, sizeA);
cudaMalloc((void**)&devB, sizeB);
cudaMalloc((void**)&devC, sizeC);
cudaMemcpy(devA, a, sizeA, cudaMemcpyHostToDevice);
cudaMemcpy(devB, b, sizeB, cudaMemcpyHostToDevice);
dim3 dimBlock(32, 32, 1);
dim3 dimGrid((COL+dimBlock.x-1)/dimBlock.x, (ROW+dimBlock.y-1)/dimBlock.y, 1);
cudaEventRecord(kernelstart,0);
MM_Basic_kernel<<<dimGrid, dimBlock>>>(devA, devB, devC, row, col, k);
cudaEventRecord(kernelstop,0);
cudaEventSynchronize(kernelstop);
cudaEventElapsedTime(&time, kernelstart, kernelstop);
printf("\tKernel Job Time: %.2f ms\n", time);
cudaMemcpy(c, devC, sizeC, cudaMemcpyDeviceToHost);
//Freeing device matrices.
cudaFree(devA); cudaFree(devB); cudaFree(devC);
}
__global__ void MM_Improved_kernel( float *devA, float *devB, float *devC, int row, int col, int k){
// Write Code here
__shared__ int shareBlockA[TILE_SIZE][TILE_SIZE];
__shared__ int shareBlockB[TILE_SIZE][TILE_SIZE];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int Row = by * TILE_SIZE + ty;
int Col = bx * TILE_SIZE + tx;
float Cvalue = 0;
for (int m = 0; m < row/TILE_SIZE; ++m) {
shareBlockA[ty][tx] = devA[Row * row + (m*TILE_SIZE + tx)];
shareBlockB[ty][tx] = devB[Col + (m * TILE_SIZE + ty) * row];
__syncthreads();
for (int k = 0; k < TILE_SIZE; ++k)
Cvalue += shareBlockA[ty][k] * shareBlockB[k][tx];
__syncthreads();
}
devC[Row*row+Col] = Cvalue;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <ctime>
#include <stdlib.h>
#include <sys/time.h>
// Thread block size
#define BLOCK_SIZE 16
#define TILE_SIZE 32
#define ROW 1024
#define COL 1024
// GPU Functions
void MM_Basic(float *a, float *b, float *c, int row, int col, int k);
__global__ void MM_Basic_kernel( float *devA, float *devB, float *devC, int row, int col, int k);
void MM_Improved(float *a, float *b, float *c, int row, int col, int k);
__global__ void MM_Improved_kernel( float *devA, float *devB, float *devC, int row, int col, int k);
/*
* Main function
*/
int main(int argC, char** argV) {
//
// Setup
//////////////////
// Time Variables
float time;
hipEvent_t start, stop;
hipEventCreate (&start);
hipEventCreate (&stop);
// Matrices
float *a, *b;
float *c_cpu, *c_gpu_basic, *c_gpu_improved;
//Setting matrix parameters.
int row = ROW;
int col = COL;
int k = COL;
int sum = 0;
// Process input arguments (if specified)
switch (argC) {
case 2: {
row = atoi(argV[1]);
col = row;
k = col;
break;
}
case 3: {
row = atoi(argV[1]);
col = atoi(argV[2]);
k = col;
break;
}
default: {
//Nothing
}
}
//Setting host memory space.
a = (float *) malloc(row*k*sizeof(float));
b = (float *) malloc(k*col*sizeof(float));
c_cpu = (float *) malloc(row*col*sizeof(float));
c_gpu_basic = (float *) malloc(row*col*sizeof(float));
c_gpu_improved = (float *) malloc(row*col*sizeof(float));
//Initializing [A] and [B] with random values from 1 to 10, and C to 0
printf ("Initializing Matricies, could take some time...\n");
for(int i = 0 ; i < row ; i++ ){
for(int j = 0 ; j < k ; j++ ){
a[i*k+j] = rand()%10;
}
}
for(int i = 0 ; i < k ; i++ ){
for(int j = 0 ; j < col ; j++ ){
b[i*col+j] = rand()%10;
}
}
for(int i = 0 ; i < k ; i++ ){
for(int j = 0 ; j < col ; j++ ){
c_cpu [i*col+j] = 0;
c_gpu_basic [i*col+j] = 0;
c_gpu_improved [i*col+j] = 0;
}
}
//
// CPU Calculation
//////////////////
printf("Running sequential job.\n");
hipEventRecord(start,0);
for(int i = 0 ; i < row ; i++ ){
for(int j = 0 ; j < col ; j++ ){
sum = 0;
for(int w = 0 ; w < k ; w++ ){
sum += a[i*k+w] * b[w*col+j];
}
c_cpu[i*col+j] = sum;
}
}
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
printf("\tSequential Job Time: %.2f ms\n", time);
//
// Basic GPU Calculation
////////////////////////
printf("Running Basic parallel job.\n");
hipEventRecord(start,0);
MM_Basic(a, b, c_gpu_basic, row, col, k);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
printf("\tBasic Parallel Job Time: %.2f ms\n", time);
// Compares matrices to make sure answer is correct, initializes c for next kernel.
bool error = false;
for(int i = 0 ; i < k ; i++ ){
for(int j = 0 ; j < col ; j++ ){
if (c_cpu[i*col+j] != c_gpu_basic[i*col+j]) {
printf("\tError: Starting at [%d][%d]\n", i, j);
error = true;
}
if (error) break;
}
if (error) break;
}
if (!error) printf("\tNo errors found.\n");
//
// Improved GPU Calculation
////////////////////////
printf("Running Improved parallel job.\n");
hipEventRecord(start,0);
MM_Improved(a, b, c_gpu_improved, row, col, k);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
printf("\tImproved Parallel Job Time: %.2f ms\n", time);
// Compares matrices to make sure answer is correct, initializes c for next kernel.
error = false;
for(int i = 0 ; i < k ; i++ ){
for(int j = 0 ; j < col ; j++ ){
if (c_cpu[i*col+j] != c_gpu_improved[i*col+j]) {
printf("\tError: Starting at [%d][%d]\n", i, j);
error = true;
}
if (error) break;
}
if (error) break;
}
if (!error) printf("\tNo errors found.\n");
free (a);
free (b);
free (c_cpu);
free (c_gpu_basic);
free (c_gpu_improved);
}
void MM_Basic(float *a, float *b, float *c, int row, int col, int k) {
hipEvent_t kernelstart, kernelstop;
float time;
hipEventCreate (&kernelstart);
hipEventCreate (&kernelstop);
int sizeA = row*k*sizeof(float);
int sizeB = k*col*sizeof(float);
int sizeC = row*col*sizeof(float);
float *devA, *devB, *devC;
hipMalloc((void**)&devA, sizeA);
hipMalloc((void**)&devB, sizeB);
hipMalloc((void**)&devC, sizeC);
hipMemcpy(devA, a, sizeA, hipMemcpyHostToDevice);
hipMemcpy(devB, b, sizeB, hipMemcpyHostToDevice);
dim3 dimBlock(16, 16, 1);
dim3 dimGrid((COL+dimBlock.x-1)/dimBlock.x, (ROW+dimBlock.y-1)/dimBlock.y, 1);
hipEventRecord(kernelstart,0);
MM_Basic_kernel<<<dimGrid, dimBlock>>>(devA, devB, devC, row, col, k);
hipEventRecord(kernelstop,0);
hipEventSynchronize(kernelstop);
hipEventElapsedTime(&time, kernelstart, kernelstop);
printf("\tKernel Job Time: %.2f ms\n", time);
hipMemcpy(c, devC, sizeC, hipMemcpyDeviceToHost);
//Freeing device matrices.
hipFree(devA); hipFree(devB); hipFree(devC);
}
__global__ void MM_Basic_kernel( float *devA, float *devB, float *devC, int row, int col, int k) {
int txID = blockIdx.x * blockDim.x + threadIdx.x;
int tyID = blockIdx.y * blockDim.y + threadIdx.y;
if ((txID < col) && (tyID < row)) {
float Pvalue = 0;
for(int w = 0 ; w < k ; w++) {
Pvalue += devA[tyID*k+w] * devB[w*k+txID];
}
devC[tyID*k+txID] = Pvalue;
}
}
void MM_Improved(float *a, float *b, float *c, int row, int col, int k){
// Write Code here
hipEvent_t kernelstart, kernelstop;
float time;
hipEventCreate (&kernelstart);
hipEventCreate (&kernelstop);
int sizeA = row*k*sizeof(float);
int sizeB = k*col*sizeof(float);
int sizeC = row*col*sizeof(float);
float *devA, *devB, *devC;
hipMalloc((void**)&devA, sizeA);
hipMalloc((void**)&devB, sizeB);
hipMalloc((void**)&devC, sizeC);
hipMemcpy(devA, a, sizeA, hipMemcpyHostToDevice);
hipMemcpy(devB, b, sizeB, hipMemcpyHostToDevice);
dim3 dimBlock(32, 32, 1);
dim3 dimGrid((COL+dimBlock.x-1)/dimBlock.x, (ROW+dimBlock.y-1)/dimBlock.y, 1);
hipEventRecord(kernelstart,0);
MM_Basic_kernel<<<dimGrid, dimBlock>>>(devA, devB, devC, row, col, k);
hipEventRecord(kernelstop,0);
hipEventSynchronize(kernelstop);
hipEventElapsedTime(&time, kernelstart, kernelstop);
printf("\tKernel Job Time: %.2f ms\n", time);
hipMemcpy(c, devC, sizeC, hipMemcpyDeviceToHost);
//Freeing device matrices.
hipFree(devA); hipFree(devB); hipFree(devC);
}
__global__ void MM_Improved_kernel( float *devA, float *devB, float *devC, int row, int col, int k){
// Write Code here
__shared__ int shareBlockA[TILE_SIZE][TILE_SIZE];
__shared__ int shareBlockB[TILE_SIZE][TILE_SIZE];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int Row = by * TILE_SIZE + ty;
int Col = bx * TILE_SIZE + tx;
float Cvalue = 0;
for (int m = 0; m < row/TILE_SIZE; ++m) {
shareBlockA[ty][tx] = devA[Row * row + (m*TILE_SIZE + tx)];
shareBlockB[ty][tx] = devB[Col + (m * TILE_SIZE + ty) * row];
__syncthreads();
for (int k = 0; k < TILE_SIZE; ++k)
Cvalue += shareBlockA[ty][k] * shareBlockB[k][tx];
__syncthreads();
}
devC[Row*row+Col] = Cvalue;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <ctime>
#include <stdlib.h>
#include <sys/time.h>
// Thread block size
#define BLOCK_SIZE 16
#define TILE_SIZE 32
#define ROW 1024
#define COL 1024
// GPU Functions
void MM_Basic(float *a, float *b, float *c, int row, int col, int k);
__global__ void MM_Basic_kernel( float *devA, float *devB, float *devC, int row, int col, int k);
void MM_Improved(float *a, float *b, float *c, int row, int col, int k);
__global__ void MM_Improved_kernel( float *devA, float *devB, float *devC, int row, int col, int k);
/*
* Main function
*/
int main(int argC, char** argV) {
//
// Setup
//////////////////
// Time Variables
float time;
hipEvent_t start, stop;
hipEventCreate (&start);
hipEventCreate (&stop);
// Matrices
float *a, *b;
float *c_cpu, *c_gpu_basic, *c_gpu_improved;
//Setting matrix parameters.
int row = ROW;
int col = COL;
int k = COL;
int sum = 0;
// Process input arguments (if specified)
switch (argC) {
case 2: {
row = atoi(argV[1]);
col = row;
k = col;
break;
}
case 3: {
row = atoi(argV[1]);
col = atoi(argV[2]);
k = col;
break;
}
default: {
//Nothing
}
}
//Setting host memory space.
a = (float *) malloc(row*k*sizeof(float));
b = (float *) malloc(k*col*sizeof(float));
c_cpu = (float *) malloc(row*col*sizeof(float));
c_gpu_basic = (float *) malloc(row*col*sizeof(float));
c_gpu_improved = (float *) malloc(row*col*sizeof(float));
//Initializing [A] and [B] with random values from 1 to 10, and C to 0
printf ("Initializing Matricies, could take some time...\n");
for(int i = 0 ; i < row ; i++ ){
for(int j = 0 ; j < k ; j++ ){
a[i*k+j] = rand()%10;
}
}
for(int i = 0 ; i < k ; i++ ){
for(int j = 0 ; j < col ; j++ ){
b[i*col+j] = rand()%10;
}
}
for(int i = 0 ; i < k ; i++ ){
for(int j = 0 ; j < col ; j++ ){
c_cpu [i*col+j] = 0;
c_gpu_basic [i*col+j] = 0;
c_gpu_improved [i*col+j] = 0;
}
}
//
// CPU Calculation
//////////////////
printf("Running sequential job.\n");
hipEventRecord(start,0);
for(int i = 0 ; i < row ; i++ ){
for(int j = 0 ; j < col ; j++ ){
sum = 0;
for(int w = 0 ; w < k ; w++ ){
sum += a[i*k+w] * b[w*col+j];
}
c_cpu[i*col+j] = sum;
}
}
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
printf("\tSequential Job Time: %.2f ms\n", time);
//
// Basic GPU Calculation
////////////////////////
printf("Running Basic parallel job.\n");
hipEventRecord(start,0);
MM_Basic(a, b, c_gpu_basic, row, col, k);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
printf("\tBasic Parallel Job Time: %.2f ms\n", time);
// Compares matrices to make sure answer is correct, initializes c for next kernel.
bool error = false;
for(int i = 0 ; i < k ; i++ ){
for(int j = 0 ; j < col ; j++ ){
if (c_cpu[i*col+j] != c_gpu_basic[i*col+j]) {
printf("\tError: Starting at [%d][%d]\n", i, j);
error = true;
}
if (error) break;
}
if (error) break;
}
if (!error) printf("\tNo errors found.\n");
//
// Improved GPU Calculation
////////////////////////
printf("Running Improved parallel job.\n");
hipEventRecord(start,0);
MM_Improved(a, b, c_gpu_improved, row, col, k);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
printf("\tImproved Parallel Job Time: %.2f ms\n", time);
// Compares matrices to make sure answer is correct, initializes c for next kernel.
error = false;
for(int i = 0 ; i < k ; i++ ){
for(int j = 0 ; j < col ; j++ ){
if (c_cpu[i*col+j] != c_gpu_improved[i*col+j]) {
printf("\tError: Starting at [%d][%d]\n", i, j);
error = true;
}
if (error) break;
}
if (error) break;
}
if (!error) printf("\tNo errors found.\n");
free (a);
free (b);
free (c_cpu);
free (c_gpu_basic);
free (c_gpu_improved);
}
void MM_Basic(float *a, float *b, float *c, int row, int col, int k) {
hipEvent_t kernelstart, kernelstop;
float time;
hipEventCreate (&kernelstart);
hipEventCreate (&kernelstop);
int sizeA = row*k*sizeof(float);
int sizeB = k*col*sizeof(float);
int sizeC = row*col*sizeof(float);
float *devA, *devB, *devC;
hipMalloc((void**)&devA, sizeA);
hipMalloc((void**)&devB, sizeB);
hipMalloc((void**)&devC, sizeC);
hipMemcpy(devA, a, sizeA, hipMemcpyHostToDevice);
hipMemcpy(devB, b, sizeB, hipMemcpyHostToDevice);
dim3 dimBlock(16, 16, 1);
dim3 dimGrid((COL+dimBlock.x-1)/dimBlock.x, (ROW+dimBlock.y-1)/dimBlock.y, 1);
hipEventRecord(kernelstart,0);
MM_Basic_kernel<<<dimGrid, dimBlock>>>(devA, devB, devC, row, col, k);
hipEventRecord(kernelstop,0);
hipEventSynchronize(kernelstop);
hipEventElapsedTime(&time, kernelstart, kernelstop);
printf("\tKernel Job Time: %.2f ms\n", time);
hipMemcpy(c, devC, sizeC, hipMemcpyDeviceToHost);
//Freeing device matrices.
hipFree(devA); hipFree(devB); hipFree(devC);
}
__global__ void MM_Basic_kernel( float *devA, float *devB, float *devC, int row, int col, int k) {
int txID = blockIdx.x * blockDim.x + threadIdx.x;
int tyID = blockIdx.y * blockDim.y + threadIdx.y;
if ((txID < col) && (tyID < row)) {
float Pvalue = 0;
for(int w = 0 ; w < k ; w++) {
Pvalue += devA[tyID*k+w] * devB[w*k+txID];
}
devC[tyID*k+txID] = Pvalue;
}
}
void MM_Improved(float *a, float *b, float *c, int row, int col, int k){
// Write Code here
hipEvent_t kernelstart, kernelstop;
float time;
hipEventCreate (&kernelstart);
hipEventCreate (&kernelstop);
int sizeA = row*k*sizeof(float);
int sizeB = k*col*sizeof(float);
int sizeC = row*col*sizeof(float);
float *devA, *devB, *devC;
hipMalloc((void**)&devA, sizeA);
hipMalloc((void**)&devB, sizeB);
hipMalloc((void**)&devC, sizeC);
hipMemcpy(devA, a, sizeA, hipMemcpyHostToDevice);
hipMemcpy(devB, b, sizeB, hipMemcpyHostToDevice);
dim3 dimBlock(32, 32, 1);
dim3 dimGrid((COL+dimBlock.x-1)/dimBlock.x, (ROW+dimBlock.y-1)/dimBlock.y, 1);
hipEventRecord(kernelstart,0);
MM_Basic_kernel<<<dimGrid, dimBlock>>>(devA, devB, devC, row, col, k);
hipEventRecord(kernelstop,0);
hipEventSynchronize(kernelstop);
hipEventElapsedTime(&time, kernelstart, kernelstop);
printf("\tKernel Job Time: %.2f ms\n", time);
hipMemcpy(c, devC, sizeC, hipMemcpyDeviceToHost);
//Freeing device matrices.
hipFree(devA); hipFree(devB); hipFree(devC);
}
__global__ void MM_Improved_kernel( float *devA, float *devB, float *devC, int row, int col, int k){
// Write Code here
__shared__ int shareBlockA[TILE_SIZE][TILE_SIZE];
__shared__ int shareBlockB[TILE_SIZE][TILE_SIZE];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int Row = by * TILE_SIZE + ty;
int Col = bx * TILE_SIZE + tx;
float Cvalue = 0;
for (int m = 0; m < row/TILE_SIZE; ++m) {
shareBlockA[ty][tx] = devA[Row * row + (m*TILE_SIZE + tx)];
shareBlockB[ty][tx] = devB[Col + (m * TILE_SIZE + ty) * row];
__syncthreads();
for (int k = 0; k < TILE_SIZE; ++k)
Cvalue += shareBlockA[ty][k] * shareBlockB[k][tx];
__syncthreads();
}
devC[Row*row+Col] = Cvalue;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15MM_Basic_kernelPfS_S_iii
.globl _Z15MM_Basic_kernelPfS_S_iii
.p2align 8
.type _Z15MM_Basic_kernelPfS_S_iii,@function
_Z15MM_Basic_kernelPfS_S_iii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s2, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_6
s_load_b32 s2, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v1, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v0
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v1, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15MM_Basic_kernelPfS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15MM_Basic_kernelPfS_S_iii, .Lfunc_end0-_Z15MM_Basic_kernelPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z18MM_Improved_kernelPfS_S_iii
.globl _Z18MM_Improved_kernelPfS_S_iii
.p2align 8
.type _Z18MM_Improved_kernelPfS_S_iii,@function
_Z18MM_Improved_kernelPfS_S_iii:
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v5, v0, 10, 10
v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v3, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v4, s15, 5, v5
v_lshl_add_u32 v0, s14, 5, v3
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 32
s_cbranch_scc1 .LBB1_5
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v8, 2, v3
v_lshlrev_b32_e32 v6, 7, v5
s_ashr_i32 s3, s2, 31
v_mad_u64_u32 v[1:2], null, v4, s2, v[3:4]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_or_b32_e32 v7, 0x1000, v8
s_lshr_b32 s3, s3, 27
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v3, v6, v8
s_add_i32 s3, s2, s3
v_add_nc_u32_e32 v8, v7, v6
s_ashr_i32 s3, s3, 5
s_mov_b32 s8, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB1_2:
s_lshl_b32 s9, s8, 5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v10, s9, v5
v_add_nc_u32_e32 v9, s9, v1
s_mov_b32 s9, 0
v_mad_u64_u32 v[11:12], null, v10, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v12, 31, v11
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, vcc_lo, s4, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v11, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
global_load_b32 v9, v[9:10], off
global_load_b32 v10, v[11:12], off
s_waitcnt vmcnt(1)
v_cvt_i32_f32_e32 v11, v9
v_mov_b32_e32 v9, v7
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v10, v10
ds_store_b32 v3, v11
ds_store_b32 v8, v10
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB1_3:
v_add_nc_u32_e32 v10, s9, v6
s_add_i32 s9, s9, 4
ds_load_b32 v11, v9
ds_load_b32 v10, v10
s_cmpk_eq_i32 s9, 0x80
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v10, v11, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v10, v10
v_dual_add_f32 v2, v2, v10 :: v_dual_add_nc_u32 v9, 0x80, v9
s_cbranch_scc0 .LBB1_3
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s8, s3
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB1_2
.LBB1_5:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[5:6], null, v4, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[0:1], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18MM_Improved_kernelPfS_S_iii
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z18MM_Improved_kernelPfS_S_iii, .Lfunc_end1-_Z18MM_Improved_kernelPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15MM_Basic_kernelPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15MM_Basic_kernelPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18MM_Improved_kernelPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18MM_Improved_kernelPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <ctime>
#include <stdlib.h>
#include <sys/time.h>
// Thread block size
#define BLOCK_SIZE 16
#define TILE_SIZE 32
#define ROW 1024
#define COL 1024
// GPU Functions
void MM_Basic(float *a, float *b, float *c, int row, int col, int k);
__global__ void MM_Basic_kernel( float *devA, float *devB, float *devC, int row, int col, int k);
void MM_Improved(float *a, float *b, float *c, int row, int col, int k);
__global__ void MM_Improved_kernel( float *devA, float *devB, float *devC, int row, int col, int k);
/*
* Main function
*/
int main(int argC, char** argV) {
//
// Setup
//////////////////
// Time Variables
float time;
hipEvent_t start, stop;
hipEventCreate (&start);
hipEventCreate (&stop);
// Matrices
float *a, *b;
float *c_cpu, *c_gpu_basic, *c_gpu_improved;
//Setting matrix parameters.
int row = ROW;
int col = COL;
int k = COL;
int sum = 0;
// Process input arguments (if specified)
switch (argC) {
case 2: {
row = atoi(argV[1]);
col = row;
k = col;
break;
}
case 3: {
row = atoi(argV[1]);
col = atoi(argV[2]);
k = col;
break;
}
default: {
//Nothing
}
}
//Setting host memory space.
a = (float *) malloc(row*k*sizeof(float));
b = (float *) malloc(k*col*sizeof(float));
c_cpu = (float *) malloc(row*col*sizeof(float));
c_gpu_basic = (float *) malloc(row*col*sizeof(float));
c_gpu_improved = (float *) malloc(row*col*sizeof(float));
//Initializing [A] and [B] with random values from 1 to 10, and C to 0
printf ("Initializing Matricies, could take some time...\n");
for(int i = 0 ; i < row ; i++ ){
for(int j = 0 ; j < k ; j++ ){
a[i*k+j] = rand()%10;
}
}
for(int i = 0 ; i < k ; i++ ){
for(int j = 0 ; j < col ; j++ ){
b[i*col+j] = rand()%10;
}
}
for(int i = 0 ; i < k ; i++ ){
for(int j = 0 ; j < col ; j++ ){
c_cpu [i*col+j] = 0;
c_gpu_basic [i*col+j] = 0;
c_gpu_improved [i*col+j] = 0;
}
}
//
// CPU Calculation
//////////////////
printf("Running sequential job.\n");
hipEventRecord(start,0);
for(int i = 0 ; i < row ; i++ ){
for(int j = 0 ; j < col ; j++ ){
sum = 0;
for(int w = 0 ; w < k ; w++ ){
sum += a[i*k+w] * b[w*col+j];
}
c_cpu[i*col+j] = sum;
}
}
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
printf("\tSequential Job Time: %.2f ms\n", time);
//
// Basic GPU Calculation
////////////////////////
printf("Running Basic parallel job.\n");
hipEventRecord(start,0);
MM_Basic(a, b, c_gpu_basic, row, col, k);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
printf("\tBasic Parallel Job Time: %.2f ms\n", time);
// Compares matrices to make sure answer is correct, initializes c for next kernel.
bool error = false;
for(int i = 0 ; i < k ; i++ ){
for(int j = 0 ; j < col ; j++ ){
if (c_cpu[i*col+j] != c_gpu_basic[i*col+j]) {
printf("\tError: Starting at [%d][%d]\n", i, j);
error = true;
}
if (error) break;
}
if (error) break;
}
if (!error) printf("\tNo errors found.\n");
//
// Improved GPU Calculation
////////////////////////
printf("Running Improved parallel job.\n");
hipEventRecord(start,0);
MM_Improved(a, b, c_gpu_improved, row, col, k);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
printf("\tImproved Parallel Job Time: %.2f ms\n", time);
// Compares matrices to make sure answer is correct, initializes c for next kernel.
error = false;
for(int i = 0 ; i < k ; i++ ){
for(int j = 0 ; j < col ; j++ ){
if (c_cpu[i*col+j] != c_gpu_improved[i*col+j]) {
printf("\tError: Starting at [%d][%d]\n", i, j);
error = true;
}
if (error) break;
}
if (error) break;
}
if (!error) printf("\tNo errors found.\n");
free (a);
free (b);
free (c_cpu);
free (c_gpu_basic);
free (c_gpu_improved);
}
void MM_Basic(float *a, float *b, float *c, int row, int col, int k) {
hipEvent_t kernelstart, kernelstop;
float time;
hipEventCreate (&kernelstart);
hipEventCreate (&kernelstop);
int sizeA = row*k*sizeof(float);
int sizeB = k*col*sizeof(float);
int sizeC = row*col*sizeof(float);
float *devA, *devB, *devC;
hipMalloc((void**)&devA, sizeA);
hipMalloc((void**)&devB, sizeB);
hipMalloc((void**)&devC, sizeC);
hipMemcpy(devA, a, sizeA, hipMemcpyHostToDevice);
hipMemcpy(devB, b, sizeB, hipMemcpyHostToDevice);
dim3 dimBlock(16, 16, 1);
dim3 dimGrid((COL+dimBlock.x-1)/dimBlock.x, (ROW+dimBlock.y-1)/dimBlock.y, 1);
hipEventRecord(kernelstart,0);
MM_Basic_kernel<<<dimGrid, dimBlock>>>(devA, devB, devC, row, col, k);
hipEventRecord(kernelstop,0);
hipEventSynchronize(kernelstop);
hipEventElapsedTime(&time, kernelstart, kernelstop);
printf("\tKernel Job Time: %.2f ms\n", time);
hipMemcpy(c, devC, sizeC, hipMemcpyDeviceToHost);
//Freeing device matrices.
hipFree(devA); hipFree(devB); hipFree(devC);
}
__global__ void MM_Basic_kernel( float *devA, float *devB, float *devC, int row, int col, int k) {
int txID = blockIdx.x * blockDim.x + threadIdx.x;
int tyID = blockIdx.y * blockDim.y + threadIdx.y;
if ((txID < col) && (tyID < row)) {
float Pvalue = 0;
for(int w = 0 ; w < k ; w++) {
Pvalue += devA[tyID*k+w] * devB[w*k+txID];
}
devC[tyID*k+txID] = Pvalue;
}
}
void MM_Improved(float *a, float *b, float *c, int row, int col, int k){
// Write Code here
hipEvent_t kernelstart, kernelstop;
float time;
hipEventCreate (&kernelstart);
hipEventCreate (&kernelstop);
int sizeA = row*k*sizeof(float);
int sizeB = k*col*sizeof(float);
int sizeC = row*col*sizeof(float);
float *devA, *devB, *devC;
hipMalloc((void**)&devA, sizeA);
hipMalloc((void**)&devB, sizeB);
hipMalloc((void**)&devC, sizeC);
hipMemcpy(devA, a, sizeA, hipMemcpyHostToDevice);
hipMemcpy(devB, b, sizeB, hipMemcpyHostToDevice);
dim3 dimBlock(32, 32, 1);
dim3 dimGrid((COL+dimBlock.x-1)/dimBlock.x, (ROW+dimBlock.y-1)/dimBlock.y, 1);
hipEventRecord(kernelstart,0);
MM_Basic_kernel<<<dimGrid, dimBlock>>>(devA, devB, devC, row, col, k);
hipEventRecord(kernelstop,0);
hipEventSynchronize(kernelstop);
hipEventElapsedTime(&time, kernelstart, kernelstop);
printf("\tKernel Job Time: %.2f ms\n", time);
hipMemcpy(c, devC, sizeC, hipMemcpyDeviceToHost);
//Freeing device matrices.
hipFree(devA); hipFree(devB); hipFree(devC);
}
__global__ void MM_Improved_kernel( float *devA, float *devB, float *devC, int row, int col, int k){
// Write Code here
__shared__ int shareBlockA[TILE_SIZE][TILE_SIZE];
__shared__ int shareBlockB[TILE_SIZE][TILE_SIZE];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int Row = by * TILE_SIZE + ty;
int Col = bx * TILE_SIZE + tx;
float Cvalue = 0;
for (int m = 0; m < row/TILE_SIZE; ++m) {
shareBlockA[ty][tx] = devA[Row * row + (m*TILE_SIZE + tx)];
shareBlockB[ty][tx] = devB[Col + (m * TILE_SIZE + ty) * row];
__syncthreads();
for (int k = 0; k < TILE_SIZE; ++k)
Cvalue += shareBlockA[ty][k] * shareBlockB[k][tx];
__syncthreads();
}
devC[Row*row+Col] = Cvalue;
} | .text
.file "MatrixMul.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %r14d
leaq 24(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
cmpl $3, %r14d
je .LBB0_3
# %bb.1:
movl $1024, %r13d # imm = 0x400
movl $1024, %eax # imm = 0x400
cmpl $2, %r14d
jne .LBB0_4
# %bb.2:
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
jmp .LBB0_4
.LBB0_3:
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
.LBB0_4:
movq %rax, 16(%rsp) # 8-byte Spill
# kill: def $eax killed $eax killed $rax
imull %r13d, %eax
movslq %eax, %r12
shlq $2, %r12
movq %r12, %rdi
callq malloc
movq %rax, 32(%rsp) # 8-byte Spill
movq 16(%rsp), %rdi # 8-byte Reload
# kill: def $edi killed $edi killed $rdi def $rdi
imull %edi, %edi
shlq $2, %rdi
callq malloc
movq %rax, %rbp
movq %r12, %rdi
callq malloc
movq %rax, 64(%rsp) # 8-byte Spill
movq %r12, %rdi
callq malloc
movq %rax, 48(%rsp) # 8-byte Spill
movq %r12, %rdi
callq malloc
movq %rax, 56(%rsp) # 8-byte Spill
movl $.Lstr, %edi
callq puts@PLT
movq 16(%rsp), %rax # 8-byte Reload
movl %r13d, %ecx
movq %rcx, 80(%rsp) # 8-byte Spill
movl %eax, %r15d
movq %r13, 72(%rsp) # 8-byte Spill
testl %r13d, %r13d
jle .LBB0_10
# %bb.5: # %.preheader167.lr.ph
xorl %ebx, %ebx
xorl %r12d, %r12d
jmp .LBB0_6
.p2align 4, 0x90
.LBB0_9: # %._crit_edge
# in Loop: Header=BB0_6 Depth=1
incq %r12
movq 16(%rsp), %rax # 8-byte Reload
addl %eax, %ebx
cmpq 80(%rsp), %r12 # 8-byte Folded Reload
je .LBB0_10
.LBB0_6: # %.preheader167
# =>This Loop Header: Depth=1
# Child Loop BB0_8 Depth 2
testl %eax, %eax
jle .LBB0_9
# %bb.7: # %.lr.ph
# in Loop: Header=BB0_6 Depth=1
movl %ebx, %eax
movq 32(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB0_8: # Parent Loop BB0_6 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%r13,4)
incq %r13
cmpq %r13, %r15
jne .LBB0_8
jmp .LBB0_9
.LBB0_10: # %.preheader166
testl %eax, %eax
jle .LBB0_15
# %bb.11: # %.preheader165.lr.ph
xorl %ebx, %ebx
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_12: # %.preheader165
# =>This Loop Header: Depth=1
# Child Loop BB0_13 Depth 2
movl %ebx, %eax
leaq (,%rax,4), %r14
addq %rbp, %r14
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB0_13: # Parent Loop BB0_12 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%r13,4)
incq %r13
cmpq %r13, %r15
jne .LBB0_13
# %bb.14: # %._crit_edge172
# in Loop: Header=BB0_12 Depth=1
incq %r12
movq 16(%rsp), %rax # 8-byte Reload
addl %eax, %ebx
cmpq %r15, %r12
jne .LBB0_12
.LBB0_15: # %.preheader164
movq %rbp, 40(%rsp) # 8-byte Spill
testl %eax, %eax
movq 64(%rsp), %r13 # 8-byte Reload
movq 56(%rsp), %rdx # 8-byte Reload
movq %rax, %r12
jle .LBB0_18
# %bb.16: # %.preheader163.lr.ph
leaq (,%r15,4), %rax
movq %rax, 88(%rsp) # 8-byte Spill
xorl %ebp, %ebp
movq %r15, %r14
movq 88(%rsp), %rbx # 8-byte Reload
.p2align 4, 0x90
.LBB0_17: # %.preheader163
# =>This Inner Loop Header: Depth=1
movl %ebp, %eax
leaq (,%rax,4), %rdi
addq %r13, %rdi
movq %r13, %r12
movq 48(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r13
leaq (%rdx,%rax,4), %rax
movq %rax, 96(%rsp) # 8-byte Spill
xorl %esi, %esi
movq %rbx, %rdx
callq memset@PLT
movq %r13, %rdi
movq %r12, %r13
movq 16(%rsp), %r12 # 8-byte Reload
xorl %esi, %esi
movq %rbx, %rdx
callq memset@PLT
movq 96(%rsp), %rdi # 8-byte Reload
xorl %esi, %esi
movq %rbx, %rdx
callq memset@PLT
movq 56(%rsp), %rdx # 8-byte Reload
addl %r12d, %ebp
decq %r14
jne .LBB0_17
.LBB0_18: # %._crit_edge178
movl $.Lstr.1, %edi
callq puts@PLT
movq 24(%rsp), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq hipEventRecord
cmpl $0, 72(%rsp) # 4-byte Folded Reload
movq 48(%rsp), %r14 # 8-byte Reload
movq %r12, %rbp
jle .LBB0_26
# %bb.19: # %.preheader162.lr.ph
movslq %ebp, %rax
leaq (,%rax,4), %rcx
xorl %edx, %edx
jmp .LBB0_20
.p2align 4, 0x90
.LBB0_25: # %._crit_edge184
# in Loop: Header=BB0_20 Depth=1
incq %rdx
movq 16(%rsp), %rbp # 8-byte Reload
addl %ebp, %ebx
cmpq 80(%rsp), %rdx # 8-byte Folded Reload
je .LBB0_26
.LBB0_20: # %.preheader162
# =>This Loop Header: Depth=1
# Child Loop BB0_22 Depth 2
# Child Loop BB0_23 Depth 3
testl %ebp, %ebp
jle .LBB0_25
# %bb.21: # %.preheader161.lr.ph
# in Loop: Header=BB0_20 Depth=1
movl %ebx, %esi
movq 32(%rsp), %rdi # 8-byte Reload
leaq (%rdi,%rsi,4), %rsi
movq %rdx, %rdi
imulq %rax, %rdi
leaq (,%rdi,4), %rdi
addq %r13, %rdi
movq 40(%rsp), %r8 # 8-byte Reload
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB0_22: # %.preheader161
# Parent Loop BB0_20 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_23 Depth 3
xorl %r10d, %r10d
movq %r8, %r11
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_23: # Parent Loop BB0_20 Depth=1
# Parent Loop BB0_22 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rsi,%r10,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss (%r11), %xmm0
xorps %xmm1, %xmm1
cvtsi2ss %ebp, %xmm1
addss %xmm0, %xmm1
cvttss2si %xmm1, %ebp
incq %r10
addq %rcx, %r11
cmpq %r10, %r15
jne .LBB0_23
# %bb.24: # %._crit_edge182
# in Loop: Header=BB0_22 Depth=2
xorps %xmm0, %xmm0
cvtsi2ss %ebp, %xmm0
movss %xmm0, (%rdi,%r9,4)
incq %r9
addq $4, %r8
cmpq %r15, %r9
jne .LBB0_22
jmp .LBB0_25
.LBB0_26: # %._crit_edge186
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq (%rsp), %rdx
leaq 12(%rsp), %r12
movq %r12, %rdi
callq hipEventElapsedTime
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movl $.Lstr.2, %edi
callq puts@PLT
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rdi # 8-byte Reload
movq 40(%rsp), %rbx # 8-byte Reload
movq %rbx, %rsi
movq %r14, %rdx
movq 72(%rsp), %rcx # 8-byte Reload
# kill: def $ecx killed $ecx killed $rcx
movl %ebp, %r8d
movl %ebp, %r9d
callq _Z8MM_BasicPfS_S_iii
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq (%rsp), %rdx
movq %r12, %rdi
callq hipEventElapsedTime
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
testl %ebp, %ebp
jle .LBB0_36
# %bb.27: # %.preheader160.lr.ph
leaq (,%r15,4), %rbx
xorl %eax, %eax
movq %r13, %rbp
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_28: # %.preheader160
# =>This Loop Header: Depth=1
# Child Loop BB0_29 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB0_29: # Parent Loop BB0_28 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbp,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss (%r14,%r13,4), %xmm0
jne .LBB0_30
jnp .LBB0_31
.LBB0_30: # in Loop: Header=BB0_29 Depth=2
movl $.L.str.5, %edi
movl %r12d, %esi
movl %r13d, %edx
xorl %eax, %eax
callq printf
movb $1, %al
.LBB0_31: # in Loop: Header=BB0_29 Depth=2
testb $1, %al
jne .LBB0_33
# %bb.32: # in Loop: Header=BB0_29 Depth=2
incq %r13
cmpq %r15, %r13
jb .LBB0_29
.LBB0_33: # %._crit_edge190
# in Loop: Header=BB0_28 Depth=1
testb $1, %al
jne .LBB0_35
# %bb.34: # %._crit_edge190
# in Loop: Header=BB0_28 Depth=1
incq %r12
addq %rbx, %rbp
addq %rbx, %r14
cmpq %r15, %r12
jne .LBB0_28
.LBB0_35: # %._crit_edge196.loopexit
testb $1, %al
movq 40(%rsp), %rbx # 8-byte Reload
movq 64(%rsp), %r13 # 8-byte Reload
movq 48(%rsp), %r14 # 8-byte Reload
jne .LBB0_37
.LBB0_36: # %.critedge
movl $.Lstr.5, %edi
callq puts@PLT
.LBB0_37:
movl $.Lstr.4, %edi
callq puts@PLT
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rdi # 8-byte Reload
movq %rbx, %rsi
movq 56(%rsp), %r12 # 8-byte Reload
movq %r12, %rdx
movq 72(%rsp), %rcx # 8-byte Reload
# kill: def $ecx killed $ecx killed $rcx
movq 16(%rsp), %rbp # 8-byte Reload
movl %ebp, %r8d
movl %ebp, %r9d
callq _Z11MM_ImprovedPfS_S_iii
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq (%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.8, %edi
movb $1, %al
callq printf
testl %ebp, %ebp
jle .LBB0_47
# %bb.38: # %.preheader.lr.ph
leaq (,%r15,4), %rbx
xorl %eax, %eax
movq %r12, %r14
movq %r13, %rbp
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_39: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_40 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB0_40: # Parent Loop BB0_39 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbp,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss (%r14,%r13,4), %xmm0
jne .LBB0_41
jnp .LBB0_42
.LBB0_41: # in Loop: Header=BB0_40 Depth=2
movl $.L.str.5, %edi
movl %r12d, %esi
movl %r13d, %edx
xorl %eax, %eax
callq printf
movb $1, %al
.LBB0_42: # in Loop: Header=BB0_40 Depth=2
testb $1, %al
jne .LBB0_44
# %bb.43: # in Loop: Header=BB0_40 Depth=2
incq %r13
cmpq %r15, %r13
jb .LBB0_40
.LBB0_44: # %._crit_edge203
# in Loop: Header=BB0_39 Depth=1
testb $1, %al
jne .LBB0_46
# %bb.45: # %._crit_edge203
# in Loop: Header=BB0_39 Depth=1
incq %r12
addq %rbx, %rbp
addq %rbx, %r14
cmpq %r15, %r12
jne .LBB0_39
.LBB0_46: # %._crit_edge209.loopexit
testb $1, %al
movq 40(%rsp), %rbx # 8-byte Reload
movq 64(%rsp), %r13 # 8-byte Reload
movq 48(%rsp), %r14 # 8-byte Reload
movq 56(%rsp), %r12 # 8-byte Reload
jne .LBB0_48
.LBB0_47: # %.critedge269
movl $.Lstr.5, %edi
callq puts@PLT
.LBB0_48:
movq 32(%rsp), %rdi # 8-byte Reload
callq free
movq %rbx, %rdi
callq free
movq %r13, %rdi
callq free
movq %r14, %rdi
callq free
movq %r12, %rdi
callq free
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z8MM_BasicPfS_S_iii # -- Begin function _Z8MM_BasicPfS_S_iii
.p2align 4, 0x90
.type _Z8MM_BasicPfS_S_iii,@function
_Z8MM_BasicPfS_S_iii: # @_Z8MM_BasicPfS_S_iii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %ebp
movl %r8d, %r15d
movl %ecx, %r14d
movq %rdx, 80(%rsp) # 8-byte Spill
movq %rsi, 72(%rsp) # 8-byte Spill
movq %rdi, %rbx
leaq 56(%rsp), %rdi
callq hipEventCreate
leaq 32(%rsp), %rdi
callq hipEventCreate
movq %r14, 64(%rsp) # 8-byte Spill
leal (,%r14,4), %r13d
movl %r13d, %eax
imull %ebp, %eax
movl %r15d, %r12d
imull %ebp, %r12d
shll $2, %r12d
imull %r15d, %r13d
movslq %eax, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movslq %r12d, %r12
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movslq %r13d, %r13
leaq 8(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq 72(%rsp), %rsi # 8-byte Reload
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 56(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $274877907008, %rdi # imm = 0x4000000040
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
movq 64(%rsp), %rax # 8-byte Reload
movl %eax, 52(%rsp)
movl %r15d, 48(%rsp)
movl %ebp, 44(%rsp)
leaq 152(%rsp), %rax
movq %rax, 160(%rsp)
leaq 144(%rsp), %rax
movq %rax, 168(%rsp)
leaq 136(%rsp), %rax
movq %rax, 176(%rsp)
leaq 52(%rsp), %rax
movq %rax, 184(%rsp)
leaq 48(%rsp), %rax
movq %rax, 192(%rsp)
leaq 44(%rsp), %rax
movq %rax, 200(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z15MM_Basic_kernelPfS_S_iii, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rdi
callq hipEventSynchronize
movq 56(%rsp), %rsi
movq 32(%rsp), %rdx
leaq 160(%rsp), %rdi
callq hipEventElapsedTime
movss 160(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.9, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rsi
movq 80(%rsp), %rdi # 8-byte Reload
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z8MM_BasicPfS_S_iii, .Lfunc_end1-_Z8MM_BasicPfS_S_iii
.cfi_endproc
# -- End function
.globl _Z11MM_ImprovedPfS_S_iii # -- Begin function _Z11MM_ImprovedPfS_S_iii
.p2align 4, 0x90
.type _Z11MM_ImprovedPfS_S_iii,@function
_Z11MM_ImprovedPfS_S_iii: # @_Z11MM_ImprovedPfS_S_iii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %ebp
movl %r8d, %r15d
movl %ecx, %r14d
movq %rdx, 80(%rsp) # 8-byte Spill
movq %rsi, 72(%rsp) # 8-byte Spill
movq %rdi, %rbx
leaq 56(%rsp), %rdi
callq hipEventCreate
leaq 32(%rsp), %rdi
callq hipEventCreate
movq %r14, 64(%rsp) # 8-byte Spill
leal (,%r14,4), %r13d
movl %r13d, %eax
imull %ebp, %eax
movl %r15d, %r12d
imull %ebp, %r12d
shll $2, %r12d
imull %r15d, %r13d
movslq %eax, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movslq %r12d, %r12
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movslq %r13d, %r13
leaq 8(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq 72(%rsp), %rsi # 8-byte Reload
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 56(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $137438953504, %rdi # imm = 0x2000000020
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
movq 64(%rsp), %rax # 8-byte Reload
movl %eax, 52(%rsp)
movl %r15d, 48(%rsp)
movl %ebp, 44(%rsp)
leaq 152(%rsp), %rax
movq %rax, 160(%rsp)
leaq 144(%rsp), %rax
movq %rax, 168(%rsp)
leaq 136(%rsp), %rax
movq %rax, 176(%rsp)
leaq 52(%rsp), %rax
movq %rax, 184(%rsp)
leaq 48(%rsp), %rax
movq %rax, 192(%rsp)
leaq 44(%rsp), %rax
movq %rax, 200(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z15MM_Basic_kernelPfS_S_iii, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rdi
callq hipEventSynchronize
movq 56(%rsp), %rsi
movq 32(%rsp), %rdx
leaq 160(%rsp), %rdi
callq hipEventElapsedTime
movss 160(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.9, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rsi
movq 80(%rsp), %rdi # 8-byte Reload
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z11MM_ImprovedPfS_S_iii, .Lfunc_end2-_Z11MM_ImprovedPfS_S_iii
.cfi_endproc
# -- End function
.globl _Z30__device_stub__MM_Basic_kernelPfS_S_iii # -- Begin function _Z30__device_stub__MM_Basic_kernelPfS_S_iii
.p2align 4, 0x90
.type _Z30__device_stub__MM_Basic_kernelPfS_S_iii,@function
_Z30__device_stub__MM_Basic_kernelPfS_S_iii: # @_Z30__device_stub__MM_Basic_kernelPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15MM_Basic_kernelPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end3:
.size _Z30__device_stub__MM_Basic_kernelPfS_S_iii, .Lfunc_end3-_Z30__device_stub__MM_Basic_kernelPfS_S_iii
.cfi_endproc
# -- End function
.globl _Z33__device_stub__MM_Improved_kernelPfS_S_iii # -- Begin function _Z33__device_stub__MM_Improved_kernelPfS_S_iii
.p2align 4, 0x90
.type _Z33__device_stub__MM_Improved_kernelPfS_S_iii,@function
_Z33__device_stub__MM_Improved_kernelPfS_S_iii: # @_Z33__device_stub__MM_Improved_kernelPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18MM_Improved_kernelPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end4:
.size _Z33__device_stub__MM_Improved_kernelPfS_S_iii, .Lfunc_end4-_Z33__device_stub__MM_Improved_kernelPfS_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15MM_Basic_kernelPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18MM_Improved_kernelPfS_S_iii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "\tSequential Job Time: %.2f ms\n"
.size .L.str.2, 31
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\tBasic Parallel Job Time: %.2f ms\n"
.size .L.str.4, 35
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\tError: Starting at [%d][%d]\n"
.size .L.str.5, 30
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "\tImproved Parallel Job Time: %.2f ms\n"
.size .L.str.8, 38
.type _Z15MM_Basic_kernelPfS_S_iii,@object # @_Z15MM_Basic_kernelPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z15MM_Basic_kernelPfS_S_iii
.p2align 3, 0x0
_Z15MM_Basic_kernelPfS_S_iii:
.quad _Z30__device_stub__MM_Basic_kernelPfS_S_iii
.size _Z15MM_Basic_kernelPfS_S_iii, 8
.type .L.str.9,@object # @.str.9
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.9:
.asciz "\tKernel Job Time: %.2f ms\n"
.size .L.str.9, 27
.type _Z18MM_Improved_kernelPfS_S_iii,@object # @_Z18MM_Improved_kernelPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z18MM_Improved_kernelPfS_S_iii
.p2align 3, 0x0
_Z18MM_Improved_kernelPfS_S_iii:
.quad _Z33__device_stub__MM_Improved_kernelPfS_S_iii
.size _Z18MM_Improved_kernelPfS_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15MM_Basic_kernelPfS_S_iii"
.size .L__unnamed_1, 29
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z18MM_Improved_kernelPfS_S_iii"
.size .L__unnamed_2, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Initializing Matricies, could take some time..."
.size .Lstr, 48
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Running sequential job."
.size .Lstr.1, 24
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Running Basic parallel job."
.size .Lstr.2, 28
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Running Improved parallel job."
.size .Lstr.4, 31
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "\tNo errors found."
.size .Lstr.5, 18
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__MM_Basic_kernelPfS_S_iii
.addrsig_sym _Z33__device_stub__MM_Improved_kernelPfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15MM_Basic_kernelPfS_S_iii
.addrsig_sym _Z18MM_Improved_kernelPfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /* To run:
nvcc -Xptxas=dlcm=ca l2_peak_bandwidth.cu -o peak
nvprof ./peak
====
nvprof --print-gpu-summary ./peak
nvprof -m l2_read_throughput ./peak
nvprof -m l2_write_throughput ./peak
*/
# include <stdio.h>
# include <stdint.h>
# include "cuda_runtime.h"
__global__
void global_latency (unsigned int* a, unsigned int* b, unsigned int* c, int N, int iterations) {
for (int k = 0; k < iterations; k++) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int j = index; j < N; j += stride) {
c[j] = a[j] + b[j];
}
}
}
void parametric_measure_global(int N, int iterations) {
cudaDeviceReset();
// host (CPU) arrays
unsigned int *ha0;
unsigned int *ha1;
unsigned int *ha2;
ha0 = (unsigned int*) malloc(sizeof(unsigned int) * N);
ha1 = (unsigned int*) malloc(sizeof(unsigned int) * N);
ha2 = (unsigned int*) malloc(sizeof(unsigned int) * N);
// device (GPU) arrays
unsigned int *da0;
unsigned int *da1;
unsigned int *da2;
cudaMalloc((void**) &da0, sizeof(unsigned int) * N);
cudaMalloc((void**) &da1, sizeof(unsigned int) * N);
cudaMalloc((void**) &da2, sizeof(unsigned int) * N);
// initialize host (CPU) array
for (int i = 0; i < N; i++) {
ha0[i] = 1;
ha1[i] = 1;
ha2[i] = 0;
}
// copy array from host to device
cudaMemcpy(da0, ha0, sizeof(unsigned int) * N, cudaMemcpyHostToDevice);
cudaMemcpy(da1, ha1, sizeof(unsigned int) * N, cudaMemcpyHostToDevice);
cudaMemcpy(da2, ha2, sizeof(unsigned int) * N, cudaMemcpyHostToDevice);
cudaThreadSynchronize();
// launch kernel with a large number of threads to saturate bandwidth
int blockSize = 512;
int numBlocks = (N + blockSize - 1) / blockSize;
//dim3 Db = dim3(32,32,1);
//dim3 Dg = dim3(512,1,1);
global_latency <<<numBlocks, blockSize>>>(da0, da1, da2, N, iterations);
cudaThreadSynchronize();
cudaError_t error_id = cudaGetLastError();
if (error_id != cudaSuccess) {
printf("Error kernel is %s\n", cudaGetErrorString(error_id));
}
cudaThreadSynchronize();
// free memory on GPu
cudaFree(da0);
cudaFree(da1);
cudaFree(da2);
// free memory on CPU
free(ha0);
free(ha1);
free(ha2);
cudaDeviceReset();
}
void measure_global() {
// access 3 1 MB arrays 1000s of times
int iterations = 100;
int N = 1024* 1024/sizeof(unsigned int); // 1 MB
printf("\n=====3 %ld MB arrays * %d times====\n", sizeof(unsigned int)*N/1024/1024, iterations);
parametric_measure_global(N, iterations);
}
int main(){
cudaSetDevice(0);
measure_global();
cudaDeviceReset();
return 0;
} | code for sm_80
Function : _Z14global_latencyPjS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0060*/ HFMA2.MMA R12, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0c7435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0080*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fe200078e02ff */
/*0090*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e260000002100 */
/*00a0*/ I2F.U32.RP R2, R0 ; /* 0x0000000000027306 */
/* 0x000e620000209000 */
/*00b0*/ IMAD.MOV R11, RZ, RZ, -R0 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0a00 */
/*00c0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fcc0003f45070 */
/*00d0*/ MUFU.RCP R2, R2 ; /* 0x0000000200027308 */
/* 0x002e620000001000 */
/*00e0*/ IMAD R3, R3, c[0x0][0x0], R4 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0204 */
/*00f0*/ IADD3 R5, R3, R0, RZ ; /* 0x0000000003057210 */
/* 0x000fc80007ffe0ff */
/*0100*/ LOP3.LUT R9, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff097212 */
/* 0x000fe400078e33ff */
/*0110*/ IADD3 R6, R2, 0xffffffe, RZ ; /* 0x0ffffffe02067810 */
/* 0x002fe40007ffe0ff */
/*0120*/ IADD3 R9, R9, c[0x0][0x178], R0 ; /* 0x00005e0009097a10 */
/* 0x000fe40007ffe000 */
/*0130*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*0140*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe400078e00ff */
/*0150*/ IMAD R11, R11, R7, RZ ; /* 0x000000070b0b7224 */
/* 0x002fc800078e02ff */
/*0160*/ IMAD.HI.U32 R2, R7, R11, R6 ; /* 0x0000000b07027227 */
/* 0x000fc800078e0006 */
/*0170*/ IMAD.WIDE R10, R3, R12, c[0x0][0x168] ; /* 0x00005a00030a7625 */
/* 0x000fc800078e020c */
/*0180*/ IMAD.HI.U32 R2, R2, R9, RZ ; /* 0x0000000902027227 */
/* 0x000fc800078e00ff */
/*0190*/ IMAD.WIDE R16, R0, 0x4, R10 ; /* 0x0000000400107825 */
/* 0x000fe200078e020a */
/*01a0*/ IADD3 R4, -R2, RZ, RZ ; /* 0x000000ff02047210 */
/* 0x000fc60007ffe1ff */
/*01b0*/ IMAD.IADD R7, R0.reuse, 0x1, R5 ; /* 0x0000000100077824 */
/* 0x040fe400078e0205 */
/*01c0*/ IMAD R9, R0.reuse, R4, R9 ; /* 0x0000000400097224 */
/* 0x040fe200078e0209 */
/*01d0*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe20000000f00 */
/*01e0*/ IMAD.WIDE R22, R0.reuse, 0x4, R16 ; /* 0x0000000400167825 */
/* 0x040fe200078e0210 */
/*01f0*/ IADD3 R6, R0, R7, RZ ; /* 0x0000000700067210 */
/* 0x000fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P0, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fda0003f06070 */
/*0210*/ @P0 IMAD.IADD R9, R9, 0x1, -R0 ; /* 0x0000000109090824 */
/* 0x000fe200078e0a00 */
/*0220*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fc80007ffe0ff */
/*0230*/ ISETP.GE.U32.AND P1, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fe20003f26070 */
/*0240*/ IMAD.WIDE R8, R3, R12, c[0x0][0x160] ; /* 0x0000580003087625 */
/* 0x000fc800078e020c */
/*0250*/ IMAD.WIDE R12, R3, R12, c[0x0][0x170] ; /* 0x00005c00030c7625 */
/* 0x000fc800078e020c */
/*0260*/ IMAD.WIDE R14, R0, 0x4, R8 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0208 */
/*0270*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe20007ffe0ff */
/*0280*/ IMAD.WIDE R18, R0, 0x4, R12 ; /* 0x0000000400127825 */
/* 0x000fe200078e020c */
/*0290*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc600078e33ff */
/*02a0*/ IMAD.WIDE R20, R0, 0x4, R14 ; /* 0x0000000400147825 */
/* 0x000fe200078e020e */
/*02b0*/ IADD3 R34, R2, 0x1, RZ ; /* 0x0000000102227810 */
/* 0x000fc60007ffe0ff */
/*02c0*/ IMAD.WIDE R24, R0, 0x4, R18 ; /* 0x0000000400187825 */
/* 0x000fe200078e0212 */
/*02d0*/ LOP3.LUT R34, R34, 0x3, RZ, 0xc0, !PT ; /* 0x0000000322227812 */
/* 0x000fc600078ec0ff */
/*02e0*/ ISETP.GE.AND P1, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe20003f26270 */
/*02f0*/ BSSY B0, 0x6f0 ; /* 0x000003f000007945 */
/* 0x000fe20003800000 */
/*0300*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fc80007ffe0ff */
/*0310*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x17c], PT ; /* 0x00005f0004007a0c */
/* 0x000fce0003f06270 */
/*0320*/ @P1 BRA 0x6e0 ; /* 0x000003b000001947 */
/* 0x001fea0003800000 */
/*0330*/ ISETP.NE.AND P1, PT, R34, RZ, PT ; /* 0x000000ff2200720c */
/* 0x000fe20003f25270 */
/*0340*/ BSSY B1, 0x4b0 ; /* 0x0000016000017945 */
/* 0x000fe20003800000 */
/*0350*/ IMAD.MOV.U32 R35, RZ, RZ, R3 ; /* 0x000000ffff237224 */
/* 0x000fd600078e0003 */
/*0360*/ @!P1 BRA 0x4a0 ; /* 0x0000013000009947 */
/* 0x000fea0003800000 */
/*0370*/ LDG.E R26, [R10.64] ; /* 0x000000040a1a7981 */
/* 0x000ea8000c1e1900 */
/*0380*/ LDG.E R27, [R8.64] ; /* 0x00000004081b7981 */
/* 0x000ea2000c1e1900 */
/*0390*/ ISETP.NE.AND P1, PT, R34, 0x1, PT ; /* 0x000000012200780c */
/* 0x000fe40003f25270 */
/*03a0*/ MOV R35, R5 ; /* 0x0000000500237202 */
/* 0x000fe40000000f00 */
/*03b0*/ IADD3 R27, R26, R27, RZ ; /* 0x0000001b1a1b7210 */
/* 0x004fca0007ffe0ff */
/*03c0*/ STG.E [R12.64], R27 ; /* 0x0000001b0c007986 */
/* 0x0001e8000c101904 */
/*03d0*/ @!P1 BRA 0x4a0 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*03e0*/ LDG.E R26, [R16.64] ; /* 0x00000004101a7981 */
/* 0x000ea8000c1e1900 */
/*03f0*/ LDG.E R27, [R14.64] ; /* 0x000000040e1b7981 */
/* 0x001ea2000c1e1900 */
/*0400*/ ISETP.NE.AND P1, PT, R34, 0x2, PT ; /* 0x000000022200780c */
/* 0x000fe40003f25270 */
/*0410*/ MOV R35, R7 ; /* 0x0000000700237202 */
/* 0x000fe20000000f00 */
/*0420*/ IMAD.IADD R27, R26, 0x1, R27 ; /* 0x000000011a1b7824 */
/* 0x004fca00078e021b */
/*0430*/ STG.E [R18.64], R27 ; /* 0x0000001b12007986 */
/* 0x0001ea000c101904 */
/*0440*/ @!P1 BRA 0x4a0 ; /* 0x0000005000009947 */
/* 0x000fea0003800000 */
/*0450*/ LDG.E R26, [R20.64] ; /* 0x00000004141a7981 */
/* 0x000ea8000c1e1900 */
/*0460*/ LDG.E R27, [R22.64] ; /* 0x00000004161b7981 */
/* 0x001ea2000c1e1900 */
/*0470*/ IMAD.MOV.U32 R35, RZ, RZ, R6 ; /* 0x000000ffff237224 */
/* 0x000fe200078e0006 */
/*0480*/ IADD3 R27, R26, R27, RZ ; /* 0x0000001b1a1b7210 */
/* 0x004fca0007ffe0ff */
/*0490*/ STG.E [R24.64], R27 ; /* 0x0000001b18007986 */
/* 0x0001e4000c101904 */
/*04a0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*04b0*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f26070 */
/*04c0*/ @!P1 BRA 0x6e0 ; /* 0x0000021000009947 */
/* 0x000fea0003800000 */
/*04d0*/ HFMA2.MMA R32, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff207435 */
/* 0x000fd400000001ff */
/*04e0*/ IMAD.WIDE R28, R35, R32, c[0x0][0x168] ; /* 0x00005a00231c7625 */
/* 0x000fc800078e0220 */
/*04f0*/ IMAD.WIDE R30, R35, R32, c[0x0][0x160] ; /* 0x00005800231e7625 */
/* 0x001fe200078e0220 */
/*0500*/ LDG.E R37, [R28.64] ; /* 0x000000041c257981 */
/* 0x0002a8000c1e1900 */
/*0510*/ LDG.E R26, [R30.64] ; /* 0x000000041e1a7981 */
/* 0x000ea2000c1e1900 */
/*0520*/ IMAD.WIDE R28, R0, 0x4, R28 ; /* 0x00000004001c7825 */
/* 0x002fe200078e021c */
/*0530*/ IADD3 R37, R37, R26, RZ ; /* 0x0000001a25257210 */
/* 0x004fc60007ffe0ff */
/*0540*/ IMAD.WIDE R26, R35, R32, c[0x0][0x170] ; /* 0x00005c00231a7625 */
/* 0x001fc800078e0220 */
/*0550*/ IMAD.WIDE R32, R0.reuse, 0x4, R30 ; /* 0x0000000400207825 */
/* 0x040fe200078e021e */
/*0560*/ STG.E [R26.64], R37 ; /* 0x000000251a007986 */
/* 0x0001e8000c101904 */
/*0570*/ LDG.E R36, [R28.64] ; /* 0x000000041c247981 */
/* 0x0002a8000c1e1900 */
/*0580*/ LDG.E R31, [R32.64] ; /* 0x00000004201f7981 */
/* 0x000ea2000c1e1900 */
/*0590*/ IMAD.WIDE R26, R0, 0x4, R26 ; /* 0x00000004001a7825 */
/* 0x001fc800078e021a */
/*05a0*/ IMAD.WIDE R28, R0, 0x4, R28 ; /* 0x00000004001c7825 */
/* 0x002fc800078e021c */
/*05b0*/ IMAD.IADD R36, R36, 0x1, R31 ; /* 0x0000000124247824 */
/* 0x004fe400078e021f */
/*05c0*/ IMAD.WIDE R30, R0, 0x4, R32 ; /* 0x00000004001e7825 */
/* 0x000fc600078e0220 */
/*05d0*/ STG.E [R26.64], R36 ; /* 0x000000241a007986 */
/* 0x0001e8000c101904 */
/*05e0*/ LDG.E R32, [R28.64] ; /* 0x000000041c207981 */
/* 0x0002a8000c1e1900 */
/*05f0*/ LDG.E R33, [R30.64] ; /* 0x000000041e217981 */
/* 0x000ea2000c1e1900 */
/*0600*/ IMAD.WIDE R26, R0, 0x4, R26 ; /* 0x00000004001a7825 */
/* 0x001fc800078e021a */
/*0610*/ IMAD.WIDE R28, R0, 0x4, R28 ; /* 0x00000004001c7825 */
/* 0x002fe200078e021c */
/*0620*/ IADD3 R37, R32, R33, RZ ; /* 0x0000002120257210 */
/* 0x004fc60007ffe0ff */
/*0630*/ IMAD.WIDE R32, R0.reuse, 0x4, R30 ; /* 0x0000000400207825 */
/* 0x040fe400078e021e */
/*0640*/ STG.E [R26.64], R37 ; /* 0x000000251a007986 */
/* 0x0001e8000c101904 */
/*0650*/ LDG.E R28, [R28.64] ; /* 0x000000041c1c7981 */
/* 0x000ea8000c1e1900 */
/*0660*/ LDG.E R33, [R32.64] ; /* 0x0000000420217981 */
/* 0x000ea2000c1e1900 */
/*0670*/ IMAD.WIDE R30, R0.reuse, 0x4, R26 ; /* 0x00000004001e7825 */
/* 0x040fe200078e021a */
/*0680*/ IADD3 R35, R0, R35, R0 ; /* 0x0000002300237210 */
/* 0x000fc80007ffe000 */
/*0690*/ IADD3 R35, R0, R35, R0 ; /* 0x0000002300237210 */
/* 0x000fc80007ffe000 */
/*06a0*/ ISETP.GE.AND P1, PT, R35, c[0x0][0x178], PT ; /* 0x00005e0023007a0c */
/* 0x000fe40003f26270 */
/*06b0*/ IADD3 R36, R28, R33, RZ ; /* 0x000000211c247210 */
/* 0x004fca0007ffe0ff */
/*06c0*/ STG.E [R30.64], R36 ; /* 0x000000241e007986 */
/* 0x0001ec000c101904 */
/*06d0*/ @!P1 BRA 0x4d0 ; /* 0xfffffdf000009947 */
/* 0x000fea000383ffff */
/*06e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06f0*/ @!P0 BRA 0x2e0 ; /* 0xfffffbe000008947 */
/* 0x000fea000383ffff */
/*0700*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0710*/ BRA 0x710; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* To run:
nvcc -Xptxas=dlcm=ca l2_peak_bandwidth.cu -o peak
nvprof ./peak
====
nvprof --print-gpu-summary ./peak
nvprof -m l2_read_throughput ./peak
nvprof -m l2_write_throughput ./peak
*/
# include <stdio.h>
# include <stdint.h>
# include "cuda_runtime.h"
__global__
void global_latency (unsigned int* a, unsigned int* b, unsigned int* c, int N, int iterations) {
for (int k = 0; k < iterations; k++) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int j = index; j < N; j += stride) {
c[j] = a[j] + b[j];
}
}
}
void parametric_measure_global(int N, int iterations) {
cudaDeviceReset();
// host (CPU) arrays
unsigned int *ha0;
unsigned int *ha1;
unsigned int *ha2;
ha0 = (unsigned int*) malloc(sizeof(unsigned int) * N);
ha1 = (unsigned int*) malloc(sizeof(unsigned int) * N);
ha2 = (unsigned int*) malloc(sizeof(unsigned int) * N);
// device (GPU) arrays
unsigned int *da0;
unsigned int *da1;
unsigned int *da2;
cudaMalloc((void**) &da0, sizeof(unsigned int) * N);
cudaMalloc((void**) &da1, sizeof(unsigned int) * N);
cudaMalloc((void**) &da2, sizeof(unsigned int) * N);
// initialize host (CPU) array
for (int i = 0; i < N; i++) {
ha0[i] = 1;
ha1[i] = 1;
ha2[i] = 0;
}
// copy array from host to device
cudaMemcpy(da0, ha0, sizeof(unsigned int) * N, cudaMemcpyHostToDevice);
cudaMemcpy(da1, ha1, sizeof(unsigned int) * N, cudaMemcpyHostToDevice);
cudaMemcpy(da2, ha2, sizeof(unsigned int) * N, cudaMemcpyHostToDevice);
cudaThreadSynchronize();
// launch kernel with a large number of threads to saturate bandwidth
int blockSize = 512;
int numBlocks = (N + blockSize - 1) / blockSize;
//dim3 Db = dim3(32,32,1);
//dim3 Dg = dim3(512,1,1);
global_latency <<<numBlocks, blockSize>>>(da0, da1, da2, N, iterations);
cudaThreadSynchronize();
cudaError_t error_id = cudaGetLastError();
if (error_id != cudaSuccess) {
printf("Error kernel is %s\n", cudaGetErrorString(error_id));
}
cudaThreadSynchronize();
// free memory on GPu
cudaFree(da0);
cudaFree(da1);
cudaFree(da2);
// free memory on CPU
free(ha0);
free(ha1);
free(ha2);
cudaDeviceReset();
}
void measure_global() {
// access 3 1 MB arrays 1000s of times
int iterations = 100;
int N = 1024* 1024/sizeof(unsigned int); // 1 MB
printf("\n=====3 %ld MB arrays * %d times====\n", sizeof(unsigned int)*N/1024/1024, iterations);
parametric_measure_global(N, iterations);
}
int main(){
cudaSetDevice(0);
measure_global();
cudaDeviceReset();
return 0;
} | .file "tmpxft_000e0c10_00000000-6_l2_peak_bandwidth.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z14global_latencyPjS_S_iiPjS_S_ii
.type _Z40__device_stub__Z14global_latencyPjS_S_iiPjS_S_ii, @function
_Z40__device_stub__Z14global_latencyPjS_S_iiPjS_S_ii:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14global_latencyPjS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z40__device_stub__Z14global_latencyPjS_S_iiPjS_S_ii, .-_Z40__device_stub__Z14global_latencyPjS_S_iiPjS_S_ii
.globl _Z14global_latencyPjS_S_ii
.type _Z14global_latencyPjS_S_ii, @function
_Z14global_latencyPjS_S_ii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z14global_latencyPjS_S_iiPjS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z14global_latencyPjS_S_ii, .-_Z14global_latencyPjS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Error kernel is %s\n"
.text
.globl _Z25parametric_measure_globalii
.type _Z25parametric_measure_globalii, @function
_Z25parametric_measure_globalii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movl %edi, %r14d
movl %esi, %r15d
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
call cudaDeviceReset@PLT
movslq %r14d, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %r14d, %r14d
jle .L12
movl $0, %eax
.L13:
movl $1, 0(%r13,%rax)
movl $1, (%r12,%rax)
movl $0, 0(%rbp,%rax)
addq $4, %rax
cmpq %rax, %rbx
jne .L13
.L12:
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
call cudaThreadSynchronize@PLT
movl $512, 44(%rsp)
movl $1, 48(%rsp)
leal 1022(%r14), %eax
movl %r14d, %edx
addl $511, %edx
cmovns %edx, %eax
sarl $9, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L14:
call cudaThreadSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L20
.L15:
call cudaThreadSynchronize@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
call cudaDeviceReset@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl %r15d, %r8d
movl %r14d, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z40__device_stub__Z14global_latencyPjS_S_iiPjS_S_ii
jmp .L14
.L20:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L15
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z25parametric_measure_globalii, .-_Z25parametric_measure_globalii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "\n=====3 %ld MB arrays * %d times====\n"
.text
.globl _Z14measure_globalv
.type _Z14measure_globalv, @function
_Z14measure_globalv:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $100, %ecx
movl $1, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $100, %esi
movl $262144, %edi
call _Z25parametric_measure_globalii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z14measure_globalv, .-_Z14measure_globalv
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $0, %edi
call cudaSetDevice@PLT
call _Z14measure_globalv
call cudaDeviceReset@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z14global_latencyPjS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z14global_latencyPjS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* To run:
nvcc -Xptxas=dlcm=ca l2_peak_bandwidth.cu -o peak
nvprof ./peak
====
nvprof --print-gpu-summary ./peak
nvprof -m l2_read_throughput ./peak
nvprof -m l2_write_throughput ./peak
*/
# include <stdio.h>
# include <stdint.h>
# include "cuda_runtime.h"
__global__
void global_latency (unsigned int* a, unsigned int* b, unsigned int* c, int N, int iterations) {
for (int k = 0; k < iterations; k++) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int j = index; j < N; j += stride) {
c[j] = a[j] + b[j];
}
}
}
void parametric_measure_global(int N, int iterations) {
cudaDeviceReset();
// host (CPU) arrays
unsigned int *ha0;
unsigned int *ha1;
unsigned int *ha2;
ha0 = (unsigned int*) malloc(sizeof(unsigned int) * N);
ha1 = (unsigned int*) malloc(sizeof(unsigned int) * N);
ha2 = (unsigned int*) malloc(sizeof(unsigned int) * N);
// device (GPU) arrays
unsigned int *da0;
unsigned int *da1;
unsigned int *da2;
cudaMalloc((void**) &da0, sizeof(unsigned int) * N);
cudaMalloc((void**) &da1, sizeof(unsigned int) * N);
cudaMalloc((void**) &da2, sizeof(unsigned int) * N);
// initialize host (CPU) array
for (int i = 0; i < N; i++) {
ha0[i] = 1;
ha1[i] = 1;
ha2[i] = 0;
}
// copy array from host to device
cudaMemcpy(da0, ha0, sizeof(unsigned int) * N, cudaMemcpyHostToDevice);
cudaMemcpy(da1, ha1, sizeof(unsigned int) * N, cudaMemcpyHostToDevice);
cudaMemcpy(da2, ha2, sizeof(unsigned int) * N, cudaMemcpyHostToDevice);
cudaThreadSynchronize();
// launch kernel with a large number of threads to saturate bandwidth
int blockSize = 512;
int numBlocks = (N + blockSize - 1) / blockSize;
//dim3 Db = dim3(32,32,1);
//dim3 Dg = dim3(512,1,1);
global_latency <<<numBlocks, blockSize>>>(da0, da1, da2, N, iterations);
cudaThreadSynchronize();
cudaError_t error_id = cudaGetLastError();
if (error_id != cudaSuccess) {
printf("Error kernel is %s\n", cudaGetErrorString(error_id));
}
cudaThreadSynchronize();
// free memory on GPu
cudaFree(da0);
cudaFree(da1);
cudaFree(da2);
// free memory on CPU
free(ha0);
free(ha1);
free(ha2);
cudaDeviceReset();
}
void measure_global() {
// access 3 1 MB arrays 1000s of times
int iterations = 100;
int N = 1024* 1024/sizeof(unsigned int); // 1 MB
printf("\n=====3 %ld MB arrays * %d times====\n", sizeof(unsigned int)*N/1024/1024, iterations);
parametric_measure_global(N, iterations);
}
int main(){
cudaSetDevice(0);
measure_global();
cudaDeviceReset();
return 0;
} | /* To run:
nvcc -Xptxas=dlcm=ca l2_peak_bandwidth.cu -o peak
nvprof ./peak
====
nvprof --print-gpu-summary ./peak
nvprof -m l2_read_throughput ./peak
nvprof -m l2_write_throughput ./peak
*/
# include <stdio.h>
# include <stdint.h>
# include "hip/hip_runtime.h"
__global__
void global_latency (unsigned int* a, unsigned int* b, unsigned int* c, int N, int iterations) {
for (int k = 0; k < iterations; k++) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int j = index; j < N; j += stride) {
c[j] = a[j] + b[j];
}
}
}
void parametric_measure_global(int N, int iterations) {
hipDeviceReset();
// host (CPU) arrays
unsigned int *ha0;
unsigned int *ha1;
unsigned int *ha2;
ha0 = (unsigned int*) malloc(sizeof(unsigned int) * N);
ha1 = (unsigned int*) malloc(sizeof(unsigned int) * N);
ha2 = (unsigned int*) malloc(sizeof(unsigned int) * N);
// device (GPU) arrays
unsigned int *da0;
unsigned int *da1;
unsigned int *da2;
hipMalloc((void**) &da0, sizeof(unsigned int) * N);
hipMalloc((void**) &da1, sizeof(unsigned int) * N);
hipMalloc((void**) &da2, sizeof(unsigned int) * N);
// initialize host (CPU) array
for (int i = 0; i < N; i++) {
ha0[i] = 1;
ha1[i] = 1;
ha2[i] = 0;
}
// copy array from host to device
hipMemcpy(da0, ha0, sizeof(unsigned int) * N, hipMemcpyHostToDevice);
hipMemcpy(da1, ha1, sizeof(unsigned int) * N, hipMemcpyHostToDevice);
hipMemcpy(da2, ha2, sizeof(unsigned int) * N, hipMemcpyHostToDevice);
hipDeviceSynchronize();
// launch kernel with a large number of threads to saturate bandwidth
int blockSize = 512;
int numBlocks = (N + blockSize - 1) / blockSize;
//dim3 Db = dim3(32,32,1);
//dim3 Dg = dim3(512,1,1);
global_latency <<<numBlocks, blockSize>>>(da0, da1, da2, N, iterations);
hipDeviceSynchronize();
hipError_t error_id = hipGetLastError();
if (error_id != hipSuccess) {
printf("Error kernel is %s\n", hipGetErrorString(error_id));
}
hipDeviceSynchronize();
// free memory on GPu
hipFree(da0);
hipFree(da1);
hipFree(da2);
// free memory on CPU
free(ha0);
free(ha1);
free(ha2);
hipDeviceReset();
}
void measure_global() {
// access 3 1 MB arrays 1000s of times
int iterations = 100;
int N = 1024* 1024/sizeof(unsigned int); // 1 MB
printf("\n=====3 %ld MB arrays * %d times====\n", sizeof(unsigned int)*N/1024/1024, iterations);
parametric_measure_global(N, iterations);
}
int main(){
hipSetDevice(0);
measure_global();
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /* To run:
nvcc -Xptxas=dlcm=ca l2_peak_bandwidth.cu -o peak
nvprof ./peak
====
nvprof --print-gpu-summary ./peak
nvprof -m l2_read_throughput ./peak
nvprof -m l2_write_throughput ./peak
*/
# include <stdio.h>
# include <stdint.h>
# include "hip/hip_runtime.h"
__global__
void global_latency (unsigned int* a, unsigned int* b, unsigned int* c, int N, int iterations) {
for (int k = 0; k < iterations; k++) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int j = index; j < N; j += stride) {
c[j] = a[j] + b[j];
}
}
}
void parametric_measure_global(int N, int iterations) {
hipDeviceReset();
// host (CPU) arrays
unsigned int *ha0;
unsigned int *ha1;
unsigned int *ha2;
ha0 = (unsigned int*) malloc(sizeof(unsigned int) * N);
ha1 = (unsigned int*) malloc(sizeof(unsigned int) * N);
ha2 = (unsigned int*) malloc(sizeof(unsigned int) * N);
// device (GPU) arrays
unsigned int *da0;
unsigned int *da1;
unsigned int *da2;
hipMalloc((void**) &da0, sizeof(unsigned int) * N);
hipMalloc((void**) &da1, sizeof(unsigned int) * N);
hipMalloc((void**) &da2, sizeof(unsigned int) * N);
// initialize host (CPU) array
for (int i = 0; i < N; i++) {
ha0[i] = 1;
ha1[i] = 1;
ha2[i] = 0;
}
// copy array from host to device
hipMemcpy(da0, ha0, sizeof(unsigned int) * N, hipMemcpyHostToDevice);
hipMemcpy(da1, ha1, sizeof(unsigned int) * N, hipMemcpyHostToDevice);
hipMemcpy(da2, ha2, sizeof(unsigned int) * N, hipMemcpyHostToDevice);
hipDeviceSynchronize();
// launch kernel with a large number of threads to saturate bandwidth
int blockSize = 512;
int numBlocks = (N + blockSize - 1) / blockSize;
//dim3 Db = dim3(32,32,1);
//dim3 Dg = dim3(512,1,1);
global_latency <<<numBlocks, blockSize>>>(da0, da1, da2, N, iterations);
hipDeviceSynchronize();
hipError_t error_id = hipGetLastError();
if (error_id != hipSuccess) {
printf("Error kernel is %s\n", hipGetErrorString(error_id));
}
hipDeviceSynchronize();
// free memory on GPu
hipFree(da0);
hipFree(da1);
hipFree(da2);
// free memory on CPU
free(ha0);
free(ha1);
free(ha2);
hipDeviceReset();
}
void measure_global() {
// access 3 1 MB arrays 1000s of times
int iterations = 100;
int N = 1024* 1024/sizeof(unsigned int); // 1 MB
printf("\n=====3 %ld MB arrays * %d times====\n", sizeof(unsigned int)*N/1024/1024, iterations);
parametric_measure_global(N, iterations);
}
int main(){
hipSetDevice(0);
measure_global();
hipDeviceReset();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14global_latencyPjS_S_ii
.globl _Z14global_latencyPjS_S_ii
.p2align 8
.type _Z14global_latencyPjS_S_ii,@function
_Z14global_latencyPjS_S_ii:
s_load_b32 s12, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s12, 1
s_cbranch_scc1 .LBB0_6
s_clause 0x4
s_load_b32 s8, s[0:1], 0x2c
s_load_b32 s9, s[0:1], 0x20
s_load_b32 s13, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s8, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
s_mul_i32 s8, s9, s0
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_lshl_b64 s[10:11], s[8:9], 2
s_mov_b32 s9, 0
v_ashrrev_i32_e32 v2, 31, v1
v_cmp_gt_i32_e32 vcc_lo, s13, v1
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s14
s_add_i32 s9, s9, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s9, s12
s_cbranch_scc1 .LBB0_6
.LBB0_3:
s_and_saveexec_b32 s14, vcc_lo
s_cbranch_execz .LBB0_2
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
v_mov_b32_e32 v0, v1
s_mov_b32 s15, 0
.p2align 6
.LBB0_5:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v6, s0, s4, v4
v_add_co_ci_u32_e64 v7, s0, s5, v5, s0
v_add_co_u32 v8, s0, s6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v9, s0, s7, v5, s0
v_add_nc_u32_e32 v0, s8, v0
global_load_b32 v10, v[6:7], off
global_load_b32 v8, v[8:9], off
v_add_co_u32 v6, s0, s2, v4
v_add_co_ci_u32_e64 v7, s0, s3, v5, s0
v_add_co_u32 v4, s0, v4, s10
v_cmp_le_i32_e64 s1, s13, v0
v_add_co_ci_u32_e64 v5, s0, s11, v5, s0
s_delay_alu instid0(VALU_DEP_2)
s_or_b32 s15, s1, s15
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v8, v8, v10
global_store_b32 v[6:7], v8, off
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_5
s_branch .LBB0_2
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14global_latencyPjS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14global_latencyPjS_S_ii, .Lfunc_end0-_Z14global_latencyPjS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14global_latencyPjS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14global_latencyPjS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* To run:
nvcc -Xptxas=dlcm=ca l2_peak_bandwidth.cu -o peak
nvprof ./peak
====
nvprof --print-gpu-summary ./peak
nvprof -m l2_read_throughput ./peak
nvprof -m l2_write_throughput ./peak
*/
# include <stdio.h>
# include <stdint.h>
# include "hip/hip_runtime.h"
__global__
void global_latency (unsigned int* a, unsigned int* b, unsigned int* c, int N, int iterations) {
for (int k = 0; k < iterations; k++) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int j = index; j < N; j += stride) {
c[j] = a[j] + b[j];
}
}
}
void parametric_measure_global(int N, int iterations) {
hipDeviceReset();
// host (CPU) arrays
unsigned int *ha0;
unsigned int *ha1;
unsigned int *ha2;
ha0 = (unsigned int*) malloc(sizeof(unsigned int) * N);
ha1 = (unsigned int*) malloc(sizeof(unsigned int) * N);
ha2 = (unsigned int*) malloc(sizeof(unsigned int) * N);
// device (GPU) arrays
unsigned int *da0;
unsigned int *da1;
unsigned int *da2;
hipMalloc((void**) &da0, sizeof(unsigned int) * N);
hipMalloc((void**) &da1, sizeof(unsigned int) * N);
hipMalloc((void**) &da2, sizeof(unsigned int) * N);
// initialize host (CPU) array
for (int i = 0; i < N; i++) {
ha0[i] = 1;
ha1[i] = 1;
ha2[i] = 0;
}
// copy array from host to device
hipMemcpy(da0, ha0, sizeof(unsigned int) * N, hipMemcpyHostToDevice);
hipMemcpy(da1, ha1, sizeof(unsigned int) * N, hipMemcpyHostToDevice);
hipMemcpy(da2, ha2, sizeof(unsigned int) * N, hipMemcpyHostToDevice);
hipDeviceSynchronize();
// launch kernel with a large number of threads to saturate bandwidth
int blockSize = 512;
int numBlocks = (N + blockSize - 1) / blockSize;
//dim3 Db = dim3(32,32,1);
//dim3 Dg = dim3(512,1,1);
global_latency <<<numBlocks, blockSize>>>(da0, da1, da2, N, iterations);
hipDeviceSynchronize();
hipError_t error_id = hipGetLastError();
if (error_id != hipSuccess) {
printf("Error kernel is %s\n", hipGetErrorString(error_id));
}
hipDeviceSynchronize();
// free memory on GPu
hipFree(da0);
hipFree(da1);
hipFree(da2);
// free memory on CPU
free(ha0);
free(ha1);
free(ha2);
hipDeviceReset();
}
void measure_global() {
// access 3 1 MB arrays 1000s of times
int iterations = 100;
int N = 1024* 1024/sizeof(unsigned int); // 1 MB
printf("\n=====3 %ld MB arrays * %d times====\n", sizeof(unsigned int)*N/1024/1024, iterations);
parametric_measure_global(N, iterations);
}
int main(){
hipSetDevice(0);
measure_global();
hipDeviceReset();
return 0;
} | .text
.file "l2_peak_bandwidth.hip"
.globl _Z29__device_stub__global_latencyPjS_S_ii # -- Begin function _Z29__device_stub__global_latencyPjS_S_ii
.p2align 4, 0x90
.type _Z29__device_stub__global_latencyPjS_S_ii,@function
_Z29__device_stub__global_latencyPjS_S_ii: # @_Z29__device_stub__global_latencyPjS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14global_latencyPjS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__global_latencyPjS_S_ii, .Lfunc_end0-_Z29__device_stub__global_latencyPjS_S_ii
.cfi_endproc
# -- End function
.globl _Z25parametric_measure_globalii # -- Begin function _Z25parametric_measure_globalii
.p2align 4, 0x90
.type _Z25parametric_measure_globalii,@function
_Z25parametric_measure_globalii: # @_Z25parametric_measure_globalii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, 36(%rsp) # 4-byte Spill
movl %edi, %r12d
callq hipDeviceReset
movslq %r12d, %rbp
leaq (,%rbp,4), %r13
movq %r13, %rdi
callq malloc
movq %rax, %rbx
movq %r13, %rdi
callq malloc
movq %rax, %r14
movq %r13, %rdi
callq malloc
movq %rax, 48(%rsp) # 8-byte Spill
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
testl %ebp, %ebp
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %r12d, %ebp
leaq (,%rbp,4), %rdx
xorl %r15d, %r15d
movq 48(%rsp), %rdi # 8-byte Reload
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $1, (%rbx,%r15,4)
movl $1, (%r14,%r15,4)
incq %r15
cmpq %r15, %rbp
jne .LBB1_2
.LBB1_3: # %._crit_edge
movq 24(%rsp), %rdi
movq %rbx, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %r14, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq 48(%rsp), %r15 # 8-byte Reload
movq %r15, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
leal 511(%r12), %eax
leal 1022(%r12), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $9, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl %r12d, 44(%rsp)
movl 36(%rsp), %eax # 4-byte Reload
movl %eax, 40(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 44(%rsp), %rax
movq %rax, 152(%rsp)
leaq 40(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z14global_latencyPjS_S_ii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
je .LBB1_7
# %bb.6:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB1_7:
callq hipDeviceSynchronize
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
callq hipDeviceReset
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z25parametric_measure_globalii, .Lfunc_end1-_Z25parametric_measure_globalii
.cfi_endproc
# -- End function
.globl _Z14measure_globalv # -- Begin function _Z14measure_globalv
.p2align 4, 0x90
.type _Z14measure_globalv,@function
_Z14measure_globalv: # @_Z14measure_globalv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.L.str.1, %edi
movl $1, %esi
movl $100, %edx
xorl %eax, %eax
callq printf
movl $262144, %edi # imm = 0x40000
movl $100, %esi
popq %rax
.cfi_def_cfa_offset 8
jmp _Z25parametric_measure_globalii # TAILCALL
.Lfunc_end2:
.size _Z14measure_globalv, .Lfunc_end2-_Z14measure_globalv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
xorl %edi, %edi
callq hipSetDevice
movl $.L.str.1, %edi
movl $1, %esi
movl $100, %edx
xorl %eax, %eax
callq printf
movl $262144, %edi # imm = 0x40000
movl $100, %esi
callq _Z25parametric_measure_globalii
callq hipDeviceReset
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14global_latencyPjS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14global_latencyPjS_S_ii,@object # @_Z14global_latencyPjS_S_ii
.section .rodata,"a",@progbits
.globl _Z14global_latencyPjS_S_ii
.p2align 3, 0x0
_Z14global_latencyPjS_S_ii:
.quad _Z29__device_stub__global_latencyPjS_S_ii
.size _Z14global_latencyPjS_S_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error kernel is %s\n"
.size .L.str, 20
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\n=====3 %ld MB arrays * %d times====\n"
.size .L.str.1, 38
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14global_latencyPjS_S_ii"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__global_latencyPjS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14global_latencyPjS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14global_latencyPjS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0060*/ HFMA2.MMA R12, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0c7435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0080*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fe200078e02ff */
/*0090*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e260000002100 */
/*00a0*/ I2F.U32.RP R2, R0 ; /* 0x0000000000027306 */
/* 0x000e620000209000 */
/*00b0*/ IMAD.MOV R11, RZ, RZ, -R0 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0a00 */
/*00c0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fcc0003f45070 */
/*00d0*/ MUFU.RCP R2, R2 ; /* 0x0000000200027308 */
/* 0x002e620000001000 */
/*00e0*/ IMAD R3, R3, c[0x0][0x0], R4 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0204 */
/*00f0*/ IADD3 R5, R3, R0, RZ ; /* 0x0000000003057210 */
/* 0x000fc80007ffe0ff */
/*0100*/ LOP3.LUT R9, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff097212 */
/* 0x000fe400078e33ff */
/*0110*/ IADD3 R6, R2, 0xffffffe, RZ ; /* 0x0ffffffe02067810 */
/* 0x002fe40007ffe0ff */
/*0120*/ IADD3 R9, R9, c[0x0][0x178], R0 ; /* 0x00005e0009097a10 */
/* 0x000fe40007ffe000 */
/*0130*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*0140*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe400078e00ff */
/*0150*/ IMAD R11, R11, R7, RZ ; /* 0x000000070b0b7224 */
/* 0x002fc800078e02ff */
/*0160*/ IMAD.HI.U32 R2, R7, R11, R6 ; /* 0x0000000b07027227 */
/* 0x000fc800078e0006 */
/*0170*/ IMAD.WIDE R10, R3, R12, c[0x0][0x168] ; /* 0x00005a00030a7625 */
/* 0x000fc800078e020c */
/*0180*/ IMAD.HI.U32 R2, R2, R9, RZ ; /* 0x0000000902027227 */
/* 0x000fc800078e00ff */
/*0190*/ IMAD.WIDE R16, R0, 0x4, R10 ; /* 0x0000000400107825 */
/* 0x000fe200078e020a */
/*01a0*/ IADD3 R4, -R2, RZ, RZ ; /* 0x000000ff02047210 */
/* 0x000fc60007ffe1ff */
/*01b0*/ IMAD.IADD R7, R0.reuse, 0x1, R5 ; /* 0x0000000100077824 */
/* 0x040fe400078e0205 */
/*01c0*/ IMAD R9, R0.reuse, R4, R9 ; /* 0x0000000400097224 */
/* 0x040fe200078e0209 */
/*01d0*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe20000000f00 */
/*01e0*/ IMAD.WIDE R22, R0.reuse, 0x4, R16 ; /* 0x0000000400167825 */
/* 0x040fe200078e0210 */
/*01f0*/ IADD3 R6, R0, R7, RZ ; /* 0x0000000700067210 */
/* 0x000fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P0, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fda0003f06070 */
/*0210*/ @P0 IMAD.IADD R9, R9, 0x1, -R0 ; /* 0x0000000109090824 */
/* 0x000fe200078e0a00 */
/*0220*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fc80007ffe0ff */
/*0230*/ ISETP.GE.U32.AND P1, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fe20003f26070 */
/*0240*/ IMAD.WIDE R8, R3, R12, c[0x0][0x160] ; /* 0x0000580003087625 */
/* 0x000fc800078e020c */
/*0250*/ IMAD.WIDE R12, R3, R12, c[0x0][0x170] ; /* 0x00005c00030c7625 */
/* 0x000fc800078e020c */
/*0260*/ IMAD.WIDE R14, R0, 0x4, R8 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0208 */
/*0270*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe20007ffe0ff */
/*0280*/ IMAD.WIDE R18, R0, 0x4, R12 ; /* 0x0000000400127825 */
/* 0x000fe200078e020c */
/*0290*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc600078e33ff */
/*02a0*/ IMAD.WIDE R20, R0, 0x4, R14 ; /* 0x0000000400147825 */
/* 0x000fe200078e020e */
/*02b0*/ IADD3 R34, R2, 0x1, RZ ; /* 0x0000000102227810 */
/* 0x000fc60007ffe0ff */
/*02c0*/ IMAD.WIDE R24, R0, 0x4, R18 ; /* 0x0000000400187825 */
/* 0x000fe200078e0212 */
/*02d0*/ LOP3.LUT R34, R34, 0x3, RZ, 0xc0, !PT ; /* 0x0000000322227812 */
/* 0x000fc600078ec0ff */
/*02e0*/ ISETP.GE.AND P1, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe20003f26270 */
/*02f0*/ BSSY B0, 0x6f0 ; /* 0x000003f000007945 */
/* 0x000fe20003800000 */
/*0300*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fc80007ffe0ff */
/*0310*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x17c], PT ; /* 0x00005f0004007a0c */
/* 0x000fce0003f06270 */
/*0320*/ @P1 BRA 0x6e0 ; /* 0x000003b000001947 */
/* 0x001fea0003800000 */
/*0330*/ ISETP.NE.AND P1, PT, R34, RZ, PT ; /* 0x000000ff2200720c */
/* 0x000fe20003f25270 */
/*0340*/ BSSY B1, 0x4b0 ; /* 0x0000016000017945 */
/* 0x000fe20003800000 */
/*0350*/ IMAD.MOV.U32 R35, RZ, RZ, R3 ; /* 0x000000ffff237224 */
/* 0x000fd600078e0003 */
/*0360*/ @!P1 BRA 0x4a0 ; /* 0x0000013000009947 */
/* 0x000fea0003800000 */
/*0370*/ LDG.E R26, [R10.64] ; /* 0x000000040a1a7981 */
/* 0x000ea8000c1e1900 */
/*0380*/ LDG.E R27, [R8.64] ; /* 0x00000004081b7981 */
/* 0x000ea2000c1e1900 */
/*0390*/ ISETP.NE.AND P1, PT, R34, 0x1, PT ; /* 0x000000012200780c */
/* 0x000fe40003f25270 */
/*03a0*/ MOV R35, R5 ; /* 0x0000000500237202 */
/* 0x000fe40000000f00 */
/*03b0*/ IADD3 R27, R26, R27, RZ ; /* 0x0000001b1a1b7210 */
/* 0x004fca0007ffe0ff */
/*03c0*/ STG.E [R12.64], R27 ; /* 0x0000001b0c007986 */
/* 0x0001e8000c101904 */
/*03d0*/ @!P1 BRA 0x4a0 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*03e0*/ LDG.E R26, [R16.64] ; /* 0x00000004101a7981 */
/* 0x000ea8000c1e1900 */
/*03f0*/ LDG.E R27, [R14.64] ; /* 0x000000040e1b7981 */
/* 0x001ea2000c1e1900 */
/*0400*/ ISETP.NE.AND P1, PT, R34, 0x2, PT ; /* 0x000000022200780c */
/* 0x000fe40003f25270 */
/*0410*/ MOV R35, R7 ; /* 0x0000000700237202 */
/* 0x000fe20000000f00 */
/*0420*/ IMAD.IADD R27, R26, 0x1, R27 ; /* 0x000000011a1b7824 */
/* 0x004fca00078e021b */
/*0430*/ STG.E [R18.64], R27 ; /* 0x0000001b12007986 */
/* 0x0001ea000c101904 */
/*0440*/ @!P1 BRA 0x4a0 ; /* 0x0000005000009947 */
/* 0x000fea0003800000 */
/*0450*/ LDG.E R26, [R20.64] ; /* 0x00000004141a7981 */
/* 0x000ea8000c1e1900 */
/*0460*/ LDG.E R27, [R22.64] ; /* 0x00000004161b7981 */
/* 0x001ea2000c1e1900 */
/*0470*/ IMAD.MOV.U32 R35, RZ, RZ, R6 ; /* 0x000000ffff237224 */
/* 0x000fe200078e0006 */
/*0480*/ IADD3 R27, R26, R27, RZ ; /* 0x0000001b1a1b7210 */
/* 0x004fca0007ffe0ff */
/*0490*/ STG.E [R24.64], R27 ; /* 0x0000001b18007986 */
/* 0x0001e4000c101904 */
/*04a0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*04b0*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f26070 */
/*04c0*/ @!P1 BRA 0x6e0 ; /* 0x0000021000009947 */
/* 0x000fea0003800000 */
/*04d0*/ HFMA2.MMA R32, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff207435 */
/* 0x000fd400000001ff */
/*04e0*/ IMAD.WIDE R28, R35, R32, c[0x0][0x168] ; /* 0x00005a00231c7625 */
/* 0x000fc800078e0220 */
/*04f0*/ IMAD.WIDE R30, R35, R32, c[0x0][0x160] ; /* 0x00005800231e7625 */
/* 0x001fe200078e0220 */
/*0500*/ LDG.E R37, [R28.64] ; /* 0x000000041c257981 */
/* 0x0002a8000c1e1900 */
/*0510*/ LDG.E R26, [R30.64] ; /* 0x000000041e1a7981 */
/* 0x000ea2000c1e1900 */
/*0520*/ IMAD.WIDE R28, R0, 0x4, R28 ; /* 0x00000004001c7825 */
/* 0x002fe200078e021c */
/*0530*/ IADD3 R37, R37, R26, RZ ; /* 0x0000001a25257210 */
/* 0x004fc60007ffe0ff */
/*0540*/ IMAD.WIDE R26, R35, R32, c[0x0][0x170] ; /* 0x00005c00231a7625 */
/* 0x001fc800078e0220 */
/*0550*/ IMAD.WIDE R32, R0.reuse, 0x4, R30 ; /* 0x0000000400207825 */
/* 0x040fe200078e021e */
/*0560*/ STG.E [R26.64], R37 ; /* 0x000000251a007986 */
/* 0x0001e8000c101904 */
/*0570*/ LDG.E R36, [R28.64] ; /* 0x000000041c247981 */
/* 0x0002a8000c1e1900 */
/*0580*/ LDG.E R31, [R32.64] ; /* 0x00000004201f7981 */
/* 0x000ea2000c1e1900 */
/*0590*/ IMAD.WIDE R26, R0, 0x4, R26 ; /* 0x00000004001a7825 */
/* 0x001fc800078e021a */
/*05a0*/ IMAD.WIDE R28, R0, 0x4, R28 ; /* 0x00000004001c7825 */
/* 0x002fc800078e021c */
/*05b0*/ IMAD.IADD R36, R36, 0x1, R31 ; /* 0x0000000124247824 */
/* 0x004fe400078e021f */
/*05c0*/ IMAD.WIDE R30, R0, 0x4, R32 ; /* 0x00000004001e7825 */
/* 0x000fc600078e0220 */
/*05d0*/ STG.E [R26.64], R36 ; /* 0x000000241a007986 */
/* 0x0001e8000c101904 */
/*05e0*/ LDG.E R32, [R28.64] ; /* 0x000000041c207981 */
/* 0x0002a8000c1e1900 */
/*05f0*/ LDG.E R33, [R30.64] ; /* 0x000000041e217981 */
/* 0x000ea2000c1e1900 */
/*0600*/ IMAD.WIDE R26, R0, 0x4, R26 ; /* 0x00000004001a7825 */
/* 0x001fc800078e021a */
/*0610*/ IMAD.WIDE R28, R0, 0x4, R28 ; /* 0x00000004001c7825 */
/* 0x002fe200078e021c */
/*0620*/ IADD3 R37, R32, R33, RZ ; /* 0x0000002120257210 */
/* 0x004fc60007ffe0ff */
/*0630*/ IMAD.WIDE R32, R0.reuse, 0x4, R30 ; /* 0x0000000400207825 */
/* 0x040fe400078e021e */
/*0640*/ STG.E [R26.64], R37 ; /* 0x000000251a007986 */
/* 0x0001e8000c101904 */
/*0650*/ LDG.E R28, [R28.64] ; /* 0x000000041c1c7981 */
/* 0x000ea8000c1e1900 */
/*0660*/ LDG.E R33, [R32.64] ; /* 0x0000000420217981 */
/* 0x000ea2000c1e1900 */
/*0670*/ IMAD.WIDE R30, R0.reuse, 0x4, R26 ; /* 0x00000004001e7825 */
/* 0x040fe200078e021a */
/*0680*/ IADD3 R35, R0, R35, R0 ; /* 0x0000002300237210 */
/* 0x000fc80007ffe000 */
/*0690*/ IADD3 R35, R0, R35, R0 ; /* 0x0000002300237210 */
/* 0x000fc80007ffe000 */
/*06a0*/ ISETP.GE.AND P1, PT, R35, c[0x0][0x178], PT ; /* 0x00005e0023007a0c */
/* 0x000fe40003f26270 */
/*06b0*/ IADD3 R36, R28, R33, RZ ; /* 0x000000211c247210 */
/* 0x004fca0007ffe0ff */
/*06c0*/ STG.E [R30.64], R36 ; /* 0x000000241e007986 */
/* 0x0001ec000c101904 */
/*06d0*/ @!P1 BRA 0x4d0 ; /* 0xfffffdf000009947 */
/* 0x000fea000383ffff */
/*06e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06f0*/ @!P0 BRA 0x2e0 ; /* 0xfffffbe000008947 */
/* 0x000fea000383ffff */
/*0700*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0710*/ BRA 0x710; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14global_latencyPjS_S_ii
.globl _Z14global_latencyPjS_S_ii
.p2align 8
.type _Z14global_latencyPjS_S_ii,@function
_Z14global_latencyPjS_S_ii:
s_load_b32 s12, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s12, 1
s_cbranch_scc1 .LBB0_6
s_clause 0x4
s_load_b32 s8, s[0:1], 0x2c
s_load_b32 s9, s[0:1], 0x20
s_load_b32 s13, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s8, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
s_mul_i32 s8, s9, s0
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_lshl_b64 s[10:11], s[8:9], 2
s_mov_b32 s9, 0
v_ashrrev_i32_e32 v2, 31, v1
v_cmp_gt_i32_e32 vcc_lo, s13, v1
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s14
s_add_i32 s9, s9, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s9, s12
s_cbranch_scc1 .LBB0_6
.LBB0_3:
s_and_saveexec_b32 s14, vcc_lo
s_cbranch_execz .LBB0_2
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
v_mov_b32_e32 v0, v1
s_mov_b32 s15, 0
.p2align 6
.LBB0_5:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v6, s0, s4, v4
v_add_co_ci_u32_e64 v7, s0, s5, v5, s0
v_add_co_u32 v8, s0, s6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v9, s0, s7, v5, s0
v_add_nc_u32_e32 v0, s8, v0
global_load_b32 v10, v[6:7], off
global_load_b32 v8, v[8:9], off
v_add_co_u32 v6, s0, s2, v4
v_add_co_ci_u32_e64 v7, s0, s3, v5, s0
v_add_co_u32 v4, s0, v4, s10
v_cmp_le_i32_e64 s1, s13, v0
v_add_co_ci_u32_e64 v5, s0, s11, v5, s0
s_delay_alu instid0(VALU_DEP_2)
s_or_b32 s15, s1, s15
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v8, v8, v10
global_store_b32 v[6:7], v8, off
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_5
s_branch .LBB0_2
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14global_latencyPjS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14global_latencyPjS_S_ii, .Lfunc_end0-_Z14global_latencyPjS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14global_latencyPjS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14global_latencyPjS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e0c10_00000000-6_l2_peak_bandwidth.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z14global_latencyPjS_S_iiPjS_S_ii
.type _Z40__device_stub__Z14global_latencyPjS_S_iiPjS_S_ii, @function
_Z40__device_stub__Z14global_latencyPjS_S_iiPjS_S_ii:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14global_latencyPjS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z40__device_stub__Z14global_latencyPjS_S_iiPjS_S_ii, .-_Z40__device_stub__Z14global_latencyPjS_S_iiPjS_S_ii
.globl _Z14global_latencyPjS_S_ii
.type _Z14global_latencyPjS_S_ii, @function
_Z14global_latencyPjS_S_ii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z14global_latencyPjS_S_iiPjS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z14global_latencyPjS_S_ii, .-_Z14global_latencyPjS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Error kernel is %s\n"
.text
.globl _Z25parametric_measure_globalii
.type _Z25parametric_measure_globalii, @function
_Z25parametric_measure_globalii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movl %edi, %r14d
movl %esi, %r15d
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
call cudaDeviceReset@PLT
movslq %r14d, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %r14d, %r14d
jle .L12
movl $0, %eax
.L13:
movl $1, 0(%r13,%rax)
movl $1, (%r12,%rax)
movl $0, 0(%rbp,%rax)
addq $4, %rax
cmpq %rax, %rbx
jne .L13
.L12:
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
call cudaThreadSynchronize@PLT
movl $512, 44(%rsp)
movl $1, 48(%rsp)
leal 1022(%r14), %eax
movl %r14d, %edx
addl $511, %edx
cmovns %edx, %eax
sarl $9, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L14:
call cudaThreadSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L20
.L15:
call cudaThreadSynchronize@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
call cudaDeviceReset@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl %r15d, %r8d
movl %r14d, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z40__device_stub__Z14global_latencyPjS_S_iiPjS_S_ii
jmp .L14
.L20:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L15
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z25parametric_measure_globalii, .-_Z25parametric_measure_globalii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "\n=====3 %ld MB arrays * %d times====\n"
.text
.globl _Z14measure_globalv
.type _Z14measure_globalv, @function
_Z14measure_globalv:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $100, %ecx
movl $1, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $100, %esi
movl $262144, %edi
call _Z25parametric_measure_globalii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z14measure_globalv, .-_Z14measure_globalv
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $0, %edi
call cudaSetDevice@PLT
call _Z14measure_globalv
call cudaDeviceReset@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z14global_latencyPjS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z14global_latencyPjS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "l2_peak_bandwidth.hip"
.globl _Z29__device_stub__global_latencyPjS_S_ii # -- Begin function _Z29__device_stub__global_latencyPjS_S_ii
.p2align 4, 0x90
.type _Z29__device_stub__global_latencyPjS_S_ii,@function
_Z29__device_stub__global_latencyPjS_S_ii: # @_Z29__device_stub__global_latencyPjS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14global_latencyPjS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__global_latencyPjS_S_ii, .Lfunc_end0-_Z29__device_stub__global_latencyPjS_S_ii
.cfi_endproc
# -- End function
.globl _Z25parametric_measure_globalii # -- Begin function _Z25parametric_measure_globalii
.p2align 4, 0x90
.type _Z25parametric_measure_globalii,@function
_Z25parametric_measure_globalii: # @_Z25parametric_measure_globalii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, 36(%rsp) # 4-byte Spill
movl %edi, %r12d
callq hipDeviceReset
movslq %r12d, %rbp
leaq (,%rbp,4), %r13
movq %r13, %rdi
callq malloc
movq %rax, %rbx
movq %r13, %rdi
callq malloc
movq %rax, %r14
movq %r13, %rdi
callq malloc
movq %rax, 48(%rsp) # 8-byte Spill
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
testl %ebp, %ebp
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %r12d, %ebp
leaq (,%rbp,4), %rdx
xorl %r15d, %r15d
movq 48(%rsp), %rdi # 8-byte Reload
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $1, (%rbx,%r15,4)
movl $1, (%r14,%r15,4)
incq %r15
cmpq %r15, %rbp
jne .LBB1_2
.LBB1_3: # %._crit_edge
movq 24(%rsp), %rdi
movq %rbx, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %r14, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq 48(%rsp), %r15 # 8-byte Reload
movq %r15, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
leal 511(%r12), %eax
leal 1022(%r12), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $9, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl %r12d, 44(%rsp)
movl 36(%rsp), %eax # 4-byte Reload
movl %eax, 40(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 44(%rsp), %rax
movq %rax, 152(%rsp)
leaq 40(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z14global_latencyPjS_S_ii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
je .LBB1_7
# %bb.6:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB1_7:
callq hipDeviceSynchronize
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
callq hipDeviceReset
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z25parametric_measure_globalii, .Lfunc_end1-_Z25parametric_measure_globalii
.cfi_endproc
# -- End function
.globl _Z14measure_globalv # -- Begin function _Z14measure_globalv
.p2align 4, 0x90
.type _Z14measure_globalv,@function
_Z14measure_globalv: # @_Z14measure_globalv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.L.str.1, %edi
movl $1, %esi
movl $100, %edx
xorl %eax, %eax
callq printf
movl $262144, %edi # imm = 0x40000
movl $100, %esi
popq %rax
.cfi_def_cfa_offset 8
jmp _Z25parametric_measure_globalii # TAILCALL
.Lfunc_end2:
.size _Z14measure_globalv, .Lfunc_end2-_Z14measure_globalv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
xorl %edi, %edi
callq hipSetDevice
movl $.L.str.1, %edi
movl $1, %esi
movl $100, %edx
xorl %eax, %eax
callq printf
movl $262144, %edi # imm = 0x40000
movl $100, %esi
callq _Z25parametric_measure_globalii
callq hipDeviceReset
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14global_latencyPjS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14global_latencyPjS_S_ii,@object # @_Z14global_latencyPjS_S_ii
.section .rodata,"a",@progbits
.globl _Z14global_latencyPjS_S_ii
.p2align 3, 0x0
_Z14global_latencyPjS_S_ii:
.quad _Z29__device_stub__global_latencyPjS_S_ii
.size _Z14global_latencyPjS_S_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error kernel is %s\n"
.size .L.str, 20
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\n=====3 %ld MB arrays * %d times====\n"
.size .L.str.1, 38
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14global_latencyPjS_S_ii"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__global_latencyPjS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14global_latencyPjS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<iostream>
#include<cuda.h>
#include<cuda_runtime.h>
#define N 10
using namespace std;
__global__ void mul(int* a_d, int n){
// printf("%d %d %d\n", blockIdx.x,blockDim.x,threadIdx.x);
int index = blockIdx.x * blockDim.x + threadIdx.x;
if(index < n){
a_d[index] *= 5;
}
}
int main(){
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
int *a, *a_d;
int size = N * sizeof(int);
a = (int*) malloc(size);
cout << "Enter " << N << " numbers: ";
for(int i=0; i<N; i++){
cin>>a[i];
}
cudaMalloc(&a_d, size);
cudaMemcpy(a_d, a, size, cudaMemcpyHostToDevice);
cudaEventRecord(start);
mul<<<1,10>>>(a_d,N);
cudaDeviceSynchronize();
cudaEventRecord(stop);
cudaMemcpy(a, a_d, size, cudaMemcpyDeviceToHost);
cout<<"Matrix After Multiplying:\n";
for(int i=0; i<N; i++){
cout<<a[i]<<" ";
}
float millis = 0;
cudaEventElapsedTime(&millis, start, stop);
cout << "\nElasped Time: " << millis << endl;
return 0;
} | code for sm_80
Function : _Z3mulPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ IMAD R5, R0, 0x5, RZ ; /* 0x0000000500057824 */
/* 0x004fca00078e02ff */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<iostream>
#include<cuda.h>
#include<cuda_runtime.h>
#define N 10
using namespace std;
__global__ void mul(int* a_d, int n){
// printf("%d %d %d\n", blockIdx.x,blockDim.x,threadIdx.x);
int index = blockIdx.x * blockDim.x + threadIdx.x;
if(index < n){
a_d[index] *= 5;
}
}
int main(){
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
int *a, *a_d;
int size = N * sizeof(int);
a = (int*) malloc(size);
cout << "Enter " << N << " numbers: ";
for(int i=0; i<N; i++){
cin>>a[i];
}
cudaMalloc(&a_d, size);
cudaMemcpy(a_d, a, size, cudaMemcpyHostToDevice);
cudaEventRecord(start);
mul<<<1,10>>>(a_d,N);
cudaDeviceSynchronize();
cudaEventRecord(stop);
cudaMemcpy(a, a_d, size, cudaMemcpyDeviceToHost);
cout<<"Matrix After Multiplying:\n";
for(int i=0; i<N; i++){
cout<<a[i]<<" ";
}
float millis = 0;
cudaEventElapsedTime(&millis, start, stop);
cout << "\nElasped Time: " << millis << endl;
return 0;
} | .file "tmpxft_00156e3d_00000000-6_mul_by_five.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z3mulPiiPii
.type _Z23__device_stub__Z3mulPiiPii, @function
_Z23__device_stub__Z3mulPiiPii:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3mulPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z23__device_stub__Z3mulPiiPii, .-_Z23__device_stub__Z3mulPiiPii
.globl _Z3mulPii
.type _Z3mulPii, @function
_Z3mulPii:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z3mulPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3mulPii, .-_Z3mulPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter "
.LC1:
.string " numbers: "
.LC2:
.string "Matrix After Multiplying:\n"
.LC3:
.string " "
.LC5:
.string "\nElasped Time: "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl $40, %edi
call malloc@PLT
movq %rax, %r14
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $10, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %r14, %rbx
leaq 40(%r14), %r12
movq %r14, %rbp
leaq _ZSt3cin(%rip), %r13
.L12:
movq %rbp, %rsi
movq %r13, %rdi
call _ZNSirsERi@PLT
addq $4, %rbp
cmpq %r12, %rbp
jne .L12
leaq 24(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $40, %edx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl $10, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $40, %edx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq _ZSt4cout(%rip), %r13
leaq .LC3(%rip), %rbp
.L14:
movl (%rbx), %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %rbp, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L14
movl $0x00000000, 44(%rsp)
leaq 44(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 44(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $10, %esi
movq 24(%rsp), %rdi
call _Z23__device_stub__Z3mulPiiPii
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z3mulPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z3mulPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<iostream>
#include<cuda.h>
#include<cuda_runtime.h>
#define N 10
using namespace std;
__global__ void mul(int* a_d, int n){
// printf("%d %d %d\n", blockIdx.x,blockDim.x,threadIdx.x);
int index = blockIdx.x * blockDim.x + threadIdx.x;
if(index < n){
a_d[index] *= 5;
}
}
int main(){
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
int *a, *a_d;
int size = N * sizeof(int);
a = (int*) malloc(size);
cout << "Enter " << N << " numbers: ";
for(int i=0; i<N; i++){
cin>>a[i];
}
cudaMalloc(&a_d, size);
cudaMemcpy(a_d, a, size, cudaMemcpyHostToDevice);
cudaEventRecord(start);
mul<<<1,10>>>(a_d,N);
cudaDeviceSynchronize();
cudaEventRecord(stop);
cudaMemcpy(a, a_d, size, cudaMemcpyDeviceToHost);
cout<<"Matrix After Multiplying:\n";
for(int i=0; i<N; i++){
cout<<a[i]<<" ";
}
float millis = 0;
cudaEventElapsedTime(&millis, start, stop);
cout << "\nElasped Time: " << millis << endl;
return 0;
} | #include<iostream>
#include<hip/hip_runtime.h>
#define N 10
using namespace std;
__global__ void mul(int* a_d, int n){
// printf("%d %d %d\n", blockIdx.x,blockDim.x,threadIdx.x);
int index = blockIdx.x * blockDim.x + threadIdx.x;
if(index < n){
a_d[index] *= 5;
}
}
int main(){
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
int *a, *a_d;
int size = N * sizeof(int);
a = (int*) malloc(size);
cout << "Enter " << N << " numbers: ";
for(int i=0; i<N; i++){
cin>>a[i];
}
hipMalloc(&a_d, size);
hipMemcpy(a_d, a, size, hipMemcpyHostToDevice);
hipEventRecord(start);
mul<<<1,10>>>(a_d,N);
hipDeviceSynchronize();
hipEventRecord(stop);
hipMemcpy(a, a_d, size, hipMemcpyDeviceToHost);
cout<<"Matrix After Multiplying:\n";
for(int i=0; i<N; i++){
cout<<a[i]<<" ";
}
float millis = 0;
hipEventElapsedTime(&millis, start, stop);
cout << "\nElasped Time: " << millis << endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include<iostream>
#include<hip/hip_runtime.h>
#define N 10
using namespace std;
__global__ void mul(int* a_d, int n){
// printf("%d %d %d\n", blockIdx.x,blockDim.x,threadIdx.x);
int index = blockIdx.x * blockDim.x + threadIdx.x;
if(index < n){
a_d[index] *= 5;
}
}
int main(){
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
int *a, *a_d;
int size = N * sizeof(int);
a = (int*) malloc(size);
cout << "Enter " << N << " numbers: ";
for(int i=0; i<N; i++){
cin>>a[i];
}
hipMalloc(&a_d, size);
hipMemcpy(a_d, a, size, hipMemcpyHostToDevice);
hipEventRecord(start);
mul<<<1,10>>>(a_d,N);
hipDeviceSynchronize();
hipEventRecord(stop);
hipMemcpy(a, a_d, size, hipMemcpyDeviceToHost);
cout<<"Matrix After Multiplying:\n";
for(int i=0; i<N; i++){
cout<<a[i]<<" ";
}
float millis = 0;
hipEventElapsedTime(&millis, start, stop);
cout << "\nElasped Time: " << millis << endl;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3mulPii
.globl _Z3mulPii
.p2align 8
.type _Z3mulPii,@function
_Z3mulPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_lshl_add_u32 v2, v2, 2, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3mulPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3mulPii, .Lfunc_end0-_Z3mulPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3mulPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3mulPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<iostream>
#include<hip/hip_runtime.h>
#define N 10
using namespace std;
__global__ void mul(int* a_d, int n){
// printf("%d %d %d\n", blockIdx.x,blockDim.x,threadIdx.x);
int index = blockIdx.x * blockDim.x + threadIdx.x;
if(index < n){
a_d[index] *= 5;
}
}
int main(){
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
int *a, *a_d;
int size = N * sizeof(int);
a = (int*) malloc(size);
cout << "Enter " << N << " numbers: ";
for(int i=0; i<N; i++){
cin>>a[i];
}
hipMalloc(&a_d, size);
hipMemcpy(a_d, a, size, hipMemcpyHostToDevice);
hipEventRecord(start);
mul<<<1,10>>>(a_d,N);
hipDeviceSynchronize();
hipEventRecord(stop);
hipMemcpy(a, a_d, size, hipMemcpyDeviceToHost);
cout<<"Matrix After Multiplying:\n";
for(int i=0; i<N; i++){
cout<<a[i]<<" ";
}
float millis = 0;
hipEventElapsedTime(&millis, start, stop);
cout << "\nElasped Time: " << millis << endl;
return 0;
} | .text
.file "mul_by_five.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__mulPii # -- Begin function _Z18__device_stub__mulPii
.p2align 4, 0x90
.type _Z18__device_stub__mulPii,@function
_Z18__device_stub__mulPii: # @_Z18__device_stub__mulPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3mulPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__mulPii, .Lfunc_end0-_Z18__device_stub__mulPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 32(%rsp), %rdi
callq hipEventCreate
movl $40, %edi
callq malloc
movq %rax, %rbx
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $10, %esi
callq _ZNSolsEi
movl $.L.str.1, %esi
movl $10, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq (%rbx,%r14), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
addq $4, %r14
cmpq $40, %r14
jne .LBB1_1
# %bb.2:
movq %rsp, %rdi
movl $40, %esi
callq hipMalloc
movq (%rsp), %rdi
movl $40, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq (%rsp), %rax
movq %rax, 96(%rsp)
movl $10, 12(%rsp)
leaq 96(%rsp), %rax
movq %rax, 16(%rsp)
leaq 12(%rsp), %rax
movq %rax, 24(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z3mulPii, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
movq 32(%rsp), %rdi
xorl %r14d, %r14d
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rsi
movl $40, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $26, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.3, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r14
cmpq $10, %r14
jne .LBB1_5
# %bb.6:
movl $0, 16(%rsp)
movq 40(%rsp), %rsi
movq 32(%rsp), %rdx
leaq 16(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 16(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_11
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_9
# %bb.8:
movzbl 67(%rbx), %ecx
jmp .LBB1_10
.LBB1_9:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_11:
.cfi_def_cfa_offset 128
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3mulPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3mulPii,@object # @_Z3mulPii
.section .rodata,"a",@progbits
.globl _Z3mulPii
.p2align 3, 0x0
_Z3mulPii:
.quad _Z18__device_stub__mulPii
.size _Z3mulPii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter "
.size .L.str, 7
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " numbers: "
.size .L.str.1, 11
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Matrix After Multiplying:\n"
.size .L.str.2, 27
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " "
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\nElasped Time: "
.size .L.str.4, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3mulPii"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__mulPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3mulPii
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3mulPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ IMAD R5, R0, 0x5, RZ ; /* 0x0000000500057824 */
/* 0x004fca00078e02ff */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3mulPii
.globl _Z3mulPii
.p2align 8
.type _Z3mulPii,@function
_Z3mulPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_lshl_add_u32 v2, v2, 2, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3mulPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3mulPii, .Lfunc_end0-_Z3mulPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3mulPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3mulPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00156e3d_00000000-6_mul_by_five.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z3mulPiiPii
.type _Z23__device_stub__Z3mulPiiPii, @function
_Z23__device_stub__Z3mulPiiPii:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3mulPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z23__device_stub__Z3mulPiiPii, .-_Z23__device_stub__Z3mulPiiPii
.globl _Z3mulPii
.type _Z3mulPii, @function
_Z3mulPii:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z3mulPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3mulPii, .-_Z3mulPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter "
.LC1:
.string " numbers: "
.LC2:
.string "Matrix After Multiplying:\n"
.LC3:
.string " "
.LC5:
.string "\nElasped Time: "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl $40, %edi
call malloc@PLT
movq %rax, %r14
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $10, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %r14, %rbx
leaq 40(%r14), %r12
movq %r14, %rbp
leaq _ZSt3cin(%rip), %r13
.L12:
movq %rbp, %rsi
movq %r13, %rdi
call _ZNSirsERi@PLT
addq $4, %rbp
cmpq %r12, %rbp
jne .L12
leaq 24(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $40, %edx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl $10, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $40, %edx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq _ZSt4cout(%rip), %r13
leaq .LC3(%rip), %rbp
.L14:
movl (%rbx), %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %rbp, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L14
movl $0x00000000, 44(%rsp)
leaq 44(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 44(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $10, %esi
movq 24(%rsp), %rdi
call _Z23__device_stub__Z3mulPiiPii
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z3mulPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z3mulPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mul_by_five.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__mulPii # -- Begin function _Z18__device_stub__mulPii
.p2align 4, 0x90
.type _Z18__device_stub__mulPii,@function
_Z18__device_stub__mulPii: # @_Z18__device_stub__mulPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3mulPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__mulPii, .Lfunc_end0-_Z18__device_stub__mulPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 32(%rsp), %rdi
callq hipEventCreate
movl $40, %edi
callq malloc
movq %rax, %rbx
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $10, %esi
callq _ZNSolsEi
movl $.L.str.1, %esi
movl $10, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq (%rbx,%r14), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
addq $4, %r14
cmpq $40, %r14
jne .LBB1_1
# %bb.2:
movq %rsp, %rdi
movl $40, %esi
callq hipMalloc
movq (%rsp), %rdi
movl $40, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq (%rsp), %rax
movq %rax, 96(%rsp)
movl $10, 12(%rsp)
leaq 96(%rsp), %rax
movq %rax, 16(%rsp)
leaq 12(%rsp), %rax
movq %rax, 24(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z3mulPii, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
movq 32(%rsp), %rdi
xorl %r14d, %r14d
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rsi
movl $40, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $26, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.3, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r14
cmpq $10, %r14
jne .LBB1_5
# %bb.6:
movl $0, 16(%rsp)
movq 40(%rsp), %rsi
movq 32(%rsp), %rdx
leaq 16(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 16(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_11
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_9
# %bb.8:
movzbl 67(%rbx), %ecx
jmp .LBB1_10
.LBB1_9:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_11:
.cfi_def_cfa_offset 128
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3mulPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3mulPii,@object # @_Z3mulPii
.section .rodata,"a",@progbits
.globl _Z3mulPii
.p2align 3, 0x0
_Z3mulPii:
.quad _Z18__device_stub__mulPii
.size _Z3mulPii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter "
.size .L.str, 7
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " numbers: "
.size .L.str.1, 11
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Matrix After Multiplying:\n"
.size .L.str.2, 27
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " "
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\nElasped Time: "
.size .L.str.4, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3mulPii"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__mulPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3mulPii
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //Author: Harindranath Ambalampitiya, PhD(Theoretical atomic and molecular physics)
//GPU accelerated Classical Trajectory Monte Carlo Methods
//electron-collision with hydrogen
#include <iostream>
#include<fstream>
#include<math.h>
#include<stdio.h>
#include<ctime>
#include<cstdlib>
#include <chrono>
#include<curand_kernel.h>
using namespace std;
using namespace std::chrono;
// initialize random_number generator on the device
//each thread gets the same seed,but different sequence
__global__ void rng_init(curandState *state,int seed,int n)
{
int id=blockIdx.x*blockDim.x+threadIdx.x;
if(id<n)
{
curand_init(seed, id, 0, &state[id]);
}
}
//root-search(bisection method) on the device
__device__ float rootxi(float alpha,float ecc,float x1,float x2)
{
int jmax=50;
float xacc=1e-4f;//accuracy
float dx,xmid,rtb;
float f=x1-ecc*sin(x1)-alpha;
float fmid=x2-ecc*sin(x2)-alpha;
rtb = f < 0.0 ? (dx=x2-x1,x1) : (dx=x1-x2,x2);
for (int j=0;j<jmax;j++)
{
xmid=rtb+(dx *= 0.5);
fmid=xmid-ecc*sin(xmid)-alpha;
if (fmid <= 0.0)
rtb=xmid;
if (abs(dx) < xacc || fmid == 0.0)
return rtb;
}
return 0;
}
// derivatives for Runge-Kutta stepper
__device__ void derivs(float t, float *y, float *dydt)
{
float R1=sqrt(y[0]*y[0]+y[2]*y[2]+y[4]*y[4]+.2);
float R2=sqrt(y[6]*y[6]+y[8]*y[8]+y[10]*y[10]+.2);
float dx=y[0]-y[6];
float dy=y[2]-y[8];
float dz=y[4]-y[10];
float R3=sqrt(dx*dx+dy*dy+dz*dz+.2);
dydt[0]=y[1];
dydt[1]=-y[0]/powf(R1,3)+dx/powf(R3,3);
dydt[2]=y[3];
dydt[3]=-y[2]/powf(R1,3)+dy/powf(R3,3);
dydt[4]=y[5];
dydt[5]=-y[4]/powf(R1,3)+dz/powf(R3,3);
dydt[6]=y[7];
dydt[7]=-y[6]/powf(R2,3)-dx/powf(R3,3);
dydt[8]=y[9];
dydt[9]=-y[8]/powf(R2,3)-dy/powf(R3,3);
dydt[10]=y[11];
dydt[11]=-y[10]/powf(R2,3)-dz/powf(R3,3);
}
//Let's calculate tics on the device
__global__ void ticsKernel(curandState *state,int *a,float Ev,float bstep)
{
int nps=3,lps=0;
// eliptical orbit parameters
//semi-major axis,period/2pi,Ps energy
float asem=powf((float)nps,2.),tred=sqrtf(powf(asem,3.));
float ehyd=-0.5/asem;
float pi=2.*asinf(1.0f);
//total energy,maximum-time iteration
float energy=ehyd+Ev/27.21,tmax=500.;
//initial velocity and z coordinates
float vinit=sqrtf(Ev/27.21),zinit=-25.;
//asymptotic z
float zasym=25.;
//impact parameter that each thread gets
int idx=blockIdx.x*blockDim.x+threadIdx.x;
float bimpact=bstep*(float)idx;
a[idx]=0;
//printf("blockid,threadid:%i\t%i\t%f \n",blockIdx.x,
//threadIdx.x,bimpact);
//copy state to local memory
curandState localState = state[idx];
// run ntrjs amount of classical trajectories
//initialize the breakup events
int ibr=0;
//first initialize the electron/positron
float y[12],dydt[12];
y[0]=bimpact;
y[1]=0.;
y[2]=0.;
y[3]=0.;
y[4]=zinit;
y[5]=vinit;
for(int i=0;i<1;i++)
{
//generate 5 random numbers in the uniform grid (0,1]
//For micro canonical ensemble
//printf("idx,i %i \t %i \n",idx,i);
float ran0 = curand_uniform(&localState);
float ran1 = curand_uniform(&localState);
float ran2 = curand_uniform(&localState);
float ran3 = curand_uniform(&localState);
float ran4 = curand_uniform(&localState);
float beta=ran0;
float alpha=ran1*2.*pi;
float psi=ran2*2.*pi;
float cothe=2.*ran3-1.;
float phi=ran4*2.*pi;
//eccentricity of the orbit
float ecc=sqrtf(1.-beta);
//root-search for eccentric anomaly
float xip=rootxi(alpha,ecc,0.0f,2.*pi);
float sixi=sinf(xip),coxi=cosf(xip);
//initial unrotated coordinates and velocities
float xr[3],vr[3];
float den=tred*(1.0f-ecc*coxi);
xr[0]=asem*sqrtf(beta)*sixi;
xr[1]=0.0f;
xr[2]=asem*(coxi-ecc);
vr[0]=asem*sqrtf(beta)*coxi/den;
vr[1]=0.;
vr[2]=-asem*sixi/den;
// check the energy
float ekin0=.5*(vr[0]*vr[0]+vr[1]*vr[1]+vr[2]*vr[2]);
float erel=ekin0-1.0f/sqrtf(xr[0]*xr[0]+xr[1]*xr[1]+xr[2]*xr[2]);
//printf("ehyd,erel: %f \t %f \n", ehyd,erel);
//prepare Euler matrix
float eul[3][3];
float co1=cos(psi),si1=sin(psi),co3=cos(phi),si3=sin(phi);
float sithe=sqrt(1.-cothe*cothe);
eul[0][0]=co1*co3-si1*cothe*si3;
eul[0][1]=-co1*si3-si1*cothe*co3;
eul[0][2]=si1*sithe;
eul[1][0]=si1*co3+co1*cothe*si3;
eul[1][1]=-si1*si3+co1*cothe*co3;
eul[1][2]=-co1*sithe;
eul[2][0]=sithe*si3;
eul[2][1]=sithe*co3;
eul[2][2]=cothe;
//rotate relative coordinates and velocities
float va[3],xa[3];
for(int ii=0;ii<3;ii++)
{
va[ii]=0.;
xa[ii]=0.;
for(int jj=0;jj<3;jj++)
{
va[ii]=va[ii]+eul[ii][jj]*vr[jj];
xa[ii]=xa[ii]+eul[ii][jj]*xr[jj];
}
//transform to the lab-frame
xa[ii]=xa[ii];
va[ii]=va[ii];
}
//initialize the electron-positron
y[6]=xa[0];
y[7]=va[0];
y[8]=xa[1];
y[9]=va[1];
y[10]=xa[2];
y[11]=va[2];
// check the initial energy
float R1=sqrt(y[0]*y[0]+y[2]*y[2]+y[4]*y[4]+.2);
float R2=sqrt(y[6]*y[6]+y[8]*y[8]+y[10]*y[10]+.2);
float dx=y[0]-y[6];
float dy=y[2]-y[8];
float dz=y[4]-y[10];
float R3=sqrt(dx*dx+dy*dy+dz*dz+.2);
float ekin=.5*(y[1]*y[1]+y[3]*y[3]+y[5]*y[5]);
float pkin=.5*(y[7]*y[7]+y[9]*y[9]+y[11]*y[11]);
float en0=ekin+pkin-1./R1-1./R2+1./R3;
derivs(0.,y,dydt);
float run_time=0.;
float tstep=1.;
int iter=tmax/tstep;
//Runge-Kutta Stepper
float dym[12],dyt[12],yt[12],yout[12];
float h=tstep,hh=h/2.,h6=h/6.;
for(int it=0;it<iter;it++)
{
//propagate y,dydt a tstep
//------------------------------------------------//
for(int ij=0;ij<12;ij++)yt[ij]=y[ij]+hh*dydt[ij];
derivs(run_time+hh,yt,dyt);
for(int ik=0;ik<12;ik++)yt[ik]=y[ik]+hh*dyt[ik];
derivs(run_time+hh,yt,dym);
for (int il=0;il<12;il++)
{
yt[il]=y[il]+h*dym[il];
dym[il] += dyt[il];
}
derivs(run_time+h,yt,dyt);
for (int ir=0;ir<12;ir++)
{
yout[ir]=y[ir]+h6*(dydt[ir]+dyt[ir]+2.0*dym[ir]);
}
//-----------------------------------------------//
//re-initialize the stepper
for(int iw=0;iw<12;iw++)y[iw]=yout[iw];
derivs(run_time+h,y,dydt);
//printf("%f\t%f\t%f\t%f\t%f\t%f\n",y[0],y[2],y[4],y[6],y[8],
//y[10]);
if(y[10]>=zasym)
break;
run_time=run_time+h;
}
//check the final energy
R1=sqrt(y[0]*y[0]+y[2]*y[2]+y[4]*y[4]+.2);
R2=sqrt(y[6]*y[6]+y[8]*y[8]+y[10]*y[10]+.2);
dx=y[0]-y[6];
dy=y[2]-y[8];
dz=y[4]-y[10];
R3=sqrt(dx*dx+dy*dy+dz*dz+.2);
ekin=.5*(y[1]*y[1]+y[3]*y[3]+y[5]*y[5]);
pkin=.5*(y[7]*y[7]+y[9]*y[9]+y[11]*y[11]);
float enf0=ekin+pkin-1./R1-1./R2+1./R3;
//check the relative energy between incomping elecron and proton/antiproton
float en1=ekin-1./R1;
float en2=pkin-1./R2;
if(en1>=0.0f && en2>=0.0f)
ibr=ibr+1;
//printf("bimpact,en1,en2,ibr: %f \t %f \t %f \t %i \n",
//bimpact,en1,en2,ibr);
}
//copy local memory to global
state[idx] = localState;
a[idx]=ibr;
//printf("here \n");
//printf("inside: %i \n",ibr);
}
float cudaticsPs(float Ev)
{
float pi=2.*asinf(1.0f);
// number of threads and blocks
// number of threads:range of impact parameters
//number of blocks: shares the total number of classical trajectories required
//int block_size,minGridSize;
//predefined number of trajectories for each block
int ntrjs=5000;
int block_size,minGridSize;
//cudaOccupancyMaxPotentialBlockSize(&minGridSize, &block_size, ticsKernel, 0, ntrjs);
//printf("block size, gridsize %i \t %i \n",block_size, minGridSize);
block_size=32;
minGridSize=1;
int n_procs=minGridSize*block_size;
//memory allocation in the host and device
size_t size=n_procs *sizeof(int);
int* a_h=(int*)malloc(size);
int* a_d;
cudaMalloc((void **) &a_d, size);
//random_states
curandState *devStates;
cudaMalloc((void **) &devStates, n_procs *sizeof(curandState));
int* ibr=(int*)malloc(size);
for(int i=0;i<n_procs;i++)ibr[i]=0;
// each thread gets a single impact parameters
float bmax=18.;
float bstep=bmax/(float)n_procs;
//initialize the random numbers
int s=12345;//seed
rng_init<<<minGridSize,block_size>>>(devStates, s, n_procs);
//pass it to parallel processing
//each parallel unit counts the number of break-up events
//run the kernel in a loop
for(int iker=0;iker<ntrjs;iker++)
{
ticsKernel<<<minGridSize,block_size>>>(devStates,a_d,Ev,bstep);
cudaDeviceSynchronize();
cudaMemcpy(a_h,a_d, sizeof(int)*n_procs,cudaMemcpyDeviceToHost);
for(int i=0;i<minGridSize;i++)
{
for(int j=0;j<block_size;j++)
{
int idx=i*block_size+j;
ibr[idx] = ibr[idx]+a_h[idx];
}
}
}
// compute the cross section
float tics=0.;
for(int i=0;i<minGridSize;i++)
{
for(int j=0;j<block_size;j++)
{
int idx=i*block_size+j;
float bimpact=bstep*(float)idx;
//printf("b,ibr:%f \t %i\n",bimpact,ibr[idx]);
if(ibr[idx]<=5)
ibr[idx]=0;
tics=tics+2.*pi*bstep*bimpact*(float)ibr[idx]/float(ntrjs);
}
}
//now free-up the space
free(a_h);
cudaFree(a_d);
return tics;
}
int main()
{
fstream pstics;
pstics.open("ticscu.txt",ios::out);
auto start = high_resolution_clock::now();
// initial hydrogen n,l states
int nps=3,lps=0;
//Threshold energy for ionization (a.u)
float eth=.5/powf((float)nps,2);
//initial electron energy
float Ev;
for(int i=0;i<50;i++)
{
Ev=eth*27.21+(float)i*2.;
float tics=cudaticsPs(Ev);
printf("Break-up cross section at %f eV is: %f \n ",Ev,tics);
pstics<<Ev<<"\t"<<tics<<endl;
}
auto stop = high_resolution_clock::now();
auto duration = duration_cast<seconds>(stop - start);
cout<<"Duration (s)"<<"\t"<<duration.count()<<endl;
} | .file "tmpxft_001b4fb2_00000000-6_ehyd2.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4122:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4122:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6rootxiffff
.type _Z6rootxiffff, @function
_Z6rootxiffff:
.LFB4113:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE4113:
.size _Z6rootxiffff, .-_Z6rootxiffff
.globl _Z6derivsfPfS_
.type _Z6derivsfPfS_, @function
_Z6derivsfPfS_:
.LFB4114:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE4114:
.size _Z6derivsfPfS_, .-_Z6derivsfPfS_
.globl _Z47__device_stub__Z8rng_initP17curandStateXORWOWiiP17curandStateXORWOWii
.type _Z47__device_stub__Z8rng_initP17curandStateXORWOWiiP17curandStateXORWOWii, @function
_Z47__device_stub__Z8rng_initP17curandStateXORWOWiiP17curandStateXORWOWii:
.LFB4144:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8rng_initP17curandStateXORWOWii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4144:
.size _Z47__device_stub__Z8rng_initP17curandStateXORWOWiiP17curandStateXORWOWii, .-_Z47__device_stub__Z8rng_initP17curandStateXORWOWiiP17curandStateXORWOWii
.globl _Z8rng_initP17curandStateXORWOWii
.type _Z8rng_initP17curandStateXORWOWii, @function
_Z8rng_initP17curandStateXORWOWii:
.LFB4145:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z8rng_initP17curandStateXORWOWiiP17curandStateXORWOWii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4145:
.size _Z8rng_initP17curandStateXORWOWii, .-_Z8rng_initP17curandStateXORWOWii
.globl _Z52__device_stub__Z10ticsKernelP17curandStateXORWOWPiffP17curandStateXORWOWPiff
.type _Z52__device_stub__Z10ticsKernelP17curandStateXORWOWPiffP17curandStateXORWOWPiff, @function
_Z52__device_stub__Z10ticsKernelP17curandStateXORWOWPiffP17curandStateXORWOWPiff:
.LFB4146:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10ticsKernelP17curandStateXORWOWPiff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4146:
.size _Z52__device_stub__Z10ticsKernelP17curandStateXORWOWPiffP17curandStateXORWOWPiff, .-_Z52__device_stub__Z10ticsKernelP17curandStateXORWOWPiffP17curandStateXORWOWPiff
.globl _Z10ticsKernelP17curandStateXORWOWPiff
.type _Z10ticsKernelP17curandStateXORWOWPiff, @function
_Z10ticsKernelP17curandStateXORWOWPiff:
.LFB4147:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z10ticsKernelP17curandStateXORWOWPiffP17curandStateXORWOWPiff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4147:
.size _Z10ticsKernelP17curandStateXORWOWPiff, .-_Z10ticsKernelP17curandStateXORWOWPiff
.globl _Z10cudaticsPsf
.type _Z10cudaticsPsf, @function
_Z10cudaticsPsf:
.LFB4115:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $128, %edi
call malloc@PLT
movq %rax, %rbp
leaq 16(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $1536, %esi
call cudaMalloc@PLT
movl $128, %edi
call malloc@PLT
movq %rax, %rbx
leaq 128(%rax), %rdx
.L24:
movl $0, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L24
movl $32, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L25:
movl $5000, %r12d
.L28:
movl $32, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L26
movss .LC1(%rip), %xmm1
movss 12(%rsp), %xmm0
movq 16(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z52__device_stub__Z10ticsKernelP17curandStateXORWOWPiffP17curandStateXORWOWPiff
.L26:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $128, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %eax
.L27:
movl 0(%rbp,%rax), %edx
addl %edx, (%rbx,%rax)
addq $4, %rax
cmpq $128, %rax
jne .L27
subl $1, %r12d
jne .L28
movl $0, %eax
movl $0x00000000, 12(%rsp)
movss .LC1(%rip), %xmm5
movsd .LC2(%rip), %xmm4
movsd .LC3(%rip), %xmm3
jmp .L30
.L37:
movl $32, %edx
movl $12345, %esi
movq 24(%rsp), %rdi
call _Z47__device_stub__Z8rng_initP17curandStateXORWOWiiP17curandStateXORWOWii
jmp .L25
.L29:
pxor %xmm1, %xmm1
cvtsi2ssl (%rbx,%rax,4), %xmm1
pxor %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtss2sd %xmm2, %xmm1
mulsd %xmm4, %xmm1
mulsd %xmm1, %xmm0
divsd %xmm3, %xmm0
pxor %xmm1, %xmm1
cvtss2sd 12(%rsp), %xmm1
addsd %xmm1, %xmm0
pxor %xmm6, %xmm6
cvtsd2ss %xmm0, %xmm6
movss %xmm6, 12(%rsp)
addq $1, %rax
cmpq $32, %rax
je .L38
.L30:
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
mulss %xmm5, %xmm2
cmpl $5, (%rbx,%rax,4)
jg .L29
movl $0, (%rbx,%rax,4)
jmp .L29
.L38:
movq %rbp, %rdi
call free@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L39
movss 12(%rsp), %xmm0
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4115:
.size _Z10cudaticsPsf, .-_Z10cudaticsPsf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "_Z10ticsKernelP17curandStateXORWOWPiff"
.align 8
.LC5:
.string "_Z8rng_initP17curandStateXORWOWii"
.section .rodata.str1.1,"aMS",@progbits,1
.LC6:
.string "precalc_xorwow_matrix"
.LC7:
.string "precalc_xorwow_offset_matrix"
.LC8:
.string "mrg32k3aM1"
.LC9:
.string "mrg32k3aM2"
.LC10:
.string "mrg32k3aM1SubSeq"
.LC11:
.string "mrg32k3aM2SubSeq"
.LC12:
.string "mrg32k3aM1Seq"
.LC13:
.string "mrg32k3aM2Seq"
.LC14:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4149:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z10ticsKernelP17curandStateXORWOWPiff(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z8rng_initP17curandStateXORWOWii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4149:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.1
.LC15:
.string "ticscu.txt"
.section .rodata.str1.8
.align 8
.LC17:
.string "Break-up cross section at %f eV is: %f \n "
.section .rodata.str1.1
.LC18:
.string "\t"
.LC19:
.string "Duration (s)"
.text
.globl main
.type main, @function
main:
.LFB4116:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4116
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $568, %rsp
.cfi_def_cfa_offset 624
movq %fs:40, %rax
movq %rax, 552(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rbx
movq %rbx, %rdi
.LEHB0:
call _ZNSt13basic_fstreamIcSt11char_traitsIcEEC1Ev@PLT
.LEHE0:
movl $16, %edx
leaq .LC15(%rip), %rsi
movq %rbx, %rdi
.LEHB1:
call _ZNSt13basic_fstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, 8(%rsp)
movl $0, %r12d
leaq .LC17(%rip), %r13
leaq 32(%rsp), %r14
leaq .LC18(%rip), %r15
jmp .L47
.L59:
pxor %xmm3, %xmm3
cvtss2sd %xmm0, %xmm3
movq %xmm3, %rbp
pxor %xmm4, %xmm4
cvtss2sd 4(%rsp), %xmm4
movq %xmm4, %rbx
movapd %xmm3, %xmm1
movapd %xmm4, %xmm0
movq %r13, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movq %rbx, %xmm0
movq %r14, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $1, %edx
movq %r15, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rbp, %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L55
cmpb $0, 56(%rbp)
je .L45
movzbl 67(%rbp), %esi
.L46:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
jmp .L56
.L55:
movq 552(%rsp), %rax
subq %fs:40, %rax
jne .L57
call _ZSt16__throw_bad_castv@PLT
.L51:
endbr64
movq %rax, %rbx
leaq 16(%rsp), %rdi
call _ZNSt13basic_fstreamIcSt11char_traitsIcEED1Ev@PLT
movq 552(%rsp), %rax
subq %fs:40, %rax
je .L49
call __stack_chk_fail@PLT
.L57:
call __stack_chk_fail@PLT
.L45:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L46
.L56:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %r12d
cmpl $50, %r12d
je .L58
.L47:
pxor %xmm0, %xmm0
cvtsi2ssl %r12d, %xmm0
cvtss2sd %xmm0, %xmm0
addsd %xmm0, %xmm0
addsd .LC16(%rip), %xmm0
pxor %xmm2, %xmm2
cvtsd2ss %xmm0, %xmm2
movss %xmm2, 4(%rsp)
movaps %xmm2, %xmm0
call _Z10cudaticsPsf
jmp .L59
.L58:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq 8(%rsp), %rcx
subq %rcx, %rax
movq %rax, %rcx
movabsq $1237940039285380275, %rdx
imulq %rdx
sarq $26, %rdx
sarq $63, %rcx
subq %rcx, %rdx
movq %rdx, %rbx
leaq .LC19(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC18(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE1:
leaq 16(%rsp), %rdi
call _ZNSt13basic_fstreamIcSt11char_traitsIcEED1Ev@PLT
movq 552(%rsp), %rax
subq %fs:40, %rax
jne .L60
movl $0, %eax
addq $568, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.LEHE2:
.L60:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4116:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4116:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4116-.LLSDACSB4116
.LLSDACSB4116:
.uleb128 .LEHB0-.LFB4116
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4116
.uleb128 .LEHE1-.LEHB1
.uleb128 .L51-.LFB4116
.uleb128 0
.uleb128 .LEHB2-.LFB4116
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.LLSDACSE4116:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1058013184
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long -872415232
.long 1074546234
.align 8
.LC3:
.long 0
.long 1085507584
.align 8
.LC16:
.long 1711443804
.long 1073229769
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //Author: Harindranath Ambalampitiya, PhD(Theoretical atomic and molecular physics)
//GPU accelerated Classical Trajectory Monte Carlo Methods
//electron-collision with hydrogen
#include <iostream>
#include<fstream>
#include<math.h>
#include<stdio.h>
#include<ctime>
#include<cstdlib>
#include <chrono>
#include<curand_kernel.h>
using namespace std;
using namespace std::chrono;
// initialize random_number generator on the device
//each thread gets the same seed,but different sequence
__global__ void rng_init(curandState *state,int seed,int n)
{
int id=blockIdx.x*blockDim.x+threadIdx.x;
if(id<n)
{
curand_init(seed, id, 0, &state[id]);
}
}
//root-search(bisection method) on the device
__device__ float rootxi(float alpha,float ecc,float x1,float x2)
{
int jmax=50;
float xacc=1e-4f;//accuracy
float dx,xmid,rtb;
float f=x1-ecc*sin(x1)-alpha;
float fmid=x2-ecc*sin(x2)-alpha;
rtb = f < 0.0 ? (dx=x2-x1,x1) : (dx=x1-x2,x2);
for (int j=0;j<jmax;j++)
{
xmid=rtb+(dx *= 0.5);
fmid=xmid-ecc*sin(xmid)-alpha;
if (fmid <= 0.0)
rtb=xmid;
if (abs(dx) < xacc || fmid == 0.0)
return rtb;
}
return 0;
}
// derivatives for Runge-Kutta stepper
__device__ void derivs(float t, float *y, float *dydt)
{
float R1=sqrt(y[0]*y[0]+y[2]*y[2]+y[4]*y[4]+.2);
float R2=sqrt(y[6]*y[6]+y[8]*y[8]+y[10]*y[10]+.2);
float dx=y[0]-y[6];
float dy=y[2]-y[8];
float dz=y[4]-y[10];
float R3=sqrt(dx*dx+dy*dy+dz*dz+.2);
dydt[0]=y[1];
dydt[1]=-y[0]/powf(R1,3)+dx/powf(R3,3);
dydt[2]=y[3];
dydt[3]=-y[2]/powf(R1,3)+dy/powf(R3,3);
dydt[4]=y[5];
dydt[5]=-y[4]/powf(R1,3)+dz/powf(R3,3);
dydt[6]=y[7];
dydt[7]=-y[6]/powf(R2,3)-dx/powf(R3,3);
dydt[8]=y[9];
dydt[9]=-y[8]/powf(R2,3)-dy/powf(R3,3);
dydt[10]=y[11];
dydt[11]=-y[10]/powf(R2,3)-dz/powf(R3,3);
}
//Let's calculate tics on the device
__global__ void ticsKernel(curandState *state,int *a,float Ev,float bstep)
{
int nps=3,lps=0;
// eliptical orbit parameters
//semi-major axis,period/2pi,Ps energy
float asem=powf((float)nps,2.),tred=sqrtf(powf(asem,3.));
float ehyd=-0.5/asem;
float pi=2.*asinf(1.0f);
//total energy,maximum-time iteration
float energy=ehyd+Ev/27.21,tmax=500.;
//initial velocity and z coordinates
float vinit=sqrtf(Ev/27.21),zinit=-25.;
//asymptotic z
float zasym=25.;
//impact parameter that each thread gets
int idx=blockIdx.x*blockDim.x+threadIdx.x;
float bimpact=bstep*(float)idx;
a[idx]=0;
//printf("blockid,threadid:%i\t%i\t%f \n",blockIdx.x,
//threadIdx.x,bimpact);
//copy state to local memory
curandState localState = state[idx];
// run ntrjs amount of classical trajectories
//initialize the breakup events
int ibr=0;
//first initialize the electron/positron
float y[12],dydt[12];
y[0]=bimpact;
y[1]=0.;
y[2]=0.;
y[3]=0.;
y[4]=zinit;
y[5]=vinit;
for(int i=0;i<1;i++)
{
//generate 5 random numbers in the uniform grid (0,1]
//For micro canonical ensemble
//printf("idx,i %i \t %i \n",idx,i);
float ran0 = curand_uniform(&localState);
float ran1 = curand_uniform(&localState);
float ran2 = curand_uniform(&localState);
float ran3 = curand_uniform(&localState);
float ran4 = curand_uniform(&localState);
float beta=ran0;
float alpha=ran1*2.*pi;
float psi=ran2*2.*pi;
float cothe=2.*ran3-1.;
float phi=ran4*2.*pi;
//eccentricity of the orbit
float ecc=sqrtf(1.-beta);
//root-search for eccentric anomaly
float xip=rootxi(alpha,ecc,0.0f,2.*pi);
float sixi=sinf(xip),coxi=cosf(xip);
//initial unrotated coordinates and velocities
float xr[3],vr[3];
float den=tred*(1.0f-ecc*coxi);
xr[0]=asem*sqrtf(beta)*sixi;
xr[1]=0.0f;
xr[2]=asem*(coxi-ecc);
vr[0]=asem*sqrtf(beta)*coxi/den;
vr[1]=0.;
vr[2]=-asem*sixi/den;
// check the energy
float ekin0=.5*(vr[0]*vr[0]+vr[1]*vr[1]+vr[2]*vr[2]);
float erel=ekin0-1.0f/sqrtf(xr[0]*xr[0]+xr[1]*xr[1]+xr[2]*xr[2]);
//printf("ehyd,erel: %f \t %f \n", ehyd,erel);
//prepare Euler matrix
float eul[3][3];
float co1=cos(psi),si1=sin(psi),co3=cos(phi),si3=sin(phi);
float sithe=sqrt(1.-cothe*cothe);
eul[0][0]=co1*co3-si1*cothe*si3;
eul[0][1]=-co1*si3-si1*cothe*co3;
eul[0][2]=si1*sithe;
eul[1][0]=si1*co3+co1*cothe*si3;
eul[1][1]=-si1*si3+co1*cothe*co3;
eul[1][2]=-co1*sithe;
eul[2][0]=sithe*si3;
eul[2][1]=sithe*co3;
eul[2][2]=cothe;
//rotate relative coordinates and velocities
float va[3],xa[3];
for(int ii=0;ii<3;ii++)
{
va[ii]=0.;
xa[ii]=0.;
for(int jj=0;jj<3;jj++)
{
va[ii]=va[ii]+eul[ii][jj]*vr[jj];
xa[ii]=xa[ii]+eul[ii][jj]*xr[jj];
}
//transform to the lab-frame
xa[ii]=xa[ii];
va[ii]=va[ii];
}
//initialize the electron-positron
y[6]=xa[0];
y[7]=va[0];
y[8]=xa[1];
y[9]=va[1];
y[10]=xa[2];
y[11]=va[2];
// check the initial energy
float R1=sqrt(y[0]*y[0]+y[2]*y[2]+y[4]*y[4]+.2);
float R2=sqrt(y[6]*y[6]+y[8]*y[8]+y[10]*y[10]+.2);
float dx=y[0]-y[6];
float dy=y[2]-y[8];
float dz=y[4]-y[10];
float R3=sqrt(dx*dx+dy*dy+dz*dz+.2);
float ekin=.5*(y[1]*y[1]+y[3]*y[3]+y[5]*y[5]);
float pkin=.5*(y[7]*y[7]+y[9]*y[9]+y[11]*y[11]);
float en0=ekin+pkin-1./R1-1./R2+1./R3;
derivs(0.,y,dydt);
float run_time=0.;
float tstep=1.;
int iter=tmax/tstep;
//Runge-Kutta Stepper
float dym[12],dyt[12],yt[12],yout[12];
float h=tstep,hh=h/2.,h6=h/6.;
for(int it=0;it<iter;it++)
{
//propagate y,dydt a tstep
//------------------------------------------------//
for(int ij=0;ij<12;ij++)yt[ij]=y[ij]+hh*dydt[ij];
derivs(run_time+hh,yt,dyt);
for(int ik=0;ik<12;ik++)yt[ik]=y[ik]+hh*dyt[ik];
derivs(run_time+hh,yt,dym);
for (int il=0;il<12;il++)
{
yt[il]=y[il]+h*dym[il];
dym[il] += dyt[il];
}
derivs(run_time+h,yt,dyt);
for (int ir=0;ir<12;ir++)
{
yout[ir]=y[ir]+h6*(dydt[ir]+dyt[ir]+2.0*dym[ir]);
}
//-----------------------------------------------//
//re-initialize the stepper
for(int iw=0;iw<12;iw++)y[iw]=yout[iw];
derivs(run_time+h,y,dydt);
//printf("%f\t%f\t%f\t%f\t%f\t%f\n",y[0],y[2],y[4],y[6],y[8],
//y[10]);
if(y[10]>=zasym)
break;
run_time=run_time+h;
}
//check the final energy
R1=sqrt(y[0]*y[0]+y[2]*y[2]+y[4]*y[4]+.2);
R2=sqrt(y[6]*y[6]+y[8]*y[8]+y[10]*y[10]+.2);
dx=y[0]-y[6];
dy=y[2]-y[8];
dz=y[4]-y[10];
R3=sqrt(dx*dx+dy*dy+dz*dz+.2);
ekin=.5*(y[1]*y[1]+y[3]*y[3]+y[5]*y[5]);
pkin=.5*(y[7]*y[7]+y[9]*y[9]+y[11]*y[11]);
float enf0=ekin+pkin-1./R1-1./R2+1./R3;
//check the relative energy between incomping elecron and proton/antiproton
float en1=ekin-1./R1;
float en2=pkin-1./R2;
if(en1>=0.0f && en2>=0.0f)
ibr=ibr+1;
//printf("bimpact,en1,en2,ibr: %f \t %f \t %f \t %i \n",
//bimpact,en1,en2,ibr);
}
//copy local memory to global
state[idx] = localState;
a[idx]=ibr;
//printf("here \n");
//printf("inside: %i \n",ibr);
}
float cudaticsPs(float Ev)
{
float pi=2.*asinf(1.0f);
// number of threads and blocks
// number of threads:range of impact parameters
//number of blocks: shares the total number of classical trajectories required
//int block_size,minGridSize;
//predefined number of trajectories for each block
int ntrjs=5000;
int block_size,minGridSize;
//cudaOccupancyMaxPotentialBlockSize(&minGridSize, &block_size, ticsKernel, 0, ntrjs);
//printf("block size, gridsize %i \t %i \n",block_size, minGridSize);
block_size=32;
minGridSize=1;
int n_procs=minGridSize*block_size;
//memory allocation in the host and device
size_t size=n_procs *sizeof(int);
int* a_h=(int*)malloc(size);
int* a_d;
cudaMalloc((void **) &a_d, size);
//random_states
curandState *devStates;
cudaMalloc((void **) &devStates, n_procs *sizeof(curandState));
int* ibr=(int*)malloc(size);
for(int i=0;i<n_procs;i++)ibr[i]=0;
// each thread gets a single impact parameters
float bmax=18.;
float bstep=bmax/(float)n_procs;
//initialize the random numbers
int s=12345;//seed
rng_init<<<minGridSize,block_size>>>(devStates, s, n_procs);
//pass it to parallel processing
//each parallel unit counts the number of break-up events
//run the kernel in a loop
for(int iker=0;iker<ntrjs;iker++)
{
ticsKernel<<<minGridSize,block_size>>>(devStates,a_d,Ev,bstep);
cudaDeviceSynchronize();
cudaMemcpy(a_h,a_d, sizeof(int)*n_procs,cudaMemcpyDeviceToHost);
for(int i=0;i<minGridSize;i++)
{
for(int j=0;j<block_size;j++)
{
int idx=i*block_size+j;
ibr[idx] = ibr[idx]+a_h[idx];
}
}
}
// compute the cross section
float tics=0.;
for(int i=0;i<minGridSize;i++)
{
for(int j=0;j<block_size;j++)
{
int idx=i*block_size+j;
float bimpact=bstep*(float)idx;
//printf("b,ibr:%f \t %i\n",bimpact,ibr[idx]);
if(ibr[idx]<=5)
ibr[idx]=0;
tics=tics+2.*pi*bstep*bimpact*(float)ibr[idx]/float(ntrjs);
}
}
//now free-up the space
free(a_h);
cudaFree(a_d);
return tics;
}
int main()
{
fstream pstics;
pstics.open("ticscu.txt",ios::out);
auto start = high_resolution_clock::now();
// initial hydrogen n,l states
int nps=3,lps=0;
//Threshold energy for ionization (a.u)
float eth=.5/powf((float)nps,2);
//initial electron energy
float Ev;
for(int i=0;i<50;i++)
{
Ev=eth*27.21+(float)i*2.;
float tics=cudaticsPs(Ev);
printf("Break-up cross section at %f eV is: %f \n ",Ev,tics);
pstics<<Ev<<"\t"<<tics<<endl;
}
auto stop = high_resolution_clock::now();
auto duration = duration_cast<seconds>(stop - start);
cout<<"Duration (s)"<<"\t"<<duration.count()<<endl;
} | //Author: Harindranath Ambalampitiya, PhD(Theoretical atomic and molecular physics)
//GPU accelerated Classical Trajectory Monte Carlo Methods
//electron-collision with hydrogen
#include <hip/hip_runtime.h>
#include <iostream>
#include<fstream>
#include<math.h>
#include<stdio.h>
#include<ctime>
#include<cstdlib>
#include <chrono>
#include<hiprand/hiprand_kernel.h>
using namespace std;
using namespace std::chrono;
// initialize random_number generator on the device
//each thread gets the same seed,but different sequence
__global__ void rng_init(hiprandState *state,int seed,int n)
{
int id=blockIdx.x*blockDim.x+threadIdx.x;
if(id<n)
{
hiprand_init(seed, id, 0, &state[id]);
}
}
//root-search(bisection method) on the device
__device__ float rootxi(float alpha,float ecc,float x1,float x2)
{
int jmax=50;
float xacc=1e-4f;//accuracy
float dx,xmid,rtb;
float f=x1-ecc*sin(x1)-alpha;
float fmid=x2-ecc*sin(x2)-alpha;
rtb = f < 0.0 ? (dx=x2-x1,x1) : (dx=x1-x2,x2);
for (int j=0;j<jmax;j++)
{
xmid=rtb+(dx *= 0.5);
fmid=xmid-ecc*sin(xmid)-alpha;
if (fmid <= 0.0)
rtb=xmid;
if (abs(dx) < xacc || fmid == 0.0)
return rtb;
}
return 0;
}
// derivatives for Runge-Kutta stepper
__device__ void derivs(float t, float *y, float *dydt)
{
float R1=sqrt(y[0]*y[0]+y[2]*y[2]+y[4]*y[4]+.2);
float R2=sqrt(y[6]*y[6]+y[8]*y[8]+y[10]*y[10]+.2);
float dx=y[0]-y[6];
float dy=y[2]-y[8];
float dz=y[4]-y[10];
float R3=sqrt(dx*dx+dy*dy+dz*dz+.2);
dydt[0]=y[1];
dydt[1]=-y[0]/powf(R1,3)+dx/powf(R3,3);
dydt[2]=y[3];
dydt[3]=-y[2]/powf(R1,3)+dy/powf(R3,3);
dydt[4]=y[5];
dydt[5]=-y[4]/powf(R1,3)+dz/powf(R3,3);
dydt[6]=y[7];
dydt[7]=-y[6]/powf(R2,3)-dx/powf(R3,3);
dydt[8]=y[9];
dydt[9]=-y[8]/powf(R2,3)-dy/powf(R3,3);
dydt[10]=y[11];
dydt[11]=-y[10]/powf(R2,3)-dz/powf(R3,3);
}
//Let's calculate tics on the device
__global__ void ticsKernel(hiprandState *state,int *a,float Ev,float bstep)
{
int nps=3,lps=0;
// eliptical orbit parameters
//semi-major axis,period/2pi,Ps energy
float asem=powf((float)nps,2.),tred=sqrtf(powf(asem,3.));
float ehyd=-0.5/asem;
float pi=2.*asinf(1.0f);
//total energy,maximum-time iteration
float energy=ehyd+Ev/27.21,tmax=500.;
//initial velocity and z coordinates
float vinit=sqrtf(Ev/27.21),zinit=-25.;
//asymptotic z
float zasym=25.;
//impact parameter that each thread gets
int idx=blockIdx.x*blockDim.x+threadIdx.x;
float bimpact=bstep*(float)idx;
a[idx]=0;
//printf("blockid,threadid:%i\t%i\t%f \n",blockIdx.x,
//threadIdx.x,bimpact);
//copy state to local memory
hiprandState localState = state[idx];
// run ntrjs amount of classical trajectories
//initialize the breakup events
int ibr=0;
//first initialize the electron/positron
float y[12],dydt[12];
y[0]=bimpact;
y[1]=0.;
y[2]=0.;
y[3]=0.;
y[4]=zinit;
y[5]=vinit;
for(int i=0;i<1;i++)
{
//generate 5 random numbers in the uniform grid (0,1]
//For micro canonical ensemble
//printf("idx,i %i \t %i \n",idx,i);
float ran0 = hiprand_uniform(&localState);
float ran1 = hiprand_uniform(&localState);
float ran2 = hiprand_uniform(&localState);
float ran3 = hiprand_uniform(&localState);
float ran4 = hiprand_uniform(&localState);
float beta=ran0;
float alpha=ran1*2.*pi;
float psi=ran2*2.*pi;
float cothe=2.*ran3-1.;
float phi=ran4*2.*pi;
//eccentricity of the orbit
float ecc=sqrtf(1.-beta);
//root-search for eccentric anomaly
float xip=rootxi(alpha,ecc,0.0f,2.*pi);
float sixi=sinf(xip),coxi=cosf(xip);
//initial unrotated coordinates and velocities
float xr[3],vr[3];
float den=tred*(1.0f-ecc*coxi);
xr[0]=asem*sqrtf(beta)*sixi;
xr[1]=0.0f;
xr[2]=asem*(coxi-ecc);
vr[0]=asem*sqrtf(beta)*coxi/den;
vr[1]=0.;
vr[2]=-asem*sixi/den;
// check the energy
float ekin0=.5*(vr[0]*vr[0]+vr[1]*vr[1]+vr[2]*vr[2]);
float erel=ekin0-1.0f/sqrtf(xr[0]*xr[0]+xr[1]*xr[1]+xr[2]*xr[2]);
//printf("ehyd,erel: %f \t %f \n", ehyd,erel);
//prepare Euler matrix
float eul[3][3];
float co1=cos(psi),si1=sin(psi),co3=cos(phi),si3=sin(phi);
float sithe=sqrt(1.-cothe*cothe);
eul[0][0]=co1*co3-si1*cothe*si3;
eul[0][1]=-co1*si3-si1*cothe*co3;
eul[0][2]=si1*sithe;
eul[1][0]=si1*co3+co1*cothe*si3;
eul[1][1]=-si1*si3+co1*cothe*co3;
eul[1][2]=-co1*sithe;
eul[2][0]=sithe*si3;
eul[2][1]=sithe*co3;
eul[2][2]=cothe;
//rotate relative coordinates and velocities
float va[3],xa[3];
for(int ii=0;ii<3;ii++)
{
va[ii]=0.;
xa[ii]=0.;
for(int jj=0;jj<3;jj++)
{
va[ii]=va[ii]+eul[ii][jj]*vr[jj];
xa[ii]=xa[ii]+eul[ii][jj]*xr[jj];
}
//transform to the lab-frame
xa[ii]=xa[ii];
va[ii]=va[ii];
}
//initialize the electron-positron
y[6]=xa[0];
y[7]=va[0];
y[8]=xa[1];
y[9]=va[1];
y[10]=xa[2];
y[11]=va[2];
// check the initial energy
float R1=sqrt(y[0]*y[0]+y[2]*y[2]+y[4]*y[4]+.2);
float R2=sqrt(y[6]*y[6]+y[8]*y[8]+y[10]*y[10]+.2);
float dx=y[0]-y[6];
float dy=y[2]-y[8];
float dz=y[4]-y[10];
float R3=sqrt(dx*dx+dy*dy+dz*dz+.2);
float ekin=.5*(y[1]*y[1]+y[3]*y[3]+y[5]*y[5]);
float pkin=.5*(y[7]*y[7]+y[9]*y[9]+y[11]*y[11]);
float en0=ekin+pkin-1./R1-1./R2+1./R3;
derivs(0.,y,dydt);
float run_time=0.;
float tstep=1.;
int iter=tmax/tstep;
//Runge-Kutta Stepper
float dym[12],dyt[12],yt[12],yout[12];
float h=tstep,hh=h/2.,h6=h/6.;
for(int it=0;it<iter;it++)
{
//propagate y,dydt a tstep
//------------------------------------------------//
for(int ij=0;ij<12;ij++)yt[ij]=y[ij]+hh*dydt[ij];
derivs(run_time+hh,yt,dyt);
for(int ik=0;ik<12;ik++)yt[ik]=y[ik]+hh*dyt[ik];
derivs(run_time+hh,yt,dym);
for (int il=0;il<12;il++)
{
yt[il]=y[il]+h*dym[il];
dym[il] += dyt[il];
}
derivs(run_time+h,yt,dyt);
for (int ir=0;ir<12;ir++)
{
yout[ir]=y[ir]+h6*(dydt[ir]+dyt[ir]+2.0*dym[ir]);
}
//-----------------------------------------------//
//re-initialize the stepper
for(int iw=0;iw<12;iw++)y[iw]=yout[iw];
derivs(run_time+h,y,dydt);
//printf("%f\t%f\t%f\t%f\t%f\t%f\n",y[0],y[2],y[4],y[6],y[8],
//y[10]);
if(y[10]>=zasym)
break;
run_time=run_time+h;
}
//check the final energy
R1=sqrt(y[0]*y[0]+y[2]*y[2]+y[4]*y[4]+.2);
R2=sqrt(y[6]*y[6]+y[8]*y[8]+y[10]*y[10]+.2);
dx=y[0]-y[6];
dy=y[2]-y[8];
dz=y[4]-y[10];
R3=sqrt(dx*dx+dy*dy+dz*dz+.2);
ekin=.5*(y[1]*y[1]+y[3]*y[3]+y[5]*y[5]);
pkin=.5*(y[7]*y[7]+y[9]*y[9]+y[11]*y[11]);
float enf0=ekin+pkin-1./R1-1./R2+1./R3;
//check the relative energy between incomping elecron and proton/antiproton
float en1=ekin-1./R1;
float en2=pkin-1./R2;
if(en1>=0.0f && en2>=0.0f)
ibr=ibr+1;
//printf("bimpact,en1,en2,ibr: %f \t %f \t %f \t %i \n",
//bimpact,en1,en2,ibr);
}
//copy local memory to global
state[idx] = localState;
a[idx]=ibr;
//printf("here \n");
//printf("inside: %i \n",ibr);
}
float cudaticsPs(float Ev)
{
float pi=2.*asinf(1.0f);
// number of threads and blocks
// number of threads:range of impact parameters
//number of blocks: shares the total number of classical trajectories required
//int block_size,minGridSize;
//predefined number of trajectories for each block
int ntrjs=5000;
int block_size,minGridSize;
//cudaOccupancyMaxPotentialBlockSize(&minGridSize, &block_size, ticsKernel, 0, ntrjs);
//printf("block size, gridsize %i \t %i \n",block_size, minGridSize);
block_size=32;
minGridSize=1;
int n_procs=minGridSize*block_size;
//memory allocation in the host and device
size_t size=n_procs *sizeof(int);
int* a_h=(int*)malloc(size);
int* a_d;
hipMalloc((void **) &a_d, size);
//random_states
hiprandState *devStates;
hipMalloc((void **) &devStates, n_procs *sizeof(hiprandState));
int* ibr=(int*)malloc(size);
for(int i=0;i<n_procs;i++)ibr[i]=0;
// each thread gets a single impact parameters
float bmax=18.;
float bstep=bmax/(float)n_procs;
//initialize the random numbers
int s=12345;//seed
rng_init<<<minGridSize,block_size>>>(devStates, s, n_procs);
//pass it to parallel processing
//each parallel unit counts the number of break-up events
//run the kernel in a loop
for(int iker=0;iker<ntrjs;iker++)
{
ticsKernel<<<minGridSize,block_size>>>(devStates,a_d,Ev,bstep);
hipDeviceSynchronize();
hipMemcpy(a_h,a_d, sizeof(int)*n_procs,hipMemcpyDeviceToHost);
for(int i=0;i<minGridSize;i++)
{
for(int j=0;j<block_size;j++)
{
int idx=i*block_size+j;
ibr[idx] = ibr[idx]+a_h[idx];
}
}
}
// compute the cross section
float tics=0.;
for(int i=0;i<minGridSize;i++)
{
for(int j=0;j<block_size;j++)
{
int idx=i*block_size+j;
float bimpact=bstep*(float)idx;
//printf("b,ibr:%f \t %i\n",bimpact,ibr[idx]);
if(ibr[idx]<=5)
ibr[idx]=0;
tics=tics+2.*pi*bstep*bimpact*(float)ibr[idx]/float(ntrjs);
}
}
//now free-up the space
free(a_h);
hipFree(a_d);
return tics;
}
int main()
{
fstream pstics;
pstics.open("ticscu.txt",ios::out);
auto start = high_resolution_clock::now();
// initial hydrogen n,l states
int nps=3,lps=0;
//Threshold energy for ionization (a.u)
float eth=.5/powf((float)nps,2);
//initial electron energy
float Ev;
for(int i=0;i<50;i++)
{
Ev=eth*27.21+(float)i*2.;
float tics=cudaticsPs(Ev);
printf("Break-up cross section at %f eV is: %f \n ",Ev,tics);
pstics<<Ev<<"\t"<<tics<<endl;
}
auto stop = high_resolution_clock::now();
auto duration = duration_cast<seconds>(stop - start);
cout<<"Duration (s)"<<"\t"<<duration.count()<<endl;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //Author: Harindranath Ambalampitiya, PhD(Theoretical atomic and molecular physics)
//GPU accelerated Classical Trajectory Monte Carlo Methods
//electron-collision with hydrogen
#include <hip/hip_runtime.h>
#include <iostream>
#include<fstream>
#include<math.h>
#include<stdio.h>
#include<ctime>
#include<cstdlib>
#include <chrono>
#include<hiprand/hiprand_kernel.h>
using namespace std;
using namespace std::chrono;
// initialize random_number generator on the device
//each thread gets the same seed,but different sequence
__global__ void rng_init(hiprandState *state,int seed,int n)
{
int id=blockIdx.x*blockDim.x+threadIdx.x;
if(id<n)
{
hiprand_init(seed, id, 0, &state[id]);
}
}
//root-search(bisection method) on the device
__device__ float rootxi(float alpha,float ecc,float x1,float x2)
{
int jmax=50;
float xacc=1e-4f;//accuracy
float dx,xmid,rtb;
float f=x1-ecc*sin(x1)-alpha;
float fmid=x2-ecc*sin(x2)-alpha;
rtb = f < 0.0 ? (dx=x2-x1,x1) : (dx=x1-x2,x2);
for (int j=0;j<jmax;j++)
{
xmid=rtb+(dx *= 0.5);
fmid=xmid-ecc*sin(xmid)-alpha;
if (fmid <= 0.0)
rtb=xmid;
if (abs(dx) < xacc || fmid == 0.0)
return rtb;
}
return 0;
}
// derivatives for Runge-Kutta stepper
__device__ void derivs(float t, float *y, float *dydt)
{
float R1=sqrt(y[0]*y[0]+y[2]*y[2]+y[4]*y[4]+.2);
float R2=sqrt(y[6]*y[6]+y[8]*y[8]+y[10]*y[10]+.2);
float dx=y[0]-y[6];
float dy=y[2]-y[8];
float dz=y[4]-y[10];
float R3=sqrt(dx*dx+dy*dy+dz*dz+.2);
dydt[0]=y[1];
dydt[1]=-y[0]/powf(R1,3)+dx/powf(R3,3);
dydt[2]=y[3];
dydt[3]=-y[2]/powf(R1,3)+dy/powf(R3,3);
dydt[4]=y[5];
dydt[5]=-y[4]/powf(R1,3)+dz/powf(R3,3);
dydt[6]=y[7];
dydt[7]=-y[6]/powf(R2,3)-dx/powf(R3,3);
dydt[8]=y[9];
dydt[9]=-y[8]/powf(R2,3)-dy/powf(R3,3);
dydt[10]=y[11];
dydt[11]=-y[10]/powf(R2,3)-dz/powf(R3,3);
}
//Let's calculate tics on the device
__global__ void ticsKernel(hiprandState *state,int *a,float Ev,float bstep)
{
int nps=3,lps=0;
// eliptical orbit parameters
//semi-major axis,period/2pi,Ps energy
float asem=powf((float)nps,2.),tred=sqrtf(powf(asem,3.));
float ehyd=-0.5/asem;
float pi=2.*asinf(1.0f);
//total energy,maximum-time iteration
float energy=ehyd+Ev/27.21,tmax=500.;
//initial velocity and z coordinates
float vinit=sqrtf(Ev/27.21),zinit=-25.;
//asymptotic z
float zasym=25.;
//impact parameter that each thread gets
int idx=blockIdx.x*blockDim.x+threadIdx.x;
float bimpact=bstep*(float)idx;
a[idx]=0;
//printf("blockid,threadid:%i\t%i\t%f \n",blockIdx.x,
//threadIdx.x,bimpact);
//copy state to local memory
hiprandState localState = state[idx];
// run ntrjs amount of classical trajectories
//initialize the breakup events
int ibr=0;
//first initialize the electron/positron
float y[12],dydt[12];
y[0]=bimpact;
y[1]=0.;
y[2]=0.;
y[3]=0.;
y[4]=zinit;
y[5]=vinit;
for(int i=0;i<1;i++)
{
//generate 5 random numbers in the uniform grid (0,1]
//For micro canonical ensemble
//printf("idx,i %i \t %i \n",idx,i);
float ran0 = hiprand_uniform(&localState);
float ran1 = hiprand_uniform(&localState);
float ran2 = hiprand_uniform(&localState);
float ran3 = hiprand_uniform(&localState);
float ran4 = hiprand_uniform(&localState);
float beta=ran0;
float alpha=ran1*2.*pi;
float psi=ran2*2.*pi;
float cothe=2.*ran3-1.;
float phi=ran4*2.*pi;
//eccentricity of the orbit
float ecc=sqrtf(1.-beta);
//root-search for eccentric anomaly
float xip=rootxi(alpha,ecc,0.0f,2.*pi);
float sixi=sinf(xip),coxi=cosf(xip);
//initial unrotated coordinates and velocities
float xr[3],vr[3];
float den=tred*(1.0f-ecc*coxi);
xr[0]=asem*sqrtf(beta)*sixi;
xr[1]=0.0f;
xr[2]=asem*(coxi-ecc);
vr[0]=asem*sqrtf(beta)*coxi/den;
vr[1]=0.;
vr[2]=-asem*sixi/den;
// check the energy
float ekin0=.5*(vr[0]*vr[0]+vr[1]*vr[1]+vr[2]*vr[2]);
float erel=ekin0-1.0f/sqrtf(xr[0]*xr[0]+xr[1]*xr[1]+xr[2]*xr[2]);
//printf("ehyd,erel: %f \t %f \n", ehyd,erel);
//prepare Euler matrix
float eul[3][3];
float co1=cos(psi),si1=sin(psi),co3=cos(phi),si3=sin(phi);
float sithe=sqrt(1.-cothe*cothe);
eul[0][0]=co1*co3-si1*cothe*si3;
eul[0][1]=-co1*si3-si1*cothe*co3;
eul[0][2]=si1*sithe;
eul[1][0]=si1*co3+co1*cothe*si3;
eul[1][1]=-si1*si3+co1*cothe*co3;
eul[1][2]=-co1*sithe;
eul[2][0]=sithe*si3;
eul[2][1]=sithe*co3;
eul[2][2]=cothe;
//rotate relative coordinates and velocities
float va[3],xa[3];
for(int ii=0;ii<3;ii++)
{
va[ii]=0.;
xa[ii]=0.;
for(int jj=0;jj<3;jj++)
{
va[ii]=va[ii]+eul[ii][jj]*vr[jj];
xa[ii]=xa[ii]+eul[ii][jj]*xr[jj];
}
//transform to the lab-frame
xa[ii]=xa[ii];
va[ii]=va[ii];
}
//initialize the electron-positron
y[6]=xa[0];
y[7]=va[0];
y[8]=xa[1];
y[9]=va[1];
y[10]=xa[2];
y[11]=va[2];
// check the initial energy
float R1=sqrt(y[0]*y[0]+y[2]*y[2]+y[4]*y[4]+.2);
float R2=sqrt(y[6]*y[6]+y[8]*y[8]+y[10]*y[10]+.2);
float dx=y[0]-y[6];
float dy=y[2]-y[8];
float dz=y[4]-y[10];
float R3=sqrt(dx*dx+dy*dy+dz*dz+.2);
float ekin=.5*(y[1]*y[1]+y[3]*y[3]+y[5]*y[5]);
float pkin=.5*(y[7]*y[7]+y[9]*y[9]+y[11]*y[11]);
float en0=ekin+pkin-1./R1-1./R2+1./R3;
derivs(0.,y,dydt);
float run_time=0.;
float tstep=1.;
int iter=tmax/tstep;
//Runge-Kutta Stepper
float dym[12],dyt[12],yt[12],yout[12];
float h=tstep,hh=h/2.,h6=h/6.;
for(int it=0;it<iter;it++)
{
//propagate y,dydt a tstep
//------------------------------------------------//
for(int ij=0;ij<12;ij++)yt[ij]=y[ij]+hh*dydt[ij];
derivs(run_time+hh,yt,dyt);
for(int ik=0;ik<12;ik++)yt[ik]=y[ik]+hh*dyt[ik];
derivs(run_time+hh,yt,dym);
for (int il=0;il<12;il++)
{
yt[il]=y[il]+h*dym[il];
dym[il] += dyt[il];
}
derivs(run_time+h,yt,dyt);
for (int ir=0;ir<12;ir++)
{
yout[ir]=y[ir]+h6*(dydt[ir]+dyt[ir]+2.0*dym[ir]);
}
//-----------------------------------------------//
//re-initialize the stepper
for(int iw=0;iw<12;iw++)y[iw]=yout[iw];
derivs(run_time+h,y,dydt);
//printf("%f\t%f\t%f\t%f\t%f\t%f\n",y[0],y[2],y[4],y[6],y[8],
//y[10]);
if(y[10]>=zasym)
break;
run_time=run_time+h;
}
//check the final energy
R1=sqrt(y[0]*y[0]+y[2]*y[2]+y[4]*y[4]+.2);
R2=sqrt(y[6]*y[6]+y[8]*y[8]+y[10]*y[10]+.2);
dx=y[0]-y[6];
dy=y[2]-y[8];
dz=y[4]-y[10];
R3=sqrt(dx*dx+dy*dy+dz*dz+.2);
ekin=.5*(y[1]*y[1]+y[3]*y[3]+y[5]*y[5]);
pkin=.5*(y[7]*y[7]+y[9]*y[9]+y[11]*y[11]);
float enf0=ekin+pkin-1./R1-1./R2+1./R3;
//check the relative energy between incomping elecron and proton/antiproton
float en1=ekin-1./R1;
float en2=pkin-1./R2;
if(en1>=0.0f && en2>=0.0f)
ibr=ibr+1;
//printf("bimpact,en1,en2,ibr: %f \t %f \t %f \t %i \n",
//bimpact,en1,en2,ibr);
}
//copy local memory to global
state[idx] = localState;
a[idx]=ibr;
//printf("here \n");
//printf("inside: %i \n",ibr);
}
float cudaticsPs(float Ev)
{
float pi=2.*asinf(1.0f);
// number of threads and blocks
// number of threads:range of impact parameters
//number of blocks: shares the total number of classical trajectories required
//int block_size,minGridSize;
//predefined number of trajectories for each block
int ntrjs=5000;
int block_size,minGridSize;
//cudaOccupancyMaxPotentialBlockSize(&minGridSize, &block_size, ticsKernel, 0, ntrjs);
//printf("block size, gridsize %i \t %i \n",block_size, minGridSize);
block_size=32;
minGridSize=1;
int n_procs=minGridSize*block_size;
//memory allocation in the host and device
size_t size=n_procs *sizeof(int);
int* a_h=(int*)malloc(size);
int* a_d;
hipMalloc((void **) &a_d, size);
//random_states
hiprandState *devStates;
hipMalloc((void **) &devStates, n_procs *sizeof(hiprandState));
int* ibr=(int*)malloc(size);
for(int i=0;i<n_procs;i++)ibr[i]=0;
// each thread gets a single impact parameters
float bmax=18.;
float bstep=bmax/(float)n_procs;
//initialize the random numbers
int s=12345;//seed
rng_init<<<minGridSize,block_size>>>(devStates, s, n_procs);
//pass it to parallel processing
//each parallel unit counts the number of break-up events
//run the kernel in a loop
for(int iker=0;iker<ntrjs;iker++)
{
ticsKernel<<<minGridSize,block_size>>>(devStates,a_d,Ev,bstep);
hipDeviceSynchronize();
hipMemcpy(a_h,a_d, sizeof(int)*n_procs,hipMemcpyDeviceToHost);
for(int i=0;i<minGridSize;i++)
{
for(int j=0;j<block_size;j++)
{
int idx=i*block_size+j;
ibr[idx] = ibr[idx]+a_h[idx];
}
}
}
// compute the cross section
float tics=0.;
for(int i=0;i<minGridSize;i++)
{
for(int j=0;j<block_size;j++)
{
int idx=i*block_size+j;
float bimpact=bstep*(float)idx;
//printf("b,ibr:%f \t %i\n",bimpact,ibr[idx]);
if(ibr[idx]<=5)
ibr[idx]=0;
tics=tics+2.*pi*bstep*bimpact*(float)ibr[idx]/float(ntrjs);
}
}
//now free-up the space
free(a_h);
hipFree(a_d);
return tics;
}
int main()
{
fstream pstics;
pstics.open("ticscu.txt",ios::out);
auto start = high_resolution_clock::now();
// initial hydrogen n,l states
int nps=3,lps=0;
//Threshold energy for ionization (a.u)
float eth=.5/powf((float)nps,2);
//initial electron energy
float Ev;
for(int i=0;i<50;i++)
{
Ev=eth*27.21+(float)i*2.;
float tics=cudaticsPs(Ev);
printf("Break-up cross section at %f eV is: %f \n ",Ev,tics);
pstics<<Ev<<"\t"<<tics<<endl;
}
auto stop = high_resolution_clock::now();
auto duration = duration_cast<seconds>(stop - start);
cout<<"Duration (s)"<<"\t"<<duration.count()<<endl;
} | .text
.file "ehyd2.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z23__device_stub__rng_initP12hiprandStateii # -- Begin function _Z23__device_stub__rng_initP12hiprandStateii
.p2align 4, 0x90
.type _Z23__device_stub__rng_initP12hiprandStateii,@function
_Z23__device_stub__rng_initP12hiprandStateii: # @_Z23__device_stub__rng_initP12hiprandStateii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8rng_initP12hiprandStateii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z23__device_stub__rng_initP12hiprandStateii, .Lfunc_end0-_Z23__device_stub__rng_initP12hiprandStateii
.cfi_endproc
# -- End function
.globl _Z25__device_stub__ticsKernelP12hiprandStatePiff # -- Begin function _Z25__device_stub__ticsKernelP12hiprandStatePiff
.p2align 4, 0x90
.type _Z25__device_stub__ticsKernelP12hiprandStatePiff,@function
_Z25__device_stub__ticsKernelP12hiprandStatePiff: # @_Z25__device_stub__ticsKernelP12hiprandStatePiff
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10ticsKernelP12hiprandStatePiff, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z25__device_stub__ticsKernelP12hiprandStatePiff, .Lfunc_end1-_Z25__device_stub__ticsKernelP12hiprandStatePiff
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z10cudaticsPsf
.LCPI2_0:
.long 0x3f100000 # float 0.5625
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_1:
.quad 0x400c463acc000000 # double 3.5342918336391449
.LCPI2_2:
.quad 0x40b3880000000000 # double 5000
.text
.globl _Z10cudaticsPsf
.p2align 4, 0x90
.type _Z10cudaticsPsf,@function
_Z10cudaticsPsf: # @_Z10cudaticsPsf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movss %xmm0, (%rsp) # 4-byte Spill
movabsq $4294967297, %r15 # imm = 0x100000001
movl $128, %edi
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $128, %esi
callq hipMalloc
leaq 88(%rsp), %rdi
movl $1536, %esi # imm = 0x600
callq hipMalloc
movl $128, %edi
callq malloc
movq %rax, %r14
xorps %xmm0, %xmm0
movups %xmm0, (%rax)
movups %xmm0, 16(%rax)
movups %xmm0, 32(%rax)
movups %xmm0, 48(%rax)
movups %xmm0, 64(%rax)
movups %xmm0, 80(%rax)
movups %xmm0, 96(%rax)
movups %xmm0, 112(%rax)
leaq 31(%r15), %r12
xorl %ebp, %ebp
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 88(%rsp), %rax
movq %rax, 72(%rsp)
movl $12345, 16(%rsp) # imm = 0x3039
movl $32, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8rng_initP12hiprandStateii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
leaq 96(%rsp), %r13
.p2align 4, 0x90
.LBB2_3: # =>This Loop Header: Depth=1
# Child Loop BB2_6 Depth 2
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4: # in Loop: Header=BB2_3 Depth=1
movq 88(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movss (%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 4(%rsp)
movl $1058013184, 84(%rsp) # imm = 0x3F100000
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 84(%rsp), %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z10ticsKernelP12hiprandStatePiff, %edi
movq %r13, %r9
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_5: # %.critedge
# in Loop: Header=BB2_3 Depth=1
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movl $128, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_6: # Parent Loop BB2_3 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%rax,4), %ecx
addl %ecx, (%r14,%rax,4)
incq %rax
cmpq $32, %rax
jne .LBB2_6
# %bb.7: # in Loop: Header=BB2_3 Depth=1
incl %ebp
cmpl $5000, %ebp # imm = 0x1388
jne .LBB2_3
# %bb.8: # %.preheader.preheader
xorps %xmm4, %xmm4
xorl %eax, %eax
movss .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movsd .LCPI2_1(%rip), %xmm1 # xmm1 = mem[0],zero
movsd .LCPI2_2(%rip), %xmm2 # xmm2 = mem[0],zero
jmp .LBB2_9
.p2align 4, 0x90
.LBB2_11: # in Loop: Header=BB2_9 Depth=1
cvtss2sd %xmm4, %xmm4
cvtss2sd %xmm3, %xmm3
mulsd %xmm1, %xmm3
xorps %xmm5, %xmm5
cvtsi2ssl (%r14,%rax,4), %xmm5
cvtss2sd %xmm5, %xmm5
mulsd %xmm3, %xmm5
divsd %xmm2, %xmm5
addsd %xmm4, %xmm5
xorps %xmm4, %xmm4
cvtsd2ss %xmm5, %xmm4
incq %rax
cmpq $32, %rax
je .LBB2_12
.LBB2_9: # %.preheader
# =>This Inner Loop Header: Depth=1
xorps %xmm3, %xmm3
cvtsi2ss %eax, %xmm3
mulss %xmm0, %xmm3
cmpl $5, (%r14,%rax,4)
jg .LBB2_11
# %bb.10: # in Loop: Header=BB2_9 Depth=1
movl $0, (%r14,%rax,4)
jmp .LBB2_11
.LBB2_12: # %.loopexit
movq %rbx, %rdi
movss %xmm4, (%rsp) # 4-byte Spill
callq free
movq 8(%rsp), %rdi
callq hipFree
movss (%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z10cudaticsPsf, .Lfunc_end2-_Z10cudaticsPsf
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x3ff82fc966028f5c # double 1.511666677929461
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $544, %rsp # imm = 0x220
.cfi_def_cfa_offset 592
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 16(%rsp), %rbx
movq %rbx, %rdi
callq _ZNSt13basic_fstreamIcSt11char_traitsIcEEC1Ev
leaq 40(%rsp), %rdi
.Ltmp0:
movl $.L.str, %esi
movl $16, %edx
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp1:
# %bb.1: # %.noexc
movq 16(%rsp), %rcx
addq -24(%rcx), %rbx
xorl %esi, %esi
testq %rax, %rax
jne .LBB3_3
# %bb.2:
movl 32(%rbx), %esi
orl $4, %esi
.LBB3_3: # %.invoke
.Ltmp2:
movq %rbx, %rdi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp3:
# %bb.4: # %_ZNSt13basic_fstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %rbx
xorl %ebp, %ebp
leaq 32(%rsp), %r14
.p2align 4, 0x90
.LBB3_5: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %ebp, %xmm0
addsd %xmm0, %xmm0
addsd .LCPI3_0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
.Ltmp5:
movss %xmm0, (%rsp) # 4-byte Spill
callq _Z10cudaticsPsf
.Ltmp6:
# %bb.6: # in Loop: Header=BB3_5 Depth=1
movss (%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
xorps %xmm2, %xmm2
cvtss2sd %xmm1, %xmm2
movsd %xmm2, (%rsp) # 8-byte Spill
xorps %xmm1, %xmm1
cvtss2sd %xmm0, %xmm1
movl $.L.str.1, %edi
movaps %xmm2, %xmm0
movsd %xmm1, 8(%rsp) # 8-byte Spill
movb $2, %al
callq printf
.Ltmp7:
movq %r14, %rdi
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp8:
# %bb.7: # %_ZNSolsEf.exit
# in Loop: Header=BB3_5 Depth=1
.Ltmp9:
movq %rax, %r15
movl $.L.str.2, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp10:
# %bb.8: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
# in Loop: Header=BB3_5 Depth=1
.Ltmp11:
movq %r15, %rdi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp12:
# %bb.9: # %_ZNSolsEf.exit25
# in Loop: Header=BB3_5 Depth=1
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB3_10
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB3_5 Depth=1
cmpb $0, 56(%r12)
je .LBB3_14
# %bb.13: # in Loop: Header=BB3_5 Depth=1
movzbl 67(%r12), %eax
jmp .LBB3_16
.p2align 4, 0x90
.LBB3_14: # in Loop: Header=BB3_5 Depth=1
.Ltmp13:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp14:
# %bb.15: # %.noexc35
# in Loop: Header=BB3_5 Depth=1
movq (%r12), %rax
.Ltmp15:
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp16:
.LBB3_16: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
# in Loop: Header=BB3_5 Depth=1
.Ltmp17:
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
.Ltmp18:
# %bb.17: # %.noexc37
# in Loop: Header=BB3_5 Depth=1
.Ltmp19:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp20:
# %bb.18: # %_ZNSolsEPFRSoS_E.exit
# in Loop: Header=BB3_5 Depth=1
incl %ebp
cmpl $50, %ebp
jne .LBB3_5
# %bb.19:
callq _ZNSt6chrono3_V212system_clock3nowEv
subq %rbx, %rax
movabsq $1237940039285380275, %rcx # imm = 0x112E0BE826D694B3
imulq %rcx
movq %rdx, %rbx
.Ltmp22:
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp23:
# %bb.20: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit28
.Ltmp24:
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp25:
# %bb.21: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit30
.Ltmp26:
movq %rbx, %rax
shrq $63, %rax
sarq $26, %rbx
addq %rax, %rbx
movl $_ZSt4cout, %edi
movq %rbx, %rsi
callq _ZNSo9_M_insertIlEERSoT_
.Ltmp27:
# %bb.22: # %_ZNSolsEl.exit
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB3_23
# %bb.27: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i40
cmpb $0, 56(%r14)
je .LBB3_29
# %bb.28:
movzbl 67(%r14), %eax
jmp .LBB3_31
.LBB3_29:
.Ltmp28:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp29:
# %bb.30: # %.noexc45
movq (%r14), %rax
.Ltmp30:
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp31:
.LBB3_31: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i42
.Ltmp32:
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp33:
# %bb.32: # %.noexc47
.Ltmp34:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp35:
# %bb.33: # %_ZNSolsEPFRSoS_E.exit33
leaq 16(%rsp), %rdi
movl $_ZTTSt13basic_fstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt13basic_fstreamIcSt11char_traitsIcEED2Ev
leaq 280(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
xorl %eax, %eax
addq $544, %rsp # imm = 0x220
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_10:
.cfi_def_cfa_offset 592
.Ltmp39:
callq _ZSt16__throw_bad_castv
.Ltmp40:
# %bb.11: # %.noexc34
.LBB3_23:
.Ltmp36:
callq _ZSt16__throw_bad_castv
.Ltmp37:
# %bb.26: # %.noexc44
.LBB3_36:
.Ltmp4:
jmp .LBB3_35
.LBB3_34:
.Ltmp38:
jmp .LBB3_35
.LBB3_25: # %.loopexit.split-lp
.Ltmp41:
jmp .LBB3_35
.LBB3_24: # %.loopexit
.Ltmp21:
.LBB3_35:
movq %rax, %rbx
leaq 16(%rsp), %rdi
movl $_ZTTSt13basic_fstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt13basic_fstreamIcSt11char_traitsIcEED2Ev
leaq 280(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table3:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp3-.Ltmp0 # Call between .Ltmp0 and .Ltmp3
.uleb128 .Ltmp4-.Lfunc_begin0 # jumps to .Ltmp4
.byte 0 # On action: cleanup
.uleb128 .Ltmp5-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp20-.Ltmp5 # Call between .Ltmp5 and .Ltmp20
.uleb128 .Ltmp21-.Lfunc_begin0 # jumps to .Ltmp21
.byte 0 # On action: cleanup
.uleb128 .Ltmp22-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp35-.Ltmp22 # Call between .Ltmp22 and .Ltmp35
.uleb128 .Ltmp38-.Lfunc_begin0 # jumps to .Ltmp38
.byte 0 # On action: cleanup
.uleb128 .Ltmp39-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp40-.Ltmp39 # Call between .Ltmp39 and .Ltmp40
.uleb128 .Ltmp41-.Lfunc_begin0 # jumps to .Ltmp41
.byte 0 # On action: cleanup
.uleb128 .Ltmp36-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp37-.Ltmp36 # Call between .Ltmp36 and .Ltmp37
.uleb128 .Ltmp38-.Lfunc_begin0 # jumps to .Ltmp38
.byte 0 # On action: cleanup
.uleb128 .Ltmp37-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Lfunc_end3-.Ltmp37 # Call between .Ltmp37 and .Lfunc_end3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8rng_initP12hiprandStateii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10ticsKernelP12hiprandStatePiff, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8rng_initP12hiprandStateii,@object # @_Z8rng_initP12hiprandStateii
.section .rodata,"a",@progbits
.globl _Z8rng_initP12hiprandStateii
.p2align 3, 0x0
_Z8rng_initP12hiprandStateii:
.quad _Z23__device_stub__rng_initP12hiprandStateii
.size _Z8rng_initP12hiprandStateii, 8
.type _Z10ticsKernelP12hiprandStatePiff,@object # @_Z10ticsKernelP12hiprandStatePiff
.globl _Z10ticsKernelP12hiprandStatePiff
.p2align 3, 0x0
_Z10ticsKernelP12hiprandStatePiff:
.quad _Z25__device_stub__ticsKernelP12hiprandStatePiff
.size _Z10ticsKernelP12hiprandStatePiff, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "ticscu.txt"
.size .L.str, 11
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Break-up cross section at %f eV is: %f \n "
.size .L.str.1, 42
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\t"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Duration (s)"
.size .L.str.3, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8rng_initP12hiprandStateii"
.size .L__unnamed_1, 29
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10ticsKernelP12hiprandStatePiff"
.size .L__unnamed_2, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__rng_initP12hiprandStateii
.addrsig_sym _Z25__device_stub__ticsKernelP12hiprandStatePiff
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z8rng_initP12hiprandStateii
.addrsig_sym _Z10ticsKernelP12hiprandStatePiff
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b4fb2_00000000-6_ehyd2.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4122:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4122:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6rootxiffff
.type _Z6rootxiffff, @function
_Z6rootxiffff:
.LFB4113:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE4113:
.size _Z6rootxiffff, .-_Z6rootxiffff
.globl _Z6derivsfPfS_
.type _Z6derivsfPfS_, @function
_Z6derivsfPfS_:
.LFB4114:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE4114:
.size _Z6derivsfPfS_, .-_Z6derivsfPfS_
.globl _Z47__device_stub__Z8rng_initP17curandStateXORWOWiiP17curandStateXORWOWii
.type _Z47__device_stub__Z8rng_initP17curandStateXORWOWiiP17curandStateXORWOWii, @function
_Z47__device_stub__Z8rng_initP17curandStateXORWOWiiP17curandStateXORWOWii:
.LFB4144:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8rng_initP17curandStateXORWOWii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4144:
.size _Z47__device_stub__Z8rng_initP17curandStateXORWOWiiP17curandStateXORWOWii, .-_Z47__device_stub__Z8rng_initP17curandStateXORWOWiiP17curandStateXORWOWii
.globl _Z8rng_initP17curandStateXORWOWii
.type _Z8rng_initP17curandStateXORWOWii, @function
_Z8rng_initP17curandStateXORWOWii:
.LFB4145:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z8rng_initP17curandStateXORWOWiiP17curandStateXORWOWii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4145:
.size _Z8rng_initP17curandStateXORWOWii, .-_Z8rng_initP17curandStateXORWOWii
.globl _Z52__device_stub__Z10ticsKernelP17curandStateXORWOWPiffP17curandStateXORWOWPiff
.type _Z52__device_stub__Z10ticsKernelP17curandStateXORWOWPiffP17curandStateXORWOWPiff, @function
_Z52__device_stub__Z10ticsKernelP17curandStateXORWOWPiffP17curandStateXORWOWPiff:
.LFB4146:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10ticsKernelP17curandStateXORWOWPiff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4146:
.size _Z52__device_stub__Z10ticsKernelP17curandStateXORWOWPiffP17curandStateXORWOWPiff, .-_Z52__device_stub__Z10ticsKernelP17curandStateXORWOWPiffP17curandStateXORWOWPiff
.globl _Z10ticsKernelP17curandStateXORWOWPiff
.type _Z10ticsKernelP17curandStateXORWOWPiff, @function
_Z10ticsKernelP17curandStateXORWOWPiff:
.LFB4147:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z10ticsKernelP17curandStateXORWOWPiffP17curandStateXORWOWPiff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4147:
.size _Z10ticsKernelP17curandStateXORWOWPiff, .-_Z10ticsKernelP17curandStateXORWOWPiff
.globl _Z10cudaticsPsf
.type _Z10cudaticsPsf, @function
_Z10cudaticsPsf:
.LFB4115:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $128, %edi
call malloc@PLT
movq %rax, %rbp
leaq 16(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $1536, %esi
call cudaMalloc@PLT
movl $128, %edi
call malloc@PLT
movq %rax, %rbx
leaq 128(%rax), %rdx
.L24:
movl $0, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L24
movl $32, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L25:
movl $5000, %r12d
.L28:
movl $32, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L26
movss .LC1(%rip), %xmm1
movss 12(%rsp), %xmm0
movq 16(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z52__device_stub__Z10ticsKernelP17curandStateXORWOWPiffP17curandStateXORWOWPiff
.L26:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $128, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %eax
.L27:
movl 0(%rbp,%rax), %edx
addl %edx, (%rbx,%rax)
addq $4, %rax
cmpq $128, %rax
jne .L27
subl $1, %r12d
jne .L28
movl $0, %eax
movl $0x00000000, 12(%rsp)
movss .LC1(%rip), %xmm5
movsd .LC2(%rip), %xmm4
movsd .LC3(%rip), %xmm3
jmp .L30
.L37:
movl $32, %edx
movl $12345, %esi
movq 24(%rsp), %rdi
call _Z47__device_stub__Z8rng_initP17curandStateXORWOWiiP17curandStateXORWOWii
jmp .L25
.L29:
pxor %xmm1, %xmm1
cvtsi2ssl (%rbx,%rax,4), %xmm1
pxor %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtss2sd %xmm2, %xmm1
mulsd %xmm4, %xmm1
mulsd %xmm1, %xmm0
divsd %xmm3, %xmm0
pxor %xmm1, %xmm1
cvtss2sd 12(%rsp), %xmm1
addsd %xmm1, %xmm0
pxor %xmm6, %xmm6
cvtsd2ss %xmm0, %xmm6
movss %xmm6, 12(%rsp)
addq $1, %rax
cmpq $32, %rax
je .L38
.L30:
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
mulss %xmm5, %xmm2
cmpl $5, (%rbx,%rax,4)
jg .L29
movl $0, (%rbx,%rax,4)
jmp .L29
.L38:
movq %rbp, %rdi
call free@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L39
movss 12(%rsp), %xmm0
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4115:
.size _Z10cudaticsPsf, .-_Z10cudaticsPsf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "_Z10ticsKernelP17curandStateXORWOWPiff"
.align 8
.LC5:
.string "_Z8rng_initP17curandStateXORWOWii"
.section .rodata.str1.1,"aMS",@progbits,1
.LC6:
.string "precalc_xorwow_matrix"
.LC7:
.string "precalc_xorwow_offset_matrix"
.LC8:
.string "mrg32k3aM1"
.LC9:
.string "mrg32k3aM2"
.LC10:
.string "mrg32k3aM1SubSeq"
.LC11:
.string "mrg32k3aM2SubSeq"
.LC12:
.string "mrg32k3aM1Seq"
.LC13:
.string "mrg32k3aM2Seq"
.LC14:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4149:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z10ticsKernelP17curandStateXORWOWPiff(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z8rng_initP17curandStateXORWOWii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4149:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.1
.LC15:
.string "ticscu.txt"
.section .rodata.str1.8
.align 8
.LC17:
.string "Break-up cross section at %f eV is: %f \n "
.section .rodata.str1.1
.LC18:
.string "\t"
.LC19:
.string "Duration (s)"
.text
.globl main
.type main, @function
main:
.LFB4116:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4116
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $568, %rsp
.cfi_def_cfa_offset 624
movq %fs:40, %rax
movq %rax, 552(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rbx
movq %rbx, %rdi
.LEHB0:
call _ZNSt13basic_fstreamIcSt11char_traitsIcEEC1Ev@PLT
.LEHE0:
movl $16, %edx
leaq .LC15(%rip), %rsi
movq %rbx, %rdi
.LEHB1:
call _ZNSt13basic_fstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, 8(%rsp)
movl $0, %r12d
leaq .LC17(%rip), %r13
leaq 32(%rsp), %r14
leaq .LC18(%rip), %r15
jmp .L47
.L59:
pxor %xmm3, %xmm3
cvtss2sd %xmm0, %xmm3
movq %xmm3, %rbp
pxor %xmm4, %xmm4
cvtss2sd 4(%rsp), %xmm4
movq %xmm4, %rbx
movapd %xmm3, %xmm1
movapd %xmm4, %xmm0
movq %r13, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movq %rbx, %xmm0
movq %r14, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $1, %edx
movq %r15, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rbp, %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L55
cmpb $0, 56(%rbp)
je .L45
movzbl 67(%rbp), %esi
.L46:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
jmp .L56
.L55:
movq 552(%rsp), %rax
subq %fs:40, %rax
jne .L57
call _ZSt16__throw_bad_castv@PLT
.L51:
endbr64
movq %rax, %rbx
leaq 16(%rsp), %rdi
call _ZNSt13basic_fstreamIcSt11char_traitsIcEED1Ev@PLT
movq 552(%rsp), %rax
subq %fs:40, %rax
je .L49
call __stack_chk_fail@PLT
.L57:
call __stack_chk_fail@PLT
.L45:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L46
.L56:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %r12d
cmpl $50, %r12d
je .L58
.L47:
pxor %xmm0, %xmm0
cvtsi2ssl %r12d, %xmm0
cvtss2sd %xmm0, %xmm0
addsd %xmm0, %xmm0
addsd .LC16(%rip), %xmm0
pxor %xmm2, %xmm2
cvtsd2ss %xmm0, %xmm2
movss %xmm2, 4(%rsp)
movaps %xmm2, %xmm0
call _Z10cudaticsPsf
jmp .L59
.L58:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq 8(%rsp), %rcx
subq %rcx, %rax
movq %rax, %rcx
movabsq $1237940039285380275, %rdx
imulq %rdx
sarq $26, %rdx
sarq $63, %rcx
subq %rcx, %rdx
movq %rdx, %rbx
leaq .LC19(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC18(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE1:
leaq 16(%rsp), %rdi
call _ZNSt13basic_fstreamIcSt11char_traitsIcEED1Ev@PLT
movq 552(%rsp), %rax
subq %fs:40, %rax
jne .L60
movl $0, %eax
addq $568, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.LEHE2:
.L60:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4116:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4116:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4116-.LLSDACSB4116
.LLSDACSB4116:
.uleb128 .LEHB0-.LFB4116
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4116
.uleb128 .LEHE1-.LEHB1
.uleb128 .L51-.LFB4116
.uleb128 0
.uleb128 .LEHB2-.LFB4116
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.LLSDACSE4116:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1058013184
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long -872415232
.long 1074546234
.align 8
.LC3:
.long 0
.long 1085507584
.align 8
.LC16:
.long 1711443804
.long 1073229769
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ehyd2.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z23__device_stub__rng_initP12hiprandStateii # -- Begin function _Z23__device_stub__rng_initP12hiprandStateii
.p2align 4, 0x90
.type _Z23__device_stub__rng_initP12hiprandStateii,@function
_Z23__device_stub__rng_initP12hiprandStateii: # @_Z23__device_stub__rng_initP12hiprandStateii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8rng_initP12hiprandStateii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z23__device_stub__rng_initP12hiprandStateii, .Lfunc_end0-_Z23__device_stub__rng_initP12hiprandStateii
.cfi_endproc
# -- End function
.globl _Z25__device_stub__ticsKernelP12hiprandStatePiff # -- Begin function _Z25__device_stub__ticsKernelP12hiprandStatePiff
.p2align 4, 0x90
.type _Z25__device_stub__ticsKernelP12hiprandStatePiff,@function
_Z25__device_stub__ticsKernelP12hiprandStatePiff: # @_Z25__device_stub__ticsKernelP12hiprandStatePiff
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10ticsKernelP12hiprandStatePiff, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z25__device_stub__ticsKernelP12hiprandStatePiff, .Lfunc_end1-_Z25__device_stub__ticsKernelP12hiprandStatePiff
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z10cudaticsPsf
.LCPI2_0:
.long 0x3f100000 # float 0.5625
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_1:
.quad 0x400c463acc000000 # double 3.5342918336391449
.LCPI2_2:
.quad 0x40b3880000000000 # double 5000
.text
.globl _Z10cudaticsPsf
.p2align 4, 0x90
.type _Z10cudaticsPsf,@function
_Z10cudaticsPsf: # @_Z10cudaticsPsf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movss %xmm0, (%rsp) # 4-byte Spill
movabsq $4294967297, %r15 # imm = 0x100000001
movl $128, %edi
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $128, %esi
callq hipMalloc
leaq 88(%rsp), %rdi
movl $1536, %esi # imm = 0x600
callq hipMalloc
movl $128, %edi
callq malloc
movq %rax, %r14
xorps %xmm0, %xmm0
movups %xmm0, (%rax)
movups %xmm0, 16(%rax)
movups %xmm0, 32(%rax)
movups %xmm0, 48(%rax)
movups %xmm0, 64(%rax)
movups %xmm0, 80(%rax)
movups %xmm0, 96(%rax)
movups %xmm0, 112(%rax)
leaq 31(%r15), %r12
xorl %ebp, %ebp
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 88(%rsp), %rax
movq %rax, 72(%rsp)
movl $12345, 16(%rsp) # imm = 0x3039
movl $32, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8rng_initP12hiprandStateii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
leaq 96(%rsp), %r13
.p2align 4, 0x90
.LBB2_3: # =>This Loop Header: Depth=1
# Child Loop BB2_6 Depth 2
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4: # in Loop: Header=BB2_3 Depth=1
movq 88(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movss (%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 4(%rsp)
movl $1058013184, 84(%rsp) # imm = 0x3F100000
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 84(%rsp), %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z10ticsKernelP12hiprandStatePiff, %edi
movq %r13, %r9
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_5: # %.critedge
# in Loop: Header=BB2_3 Depth=1
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movl $128, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_6: # Parent Loop BB2_3 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%rax,4), %ecx
addl %ecx, (%r14,%rax,4)
incq %rax
cmpq $32, %rax
jne .LBB2_6
# %bb.7: # in Loop: Header=BB2_3 Depth=1
incl %ebp
cmpl $5000, %ebp # imm = 0x1388
jne .LBB2_3
# %bb.8: # %.preheader.preheader
xorps %xmm4, %xmm4
xorl %eax, %eax
movss .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movsd .LCPI2_1(%rip), %xmm1 # xmm1 = mem[0],zero
movsd .LCPI2_2(%rip), %xmm2 # xmm2 = mem[0],zero
jmp .LBB2_9
.p2align 4, 0x90
.LBB2_11: # in Loop: Header=BB2_9 Depth=1
cvtss2sd %xmm4, %xmm4
cvtss2sd %xmm3, %xmm3
mulsd %xmm1, %xmm3
xorps %xmm5, %xmm5
cvtsi2ssl (%r14,%rax,4), %xmm5
cvtss2sd %xmm5, %xmm5
mulsd %xmm3, %xmm5
divsd %xmm2, %xmm5
addsd %xmm4, %xmm5
xorps %xmm4, %xmm4
cvtsd2ss %xmm5, %xmm4
incq %rax
cmpq $32, %rax
je .LBB2_12
.LBB2_9: # %.preheader
# =>This Inner Loop Header: Depth=1
xorps %xmm3, %xmm3
cvtsi2ss %eax, %xmm3
mulss %xmm0, %xmm3
cmpl $5, (%r14,%rax,4)
jg .LBB2_11
# %bb.10: # in Loop: Header=BB2_9 Depth=1
movl $0, (%r14,%rax,4)
jmp .LBB2_11
.LBB2_12: # %.loopexit
movq %rbx, %rdi
movss %xmm4, (%rsp) # 4-byte Spill
callq free
movq 8(%rsp), %rdi
callq hipFree
movss (%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z10cudaticsPsf, .Lfunc_end2-_Z10cudaticsPsf
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x3ff82fc966028f5c # double 1.511666677929461
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $544, %rsp # imm = 0x220
.cfi_def_cfa_offset 592
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 16(%rsp), %rbx
movq %rbx, %rdi
callq _ZNSt13basic_fstreamIcSt11char_traitsIcEEC1Ev
leaq 40(%rsp), %rdi
.Ltmp0:
movl $.L.str, %esi
movl $16, %edx
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp1:
# %bb.1: # %.noexc
movq 16(%rsp), %rcx
addq -24(%rcx), %rbx
xorl %esi, %esi
testq %rax, %rax
jne .LBB3_3
# %bb.2:
movl 32(%rbx), %esi
orl $4, %esi
.LBB3_3: # %.invoke
.Ltmp2:
movq %rbx, %rdi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp3:
# %bb.4: # %_ZNSt13basic_fstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %rbx
xorl %ebp, %ebp
leaq 32(%rsp), %r14
.p2align 4, 0x90
.LBB3_5: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %ebp, %xmm0
addsd %xmm0, %xmm0
addsd .LCPI3_0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
.Ltmp5:
movss %xmm0, (%rsp) # 4-byte Spill
callq _Z10cudaticsPsf
.Ltmp6:
# %bb.6: # in Loop: Header=BB3_5 Depth=1
movss (%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
xorps %xmm2, %xmm2
cvtss2sd %xmm1, %xmm2
movsd %xmm2, (%rsp) # 8-byte Spill
xorps %xmm1, %xmm1
cvtss2sd %xmm0, %xmm1
movl $.L.str.1, %edi
movaps %xmm2, %xmm0
movsd %xmm1, 8(%rsp) # 8-byte Spill
movb $2, %al
callq printf
.Ltmp7:
movq %r14, %rdi
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp8:
# %bb.7: # %_ZNSolsEf.exit
# in Loop: Header=BB3_5 Depth=1
.Ltmp9:
movq %rax, %r15
movl $.L.str.2, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp10:
# %bb.8: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
# in Loop: Header=BB3_5 Depth=1
.Ltmp11:
movq %r15, %rdi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp12:
# %bb.9: # %_ZNSolsEf.exit25
# in Loop: Header=BB3_5 Depth=1
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB3_10
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB3_5 Depth=1
cmpb $0, 56(%r12)
je .LBB3_14
# %bb.13: # in Loop: Header=BB3_5 Depth=1
movzbl 67(%r12), %eax
jmp .LBB3_16
.p2align 4, 0x90
.LBB3_14: # in Loop: Header=BB3_5 Depth=1
.Ltmp13:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp14:
# %bb.15: # %.noexc35
# in Loop: Header=BB3_5 Depth=1
movq (%r12), %rax
.Ltmp15:
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp16:
.LBB3_16: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
# in Loop: Header=BB3_5 Depth=1
.Ltmp17:
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
.Ltmp18:
# %bb.17: # %.noexc37
# in Loop: Header=BB3_5 Depth=1
.Ltmp19:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp20:
# %bb.18: # %_ZNSolsEPFRSoS_E.exit
# in Loop: Header=BB3_5 Depth=1
incl %ebp
cmpl $50, %ebp
jne .LBB3_5
# %bb.19:
callq _ZNSt6chrono3_V212system_clock3nowEv
subq %rbx, %rax
movabsq $1237940039285380275, %rcx # imm = 0x112E0BE826D694B3
imulq %rcx
movq %rdx, %rbx
.Ltmp22:
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp23:
# %bb.20: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit28
.Ltmp24:
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp25:
# %bb.21: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit30
.Ltmp26:
movq %rbx, %rax
shrq $63, %rax
sarq $26, %rbx
addq %rax, %rbx
movl $_ZSt4cout, %edi
movq %rbx, %rsi
callq _ZNSo9_M_insertIlEERSoT_
.Ltmp27:
# %bb.22: # %_ZNSolsEl.exit
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB3_23
# %bb.27: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i40
cmpb $0, 56(%r14)
je .LBB3_29
# %bb.28:
movzbl 67(%r14), %eax
jmp .LBB3_31
.LBB3_29:
.Ltmp28:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp29:
# %bb.30: # %.noexc45
movq (%r14), %rax
.Ltmp30:
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp31:
.LBB3_31: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i42
.Ltmp32:
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp33:
# %bb.32: # %.noexc47
.Ltmp34:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp35:
# %bb.33: # %_ZNSolsEPFRSoS_E.exit33
leaq 16(%rsp), %rdi
movl $_ZTTSt13basic_fstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt13basic_fstreamIcSt11char_traitsIcEED2Ev
leaq 280(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
xorl %eax, %eax
addq $544, %rsp # imm = 0x220
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_10:
.cfi_def_cfa_offset 592
.Ltmp39:
callq _ZSt16__throw_bad_castv
.Ltmp40:
# %bb.11: # %.noexc34
.LBB3_23:
.Ltmp36:
callq _ZSt16__throw_bad_castv
.Ltmp37:
# %bb.26: # %.noexc44
.LBB3_36:
.Ltmp4:
jmp .LBB3_35
.LBB3_34:
.Ltmp38:
jmp .LBB3_35
.LBB3_25: # %.loopexit.split-lp
.Ltmp41:
jmp .LBB3_35
.LBB3_24: # %.loopexit
.Ltmp21:
.LBB3_35:
movq %rax, %rbx
leaq 16(%rsp), %rdi
movl $_ZTTSt13basic_fstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt13basic_fstreamIcSt11char_traitsIcEED2Ev
leaq 280(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table3:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp3-.Ltmp0 # Call between .Ltmp0 and .Ltmp3
.uleb128 .Ltmp4-.Lfunc_begin0 # jumps to .Ltmp4
.byte 0 # On action: cleanup
.uleb128 .Ltmp5-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp20-.Ltmp5 # Call between .Ltmp5 and .Ltmp20
.uleb128 .Ltmp21-.Lfunc_begin0 # jumps to .Ltmp21
.byte 0 # On action: cleanup
.uleb128 .Ltmp22-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp35-.Ltmp22 # Call between .Ltmp22 and .Ltmp35
.uleb128 .Ltmp38-.Lfunc_begin0 # jumps to .Ltmp38
.byte 0 # On action: cleanup
.uleb128 .Ltmp39-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp40-.Ltmp39 # Call between .Ltmp39 and .Ltmp40
.uleb128 .Ltmp41-.Lfunc_begin0 # jumps to .Ltmp41
.byte 0 # On action: cleanup
.uleb128 .Ltmp36-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp37-.Ltmp36 # Call between .Ltmp36 and .Ltmp37
.uleb128 .Ltmp38-.Lfunc_begin0 # jumps to .Ltmp38
.byte 0 # On action: cleanup
.uleb128 .Ltmp37-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Lfunc_end3-.Ltmp37 # Call between .Ltmp37 and .Lfunc_end3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8rng_initP12hiprandStateii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10ticsKernelP12hiprandStatePiff, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8rng_initP12hiprandStateii,@object # @_Z8rng_initP12hiprandStateii
.section .rodata,"a",@progbits
.globl _Z8rng_initP12hiprandStateii
.p2align 3, 0x0
_Z8rng_initP12hiprandStateii:
.quad _Z23__device_stub__rng_initP12hiprandStateii
.size _Z8rng_initP12hiprandStateii, 8
.type _Z10ticsKernelP12hiprandStatePiff,@object # @_Z10ticsKernelP12hiprandStatePiff
.globl _Z10ticsKernelP12hiprandStatePiff
.p2align 3, 0x0
_Z10ticsKernelP12hiprandStatePiff:
.quad _Z25__device_stub__ticsKernelP12hiprandStatePiff
.size _Z10ticsKernelP12hiprandStatePiff, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "ticscu.txt"
.size .L.str, 11
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Break-up cross section at %f eV is: %f \n "
.size .L.str.1, 42
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\t"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Duration (s)"
.size .L.str.3, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8rng_initP12hiprandStateii"
.size .L__unnamed_1, 29
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10ticsKernelP12hiprandStatePiff"
.size .L__unnamed_2, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__rng_initP12hiprandStateii
.addrsig_sym _Z25__device_stub__ticsKernelP12hiprandStatePiff
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z8rng_initP12hiprandStateii
.addrsig_sym _Z10ticsKernelP12hiprandStatePiff
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <cuda.h>
#include <cuda_runtime.h>
typedef unsigned int uint;
// O kernel processará o espaço do bloco, eliminando todos os múltiplos de k
__global__ void sieve(uint* d_array, uint k) {
int idx = threadIdx.x + (32 * blockIdx.x);
if ( (d_array[idx] % k) == 0) {
d_array[idx] = 0;
}
__syncthreads();
}
extern "C++" void onDevice(uint *ptrK, uint block_size, uint n, uint *h_array) {
uint k = *ptrK;
// Alocando os espaços na GPU para processamento.
uint* d_array;
// Allocando memória na GPU.
cudaMalloc((void**)&d_array, (block_size) * sizeof(uint));
// Copiando conteudo para a GPU.
cudaMemcpy(d_array, h_array, (block_size) * sizeof(uint), cudaMemcpyHostToDevice);
dim3 threadsPorBloco(32, 1, 1);
dim3 blocosPorGrid(ceil( (double)block_size/32), 1, 1);
// Uso da GPU para eliminar os múltiplos do bloco
// Invoka o kernel para operações de mod
sieve<<<blocosPorGrid, threadsPorBloco>>>(d_array, k);
// Detecção de erro caso o kernel apresente algum...
cudaError_t err = cudaGetLastError();
if (err != cudaSuccess)
printf("Error: %s\n", cudaGetErrorString(err));
// Atualiza o array presente na CPU depois do resultado.
cudaMemcpy(h_array, d_array, block_size * sizeof(uint), cudaMemcpyDeviceToHost);
// Desaloca os espaços alocados.
cudaFree(d_array);
} | code for sm_80
Function : _Z5sievePjj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ LEA R2, R2, R3, 0x5 ; /* 0x0000000302027211 */
/* 0x001fca00078e28ff */
/*0060*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*0080*/ I2F.U32.RP R6, c[0x0][0x168] ; /* 0x00005a0000067b06 */
/* 0x000e220000209000 */
/*0090*/ ISETP.NE.U32.AND P1, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fce0003f25070 */
/*00a0*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*00b0*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*00c0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*00d0*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*00e0*/ IMAD.MOV R7, RZ, RZ, -R5 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a05 */
/*00f0*/ IMAD R7, R7, c[0x0][0x168], RZ ; /* 0x00005a0007077a24 */
/* 0x000fca00078e02ff */
/*0100*/ IMAD.HI.U32 R5, R5, R7, R4 ; /* 0x0000000705057227 */
/* 0x000fcc00078e0004 */
/*0110*/ IMAD.HI.U32 R5, R5, R0, RZ ; /* 0x0000000005057227 */
/* 0x004fc800078e00ff */
/*0120*/ IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a05 */
/*0130*/ IMAD R0, R5, c[0x0][0x168], R0 ; /* 0x00005a0005007a24 */
/* 0x000fca00078e0200 */
/*0140*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06070 */
/*0150*/ @P0 IADD3 R0, R0, -c[0x0][0x168], RZ ; /* 0x80005a0000000a10 */
/* 0x000fc80007ffe0ff */
/*0160*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06070 */
/*0170*/ @P0 IADD3 R0, R0, -c[0x0][0x168], RZ ; /* 0x80005a0000000a10 */
/* 0x000fe40007ffe0ff */
/*0180*/ @!P1 LOP3.LUT R0, RZ, c[0x0][0x168], RZ, 0x33, !PT ; /* 0x00005a00ff009a12 */
/* 0x000fc800078e33ff */
/*0190*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*01a0*/ @!P0 STG.E [R2.64], RZ ; /* 0x000000ff02008986 */
/* 0x000fe8000c101904 */
/*01b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <cuda.h>
#include <cuda_runtime.h>
typedef unsigned int uint;
// O kernel processará o espaço do bloco, eliminando todos os múltiplos de k
__global__ void sieve(uint* d_array, uint k) {
int idx = threadIdx.x + (32 * blockIdx.x);
if ( (d_array[idx] % k) == 0) {
d_array[idx] = 0;
}
__syncthreads();
}
extern "C++" void onDevice(uint *ptrK, uint block_size, uint n, uint *h_array) {
uint k = *ptrK;
// Alocando os espaços na GPU para processamento.
uint* d_array;
// Allocando memória na GPU.
cudaMalloc((void**)&d_array, (block_size) * sizeof(uint));
// Copiando conteudo para a GPU.
cudaMemcpy(d_array, h_array, (block_size) * sizeof(uint), cudaMemcpyHostToDevice);
dim3 threadsPorBloco(32, 1, 1);
dim3 blocosPorGrid(ceil( (double)block_size/32), 1, 1);
// Uso da GPU para eliminar os múltiplos do bloco
// Invoka o kernel para operações de mod
sieve<<<blocosPorGrid, threadsPorBloco>>>(d_array, k);
// Detecção de erro caso o kernel apresente algum...
cudaError_t err = cudaGetLastError();
if (err != cudaSuccess)
printf("Error: %s\n", cudaGetErrorString(err));
// Atualiza o array presente na CPU depois do resultado.
cudaMemcpy(h_array, d_array, block_size * sizeof(uint), cudaMemcpyDeviceToHost);
// Desaloca os espaços alocados.
cudaFree(d_array);
} | .file "tmpxft_00123f75_00000000-6_sieve_hybrid_cuda.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z5sievePjjPjj
.type _Z25__device_stub__Z5sievePjjPjj, @function
_Z25__device_stub__Z5sievePjjPjj:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z5sievePjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z25__device_stub__Z5sievePjjPjj, .-_Z25__device_stub__Z5sievePjjPjj
.globl _Z5sievePjj
.type _Z5sievePjj, @function
_Z5sievePjj:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z5sievePjjPjj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z5sievePjj, .-_Z5sievePjj
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "Error: %s\n"
.text
.globl _Z8onDevicePjjjS_
.type _Z8onDevicePjjjS_, @function
_Z8onDevicePjjjS_:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %rcx, %rbx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl (%rdi), %r12d
movl %esi, %ebp
leaq 0(,%rbp,4), %r13
leaq 8(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
pxor %xmm0, %xmm0
cvtsi2sdq %rbp, %xmm0
mulsd .LC0(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC5(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC1(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L14
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC3(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L14:
cvttsd2siq %xmm3, %rax
movl %eax, 28(%rsp)
movl $1, 32(%rsp)
movl 24(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L20
.L16:
movl $2, %ecx
movq %r13, %rdx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl %r12d, %esi
movq 8(%rsp), %rdi
call _Z25__device_stub__Z5sievePjjPjj
jmp .L15
.L20:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z8onDevicePjjjS_, .-_Z8onDevicePjjjS_
.section .rodata.str1.1
.LC6:
.string "_Z5sievePjj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z5sievePjj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1067450368
.align 8
.LC1:
.long 0
.long 1127219200
.align 8
.LC3:
.long 0
.long 1072693248
.align 8
.LC5:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cuda.h>
#include <cuda_runtime.h>
typedef unsigned int uint;
// O kernel processará o espaço do bloco, eliminando todos os múltiplos de k
__global__ void sieve(uint* d_array, uint k) {
int idx = threadIdx.x + (32 * blockIdx.x);
if ( (d_array[idx] % k) == 0) {
d_array[idx] = 0;
}
__syncthreads();
}
extern "C++" void onDevice(uint *ptrK, uint block_size, uint n, uint *h_array) {
uint k = *ptrK;
// Alocando os espaços na GPU para processamento.
uint* d_array;
// Allocando memória na GPU.
cudaMalloc((void**)&d_array, (block_size) * sizeof(uint));
// Copiando conteudo para a GPU.
cudaMemcpy(d_array, h_array, (block_size) * sizeof(uint), cudaMemcpyHostToDevice);
dim3 threadsPorBloco(32, 1, 1);
dim3 blocosPorGrid(ceil( (double)block_size/32), 1, 1);
// Uso da GPU para eliminar os múltiplos do bloco
// Invoka o kernel para operações de mod
sieve<<<blocosPorGrid, threadsPorBloco>>>(d_array, k);
// Detecção de erro caso o kernel apresente algum...
cudaError_t err = cudaGetLastError();
if (err != cudaSuccess)
printf("Error: %s\n", cudaGetErrorString(err));
// Atualiza o array presente na CPU depois do resultado.
cudaMemcpy(h_array, d_array, block_size * sizeof(uint), cudaMemcpyDeviceToHost);
// Desaloca os espaços alocados.
cudaFree(d_array);
} | #include <iostream>
#include <hip/hip_runtime.h>
typedef unsigned int uint;
// O kernel processará o espaço do bloco, eliminando todos os múltiplos de k
__global__ void sieve(uint* d_array, uint k) {
int idx = threadIdx.x + (32 * blockIdx.x);
if ( (d_array[idx] % k) == 0) {
d_array[idx] = 0;
}
__syncthreads();
}
extern "C++" void onDevice(uint *ptrK, uint block_size, uint n, uint *h_array) {
uint k = *ptrK;
// Alocando os espaços na GPU para processamento.
uint* d_array;
// Allocando memória na GPU.
hipMalloc((void**)&d_array, (block_size) * sizeof(uint));
// Copiando conteudo para a GPU.
hipMemcpy(d_array, h_array, (block_size) * sizeof(uint), hipMemcpyHostToDevice);
dim3 threadsPorBloco(32, 1, 1);
dim3 blocosPorGrid(ceil( (double)block_size/32), 1, 1);
// Uso da GPU para eliminar os múltiplos do bloco
// Invoka o kernel para operações de mod
sieve<<<blocosPorGrid, threadsPorBloco>>>(d_array, k);
// Detecção de erro caso o kernel apresente algum...
hipError_t err = hipGetLastError();
if (err != hipSuccess)
printf("Error: %s\n", hipGetErrorString(err));
// Atualiza o array presente na CPU depois do resultado.
hipMemcpy(h_array, d_array, block_size * sizeof(uint), hipMemcpyDeviceToHost);
// Desaloca os espaços alocados.
hipFree(d_array);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <iostream>
#include <hip/hip_runtime.h>
typedef unsigned int uint;
// O kernel processará o espaço do bloco, eliminando todos os múltiplos de k
__global__ void sieve(uint* d_array, uint k) {
int idx = threadIdx.x + (32 * blockIdx.x);
if ( (d_array[idx] % k) == 0) {
d_array[idx] = 0;
}
__syncthreads();
}
extern "C++" void onDevice(uint *ptrK, uint block_size, uint n, uint *h_array) {
uint k = *ptrK;
// Alocando os espaços na GPU para processamento.
uint* d_array;
// Allocando memória na GPU.
hipMalloc((void**)&d_array, (block_size) * sizeof(uint));
// Copiando conteudo para a GPU.
hipMemcpy(d_array, h_array, (block_size) * sizeof(uint), hipMemcpyHostToDevice);
dim3 threadsPorBloco(32, 1, 1);
dim3 blocosPorGrid(ceil( (double)block_size/32), 1, 1);
// Uso da GPU para eliminar os múltiplos do bloco
// Invoka o kernel para operações de mod
sieve<<<blocosPorGrid, threadsPorBloco>>>(d_array, k);
// Detecção de erro caso o kernel apresente algum...
hipError_t err = hipGetLastError();
if (err != hipSuccess)
printf("Error: %s\n", hipGetErrorString(err));
// Atualiza o array presente na CPU depois do resultado.
hipMemcpy(h_array, d_array, block_size * sizeof(uint), hipMemcpyDeviceToHost);
// Desaloca os espaços alocados.
hipFree(d_array);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5sievePjj
.globl _Z5sievePjj
.p2align 8
.type _Z5sievePjj,@function
_Z5sievePjj:
s_load_b64 s[2:3], s[0:1], 0x0
v_lshl_add_u32 v0, s15, 5, v0
s_load_b32 s0, s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_cvt_f32_u32_e32 v3, s0
s_sub_i32 s1, 0, s0
global_load_b32 v2, v[0:1], off
v_rcp_iflag_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x4f7ffffe, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v3, v3
v_mul_lo_u32 v4, s1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v4, v3, v4
v_add_nc_u32_e32 v3, v3, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v2, v3
v_mul_lo_u32 v3, v3, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v3
v_subrev_nc_u32_e32 v3, s0, v2
v_cmp_le_u32_e32 vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_subrev_nc_u32_e32 v3, s0, v2
v_cmp_le_u32_e32 vcc_lo, s0, v2
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v2, 0
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5sievePjj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5sievePjj, .Lfunc_end0-_Z5sievePjj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5sievePjj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5sievePjj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <iostream>
#include <hip/hip_runtime.h>
typedef unsigned int uint;
// O kernel processará o espaço do bloco, eliminando todos os múltiplos de k
__global__ void sieve(uint* d_array, uint k) {
int idx = threadIdx.x + (32 * blockIdx.x);
if ( (d_array[idx] % k) == 0) {
d_array[idx] = 0;
}
__syncthreads();
}
extern "C++" void onDevice(uint *ptrK, uint block_size, uint n, uint *h_array) {
uint k = *ptrK;
// Alocando os espaços na GPU para processamento.
uint* d_array;
// Allocando memória na GPU.
hipMalloc((void**)&d_array, (block_size) * sizeof(uint));
// Copiando conteudo para a GPU.
hipMemcpy(d_array, h_array, (block_size) * sizeof(uint), hipMemcpyHostToDevice);
dim3 threadsPorBloco(32, 1, 1);
dim3 blocosPorGrid(ceil( (double)block_size/32), 1, 1);
// Uso da GPU para eliminar os múltiplos do bloco
// Invoka o kernel para operações de mod
sieve<<<blocosPorGrid, threadsPorBloco>>>(d_array, k);
// Detecção de erro caso o kernel apresente algum...
hipError_t err = hipGetLastError();
if (err != hipSuccess)
printf("Error: %s\n", hipGetErrorString(err));
// Atualiza o array presente na CPU depois do resultado.
hipMemcpy(h_array, d_array, block_size * sizeof(uint), hipMemcpyDeviceToHost);
// Desaloca os espaços alocados.
hipFree(d_array);
} | .text
.file "sieve_hybrid_cuda.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z20__device_stub__sievePjj # -- Begin function _Z20__device_stub__sievePjj
.p2align 4, 0x90
.type _Z20__device_stub__sievePjj,@function
_Z20__device_stub__sievePjj: # @_Z20__device_stub__sievePjj
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z5sievePjj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z20__device_stub__sievePjj, .Lfunc_end0-_Z20__device_stub__sievePjj
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z8onDevicePjjjS_
.LCPI1_0:
.quad 0x3fa0000000000000 # double 0.03125
.text
.globl _Z8onDevicePjjjS_
.p2align 4, 0x90
.type _Z8onDevicePjjjS_,@function
_Z8onDevicePjjjS_: # @_Z8onDevicePjjjS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $104, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rcx, %rbx
movl (%rdi), %ebp
movl %esi, %r15d
leaq (,%r15,4), %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
cvtsi2sd %r15, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $32, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl %ebp, 20(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5sievePjj, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipGetLastError
testl %eax, %eax
je .LBB1_4
# %bb.3:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB1_4:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
addq $104, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z8onDevicePjjjS_, .Lfunc_end1-_Z8onDevicePjjjS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5sievePjj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5sievePjj,@object # @_Z5sievePjj
.section .rodata,"a",@progbits
.globl _Z5sievePjj
.p2align 3, 0x0
_Z5sievePjj:
.quad _Z20__device_stub__sievePjj
.size _Z5sievePjj, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error: %s\n"
.size .L.str, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5sievePjj"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__sievePjj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5sievePjj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5sievePjj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ LEA R2, R2, R3, 0x5 ; /* 0x0000000302027211 */
/* 0x001fca00078e28ff */
/*0060*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*0080*/ I2F.U32.RP R6, c[0x0][0x168] ; /* 0x00005a0000067b06 */
/* 0x000e220000209000 */
/*0090*/ ISETP.NE.U32.AND P1, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fce0003f25070 */
/*00a0*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*00b0*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*00c0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*00d0*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*00e0*/ IMAD.MOV R7, RZ, RZ, -R5 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a05 */
/*00f0*/ IMAD R7, R7, c[0x0][0x168], RZ ; /* 0x00005a0007077a24 */
/* 0x000fca00078e02ff */
/*0100*/ IMAD.HI.U32 R5, R5, R7, R4 ; /* 0x0000000705057227 */
/* 0x000fcc00078e0004 */
/*0110*/ IMAD.HI.U32 R5, R5, R0, RZ ; /* 0x0000000005057227 */
/* 0x004fc800078e00ff */
/*0120*/ IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a05 */
/*0130*/ IMAD R0, R5, c[0x0][0x168], R0 ; /* 0x00005a0005007a24 */
/* 0x000fca00078e0200 */
/*0140*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06070 */
/*0150*/ @P0 IADD3 R0, R0, -c[0x0][0x168], RZ ; /* 0x80005a0000000a10 */
/* 0x000fc80007ffe0ff */
/*0160*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06070 */
/*0170*/ @P0 IADD3 R0, R0, -c[0x0][0x168], RZ ; /* 0x80005a0000000a10 */
/* 0x000fe40007ffe0ff */
/*0180*/ @!P1 LOP3.LUT R0, RZ, c[0x0][0x168], RZ, 0x33, !PT ; /* 0x00005a00ff009a12 */
/* 0x000fc800078e33ff */
/*0190*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*01a0*/ @!P0 STG.E [R2.64], RZ ; /* 0x000000ff02008986 */
/* 0x000fe8000c101904 */
/*01b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5sievePjj
.globl _Z5sievePjj
.p2align 8
.type _Z5sievePjj,@function
_Z5sievePjj:
s_load_b64 s[2:3], s[0:1], 0x0
v_lshl_add_u32 v0, s15, 5, v0
s_load_b32 s0, s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_cvt_f32_u32_e32 v3, s0
s_sub_i32 s1, 0, s0
global_load_b32 v2, v[0:1], off
v_rcp_iflag_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x4f7ffffe, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v3, v3
v_mul_lo_u32 v4, s1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v4, v3, v4
v_add_nc_u32_e32 v3, v3, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v2, v3
v_mul_lo_u32 v3, v3, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v3
v_subrev_nc_u32_e32 v3, s0, v2
v_cmp_le_u32_e32 vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_subrev_nc_u32_e32 v3, s0, v2
v_cmp_le_u32_e32 vcc_lo, s0, v2
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v2, 0
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5sievePjj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5sievePjj, .Lfunc_end0-_Z5sievePjj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5sievePjj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5sievePjj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00123f75_00000000-6_sieve_hybrid_cuda.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z5sievePjjPjj
.type _Z25__device_stub__Z5sievePjjPjj, @function
_Z25__device_stub__Z5sievePjjPjj:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z5sievePjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z25__device_stub__Z5sievePjjPjj, .-_Z25__device_stub__Z5sievePjjPjj
.globl _Z5sievePjj
.type _Z5sievePjj, @function
_Z5sievePjj:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z5sievePjjPjj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z5sievePjj, .-_Z5sievePjj
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "Error: %s\n"
.text
.globl _Z8onDevicePjjjS_
.type _Z8onDevicePjjjS_, @function
_Z8onDevicePjjjS_:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %rcx, %rbx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl (%rdi), %r12d
movl %esi, %ebp
leaq 0(,%rbp,4), %r13
leaq 8(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
pxor %xmm0, %xmm0
cvtsi2sdq %rbp, %xmm0
mulsd .LC0(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC5(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC1(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L14
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC3(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L14:
cvttsd2siq %xmm3, %rax
movl %eax, 28(%rsp)
movl $1, 32(%rsp)
movl 24(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L20
.L16:
movl $2, %ecx
movq %r13, %rdx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl %r12d, %esi
movq 8(%rsp), %rdi
call _Z25__device_stub__Z5sievePjjPjj
jmp .L15
.L20:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z8onDevicePjjjS_, .-_Z8onDevicePjjjS_
.section .rodata.str1.1
.LC6:
.string "_Z5sievePjj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z5sievePjj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1067450368
.align 8
.LC1:
.long 0
.long 1127219200
.align 8
.LC3:
.long 0
.long 1072693248
.align 8
.LC5:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sieve_hybrid_cuda.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z20__device_stub__sievePjj # -- Begin function _Z20__device_stub__sievePjj
.p2align 4, 0x90
.type _Z20__device_stub__sievePjj,@function
_Z20__device_stub__sievePjj: # @_Z20__device_stub__sievePjj
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z5sievePjj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z20__device_stub__sievePjj, .Lfunc_end0-_Z20__device_stub__sievePjj
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z8onDevicePjjjS_
.LCPI1_0:
.quad 0x3fa0000000000000 # double 0.03125
.text
.globl _Z8onDevicePjjjS_
.p2align 4, 0x90
.type _Z8onDevicePjjjS_,@function
_Z8onDevicePjjjS_: # @_Z8onDevicePjjjS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $104, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rcx, %rbx
movl (%rdi), %ebp
movl %esi, %r15d
leaq (,%r15,4), %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
cvtsi2sd %r15, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $32, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl %ebp, 20(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5sievePjj, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipGetLastError
testl %eax, %eax
je .LBB1_4
# %bb.3:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB1_4:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
addq $104, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z8onDevicePjjjS_, .Lfunc_end1-_Z8onDevicePjjjS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5sievePjj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5sievePjj,@object # @_Z5sievePjj
.section .rodata,"a",@progbits
.globl _Z5sievePjj
.p2align 3, 0x0
_Z5sievePjj:
.quad _Z20__device_stub__sievePjj
.size _Z5sievePjj, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error: %s\n"
.size .L.str, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5sievePjj"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__sievePjj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5sievePjj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*------------check.cu------------------------------------------------------//
*
* Purpose: This is a simple cuda file for checking your gpu works
*
* It prints 0 -> 63
*
*-----------------------------------------------------------------------------*/
#include <iostream>
#include <math.h>
__global__ void findID(double *a, int n){
// First we need to find our global threadID
int id = blockIdx.x*blockDim.x + threadIdx.x;
// Make sure we are not out of range
if (id < n){
a[id] = id;
}
}
int main(){
// size of vectors
int n = 64;
// Host vectors
double *h_a;
// Device vectors
double *d_a;
// allocating space on host and device
h_a = (double*)malloc(sizeof(double)*n);
// Allocating space on GPU
cudaMalloc(&d_a, sizeof(double)*n);
// Creating blocks and grid ints
int threads, grid;
threads = 64;
grid = (int)ceil((float)n/threads);
findID<<<grid, threads>>>(d_a, n);
// Now to copy c back
cudaMemcpy(h_a, d_a, sizeof(double)*n, cudaMemcpyDeviceToHost);
for (int i = 0; i < n; ++i){
std::cout << h_a[i] << '\n';
}
// Release memory
cudaFree(d_a);
free(h_a);
} | code for sm_80
Function : _Z6findIDPdi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ I2F.F64 R4, R0 ; /* 0x0000000000047312 */
/* 0x000e220000201c00 */
/*0070*/ HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff037435 */
/* 0x000fe200000001ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0090*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*00a0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x001fe2000c101b04 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*------------check.cu------------------------------------------------------//
*
* Purpose: This is a simple cuda file for checking your gpu works
*
* It prints 0 -> 63
*
*-----------------------------------------------------------------------------*/
#include <iostream>
#include <math.h>
__global__ void findID(double *a, int n){
// First we need to find our global threadID
int id = blockIdx.x*blockDim.x + threadIdx.x;
// Make sure we are not out of range
if (id < n){
a[id] = id;
}
}
int main(){
// size of vectors
int n = 64;
// Host vectors
double *h_a;
// Device vectors
double *d_a;
// allocating space on host and device
h_a = (double*)malloc(sizeof(double)*n);
// Allocating space on GPU
cudaMalloc(&d_a, sizeof(double)*n);
// Creating blocks and grid ints
int threads, grid;
threads = 64;
grid = (int)ceil((float)n/threads);
findID<<<grid, threads>>>(d_a, n);
// Now to copy c back
cudaMemcpy(h_a, d_a, sizeof(double)*n, cudaMemcpyDeviceToHost);
for (int i = 0; i < n; ++i){
std::cout << h_a[i] << '\n';
}
// Release memory
cudaFree(d_a);
free(h_a);
} | .file "tmpxft_00149976_00000000-6_check.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z6findIDPdiPdi
.type _Z26__device_stub__Z6findIDPdiPdi, @function
_Z26__device_stub__Z6findIDPdiPdi:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6findIDPdi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z26__device_stub__Z6findIDPdiPdi, .-_Z26__device_stub__Z6findIDPdiPdi
.globl _Z6findIDPdi
.type _Z6findIDPdi, @function
_Z6findIDPdi:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6findIDPdiPdi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z6findIDPdi, .-_Z6findIDPdi
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $512, %edi
call malloc@PLT
movq %rax, %r13
leaq 8(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
movl $64, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L12:
movl $2, %ecx
movl $512, %edx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq %r13, %rbx
leaq 512(%r13), %r12
leaq _ZSt4cout(%rip), %rbp
jmp .L15
.L19:
movl $64, %esi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z6findIDPdiPdi
jmp .L12
.L13:
movl $10, %esi
call _ZNSo3putEc@PLT
.L14:
addq $8, %rbx
cmpq %r12, %rbx
je .L20
.L15:
movsd (%rbx), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movb $10, 28(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .L13
leaq 28(%rsp), %rsi
movl $1, %edx
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L14
.L20:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6findIDPdi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6findIDPdi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*------------check.cu------------------------------------------------------//
*
* Purpose: This is a simple cuda file for checking your gpu works
*
* It prints 0 -> 63
*
*-----------------------------------------------------------------------------*/
#include <iostream>
#include <math.h>
__global__ void findID(double *a, int n){
// First we need to find our global threadID
int id = blockIdx.x*blockDim.x + threadIdx.x;
// Make sure we are not out of range
if (id < n){
a[id] = id;
}
}
int main(){
// size of vectors
int n = 64;
// Host vectors
double *h_a;
// Device vectors
double *d_a;
// allocating space on host and device
h_a = (double*)malloc(sizeof(double)*n);
// Allocating space on GPU
cudaMalloc(&d_a, sizeof(double)*n);
// Creating blocks and grid ints
int threads, grid;
threads = 64;
grid = (int)ceil((float)n/threads);
findID<<<grid, threads>>>(d_a, n);
// Now to copy c back
cudaMemcpy(h_a, d_a, sizeof(double)*n, cudaMemcpyDeviceToHost);
for (int i = 0; i < n; ++i){
std::cout << h_a[i] << '\n';
}
// Release memory
cudaFree(d_a);
free(h_a);
} | /*------------check.cu------------------------------------------------------//
*
* Purpose: This is a simple cuda file for checking your gpu works
*
* It prints 0 -> 63
*
*-----------------------------------------------------------------------------*/
#include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
__global__ void findID(double *a, int n){
// First we need to find our global threadID
int id = blockIdx.x*blockDim.x + threadIdx.x;
// Make sure we are not out of range
if (id < n){
a[id] = id;
}
}
int main(){
// size of vectors
int n = 64;
// Host vectors
double *h_a;
// Device vectors
double *d_a;
// allocating space on host and device
h_a = (double*)malloc(sizeof(double)*n);
// Allocating space on GPU
hipMalloc(&d_a, sizeof(double)*n);
// Creating blocks and grid ints
int threads, grid;
threads = 64;
grid = (int)ceil((float)n/threads);
findID<<<grid, threads>>>(d_a, n);
// Now to copy c back
hipMemcpy(h_a, d_a, sizeof(double)*n, hipMemcpyDeviceToHost);
for (int i = 0; i < n; ++i){
std::cout << h_a[i] << '\n';
}
// Release memory
hipFree(d_a);
free(h_a);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*------------check.cu------------------------------------------------------//
*
* Purpose: This is a simple cuda file for checking your gpu works
*
* It prints 0 -> 63
*
*-----------------------------------------------------------------------------*/
#include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
__global__ void findID(double *a, int n){
// First we need to find our global threadID
int id = blockIdx.x*blockDim.x + threadIdx.x;
// Make sure we are not out of range
if (id < n){
a[id] = id;
}
}
int main(){
// size of vectors
int n = 64;
// Host vectors
double *h_a;
// Device vectors
double *d_a;
// allocating space on host and device
h_a = (double*)malloc(sizeof(double)*n);
// Allocating space on GPU
hipMalloc(&d_a, sizeof(double)*n);
// Creating blocks and grid ints
int threads, grid;
threads = 64;
grid = (int)ceil((float)n/threads);
findID<<<grid, threads>>>(d_a, n);
// Now to copy c back
hipMemcpy(h_a, d_a, sizeof(double)*n, hipMemcpyDeviceToHost);
for (int i = 0; i < n; ++i){
std::cout << h_a[i] << '\n';
}
// Release memory
hipFree(d_a);
free(h_a);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6findIDPdi
.globl _Z6findIDPdi
.p2align 8
.type _Z6findIDPdi,@function
_Z6findIDPdi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
v_cvt_f64_i32_e32 v[3:4], v1
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[3:4], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6findIDPdi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6findIDPdi, .Lfunc_end0-_Z6findIDPdi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6findIDPdi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6findIDPdi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*------------check.cu------------------------------------------------------//
*
* Purpose: This is a simple cuda file for checking your gpu works
*
* It prints 0 -> 63
*
*-----------------------------------------------------------------------------*/
#include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
__global__ void findID(double *a, int n){
// First we need to find our global threadID
int id = blockIdx.x*blockDim.x + threadIdx.x;
// Make sure we are not out of range
if (id < n){
a[id] = id;
}
}
int main(){
// size of vectors
int n = 64;
// Host vectors
double *h_a;
// Device vectors
double *d_a;
// allocating space on host and device
h_a = (double*)malloc(sizeof(double)*n);
// Allocating space on GPU
hipMalloc(&d_a, sizeof(double)*n);
// Creating blocks and grid ints
int threads, grid;
threads = 64;
grid = (int)ceil((float)n/threads);
findID<<<grid, threads>>>(d_a, n);
// Now to copy c back
hipMemcpy(h_a, d_a, sizeof(double)*n, hipMemcpyDeviceToHost);
for (int i = 0; i < n; ++i){
std::cout << h_a[i] << '\n';
}
// Release memory
hipFree(d_a);
free(h_a);
} | .text
.file "check.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__findIDPdi # -- Begin function _Z21__device_stub__findIDPdi
.p2align 4, 0x90
.type _Z21__device_stub__findIDPdi,@function
_Z21__device_stub__findIDPdi: # @_Z21__device_stub__findIDPdi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6findIDPdi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__findIDPdi, .Lfunc_end0-_Z21__device_stub__findIDPdi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $96, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $512, %edi # imm = 0x200
callq malloc
movq %rax, %rbx
movq %rsp, %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 63(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq (%rsp), %rax
movq %rax, 88(%rsp)
movl $64, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 16(%rsp)
leaq 12(%rsp), %rax
movq %rax, 24(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z6findIDPdi, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
movl $512, %edx # imm = 0x200
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r15d, %r15d
leaq 16(%rsp), %r14
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_3 Depth=1
movq %rax, %rdi
movl $10, %esi
callq _ZNSo3putEc
.LBB1_6: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
# in Loop: Header=BB1_3 Depth=1
incq %r15
cmpq $64, %r15
je .LBB1_7
.LBB1_3: # =>This Inner Loop Header: Depth=1
movsd (%rbx,%r15,8), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movb $10, 16(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB1_5
# %bb.4: # in Loop: Header=BB1_3 Depth=1
movl $1, %edx
movq %rax, %rdi
movq %r14, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_6
.LBB1_7:
movq (%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6findIDPdi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6findIDPdi,@object # @_Z6findIDPdi
.section .rodata,"a",@progbits
.globl _Z6findIDPdi
.p2align 3, 0x0
_Z6findIDPdi:
.quad _Z21__device_stub__findIDPdi
.size _Z6findIDPdi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6findIDPdi"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__findIDPdi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6findIDPdi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6findIDPdi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ I2F.F64 R4, R0 ; /* 0x0000000000047312 */
/* 0x000e220000201c00 */
/*0070*/ HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff037435 */
/* 0x000fe200000001ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0090*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*00a0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x001fe2000c101b04 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6findIDPdi
.globl _Z6findIDPdi
.p2align 8
.type _Z6findIDPdi,@function
_Z6findIDPdi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
v_cvt_f64_i32_e32 v[3:4], v1
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[3:4], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6findIDPdi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6findIDPdi, .Lfunc_end0-_Z6findIDPdi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6findIDPdi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6findIDPdi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00149976_00000000-6_check.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z6findIDPdiPdi
.type _Z26__device_stub__Z6findIDPdiPdi, @function
_Z26__device_stub__Z6findIDPdiPdi:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6findIDPdi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z26__device_stub__Z6findIDPdiPdi, .-_Z26__device_stub__Z6findIDPdiPdi
.globl _Z6findIDPdi
.type _Z6findIDPdi, @function
_Z6findIDPdi:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6findIDPdiPdi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z6findIDPdi, .-_Z6findIDPdi
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $512, %edi
call malloc@PLT
movq %rax, %r13
leaq 8(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
movl $64, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L12:
movl $2, %ecx
movl $512, %edx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq %r13, %rbx
leaq 512(%r13), %r12
leaq _ZSt4cout(%rip), %rbp
jmp .L15
.L19:
movl $64, %esi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z6findIDPdiPdi
jmp .L12
.L13:
movl $10, %esi
call _ZNSo3putEc@PLT
.L14:
addq $8, %rbx
cmpq %r12, %rbx
je .L20
.L15:
movsd (%rbx), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movb $10, 28(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .L13
leaq 28(%rsp), %rsi
movl $1, %edx
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L14
.L20:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6findIDPdi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6findIDPdi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "check.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__findIDPdi # -- Begin function _Z21__device_stub__findIDPdi
.p2align 4, 0x90
.type _Z21__device_stub__findIDPdi,@function
_Z21__device_stub__findIDPdi: # @_Z21__device_stub__findIDPdi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6findIDPdi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__findIDPdi, .Lfunc_end0-_Z21__device_stub__findIDPdi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $96, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $512, %edi # imm = 0x200
callq malloc
movq %rax, %rbx
movq %rsp, %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 63(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq (%rsp), %rax
movq %rax, 88(%rsp)
movl $64, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 16(%rsp)
leaq 12(%rsp), %rax
movq %rax, 24(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z6findIDPdi, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
movl $512, %edx # imm = 0x200
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r15d, %r15d
leaq 16(%rsp), %r14
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_3 Depth=1
movq %rax, %rdi
movl $10, %esi
callq _ZNSo3putEc
.LBB1_6: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
# in Loop: Header=BB1_3 Depth=1
incq %r15
cmpq $64, %r15
je .LBB1_7
.LBB1_3: # =>This Inner Loop Header: Depth=1
movsd (%rbx,%r15,8), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movb $10, 16(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB1_5
# %bb.4: # in Loop: Header=BB1_3 Depth=1
movl $1, %edx
movq %rax, %rdi
movq %r14, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_6
.LBB1_7:
movq (%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6findIDPdi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6findIDPdi,@object # @_Z6findIDPdi
.section .rodata,"a",@progbits
.globl _Z6findIDPdi
.p2align 3, 0x0
_Z6findIDPdi:
.quad _Z21__device_stub__findIDPdi
.size _Z6findIDPdi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6findIDPdi"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__findIDPdi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6findIDPdi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <stdio.h>
#include <cuda.h>
__global__ void myfirstkernel(void)
{
printf("First msg\n");
}
int main(void)
{
myfirstkernel <<< 1,1 >>>();
printf("Hello Cuda\n");
return 0;
} | code for sm_80
Function : _Z13myfirstkernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <stdio.h>
#include <cuda.h>
__global__ void myfirstkernel(void)
{
printf("First msg\n");
}
int main(void)
{
myfirstkernel <<< 1,1 >>>();
printf("Hello Cuda\n");
return 0;
} | .file "tmpxft_0007f506_00000000-6_hello.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z13myfirstkernelvv
.type _Z32__device_stub__Z13myfirstkernelvv, @function
_Z32__device_stub__Z13myfirstkernelvv:
.LFB3694:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z13myfirstkernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z32__device_stub__Z13myfirstkernelvv, .-_Z32__device_stub__Z13myfirstkernelvv
.globl _Z13myfirstkernelv
.type _Z13myfirstkernelv, @function
_Z13myfirstkernelv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z13myfirstkernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z13myfirstkernelv, .-_Z13myfirstkernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello Cuda\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z32__device_stub__Z13myfirstkernelvv
jmp .L12
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z13myfirstkernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z13myfirstkernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <stdio.h>
#include <cuda.h>
__global__ void myfirstkernel(void)
{
printf("First msg\n");
}
int main(void)
{
myfirstkernel <<< 1,1 >>>();
printf("Hello Cuda\n");
return 0;
} | #include <iostream>
#include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void myfirstkernel(void)
{
printf("First msg\n");
}
int main(void)
{
myfirstkernel <<< 1,1 >>>();
printf("Hello Cuda\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <iostream>
#include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void myfirstkernel(void)
{
printf("First msg\n");
}
int main(void)
{
myfirstkernel <<< 1,1 >>>();
printf("Hello Cuda\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13myfirstkernelv
.globl _Z13myfirstkernelv
.p2align 8
.type _Z13myfirstkernelv,@function
_Z13myfirstkernelv:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 11
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13myfirstkernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13myfirstkernelv, .Lfunc_end0-_Z13myfirstkernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "First msg\n"
.size .str, 11
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13myfirstkernelv
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z13myfirstkernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <iostream>
#include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void myfirstkernel(void)
{
printf("First msg\n");
}
int main(void)
{
myfirstkernel <<< 1,1 >>>();
printf("Hello Cuda\n");
return 0;
} | .text
.file "hello.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z28__device_stub__myfirstkernelv # -- Begin function _Z28__device_stub__myfirstkernelv
.p2align 4, 0x90
.type _Z28__device_stub__myfirstkernelv,@function
_Z28__device_stub__myfirstkernelv: # @_Z28__device_stub__myfirstkernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z13myfirstkernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z28__device_stub__myfirstkernelv, .Lfunc_end0-_Z28__device_stub__myfirstkernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z13myfirstkernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13myfirstkernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13myfirstkernelv,@object # @_Z13myfirstkernelv
.section .rodata,"a",@progbits
.globl _Z13myfirstkernelv
.p2align 3, 0x0
_Z13myfirstkernelv:
.quad _Z28__device_stub__myfirstkernelv
.size _Z13myfirstkernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13myfirstkernelv"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello Cuda"
.size .Lstr, 11
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__myfirstkernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13myfirstkernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13myfirstkernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13myfirstkernelv
.globl _Z13myfirstkernelv
.p2align 8
.type _Z13myfirstkernelv,@function
_Z13myfirstkernelv:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 11
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13myfirstkernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13myfirstkernelv, .Lfunc_end0-_Z13myfirstkernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "First msg\n"
.size .str, 11
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13myfirstkernelv
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z13myfirstkernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007f506_00000000-6_hello.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z13myfirstkernelvv
.type _Z32__device_stub__Z13myfirstkernelvv, @function
_Z32__device_stub__Z13myfirstkernelvv:
.LFB3694:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z13myfirstkernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z32__device_stub__Z13myfirstkernelvv, .-_Z32__device_stub__Z13myfirstkernelvv
.globl _Z13myfirstkernelv
.type _Z13myfirstkernelv, @function
_Z13myfirstkernelv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z13myfirstkernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z13myfirstkernelv, .-_Z13myfirstkernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello Cuda\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z32__device_stub__Z13myfirstkernelvv
jmp .L12
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z13myfirstkernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z13myfirstkernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hello.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z28__device_stub__myfirstkernelv # -- Begin function _Z28__device_stub__myfirstkernelv
.p2align 4, 0x90
.type _Z28__device_stub__myfirstkernelv,@function
_Z28__device_stub__myfirstkernelv: # @_Z28__device_stub__myfirstkernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z13myfirstkernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z28__device_stub__myfirstkernelv, .Lfunc_end0-_Z28__device_stub__myfirstkernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z13myfirstkernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13myfirstkernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13myfirstkernelv,@object # @_Z13myfirstkernelv
.section .rodata,"a",@progbits
.globl _Z13myfirstkernelv
.p2align 3, 0x0
_Z13myfirstkernelv:
.quad _Z28__device_stub__myfirstkernelv
.size _Z13myfirstkernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13myfirstkernelv"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello Cuda"
.size .Lstr, 11
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__myfirstkernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13myfirstkernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* Copyright (c) 2001-2018, The Ohio State University. All rights
* reserved.
*
* This file is part of the MVAPICH2 software package developed by the
* team members of The Ohio State University's Network-Based Computing
* Laboratory (NBCL), headed by Professor Dhabaleswar K. (DK) Panda.
*
* For detailed copyright and licensing information, please refer to the
* copyright file COPYRIGHT in the top level MVAPICH2 directory.
*
*/
#define MPI_ORDER_C 56
#define MPI_ORDER_FORTRAN 57
extern int rdma_cuda_vec_thread_blksz;
extern int rdma_cuda_vec_thread_ysz;
extern int rdma_cuda_subarr_thread_blksz;
extern int rdma_cuda_subarr_thread_xdim;
extern int rdma_cuda_subarr_thread_ydim;
extern int rdma_cuda_subarr_thread_zdim;
struct iovec
{
void *iov_base; /* Pointer to data. */
size_t iov_len; /* Length of data. */
};
__global__ void pack_subarray_c_double( double *dst, double *src, int nx, int ny, int nz, int sub_nx, int sub_ny, int sub_nz, int h_x, int h_y, int h_z)
{
//==============================================================================
// 2 Registers | 3 arguments
//==============================================================================
int i, j, k;
//==============================================================================
// Identify current thread
// Notice the +1 shift that is used in order to avoid ghost nodes
i = blockIdx.x * blockDim.x + threadIdx.x;
j = blockIdx.y * blockDim.y + threadIdx.y;
k = blockIdx.z * blockDim.z + threadIdx.z;
if ( (i < sub_nx) && (j < sub_ny) && (k < sub_nz) ) {
dst[ i * sub_ny * sub_nz + j * sub_nz + k ] = src[ (i + h_x) * ny * nz + (j + h_y) * nz + (k + h_z) ];
}
}
__global__ void unpack_subarray_c_double( double *dst, double *src, int nx, int ny, int nz, int sub_nx, int sub_ny, int sub_nz, int h_x, int h_y, int h_z)
{
//==============================================================================
// 2 Registers | 3 arguments
//==============================================================================
int i, j, k;
//==============================================================================
// Identify current thread
// Notice the +1 shift that is used in order to avoid ghost nodes
i = blockIdx.x * blockDim.x + threadIdx.x;
j = blockIdx.y * blockDim.y + threadIdx.y;
k = blockIdx.z * blockDim.z + threadIdx.z;
if ( (i < sub_nx) && (j < sub_ny) && (k < sub_nz) ) {
dst[ (i + h_x) * ny * nz + (j + h_y) * nz + (k + h_z) ] = src[ i * sub_ny * sub_nz + j * sub_nz + k ];
}
}
__global__ void pack_subarray_f_double( double *dst, double *src, int nx, int ny, int nz, int sub_nx, int sub_ny, int sub_nz, int h_x, int h_y, int h_z)
{
//==============================================================================
// 2 Registers | 3 arguments
//==============================================================================
int i, j, k;
//==============================================================================
// Identify current thread
// Notice the +1 shift that is used in order to avoid ghost nodes
i = blockIdx.x * blockDim.x + threadIdx.x;
j = blockIdx.y * blockDim.y + threadIdx.y;
k = blockIdx.z * blockDim.z + threadIdx.z;
if ( (i < sub_nx) && (j < sub_ny) && (k < sub_nz) ) {
dst[ i + sub_nx * j + sub_nx * sub_ny * k ] = src[ (i + h_x) + nx * (j + h_y) + nx * ny * (k + h_z) ];
}
}
__global__ void unpack_subarray_f_double( double *dst, double *src, int nx, int ny, int nz, int sub_nx, int sub_ny, int sub_nz, int h_x, int h_y, int h_z)
{
//==============================================================================
// 2 Registers | 3 arguments
//==============================================================================
int i, j, k;
//==============================================================================
// Identify current thread
// Notice the +1 shift that is used in order to avoid ghost nodes
i = blockIdx.x * blockDim.x + threadIdx.x;
j = blockIdx.y * blockDim.y + threadIdx.y;
k = blockIdx.z * blockDim.z + threadIdx.z;
if ( (i < sub_nx) && (j < sub_ny) && (k < sub_nz) ) {
dst[ (i + h_x) + nx * (j + h_y) + nx * ny * (k + h_z) ] = src[ i + sub_nx * j + sub_nx * sub_ny * k ];
}
}
__global__ void pack_subarray_c_float( float *dst, float *src, int nx, int ny, int nz, int sub_nx, int sub_ny, int sub_nz, int h_x, int h_y, int h_z)
{
//==============================================================================
// 2 Registers | 3 arguments
//==============================================================================
int i, j, k;
//==============================================================================
// Identify current thread
// Notice the +1 shift that is used in order to avoid ghost nodes
i = blockIdx.x * blockDim.x + threadIdx.x;
j = blockIdx.y * blockDim.y + threadIdx.y;
k = blockIdx.z * blockDim.z + threadIdx.z;
if ( (i < sub_nx) && (j < sub_ny) && (k < sub_nz) ) {
dst[ i * sub_ny * sub_nz + j * sub_nz + k ] = src[ (i + h_x) * ny * nz + (j + h_y) * nz + (k + h_z) ];
}
}
__global__ void unpack_subarray_c_float( float *dst, float *src, int nx, int ny, int nz, int sub_nx, int sub_ny, int sub_nz, int h_x, int h_y, int h_z)
{
//==============================================================================
// 2 Registers | 3 arguments
//==============================================================================
int i, j, k;
//==============================================================================
// Identify current thread
// Notice the +1 shift that is used in order to avoid ghost nodes
i = blockIdx.x * blockDim.x + threadIdx.x;
j = blockIdx.y * blockDim.y + threadIdx.y;
k = blockIdx.z * blockDim.z + threadIdx.z;
if ( (i < sub_nx) && (j < sub_ny) && (k < sub_nz) ) {
dst[ (i + h_x) * ny * nz + (j + h_y) * nz + (k + h_z) ] = src[ i * sub_ny * sub_nz + j * sub_nz + k ];
}
}
__global__ void pack_subarray_f_float( float *dst, float *src, int nx, int ny, int nz, int sub_nx, int sub_ny, int sub_nz, int h_x, int h_y, int h_z)
{
//==============================================================================
// 2 Registers | 3 arguments
//==============================================================================
int i, j, k;
//==============================================================================
// Identify current thread
// Notice the +1 shift that is used in order to avoid ghost nodes
i = blockIdx.x * blockDim.x + threadIdx.x;
j = blockIdx.y * blockDim.y + threadIdx.y;
k = blockIdx.z * blockDim.z + threadIdx.z;
if ( (i < sub_nx) && (j < sub_ny) && (k < sub_nz) ) {
dst[ i + sub_nx * j + sub_nx * sub_ny * k ] = src[ (i + h_x) + nx * (j + h_y) + nx * ny * (k + h_z) ];
}
}
__global__ void unpack_subarray_f_float( float *dst, float *src, int nx, int ny, int nz, int sub_nx, int sub_ny, int sub_nz, int h_x, int h_y, int h_z)
{
//==============================================================================
// 2 Registers | 3 arguments
//==============================================================================
int i, j, k;
//==============================================================================
// Identify current thread
// Notice the +1 shift that is used in order to avoid ghost nodes
i = blockIdx.x * blockDim.x + threadIdx.x;
j = blockIdx.y * blockDim.y + threadIdx.y;
k = blockIdx.z * blockDim.z + threadIdx.z;
if ( (i < sub_nx) && (j < sub_ny) && (k < sub_nz) ) {
dst[ (i + h_x) + nx * (j + h_y) + nx * ny * (k + h_z) ] = src[ i + sub_nx * j + sub_nx * sub_ny * k ];
}
}
__global__ void pack_subarray_c_char( char *dst, char *src, int nx, int ny, int nz, int sub_nx, int sub_ny, int sub_nz, int h_x, int h_y, int h_z)
{
//==============================================================================
// 2 Registers | 3 arguments
//==============================================================================
int i, j, k;
//==============================================================================
// Identify current thread
// Notice the +1 shift that is used in order to avoid ghost nodes
i = blockIdx.x * blockDim.x + threadIdx.x;
j = blockIdx.y * blockDim.y + threadIdx.y;
k = blockIdx.z * blockDim.z + threadIdx.z;
if ( (i < sub_nx) && (j < sub_ny) && (k < sub_nz) ) {
dst[ i * sub_ny * sub_nz + j * sub_nz + k ] = src[ (i + h_x) * ny * nz + (j + h_y) * nz + (k + h_z) ];
}
}
__global__ void unpack_subarray_c_char( char *dst, char *src, int nx, int ny, int nz, int sub_nx, int sub_ny, int sub_nz, int h_x, int h_y, int h_z)
{
//==============================================================================
// 2 Registers | 3 arguments
//==============================================================================
int i, j, k;
//==============================================================================
// Identify current thread
// Notice the +1 shift that is used in order to avoid ghost nodes
i = blockIdx.x * blockDim.x + threadIdx.x;
j = blockIdx.y * blockDim.y + threadIdx.y;
k = blockIdx.z * blockDim.z + threadIdx.z;
if ( (i < sub_nx) && (j < sub_ny) && (k < sub_nz) ) {
dst[ (i + h_x) * ny * nz + (j + h_y) * nz + (k + h_z) ] = src[ i * sub_ny * sub_nz + j * sub_nz + k ];
}
}
__global__ void pack_subarray_f_char( char *dst, char *src, int nx, int ny, int nz, int sub_nx, int sub_ny, int sub_nz, int h_x, int h_y, int h_z)
{
//==============================================================================
// 2 Registers | 3 arguments
//==============================================================================
int i, j, k;
//==============================================================================
// Identify current thread
// Notice the +1 shift that is used in order to avoid ghost nodes
i = blockIdx.x * blockDim.x + threadIdx.x;
j = blockIdx.y * blockDim.y + threadIdx.y;
k = blockIdx.z * blockDim.z + threadIdx.z;
if ( (i < sub_nx) && (j < sub_ny) && (k < sub_nz) ) {
dst[ i + sub_nx * j + sub_nx * sub_ny * k ] = src[ (i + h_x) + nx * (j + h_y) + nx * ny * (k + h_z) ];
}
}
__global__ void unpack_subarray_f_char( char *dst, char *src, int nx, int ny, int nz, int sub_nx, int sub_ny, int sub_nz, int h_x, int h_y, int h_z)
{
//==============================================================================
// 2 Registers | 3 arguments
//==============================================================================
int i, j, k;
//==============================================================================
// Identify current thread
// Notice the +1 shift that is used in order to avoid ghost nodes
i = blockIdx.x * blockDim.x + threadIdx.x;
j = blockIdx.y * blockDim.y + threadIdx.y;
k = blockIdx.z * blockDim.z + threadIdx.z;
if ( (i < sub_nx) && (j < sub_ny) && (k < sub_nz) ) {
dst[ (i + h_x) + nx * (j + h_y) + nx * ny * (k + h_z) ] = src[ i + sub_nx * j + sub_nx * sub_ny * k ];
}
}
extern "C" void pack_subarray( void *dst, void *src, int dim, int nx, int ny, int nz, int sub_nx, int sub_ny, int sub_nz, int h_x, int h_y, int h_z, int sub_order, int el_size, cudaStream_t stream)
{
int BLOCK_SIZE_X = 8;
int BLOCK_SIZE_Y = 8;
int BLOCK_SIZE_Z = 16;
int BLOCK_THREAD_SIZE = 1024;
if ( rdma_cuda_subarr_thread_xdim != 0 && !(rdma_cuda_subarr_thread_xdim & (rdma_cuda_subarr_thread_xdim-1)) ){
BLOCK_SIZE_X = rdma_cuda_subarr_thread_xdim;
}
if ( dim > 1 && rdma_cuda_subarr_thread_ydim != 0 && !(rdma_cuda_subarr_thread_ydim & (rdma_cuda_subarr_thread_ydim-1)) ){
BLOCK_SIZE_Y = rdma_cuda_subarr_thread_ydim;
}
if ( dim > 2 && rdma_cuda_subarr_thread_zdim != 0 && !(rdma_cuda_subarr_thread_zdim & (rdma_cuda_subarr_thread_zdim-1)) ){
BLOCK_SIZE_Z = rdma_cuda_subarr_thread_zdim;
}
if ( rdma_cuda_subarr_thread_blksz != 0 && !(rdma_cuda_subarr_thread_blksz & (rdma_cuda_subarr_thread_blksz-1)) ){
BLOCK_THREAD_SIZE = ( (rdma_cuda_subarr_thread_blksz < 1024) ? rdma_cuda_subarr_thread_blksz : 1024);
}
if ( 3 == dim && BLOCK_SIZE_X * BLOCK_SIZE_Y * BLOCK_SIZE_Z > BLOCK_THREAD_SIZE ){
BLOCK_SIZE_X = 8;
BLOCK_SIZE_Y = 8;
BLOCK_SIZE_Z = 16;
} else if ( 2 == dim && BLOCK_SIZE_X * BLOCK_SIZE_Y > BLOCK_THREAD_SIZE ){
BLOCK_SIZE_X = 16;
BLOCK_SIZE_Y = 32;
BLOCK_SIZE_Z = 1;
} else if ( 1 == dim ) {
BLOCK_SIZE_X = 256;
BLOCK_SIZE_Y = 4;
BLOCK_SIZE_Z = 1;
}
int GRID_SIZE_X = (sub_nx + BLOCK_SIZE_X - 1) / BLOCK_SIZE_X;
int GRID_SIZE_Y = (sub_ny + BLOCK_SIZE_Y - 1) / BLOCK_SIZE_Y;
int GRID_SIZE_Z = (sub_nz + BLOCK_SIZE_Z - 1) / BLOCK_SIZE_Z;
dim3 dimblock( BLOCK_SIZE_X, BLOCK_SIZE_Y, BLOCK_SIZE_Z );
dim3 dimgrid( GRID_SIZE_X, GRID_SIZE_Y, GRID_SIZE_Z );
if ( MPI_ORDER_C == sub_order ){
if (el_size == 4) {
pack_subarray_c_float<<<dimgrid, dimblock, 0, stream>>>((float *) dst, (float *) src, nx, ny, nz, sub_nx, sub_ny, sub_nz, h_x, h_y, h_z );
} else if (el_size == 1) {
pack_subarray_c_char<<<dimgrid, dimblock, 0, stream>>>((char *) dst, (char *) src, nx, ny, nz, sub_nx, sub_ny, sub_nz, h_x, h_y, h_z );
} else if (el_size == 8) {
pack_subarray_c_double<<<dimgrid, dimblock, 0, stream>>>((double *) dst, (double *) src, nx, ny, nz, sub_nx, sub_ny, sub_nz, h_x, h_y, h_z );
}
} else if ( MPI_ORDER_FORTRAN == sub_order ){
if (el_size == 4) {
pack_subarray_f_float<<<dimgrid, dimblock, 0, stream>>>((float *) dst, (float *) src, nx, ny, nz, sub_nx, sub_ny, sub_nz, h_x, h_y, h_z );
} else if (el_size == 1) {
pack_subarray_f_char<<<dimgrid, dimblock, 0, stream>>>((char *) dst, (char *) src, nx, ny, nz, sub_nx, sub_ny, sub_nz, h_x, h_y, h_z );
} else if (el_size == 8) {
pack_subarray_f_double<<<dimgrid, dimblock, 0, stream>>>((double *) dst, (double *) src, nx, ny, nz, sub_nx, sub_ny, sub_nz, h_x, h_y, h_z );
}
}
}
extern "C" void unpack_subarray( void *dst, void *src, int dim, int nx, int ny, int nz, int sub_nx, int sub_ny, int sub_nz, int h_x, int h_y, int h_z, int sub_order, int el_size, cudaStream_t stream)
{
int BLOCK_SIZE_X = 8;
int BLOCK_SIZE_Y = 8;
int BLOCK_SIZE_Z = 16;
int BLOCK_THREAD_SIZE = 1024;
if ( rdma_cuda_subarr_thread_xdim != 0 && !(rdma_cuda_subarr_thread_xdim & (rdma_cuda_subarr_thread_xdim-1)) ){
BLOCK_SIZE_X = rdma_cuda_subarr_thread_xdim;
}
if ( dim > 1 && rdma_cuda_subarr_thread_ydim != 0 && !(rdma_cuda_subarr_thread_ydim & (rdma_cuda_subarr_thread_ydim-1)) ){
BLOCK_SIZE_Y = rdma_cuda_subarr_thread_ydim;
}
if ( dim > 2 && rdma_cuda_subarr_thread_zdim != 0 && !(rdma_cuda_subarr_thread_zdim & (rdma_cuda_subarr_thread_zdim-1)) ){
BLOCK_SIZE_Z = rdma_cuda_subarr_thread_zdim;
}
if ( rdma_cuda_subarr_thread_blksz != 0 && !(rdma_cuda_subarr_thread_blksz & (rdma_cuda_subarr_thread_blksz-1)) ){
BLOCK_THREAD_SIZE = ( (rdma_cuda_subarr_thread_blksz < 1024) ? rdma_cuda_subarr_thread_blksz : 1024);
}
if ( 3 == dim && BLOCK_SIZE_X * BLOCK_SIZE_Y * BLOCK_SIZE_Z > BLOCK_THREAD_SIZE ){
BLOCK_SIZE_X = 8;
BLOCK_SIZE_Y = 8;
BLOCK_SIZE_Z = 16;
} else if ( 2 == dim && BLOCK_SIZE_X * BLOCK_SIZE_Y > BLOCK_THREAD_SIZE ){
BLOCK_SIZE_X = 16;
BLOCK_SIZE_Y = 32;
BLOCK_SIZE_Z = 1;
} else if ( 1 == dim ) {
BLOCK_SIZE_X = 256;
BLOCK_SIZE_Y = 4;
BLOCK_SIZE_Z = 1;
}
int GRID_SIZE_X = (sub_nx + BLOCK_SIZE_X - 1) / BLOCK_SIZE_X;
int GRID_SIZE_Y = (sub_ny + BLOCK_SIZE_Y - 1) / BLOCK_SIZE_Y;
int GRID_SIZE_Z = (sub_nz + BLOCK_SIZE_Z - 1) / BLOCK_SIZE_Z;
dim3 dimblock( BLOCK_SIZE_X, BLOCK_SIZE_Y, BLOCK_SIZE_Z );
dim3 dimgrid( GRID_SIZE_X, GRID_SIZE_Y, GRID_SIZE_Z );
if ( MPI_ORDER_C == sub_order ){
if (el_size == 4) {
unpack_subarray_c_float<<<dimgrid, dimblock, 0, stream>>>((float *) dst, (float *) src, nx, ny, nz, sub_nx, sub_ny, sub_nz, h_x, h_y, h_z );
} else if (el_size == 1) {
unpack_subarray_c_char<<<dimgrid, dimblock, 0, stream>>>((char *) dst, (char *) src, nx, ny, nz, sub_nx, sub_ny, sub_nz, h_x, h_y, h_z );
} else if (el_size == 8) {
unpack_subarray_c_double<<<dimgrid, dimblock, 0, stream>>>((double *) dst, (double *) src, nx, ny, nz, sub_nx, sub_ny, sub_nz, h_x, h_y, h_z );
}
} else if ( MPI_ORDER_FORTRAN == sub_order ){
if (el_size == 4) {
unpack_subarray_f_float<<<dimgrid, dimblock, 0, stream>>>((float *) dst, (float *) src, nx, ny, nz, sub_nx, sub_ny, sub_nz, h_x, h_y, h_z );
} else if (el_size == 1) {
unpack_subarray_f_char<<<dimgrid, dimblock, 0, stream>>>((char *) dst, (char *) src, nx, ny, nz, sub_nx, sub_ny, sub_nz, h_x, h_y, h_z );
} else if (el_size == 8) {
unpack_subarray_f_double<<<dimgrid, dimblock, 0, stream>>>((double *) dst, (double *) src, nx, ny, nz, sub_nx, sub_ny, sub_nz, h_x, h_y, h_z );
}
}
}
__global__ void pack_unpack_vector_double( double *dst, int dpitch, double *src, int spitch, int width, int height)
{
//==============================================================================
// 2 Registers | 2 arguments
//==============================================================================
int i, j;
//==============================================================================
i = blockIdx.x * blockDim.x + threadIdx.x;
j = blockIdx.y * blockDim.y + threadIdx.y;
if ( i < height && j < width ) {
dst[i * dpitch + j] = src[i * spitch + j];
}
}
__global__ void pack_unpack_vector_float( float *dst, int dpitch, float *src, int spitch, int width, int height)
{
//==============================================================================
// 2 Registers | 2 arguments
//==============================================================================
int i, j;
//==============================================================================
i = blockIdx.x * blockDim.x + threadIdx.x;
j = blockIdx.y * blockDim.y + threadIdx.y;
if ( i < height && j < width ) {
dst[i * dpitch + j] = src[i * spitch + j];
}
}
__global__ void pack_unpack_vector_char( char *dst, int dpitch, char *src, int spitch, int width, int height)
{
//==============================================================================
// 2 Registers | 2 arguments
//==============================================================================
int i, j;
//==============================================================================
i = blockIdx.x * blockDim.x + threadIdx.x;
j = blockIdx.y * blockDim.y + threadIdx.y;
if (i < height && j < width ) {
dst[i * dpitch + j] = src[i * spitch + j];
}
}
extern "C" void pack_unpack_vector_kernel( void *dst, int dpitch, void *src, int spitch, int width, int height, cudaStream_t stream)
{
int BLOCK_SIZE_Y, BLOCK_THREAD_SIZE;
int dtsize;
int elems;
if ((0 == (width % sizeof(double))) && (0 == (dpitch % sizeof(double))) && (0 == (spitch % sizeof(double)))) {
dtsize = sizeof(double);
} else if ((0 == (width % sizeof(float))) && (0 == (dpitch % sizeof(float))) && (0 == (spitch % sizeof(float)))) {
dtsize = sizeof(float);
} else {
dtsize = sizeof(char);
}
elems = width / dtsize;
if ( rdma_cuda_vec_thread_ysz != 0 && !(rdma_cuda_vec_thread_ysz & (rdma_cuda_vec_thread_ysz-1)) ){
BLOCK_SIZE_Y = rdma_cuda_vec_thread_ysz;
}else{
switch ( elems ){
case 1:
BLOCK_SIZE_Y = 1;
break;
case 2:
BLOCK_SIZE_Y = 2;
break;
case 3: case 4:
BLOCK_SIZE_Y = 4;
break;
case 5: case 6: case 7: case 8:
BLOCK_SIZE_Y = 8;
break;
case 9: case 10: case 11: case 12: case 13: case 14: case 15: case 16:
BLOCK_SIZE_Y = 16;
break;
default:
BLOCK_SIZE_Y = 32;
break;
}
}
if ( rdma_cuda_vec_thread_blksz != 0 && !(rdma_cuda_vec_thread_blksz & (rdma_cuda_vec_thread_blksz-1)) ){
BLOCK_THREAD_SIZE = ( (rdma_cuda_vec_thread_blksz < 1024) ? rdma_cuda_vec_thread_blksz : 1024);
}
else{
BLOCK_THREAD_SIZE = 1024;
}
int BLOCK_SIZE_X = BLOCK_THREAD_SIZE / BLOCK_SIZE_Y;
int GRID_SIZE_X = (height + BLOCK_SIZE_X - 1) / BLOCK_SIZE_X;
int GRID_SIZE_Y = (elems + BLOCK_SIZE_Y - 1) / BLOCK_SIZE_Y;
dim3 dimblock( BLOCK_SIZE_X, BLOCK_SIZE_Y, 1);
dim3 dimgrid( GRID_SIZE_X, GRID_SIZE_Y, 1);
if ((0 == (width % sizeof(double))) && (0 == (dpitch % sizeof(double))) && (0 == (spitch % sizeof(double)))) {
pack_unpack_vector_double<<<dimgrid, dimblock, 0, stream>>>((double *) dst, dpitch / sizeof(double),
(double *) src, spitch / sizeof(double), width / sizeof(double), height);
} else if ((0 == (width % sizeof(float))) && (0 == (dpitch % sizeof(float))) && (0 == (spitch % sizeof(float)))) {
pack_unpack_vector_float<<<dimgrid, dimblock, 0, stream>>>((float *) dst, dpitch / sizeof(float),
(float *) src, spitch / sizeof(float), width / sizeof(float), height);
} else if ((0 == (width % sizeof(char))) && (0 == (dpitch % sizeof(char))) && (0 == (spitch % sizeof(char)))) {
pack_unpack_vector_char<<<dimgrid, dimblock, 0, stream>>>((char *) dst, dpitch / sizeof(char),
(char *) src, spitch / sizeof(char), width / sizeof(char), height);
}
} | #include <hip/hip_runtime.h>
/* Copyright (c) 2001-2018, The Ohio State University. All rights
* reserved.
*
* This file is part of the MVAPICH2 software package developed by the
* team members of The Ohio State University's Network-Based Computing
* Laboratory (NBCL), headed by Professor Dhabaleswar K. (DK) Panda.
*
* For detailed copyright and licensing information, please refer to the
* copyright file COPYRIGHT in the top level MVAPICH2 directory.
*
*/
#define MPI_ORDER_C 56
#define MPI_ORDER_FORTRAN 57
extern int rdma_cuda_vec_thread_blksz;
extern int rdma_cuda_vec_thread_ysz;
extern int rdma_cuda_subarr_thread_blksz;
extern int rdma_cuda_subarr_thread_xdim;
extern int rdma_cuda_subarr_thread_ydim;
extern int rdma_cuda_subarr_thread_zdim;
struct iovec
{
void *iov_base; /* Pointer to data. */
size_t iov_len; /* Length of data. */
};
__global__ void pack_subarray_c_double( double *dst, double *src, int nx, int ny, int nz, int sub_nx, int sub_ny, int sub_nz, int h_x, int h_y, int h_z)
{
//==============================================================================
// 2 Registers | 3 arguments
//==============================================================================
int i, j, k;
//==============================================================================
// Identify current thread
// Notice the +1 shift that is used in order to avoid ghost nodes
i = blockIdx.x * blockDim.x + threadIdx.x;
j = blockIdx.y * blockDim.y + threadIdx.y;
k = blockIdx.z * blockDim.z + threadIdx.z;
if ( (i < sub_nx) && (j < sub_ny) && (k < sub_nz) ) {
dst[ i * sub_ny * sub_nz + j * sub_nz + k ] = src[ (i + h_x) * ny * nz + (j + h_y) * nz + (k + h_z) ];
}
}
__global__ void unpack_subarray_c_double( double *dst, double *src, int nx, int ny, int nz, int sub_nx, int sub_ny, int sub_nz, int h_x, int h_y, int h_z)
{
//==============================================================================
// 2 Registers | 3 arguments
//==============================================================================
int i, j, k;
//==============================================================================
// Identify current thread
// Notice the +1 shift that is used in order to avoid ghost nodes
i = blockIdx.x * blockDim.x + threadIdx.x;
j = blockIdx.y * blockDim.y + threadIdx.y;
k = blockIdx.z * blockDim.z + threadIdx.z;
if ( (i < sub_nx) && (j < sub_ny) && (k < sub_nz) ) {
dst[ (i + h_x) * ny * nz + (j + h_y) * nz + (k + h_z) ] = src[ i * sub_ny * sub_nz + j * sub_nz + k ];
}
}
__global__ void pack_subarray_f_double( double *dst, double *src, int nx, int ny, int nz, int sub_nx, int sub_ny, int sub_nz, int h_x, int h_y, int h_z)
{
//==============================================================================
// 2 Registers | 3 arguments
//==============================================================================
int i, j, k;
//==============================================================================
// Identify current thread
// Notice the +1 shift that is used in order to avoid ghost nodes
i = blockIdx.x * blockDim.x + threadIdx.x;
j = blockIdx.y * blockDim.y + threadIdx.y;
k = blockIdx.z * blockDim.z + threadIdx.z;
if ( (i < sub_nx) && (j < sub_ny) && (k < sub_nz) ) {
dst[ i + sub_nx * j + sub_nx * sub_ny * k ] = src[ (i + h_x) + nx * (j + h_y) + nx * ny * (k + h_z) ];
}
}
__global__ void unpack_subarray_f_double( double *dst, double *src, int nx, int ny, int nz, int sub_nx, int sub_ny, int sub_nz, int h_x, int h_y, int h_z)
{
//==============================================================================
// 2 Registers | 3 arguments
//==============================================================================
int i, j, k;
//==============================================================================
// Identify current thread
// Notice the +1 shift that is used in order to avoid ghost nodes
i = blockIdx.x * blockDim.x + threadIdx.x;
j = blockIdx.y * blockDim.y + threadIdx.y;
k = blockIdx.z * blockDim.z + threadIdx.z;
if ( (i < sub_nx) && (j < sub_ny) && (k < sub_nz) ) {
dst[ (i + h_x) + nx * (j + h_y) + nx * ny * (k + h_z) ] = src[ i + sub_nx * j + sub_nx * sub_ny * k ];
}
}
__global__ void pack_subarray_c_float( float *dst, float *src, int nx, int ny, int nz, int sub_nx, int sub_ny, int sub_nz, int h_x, int h_y, int h_z)
{
//==============================================================================
// 2 Registers | 3 arguments
//==============================================================================
int i, j, k;
//==============================================================================
// Identify current thread
// Notice the +1 shift that is used in order to avoid ghost nodes
i = blockIdx.x * blockDim.x + threadIdx.x;
j = blockIdx.y * blockDim.y + threadIdx.y;
k = blockIdx.z * blockDim.z + threadIdx.z;
if ( (i < sub_nx) && (j < sub_ny) && (k < sub_nz) ) {
dst[ i * sub_ny * sub_nz + j * sub_nz + k ] = src[ (i + h_x) * ny * nz + (j + h_y) * nz + (k + h_z) ];
}
}
__global__ void unpack_subarray_c_float( float *dst, float *src, int nx, int ny, int nz, int sub_nx, int sub_ny, int sub_nz, int h_x, int h_y, int h_z)
{
//==============================================================================
// 2 Registers | 3 arguments
//==============================================================================
int i, j, k;
//==============================================================================
// Identify current thread
// Notice the +1 shift that is used in order to avoid ghost nodes
i = blockIdx.x * blockDim.x + threadIdx.x;
j = blockIdx.y * blockDim.y + threadIdx.y;
k = blockIdx.z * blockDim.z + threadIdx.z;
if ( (i < sub_nx) && (j < sub_ny) && (k < sub_nz) ) {
dst[ (i + h_x) * ny * nz + (j + h_y) * nz + (k + h_z) ] = src[ i * sub_ny * sub_nz + j * sub_nz + k ];
}
}
__global__ void pack_subarray_f_float( float *dst, float *src, int nx, int ny, int nz, int sub_nx, int sub_ny, int sub_nz, int h_x, int h_y, int h_z)
{
//==============================================================================
// 2 Registers | 3 arguments
//==============================================================================
int i, j, k;
//==============================================================================
// Identify current thread
// Notice the +1 shift that is used in order to avoid ghost nodes
i = blockIdx.x * blockDim.x + threadIdx.x;
j = blockIdx.y * blockDim.y + threadIdx.y;
k = blockIdx.z * blockDim.z + threadIdx.z;
if ( (i < sub_nx) && (j < sub_ny) && (k < sub_nz) ) {
dst[ i + sub_nx * j + sub_nx * sub_ny * k ] = src[ (i + h_x) + nx * (j + h_y) + nx * ny * (k + h_z) ];
}
}
__global__ void unpack_subarray_f_float( float *dst, float *src, int nx, int ny, int nz, int sub_nx, int sub_ny, int sub_nz, int h_x, int h_y, int h_z)
{
//==============================================================================
// 2 Registers | 3 arguments
//==============================================================================
int i, j, k;
//==============================================================================
// Identify current thread
// Notice the +1 shift that is used in order to avoid ghost nodes
i = blockIdx.x * blockDim.x + threadIdx.x;
j = blockIdx.y * blockDim.y + threadIdx.y;
k = blockIdx.z * blockDim.z + threadIdx.z;
if ( (i < sub_nx) && (j < sub_ny) && (k < sub_nz) ) {
dst[ (i + h_x) + nx * (j + h_y) + nx * ny * (k + h_z) ] = src[ i + sub_nx * j + sub_nx * sub_ny * k ];
}
}
__global__ void pack_subarray_c_char( char *dst, char *src, int nx, int ny, int nz, int sub_nx, int sub_ny, int sub_nz, int h_x, int h_y, int h_z)
{
//==============================================================================
// 2 Registers | 3 arguments
//==============================================================================
int i, j, k;
//==============================================================================
// Identify current thread
// Notice the +1 shift that is used in order to avoid ghost nodes
i = blockIdx.x * blockDim.x + threadIdx.x;
j = blockIdx.y * blockDim.y + threadIdx.y;
k = blockIdx.z * blockDim.z + threadIdx.z;
if ( (i < sub_nx) && (j < sub_ny) && (k < sub_nz) ) {
dst[ i * sub_ny * sub_nz + j * sub_nz + k ] = src[ (i + h_x) * ny * nz + (j + h_y) * nz + (k + h_z) ];
}
}
__global__ void unpack_subarray_c_char( char *dst, char *src, int nx, int ny, int nz, int sub_nx, int sub_ny, int sub_nz, int h_x, int h_y, int h_z)
{
//==============================================================================
// 2 Registers | 3 arguments
//==============================================================================
int i, j, k;
//==============================================================================
// Identify current thread
// Notice the +1 shift that is used in order to avoid ghost nodes
i = blockIdx.x * blockDim.x + threadIdx.x;
j = blockIdx.y * blockDim.y + threadIdx.y;
k = blockIdx.z * blockDim.z + threadIdx.z;
if ( (i < sub_nx) && (j < sub_ny) && (k < sub_nz) ) {
dst[ (i + h_x) * ny * nz + (j + h_y) * nz + (k + h_z) ] = src[ i * sub_ny * sub_nz + j * sub_nz + k ];
}
}
__global__ void pack_subarray_f_char( char *dst, char *src, int nx, int ny, int nz, int sub_nx, int sub_ny, int sub_nz, int h_x, int h_y, int h_z)
{
//==============================================================================
// 2 Registers | 3 arguments
//==============================================================================
int i, j, k;
//==============================================================================
// Identify current thread
// Notice the +1 shift that is used in order to avoid ghost nodes
i = blockIdx.x * blockDim.x + threadIdx.x;
j = blockIdx.y * blockDim.y + threadIdx.y;
k = blockIdx.z * blockDim.z + threadIdx.z;
if ( (i < sub_nx) && (j < sub_ny) && (k < sub_nz) ) {
dst[ i + sub_nx * j + sub_nx * sub_ny * k ] = src[ (i + h_x) + nx * (j + h_y) + nx * ny * (k + h_z) ];
}
}
__global__ void unpack_subarray_f_char( char *dst, char *src, int nx, int ny, int nz, int sub_nx, int sub_ny, int sub_nz, int h_x, int h_y, int h_z)
{
//==============================================================================
// 2 Registers | 3 arguments
//==============================================================================
int i, j, k;
//==============================================================================
// Identify current thread
// Notice the +1 shift that is used in order to avoid ghost nodes
i = blockIdx.x * blockDim.x + threadIdx.x;
j = blockIdx.y * blockDim.y + threadIdx.y;
k = blockIdx.z * blockDim.z + threadIdx.z;
if ( (i < sub_nx) && (j < sub_ny) && (k < sub_nz) ) {
dst[ (i + h_x) + nx * (j + h_y) + nx * ny * (k + h_z) ] = src[ i + sub_nx * j + sub_nx * sub_ny * k ];
}
}
extern "C" void pack_subarray( void *dst, void *src, int dim, int nx, int ny, int nz, int sub_nx, int sub_ny, int sub_nz, int h_x, int h_y, int h_z, int sub_order, int el_size, hipStream_t stream)
{
int BLOCK_SIZE_X = 8;
int BLOCK_SIZE_Y = 8;
int BLOCK_SIZE_Z = 16;
int BLOCK_THREAD_SIZE = 1024;
if ( rdma_cuda_subarr_thread_xdim != 0 && !(rdma_cuda_subarr_thread_xdim & (rdma_cuda_subarr_thread_xdim-1)) ){
BLOCK_SIZE_X = rdma_cuda_subarr_thread_xdim;
}
if ( dim > 1 && rdma_cuda_subarr_thread_ydim != 0 && !(rdma_cuda_subarr_thread_ydim & (rdma_cuda_subarr_thread_ydim-1)) ){
BLOCK_SIZE_Y = rdma_cuda_subarr_thread_ydim;
}
if ( dim > 2 && rdma_cuda_subarr_thread_zdim != 0 && !(rdma_cuda_subarr_thread_zdim & (rdma_cuda_subarr_thread_zdim-1)) ){
BLOCK_SIZE_Z = rdma_cuda_subarr_thread_zdim;
}
if ( rdma_cuda_subarr_thread_blksz != 0 && !(rdma_cuda_subarr_thread_blksz & (rdma_cuda_subarr_thread_blksz-1)) ){
BLOCK_THREAD_SIZE = ( (rdma_cuda_subarr_thread_blksz < 1024) ? rdma_cuda_subarr_thread_blksz : 1024);
}
if ( 3 == dim && BLOCK_SIZE_X * BLOCK_SIZE_Y * BLOCK_SIZE_Z > BLOCK_THREAD_SIZE ){
BLOCK_SIZE_X = 8;
BLOCK_SIZE_Y = 8;
BLOCK_SIZE_Z = 16;
} else if ( 2 == dim && BLOCK_SIZE_X * BLOCK_SIZE_Y > BLOCK_THREAD_SIZE ){
BLOCK_SIZE_X = 16;
BLOCK_SIZE_Y = 32;
BLOCK_SIZE_Z = 1;
} else if ( 1 == dim ) {
BLOCK_SIZE_X = 256;
BLOCK_SIZE_Y = 4;
BLOCK_SIZE_Z = 1;
}
int GRID_SIZE_X = (sub_nx + BLOCK_SIZE_X - 1) / BLOCK_SIZE_X;
int GRID_SIZE_Y = (sub_ny + BLOCK_SIZE_Y - 1) / BLOCK_SIZE_Y;
int GRID_SIZE_Z = (sub_nz + BLOCK_SIZE_Z - 1) / BLOCK_SIZE_Z;
dim3 dimblock( BLOCK_SIZE_X, BLOCK_SIZE_Y, BLOCK_SIZE_Z );
dim3 dimgrid( GRID_SIZE_X, GRID_SIZE_Y, GRID_SIZE_Z );
if ( MPI_ORDER_C == sub_order ){
if (el_size == 4) {
pack_subarray_c_float<<<dimgrid, dimblock, 0, stream>>>((float *) dst, (float *) src, nx, ny, nz, sub_nx, sub_ny, sub_nz, h_x, h_y, h_z );
} else if (el_size == 1) {
pack_subarray_c_char<<<dimgrid, dimblock, 0, stream>>>((char *) dst, (char *) src, nx, ny, nz, sub_nx, sub_ny, sub_nz, h_x, h_y, h_z );
} else if (el_size == 8) {
pack_subarray_c_double<<<dimgrid, dimblock, 0, stream>>>((double *) dst, (double *) src, nx, ny, nz, sub_nx, sub_ny, sub_nz, h_x, h_y, h_z );
}
} else if ( MPI_ORDER_FORTRAN == sub_order ){
if (el_size == 4) {
pack_subarray_f_float<<<dimgrid, dimblock, 0, stream>>>((float *) dst, (float *) src, nx, ny, nz, sub_nx, sub_ny, sub_nz, h_x, h_y, h_z );
} else if (el_size == 1) {
pack_subarray_f_char<<<dimgrid, dimblock, 0, stream>>>((char *) dst, (char *) src, nx, ny, nz, sub_nx, sub_ny, sub_nz, h_x, h_y, h_z );
} else if (el_size == 8) {
pack_subarray_f_double<<<dimgrid, dimblock, 0, stream>>>((double *) dst, (double *) src, nx, ny, nz, sub_nx, sub_ny, sub_nz, h_x, h_y, h_z );
}
}
}
extern "C" void unpack_subarray( void *dst, void *src, int dim, int nx, int ny, int nz, int sub_nx, int sub_ny, int sub_nz, int h_x, int h_y, int h_z, int sub_order, int el_size, hipStream_t stream)
{
int BLOCK_SIZE_X = 8;
int BLOCK_SIZE_Y = 8;
int BLOCK_SIZE_Z = 16;
int BLOCK_THREAD_SIZE = 1024;
if ( rdma_cuda_subarr_thread_xdim != 0 && !(rdma_cuda_subarr_thread_xdim & (rdma_cuda_subarr_thread_xdim-1)) ){
BLOCK_SIZE_X = rdma_cuda_subarr_thread_xdim;
}
if ( dim > 1 && rdma_cuda_subarr_thread_ydim != 0 && !(rdma_cuda_subarr_thread_ydim & (rdma_cuda_subarr_thread_ydim-1)) ){
BLOCK_SIZE_Y = rdma_cuda_subarr_thread_ydim;
}
if ( dim > 2 && rdma_cuda_subarr_thread_zdim != 0 && !(rdma_cuda_subarr_thread_zdim & (rdma_cuda_subarr_thread_zdim-1)) ){
BLOCK_SIZE_Z = rdma_cuda_subarr_thread_zdim;
}
if ( rdma_cuda_subarr_thread_blksz != 0 && !(rdma_cuda_subarr_thread_blksz & (rdma_cuda_subarr_thread_blksz-1)) ){
BLOCK_THREAD_SIZE = ( (rdma_cuda_subarr_thread_blksz < 1024) ? rdma_cuda_subarr_thread_blksz : 1024);
}
if ( 3 == dim && BLOCK_SIZE_X * BLOCK_SIZE_Y * BLOCK_SIZE_Z > BLOCK_THREAD_SIZE ){
BLOCK_SIZE_X = 8;
BLOCK_SIZE_Y = 8;
BLOCK_SIZE_Z = 16;
} else if ( 2 == dim && BLOCK_SIZE_X * BLOCK_SIZE_Y > BLOCK_THREAD_SIZE ){
BLOCK_SIZE_X = 16;
BLOCK_SIZE_Y = 32;
BLOCK_SIZE_Z = 1;
} else if ( 1 == dim ) {
BLOCK_SIZE_X = 256;
BLOCK_SIZE_Y = 4;
BLOCK_SIZE_Z = 1;
}
int GRID_SIZE_X = (sub_nx + BLOCK_SIZE_X - 1) / BLOCK_SIZE_X;
int GRID_SIZE_Y = (sub_ny + BLOCK_SIZE_Y - 1) / BLOCK_SIZE_Y;
int GRID_SIZE_Z = (sub_nz + BLOCK_SIZE_Z - 1) / BLOCK_SIZE_Z;
dim3 dimblock( BLOCK_SIZE_X, BLOCK_SIZE_Y, BLOCK_SIZE_Z );
dim3 dimgrid( GRID_SIZE_X, GRID_SIZE_Y, GRID_SIZE_Z );
if ( MPI_ORDER_C == sub_order ){
if (el_size == 4) {
unpack_subarray_c_float<<<dimgrid, dimblock, 0, stream>>>((float *) dst, (float *) src, nx, ny, nz, sub_nx, sub_ny, sub_nz, h_x, h_y, h_z );
} else if (el_size == 1) {
unpack_subarray_c_char<<<dimgrid, dimblock, 0, stream>>>((char *) dst, (char *) src, nx, ny, nz, sub_nx, sub_ny, sub_nz, h_x, h_y, h_z );
} else if (el_size == 8) {
unpack_subarray_c_double<<<dimgrid, dimblock, 0, stream>>>((double *) dst, (double *) src, nx, ny, nz, sub_nx, sub_ny, sub_nz, h_x, h_y, h_z );
}
} else if ( MPI_ORDER_FORTRAN == sub_order ){
if (el_size == 4) {
unpack_subarray_f_float<<<dimgrid, dimblock, 0, stream>>>((float *) dst, (float *) src, nx, ny, nz, sub_nx, sub_ny, sub_nz, h_x, h_y, h_z );
} else if (el_size == 1) {
unpack_subarray_f_char<<<dimgrid, dimblock, 0, stream>>>((char *) dst, (char *) src, nx, ny, nz, sub_nx, sub_ny, sub_nz, h_x, h_y, h_z );
} else if (el_size == 8) {
unpack_subarray_f_double<<<dimgrid, dimblock, 0, stream>>>((double *) dst, (double *) src, nx, ny, nz, sub_nx, sub_ny, sub_nz, h_x, h_y, h_z );
}
}
}
__global__ void pack_unpack_vector_double( double *dst, int dpitch, double *src, int spitch, int width, int height)
{
//==============================================================================
// 2 Registers | 2 arguments
//==============================================================================
int i, j;
//==============================================================================
i = blockIdx.x * blockDim.x + threadIdx.x;
j = blockIdx.y * blockDim.y + threadIdx.y;
if ( i < height && j < width ) {
dst[i * dpitch + j] = src[i * spitch + j];
}
}
__global__ void pack_unpack_vector_float( float *dst, int dpitch, float *src, int spitch, int width, int height)
{
//==============================================================================
// 2 Registers | 2 arguments
//==============================================================================
int i, j;
//==============================================================================
i = blockIdx.x * blockDim.x + threadIdx.x;
j = blockIdx.y * blockDim.y + threadIdx.y;
if ( i < height && j < width ) {
dst[i * dpitch + j] = src[i * spitch + j];
}
}
__global__ void pack_unpack_vector_char( char *dst, int dpitch, char *src, int spitch, int width, int height)
{
//==============================================================================
// 2 Registers | 2 arguments
//==============================================================================
int i, j;
//==============================================================================
i = blockIdx.x * blockDim.x + threadIdx.x;
j = blockIdx.y * blockDim.y + threadIdx.y;
if (i < height && j < width ) {
dst[i * dpitch + j] = src[i * spitch + j];
}
}
extern "C" void pack_unpack_vector_kernel( void *dst, int dpitch, void *src, int spitch, int width, int height, hipStream_t stream)
{
int BLOCK_SIZE_Y, BLOCK_THREAD_SIZE;
int dtsize;
int elems;
if ((0 == (width % sizeof(double))) && (0 == (dpitch % sizeof(double))) && (0 == (spitch % sizeof(double)))) {
dtsize = sizeof(double);
} else if ((0 == (width % sizeof(float))) && (0 == (dpitch % sizeof(float))) && (0 == (spitch % sizeof(float)))) {
dtsize = sizeof(float);
} else {
dtsize = sizeof(char);
}
elems = width / dtsize;
if ( rdma_cuda_vec_thread_ysz != 0 && !(rdma_cuda_vec_thread_ysz & (rdma_cuda_vec_thread_ysz-1)) ){
BLOCK_SIZE_Y = rdma_cuda_vec_thread_ysz;
}else{
switch ( elems ){
case 1:
BLOCK_SIZE_Y = 1;
break;
case 2:
BLOCK_SIZE_Y = 2;
break;
case 3: case 4:
BLOCK_SIZE_Y = 4;
break;
case 5: case 6: case 7: case 8:
BLOCK_SIZE_Y = 8;
break;
case 9: case 10: case 11: case 12: case 13: case 14: case 15: case 16:
BLOCK_SIZE_Y = 16;
break;
default:
BLOCK_SIZE_Y = 32;
break;
}
}
if ( rdma_cuda_vec_thread_blksz != 0 && !(rdma_cuda_vec_thread_blksz & (rdma_cuda_vec_thread_blksz-1)) ){
BLOCK_THREAD_SIZE = ( (rdma_cuda_vec_thread_blksz < 1024) ? rdma_cuda_vec_thread_blksz : 1024);
}
else{
BLOCK_THREAD_SIZE = 1024;
}
int BLOCK_SIZE_X = BLOCK_THREAD_SIZE / BLOCK_SIZE_Y;
int GRID_SIZE_X = (height + BLOCK_SIZE_X - 1) / BLOCK_SIZE_X;
int GRID_SIZE_Y = (elems + BLOCK_SIZE_Y - 1) / BLOCK_SIZE_Y;
dim3 dimblock( BLOCK_SIZE_X, BLOCK_SIZE_Y, 1);
dim3 dimgrid( GRID_SIZE_X, GRID_SIZE_Y, 1);
if ((0 == (width % sizeof(double))) && (0 == (dpitch % sizeof(double))) && (0 == (spitch % sizeof(double)))) {
pack_unpack_vector_double<<<dimgrid, dimblock, 0, stream>>>((double *) dst, dpitch / sizeof(double),
(double *) src, spitch / sizeof(double), width / sizeof(double), height);
} else if ((0 == (width % sizeof(float))) && (0 == (dpitch % sizeof(float))) && (0 == (spitch % sizeof(float)))) {
pack_unpack_vector_float<<<dimgrid, dimblock, 0, stream>>>((float *) dst, dpitch / sizeof(float),
(float *) src, spitch / sizeof(float), width / sizeof(float), height);
} else if ((0 == (width % sizeof(char))) && (0 == (dpitch % sizeof(char))) && (0 == (spitch % sizeof(char)))) {
pack_unpack_vector_char<<<dimgrid, dimblock, 0, stream>>>((char *) dst, dpitch / sizeof(char),
(char *) src, spitch / sizeof(char), width / sizeof(char), height);
}
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include "cuda_runtime.h"
#define M 8
#define N 12
extern __shared__ int shared[];
__global__ void func(int*data, int m,int n){
int * t_s = shared;
// __shared__ int t_s[12];
if(threadIdx.x==0){
memcpy(t_s + blockIdx.x*n,data + blockIdx.x*n,sizeof(int)*n);
}
__syncthreads();
data[blockIdx.x*n + threadIdx.x] =
t_s[blockIdx.x*n + threadIdx.x+1];
}
int main(){
int h_d[M*N];
int *d_d;
for(int i=0;i<M*N;i++)
h_d[i]=i+1;
for(int i=0;i<M;i++){
for(int j=0;j<N;j++)
printf("%2d ",h_d[i*N+j]);
printf("\n");
}
printf("\n");
cudaMalloc((void**)&d_d,sizeof(int)*M*N);
cudaMemcpy(d_d,h_d,sizeof(int)*M*N,cudaMemcpyHostToDevice);
func<<<M,N-1,sizeof(int)*M*N>>>(d_d,M,N);
cudaThreadSynchronize();
memset(h_d,0,sizeof(int)*M*N);
cudaMemcpy(h_d,d_d,sizeof(int)*M*N,cudaMemcpyDeviceToHost);
for(int i=0;i<M;i++){
for(int j=0;j<N;j++)
printf("%2d ",h_d[i*N+j]);
printf("\n");
}
printf("\n");
return 0;
} | code for sm_80
Function : _Z4funcPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x16c], PT ; /* 0x00005b00ff007a0c */
/* 0x000fe20003f05270 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ BSSY B0, 0x4e0 ; /* 0x0000049000007945 */
/* 0x000fe20003800000 */
/*0050*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e620000002500 */
/*0060*/ ISETP.NE.OR P0, PT, R0, RZ, !P0 ; /* 0x000000ff0000720c */
/* 0x001fe20004705670 */
/*0070*/ IMAD R9, R9, c[0x0][0x16c], RZ ; /* 0x00005b0009097a24 */
/* 0x002fd800078e02ff */
/*0080*/ @P0 BRA 0x4d0 ; /* 0x0000044000000947 */
/* 0x000fea0003800000 */
/*0090*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe400078e00ff */
/*00b0*/ IMAD.WIDE R2, R4, c[0x0][0x16c], RZ ; /* 0x00005b0004027a25 */
/* 0x000fc800078e02ff */
/*00c0*/ IMAD.WIDE.U32 R4, R9, R4, c[0x0][0x160] ; /* 0x0000580009047625 */
/* 0x000fe200078e0004 */
/*00d0*/ ISETP.GT.U32.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fc60003f04070 */
/*00e0*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e00ff */
/*00f0*/ ISETP.GT.U32.AND.EX P0, PT, R3, RZ, PT, P0 ; /* 0x000000ff0300720c */
/* 0x000fda0003f04100 */
/*0100*/ @!P0 IADD3 R12, P1, R4, R7, RZ ; /* 0x00000007040c8210 */
/* 0x000fca0007f3e0ff */
/*0110*/ @!P0 IMAD.X R13, R5, 0x1, R11, P1 ; /* 0x00000001050d8824 */
/* 0x000fca00008e060b */
/*0120*/ @!P0 LDG.E.U8 R12, [R12.64] ; /* 0x000000040c0c8981 */
/* 0x000ea2000c1e1100 */
/*0130*/ IMAD.SHL.U32 R6, R9, 0x4, RZ ; /* 0x0000000409067824 */
/* 0x000fe400078e00ff */
/*0140*/ @!P0 IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b8224 */
/* 0x000fe400078e00ff */
/*0150*/ @!P0 IMAD.IADD R15, R6, 0x1, R7 ; /* 0x00000001060f8824 */
/* 0x000fe400078e0207 */
/*0160*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff078424 */
/* 0x000fca00078e00ff */
/*0170*/ IADD3 R8, P3, R2.reuse, -R7.reuse, RZ ; /* 0x8000000702087210 */
/* 0x0c0fe40007f7e0ff */
/*0180*/ ISETP.GT.U32.AND P2, PT, R2, R7, PT ; /* 0x000000070200720c */
/* 0x000fe40003f44070 */
/*0190*/ ISETP.LE.U32.AND P1, PT, R8, 0x3, PT ; /* 0x000000030800780c */
/* 0x000fe20003f23070 */
/*01a0*/ IMAD.X R8, R3.reuse, 0x1, ~R11, P3 ; /* 0x0000000103087824 */
/* 0x040fe200018e0e0b */
/*01b0*/ ISETP.GT.U32.AND.EX P2, PT, R3, R11, PT, P2 ; /* 0x0000000b0300720c */
/* 0x000fc80003f44120 */
/*01c0*/ ISETP.LE.U32.OR.EX P1, PT, R8, RZ, !P2, P1 ; /* 0x000000ff0800720c */
/* 0x000fe20005723510 */
/*01d0*/ @!P0 STS.U8 [R15], R12 ; /* 0x0000000c0f008388 */
/* 0x0041d80000000000 */
/*01e0*/ @P1 BRA 0x350 ; /* 0x0000016000001947 */
/* 0x000fea0003800000 */
/*01f0*/ IADD3 R16, P1, R2, -0x3, RZ ; /* 0xfffffffd02107810 */
/* 0x000fe40007f3e0ff */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ IADD3.X R18, R3, -0x1, RZ, P1, !PT ; /* 0xffffffff03127810 */
/* 0x000fe40000ffe4ff */
/*0220*/ IADD3 R12, P1, R4, R7, RZ ; /* 0x00000007040c7210 */
/* 0x001fca0007f3e0ff */
/*0230*/ IMAD.X R13, R5, 0x1, R11, P1 ; /* 0x00000001050d7824 */
/* 0x000fca00008e060b */
/*0240*/ LDG.E.U8 R8, [R12.64] ; /* 0x000000040c087981 */
/* 0x000ea8000c1e1100 */
/*0250*/ LDG.E.U8 R10, [R12.64+0x1] ; /* 0x000001040c0a7981 */
/* 0x000ee8000c1e1100 */
/*0260*/ LDG.E.U8 R14, [R12.64+0x2] ; /* 0x000002040c0e7981 */
/* 0x000f28000c1e1100 */
/*0270*/ LDG.E.U8 R15, [R12.64+0x3] ; /* 0x000003040c0f7981 */
/* 0x000f62000c1e1100 */
/*0280*/ IMAD.IADD R21, R6.reuse, 0x1, R7.reuse ; /* 0x0000000106157824 */
/* 0x140fe200078e0207 */
/*0290*/ IADD3 R19, R6, 0x1, R7 ; /* 0x0000000106137810 */
/* 0x000fc40007ffe007 */
/*02a0*/ IADD3 R17, R6.reuse, 0x2, R7.reuse ; /* 0x0000000206117810 */
/* 0x140fe40007ffe007 */
/*02b0*/ IADD3 R20, R6, 0x3, R7 ; /* 0x0000000306147810 */
/* 0x000fe40007ffe007 */
/*02c0*/ IADD3 R7, P1, R7, 0x4, RZ ; /* 0x0000000407077810 */
/* 0x000fca0007f3e0ff */
/*02d0*/ IMAD.X R11, RZ, RZ, R11, P1 ; /* 0x000000ffff0b7224 */
/* 0x000fe200008e060b */
/*02e0*/ ISETP.GE.U32.AND P1, PT, R7, R16, PT ; /* 0x000000100700720c */
/* 0x000fc80003f26070 */
/*02f0*/ ISETP.GE.U32.AND.EX P1, PT, R11, R18, PT, P1 ; /* 0x000000120b00720c */
/* 0x000fe20003f26110 */
/*0300*/ STS.U8 [R21], R8 ; /* 0x0000000815007388 */
/* 0x0041e80000000000 */
/*0310*/ STS.U8 [R19], R10 ; /* 0x0000000a13007388 */
/* 0x0081e80000000000 */
/*0320*/ STS.U8 [R17], R14 ; /* 0x0000000e11007388 */
/* 0x0101e80000000000 */
/*0330*/ STS.U8 [R20], R15 ; /* 0x0000000f14007388 */
/* 0x0201e20000000000 */
/*0340*/ @!P1 BRA 0x220 ; /* 0xfffffed000009947 */
/* 0x000fea000383ffff */
/*0350*/ IADD3 R8, P3, R2.reuse, -R7.reuse, RZ ; /* 0x8000000702087210 */
/* 0x0c1fe40007f7e0ff */
/*0360*/ ISETP.GT.U32.AND P2, PT, R2, R7, PT ; /* 0x000000070200720c */
/* 0x000fc40003f44070 */
/*0370*/ ISETP.LE.U32.AND P1, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fe20003f23070 */
/*0380*/ IMAD.X R8, R3.reuse, 0x1, ~R11, P3 ; /* 0x0000000103087824 */
/* 0x040fe200018e0e0b */
/*0390*/ ISETP.GT.U32.AND.EX P2, PT, R3, R11, PT, P2 ; /* 0x0000000b0300720c */
/* 0x000fc80003f44120 */
/*03a0*/ ISETP.LE.U32.OR.EX P1, PT, R8, RZ, !P2, P1 ; /* 0x000000ff0800720c */
/* 0x000fda0005723510 */
/*03b0*/ @!P1 PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000981c */
/* 0x000fe20003f0e170 */
/*03c0*/ @!P1 IMAD.IADD R15, R6, 0x1, R7.reuse ; /* 0x00000001060f9824 */
/* 0x100fe200078e0207 */
/*03d0*/ @!P1 IADD3 R12, P3, R4, R7, RZ ; /* 0x00000007040c9210 */
/* 0x000fe40007f7e0ff */
/*03e0*/ @!P1 IADD3 R8, R6, 0x1, R7 ; /* 0x0000000106089810 */
/* 0x000fe40007ffe007 */
/*03f0*/ @!P1 IADD3 R7, P2, R7, 0x2, RZ ; /* 0x0000000207079810 */
/* 0x000fe20007f5e0ff */
/*0400*/ @!P1 IMAD.X R13, R5, 0x1, R11, P3 ; /* 0x00000001050d9824 */
/* 0x000fc800018e060b */
/*0410*/ @!P1 IMAD.X R11, RZ, RZ, R11, P2 ; /* 0x000000ffff0b9224 */
/* 0x000fe200010e060b */
/*0420*/ ISETP.LT.U32.AND P2, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x000fc80003f41070 */
/*0430*/ ISETP.LT.U32.OR.EX P0, PT, R11, R3, P0, P2 ; /* 0x000000030b00720c */
/* 0x000fda0000701520 */
/*0440*/ @P0 IADD3 R2, P2, R4, R7, RZ ; /* 0x0000000704020210 */
/* 0x000fe40007f5e0ff */
/*0450*/ @!P1 LDG.E.U8 R4, [R12.64] ; /* 0x000000040c049981 */
/* 0x000ea6000c1e1100 */
/*0460*/ @P0 IMAD.X R3, R5, 0x1, R11, P2 ; /* 0x0000000105030824 */
/* 0x000fe400010e060b */
/*0470*/ @!P1 LDG.E.U8 R5, [R12.64+0x1] ; /* 0x000001040c059981 */
/* 0x000ee8000c1e1100 */
/*0480*/ @P0 LDG.E.U8 R2, [R2.64] ; /* 0x0000000402020981 */
/* 0x000f22000c1e1100 */
/*0490*/ @P0 IMAD.IADD R7, R6, 0x1, R7 ; /* 0x0000000106070824 */
/* 0x000fc600078e0207 */
/*04a0*/ @!P1 STS.U8 [R15], R4 ; /* 0x000000040f009388 */
/* 0x0041e80000000000 */
/*04b0*/ @!P1 STS.U8 [R8], R5 ; /* 0x0000000508009388 */
/* 0x0081e80000000000 */
/*04c0*/ @P0 STS.U8 [R7], R2 ; /* 0x0000000207000388 */
/* 0x0101e40000000000 */
/*04d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*04f0*/ IMAD.IADD R0, R9, 0x1, R0 ; /* 0x0000000109007824 */
/* 0x000fe400078e0200 */
/*0500*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0510*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x001fe200078e0003 */
/*0520*/ LDS R5, [R0.X4+0x4] ; /* 0x0000040000057984 */
/* 0x000e280000004800 */
/*0530*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0540*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0550*/ BRA 0x550; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include "cuda_runtime.h"
#define M 8
#define N 12
extern __shared__ int shared[];
__global__ void func(int*data, int m,int n){
int * t_s = shared;
// __shared__ int t_s[12];
if(threadIdx.x==0){
memcpy(t_s + blockIdx.x*n,data + blockIdx.x*n,sizeof(int)*n);
}
__syncthreads();
data[blockIdx.x*n + threadIdx.x] =
t_s[blockIdx.x*n + threadIdx.x+1];
}
int main(){
int h_d[M*N];
int *d_d;
for(int i=0;i<M*N;i++)
h_d[i]=i+1;
for(int i=0;i<M;i++){
for(int j=0;j<N;j++)
printf("%2d ",h_d[i*N+j]);
printf("\n");
}
printf("\n");
cudaMalloc((void**)&d_d,sizeof(int)*M*N);
cudaMemcpy(d_d,h_d,sizeof(int)*M*N,cudaMemcpyHostToDevice);
func<<<M,N-1,sizeof(int)*M*N>>>(d_d,M,N);
cudaThreadSynchronize();
memset(h_d,0,sizeof(int)*M*N);
cudaMemcpy(h_d,d_d,sizeof(int)*M*N,cudaMemcpyDeviceToHost);
for(int i=0;i<M;i++){
for(int j=0;j<N;j++)
printf("%2d ",h_d[i*N+j]);
printf("\n");
}
printf("\n");
return 0;
} | .file "tmpxft_000e94e6_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z4funcPiiiPiii
.type _Z25__device_stub__Z4funcPiiiPiii, @function
_Z25__device_stub__Z4funcPiiiPiii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4funcPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z25__device_stub__Z4funcPiiiPiii, .-_Z25__device_stub__Z4funcPiiiPiii
.globl _Z4funcPiii
.type _Z4funcPiii, @function
_Z4funcPiii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z4funcPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z4funcPiii, .-_Z4funcPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%2d "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $440, %rsp
.cfi_def_cfa_offset 496
movq %fs:40, %rax
movq %rax, 424(%rsp)
xorl %eax, %eax
movl $1, %eax
.L12:
movl %eax, 28(%rsp,%rax,4)
addq $1, %rax
cmpq $97, %rax
jne .L12
leaq 80(%rsp), %rbp
leaq 464(%rsp), %r13
movq %rbp, %r12
leaq .LC0(%rip), %r14
leaq .LC1(%rip), %r15
.L13:
leaq -48(%r12), %rbx
.L14:
movl (%rbx), %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L14
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $48, %r12
cmpq %r13, %r12
jne .L13
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rsp, %rdi
movl $384, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $384, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $11, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $8, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $384, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L16:
call cudaThreadSynchronize@PLT
leaq 32(%rsp), %r8
movl $48, %ecx
movl $0, %eax
movq %r8, %rdi
rep stosq
movl $2, %ecx
movl $384, %edx
movq (%rsp), %rsi
movq %r8, %rdi
call cudaMemcpy@PLT
leaq .LC0(%rip), %r12
leaq .LC1(%rip), %r14
.L17:
leaq -48(%rbp), %rbx
.L18:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L18
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $48, %rbp
cmpq %r13, %rbp
jne .L17
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 424(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $440, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movl $12, %edx
movl $8, %esi
movq (%rsp), %rdi
call _Z25__device_stub__Z4funcPiiiPiii
jmp .L16
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z4funcPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z4funcPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include "cuda_runtime.h"
#define M 8
#define N 12
extern __shared__ int shared[];
__global__ void func(int*data, int m,int n){
int * t_s = shared;
// __shared__ int t_s[12];
if(threadIdx.x==0){
memcpy(t_s + blockIdx.x*n,data + blockIdx.x*n,sizeof(int)*n);
}
__syncthreads();
data[blockIdx.x*n + threadIdx.x] =
t_s[blockIdx.x*n + threadIdx.x+1];
}
int main(){
int h_d[M*N];
int *d_d;
for(int i=0;i<M*N;i++)
h_d[i]=i+1;
for(int i=0;i<M;i++){
for(int j=0;j<N;j++)
printf("%2d ",h_d[i*N+j]);
printf("\n");
}
printf("\n");
cudaMalloc((void**)&d_d,sizeof(int)*M*N);
cudaMemcpy(d_d,h_d,sizeof(int)*M*N,cudaMemcpyHostToDevice);
func<<<M,N-1,sizeof(int)*M*N>>>(d_d,M,N);
cudaThreadSynchronize();
memset(h_d,0,sizeof(int)*M*N);
cudaMemcpy(h_d,d_d,sizeof(int)*M*N,cudaMemcpyDeviceToHost);
for(int i=0;i<M;i++){
for(int j=0;j<N;j++)
printf("%2d ",h_d[i*N+j]);
printf("\n");
}
printf("\n");
return 0;
} | #include <stdio.h>
#include "hip/hip_runtime.h"
#define M 8
#define N 12
extern __shared__ int shared[];
__global__ void func(int*data, int m,int n){
int * t_s = shared;
// __shared__ int t_s[12];
if(threadIdx.x==0){
memcpy(t_s + blockIdx.x*n,data + blockIdx.x*n,sizeof(int)*n);
}
__syncthreads();
data[blockIdx.x*n + threadIdx.x] =
t_s[blockIdx.x*n + threadIdx.x+1];
}
int main(){
int h_d[M*N];
int *d_d;
for(int i=0;i<M*N;i++)
h_d[i]=i+1;
for(int i=0;i<M;i++){
for(int j=0;j<N;j++)
printf("%2d ",h_d[i*N+j]);
printf("\n");
}
printf("\n");
hipMalloc((void**)&d_d,sizeof(int)*M*N);
hipMemcpy(d_d,h_d,sizeof(int)*M*N,hipMemcpyHostToDevice);
func<<<M,N-1,sizeof(int)*M*N>>>(d_d,M,N);
hipDeviceSynchronize();
memset(h_d,0,sizeof(int)*M*N);
hipMemcpy(h_d,d_d,sizeof(int)*M*N,hipMemcpyDeviceToHost);
for(int i=0;i<M;i++){
for(int j=0;j<N;j++)
printf("%2d ",h_d[i*N+j]);
printf("\n");
}
printf("\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include "hip/hip_runtime.h"
#define M 8
#define N 12
extern __shared__ int shared[];
__global__ void func(int*data, int m,int n){
int * t_s = shared;
// __shared__ int t_s[12];
if(threadIdx.x==0){
memcpy(t_s + blockIdx.x*n,data + blockIdx.x*n,sizeof(int)*n);
}
__syncthreads();
data[blockIdx.x*n + threadIdx.x] =
t_s[blockIdx.x*n + threadIdx.x+1];
}
int main(){
int h_d[M*N];
int *d_d;
for(int i=0;i<M*N;i++)
h_d[i]=i+1;
for(int i=0;i<M;i++){
for(int j=0;j<N;j++)
printf("%2d ",h_d[i*N+j]);
printf("\n");
}
printf("\n");
hipMalloc((void**)&d_d,sizeof(int)*M*N);
hipMemcpy(d_d,h_d,sizeof(int)*M*N,hipMemcpyHostToDevice);
func<<<M,N-1,sizeof(int)*M*N>>>(d_d,M,N);
hipDeviceSynchronize();
memset(h_d,0,sizeof(int)*M*N);
hipMemcpy(h_d,d_d,sizeof(int)*M*N,hipMemcpyDeviceToHost);
for(int i=0;i<M;i++){
for(int j=0;j<N;j++)
printf("%2d ",h_d[i*N+j]);
printf("\n");
}
printf("\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4funcPiii
.globl _Z4funcPiii
.p2align 8
.type _Z4funcPiii,@function
_Z4funcPiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0xc
s_load_b64 s[0:1], s[0:1], 0x0
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_mov_b32 s7, 0
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s2, 0
s_cselect_b32 s3, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, vcc_lo, s3
s_and_saveexec_b32 s8, s3
s_cbranch_execz .LBB0_3
s_mul_i32 s6, s15, s2
s_ashr_i32 s3, s2, 31
s_lshl_b64 s[4:5], s[6:7], 2
v_mov_b32_e32 v1, 0
s_add_u32 s4, s0, s4
s_addc_u32 s5, s1, s5
s_lshl_b32 s9, s6, 2
s_lshl_b64 s[6:7], s[2:3], 2
s_add_i32 s3, s9, 0
s_sub_u32 s6, 0, s6
s_subb_u32 s7, 0, s7
.p2align 6
.LBB0_2:
s_clause 0x3
global_load_u8 v2, v1, s[4:5]
global_load_u8 v3, v1, s[4:5] offset:1
global_load_u8 v4, v1, s[4:5] offset:2
global_load_u8 v5, v1, s[4:5] offset:3
s_add_u32 s4, s4, 4
v_mov_b32_e32 v6, s3
s_addc_u32 s5, s5, 0
s_add_i32 s3, s3, 4
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_waitcnt vmcnt(3)
ds_store_b8 v6, v2
s_waitcnt vmcnt(2)
ds_store_b8 v6, v3 offset:1
s_waitcnt vmcnt(1)
ds_store_b8 v6, v4 offset:2
s_waitcnt vmcnt(0)
ds_store_b8 v6, v5 offset:3
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s8
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_mov_b32_e32 v2, 0
v_lshl_add_u32 v0, v1, 2, 0
ds_load_b32 v3, v0 offset:4
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4funcPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4funcPiii, .Lfunc_end0-_Z4funcPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4funcPiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4funcPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include "hip/hip_runtime.h"
#define M 8
#define N 12
extern __shared__ int shared[];
__global__ void func(int*data, int m,int n){
int * t_s = shared;
// __shared__ int t_s[12];
if(threadIdx.x==0){
memcpy(t_s + blockIdx.x*n,data + blockIdx.x*n,sizeof(int)*n);
}
__syncthreads();
data[blockIdx.x*n + threadIdx.x] =
t_s[blockIdx.x*n + threadIdx.x+1];
}
int main(){
int h_d[M*N];
int *d_d;
for(int i=0;i<M*N;i++)
h_d[i]=i+1;
for(int i=0;i<M;i++){
for(int j=0;j<N;j++)
printf("%2d ",h_d[i*N+j]);
printf("\n");
}
printf("\n");
hipMalloc((void**)&d_d,sizeof(int)*M*N);
hipMemcpy(d_d,h_d,sizeof(int)*M*N,hipMemcpyHostToDevice);
func<<<M,N-1,sizeof(int)*M*N>>>(d_d,M,N);
hipDeviceSynchronize();
memset(h_d,0,sizeof(int)*M*N);
hipMemcpy(h_d,d_d,sizeof(int)*M*N,hipMemcpyDeviceToHost);
for(int i=0;i<M;i++){
for(int j=0;j<N;j++)
printf("%2d ",h_d[i*N+j]);
printf("\n");
}
printf("\n");
return 0;
} | .text
.file "main.hip"
.globl _Z19__device_stub__funcPiii # -- Begin function _Z19__device_stub__funcPiii
.p2align 4, 0x90
.type _Z19__device_stub__funcPiii,@function
_Z19__device_stub__funcPiii: # @_Z19__device_stub__funcPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4funcPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z19__device_stub__funcPiii, .Lfunc_end0-_Z19__device_stub__funcPiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $496, %rsp # imm = 0x1F0
.cfi_def_cfa_offset 528
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq 1(%rax), %rcx
movl %ecx, 112(%rsp,%rax,4)
movq %rcx, %rax
cmpq $96, %rcx
jne .LBB1_1
# %bb.2: # %.preheader29.preheader
leaq 112(%rsp), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_3: # %.preheader29
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_3 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%r15,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $12, %r15
jne .LBB1_4
# %bb.5: # in Loop: Header=BB1_3 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq $48, %rbx
cmpq $8, %r14
jne .LBB1_3
# %bb.6:
movl $10, %edi
callq putchar@PLT
leaq 8(%rsp), %rdi
movl $384, %esi # imm = 0x180
callq hipMalloc
movq 8(%rsp), %rdi
leaq 112(%rsp), %rbx
movl $384, %edx # imm = 0x180
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967304, %rdi # imm = 0x100000008
leaq 3(%rdi), %rdx
movl $384, %r8d # imm = 0x180
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $8, 20(%rsp)
movl $12, 16(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4funcPiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
callq hipDeviceSynchronize
movl $384, %edx # imm = 0x180
movq %rbx, %rdi
xorl %esi, %esi
callq memset@PLT
movq 8(%rsp), %rsi
movl $384, %edx # imm = 0x180
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_9: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_10 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_10: # Parent Loop BB1_9 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%r15,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $12, %r15
jne .LBB1_10
# %bb.11: # in Loop: Header=BB1_9 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq $48, %rbx
cmpq $8, %r14
jne .LBB1_9
# %bb.12:
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $496, %rsp # imm = 0x1F0
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4funcPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4funcPiii,@object # @_Z4funcPiii
.section .rodata,"a",@progbits
.globl _Z4funcPiii
.p2align 3, 0x0
_Z4funcPiii:
.quad _Z19__device_stub__funcPiii
.size _Z4funcPiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%2d "
.size .L.str, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4funcPiii"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__funcPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4funcPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.