system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
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You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
constexpr int LEN_INITAL = 8;
constexpr int STEPS = 6;
constexpr int LEN_W = 1 + 2 * STEPS;
constexpr int LEN_Z = LEN_W;
constexpr int LEN_Y = LEN_INITAL + 2 * STEPS;
constexpr int LEN_X = LEN_INITAL + 2 * STEPS;
constexpr int LEN_TOTAL = LEN_W * LEN_Z * LEN_Y * LEN_X;
constexpr int SIZE_W = LEN_Z * LEN_Y * LEN_X;
constexpr int SIZE_Z = LEN_Y * LEN_X;
constexpr int SIZE_Y = LEN_X;
constexpr int NUM_THREADS = 512;
constexpr int NUM_BLOCKS = LEN_TOTAL / NUM_THREADS;
inline int coord_to_idx(const int w, const int z, const int y, const int x) {
return
w * SIZE_W +
z * SIZE_Z +
y * SIZE_Y +
x;
}
inline void print_slice(const int* grid, const int w, const int z) {
for (int row = 0; row < LEN_Y; ++row) {
for (int col = 0; col < LEN_X; ++col) {
std::cout << grid[coord_to_idx(w, z, row, col)] << " ";
}
std::cout << "\n";
}
}
__device__
int coord_to_idx_dev(const int w, const int z, const int y, const int x) {
return w * SIZE_W + z * SIZE_Z + y * SIZE_Y + x;
}
__global__
void step(const int* grid, int* grid_next) {
// Find out where we are.
const int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < LEN_TOTAL) {
int left = idx;
int w = idx / SIZE_W;
left = idx - w * SIZE_W;
int z = left / SIZE_Z;
left = left - z * SIZE_Z;
int y = left / SIZE_Y;
int x = left - y * SIZE_Y;
// TODO: for loop here?
const int active = grid[idx];
// Count active neighbors.
int active_neighbors = 0;
int min_nw = max(0, w - 1);
int max_nw = min(LEN_W, w + 2);
int min_nz = max(0, z - 1);
int max_nz = min(LEN_Z, z + 2);
int min_ny = max(0, y - 1);
int max_ny = min(LEN_Y, y + 2);
int min_nx = max(0, x - 1);
int max_nx = min(LEN_X, x + 2);
for (int nw = min_nw; nw < max_nw; ++nw) {
for (int nz = min_nz; nz < max_nz; ++nz) {
for (int ny = min_ny; ny < max_ny; ++ny) {
for (int nx = min_nx; nx < max_nx; ++nx) {
active_neighbors += grid[coord_to_idx_dev(nw, nz, ny, nx)];
}
}
}
}
active_neighbors -= active;
// Rules
int active_next = active;
if (active == 1 && (active_neighbors < 2 || active_neighbors > 3)) {
active_next = 0;
}
else if (active == 0 && active_neighbors == 3) {
active_next = 1;
}
//active_next = idx;
grid_next[idx] = active_next;
}
}
int main() {
// Initialize grid.
int* grid;
cudaMallocManaged(&grid, LEN_TOTAL * sizeof(int));
cudaMemset(grid, 0, LEN_TOTAL);
int initial_grid[LEN_INITAL][LEN_INITAL] = {
{1, 1, 0, 0, 1, 0, 1, 0},
{1, 1, 1, 0, 1, 0, 1, 1},
{0, 0, 1, 1, 1, 0, 0, 1},
{0, 1, 0, 0, 0, 0, 1, 1},
{0, 1, 0, 0, 1, 1, 1, 1},
{1, 1, 1, 1, 1, 0, 0, 0},
{1, 1, 1, 1, 1, 1, 1, 0},
{1, 0, 1, 1, 0, 1, 0, 1}
};
for (int row = 0; row < LEN_INITAL; ++row) {
for (int col = 0; col < LEN_INITAL; ++col) {
grid[coord_to_idx(STEPS, STEPS, STEPS + row, STEPS + col)] = initial_grid[row][col];
}
}
//print_slice(grid, STEPS, STEPS);
int* grid_next;
cudaMallocManaged(&grid_next, LEN_TOTAL * sizeof(int));
for (int i = 0; i < STEPS; ++i) {
//std::cout << "Step " << i << "\n";
step<<<NUM_BLOCKS, NUM_THREADS>>>(grid, grid_next);
cudaDeviceSynchronize();
std::swap(grid, grid_next);
//print_slice(grid, STEPS, STEPS);
}
// Count actives.
int count = 0;
for (int i = 0; i < LEN_TOTAL; ++i) {
count += grid[i];
}
std::cout << "Active: " << count << "\n";
cudaFree(grid);
cudaFree(grid_next);
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
constexpr int LEN_INITAL = 8;
constexpr int STEPS = 6;
constexpr int LEN_W = 1 + 2 * STEPS;
constexpr int LEN_Z = LEN_W;
constexpr int LEN_Y = LEN_INITAL + 2 * STEPS;
constexpr int LEN_X = LEN_INITAL + 2 * STEPS;
constexpr int LEN_TOTAL = LEN_W * LEN_Z * LEN_Y * LEN_X;
constexpr int SIZE_W = LEN_Z * LEN_Y * LEN_X;
constexpr int SIZE_Z = LEN_Y * LEN_X;
constexpr int SIZE_Y = LEN_X;
constexpr int NUM_THREADS = 512;
constexpr int NUM_BLOCKS = LEN_TOTAL / NUM_THREADS;
inline int coord_to_idx(const int w, const int z, const int y, const int x) {
return
w * SIZE_W +
z * SIZE_Z +
y * SIZE_Y +
x;
}
inline void print_slice(const int* grid, const int w, const int z) {
for (int row = 0; row < LEN_Y; ++row) {
for (int col = 0; col < LEN_X; ++col) {
std::cout << grid[coord_to_idx(w, z, row, col)] << " ";
}
std::cout << "\n";
}
}
__device__
int coord_to_idx_dev(const int w, const int z, const int y, const int x) {
return w * SIZE_W + z * SIZE_Z + y * SIZE_Y + x;
}
__global__
void step(const int* grid, int* grid_next) {
// Find out where we are.
const int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < LEN_TOTAL) {
int left = idx;
int w = idx / SIZE_W;
left = idx - w * SIZE_W;
int z = left / SIZE_Z;
left = left - z * SIZE_Z;
int y = left / SIZE_Y;
int x = left - y * SIZE_Y;
// TODO: for loop here?
const int active = grid[idx];
// Count active neighbors.
int active_neighbors = 0;
int min_nw = max(0, w - 1);
int max_nw = min(LEN_W, w + 2);
int min_nz = max(0, z - 1);
int max_nz = min(LEN_Z, z + 2);
int min_ny = max(0, y - 1);
int max_ny = min(LEN_Y, y + 2);
int min_nx = max(0, x - 1);
int max_nx = min(LEN_X, x + 2);
for (int nw = min_nw; nw < max_nw; ++nw) {
for (int nz = min_nz; nz < max_nz; ++nz) {
for (int ny = min_ny; ny < max_ny; ++ny) {
for (int nx = min_nx; nx < max_nx; ++nx) {
active_neighbors += grid[coord_to_idx_dev(nw, nz, ny, nx)];
}
}
}
}
active_neighbors -= active;
// Rules
int active_next = active;
if (active == 1 && (active_neighbors < 2 || active_neighbors > 3)) {
active_next = 0;
}
else if (active == 0 && active_neighbors == 3) {
active_next = 1;
}
//active_next = idx;
grid_next[idx] = active_next;
}
}
int main() {
// Initialize grid.
int* grid;
hipMallocManaged(&grid, LEN_TOTAL * sizeof(int));
hipMemset(grid, 0, LEN_TOTAL);
int initial_grid[LEN_INITAL][LEN_INITAL] = {
{1, 1, 0, 0, 1, 0, 1, 0},
{1, 1, 1, 0, 1, 0, 1, 1},
{0, 0, 1, 1, 1, 0, 0, 1},
{0, 1, 0, 0, 0, 0, 1, 1},
{0, 1, 0, 0, 1, 1, 1, 1},
{1, 1, 1, 1, 1, 0, 0, 0},
{1, 1, 1, 1, 1, 1, 1, 0},
{1, 0, 1, 1, 0, 1, 0, 1}
};
for (int row = 0; row < LEN_INITAL; ++row) {
for (int col = 0; col < LEN_INITAL; ++col) {
grid[coord_to_idx(STEPS, STEPS, STEPS + row, STEPS + col)] = initial_grid[row][col];
}
}
//print_slice(grid, STEPS, STEPS);
int* grid_next;
hipMallocManaged(&grid_next, LEN_TOTAL * sizeof(int));
for (int i = 0; i < STEPS; ++i) {
//std::cout << "Step " << i << "\n";
step<<<NUM_BLOCKS, NUM_THREADS>>>(grid, grid_next);
hipDeviceSynchronize();
std::swap(grid, grid_next);
//print_slice(grid, STEPS, STEPS);
}
// Count actives.
int count = 0;
for (int i = 0; i < LEN_TOTAL; ++i) {
count += grid[i];
}
std::cout << "Active: " << count << "\n";
hipFree(grid);
hipFree(grid_next);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
constexpr int LEN_INITAL = 8;
constexpr int STEPS = 6;
constexpr int LEN_W = 1 + 2 * STEPS;
constexpr int LEN_Z = LEN_W;
constexpr int LEN_Y = LEN_INITAL + 2 * STEPS;
constexpr int LEN_X = LEN_INITAL + 2 * STEPS;
constexpr int LEN_TOTAL = LEN_W * LEN_Z * LEN_Y * LEN_X;
constexpr int SIZE_W = LEN_Z * LEN_Y * LEN_X;
constexpr int SIZE_Z = LEN_Y * LEN_X;
constexpr int SIZE_Y = LEN_X;
constexpr int NUM_THREADS = 512;
constexpr int NUM_BLOCKS = LEN_TOTAL / NUM_THREADS;
inline int coord_to_idx(const int w, const int z, const int y, const int x) {
return
w * SIZE_W +
z * SIZE_Z +
y * SIZE_Y +
x;
}
inline void print_slice(const int* grid, const int w, const int z) {
for (int row = 0; row < LEN_Y; ++row) {
for (int col = 0; col < LEN_X; ++col) {
std::cout << grid[coord_to_idx(w, z, row, col)] << " ";
}
std::cout << "\n";
}
}
__device__
int coord_to_idx_dev(const int w, const int z, const int y, const int x) {
return w * SIZE_W + z * SIZE_Z + y * SIZE_Y + x;
}
__global__
void step(const int* grid, int* grid_next) {
// Find out where we are.
const int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < LEN_TOTAL) {
int left = idx;
int w = idx / SIZE_W;
left = idx - w * SIZE_W;
int z = left / SIZE_Z;
left = left - z * SIZE_Z;
int y = left / SIZE_Y;
int x = left - y * SIZE_Y;
// TODO: for loop here?
const int active = grid[idx];
// Count active neighbors.
int active_neighbors = 0;
int min_nw = max(0, w - 1);
int max_nw = min(LEN_W, w + 2);
int min_nz = max(0, z - 1);
int max_nz = min(LEN_Z, z + 2);
int min_ny = max(0, y - 1);
int max_ny = min(LEN_Y, y + 2);
int min_nx = max(0, x - 1);
int max_nx = min(LEN_X, x + 2);
for (int nw = min_nw; nw < max_nw; ++nw) {
for (int nz = min_nz; nz < max_nz; ++nz) {
for (int ny = min_ny; ny < max_ny; ++ny) {
for (int nx = min_nx; nx < max_nx; ++nx) {
active_neighbors += grid[coord_to_idx_dev(nw, nz, ny, nx)];
}
}
}
}
active_neighbors -= active;
// Rules
int active_next = active;
if (active == 1 && (active_neighbors < 2 || active_neighbors > 3)) {
active_next = 0;
}
else if (active == 0 && active_neighbors == 3) {
active_next = 1;
}
//active_next = idx;
grid_next[idx] = active_next;
}
}
int main() {
// Initialize grid.
int* grid;
hipMallocManaged(&grid, LEN_TOTAL * sizeof(int));
hipMemset(grid, 0, LEN_TOTAL);
int initial_grid[LEN_INITAL][LEN_INITAL] = {
{1, 1, 0, 0, 1, 0, 1, 0},
{1, 1, 1, 0, 1, 0, 1, 1},
{0, 0, 1, 1, 1, 0, 0, 1},
{0, 1, 0, 0, 0, 0, 1, 1},
{0, 1, 0, 0, 1, 1, 1, 1},
{1, 1, 1, 1, 1, 0, 0, 0},
{1, 1, 1, 1, 1, 1, 1, 0},
{1, 0, 1, 1, 0, 1, 0, 1}
};
for (int row = 0; row < LEN_INITAL; ++row) {
for (int col = 0; col < LEN_INITAL; ++col) {
grid[coord_to_idx(STEPS, STEPS, STEPS + row, STEPS + col)] = initial_grid[row][col];
}
}
//print_slice(grid, STEPS, STEPS);
int* grid_next;
hipMallocManaged(&grid_next, LEN_TOTAL * sizeof(int));
for (int i = 0; i < STEPS; ++i) {
//std::cout << "Step " << i << "\n";
step<<<NUM_BLOCKS, NUM_THREADS>>>(grid, grid_next);
hipDeviceSynchronize();
std::swap(grid, grid_next);
//print_slice(grid, STEPS, STEPS);
}
// Count actives.
int count = 0;
for (int i = 0; i < LEN_TOTAL; ++i) {
count += grid[i];
}
std::cout << "Active: " << count << "\n";
hipFree(grid);
hipFree(grid_next);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4stepPKiPi
.globl _Z4stepPKiPi
.p2align 8
.type _Z4stepPKiPi,@function
_Z4stepPKiPi:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x10810, v1
s_cbranch_execz .LBB0_18
s_load_b64 s[6:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s8, exec_lo
v_mov_b32_e32 v9, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b32 v0, v[3:4], off
v_mul_hi_i32 v3, v1, 0x64d319ff
v_lshrrev_b32_e32 v4, 31, v3
v_ashrrev_i32_e32 v3, 11, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v3, v4
v_min_i32_e32 v5, 11, v4
v_max_i32_e32 v3, 1, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v6, 2, v5
v_cmpx_le_i32_e64 v3, v6
s_cbranch_execz .LBB0_17
v_mad_i32_i24 v4, v4, 0xffffebb0, v1
s_mov_b32 s9, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_i32 v5, v4, 0x51eb851f
v_lshrrev_b32_e32 v7, 31, v5
v_ashrrev_i32_e32 v5, 7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, v5, v7
v_mad_i32_i24 v4, v5, 0xfffffe70, v4
v_max_i32_e32 v12, 1, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_i32 v7, v4, 0x66666667
v_lshrrev_b32_e32 v8, 31, v7
v_ashrrev_i32_e32 v7, 3, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v11, v7, v8
v_add_nc_u32_e32 v7, -1, v3
v_mul_u32_u24_e32 v3, 0x1450, v3
v_add_nc_u32_e32 v8, -1, v12
v_mad_u64_u32 v[9:10], null, v11, 0xffffffec, v[4:5]
v_min_i32_e32 v4, 11, v5
v_mul_lo_u32 v5, v12, 0x190
v_max_i32_e32 v14, 1, v11
v_min_i32_e32 v13, 18, v11
s_delay_alu instid0(VALU_DEP_4)
v_add_nc_u32_e32 v10, 2, v4
v_min_i32_e32 v4, 18, v9
v_max_i32_e32 v9, 1, v9
v_mul_lo_u32 v15, v14, 20
v_add_nc_u32_e32 v11, 2, v13
v_cmp_le_i32_e32 vcc_lo, v12, v10
v_add_nc_u32_e32 v12, 2, v4
v_add3_u32 v3, v9, v3, v5
v_add_nc_u32_e32 v13, -1, v14
v_cmp_le_i32_e64 s2, v14, v11
v_add_nc_u32_e32 v14, -1, v9
v_cmp_le_i32_e64 s3, v9, v12
v_mov_b32_e32 v9, 0
v_add3_u32 v15, v3, v15, 0xffffea0b
s_branch .LBB0_5
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s11
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
s_or_b32 exec_lo, exec_lo, s10
v_add_nc_u32_e32 v7, 1, v7
v_add_nc_u32_e32 v15, 0x1450, v15
v_cmp_ge_i32_e64 s4, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s9, s4, s9
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execz .LBB0_16
.LBB0_5:
s_and_saveexec_b32 s10, vcc_lo
s_cbranch_execz .LBB0_4
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v16, v15 :: v_dual_mov_b32 v17, v8
s_mov_b32 s11, 0
s_branch .LBB0_9
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s13
.LBB0_8:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
s_or_b32 exec_lo, exec_lo, s12
v_add_nc_u32_e32 v17, 1, v17
v_add_nc_u32_e32 v16, 0x190, v16
v_cmp_ge_i32_e64 s4, v17, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s11, s4, s11
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execz .LBB0_3
.LBB0_9:
s_and_saveexec_b32 s12, s2
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v3, v16 :: v_dual_mov_b32 v18, v13
s_mov_b32 s13, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_12
.p2align 6
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s14
v_add_nc_u32_e32 v18, 1, v18
v_add_nc_u32_e32 v3, 20, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_i32_e64 s4, v18, v11
s_or_b32 s13, s4, s13
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execz .LBB0_7
.LBB0_12:
s_and_saveexec_b32 s14, s3
s_cbranch_execz .LBB0_11
v_ashrrev_i32_e32 v4, 31, v3
v_mov_b32_e32 v19, v14
s_mov_b32 s15, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[3:4]
v_add_co_u32 v4, s4, s6, v4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s4, s7, v5, s4
.LBB0_14:
global_load_b32 v20, v[4:5], off
v_add_nc_u32_e32 v19, 1, v19
v_add_co_u32 v4, s4, v4, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v5, s4, 0, v5, s4
v_cmp_ge_i32_e64 s5, v19, v12
s_delay_alu instid0(VALU_DEP_1)
s_or_b32 s15, s5, s15
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v9, v20, v9
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_14
s_or_b32 exec_lo, exec_lo, s15
s_branch .LBB0_11
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s9
.LBB0_17:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s8
s_load_b64 s[4:5], s[0:1], 0x8
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v3, v9, v0
v_cmp_eq_u32_e32 vcc_lo, 0, v0
v_cmp_eq_u32_e64 s1, 1, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_eq_u32_e64 s0, 3, v3
v_add_nc_u32_e32 v4, -4, v3
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cmp_gt_u32_e64 s2, -2, v4
v_cndmask_b32_e64 v3, v0, 1, s0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_and_b32 s0, s1, s2
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_cndmask_b32_e64 v2, v3, 0, s0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_18:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4stepPKiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4stepPKiPi, .Lfunc_end0-_Z4stepPKiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4stepPKiPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4stepPKiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
constexpr int LEN_INITAL = 8;
constexpr int STEPS = 6;
constexpr int LEN_W = 1 + 2 * STEPS;
constexpr int LEN_Z = LEN_W;
constexpr int LEN_Y = LEN_INITAL + 2 * STEPS;
constexpr int LEN_X = LEN_INITAL + 2 * STEPS;
constexpr int LEN_TOTAL = LEN_W * LEN_Z * LEN_Y * LEN_X;
constexpr int SIZE_W = LEN_Z * LEN_Y * LEN_X;
constexpr int SIZE_Z = LEN_Y * LEN_X;
constexpr int SIZE_Y = LEN_X;
constexpr int NUM_THREADS = 512;
constexpr int NUM_BLOCKS = LEN_TOTAL / NUM_THREADS;
inline int coord_to_idx(const int w, const int z, const int y, const int x) {
return
w * SIZE_W +
z * SIZE_Z +
y * SIZE_Y +
x;
}
inline void print_slice(const int* grid, const int w, const int z) {
for (int row = 0; row < LEN_Y; ++row) {
for (int col = 0; col < LEN_X; ++col) {
std::cout << grid[coord_to_idx(w, z, row, col)] << " ";
}
std::cout << "\n";
}
}
__device__
int coord_to_idx_dev(const int w, const int z, const int y, const int x) {
return w * SIZE_W + z * SIZE_Z + y * SIZE_Y + x;
}
__global__
void step(const int* grid, int* grid_next) {
// Find out where we are.
const int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < LEN_TOTAL) {
int left = idx;
int w = idx / SIZE_W;
left = idx - w * SIZE_W;
int z = left / SIZE_Z;
left = left - z * SIZE_Z;
int y = left / SIZE_Y;
int x = left - y * SIZE_Y;
// TODO: for loop here?
const int active = grid[idx];
// Count active neighbors.
int active_neighbors = 0;
int min_nw = max(0, w - 1);
int max_nw = min(LEN_W, w + 2);
int min_nz = max(0, z - 1);
int max_nz = min(LEN_Z, z + 2);
int min_ny = max(0, y - 1);
int max_ny = min(LEN_Y, y + 2);
int min_nx = max(0, x - 1);
int max_nx = min(LEN_X, x + 2);
for (int nw = min_nw; nw < max_nw; ++nw) {
for (int nz = min_nz; nz < max_nz; ++nz) {
for (int ny = min_ny; ny < max_ny; ++ny) {
for (int nx = min_nx; nx < max_nx; ++nx) {
active_neighbors += grid[coord_to_idx_dev(nw, nz, ny, nx)];
}
}
}
}
active_neighbors -= active;
// Rules
int active_next = active;
if (active == 1 && (active_neighbors < 2 || active_neighbors > 3)) {
active_next = 0;
}
else if (active == 0 && active_neighbors == 3) {
active_next = 1;
}
//active_next = idx;
grid_next[idx] = active_next;
}
}
int main() {
// Initialize grid.
int* grid;
hipMallocManaged(&grid, LEN_TOTAL * sizeof(int));
hipMemset(grid, 0, LEN_TOTAL);
int initial_grid[LEN_INITAL][LEN_INITAL] = {
{1, 1, 0, 0, 1, 0, 1, 0},
{1, 1, 1, 0, 1, 0, 1, 1},
{0, 0, 1, 1, 1, 0, 0, 1},
{0, 1, 0, 0, 0, 0, 1, 1},
{0, 1, 0, 0, 1, 1, 1, 1},
{1, 1, 1, 1, 1, 0, 0, 0},
{1, 1, 1, 1, 1, 1, 1, 0},
{1, 0, 1, 1, 0, 1, 0, 1}
};
for (int row = 0; row < LEN_INITAL; ++row) {
for (int col = 0; col < LEN_INITAL; ++col) {
grid[coord_to_idx(STEPS, STEPS, STEPS + row, STEPS + col)] = initial_grid[row][col];
}
}
//print_slice(grid, STEPS, STEPS);
int* grid_next;
hipMallocManaged(&grid_next, LEN_TOTAL * sizeof(int));
for (int i = 0; i < STEPS; ++i) {
//std::cout << "Step " << i << "\n";
step<<<NUM_BLOCKS, NUM_THREADS>>>(grid, grid_next);
hipDeviceSynchronize();
std::swap(grid, grid_next);
//print_slice(grid, STEPS, STEPS);
}
// Count actives.
int count = 0;
for (int i = 0; i < LEN_TOTAL; ++i) {
count += grid[i];
}
std::cout << "Active: " << count << "\n";
hipFree(grid);
hipFree(grid_next);
return 0;
} | .text
.file "17.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z19__device_stub__stepPKiPi # -- Begin function _Z19__device_stub__stepPKiPi
.p2align 4, 0x90
.type _Z19__device_stub__stepPKiPi,@function
_Z19__device_stub__stepPKiPi: # @_Z19__device_stub__stepPKiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4stepPKiPi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z19__device_stub__stepPKiPi, .Lfunc_end0-_Z19__device_stub__stepPKiPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsp, %rdi
movl $270400, %esi # imm = 0x42040
movl $1, %edx
callq hipMallocManaged
movq (%rsp), %rdi
xorl %ebx, %ebx
movl $67600, %edx # imm = 0x10810
xorl %esi, %esi
callq hipMemset
movl $134904, %eax # imm = 0x20EF8
addq (%rsp), %rax
movl $.L__const.main.initial_grid, %ecx
.p2align 4, 0x90
.LBB1_1: # %.preheader25
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rcx,%rdx,4), %esi
movl %esi, (%rax,%rdx,4)
incq %rdx
cmpq $8, %rdx
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %rbx
addq $80, %rax
addq $32, %rcx
cmpq $8, %rbx
jne .LBB1_1
# %bb.4:
movabsq $4294967428, %rbx # imm = 0x100000084
leaq 8(%rsp), %rdi
movl $270400, %esi # imm = 0x42040
movl $1, %edx
callq hipMallocManaged
movl $6, %r12d
leaq 380(%rbx), %r14
leaq 24(%rsp), %r13
leaq 16(%rsp), %rbp
leaq 80(%rsp), %r15
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_5 Depth=1
callq hipDeviceSynchronize
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq %rcx, (%rsp)
movq %rax, 8(%rsp)
decl %r12d
je .LBB1_8
.LBB1_5: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6: # in Loop: Header=BB1_5 Depth=1
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z4stepPKiPi, %edi
movq %r15, %r9
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_7
.LBB1_8: # %.preheader
xorl %eax, %eax
movq (%rsp), %rcx
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_9: # =>This Inner Loop Header: Depth=1
addl (%rcx,%rax,4), %ebx
incq %rax
cmpq $67600, %rax # imm = 0x10810
jne .LBB1_9
# %bb.10:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4stepPKiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4stepPKiPi,@object # @_Z4stepPKiPi
.section .rodata,"a",@progbits
.globl _Z4stepPKiPi
.p2align 3, 0x0
_Z4stepPKiPi:
.quad _Z19__device_stub__stepPKiPi
.size _Z4stepPKiPi, 8
.type .L__const.main.initial_grid,@object # @__const.main.initial_grid
.p2align 4, 0x0
.L__const.main.initial_grid:
.long 1 # 0x1
.long 1 # 0x1
.long 0 # 0x0
.long 0 # 0x0
.long 1 # 0x1
.long 0 # 0x0
.long 1 # 0x1
.long 0 # 0x0
.long 1 # 0x1
.long 1 # 0x1
.long 1 # 0x1
.long 0 # 0x0
.long 1 # 0x1
.long 0 # 0x0
.long 1 # 0x1
.long 1 # 0x1
.long 0 # 0x0
.long 0 # 0x0
.long 1 # 0x1
.long 1 # 0x1
.long 1 # 0x1
.long 0 # 0x0
.long 0 # 0x0
.long 1 # 0x1
.long 0 # 0x0
.long 1 # 0x1
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 1 # 0x1
.long 1 # 0x1
.long 0 # 0x0
.long 1 # 0x1
.long 0 # 0x0
.long 0 # 0x0
.long 1 # 0x1
.long 1 # 0x1
.long 1 # 0x1
.long 1 # 0x1
.long 1 # 0x1
.long 1 # 0x1
.long 1 # 0x1
.long 1 # 0x1
.long 1 # 0x1
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 1 # 0x1
.long 1 # 0x1
.long 1 # 0x1
.long 1 # 0x1
.long 1 # 0x1
.long 1 # 0x1
.long 1 # 0x1
.long 0 # 0x0
.long 1 # 0x1
.long 0 # 0x0
.long 1 # 0x1
.long 1 # 0x1
.long 0 # 0x0
.long 1 # 0x1
.long 0 # 0x0
.long 1 # 0x1
.size .L__const.main.initial_grid, 256
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Active: "
.size .L.str, 9
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\n"
.size .L.str.1, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4stepPKiPi"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__stepPKiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4stepPKiPi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4stepPKiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R2, c[0x0][0x0], R3 ; /* 0x0000000002007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R0, 0x1080f, PT ; /* 0x0001080f0000780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.HI R6, R0, 0x64d319ff, RZ ; /* 0x64d319ff00067827 */
/* 0x000fe200078e02ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0090*/ SHF.R.U32.HI R7, RZ, 0x1f, R6 ; /* 0x0000001fff077819 */
/* 0x000fc60000011606 */
/*00a0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fe200078e0205 */
/*00b0*/ LEA.HI.SX32 R15, R6, R7, 0x15 ; /* 0x00000007060f7211 */
/* 0x000fca00078faaff */
/*00c0*/ IMAD R7, R15.reuse, -0x1450, R0 ; /* 0xffffebb00f077824 */
/* 0x040fe200078e0200 */
/*00d0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000162000c1e1900 */
/*00e0*/ IADD3 R10, R15, -0x1, RZ ; /* 0xffffffff0f0a7810 */
/* 0x000fe20007ffe0ff */
/*00f0*/ BSSY B3, 0xb60 ; /* 0x00000a6000037945 */
/* 0x000fe20003800000 */
/*0100*/ IMAD.HI R12, R7, 0x51eb851f, RZ ; /* 0x51eb851f070c7827 */
/* 0x000fe400078e02ff */
/*0110*/ IMNMX R10, RZ, R10, !PT ; /* 0x0000000aff0a7217 */
/* 0x000fe40007800200 */
/*0120*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e00ff */
/*0130*/ SHF.R.U32.HI R9, RZ, 0x1f, R12 ; /* 0x0000001fff097819 */
/* 0x000fe4000001160c */
/*0140*/ IADD3 R5, R15, 0x2, RZ ; /* 0x000000020f057810 */
/* 0x001fc40007ffe0ff */
/*0150*/ LEA.HI.SX32 R12, R12, R9, 0x19 ; /* 0x000000090c0c7211 */
/* 0x000fe400078fcaff */
/*0160*/ IMNMX R5, R5, 0xd, PT ; /* 0x0000000d05057817 */
/* 0x000fc60003800200 */
/*0170*/ IMAD R6, R12, -0x190, R7 ; /* 0xfffffe700c067824 */
/* 0x000fe200078e0207 */
/*0180*/ ISETP.GE.AND P0, PT, R10, R5, PT ; /* 0x000000050a00720c */
/* 0x000fe40003f06270 */
/*0190*/ SHF.R.S32.HI R7, RZ, 0x1f, R0 ; /* 0x0000001fff077819 */
/* 0x000fe20000011400 */
/*01a0*/ IMAD.HI R13, R6, 0x66666667, RZ ; /* 0x66666667060d7827 */
/* 0x000fca00078e02ff */
/*01b0*/ SHF.R.U32.HI R8, RZ, 0x1f, R13 ; /* 0x0000001fff087819 */
/* 0x000fc8000001160d */
/*01c0*/ LEA.HI.SX32 R13, R13, R8, 0x1d ; /* 0x000000080d0d7211 */
/* 0x000fc800078feaff */
/*01d0*/ IADD3 R8, R13.reuse, -0x1, RZ ; /* 0xffffffff0d087810 */
/* 0x040fe20007ffe0ff */
/*01e0*/ IMAD R14, R13, -0x14, R6 ; /* 0xffffffec0d0e7824 */
/* 0x000fe200078e0206 */
/*01f0*/ IADD3 R6, R12, -0x1, RZ ; /* 0xffffffff0c067810 */
/* 0x000fe40007ffe0ff */
/*0200*/ IMNMX R8, RZ, R8, !PT ; /* 0x00000008ff087217 */
/* 0x000fe40007800200 */
/*0210*/ IADD3 R9, R14, -0x1, RZ ; /* 0xffffffff0e097810 */
/* 0x000fe40007ffe0ff */
/*0220*/ IMNMX R6, RZ, R6, !PT ; /* 0x00000006ff067217 */
/* 0x000fe40007800200 */
/*0230*/ IMNMX R9, RZ, R9, !PT ; /* 0x00000009ff097217 */
/* 0x000fe20007800200 */
/*0240*/ @P0 BRA 0xb50 ; /* 0x0000090000000947 */
/* 0x000fea0003800000 */
/*0250*/ IMAD R16, R15, 0xd, R12 ; /* 0x0000000d0f107824 */
/* 0x000fe200078e020c */
/*0260*/ IADD3 R14, R14, 0x2, RZ ; /* 0x000000020e0e7810 */
/* 0x000fe20007ffe0ff */
/*0270*/ IMAD.MOV.U32 R15, RZ, RZ, 0x14 ; /* 0x00000014ff0f7424 */
/* 0x000fe200078e00ff */
/*0280*/ IADD3 R17, R13, 0x2, RZ ; /* 0x000000020d117810 */
/* 0x000fe20007ffe0ff */
/*0290*/ IMAD R16, R16, 0x14, R13 ; /* 0x0000001410107824 */
/* 0x000fe200078e020d */
/*02a0*/ IADD3 R13, R9.reuse, 0x1, RZ ; /* 0x00000001090d7810 */
/* 0x040fe20007ffe0ff */
/*02b0*/ IMAD.MOV R11, RZ, RZ, -R2 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0a02 */
/*02c0*/ IADD3 R23, R9, 0x3, RZ ; /* 0x0000000309177810 */
/* 0x000fe20007ffe0ff */
/*02d0*/ IMAD R2, R16, R15, -0x3 ; /* 0xfffffffd10027424 */
/* 0x000fe200078e020f */
/*02e0*/ IADD3 R15, R12, 0x2, RZ ; /* 0x000000020c0f7810 */
/* 0x000fc40007ffe0ff */
/*02f0*/ IADD3 R12, R9, 0x2, RZ ; /* 0x00000002090c7810 */
/* 0x000fe20007ffe0ff */
/*0300*/ IMAD R2, R11, c[0x0][0x0], R2 ; /* 0x000000000b027a24 */
/* 0x000fe200078e0202 */
/*0310*/ IMNMX R14, R14, 0x14, PT ; /* 0x000000140e0e7817 */
/* 0x000fe20003800200 */
/*0320*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e00ff */
/*0330*/ IMNMX R15, R15, 0xd, PT ; /* 0x0000000d0f0f7817 */
/* 0x000fe20003800200 */
/*0340*/ IMAD.IADD R2, R2, 0x1, -R3 ; /* 0x0000000102027824 */
/* 0x000fe200078e0a03 */
/*0350*/ IMNMX R17, R17, 0x14, PT ; /* 0x0000001411117817 */
/* 0x000fc80003800200 */
/*0360*/ IMNMX R2, R2, -0x15, !PT ; /* 0xffffffeb02027817 */
/* 0x000fc80007800200 */
/*0370*/ IADD3 R3, -R9, -0x2, -R2 ; /* 0xfffffffe09037810 */
/* 0x000fe40007ffe902 */
/*0380*/ LOP3.LUT R2, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff027212 */
/* 0x000fe400078e33ff */
/*0390*/ ISETP.GE.U32.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fc60003f26070 */
/*03a0*/ IMAD.IADD R2, R2, 0x1, -R9 ; /* 0x0000000102027824 */
/* 0x000fca00078e0a09 */
/*03b0*/ LOP3.LUT R16, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302107812 */
/* 0x000fe400078ec0ff */
/*03c0*/ ISETP.GE.AND P0, PT, R6, R15, PT ; /* 0x0000000f0600720c */
/* 0x000fe20003f06270 */
/*03d0*/ BSSY B2, 0xb20 ; /* 0x0000074000027945 */
/* 0x000fd80003800000 */
/*03e0*/ @P0 BRA 0xb10 ; /* 0x0000072000000947 */
/* 0x000fea0003800000 */
/*03f0*/ IMAD.MOV.U32 R18, RZ, RZ, R6 ; /* 0x000000ffff127224 */
/* 0x000fe400078e0006 */
/*0400*/ ISETP.GE.AND P0, PT, R8, R17, PT ; /* 0x000000110800720c */
/* 0x000fe20003f06270 */
/*0410*/ BSSY B1, 0xae0 ; /* 0x000006c000017945 */
/* 0x000fd80003800000 */
/*0420*/ @P0 BRA 0xad0 ; /* 0x000006a000000947 */
/* 0x000fea0003800000 */
/*0430*/ IMAD R19, R10, 0xd, R18 ; /* 0x0000000d0a137824 */
/* 0x000fe400078e0212 */
/*0440*/ IMAD.MOV.U32 R20, RZ, RZ, R8 ; /* 0x000000ffff147224 */
/* 0x000fe400078e0008 */
/*0450*/ IMAD R19, R19, 0x190, RZ ; /* 0x0000019013137824 */
/* 0x000fe400078e02ff */
/*0460*/ ISETP.GE.AND P0, PT, R9, R14, PT ; /* 0x0000000e0900720c */
/* 0x000fe20003f06270 */
/*0470*/ BSSY B0, 0xaa0 ; /* 0x0000062000007945 */
/* 0x000fd80003800000 */
/*0480*/ @P0 BRA 0xa90 ; /* 0x0000060000000947 */
/* 0x000fea0003800000 */
/*0490*/ ISETP.NE.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe20003f05270 */
/*04a0*/ BSSY B4, 0x5e0 ; /* 0x0000013000047945 */
/* 0x000fe20003800000 */
/*04b0*/ IMAD.MOV.U32 R21, RZ, RZ, R9 ; /* 0x000000ffff157224 */
/* 0x000fd600078e0009 */
/*04c0*/ @!P0 BRA 0x5d0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*04d0*/ IMAD R2, R20, 0x14, R19 ; /* 0x0000001414027824 */
/* 0x000fe400078e0213 */
/*04e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*04f0*/ IMAD.IADD R2, R9, 0x1, R2 ; /* 0x0000000109027824 */
/* 0x000fc800078e0202 */
/*0500*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0510*/ LDG.E R22, [R2.64] ; /* 0x0000000402167981 */
/* 0x000ea2000c1e1900 */
/*0520*/ ISETP.NE.AND P0, PT, R16, 0x1, PT ; /* 0x000000011000780c */
/* 0x000fe20003f05270 */
/*0530*/ IMAD.MOV.U32 R21, RZ, RZ, R13 ; /* 0x000000ffff157224 */
/* 0x000fe400078e000d */
/*0540*/ IMAD.IADD R11, R11, 0x1, R22 ; /* 0x000000010b0b7824 */
/* 0x004fd400078e0216 */
/*0550*/ @!P0 BRA 0x5d0 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*0560*/ ISETP.NE.AND P0, PT, R16, 0x2, PT ; /* 0x000000021000780c */
/* 0x000fe20003f05270 */
/*0570*/ LDG.E R22, [R2.64+0x4] ; /* 0x0000040402167981 */
/* 0x000e98000c1e1900 */
/*0580*/ @P0 LDG.E R24, [R2.64+0x8] ; /* 0x0000080402180981 */
/* 0x000ee2000c1e1900 */
/*0590*/ IMAD.MOV.U32 R21, RZ, RZ, R12 ; /* 0x000000ffff157224 */
/* 0x000fe400078e000c */
/*05a0*/ @P0 IMAD.MOV.U32 R21, RZ, RZ, R23 ; /* 0x000000ffff150224 */
/* 0x000fe400078e0017 */
/*05b0*/ IMAD.IADD R11, R11, 0x1, R22 ; /* 0x000000010b0b7824 */
/* 0x004fc800078e0216 */
/*05c0*/ @P0 IMAD.IADD R11, R11, 0x1, R24 ; /* 0x000000010b0b0824 */
/* 0x008fe400078e0218 */
/*05d0*/ BSYNC B4 ; /* 0x0000000000047941 */
/* 0x000fea0003800000 */
/*05e0*/ @!P1 BRA 0xa90 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*05f0*/ IMAD.IADD R2, R14, 0x1, -R21.reuse ; /* 0x000000010e027824 */
/* 0x100fe200078e0a15 */
/*0600*/ BSSY B4, 0x8a0 ; /* 0x0000029000047945 */
/* 0x000fe20003800000 */
/*0610*/ IMAD.IADD R3, R19, 0x1, R21 ; /* 0x0000000113037824 */
/* 0x000fe200078e0215 */
/*0620*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*0630*/ ISETP.GT.AND P2, PT, R2, 0xc, PT ; /* 0x0000000c0200780c */
/* 0x000fe20003f44270 */
/*0640*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe400078e00ff */
/*0650*/ IMAD R3, R20, 0x14, R3 ; /* 0x0000001414037824 */
/* 0x000fc800078e0203 */
/*0660*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fcc00078e0202 */
/*0670*/ @!P2 BRA 0x890 ; /* 0x000002100000a947 */
/* 0x000fea0003800000 */
/*0680*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0690*/ IADD3 R22, R14, -0xc, RZ ; /* 0xfffffff40e167810 */
/* 0x000fe40007ffe0ff */
/*06a0*/ LDG.E R24, [R2.64] ; /* 0x0000000402187981 */
/* 0x000ea8000c1e1900 */
/*06b0*/ LDG.E R25, [R2.64+0x4] ; /* 0x0000040402197981 */
/* 0x000ea8000c1e1900 */
/*06c0*/ LDG.E R27, [R2.64+0x8] ; /* 0x00000804021b7981 */
/* 0x000ee8000c1e1900 */
/*06d0*/ LDG.E R26, [R2.64+0xc] ; /* 0x00000c04021a7981 */
/* 0x000ee2000c1e1900 */
/*06e0*/ IADD3 R24, R25, R24, R11 ; /* 0x0000001819187210 */
/* 0x004fc60007ffe00b */
/*06f0*/ LDG.E R11, [R2.64+0x10] ; /* 0x00001004020b7981 */
/* 0x000ea8000c1e1900 */
/*0700*/ LDG.E R25, [R2.64+0x14] ; /* 0x0000140402197981 */
/* 0x000ea2000c1e1900 */
/*0710*/ IADD3 R24, R26, R27, R24 ; /* 0x0000001b1a187210 */
/* 0x008fc60007ffe018 */
/*0720*/ LDG.E R26, [R2.64+0x18] ; /* 0x00001804021a7981 */
/* 0x000ee8000c1e1900 */
/*0730*/ LDG.E R27, [R2.64+0x1c] ; /* 0x00001c04021b7981 */
/* 0x000ee2000c1e1900 */
/*0740*/ IADD3 R11, R25, R11, R24 ; /* 0x0000000b190b7210 */
/* 0x004fc60007ffe018 */
/*0750*/ LDG.E R24, [R2.64+0x20] ; /* 0x0000200402187981 */
/* 0x000ea8000c1e1900 */
/*0760*/ LDG.E R25, [R2.64+0x24] ; /* 0x0000240402197981 */
/* 0x000ea2000c1e1900 */
/*0770*/ IADD3 R11, R27, R26, R11 ; /* 0x0000001a1b0b7210 */
/* 0x008fc60007ffe00b */
/*0780*/ LDG.E R26, [R2.64+0x28] ; /* 0x00002804021a7981 */
/* 0x000ee8000c1e1900 */
/*0790*/ LDG.E R27, [R2.64+0x2c] ; /* 0x00002c04021b7981 */
/* 0x000ee2000c1e1900 */
/*07a0*/ IADD3 R11, R25, R24, R11 ; /* 0x00000018190b7210 */
/* 0x004fc60007ffe00b */
/*07b0*/ LDG.E R25, [R2.64+0x30] ; /* 0x0000300402197981 */
/* 0x000ea8000c1e1900 */
/*07c0*/ LDG.E R24, [R2.64+0x38] ; /* 0x0000380402187981 */
/* 0x000f22000c1e1900 */
/*07d0*/ IADD3 R26, R27, R26, R11 ; /* 0x0000001a1b1a7210 */
/* 0x008fc60007ffe00b */
/*07e0*/ LDG.E R27, [R2.64+0x34] ; /* 0x00003404021b7981 */
/* 0x000ea8000c1e1900 */
/*07f0*/ LDG.E R11, [R2.64+0x3c] ; /* 0x00003c04020b7981 */
/* 0x000f22000c1e1900 */
/*0800*/ IADD3 R21, R21, 0x10, RZ ; /* 0x0000001015157810 */
/* 0x000fc80007ffe0ff */
/*0810*/ ISETP.GE.AND P2, PT, R21, R22, PT ; /* 0x000000161500720c */
/* 0x000fe40003f46270 */
/*0820*/ IADD3 R25, R27, R25, R26 ; /* 0x000000191b197210 */
/* 0x004fe40007ffe01a */
/*0830*/ IADD3 R26, P3, R2, 0x40, RZ ; /* 0x00000040021a7810 */
/* 0x000fca0007f7e0ff */
/*0840*/ IMAD.X R27, RZ, RZ, R3, P3 ; /* 0x000000ffff1b7224 */
/* 0x000fe200018e0603 */
/*0850*/ IADD3 R11, R11, R24, R25 ; /* 0x000000180b0b7210 */
/* 0x010fe20007ffe019 */
/*0860*/ IMAD.MOV.U32 R2, RZ, RZ, R26 ; /* 0x000000ffff027224 */
/* 0x000fe400078e001a */
/*0870*/ IMAD.MOV.U32 R3, RZ, RZ, R27 ; /* 0x000000ffff037224 */
/* 0x000fe200078e001b */
/*0880*/ @!P2 BRA 0x6a0 ; /* 0xfffffe100000a947 */
/* 0x000fea000383ffff */
/*0890*/ BSYNC B4 ; /* 0x0000000000047941 */
/* 0x000fea0003800000 */
/*08a0*/ IMAD.IADD R22, R14, 0x1, -R21 ; /* 0x000000010e167824 */
/* 0x000fe200078e0a15 */
/*08b0*/ BSSY B4, 0xa10 ; /* 0x0000015000047945 */
/* 0x000fe80003800000 */
/*08c0*/ ISETP.GT.AND P2, PT, R22, 0x4, PT ; /* 0x000000041600780c */
/* 0x000fda0003f44270 */
/*08d0*/ @!P2 BRA 0xa00 ; /* 0x000001200000a947 */
/* 0x000fea0003800000 */
/*08e0*/ LDG.E R22, [R2.64] ; /* 0x0000000402167981 */
/* 0x000ea8000c1e1900 */
/*08f0*/ LDG.E R24, [R2.64+0x4] ; /* 0x0000040402187981 */
/* 0x000ea8000c1e1900 */
/*0900*/ LDG.E R25, [R2.64+0x8] ; /* 0x0000080402197981 */
/* 0x000ee8000c1e1900 */
/*0910*/ LDG.E R26, [R2.64+0xc] ; /* 0x00000c04021a7981 */
/* 0x000ee2000c1e1900 */
/*0920*/ IADD3 R22, R24, R22, R11 ; /* 0x0000001618167210 */
/* 0x004fc60007ffe00b */
/*0930*/ LDG.E R11, [R2.64+0x10] ; /* 0x00001004020b7981 */
/* 0x000ea8000c1e1900 */
/*0940*/ LDG.E R24, [R2.64+0x14] ; /* 0x0000140402187981 */
/* 0x000ea2000c1e1900 */
/*0950*/ IADD3 R22, R26, R25, R22 ; /* 0x000000191a167210 */
/* 0x008fc60007ffe016 */
/*0960*/ LDG.E R26, [R2.64+0x18] ; /* 0x00001804021a7981 */
/* 0x000ee8000c1e1900 */
/*0970*/ LDG.E R25, [R2.64+0x1c] ; /* 0x00001c0402197981 */
/* 0x000ee2000c1e1900 */
/*0980*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0990*/ IADD3 R21, R21, 0x8, RZ ; /* 0x0000000815157810 */
/* 0x000fe40007ffe0ff */
/*09a0*/ IADD3 R11, R24, R11, R22 ; /* 0x0000000b180b7210 */
/* 0x004fe40007ffe016 */
/*09b0*/ IADD3 R22, P2, R2, 0x20, RZ ; /* 0x0000002002167810 */
/* 0x000fca0007f5e0ff */
/*09c0*/ IMAD.X R27, RZ, RZ, R3, P2 ; /* 0x000000ffff1b7224 */
/* 0x000fe200010e0603 */
/*09d0*/ IADD3 R11, R25, R26, R11 ; /* 0x0000001a190b7210 */
/* 0x008fe20007ffe00b */
/*09e0*/ IMAD.MOV.U32 R2, RZ, RZ, R22 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0016 */
/*09f0*/ IMAD.MOV.U32 R3, RZ, RZ, R27 ; /* 0x000000ffff037224 */
/* 0x000fe400078e001b */
/*0a00*/ BSYNC B4 ; /* 0x0000000000047941 */
/* 0x000fea0003800000 */
/*0a10*/ ISETP.LT.OR P0, PT, R21, R14, P0 ; /* 0x0000000e1500720c */
/* 0x000fda0000701670 */
/*0a20*/ @!P0 BRA 0xa90 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*0a30*/ LDG.E R22, [R2.64] ; /* 0x0000000402167981 */
/* 0x000ea8000c1e1900 */
/*0a40*/ LDG.E R21, [R2.64+0x4] ; /* 0x0000040402157981 */
/* 0x000ea8000c1e1900 */
/*0a50*/ LDG.E R24, [R2.64+0x8] ; /* 0x0000080402187981 */
/* 0x000ee8000c1e1900 */
/*0a60*/ LDG.E R25, [R2.64+0xc] ; /* 0x00000c0402197981 */
/* 0x000ee2000c1e1900 */
/*0a70*/ IADD3 R11, R21, R22, R11 ; /* 0x00000016150b7210 */
/* 0x004fc80007ffe00b */
/*0a80*/ IADD3 R11, R25, R24, R11 ; /* 0x00000018190b7210 */
/* 0x008fe40007ffe00b */
/*0a90*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0aa0*/ IADD3 R20, R20, 0x1, RZ ; /* 0x0000000114147810 */
/* 0x000fc80007ffe0ff */
/*0ab0*/ ISETP.GE.AND P0, PT, R20, R17, PT ; /* 0x000000111400720c */
/* 0x000fda0003f06270 */
/*0ac0*/ @!P0 BRA 0x460 ; /* 0xfffff99000008947 */
/* 0x000fea000383ffff */
/*0ad0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0ae0*/ IADD3 R18, R18, 0x1, RZ ; /* 0x0000000112127810 */
/* 0x000fc80007ffe0ff */
/*0af0*/ ISETP.GE.AND P0, PT, R18, R15, PT ; /* 0x0000000f1200720c */
/* 0x000fda0003f06270 */
/*0b00*/ @!P0 BRA 0x400 ; /* 0xfffff8f000008947 */
/* 0x000fea000383ffff */
/*0b10*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0b20*/ IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a7810 */
/* 0x000fc80007ffe0ff */
/*0b30*/ ISETP.GE.AND P0, PT, R10, R5, PT ; /* 0x000000050a00720c */
/* 0x000fda0003f06270 */
/*0b40*/ @!P0 BRA 0x3c0 ; /* 0xfffff87000008947 */
/* 0x000fea000383ffff */
/*0b50*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0b60*/ IMAD.IADD R11, R11, 0x1, -R4 ; /* 0x000000010b0b7824 */
/* 0x020fca00078e0a04 */
/*0b70*/ LOP3.LUT R2, R11.reuse, 0xfffffffe, RZ, 0xc0, !PT ; /* 0xfffffffe0b027812 */
/* 0x040fe400078ec0ff */
/*0b80*/ ISETP.NE.AND P1, PT, R11, 0x3, PT ; /* 0x000000030b00780c */
/* 0x000fe40003f25270 */
/*0b90*/ ISETP.NE.AND P0, PT, R2, 0x2, PT ; /* 0x000000020200780c */
/* 0x000fe40003f05270 */
/*0ba0*/ ISETP.EQ.AND P1, PT, R4.reuse, RZ, !P1 ; /* 0x000000ff0400720c */
/* 0x040fe40004f22270 */
/*0bb0*/ ISETP.EQ.AND P0, PT, R4, 0x1, P0 ; /* 0x000000010400780c */
/* 0x000fe40000702270 */
/*0bc0*/ LEA R2, P2, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fc400078410ff */
/*0bd0*/ SEL R4, R4, 0x1, !P1 ; /* 0x0000000104047807 */
/* 0x000fe40004800000 */
/*0be0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R7, 0x2, P2 ; /* 0x00005b0000037a11 */
/* 0x000fe400010f1407 */
/*0bf0*/ SEL R5, R4, RZ, !P0 ; /* 0x000000ff04057207 */
/* 0x000fca0004000000 */
/*0c00*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0c10*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c20*/ BRA 0xc20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4stepPKiPi
.globl _Z4stepPKiPi
.p2align 8
.type _Z4stepPKiPi,@function
_Z4stepPKiPi:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x10810, v1
s_cbranch_execz .LBB0_18
s_load_b64 s[6:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s8, exec_lo
v_mov_b32_e32 v9, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b32 v0, v[3:4], off
v_mul_hi_i32 v3, v1, 0x64d319ff
v_lshrrev_b32_e32 v4, 31, v3
v_ashrrev_i32_e32 v3, 11, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v3, v4
v_min_i32_e32 v5, 11, v4
v_max_i32_e32 v3, 1, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v6, 2, v5
v_cmpx_le_i32_e64 v3, v6
s_cbranch_execz .LBB0_17
v_mad_i32_i24 v4, v4, 0xffffebb0, v1
s_mov_b32 s9, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_i32 v5, v4, 0x51eb851f
v_lshrrev_b32_e32 v7, 31, v5
v_ashrrev_i32_e32 v5, 7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, v5, v7
v_mad_i32_i24 v4, v5, 0xfffffe70, v4
v_max_i32_e32 v12, 1, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_i32 v7, v4, 0x66666667
v_lshrrev_b32_e32 v8, 31, v7
v_ashrrev_i32_e32 v7, 3, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v11, v7, v8
v_add_nc_u32_e32 v7, -1, v3
v_mul_u32_u24_e32 v3, 0x1450, v3
v_add_nc_u32_e32 v8, -1, v12
v_mad_u64_u32 v[9:10], null, v11, 0xffffffec, v[4:5]
v_min_i32_e32 v4, 11, v5
v_mul_lo_u32 v5, v12, 0x190
v_max_i32_e32 v14, 1, v11
v_min_i32_e32 v13, 18, v11
s_delay_alu instid0(VALU_DEP_4)
v_add_nc_u32_e32 v10, 2, v4
v_min_i32_e32 v4, 18, v9
v_max_i32_e32 v9, 1, v9
v_mul_lo_u32 v15, v14, 20
v_add_nc_u32_e32 v11, 2, v13
v_cmp_le_i32_e32 vcc_lo, v12, v10
v_add_nc_u32_e32 v12, 2, v4
v_add3_u32 v3, v9, v3, v5
v_add_nc_u32_e32 v13, -1, v14
v_cmp_le_i32_e64 s2, v14, v11
v_add_nc_u32_e32 v14, -1, v9
v_cmp_le_i32_e64 s3, v9, v12
v_mov_b32_e32 v9, 0
v_add3_u32 v15, v3, v15, 0xffffea0b
s_branch .LBB0_5
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s11
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
s_or_b32 exec_lo, exec_lo, s10
v_add_nc_u32_e32 v7, 1, v7
v_add_nc_u32_e32 v15, 0x1450, v15
v_cmp_ge_i32_e64 s4, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s9, s4, s9
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execz .LBB0_16
.LBB0_5:
s_and_saveexec_b32 s10, vcc_lo
s_cbranch_execz .LBB0_4
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v16, v15 :: v_dual_mov_b32 v17, v8
s_mov_b32 s11, 0
s_branch .LBB0_9
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s13
.LBB0_8:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
s_or_b32 exec_lo, exec_lo, s12
v_add_nc_u32_e32 v17, 1, v17
v_add_nc_u32_e32 v16, 0x190, v16
v_cmp_ge_i32_e64 s4, v17, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s11, s4, s11
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execz .LBB0_3
.LBB0_9:
s_and_saveexec_b32 s12, s2
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v3, v16 :: v_dual_mov_b32 v18, v13
s_mov_b32 s13, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_12
.p2align 6
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s14
v_add_nc_u32_e32 v18, 1, v18
v_add_nc_u32_e32 v3, 20, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_i32_e64 s4, v18, v11
s_or_b32 s13, s4, s13
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execz .LBB0_7
.LBB0_12:
s_and_saveexec_b32 s14, s3
s_cbranch_execz .LBB0_11
v_ashrrev_i32_e32 v4, 31, v3
v_mov_b32_e32 v19, v14
s_mov_b32 s15, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[3:4]
v_add_co_u32 v4, s4, s6, v4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s4, s7, v5, s4
.LBB0_14:
global_load_b32 v20, v[4:5], off
v_add_nc_u32_e32 v19, 1, v19
v_add_co_u32 v4, s4, v4, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v5, s4, 0, v5, s4
v_cmp_ge_i32_e64 s5, v19, v12
s_delay_alu instid0(VALU_DEP_1)
s_or_b32 s15, s5, s15
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v9, v20, v9
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_14
s_or_b32 exec_lo, exec_lo, s15
s_branch .LBB0_11
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s9
.LBB0_17:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s8
s_load_b64 s[4:5], s[0:1], 0x8
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v3, v9, v0
v_cmp_eq_u32_e32 vcc_lo, 0, v0
v_cmp_eq_u32_e64 s1, 1, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_eq_u32_e64 s0, 3, v3
v_add_nc_u32_e32 v4, -4, v3
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cmp_gt_u32_e64 s2, -2, v4
v_cndmask_b32_e64 v3, v0, 1, s0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_and_b32 s0, s1, s2
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_cndmask_b32_e64 v2, v3, 0, s0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_18:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4stepPKiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4stepPKiPi, .Lfunc_end0-_Z4stepPKiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4stepPKiPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4stepPKiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00178d59_00000000-6_17.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3676:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3676:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z16coord_to_idx_deviiii
.type _Z16coord_to_idx_deviiii, @function
_Z16coord_to_idx_deviiii:
.LFB3671:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3671:
.size _Z16coord_to_idx_deviiii, .-_Z16coord_to_idx_deviiii
.globl _Z26__device_stub__Z4stepPKiPiPKiPi
.type _Z26__device_stub__Z4stepPKiPiPKiPi, @function
_Z26__device_stub__Z4stepPKiPiPKiPi:
.LFB3698:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4stepPKiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3698:
.size _Z26__device_stub__Z4stepPKiPiPKiPi, .-_Z26__device_stub__Z4stepPKiPiPKiPi
.globl _Z4stepPKiPi
.type _Z4stepPKiPi, @function
_Z4stepPKiPi:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z4stepPKiPiPKiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _Z4stepPKiPi, .-_Z4stepPKiPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Active: "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB3672:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $320, %rsp
.cfi_def_cfa_offset 336
movq %fs:40, %rax
movq %rax, 312(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $270400, %esi
call cudaMallocManaged@PLT
movl $67600, %edx
movl $0, %esi
movq 8(%rsp), %rdi
call cudaMemset@PLT
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, 56(%rsp)
movl $0, 60(%rsp)
movl $1, 64(%rsp)
movl $0, 68(%rsp)
movl $1, 72(%rsp)
movl $0, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $0, 92(%rsp)
movl $1, 96(%rsp)
movl $0, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $0, 112(%rsp)
movl $0, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $0, 132(%rsp)
movl $0, 136(%rsp)
movl $1, 140(%rsp)
movl $0, 144(%rsp)
movl $1, 148(%rsp)
movl $0, 152(%rsp)
movl $0, 156(%rsp)
movl $0, 160(%rsp)
movl $0, 164(%rsp)
movl $1, 168(%rsp)
movl $1, 172(%rsp)
movl $0, 176(%rsp)
movl $1, 180(%rsp)
movl $0, 184(%rsp)
movl $0, 188(%rsp)
movl $1, 192(%rsp)
movl $1, 196(%rsp)
movl $1, 200(%rsp)
movl $1, 204(%rsp)
movl $1, 208(%rsp)
movl $1, 212(%rsp)
movl $1, 216(%rsp)
movl $1, 220(%rsp)
movl $1, 224(%rsp)
movl $0, 228(%rsp)
movl $0, 232(%rsp)
movl $0, 236(%rsp)
movl $1, 240(%rsp)
movl $1, 244(%rsp)
movl $1, 248(%rsp)
movl $1, 252(%rsp)
movl $1, 256(%rsp)
movl $1, 260(%rsp)
movl $1, 264(%rsp)
movl $0, 268(%rsp)
movl $1, 272(%rsp)
movl $0, 276(%rsp)
movl $1, 280(%rsp)
movl $1, 284(%rsp)
movl $0, 288(%rsp)
movl $1, 292(%rsp)
movl $0, 296(%rsp)
movl $1, 300(%rsp)
leaq 48(%rsp), %rdi
leaq -336(%rsp), %r8
movl $134936, %esi
.L14:
leaq -32(%rsi), %rax
.L15:
movl -134904(%rdi,%rax), %ecx
movq 8(%rsp), %rdx
movl %ecx, (%rdx,%rax)
addq $4, %rax
cmpq %rsi, %rax
jne .L15
subq $48, %rdi
addq $80, %rsi
cmpq %r8, %rdi
jne .L14
leaq 16(%rsp), %rdi
movl $1, %edx
movl $270400, %esi
call cudaMallocManaged@PLT
movl $6, %ebx
jmp .L18
.L17:
call cudaDeviceSynchronize@PLT
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rcx, 8(%rsp)
movq %rax, 16(%rsp)
subl $1, %ebx
je .L25
.L18:
movl $512, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $132, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L17
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z4stepPKiPiPKiPi
jmp .L17
.L25:
movq %rcx, %rax
addq $270400, %rcx
movl $0, %edx
.L19:
movl %edx, %ebx
addl (%rax), %ebx
movl %ebx, %edx
addq $4, %rax
cmpq %rcx, %rax
jne .L19
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 312(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $320, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3672:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z4stepPKiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3701:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z4stepPKiPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "17.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z19__device_stub__stepPKiPi # -- Begin function _Z19__device_stub__stepPKiPi
.p2align 4, 0x90
.type _Z19__device_stub__stepPKiPi,@function
_Z19__device_stub__stepPKiPi: # @_Z19__device_stub__stepPKiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4stepPKiPi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z19__device_stub__stepPKiPi, .Lfunc_end0-_Z19__device_stub__stepPKiPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsp, %rdi
movl $270400, %esi # imm = 0x42040
movl $1, %edx
callq hipMallocManaged
movq (%rsp), %rdi
xorl %ebx, %ebx
movl $67600, %edx # imm = 0x10810
xorl %esi, %esi
callq hipMemset
movl $134904, %eax # imm = 0x20EF8
addq (%rsp), %rax
movl $.L__const.main.initial_grid, %ecx
.p2align 4, 0x90
.LBB1_1: # %.preheader25
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rcx,%rdx,4), %esi
movl %esi, (%rax,%rdx,4)
incq %rdx
cmpq $8, %rdx
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %rbx
addq $80, %rax
addq $32, %rcx
cmpq $8, %rbx
jne .LBB1_1
# %bb.4:
movabsq $4294967428, %rbx # imm = 0x100000084
leaq 8(%rsp), %rdi
movl $270400, %esi # imm = 0x42040
movl $1, %edx
callq hipMallocManaged
movl $6, %r12d
leaq 380(%rbx), %r14
leaq 24(%rsp), %r13
leaq 16(%rsp), %rbp
leaq 80(%rsp), %r15
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_5 Depth=1
callq hipDeviceSynchronize
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq %rcx, (%rsp)
movq %rax, 8(%rsp)
decl %r12d
je .LBB1_8
.LBB1_5: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6: # in Loop: Header=BB1_5 Depth=1
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z4stepPKiPi, %edi
movq %r15, %r9
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_7
.LBB1_8: # %.preheader
xorl %eax, %eax
movq (%rsp), %rcx
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_9: # =>This Inner Loop Header: Depth=1
addl (%rcx,%rax,4), %ebx
incq %rax
cmpq $67600, %rax # imm = 0x10810
jne .LBB1_9
# %bb.10:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4stepPKiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4stepPKiPi,@object # @_Z4stepPKiPi
.section .rodata,"a",@progbits
.globl _Z4stepPKiPi
.p2align 3, 0x0
_Z4stepPKiPi:
.quad _Z19__device_stub__stepPKiPi
.size _Z4stepPKiPi, 8
.type .L__const.main.initial_grid,@object # @__const.main.initial_grid
.p2align 4, 0x0
.L__const.main.initial_grid:
.long 1 # 0x1
.long 1 # 0x1
.long 0 # 0x0
.long 0 # 0x0
.long 1 # 0x1
.long 0 # 0x0
.long 1 # 0x1
.long 0 # 0x0
.long 1 # 0x1
.long 1 # 0x1
.long 1 # 0x1
.long 0 # 0x0
.long 1 # 0x1
.long 0 # 0x0
.long 1 # 0x1
.long 1 # 0x1
.long 0 # 0x0
.long 0 # 0x0
.long 1 # 0x1
.long 1 # 0x1
.long 1 # 0x1
.long 0 # 0x0
.long 0 # 0x0
.long 1 # 0x1
.long 0 # 0x0
.long 1 # 0x1
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 1 # 0x1
.long 1 # 0x1
.long 0 # 0x0
.long 1 # 0x1
.long 0 # 0x0
.long 0 # 0x0
.long 1 # 0x1
.long 1 # 0x1
.long 1 # 0x1
.long 1 # 0x1
.long 1 # 0x1
.long 1 # 0x1
.long 1 # 0x1
.long 1 # 0x1
.long 1 # 0x1
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 1 # 0x1
.long 1 # 0x1
.long 1 # 0x1
.long 1 # 0x1
.long 1 # 0x1
.long 1 # 0x1
.long 1 # 0x1
.long 0 # 0x0
.long 1 # 0x1
.long 0 # 0x0
.long 1 # 0x1
.long 1 # 0x1
.long 0 # 0x0
.long 1 # 0x1
.long 0 # 0x0
.long 1 # 0x1
.size .L__const.main.initial_grid, 256
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Active: "
.size .L.str, 9
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\n"
.size .L.str.1, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4stepPKiPi"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__stepPKiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4stepPKiPi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
using namespace std;
#include <thrust/reduce.h>
#include <thrust/sequence.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
__global__ void fillKernel(int *a,int n)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < n) a[tid] = tid;
}
void fill(int * d_a, int n)
{
int nThreadPerBlock = 512;
int nBlocks = n / nThreadPerBlock + ((n%nThreadPerBlock)?1:0);
fillKernel <<< nBlocks, nThreadPerBlock >>> (d_a, n);
}
int main()
{
const int N = 50000;
thrust::device_vector<int> a(N);
fill(thrust::raw_pointer_cast(&a[0]), N);
int sumA = thrust::reduce(a.begin(), a.end(), 0);
int sumCheck = 0;
for(int i=0; i!=N; ++i)
sumCheck += i;
if(sumA == sumCheck)
cout << "Test Succeeded!" << endl;
else {
cerr << "Test FAILED!" << endl;
return 1;
}
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
#include <thrust/reduce.h>
#include <thrust/sequence.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
__global__ void fillKernel(int *a,int n)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < n) a[tid] = tid;
}
void fill(int * d_a, int n)
{
int nThreadPerBlock = 512;
int nBlocks = n / nThreadPerBlock + ((n%nThreadPerBlock)?1:0);
fillKernel <<< nBlocks, nThreadPerBlock >>> (d_a, n);
}
int main()
{
const int N = 50000;
thrust::device_vector<int> a(N);
fill(thrust::raw_pointer_cast(&a[0]), N);
int sumA = thrust::reduce(a.begin(), a.end(), 0);
int sumCheck = 0;
for(int i=0; i!=N; ++i)
sumCheck += i;
if(sumA == sumCheck)
cout << "Test Succeeded!" << endl;
else {
cerr << "Test FAILED!" << endl;
return 1;
}
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#define WEIGHTSUM 273
#define BLOCK_SIZE 16
int * heatmap;
size_t heatmap_pitch;
int * scaled_heatmap;
size_t scaled_heatmap_pitch;
int * blurred_heatmap;
size_t blurred_heatmap_pitch;
float* d_desiredPositionX;
float* d_desiredPositionY;
__global__ void computeScaledHeatmap(int* heatmap, size_t heatmap_pitch, int* scaled_heatmap, size_t scaled_heatmap_pitch) {
// Block row and column
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
// Thread row and column block
int row = threadIdx.y;
int col = threadIdx.x;
// x, y coordinate
int x = blockCol * blockDim.x + col;
int y = blockRow * blockDim.y + row;
// Scale the data for visual representation
int value = *((int*)((char*)heatmap + y * heatmap_pitch) + x);
for (int r = 0; r < CELLSIZE; r++) {
int* row = (int*)((char*)scaled_heatmap + (r + y * CELLSIZE) * scaled_heatmap_pitch);
for (int c = 0; c < CELLSIZE; c++) {
row[x * CELLSIZE + c] = value;
}
}
} | code for sm_80
Function : _Z20computeScaledHeatmapPimS_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*0020*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002200 */
/*0050*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0060*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e620000002100 */
/*0070*/ IMAD R3, R3, c[0x0][0x4], R0 ; /* 0x0000010003037a24 */
/* 0x001fc800078e0200 */
/*0080*/ IMAD.WIDE.U32 R4, R3, R4, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fe200078e0004 */
/*0090*/ SHF.R.S32.HI R0, RZ, 0x1f, R3 ; /* 0x0000001fff007819 */
/* 0x000fc60000011403 */
/*00a0*/ IMAD R2, R2, c[0x0][0x0], R7 ; /* 0x0000000002027a24 */
/* 0x002fe400078e0207 */
/*00b0*/ IMAD R0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000007a24 */
/* 0x000fc800078e02ff */
/*00c0*/ IMAD R9, R3, c[0x0][0x16c], R0 ; /* 0x00005b0003097a24 */
/* 0x000fca00078e0200 */
/*00d0*/ IADD3 R5, R5, R9, RZ ; /* 0x0000000905057210 */
/* 0x000fca0007ffe0ff */
/*00e0*/ IMAD.WIDE R4, R2, 0x4, R4 ; /* 0x0000000402047825 */
/* 0x000fca00078e0204 */
/*00f0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x0000a2000c1e1900 */
/*0100*/ LEA R6, R3, R3, 0x2 ; /* 0x0000000303067211 */
/* 0x000fe400078e10ff */
/*0110*/ MOV R3, c[0x0][0x178] ; /* 0x00005e0000037a02 */
/* 0x000fe40000000f00 */
/*0120*/ SHF.R.S32.HI R7, RZ, 0x1f, R6 ; /* 0x0000001fff077819 */
/* 0x000fe40000011406 */
/*0130*/ IADD3 R10, R6.reuse, 0x3, RZ ; /* 0x00000003060a7810 */
/* 0x040fe40007ffe0ff */
/*0140*/ IADD3 R8, R6.reuse, 0x1, RZ ; /* 0x0000000106087810 */
/* 0x040fe20007ffe0ff */
/*0150*/ IMAD R11, R7, c[0x0][0x178], RZ ; /* 0x00005e00070b7a24 */
/* 0x000fe200078e02ff */
/*0160*/ IADD3 R14, R6.reuse, 0x2, RZ ; /* 0x00000002060e7810 */
/* 0x040fe20007ffe0ff */
/*0170*/ IMAD.WIDE.U32 R4, R6.reuse, R3, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x041fe200078e0003 */
/*0180*/ IADD3 R12, R6, 0x4, RZ ; /* 0x00000004060c7810 */
/* 0x000fc40007ffe0ff */
/*0190*/ SHF.R.S32.HI R7, RZ, 0x1f, R8 ; /* 0x0000001fff077819 */
/* 0x000fe20000011408 */
/*01a0*/ IMAD R15, R6, c[0x0][0x17c], R11 ; /* 0x00005f00060f7a24 */
/* 0x000fe200078e020b */
/*01b0*/ SHF.R.S32.HI R11, RZ, 0x1f, R10 ; /* 0x0000001fff0b7819 */
/* 0x000fe4000001140a */
/*01c0*/ SHF.R.S32.HI R9, RZ, 0x1f, R14 ; /* 0x0000001fff097819 */
/* 0x000fe2000001140e */
/*01d0*/ IMAD R7, R7, c[0x0][0x178], RZ ; /* 0x00005e0007077a24 */
/* 0x000fe200078e02ff */
/*01e0*/ SHF.R.S32.HI R13, RZ, 0x1f, R12 ; /* 0x0000001fff0d7819 */
/* 0x000fe2000001140c */
/*01f0*/ IMAD R11, R11, c[0x0][0x178], RZ ; /* 0x00005e000b0b7a24 */
/* 0x000fe200078e02ff */
/*0200*/ IADD3 R5, R5, R15, RZ ; /* 0x0000000f05057210 */
/* 0x000fe20007ffe0ff */
/*0210*/ IMAD R9, R9, c[0x0][0x178], RZ ; /* 0x00005e0009097a24 */
/* 0x000fe400078e02ff */
/*0220*/ IMAD R15, R10, c[0x0][0x17c], R11 ; /* 0x00005f000a0f7a24 */
/* 0x000fc400078e020b */
/*0230*/ IMAD R13, R13, c[0x0][0x178], RZ ; /* 0x00005e000d0d7a24 */
/* 0x000fe400078e02ff */
/*0240*/ IMAD.WIDE.U32 R10, R10, R3, c[0x0][0x170] ; /* 0x00005c000a0a7625 */
/* 0x000fc800078e0003 */
/*0250*/ IMAD R17, R8.reuse, c[0x0][0x17c], R7 ; /* 0x00005f0008117a24 */
/* 0x040fe200078e0207 */
/*0260*/ IADD3 R11, R11, R15, RZ ; /* 0x0000000f0b0b7210 */
/* 0x000fe20007ffe0ff */
/*0270*/ IMAD.WIDE.U32 R6, R8, R3, c[0x0][0x170] ; /* 0x00005c0008067625 */
/* 0x000fe200078e0003 */
/*0280*/ LEA R15, R2, R2, 0x2 ; /* 0x00000002020f7211 */
/* 0x000fc600078e10ff */
/*0290*/ IMAD R19, R14.reuse, c[0x0][0x17c], R9 ; /* 0x00005f000e137a24 */
/* 0x040fe200078e0209 */
/*02a0*/ IADD3 R7, R7, R17, RZ ; /* 0x0000001107077210 */
/* 0x000fe20007ffe0ff */
/*02b0*/ IMAD.WIDE.U32 R8, R14, R3, c[0x0][0x170] ; /* 0x00005c000e087625 */
/* 0x000fc800078e0003 */
/*02c0*/ IMAD R21, R12.reuse, c[0x0][0x17c], R13 ; /* 0x00005f000c157a24 */
/* 0x040fe200078e020d */
/*02d0*/ IADD3 R9, R9, R19, RZ ; /* 0x0000001309097210 */
/* 0x000fe20007ffe0ff */
/*02e0*/ IMAD.WIDE.U32 R12, R12, R3, c[0x0][0x170] ; /* 0x00005c000c0c7625 */
/* 0x000fc800078e0003 */
/*02f0*/ IMAD.WIDE R4, R15, 0x4, R4 ; /* 0x000000040f047825 */
/* 0x000fe200078e0204 */
/*0300*/ IADD3 R13, R13, R21, RZ ; /* 0x000000150d0d7210 */
/* 0x000fc60007ffe0ff */
/*0310*/ IMAD.WIDE R6, R15, 0x4, R6 ; /* 0x000000040f067825 */
/* 0x000fc800078e0206 */
/*0320*/ IMAD.WIDE R2, R15, 0x4, R8 ; /* 0x000000040f027825 */
/* 0x000fc800078e0208 */
/*0330*/ IMAD.WIDE R8, R15, 0x4, R10 ; /* 0x000000040f087825 */
/* 0x000fc800078e020a */
/*0340*/ IMAD.WIDE R10, R15, 0x4, R12 ; /* 0x000000040f0a7825 */
/* 0x000fe200078e020c */
/*0350*/ STG.E [R4.64], R0 ; /* 0x0000000004007986 */
/* 0x004fe8000c101904 */
/*0360*/ STG.E [R4.64+0x4], R0 ; /* 0x0000040004007986 */
/* 0x000fe8000c101904 */
/*0370*/ STG.E [R4.64+0x8], R0 ; /* 0x0000080004007986 */
/* 0x000fe8000c101904 */
/*0380*/ STG.E [R4.64+0xc], R0 ; /* 0x00000c0004007986 */
/* 0x000fe8000c101904 */
/*0390*/ STG.E [R4.64+0x10], R0 ; /* 0x0000100004007986 */
/* 0x000fe8000c101904 */
/*03a0*/ STG.E [R6.64], R0 ; /* 0x0000000006007986 */
/* 0x000fe8000c101904 */
/*03b0*/ STG.E [R6.64+0x4], R0 ; /* 0x0000040006007986 */
/* 0x000fe8000c101904 */
/*03c0*/ STG.E [R6.64+0x8], R0 ; /* 0x0000080006007986 */
/* 0x000fe8000c101904 */
/*03d0*/ STG.E [R6.64+0xc], R0 ; /* 0x00000c0006007986 */
/* 0x000fe8000c101904 */
/*03e0*/ STG.E [R6.64+0x10], R0 ; /* 0x0000100006007986 */
/* 0x000fe8000c101904 */
/*03f0*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe8000c101904 */
/*0400*/ STG.E [R2.64+0x4], R0 ; /* 0x0000040002007986 */
/* 0x000fe8000c101904 */
/*0410*/ STG.E [R2.64+0x8], R0 ; /* 0x0000080002007986 */
/* 0x000fe8000c101904 */
/*0420*/ STG.E [R2.64+0xc], R0 ; /* 0x00000c0002007986 */
/* 0x000fe8000c101904 */
/*0430*/ STG.E [R2.64+0x10], R0 ; /* 0x0000100002007986 */
/* 0x000fe8000c101904 */
/*0440*/ STG.E [R8.64], R0 ; /* 0x0000000008007986 */
/* 0x000fe8000c101904 */
/*0450*/ STG.E [R8.64+0x4], R0 ; /* 0x0000040008007986 */
/* 0x000fe8000c101904 */
/*0460*/ STG.E [R8.64+0x8], R0 ; /* 0x0000080008007986 */
/* 0x000fe8000c101904 */
/*0470*/ STG.E [R8.64+0xc], R0 ; /* 0x00000c0008007986 */
/* 0x000fe8000c101904 */
/*0480*/ STG.E [R8.64+0x10], R0 ; /* 0x0000100008007986 */
/* 0x000fe8000c101904 */
/*0490*/ STG.E [R10.64], R0 ; /* 0x000000000a007986 */
/* 0x000fe8000c101904 */
/*04a0*/ STG.E [R10.64+0x4], R0 ; /* 0x000004000a007986 */
/* 0x000fe8000c101904 */
/*04b0*/ STG.E [R10.64+0x8], R0 ; /* 0x000008000a007986 */
/* 0x000fe8000c101904 */
/*04c0*/ STG.E [R10.64+0xc], R0 ; /* 0x00000c000a007986 */
/* 0x000fe8000c101904 */
/*04d0*/ STG.E [R10.64+0x10], R0 ; /* 0x000010000a007986 */
/* 0x000fe2000c101904 */
/*04e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04f0*/ BRA 0x4f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define WEIGHTSUM 273
#define BLOCK_SIZE 16
int * heatmap;
size_t heatmap_pitch;
int * scaled_heatmap;
size_t scaled_heatmap_pitch;
int * blurred_heatmap;
size_t blurred_heatmap_pitch;
float* d_desiredPositionX;
float* d_desiredPositionY;
__global__ void computeScaledHeatmap(int* heatmap, size_t heatmap_pitch, int* scaled_heatmap, size_t scaled_heatmap_pitch) {
// Block row and column
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
// Thread row and column block
int row = threadIdx.y;
int col = threadIdx.x;
// x, y coordinate
int x = blockCol * blockDim.x + col;
int y = blockRow * blockDim.y + row;
// Scale the data for visual representation
int value = *((int*)((char*)heatmap + y * heatmap_pitch) + x);
for (int r = 0; r < CELLSIZE; r++) {
int* row = (int*)((char*)scaled_heatmap + (r + y * CELLSIZE) * scaled_heatmap_pitch);
for (int c = 0; c < CELLSIZE; c++) {
row[x * CELLSIZE + c] = value;
}
}
} | .file "tmpxft_0019c081_00000000-6_computeScaledHeatmap.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z20computeScaledHeatmapPimS_mPimS_m
.type _Z44__device_stub__Z20computeScaledHeatmapPimS_mPimS_m, @function
_Z44__device_stub__Z20computeScaledHeatmapPimS_mPimS_m:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20computeScaledHeatmapPimS_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z20computeScaledHeatmapPimS_mPimS_m, .-_Z44__device_stub__Z20computeScaledHeatmapPimS_mPimS_m
.globl _Z20computeScaledHeatmapPimS_m
.type _Z20computeScaledHeatmapPimS_m, @function
_Z20computeScaledHeatmapPimS_m:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z20computeScaledHeatmapPimS_mPimS_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20computeScaledHeatmapPimS_m, .-_Z20computeScaledHeatmapPimS_m
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20computeScaledHeatmapPimS_m"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20computeScaledHeatmapPimS_m(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl d_desiredPositionY
.bss
.align 8
.type d_desiredPositionY, @object
.size d_desiredPositionY, 8
d_desiredPositionY:
.zero 8
.globl d_desiredPositionX
.align 8
.type d_desiredPositionX, @object
.size d_desiredPositionX, 8
d_desiredPositionX:
.zero 8
.globl blurred_heatmap_pitch
.align 8
.type blurred_heatmap_pitch, @object
.size blurred_heatmap_pitch, 8
blurred_heatmap_pitch:
.zero 8
.globl blurred_heatmap
.align 8
.type blurred_heatmap, @object
.size blurred_heatmap, 8
blurred_heatmap:
.zero 8
.globl scaled_heatmap_pitch
.align 8
.type scaled_heatmap_pitch, @object
.size scaled_heatmap_pitch, 8
scaled_heatmap_pitch:
.zero 8
.globl scaled_heatmap
.align 8
.type scaled_heatmap, @object
.size scaled_heatmap, 8
scaled_heatmap:
.zero 8
.globl heatmap_pitch
.align 8
.type heatmap_pitch, @object
.size heatmap_pitch, 8
heatmap_pitch:
.zero 8
.globl heatmap
.align 8
.type heatmap, @object
.size heatmap, 8
heatmap:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define WEIGHTSUM 273
#define BLOCK_SIZE 16
int * heatmap;
size_t heatmap_pitch;
int * scaled_heatmap;
size_t scaled_heatmap_pitch;
int * blurred_heatmap;
size_t blurred_heatmap_pitch;
float* d_desiredPositionX;
float* d_desiredPositionY;
__global__ void computeScaledHeatmap(int* heatmap, size_t heatmap_pitch, int* scaled_heatmap, size_t scaled_heatmap_pitch) {
// Block row and column
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
// Thread row and column block
int row = threadIdx.y;
int col = threadIdx.x;
// x, y coordinate
int x = blockCol * blockDim.x + col;
int y = blockRow * blockDim.y + row;
// Scale the data for visual representation
int value = *((int*)((char*)heatmap + y * heatmap_pitch) + x);
for (int r = 0; r < CELLSIZE; r++) {
int* row = (int*)((char*)scaled_heatmap + (r + y * CELLSIZE) * scaled_heatmap_pitch);
for (int c = 0; c < CELLSIZE; c++) {
row[x * CELLSIZE + c] = value;
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define WEIGHTSUM 273
#define BLOCK_SIZE 16
int * heatmap;
size_t heatmap_pitch;
int * scaled_heatmap;
size_t scaled_heatmap_pitch;
int * blurred_heatmap;
size_t blurred_heatmap_pitch;
float* d_desiredPositionX;
float* d_desiredPositionY;
__global__ void computeScaledHeatmap(int* heatmap, size_t heatmap_pitch, int* scaled_heatmap, size_t scaled_heatmap_pitch) {
// Block row and column
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
// Thread row and column block
int row = threadIdx.y;
int col = threadIdx.x;
// x, y coordinate
int x = blockCol * blockDim.x + col;
int y = blockRow * blockDim.y + row;
// Scale the data for visual representation
int value = *((int*)((char*)heatmap + y * heatmap_pitch) + x);
for (int r = 0; r < CELLSIZE; r++) {
int* row = (int*)((char*)scaled_heatmap + (r + y * CELLSIZE) * scaled_heatmap_pitch);
for (int c = 0; c < CELLSIZE; c++) {
row[x * CELLSIZE + c] = value;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define WEIGHTSUM 273
#define BLOCK_SIZE 16
int * heatmap;
size_t heatmap_pitch;
int * scaled_heatmap;
size_t scaled_heatmap_pitch;
int * blurred_heatmap;
size_t blurred_heatmap_pitch;
float* d_desiredPositionX;
float* d_desiredPositionY;
__global__ void computeScaledHeatmap(int* heatmap, size_t heatmap_pitch, int* scaled_heatmap, size_t scaled_heatmap_pitch) {
// Block row and column
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
// Thread row and column block
int row = threadIdx.y;
int col = threadIdx.x;
// x, y coordinate
int x = blockCol * blockDim.x + col;
int y = blockRow * blockDim.y + row;
// Scale the data for visual representation
int value = *((int*)((char*)heatmap + y * heatmap_pitch) + x);
for (int r = 0; r < CELLSIZE; r++) {
int* row = (int*)((char*)scaled_heatmap + (r + y * CELLSIZE) * scaled_heatmap_pitch);
for (int c = 0; c < CELLSIZE; c++) {
row[x * CELLSIZE + c] = value;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20computeScaledHeatmapPimS_m
.globl _Z20computeScaledHeatmapPimS_m
.p2align 8
.type _Z20computeScaledHeatmapPimS_m,@function
_Z20computeScaledHeatmapPimS_m:
s_clause 0x1
s_load_b32 s8, s[0:1], 0x2c
s_load_b256 s[0:7], s[0:1], 0x0
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s9, s8, 16
s_and_b32 s8, s8, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s9, v[1:2]
v_mad_u64_u32 v[3:4], null, s14, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v4, 31, v2
v_mul_lo_u32 v6, v2, s3
v_mad_u64_u32 v[0:1], null, v2, s2, s[0:1]
v_mul_lo_u32 v7, v4, s2
v_ashrrev_i32_e32 v4, 31, v3
s_mov_b32 s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[4:5], 2, v[3:4]
v_add3_u32 v1, v7, v1, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v4
v_add_co_ci_u32_e32 v1, vcc_lo, v1, v5, vcc_lo
v_lshl_add_u32 v5, v2, 2, v2
global_load_b32 v0, v[0:1], off
v_lshl_add_u32 v1, v3, 2, v3
v_ashrrev_i32_e32 v3, 31, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_mul_lo_u32 v6, s6, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_mad_u64_u32 v[3:4], null, s6, v5, v[1:2]
v_mul_lo_u32 v1, s7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add3_u32 v2, v1, v4, v6
v_add_co_u32 v1, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
.LBB0_1:
s_mov_b64 s[0:1], 0
.LBB0_2:
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_add_co_u32 v3, vcc_lo, v1, s0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v2, vcc_lo
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_eq_u32 s0, 20
s_waitcnt vmcnt(0)
global_store_b32 v[3:4], v0, off
s_cbranch_scc0 .LBB0_2
v_add_co_u32 v1, vcc_lo, v1, s6
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
s_add_i32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 5
s_cbranch_scc0 .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20computeScaledHeatmapPimS_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20computeScaledHeatmapPimS_m, .Lfunc_end0-_Z20computeScaledHeatmapPimS_m
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20computeScaledHeatmapPimS_m
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20computeScaledHeatmapPimS_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define WEIGHTSUM 273
#define BLOCK_SIZE 16
int * heatmap;
size_t heatmap_pitch;
int * scaled_heatmap;
size_t scaled_heatmap_pitch;
int * blurred_heatmap;
size_t blurred_heatmap_pitch;
float* d_desiredPositionX;
float* d_desiredPositionY;
__global__ void computeScaledHeatmap(int* heatmap, size_t heatmap_pitch, int* scaled_heatmap, size_t scaled_heatmap_pitch) {
// Block row and column
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
// Thread row and column block
int row = threadIdx.y;
int col = threadIdx.x;
// x, y coordinate
int x = blockCol * blockDim.x + col;
int y = blockRow * blockDim.y + row;
// Scale the data for visual representation
int value = *((int*)((char*)heatmap + y * heatmap_pitch) + x);
for (int r = 0; r < CELLSIZE; r++) {
int* row = (int*)((char*)scaled_heatmap + (r + y * CELLSIZE) * scaled_heatmap_pitch);
for (int c = 0; c < CELLSIZE; c++) {
row[x * CELLSIZE + c] = value;
}
}
} | .text
.file "computeScaledHeatmap.hip"
.globl _Z35__device_stub__computeScaledHeatmapPimS_m # -- Begin function _Z35__device_stub__computeScaledHeatmapPimS_m
.p2align 4, 0x90
.type _Z35__device_stub__computeScaledHeatmapPimS_m,@function
_Z35__device_stub__computeScaledHeatmapPimS_m: # @_Z35__device_stub__computeScaledHeatmapPimS_m
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20computeScaledHeatmapPimS_m, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z35__device_stub__computeScaledHeatmapPimS_m, .Lfunc_end0-_Z35__device_stub__computeScaledHeatmapPimS_m
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20computeScaledHeatmapPimS_m, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type heatmap,@object # @heatmap
.bss
.globl heatmap
.p2align 3, 0x0
heatmap:
.quad 0
.size heatmap, 8
.type heatmap_pitch,@object # @heatmap_pitch
.globl heatmap_pitch
.p2align 3, 0x0
heatmap_pitch:
.quad 0 # 0x0
.size heatmap_pitch, 8
.type scaled_heatmap,@object # @scaled_heatmap
.globl scaled_heatmap
.p2align 3, 0x0
scaled_heatmap:
.quad 0
.size scaled_heatmap, 8
.type scaled_heatmap_pitch,@object # @scaled_heatmap_pitch
.globl scaled_heatmap_pitch
.p2align 3, 0x0
scaled_heatmap_pitch:
.quad 0 # 0x0
.size scaled_heatmap_pitch, 8
.type blurred_heatmap,@object # @blurred_heatmap
.globl blurred_heatmap
.p2align 3, 0x0
blurred_heatmap:
.quad 0
.size blurred_heatmap, 8
.type blurred_heatmap_pitch,@object # @blurred_heatmap_pitch
.globl blurred_heatmap_pitch
.p2align 3, 0x0
blurred_heatmap_pitch:
.quad 0 # 0x0
.size blurred_heatmap_pitch, 8
.type d_desiredPositionX,@object # @d_desiredPositionX
.globl d_desiredPositionX
.p2align 3, 0x0
d_desiredPositionX:
.quad 0
.size d_desiredPositionX, 8
.type d_desiredPositionY,@object # @d_desiredPositionY
.globl d_desiredPositionY
.p2align 3, 0x0
d_desiredPositionY:
.quad 0
.size d_desiredPositionY, 8
.type _Z20computeScaledHeatmapPimS_m,@object # @_Z20computeScaledHeatmapPimS_m
.section .rodata,"a",@progbits
.globl _Z20computeScaledHeatmapPimS_m
.p2align 3, 0x0
_Z20computeScaledHeatmapPimS_m:
.quad _Z35__device_stub__computeScaledHeatmapPimS_m
.size _Z20computeScaledHeatmapPimS_m, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20computeScaledHeatmapPimS_m"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__computeScaledHeatmapPimS_m
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20computeScaledHeatmapPimS_m
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z20computeScaledHeatmapPimS_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*0020*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002200 */
/*0050*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0060*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e620000002100 */
/*0070*/ IMAD R3, R3, c[0x0][0x4], R0 ; /* 0x0000010003037a24 */
/* 0x001fc800078e0200 */
/*0080*/ IMAD.WIDE.U32 R4, R3, R4, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fe200078e0004 */
/*0090*/ SHF.R.S32.HI R0, RZ, 0x1f, R3 ; /* 0x0000001fff007819 */
/* 0x000fc60000011403 */
/*00a0*/ IMAD R2, R2, c[0x0][0x0], R7 ; /* 0x0000000002027a24 */
/* 0x002fe400078e0207 */
/*00b0*/ IMAD R0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000007a24 */
/* 0x000fc800078e02ff */
/*00c0*/ IMAD R9, R3, c[0x0][0x16c], R0 ; /* 0x00005b0003097a24 */
/* 0x000fca00078e0200 */
/*00d0*/ IADD3 R5, R5, R9, RZ ; /* 0x0000000905057210 */
/* 0x000fca0007ffe0ff */
/*00e0*/ IMAD.WIDE R4, R2, 0x4, R4 ; /* 0x0000000402047825 */
/* 0x000fca00078e0204 */
/*00f0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x0000a2000c1e1900 */
/*0100*/ LEA R6, R3, R3, 0x2 ; /* 0x0000000303067211 */
/* 0x000fe400078e10ff */
/*0110*/ MOV R3, c[0x0][0x178] ; /* 0x00005e0000037a02 */
/* 0x000fe40000000f00 */
/*0120*/ SHF.R.S32.HI R7, RZ, 0x1f, R6 ; /* 0x0000001fff077819 */
/* 0x000fe40000011406 */
/*0130*/ IADD3 R10, R6.reuse, 0x3, RZ ; /* 0x00000003060a7810 */
/* 0x040fe40007ffe0ff */
/*0140*/ IADD3 R8, R6.reuse, 0x1, RZ ; /* 0x0000000106087810 */
/* 0x040fe20007ffe0ff */
/*0150*/ IMAD R11, R7, c[0x0][0x178], RZ ; /* 0x00005e00070b7a24 */
/* 0x000fe200078e02ff */
/*0160*/ IADD3 R14, R6.reuse, 0x2, RZ ; /* 0x00000002060e7810 */
/* 0x040fe20007ffe0ff */
/*0170*/ IMAD.WIDE.U32 R4, R6.reuse, R3, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x041fe200078e0003 */
/*0180*/ IADD3 R12, R6, 0x4, RZ ; /* 0x00000004060c7810 */
/* 0x000fc40007ffe0ff */
/*0190*/ SHF.R.S32.HI R7, RZ, 0x1f, R8 ; /* 0x0000001fff077819 */
/* 0x000fe20000011408 */
/*01a0*/ IMAD R15, R6, c[0x0][0x17c], R11 ; /* 0x00005f00060f7a24 */
/* 0x000fe200078e020b */
/*01b0*/ SHF.R.S32.HI R11, RZ, 0x1f, R10 ; /* 0x0000001fff0b7819 */
/* 0x000fe4000001140a */
/*01c0*/ SHF.R.S32.HI R9, RZ, 0x1f, R14 ; /* 0x0000001fff097819 */
/* 0x000fe2000001140e */
/*01d0*/ IMAD R7, R7, c[0x0][0x178], RZ ; /* 0x00005e0007077a24 */
/* 0x000fe200078e02ff */
/*01e0*/ SHF.R.S32.HI R13, RZ, 0x1f, R12 ; /* 0x0000001fff0d7819 */
/* 0x000fe2000001140c */
/*01f0*/ IMAD R11, R11, c[0x0][0x178], RZ ; /* 0x00005e000b0b7a24 */
/* 0x000fe200078e02ff */
/*0200*/ IADD3 R5, R5, R15, RZ ; /* 0x0000000f05057210 */
/* 0x000fe20007ffe0ff */
/*0210*/ IMAD R9, R9, c[0x0][0x178], RZ ; /* 0x00005e0009097a24 */
/* 0x000fe400078e02ff */
/*0220*/ IMAD R15, R10, c[0x0][0x17c], R11 ; /* 0x00005f000a0f7a24 */
/* 0x000fc400078e020b */
/*0230*/ IMAD R13, R13, c[0x0][0x178], RZ ; /* 0x00005e000d0d7a24 */
/* 0x000fe400078e02ff */
/*0240*/ IMAD.WIDE.U32 R10, R10, R3, c[0x0][0x170] ; /* 0x00005c000a0a7625 */
/* 0x000fc800078e0003 */
/*0250*/ IMAD R17, R8.reuse, c[0x0][0x17c], R7 ; /* 0x00005f0008117a24 */
/* 0x040fe200078e0207 */
/*0260*/ IADD3 R11, R11, R15, RZ ; /* 0x0000000f0b0b7210 */
/* 0x000fe20007ffe0ff */
/*0270*/ IMAD.WIDE.U32 R6, R8, R3, c[0x0][0x170] ; /* 0x00005c0008067625 */
/* 0x000fe200078e0003 */
/*0280*/ LEA R15, R2, R2, 0x2 ; /* 0x00000002020f7211 */
/* 0x000fc600078e10ff */
/*0290*/ IMAD R19, R14.reuse, c[0x0][0x17c], R9 ; /* 0x00005f000e137a24 */
/* 0x040fe200078e0209 */
/*02a0*/ IADD3 R7, R7, R17, RZ ; /* 0x0000001107077210 */
/* 0x000fe20007ffe0ff */
/*02b0*/ IMAD.WIDE.U32 R8, R14, R3, c[0x0][0x170] ; /* 0x00005c000e087625 */
/* 0x000fc800078e0003 */
/*02c0*/ IMAD R21, R12.reuse, c[0x0][0x17c], R13 ; /* 0x00005f000c157a24 */
/* 0x040fe200078e020d */
/*02d0*/ IADD3 R9, R9, R19, RZ ; /* 0x0000001309097210 */
/* 0x000fe20007ffe0ff */
/*02e0*/ IMAD.WIDE.U32 R12, R12, R3, c[0x0][0x170] ; /* 0x00005c000c0c7625 */
/* 0x000fc800078e0003 */
/*02f0*/ IMAD.WIDE R4, R15, 0x4, R4 ; /* 0x000000040f047825 */
/* 0x000fe200078e0204 */
/*0300*/ IADD3 R13, R13, R21, RZ ; /* 0x000000150d0d7210 */
/* 0x000fc60007ffe0ff */
/*0310*/ IMAD.WIDE R6, R15, 0x4, R6 ; /* 0x000000040f067825 */
/* 0x000fc800078e0206 */
/*0320*/ IMAD.WIDE R2, R15, 0x4, R8 ; /* 0x000000040f027825 */
/* 0x000fc800078e0208 */
/*0330*/ IMAD.WIDE R8, R15, 0x4, R10 ; /* 0x000000040f087825 */
/* 0x000fc800078e020a */
/*0340*/ IMAD.WIDE R10, R15, 0x4, R12 ; /* 0x000000040f0a7825 */
/* 0x000fe200078e020c */
/*0350*/ STG.E [R4.64], R0 ; /* 0x0000000004007986 */
/* 0x004fe8000c101904 */
/*0360*/ STG.E [R4.64+0x4], R0 ; /* 0x0000040004007986 */
/* 0x000fe8000c101904 */
/*0370*/ STG.E [R4.64+0x8], R0 ; /* 0x0000080004007986 */
/* 0x000fe8000c101904 */
/*0380*/ STG.E [R4.64+0xc], R0 ; /* 0x00000c0004007986 */
/* 0x000fe8000c101904 */
/*0390*/ STG.E [R4.64+0x10], R0 ; /* 0x0000100004007986 */
/* 0x000fe8000c101904 */
/*03a0*/ STG.E [R6.64], R0 ; /* 0x0000000006007986 */
/* 0x000fe8000c101904 */
/*03b0*/ STG.E [R6.64+0x4], R0 ; /* 0x0000040006007986 */
/* 0x000fe8000c101904 */
/*03c0*/ STG.E [R6.64+0x8], R0 ; /* 0x0000080006007986 */
/* 0x000fe8000c101904 */
/*03d0*/ STG.E [R6.64+0xc], R0 ; /* 0x00000c0006007986 */
/* 0x000fe8000c101904 */
/*03e0*/ STG.E [R6.64+0x10], R0 ; /* 0x0000100006007986 */
/* 0x000fe8000c101904 */
/*03f0*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe8000c101904 */
/*0400*/ STG.E [R2.64+0x4], R0 ; /* 0x0000040002007986 */
/* 0x000fe8000c101904 */
/*0410*/ STG.E [R2.64+0x8], R0 ; /* 0x0000080002007986 */
/* 0x000fe8000c101904 */
/*0420*/ STG.E [R2.64+0xc], R0 ; /* 0x00000c0002007986 */
/* 0x000fe8000c101904 */
/*0430*/ STG.E [R2.64+0x10], R0 ; /* 0x0000100002007986 */
/* 0x000fe8000c101904 */
/*0440*/ STG.E [R8.64], R0 ; /* 0x0000000008007986 */
/* 0x000fe8000c101904 */
/*0450*/ STG.E [R8.64+0x4], R0 ; /* 0x0000040008007986 */
/* 0x000fe8000c101904 */
/*0460*/ STG.E [R8.64+0x8], R0 ; /* 0x0000080008007986 */
/* 0x000fe8000c101904 */
/*0470*/ STG.E [R8.64+0xc], R0 ; /* 0x00000c0008007986 */
/* 0x000fe8000c101904 */
/*0480*/ STG.E [R8.64+0x10], R0 ; /* 0x0000100008007986 */
/* 0x000fe8000c101904 */
/*0490*/ STG.E [R10.64], R0 ; /* 0x000000000a007986 */
/* 0x000fe8000c101904 */
/*04a0*/ STG.E [R10.64+0x4], R0 ; /* 0x000004000a007986 */
/* 0x000fe8000c101904 */
/*04b0*/ STG.E [R10.64+0x8], R0 ; /* 0x000008000a007986 */
/* 0x000fe8000c101904 */
/*04c0*/ STG.E [R10.64+0xc], R0 ; /* 0x00000c000a007986 */
/* 0x000fe8000c101904 */
/*04d0*/ STG.E [R10.64+0x10], R0 ; /* 0x000010000a007986 */
/* 0x000fe2000c101904 */
/*04e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04f0*/ BRA 0x4f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20computeScaledHeatmapPimS_m
.globl _Z20computeScaledHeatmapPimS_m
.p2align 8
.type _Z20computeScaledHeatmapPimS_m,@function
_Z20computeScaledHeatmapPimS_m:
s_clause 0x1
s_load_b32 s8, s[0:1], 0x2c
s_load_b256 s[0:7], s[0:1], 0x0
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s9, s8, 16
s_and_b32 s8, s8, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s9, v[1:2]
v_mad_u64_u32 v[3:4], null, s14, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v4, 31, v2
v_mul_lo_u32 v6, v2, s3
v_mad_u64_u32 v[0:1], null, v2, s2, s[0:1]
v_mul_lo_u32 v7, v4, s2
v_ashrrev_i32_e32 v4, 31, v3
s_mov_b32 s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[4:5], 2, v[3:4]
v_add3_u32 v1, v7, v1, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v4
v_add_co_ci_u32_e32 v1, vcc_lo, v1, v5, vcc_lo
v_lshl_add_u32 v5, v2, 2, v2
global_load_b32 v0, v[0:1], off
v_lshl_add_u32 v1, v3, 2, v3
v_ashrrev_i32_e32 v3, 31, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_mul_lo_u32 v6, s6, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_mad_u64_u32 v[3:4], null, s6, v5, v[1:2]
v_mul_lo_u32 v1, s7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add3_u32 v2, v1, v4, v6
v_add_co_u32 v1, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
.LBB0_1:
s_mov_b64 s[0:1], 0
.LBB0_2:
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_add_co_u32 v3, vcc_lo, v1, s0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v2, vcc_lo
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_eq_u32 s0, 20
s_waitcnt vmcnt(0)
global_store_b32 v[3:4], v0, off
s_cbranch_scc0 .LBB0_2
v_add_co_u32 v1, vcc_lo, v1, s6
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
s_add_i32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 5
s_cbranch_scc0 .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20computeScaledHeatmapPimS_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20computeScaledHeatmapPimS_m, .Lfunc_end0-_Z20computeScaledHeatmapPimS_m
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20computeScaledHeatmapPimS_m
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20computeScaledHeatmapPimS_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0019c081_00000000-6_computeScaledHeatmap.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z20computeScaledHeatmapPimS_mPimS_m
.type _Z44__device_stub__Z20computeScaledHeatmapPimS_mPimS_m, @function
_Z44__device_stub__Z20computeScaledHeatmapPimS_mPimS_m:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20computeScaledHeatmapPimS_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z20computeScaledHeatmapPimS_mPimS_m, .-_Z44__device_stub__Z20computeScaledHeatmapPimS_mPimS_m
.globl _Z20computeScaledHeatmapPimS_m
.type _Z20computeScaledHeatmapPimS_m, @function
_Z20computeScaledHeatmapPimS_m:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z20computeScaledHeatmapPimS_mPimS_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20computeScaledHeatmapPimS_m, .-_Z20computeScaledHeatmapPimS_m
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20computeScaledHeatmapPimS_m"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20computeScaledHeatmapPimS_m(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl d_desiredPositionY
.bss
.align 8
.type d_desiredPositionY, @object
.size d_desiredPositionY, 8
d_desiredPositionY:
.zero 8
.globl d_desiredPositionX
.align 8
.type d_desiredPositionX, @object
.size d_desiredPositionX, 8
d_desiredPositionX:
.zero 8
.globl blurred_heatmap_pitch
.align 8
.type blurred_heatmap_pitch, @object
.size blurred_heatmap_pitch, 8
blurred_heatmap_pitch:
.zero 8
.globl blurred_heatmap
.align 8
.type blurred_heatmap, @object
.size blurred_heatmap, 8
blurred_heatmap:
.zero 8
.globl scaled_heatmap_pitch
.align 8
.type scaled_heatmap_pitch, @object
.size scaled_heatmap_pitch, 8
scaled_heatmap_pitch:
.zero 8
.globl scaled_heatmap
.align 8
.type scaled_heatmap, @object
.size scaled_heatmap, 8
scaled_heatmap:
.zero 8
.globl heatmap_pitch
.align 8
.type heatmap_pitch, @object
.size heatmap_pitch, 8
heatmap_pitch:
.zero 8
.globl heatmap
.align 8
.type heatmap, @object
.size heatmap, 8
heatmap:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "computeScaledHeatmap.hip"
.globl _Z35__device_stub__computeScaledHeatmapPimS_m # -- Begin function _Z35__device_stub__computeScaledHeatmapPimS_m
.p2align 4, 0x90
.type _Z35__device_stub__computeScaledHeatmapPimS_m,@function
_Z35__device_stub__computeScaledHeatmapPimS_m: # @_Z35__device_stub__computeScaledHeatmapPimS_m
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20computeScaledHeatmapPimS_m, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z35__device_stub__computeScaledHeatmapPimS_m, .Lfunc_end0-_Z35__device_stub__computeScaledHeatmapPimS_m
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20computeScaledHeatmapPimS_m, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type heatmap,@object # @heatmap
.bss
.globl heatmap
.p2align 3, 0x0
heatmap:
.quad 0
.size heatmap, 8
.type heatmap_pitch,@object # @heatmap_pitch
.globl heatmap_pitch
.p2align 3, 0x0
heatmap_pitch:
.quad 0 # 0x0
.size heatmap_pitch, 8
.type scaled_heatmap,@object # @scaled_heatmap
.globl scaled_heatmap
.p2align 3, 0x0
scaled_heatmap:
.quad 0
.size scaled_heatmap, 8
.type scaled_heatmap_pitch,@object # @scaled_heatmap_pitch
.globl scaled_heatmap_pitch
.p2align 3, 0x0
scaled_heatmap_pitch:
.quad 0 # 0x0
.size scaled_heatmap_pitch, 8
.type blurred_heatmap,@object # @blurred_heatmap
.globl blurred_heatmap
.p2align 3, 0x0
blurred_heatmap:
.quad 0
.size blurred_heatmap, 8
.type blurred_heatmap_pitch,@object # @blurred_heatmap_pitch
.globl blurred_heatmap_pitch
.p2align 3, 0x0
blurred_heatmap_pitch:
.quad 0 # 0x0
.size blurred_heatmap_pitch, 8
.type d_desiredPositionX,@object # @d_desiredPositionX
.globl d_desiredPositionX
.p2align 3, 0x0
d_desiredPositionX:
.quad 0
.size d_desiredPositionX, 8
.type d_desiredPositionY,@object # @d_desiredPositionY
.globl d_desiredPositionY
.p2align 3, 0x0
d_desiredPositionY:
.quad 0
.size d_desiredPositionY, 8
.type _Z20computeScaledHeatmapPimS_m,@object # @_Z20computeScaledHeatmapPimS_m
.section .rodata,"a",@progbits
.globl _Z20computeScaledHeatmapPimS_m
.p2align 3, 0x0
_Z20computeScaledHeatmapPimS_m:
.quad _Z35__device_stub__computeScaledHeatmapPimS_m
.size _Z20computeScaledHeatmapPimS_m, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20computeScaledHeatmapPimS_m"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__computeScaledHeatmapPimS_m
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20computeScaledHeatmapPimS_m
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <stdio.h>
#include <math.h>
#define kx 3
#define ky 3
#define nx 224
#define ny 224
#define ni 64
#define nn 64
#define batch 64
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
void random_ints(int* a, int N)
{
int i;
for (i = 0; i < N; i++)
{
a[i] = rand();
}
}
void zeros(int* a, int N)
{
int i;
for (i = 0; i < N; i++)
{
a[i] = 0;
}
}
// CURRENT MEMORY PERFORMANCE = 5.77 GB/s
// perform a single application (matrix-vector multiply) of 1 weights matrix to a subset of a single input feature map
// the batch size (batch) determines the size of the subset
// the dimensions of the weights matrix are (kx, ky)
// the dimensions of all input and output feature maps are (nx, ny)
// the number of input feature maps is ni
// the number of output feature maps is nn
// the input and output feature maps are thus represented as 3D arrays (logically)
// the corresponding weights matrices are thus represented as a 4D array (logically)
// this is what is done in a 3D convolution layer
// this method utilizes a scratchpad memory for better thread block performance
__global__
void matrix_vector_mult(int *inp, int *outp, int *kern)
{
// scratchpad memory used for shared variables
// NOTE: must batch enough such that this data can fit in the shared memory
__shared__ int temp_kern[nn * kx * ky]; // all kernel matrices for given input feature map
__shared__ int temp_inp[nx * ny / batch]; // batched subset of given input feature map
// only 1 thread in block needs to populate all shared variables but temp_ind
if (threadIdx.x == 0) {
int hold = nn* kx * ky;
int k_start = (blockIdx.x/batch) * kx * ky; // every (batch) thread blocks use the same weights matrices
for (int j = 0; j < hold; j++) { // populate temp_kern
int t = k_start + j;
temp_kern[j] = kern[t];
}
}
int i_index = (blockIdx.x * (nx * ny / batch)) + threadIdx.x; // 1 thread block per subset of each feature map
temp_inp[threadIdx.x] = inp[i_index]; // piecemeal load in the input feature map
__syncthreads(); // sync all threads to this point - input feature map loaded
int l_start = threadIdx.x - ky/2 - (ny/(batch/2) * (kx/2));
for (int i=0; i<nn; i++) {
int out = 0;
for (int j=0; j<kx; j++) {
for (int k=0; k<ky; k++) {
int curr = l_start + (ny/(batch/2)*j) + k;
int k_index = (i*kx*ky) + (j*ky) + k;
if ((curr >= 0) && (curr <= (nx*ny/batch-1))) { // check against barriers of input feature map
out += temp_inp[curr] * temp_kern[k_index];
}
}
}
// store output
int n_index = (i * nx * ny) + threadIdx.x; // rotate through output feature maps constantly
outp[n_index] += out;
}
}
int main(void)
{
// declare host + device pointers
int *inp, *outp, *kern;
int *d_inp, *d_outp, *d_kern;
// compute array sizes
int i_size = ni*nx*ny;
int o_size = nn*nx*ny;
int k_size = nn*ni*kx*ky;
// allocate space for each array on the device
gpuErrchk( cudaMalloc(&d_inp, i_size*sizeof(int)) );
gpuErrchk( cudaMalloc(&d_outp, o_size*sizeof(int)) );
gpuErrchk( cudaMalloc(&d_kern, k_size*sizeof(int)) );
// allocate space and populate each array on the host
inp = (int*)malloc(i_size*sizeof(int));
outp = (int*)malloc(o_size*sizeof(int));
kern = (int*)malloc(k_size*sizeof(int));
random_ints(inp, i_size);
zeros(outp, o_size);
random_ints(kern, k_size);
// copy populated host arrays to corresponding device arrays
gpuErrchk( cudaMemcpy(d_inp, inp, i_size*sizeof(int), cudaMemcpyHostToDevice) );
gpuErrchk( cudaMemcpy(d_outp, outp, o_size*sizeof(int), cudaMemcpyHostToDevice) );
gpuErrchk( cudaMemcpy(d_kern, kern, k_size*sizeof(int), cudaMemcpyHostToDevice) );
// launch all threads on device
// # blocks = # input feature maps * # batches / input feature map
// # threads / block = # elements in each batch
matrix_vector_mult<<<ni*batch, nx*ny/batch>>>(d_inp, d_outp, d_kern);
// determine if run succeeded
gpuErrchk( cudaPeekAtLastError() );
gpuErrchk( cudaDeviceSynchronize() );
// copy output array back to host
gpuErrchk( cudaMemcpy(outp, d_outp, o_size, cudaMemcpyDeviceToHost) );
// free all memory
free(inp); free(outp); free(kern);
gpuErrchk( cudaFree(d_inp) ); gpuErrchk( cudaFree(d_outp) ); gpuErrchk( cudaFree(d_kern) );
return 0;
} | .file "tmpxft_00135310_00000000-6_conv1.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3675:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
.string "GPUassert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB3669:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L10
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.text
.globl _Z11random_intsPii
.type _Z11random_intsPii, @function
_Z11random_intsPii:
.LFB3670:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L16
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L13:
call rand@PLT
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L13
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE3670:
.size _Z11random_intsPii, .-_Z11random_intsPii
.globl _Z5zerosPii
.type _Z5zerosPii, @function
_Z5zerosPii:
.LFB3671:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L19
movq %rdi, %rax
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rdx
.L21:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L21
.L19:
ret
.cfi_endproc
.LFE3671:
.size _Z5zerosPii, .-_Z5zerosPii
.globl _Z42__device_stub__Z18matrix_vector_multPiS_S_PiS_S_
.type _Z42__device_stub__Z18matrix_vector_multPiS_S_PiS_S_, @function
_Z42__device_stub__Z18matrix_vector_multPiS_S_PiS_S_:
.LFB3697:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18matrix_vector_multPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z42__device_stub__Z18matrix_vector_multPiS_S_PiS_S_, .-_Z42__device_stub__Z18matrix_vector_multPiS_S_PiS_S_
.globl _Z18matrix_vector_multPiS_S_
.type _Z18matrix_vector_multPiS_S_, @function
_Z18matrix_vector_multPiS_S_:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z18matrix_vector_multPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z18matrix_vector_multPiS_S_, .-_Z18matrix_vector_multPiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/joshkimmel16/cuda-kernels/master/conv1.cu"
.text
.globl main
.type main, @function
main:
.LFB3672:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $12845056, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $107, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 16(%rsp), %rdi
movl $12845056, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $108, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 24(%rsp), %rdi
movl $147456, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $109, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $12845056, %edi
call malloc@PLT
movq %rax, %r13
movl $12845056, %edi
call malloc@PLT
movq %rax, %rbp
movl $147456, %edi
call malloc@PLT
movq %rax, %r12
movl $3211264, %esi
movq %r13, %rdi
call _Z11random_intsPii
movl $3211264, %esi
movq %rbp, %rdi
call _Z5zerosPii
movl $36864, %esi
movq %r12, %rdi
call _Z11random_intsPii
movl $1, %ecx
movl $12845056, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $120, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movl $12845056, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $121, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movl $147456, %edx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $122, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $784, 44(%rsp)
movl $1, 48(%rsp)
movl $4096, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L32:
call cudaPeekAtLastError@PLT
movl %eax, %edi
movl $1, %ecx
movl $130, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $1, %ecx
movl $131, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $2, %ecx
movl $3211264, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $134, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq %r13, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $138, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $138, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 24(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $138, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L36
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z42__device_stub__Z18matrix_vector_multPiS_S_PiS_S_
jmp .L32
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3672:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z18matrix_vector_multPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z18matrix_vector_multPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <stdio.h>
#include <math.h>
#define kx 3
#define ky 3
#define nx 224
#define ny 224
#define ni 64
#define nn 64
#define batch 64
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
void random_ints(int* a, int N)
{
int i;
for (i = 0; i < N; i++)
{
a[i] = rand();
}
}
void zeros(int* a, int N)
{
int i;
for (i = 0; i < N; i++)
{
a[i] = 0;
}
}
// CURRENT MEMORY PERFORMANCE = 5.77 GB/s
// perform a single application (matrix-vector multiply) of 1 weights matrix to a subset of a single input feature map
// the batch size (batch) determines the size of the subset
// the dimensions of the weights matrix are (kx, ky)
// the dimensions of all input and output feature maps are (nx, ny)
// the number of input feature maps is ni
// the number of output feature maps is nn
// the input and output feature maps are thus represented as 3D arrays (logically)
// the corresponding weights matrices are thus represented as a 4D array (logically)
// this is what is done in a 3D convolution layer
// this method utilizes a scratchpad memory for better thread block performance
__global__
void matrix_vector_mult(int *inp, int *outp, int *kern)
{
// scratchpad memory used for shared variables
// NOTE: must batch enough such that this data can fit in the shared memory
__shared__ int temp_kern[nn * kx * ky]; // all kernel matrices for given input feature map
__shared__ int temp_inp[nx * ny / batch]; // batched subset of given input feature map
// only 1 thread in block needs to populate all shared variables but temp_ind
if (threadIdx.x == 0) {
int hold = nn* kx * ky;
int k_start = (blockIdx.x/batch) * kx * ky; // every (batch) thread blocks use the same weights matrices
for (int j = 0; j < hold; j++) { // populate temp_kern
int t = k_start + j;
temp_kern[j] = kern[t];
}
}
int i_index = (blockIdx.x * (nx * ny / batch)) + threadIdx.x; // 1 thread block per subset of each feature map
temp_inp[threadIdx.x] = inp[i_index]; // piecemeal load in the input feature map
__syncthreads(); // sync all threads to this point - input feature map loaded
int l_start = threadIdx.x - ky/2 - (ny/(batch/2) * (kx/2));
for (int i=0; i<nn; i++) {
int out = 0;
for (int j=0; j<kx; j++) {
for (int k=0; k<ky; k++) {
int curr = l_start + (ny/(batch/2)*j) + k;
int k_index = (i*kx*ky) + (j*ky) + k;
if ((curr >= 0) && (curr <= (nx*ny/batch-1))) { // check against barriers of input feature map
out += temp_inp[curr] * temp_kern[k_index];
}
}
}
// store output
int n_index = (i * nx * ny) + threadIdx.x; // rotate through output feature maps constantly
outp[n_index] += out;
}
}
int main(void)
{
// declare host + device pointers
int *inp, *outp, *kern;
int *d_inp, *d_outp, *d_kern;
// compute array sizes
int i_size = ni*nx*ny;
int o_size = nn*nx*ny;
int k_size = nn*ni*kx*ky;
// allocate space for each array on the device
gpuErrchk( cudaMalloc(&d_inp, i_size*sizeof(int)) );
gpuErrchk( cudaMalloc(&d_outp, o_size*sizeof(int)) );
gpuErrchk( cudaMalloc(&d_kern, k_size*sizeof(int)) );
// allocate space and populate each array on the host
inp = (int*)malloc(i_size*sizeof(int));
outp = (int*)malloc(o_size*sizeof(int));
kern = (int*)malloc(k_size*sizeof(int));
random_ints(inp, i_size);
zeros(outp, o_size);
random_ints(kern, k_size);
// copy populated host arrays to corresponding device arrays
gpuErrchk( cudaMemcpy(d_inp, inp, i_size*sizeof(int), cudaMemcpyHostToDevice) );
gpuErrchk( cudaMemcpy(d_outp, outp, o_size*sizeof(int), cudaMemcpyHostToDevice) );
gpuErrchk( cudaMemcpy(d_kern, kern, k_size*sizeof(int), cudaMemcpyHostToDevice) );
// launch all threads on device
// # blocks = # input feature maps * # batches / input feature map
// # threads / block = # elements in each batch
matrix_vector_mult<<<ni*batch, nx*ny/batch>>>(d_inp, d_outp, d_kern);
// determine if run succeeded
gpuErrchk( cudaPeekAtLastError() );
gpuErrchk( cudaDeviceSynchronize() );
// copy output array back to host
gpuErrchk( cudaMemcpy(outp, d_outp, o_size, cudaMemcpyDeviceToHost) );
// free all memory
free(inp); free(outp); free(kern);
gpuErrchk( cudaFree(d_inp) ); gpuErrchk( cudaFree(d_outp) ); gpuErrchk( cudaFree(d_kern) );
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <math.h>
#define kx 3
#define ky 3
#define nx 224
#define ny 224
#define ni 64
#define nn 64
#define batch 64
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
void random_ints(int* a, int N)
{
int i;
for (i = 0; i < N; i++)
{
a[i] = rand();
}
}
void zeros(int* a, int N)
{
int i;
for (i = 0; i < N; i++)
{
a[i] = 0;
}
}
// CURRENT MEMORY PERFORMANCE = 5.77 GB/s
// perform a single application (matrix-vector multiply) of 1 weights matrix to a subset of a single input feature map
// the batch size (batch) determines the size of the subset
// the dimensions of the weights matrix are (kx, ky)
// the dimensions of all input and output feature maps are (nx, ny)
// the number of input feature maps is ni
// the number of output feature maps is nn
// the input and output feature maps are thus represented as 3D arrays (logically)
// the corresponding weights matrices are thus represented as a 4D array (logically)
// this is what is done in a 3D convolution layer
// this method utilizes a scratchpad memory for better thread block performance
__global__
void matrix_vector_mult(int *inp, int *outp, int *kern)
{
// scratchpad memory used for shared variables
// NOTE: must batch enough such that this data can fit in the shared memory
__shared__ int temp_kern[nn * kx * ky]; // all kernel matrices for given input feature map
__shared__ int temp_inp[nx * ny / batch]; // batched subset of given input feature map
// only 1 thread in block needs to populate all shared variables but temp_ind
if (threadIdx.x == 0) {
int hold = nn* kx * ky;
int k_start = (blockIdx.x/batch) * kx * ky; // every (batch) thread blocks use the same weights matrices
for (int j = 0; j < hold; j++) { // populate temp_kern
int t = k_start + j;
temp_kern[j] = kern[t];
}
}
int i_index = (blockIdx.x * (nx * ny / batch)) + threadIdx.x; // 1 thread block per subset of each feature map
temp_inp[threadIdx.x] = inp[i_index]; // piecemeal load in the input feature map
__syncthreads(); // sync all threads to this point - input feature map loaded
int l_start = threadIdx.x - ky/2 - (ny/(batch/2) * (kx/2));
for (int i=0; i<nn; i++) {
int out = 0;
for (int j=0; j<kx; j++) {
for (int k=0; k<ky; k++) {
int curr = l_start + (ny/(batch/2)*j) + k;
int k_index = (i*kx*ky) + (j*ky) + k;
if ((curr >= 0) && (curr <= (nx*ny/batch-1))) { // check against barriers of input feature map
out += temp_inp[curr] * temp_kern[k_index];
}
}
}
// store output
int n_index = (i * nx * ny) + threadIdx.x; // rotate through output feature maps constantly
outp[n_index] += out;
}
}
int main(void)
{
// declare host + device pointers
int *inp, *outp, *kern;
int *d_inp, *d_outp, *d_kern;
// compute array sizes
int i_size = ni*nx*ny;
int o_size = nn*nx*ny;
int k_size = nn*ni*kx*ky;
// allocate space for each array on the device
gpuErrchk( hipMalloc(&d_inp, i_size*sizeof(int)) );
gpuErrchk( hipMalloc(&d_outp, o_size*sizeof(int)) );
gpuErrchk( hipMalloc(&d_kern, k_size*sizeof(int)) );
// allocate space and populate each array on the host
inp = (int*)malloc(i_size*sizeof(int));
outp = (int*)malloc(o_size*sizeof(int));
kern = (int*)malloc(k_size*sizeof(int));
random_ints(inp, i_size);
zeros(outp, o_size);
random_ints(kern, k_size);
// copy populated host arrays to corresponding device arrays
gpuErrchk( hipMemcpy(d_inp, inp, i_size*sizeof(int), hipMemcpyHostToDevice) );
gpuErrchk( hipMemcpy(d_outp, outp, o_size*sizeof(int), hipMemcpyHostToDevice) );
gpuErrchk( hipMemcpy(d_kern, kern, k_size*sizeof(int), hipMemcpyHostToDevice) );
// launch all threads on device
// # blocks = # input feature maps * # batches / input feature map
// # threads / block = # elements in each batch
matrix_vector_mult<<<ni*batch, nx*ny/batch>>>(d_inp, d_outp, d_kern);
// determine if run succeeded
gpuErrchk( hipPeekAtLastError() );
gpuErrchk( hipDeviceSynchronize() );
// copy output array back to host
gpuErrchk( hipMemcpy(outp, d_outp, o_size, hipMemcpyDeviceToHost) );
// free all memory
free(inp); free(outp); free(kern);
gpuErrchk( hipFree(d_inp) ); gpuErrchk( hipFree(d_outp) ); gpuErrchk( hipFree(d_kern) );
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <math.h>
#define kx 3
#define ky 3
#define nx 224
#define ny 224
#define ni 64
#define nn 64
#define batch 64
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
void random_ints(int* a, int N)
{
int i;
for (i = 0; i < N; i++)
{
a[i] = rand();
}
}
void zeros(int* a, int N)
{
int i;
for (i = 0; i < N; i++)
{
a[i] = 0;
}
}
// CURRENT MEMORY PERFORMANCE = 5.77 GB/s
// perform a single application (matrix-vector multiply) of 1 weights matrix to a subset of a single input feature map
// the batch size (batch) determines the size of the subset
// the dimensions of the weights matrix are (kx, ky)
// the dimensions of all input and output feature maps are (nx, ny)
// the number of input feature maps is ni
// the number of output feature maps is nn
// the input and output feature maps are thus represented as 3D arrays (logically)
// the corresponding weights matrices are thus represented as a 4D array (logically)
// this is what is done in a 3D convolution layer
// this method utilizes a scratchpad memory for better thread block performance
__global__
void matrix_vector_mult(int *inp, int *outp, int *kern)
{
// scratchpad memory used for shared variables
// NOTE: must batch enough such that this data can fit in the shared memory
__shared__ int temp_kern[nn * kx * ky]; // all kernel matrices for given input feature map
__shared__ int temp_inp[nx * ny / batch]; // batched subset of given input feature map
// only 1 thread in block needs to populate all shared variables but temp_ind
if (threadIdx.x == 0) {
int hold = nn* kx * ky;
int k_start = (blockIdx.x/batch) * kx * ky; // every (batch) thread blocks use the same weights matrices
for (int j = 0; j < hold; j++) { // populate temp_kern
int t = k_start + j;
temp_kern[j] = kern[t];
}
}
int i_index = (blockIdx.x * (nx * ny / batch)) + threadIdx.x; // 1 thread block per subset of each feature map
temp_inp[threadIdx.x] = inp[i_index]; // piecemeal load in the input feature map
__syncthreads(); // sync all threads to this point - input feature map loaded
int l_start = threadIdx.x - ky/2 - (ny/(batch/2) * (kx/2));
for (int i=0; i<nn; i++) {
int out = 0;
for (int j=0; j<kx; j++) {
for (int k=0; k<ky; k++) {
int curr = l_start + (ny/(batch/2)*j) + k;
int k_index = (i*kx*ky) + (j*ky) + k;
if ((curr >= 0) && (curr <= (nx*ny/batch-1))) { // check against barriers of input feature map
out += temp_inp[curr] * temp_kern[k_index];
}
}
}
// store output
int n_index = (i * nx * ny) + threadIdx.x; // rotate through output feature maps constantly
outp[n_index] += out;
}
}
int main(void)
{
// declare host + device pointers
int *inp, *outp, *kern;
int *d_inp, *d_outp, *d_kern;
// compute array sizes
int i_size = ni*nx*ny;
int o_size = nn*nx*ny;
int k_size = nn*ni*kx*ky;
// allocate space for each array on the device
gpuErrchk( hipMalloc(&d_inp, i_size*sizeof(int)) );
gpuErrchk( hipMalloc(&d_outp, o_size*sizeof(int)) );
gpuErrchk( hipMalloc(&d_kern, k_size*sizeof(int)) );
// allocate space and populate each array on the host
inp = (int*)malloc(i_size*sizeof(int));
outp = (int*)malloc(o_size*sizeof(int));
kern = (int*)malloc(k_size*sizeof(int));
random_ints(inp, i_size);
zeros(outp, o_size);
random_ints(kern, k_size);
// copy populated host arrays to corresponding device arrays
gpuErrchk( hipMemcpy(d_inp, inp, i_size*sizeof(int), hipMemcpyHostToDevice) );
gpuErrchk( hipMemcpy(d_outp, outp, o_size*sizeof(int), hipMemcpyHostToDevice) );
gpuErrchk( hipMemcpy(d_kern, kern, k_size*sizeof(int), hipMemcpyHostToDevice) );
// launch all threads on device
// # blocks = # input feature maps * # batches / input feature map
// # threads / block = # elements in each batch
matrix_vector_mult<<<ni*batch, nx*ny/batch>>>(d_inp, d_outp, d_kern);
// determine if run succeeded
gpuErrchk( hipPeekAtLastError() );
gpuErrchk( hipDeviceSynchronize() );
// copy output array back to host
gpuErrchk( hipMemcpy(outp, d_outp, o_size, hipMemcpyDeviceToHost) );
// free all memory
free(inp); free(outp); free(kern);
gpuErrchk( hipFree(d_inp) ); gpuErrchk( hipFree(d_outp) ); gpuErrchk( hipFree(d_kern) );
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18matrix_vector_multPiS_S_
.globl _Z18matrix_vector_multPiS_S_
.p2align 8
.type _Z18matrix_vector_multPiS_S_,@function
_Z18matrix_vector_multPiS_S_:
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_3
s_load_b64 s[2:3], s[0:1], 0x10
s_lshr_b32 s5, s15, 6
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s5, s5, 36
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s5
s_addc_u32 s3, s3, 0
s_movk_i32 s5, 0xf700
.LBB0_2:
s_load_b32 s6, s[2:3], 0x0
v_mov_b32_e32 v1, s5
s_add_i32 s5, s5, 4
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmp_lg_u32 s5, 0
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v2, s6
ds_store_b32 v1, v2 offset:5440
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s4
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, s15, 0x310, v[0:1]
v_lshlrev_b32_e32 v3, 2, v0
v_add_nc_u32_e32 v4, -8, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_mov_b32 s0, 0
s_movk_i32 s1, 0xc40
global_load_b32 v1, v[1:2], off
v_mov_b32_e32 v2, 0
v_subrev_nc_u32_e32 v5, 32, v3
s_waitcnt vmcnt(0)
ds_store_b32 v3, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_branch .LBB0_5
.LBB0_4:
s_set_inst_prefetch_distance 0x2
s_mul_i32 s4, s0, 0xc400
s_add_i32 s0, s0, 1
v_or_b32_e32 v1, s4, v0
s_add_i32 s1, s1, 36
s_cmp_eq_u32 s0, 64
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[1:2]
v_add_co_u32 v6, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
global_load_b32 v1, v[6:7], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v1, v3
global_store_b32 v[6:7], v1, off
s_cbranch_scc1 .LBB0_11
.LBB0_5:
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v6, v5
v_mov_b32_e32 v1, v4
s_mov_b32 s4, s1
s_mov_b32 s5, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_7
.p2align 6
.LBB0_6:
v_add_nc_u32_e32 v6, 28, v6
v_add_nc_u32_e32 v1, 7, v1
s_add_i32 s5, s5, 1
s_add_i32 s4, s4, 12
s_cmp_eq_u32 s5, 3
s_cbranch_scc1 .LBB0_4
.LBB0_7:
v_mov_b32_e32 v7, v1
s_mov_b32 s6, 0
s_branch .LBB0_9
.p2align 6
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s7
v_add_nc_u32_e32 v7, 1, v7
s_add_i32 s6, s6, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s6, 12
s_cbranch_scc1 .LBB0_6
.LBB0_9:
s_mov_b32 s7, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e32 0x310, v7
s_cbranch_execz .LBB0_8
s_add_i32 s8, s4, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_dual_mov_b32 v9, s8 :: v_dual_add_nc_u32 v8, s6, v6
ds_load_b32 v10, v8
ds_load_b32 v11, v9
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[8:9], null, v11, v10, v[3:4]
v_mov_b32_e32 v3, v8
s_branch .LBB0_8
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18matrix_vector_multPiS_S_
.amdhsa_group_segment_fixed_size 5440
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18matrix_vector_multPiS_S_, .Lfunc_end0-_Z18matrix_vector_multPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 5440
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18matrix_vector_multPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18matrix_vector_multPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <math.h>
#define kx 3
#define ky 3
#define nx 224
#define ny 224
#define ni 64
#define nn 64
#define batch 64
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
void random_ints(int* a, int N)
{
int i;
for (i = 0; i < N; i++)
{
a[i] = rand();
}
}
void zeros(int* a, int N)
{
int i;
for (i = 0; i < N; i++)
{
a[i] = 0;
}
}
// CURRENT MEMORY PERFORMANCE = 5.77 GB/s
// perform a single application (matrix-vector multiply) of 1 weights matrix to a subset of a single input feature map
// the batch size (batch) determines the size of the subset
// the dimensions of the weights matrix are (kx, ky)
// the dimensions of all input and output feature maps are (nx, ny)
// the number of input feature maps is ni
// the number of output feature maps is nn
// the input and output feature maps are thus represented as 3D arrays (logically)
// the corresponding weights matrices are thus represented as a 4D array (logically)
// this is what is done in a 3D convolution layer
// this method utilizes a scratchpad memory for better thread block performance
__global__
void matrix_vector_mult(int *inp, int *outp, int *kern)
{
// scratchpad memory used for shared variables
// NOTE: must batch enough such that this data can fit in the shared memory
__shared__ int temp_kern[nn * kx * ky]; // all kernel matrices for given input feature map
__shared__ int temp_inp[nx * ny / batch]; // batched subset of given input feature map
// only 1 thread in block needs to populate all shared variables but temp_ind
if (threadIdx.x == 0) {
int hold = nn* kx * ky;
int k_start = (blockIdx.x/batch) * kx * ky; // every (batch) thread blocks use the same weights matrices
for (int j = 0; j < hold; j++) { // populate temp_kern
int t = k_start + j;
temp_kern[j] = kern[t];
}
}
int i_index = (blockIdx.x * (nx * ny / batch)) + threadIdx.x; // 1 thread block per subset of each feature map
temp_inp[threadIdx.x] = inp[i_index]; // piecemeal load in the input feature map
__syncthreads(); // sync all threads to this point - input feature map loaded
int l_start = threadIdx.x - ky/2 - (ny/(batch/2) * (kx/2));
for (int i=0; i<nn; i++) {
int out = 0;
for (int j=0; j<kx; j++) {
for (int k=0; k<ky; k++) {
int curr = l_start + (ny/(batch/2)*j) + k;
int k_index = (i*kx*ky) + (j*ky) + k;
if ((curr >= 0) && (curr <= (nx*ny/batch-1))) { // check against barriers of input feature map
out += temp_inp[curr] * temp_kern[k_index];
}
}
}
// store output
int n_index = (i * nx * ny) + threadIdx.x; // rotate through output feature maps constantly
outp[n_index] += out;
}
}
int main(void)
{
// declare host + device pointers
int *inp, *outp, *kern;
int *d_inp, *d_outp, *d_kern;
// compute array sizes
int i_size = ni*nx*ny;
int o_size = nn*nx*ny;
int k_size = nn*ni*kx*ky;
// allocate space for each array on the device
gpuErrchk( hipMalloc(&d_inp, i_size*sizeof(int)) );
gpuErrchk( hipMalloc(&d_outp, o_size*sizeof(int)) );
gpuErrchk( hipMalloc(&d_kern, k_size*sizeof(int)) );
// allocate space and populate each array on the host
inp = (int*)malloc(i_size*sizeof(int));
outp = (int*)malloc(o_size*sizeof(int));
kern = (int*)malloc(k_size*sizeof(int));
random_ints(inp, i_size);
zeros(outp, o_size);
random_ints(kern, k_size);
// copy populated host arrays to corresponding device arrays
gpuErrchk( hipMemcpy(d_inp, inp, i_size*sizeof(int), hipMemcpyHostToDevice) );
gpuErrchk( hipMemcpy(d_outp, outp, o_size*sizeof(int), hipMemcpyHostToDevice) );
gpuErrchk( hipMemcpy(d_kern, kern, k_size*sizeof(int), hipMemcpyHostToDevice) );
// launch all threads on device
// # blocks = # input feature maps * # batches / input feature map
// # threads / block = # elements in each batch
matrix_vector_mult<<<ni*batch, nx*ny/batch>>>(d_inp, d_outp, d_kern);
// determine if run succeeded
gpuErrchk( hipPeekAtLastError() );
gpuErrchk( hipDeviceSynchronize() );
// copy output array back to host
gpuErrchk( hipMemcpy(outp, d_outp, o_size, hipMemcpyDeviceToHost) );
// free all memory
free(inp); free(outp); free(kern);
gpuErrchk( hipFree(d_inp) ); gpuErrchk( hipFree(d_outp) ); gpuErrchk( hipFree(d_kern) );
return 0;
} | .text
.file "conv1.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z11random_intsPii # -- Begin function _Z11random_intsPii
.p2align 4, 0x90
.type _Z11random_intsPii,@function
_Z11random_intsPii: # @_Z11random_intsPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB0_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB0_4: # %._crit_edge
retq
.Lfunc_end0:
.size _Z11random_intsPii, .Lfunc_end0-_Z11random_intsPii
.cfi_endproc
# -- End function
.globl _Z5zerosPii # -- Begin function _Z5zerosPii
.p2align 4, 0x90
.type _Z5zerosPii,@function
_Z5zerosPii: # @_Z5zerosPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_1
# %bb.2: # %.lr.ph.preheader
movl %esi, %edx
shlq $2, %rdx
xorl %esi, %esi
jmp memset@PLT # TAILCALL
.LBB1_1: # %._crit_edge
retq
.Lfunc_end1:
.size _Z5zerosPii, .Lfunc_end1-_Z5zerosPii
.cfi_endproc
# -- End function
.globl _Z33__device_stub__matrix_vector_multPiS_S_ # -- Begin function _Z33__device_stub__matrix_vector_multPiS_S_
.p2align 4, 0x90
.type _Z33__device_stub__matrix_vector_multPiS_S_,@function
_Z33__device_stub__matrix_vector_multPiS_S_: # @_Z33__device_stub__matrix_vector_multPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18matrix_vector_multPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z33__device_stub__matrix_vector_multPiS_S_, .Lfunc_end2-_Z33__device_stub__matrix_vector_multPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 16(%rsp), %rdi
movl $12845056, %esi # imm = 0xC40000
callq hipMalloc
testl %eax, %eax
jne .LBB3_1
# %bb.3: # %_Z9gpuAssert10hipError_tPKcib.exit
movq %rsp, %rdi
movl $12845056, %esi # imm = 0xC40000
callq hipMalloc
testl %eax, %eax
jne .LBB3_4
# %bb.5: # %_Z9gpuAssert10hipError_tPKcib.exit25
leaq 8(%rsp), %rdi
movl $147456, %esi # imm = 0x24000
callq hipMalloc
testl %eax, %eax
jne .LBB3_6
# %bb.7: # %_Z9gpuAssert10hipError_tPKcib.exit27
movl $12845056, %edi # imm = 0xC40000
callq malloc
movq %rax, %rbx
movl $12845056, %edi # imm = 0xC40000
callq malloc
movq %rax, %r14
movl $147456, %edi # imm = 0x24000
callq malloc
movq %rax, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_8: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
movl %eax, (%rbx,%r12,4)
incq %r12
cmpq $3211264, %r12 # imm = 0x310000
jne .LBB3_8
# %bb.9: # %_Z11random_intsPii.exit
xorl %r12d, %r12d
movl $12845056, %edx # imm = 0xC40000
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB3_10: # %.lr.ph.i28
# =>This Inner Loop Header: Depth=1
callq rand
movl %eax, (%r15,%r12,4)
incq %r12
cmpq $36864, %r12 # imm = 0x9000
jne .LBB3_10
# %bb.11: # %_Z11random_intsPii.exit32
movq 16(%rsp), %rdi
movl $12845056, %edx # imm = 0xC40000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_12
# %bb.13: # %_Z9gpuAssert10hipError_tPKcib.exit34
movq (%rsp), %rdi
movl $12845056, %edx # imm = 0xC40000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_14
# %bb.15: # %_Z9gpuAssert10hipError_tPKcib.exit36
movq 8(%rsp), %rdi
movl $147456, %edx # imm = 0x24000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_16
# %bb.17: # %_Z9gpuAssert10hipError_tPKcib.exit38
movabsq $4294968080, %rdx # imm = 0x100000310
leaq 3312(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_19
# %bb.18:
movq 16(%rsp), %rax
movq (%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18matrix_vector_multPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_19:
callq hipPeekAtLastError
testl %eax, %eax
jne .LBB3_20
# %bb.21: # %_Z9gpuAssert10hipError_tPKcib.exit40
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB3_22
# %bb.23: # %_Z9gpuAssert10hipError_tPKcib.exit42
movq (%rsp), %rsi
movl $3211264, %edx # imm = 0x310000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_24
# %bb.25: # %_Z9gpuAssert10hipError_tPKcib.exit44
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB3_26
# %bb.27: # %_Z9gpuAssert10hipError_tPKcib.exit46
movq (%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB3_26
# %bb.28: # %_Z9gpuAssert10hipError_tPKcib.exit48
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB3_26
# %bb.29: # %_Z9gpuAssert10hipError_tPKcib.exit50
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_26:
.cfi_def_cfa_offset 176
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $140, %r8d
jmp .LBB3_2
.LBB3_1:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $109, %r8d
jmp .LBB3_2
.LBB3_4:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $110, %r8d
jmp .LBB3_2
.LBB3_6:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $111, %r8d
jmp .LBB3_2
.LBB3_12:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $122, %r8d
jmp .LBB3_2
.LBB3_14:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $123, %r8d
jmp .LBB3_2
.LBB3_16:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $124, %r8d
jmp .LBB3_2
.LBB3_20:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $132, %r8d
jmp .LBB3_2
.LBB3_22:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $133, %r8d
jmp .LBB3_2
.LBB3_24:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $136, %r8d
.LBB3_2:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18matrix_vector_multPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18matrix_vector_multPiS_S_,@object # @_Z18matrix_vector_multPiS_S_
.section .rodata,"a",@progbits
.globl _Z18matrix_vector_multPiS_S_
.p2align 3, 0x0
_Z18matrix_vector_multPiS_S_:
.quad _Z33__device_stub__matrix_vector_multPiS_S_
.size _Z18matrix_vector_multPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/joshkimmel16/cuda-kernels/master/conv1.hip"
.size .L.str, 100
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.1, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z18matrix_vector_multPiS_S_"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__matrix_vector_multPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18matrix_vector_multPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00135310_00000000-6_conv1.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3675:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
.string "GPUassert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB3669:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L10
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.text
.globl _Z11random_intsPii
.type _Z11random_intsPii, @function
_Z11random_intsPii:
.LFB3670:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L16
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L13:
call rand@PLT
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L13
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE3670:
.size _Z11random_intsPii, .-_Z11random_intsPii
.globl _Z5zerosPii
.type _Z5zerosPii, @function
_Z5zerosPii:
.LFB3671:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L19
movq %rdi, %rax
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rdx
.L21:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L21
.L19:
ret
.cfi_endproc
.LFE3671:
.size _Z5zerosPii, .-_Z5zerosPii
.globl _Z42__device_stub__Z18matrix_vector_multPiS_S_PiS_S_
.type _Z42__device_stub__Z18matrix_vector_multPiS_S_PiS_S_, @function
_Z42__device_stub__Z18matrix_vector_multPiS_S_PiS_S_:
.LFB3697:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18matrix_vector_multPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z42__device_stub__Z18matrix_vector_multPiS_S_PiS_S_, .-_Z42__device_stub__Z18matrix_vector_multPiS_S_PiS_S_
.globl _Z18matrix_vector_multPiS_S_
.type _Z18matrix_vector_multPiS_S_, @function
_Z18matrix_vector_multPiS_S_:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z18matrix_vector_multPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z18matrix_vector_multPiS_S_, .-_Z18matrix_vector_multPiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/joshkimmel16/cuda-kernels/master/conv1.cu"
.text
.globl main
.type main, @function
main:
.LFB3672:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $12845056, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $107, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 16(%rsp), %rdi
movl $12845056, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $108, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 24(%rsp), %rdi
movl $147456, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $109, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $12845056, %edi
call malloc@PLT
movq %rax, %r13
movl $12845056, %edi
call malloc@PLT
movq %rax, %rbp
movl $147456, %edi
call malloc@PLT
movq %rax, %r12
movl $3211264, %esi
movq %r13, %rdi
call _Z11random_intsPii
movl $3211264, %esi
movq %rbp, %rdi
call _Z5zerosPii
movl $36864, %esi
movq %r12, %rdi
call _Z11random_intsPii
movl $1, %ecx
movl $12845056, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $120, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movl $12845056, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $121, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movl $147456, %edx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $122, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $784, 44(%rsp)
movl $1, 48(%rsp)
movl $4096, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L32:
call cudaPeekAtLastError@PLT
movl %eax, %edi
movl $1, %ecx
movl $130, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $1, %ecx
movl $131, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $2, %ecx
movl $3211264, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $134, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq %r13, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $138, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $138, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 24(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $138, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L36
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z42__device_stub__Z18matrix_vector_multPiS_S_PiS_S_
jmp .L32
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3672:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z18matrix_vector_multPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z18matrix_vector_multPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "conv1.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z11random_intsPii # -- Begin function _Z11random_intsPii
.p2align 4, 0x90
.type _Z11random_intsPii,@function
_Z11random_intsPii: # @_Z11random_intsPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB0_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB0_4: # %._crit_edge
retq
.Lfunc_end0:
.size _Z11random_intsPii, .Lfunc_end0-_Z11random_intsPii
.cfi_endproc
# -- End function
.globl _Z5zerosPii # -- Begin function _Z5zerosPii
.p2align 4, 0x90
.type _Z5zerosPii,@function
_Z5zerosPii: # @_Z5zerosPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_1
# %bb.2: # %.lr.ph.preheader
movl %esi, %edx
shlq $2, %rdx
xorl %esi, %esi
jmp memset@PLT # TAILCALL
.LBB1_1: # %._crit_edge
retq
.Lfunc_end1:
.size _Z5zerosPii, .Lfunc_end1-_Z5zerosPii
.cfi_endproc
# -- End function
.globl _Z33__device_stub__matrix_vector_multPiS_S_ # -- Begin function _Z33__device_stub__matrix_vector_multPiS_S_
.p2align 4, 0x90
.type _Z33__device_stub__matrix_vector_multPiS_S_,@function
_Z33__device_stub__matrix_vector_multPiS_S_: # @_Z33__device_stub__matrix_vector_multPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18matrix_vector_multPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z33__device_stub__matrix_vector_multPiS_S_, .Lfunc_end2-_Z33__device_stub__matrix_vector_multPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 16(%rsp), %rdi
movl $12845056, %esi # imm = 0xC40000
callq hipMalloc
testl %eax, %eax
jne .LBB3_1
# %bb.3: # %_Z9gpuAssert10hipError_tPKcib.exit
movq %rsp, %rdi
movl $12845056, %esi # imm = 0xC40000
callq hipMalloc
testl %eax, %eax
jne .LBB3_4
# %bb.5: # %_Z9gpuAssert10hipError_tPKcib.exit25
leaq 8(%rsp), %rdi
movl $147456, %esi # imm = 0x24000
callq hipMalloc
testl %eax, %eax
jne .LBB3_6
# %bb.7: # %_Z9gpuAssert10hipError_tPKcib.exit27
movl $12845056, %edi # imm = 0xC40000
callq malloc
movq %rax, %rbx
movl $12845056, %edi # imm = 0xC40000
callq malloc
movq %rax, %r14
movl $147456, %edi # imm = 0x24000
callq malloc
movq %rax, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_8: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
movl %eax, (%rbx,%r12,4)
incq %r12
cmpq $3211264, %r12 # imm = 0x310000
jne .LBB3_8
# %bb.9: # %_Z11random_intsPii.exit
xorl %r12d, %r12d
movl $12845056, %edx # imm = 0xC40000
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB3_10: # %.lr.ph.i28
# =>This Inner Loop Header: Depth=1
callq rand
movl %eax, (%r15,%r12,4)
incq %r12
cmpq $36864, %r12 # imm = 0x9000
jne .LBB3_10
# %bb.11: # %_Z11random_intsPii.exit32
movq 16(%rsp), %rdi
movl $12845056, %edx # imm = 0xC40000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_12
# %bb.13: # %_Z9gpuAssert10hipError_tPKcib.exit34
movq (%rsp), %rdi
movl $12845056, %edx # imm = 0xC40000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_14
# %bb.15: # %_Z9gpuAssert10hipError_tPKcib.exit36
movq 8(%rsp), %rdi
movl $147456, %edx # imm = 0x24000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_16
# %bb.17: # %_Z9gpuAssert10hipError_tPKcib.exit38
movabsq $4294968080, %rdx # imm = 0x100000310
leaq 3312(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_19
# %bb.18:
movq 16(%rsp), %rax
movq (%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18matrix_vector_multPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_19:
callq hipPeekAtLastError
testl %eax, %eax
jne .LBB3_20
# %bb.21: # %_Z9gpuAssert10hipError_tPKcib.exit40
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB3_22
# %bb.23: # %_Z9gpuAssert10hipError_tPKcib.exit42
movq (%rsp), %rsi
movl $3211264, %edx # imm = 0x310000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_24
# %bb.25: # %_Z9gpuAssert10hipError_tPKcib.exit44
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB3_26
# %bb.27: # %_Z9gpuAssert10hipError_tPKcib.exit46
movq (%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB3_26
# %bb.28: # %_Z9gpuAssert10hipError_tPKcib.exit48
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB3_26
# %bb.29: # %_Z9gpuAssert10hipError_tPKcib.exit50
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_26:
.cfi_def_cfa_offset 176
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $140, %r8d
jmp .LBB3_2
.LBB3_1:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $109, %r8d
jmp .LBB3_2
.LBB3_4:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $110, %r8d
jmp .LBB3_2
.LBB3_6:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $111, %r8d
jmp .LBB3_2
.LBB3_12:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $122, %r8d
jmp .LBB3_2
.LBB3_14:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $123, %r8d
jmp .LBB3_2
.LBB3_16:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $124, %r8d
jmp .LBB3_2
.LBB3_20:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $132, %r8d
jmp .LBB3_2
.LBB3_22:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $133, %r8d
jmp .LBB3_2
.LBB3_24:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $136, %r8d
.LBB3_2:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18matrix_vector_multPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18matrix_vector_multPiS_S_,@object # @_Z18matrix_vector_multPiS_S_
.section .rodata,"a",@progbits
.globl _Z18matrix_vector_multPiS_S_
.p2align 3, 0x0
_Z18matrix_vector_multPiS_S_:
.quad _Z33__device_stub__matrix_vector_multPiS_S_
.size _Z18matrix_vector_multPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/joshkimmel16/cuda-kernels/master/conv1.hip"
.size .L.str, 100
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.1, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z18matrix_vector_multPiS_S_"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__matrix_vector_multPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18matrix_vector_multPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void apply_weight_decay_util_kernel( const float4 * __restrict learning_rates, float4 * __restrict weights, float weight_decay, int elem_count)
{
int elem_id = blockDim.x * blockIdx.x + threadIdx.x;
if (elem_id < elem_count)
{
float4 val = learning_rates[elem_id];
float4 current_weight = weights[elem_id];
val.x = 1.0F - val.x * weight_decay;
val.y = 1.0F - val.y * weight_decay;
val.z = 1.0F - val.z * weight_decay;
val.w = 1.0F - val.w * weight_decay;
current_weight.x *= val.x;
current_weight.y *= val.y;
current_weight.z *= val.z;
current_weight.w *= val.w;
weights[elem_id] = current_weight;
}
} | code for sm_80
Function : _Z30apply_weight_decay_util_kernelPK6float4PS_fi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x174], PT ; /* 0x00005d0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R8, R2, R3, c[0x0][0x160] ; /* 0x0000580002087625 */
/* 0x000fc800078e0203 */
/*0090*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fe400078e0203 */
/*00a0*/ LDG.E.128.CONSTANT R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e9d00 */
/*00b0*/ LDG.E.128 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ee2000c1e1d00 */
/*00c0*/ MOV R14, c[0x0][0x170] ; /* 0x00005c00000e7a02 */
/* 0x000fca0000000f00 */
/*00d0*/ FFMA R12, -R11, R14.reuse, 1 ; /* 0x3f8000000b0c7423 */
/* 0x084fe4000000010e */
/*00e0*/ FFMA R13, -R10, R14.reuse, 1 ; /* 0x3f8000000a0d7423 */
/* 0x080fe4000000010e */
/*00f0*/ FFMA R0, -R9, R14.reuse, 1 ; /* 0x3f80000009007423 */
/* 0x080fe4000000010e */
/*0100*/ FFMA R11, -R8, R14, 1 ; /* 0x3f800000080b7423 */
/* 0x000fe4000000010e */
/*0110*/ FMUL R7, R7, R12 ; /* 0x0000000c07077220 */
/* 0x008fe40000400000 */
/*0120*/ FMUL R6, R6, R13 ; /* 0x0000000d06067220 */
/* 0x000fc40000400000 */
/*0130*/ FMUL R5, R5, R0 ; /* 0x0000000005057220 */
/* 0x000fe40000400000 */
/*0140*/ FMUL R4, R4, R11 ; /* 0x0000000b04047220 */
/* 0x000fca0000400000 */
/*0150*/ STG.E.128 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101d04 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void apply_weight_decay_util_kernel( const float4 * __restrict learning_rates, float4 * __restrict weights, float weight_decay, int elem_count)
{
int elem_id = blockDim.x * blockIdx.x + threadIdx.x;
if (elem_id < elem_count)
{
float4 val = learning_rates[elem_id];
float4 current_weight = weights[elem_id];
val.x = 1.0F - val.x * weight_decay;
val.y = 1.0F - val.y * weight_decay;
val.z = 1.0F - val.z * weight_decay;
val.w = 1.0F - val.w * weight_decay;
current_weight.x *= val.x;
current_weight.y *= val.y;
current_weight.z *= val.z;
current_weight.w *= val.w;
weights[elem_id] = current_weight;
}
} | .file "tmpxft_000bf78b_00000000-6_apply_weight_decay_util_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z62__device_stub__Z30apply_weight_decay_util_kernelPK6float4PS_fiPK6float4PS_fi
.type _Z62__device_stub__Z30apply_weight_decay_util_kernelPK6float4PS_fiPK6float4PS_fi, @function
_Z62__device_stub__Z30apply_weight_decay_util_kernelPK6float4PS_fiPK6float4PS_fi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movq %rdi, 16(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z30apply_weight_decay_util_kernelPK6float4PS_fi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z62__device_stub__Z30apply_weight_decay_util_kernelPK6float4PS_fiPK6float4PS_fi, .-_Z62__device_stub__Z30apply_weight_decay_util_kernelPK6float4PS_fiPK6float4PS_fi
.globl _Z30apply_weight_decay_util_kernelPK6float4PS_fi
.type _Z30apply_weight_decay_util_kernelPK6float4PS_fi, @function
_Z30apply_weight_decay_util_kernelPK6float4PS_fi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z62__device_stub__Z30apply_weight_decay_util_kernelPK6float4PS_fiPK6float4PS_fi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z30apply_weight_decay_util_kernelPK6float4PS_fi, .-_Z30apply_weight_decay_util_kernelPK6float4PS_fi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z30apply_weight_decay_util_kernelPK6float4PS_fi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z30apply_weight_decay_util_kernelPK6float4PS_fi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void apply_weight_decay_util_kernel( const float4 * __restrict learning_rates, float4 * __restrict weights, float weight_decay, int elem_count)
{
int elem_id = blockDim.x * blockIdx.x + threadIdx.x;
if (elem_id < elem_count)
{
float4 val = learning_rates[elem_id];
float4 current_weight = weights[elem_id];
val.x = 1.0F - val.x * weight_decay;
val.y = 1.0F - val.y * weight_decay;
val.z = 1.0F - val.z * weight_decay;
val.w = 1.0F - val.w * weight_decay;
current_weight.x *= val.x;
current_weight.y *= val.y;
current_weight.z *= val.z;
current_weight.w *= val.w;
weights[elem_id] = current_weight;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void apply_weight_decay_util_kernel( const float4 * __restrict learning_rates, float4 * __restrict weights, float weight_decay, int elem_count)
{
int elem_id = blockDim.x * blockIdx.x + threadIdx.x;
if (elem_id < elem_count)
{
float4 val = learning_rates[elem_id];
float4 current_weight = weights[elem_id];
val.x = 1.0F - val.x * weight_decay;
val.y = 1.0F - val.y * weight_decay;
val.z = 1.0F - val.z * weight_decay;
val.w = 1.0F - val.w * weight_decay;
current_weight.x *= val.x;
current_weight.y *= val.y;
current_weight.z *= val.z;
current_weight.w *= val.w;
weights[elem_id] = current_weight;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void apply_weight_decay_util_kernel( const float4 * __restrict learning_rates, float4 * __restrict weights, float weight_decay, int elem_count)
{
int elem_id = blockDim.x * blockIdx.x + threadIdx.x;
if (elem_id < elem_count)
{
float4 val = learning_rates[elem_id];
float4 current_weight = weights[elem_id];
val.x = 1.0F - val.x * weight_decay;
val.y = 1.0F - val.y * weight_decay;
val.z = 1.0F - val.z * weight_decay;
val.w = 1.0F - val.w * weight_decay;
current_weight.x *= val.x;
current_weight.y *= val.y;
current_weight.z *= val.z;
current_weight.w *= val.w;
weights[elem_id] = current_weight;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z30apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi
.globl _Z30apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi
.p2align 8
.type _Z30apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi,@function
_Z30apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 4, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v8, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v1, vcc_lo
global_load_b128 v[0:3], v[2:3], off
global_load_b128 v[4:7], v[8:9], off
s_waitcnt vmcnt(1)
v_fma_f32 v0, -v0, s0, 1.0
v_fma_f32 v1, -v1, s0, 1.0
v_fma_f32 v2, -v2, s0, 1.0
v_fma_f32 v3, -v3, s0, 1.0
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mul_f32 v0, v0, v4 :: v_dual_mul_f32 v1, v1, v5
v_dual_mul_f32 v2, v2, v6 :: v_dual_mul_f32 v3, v3, v7
global_store_b128 v[8:9], v[0:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z30apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z30apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi, .Lfunc_end0-_Z30apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .actual_access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z30apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z30apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void apply_weight_decay_util_kernel( const float4 * __restrict learning_rates, float4 * __restrict weights, float weight_decay, int elem_count)
{
int elem_id = blockDim.x * blockIdx.x + threadIdx.x;
if (elem_id < elem_count)
{
float4 val = learning_rates[elem_id];
float4 current_weight = weights[elem_id];
val.x = 1.0F - val.x * weight_decay;
val.y = 1.0F - val.y * weight_decay;
val.z = 1.0F - val.z * weight_decay;
val.w = 1.0F - val.w * weight_decay;
current_weight.x *= val.x;
current_weight.y *= val.y;
current_weight.z *= val.z;
current_weight.w *= val.w;
weights[elem_id] = current_weight;
}
} | .text
.file "apply_weight_decay_util_kernel.hip"
.globl _Z45__device_stub__apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi # -- Begin function _Z45__device_stub__apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi
.p2align 4, 0x90
.type _Z45__device_stub__apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi,@function
_Z45__device_stub__apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi: # @_Z45__device_stub__apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z30apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z45__device_stub__apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi, .Lfunc_end0-_Z45__device_stub__apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z30apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z30apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi,@object # @_Z30apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi
.section .rodata,"a",@progbits
.globl _Z30apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi
.p2align 3, 0x0
_Z30apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi:
.quad _Z45__device_stub__apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi
.size _Z30apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z30apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi"
.size .L__unnamed_1, 67
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z45__device_stub__apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z30apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z30apply_weight_decay_util_kernelPK6float4PS_fi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x174], PT ; /* 0x00005d0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R8, R2, R3, c[0x0][0x160] ; /* 0x0000580002087625 */
/* 0x000fc800078e0203 */
/*0090*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fe400078e0203 */
/*00a0*/ LDG.E.128.CONSTANT R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e9d00 */
/*00b0*/ LDG.E.128 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ee2000c1e1d00 */
/*00c0*/ MOV R14, c[0x0][0x170] ; /* 0x00005c00000e7a02 */
/* 0x000fca0000000f00 */
/*00d0*/ FFMA R12, -R11, R14.reuse, 1 ; /* 0x3f8000000b0c7423 */
/* 0x084fe4000000010e */
/*00e0*/ FFMA R13, -R10, R14.reuse, 1 ; /* 0x3f8000000a0d7423 */
/* 0x080fe4000000010e */
/*00f0*/ FFMA R0, -R9, R14.reuse, 1 ; /* 0x3f80000009007423 */
/* 0x080fe4000000010e */
/*0100*/ FFMA R11, -R8, R14, 1 ; /* 0x3f800000080b7423 */
/* 0x000fe4000000010e */
/*0110*/ FMUL R7, R7, R12 ; /* 0x0000000c07077220 */
/* 0x008fe40000400000 */
/*0120*/ FMUL R6, R6, R13 ; /* 0x0000000d06067220 */
/* 0x000fc40000400000 */
/*0130*/ FMUL R5, R5, R0 ; /* 0x0000000005057220 */
/* 0x000fe40000400000 */
/*0140*/ FMUL R4, R4, R11 ; /* 0x0000000b04047220 */
/* 0x000fca0000400000 */
/*0150*/ STG.E.128 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101d04 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z30apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi
.globl _Z30apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi
.p2align 8
.type _Z30apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi,@function
_Z30apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 4, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v8, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v1, vcc_lo
global_load_b128 v[0:3], v[2:3], off
global_load_b128 v[4:7], v[8:9], off
s_waitcnt vmcnt(1)
v_fma_f32 v0, -v0, s0, 1.0
v_fma_f32 v1, -v1, s0, 1.0
v_fma_f32 v2, -v2, s0, 1.0
v_fma_f32 v3, -v3, s0, 1.0
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mul_f32 v0, v0, v4 :: v_dual_mul_f32 v1, v1, v5
v_dual_mul_f32 v2, v2, v6 :: v_dual_mul_f32 v3, v3, v7
global_store_b128 v[8:9], v[0:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z30apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z30apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi, .Lfunc_end0-_Z30apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .actual_access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z30apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z30apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000bf78b_00000000-6_apply_weight_decay_util_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z62__device_stub__Z30apply_weight_decay_util_kernelPK6float4PS_fiPK6float4PS_fi
.type _Z62__device_stub__Z30apply_weight_decay_util_kernelPK6float4PS_fiPK6float4PS_fi, @function
_Z62__device_stub__Z30apply_weight_decay_util_kernelPK6float4PS_fiPK6float4PS_fi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movq %rdi, 16(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z30apply_weight_decay_util_kernelPK6float4PS_fi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z62__device_stub__Z30apply_weight_decay_util_kernelPK6float4PS_fiPK6float4PS_fi, .-_Z62__device_stub__Z30apply_weight_decay_util_kernelPK6float4PS_fiPK6float4PS_fi
.globl _Z30apply_weight_decay_util_kernelPK6float4PS_fi
.type _Z30apply_weight_decay_util_kernelPK6float4PS_fi, @function
_Z30apply_weight_decay_util_kernelPK6float4PS_fi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z62__device_stub__Z30apply_weight_decay_util_kernelPK6float4PS_fiPK6float4PS_fi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z30apply_weight_decay_util_kernelPK6float4PS_fi, .-_Z30apply_weight_decay_util_kernelPK6float4PS_fi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z30apply_weight_decay_util_kernelPK6float4PS_fi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z30apply_weight_decay_util_kernelPK6float4PS_fi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "apply_weight_decay_util_kernel.hip"
.globl _Z45__device_stub__apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi # -- Begin function _Z45__device_stub__apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi
.p2align 4, 0x90
.type _Z45__device_stub__apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi,@function
_Z45__device_stub__apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi: # @_Z45__device_stub__apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z30apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z45__device_stub__apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi, .Lfunc_end0-_Z45__device_stub__apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z30apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z30apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi,@object # @_Z30apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi
.section .rodata,"a",@progbits
.globl _Z30apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi
.p2align 3, 0x0
_Z30apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi:
.quad _Z45__device_stub__apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi
.size _Z30apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z30apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi"
.size .L__unnamed_1, 67
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z45__device_stub__apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z30apply_weight_decay_util_kernelPK15HIP_vector_typeIfLj4EEPS0_fi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* This is a automatically generated test. Do not modify */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,int var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20,float var_21,float var_22,float var_23,float var_24,float var_25,float var_26,float var_27,float var_28,float var_29,float var_30,float var_31,float var_32,float var_33) {
for (int i=0; i < var_1; ++i) {
for (int i=0; i < var_2; ++i) {
if (comp < +1.4268E-35f + var_3 - fmodf(var_4 + (-1.2361E-18f * (var_5 * var_6)), var_7 - var_8)) {
if (comp >= -1.7135E29f / var_9 - +1.1539E27f) {
float tmp_1 = -0.0f;
comp += tmp_1 - +1.2048E34f / +1.6050E21f;
if (comp == sqrtf(-1.1915E14f)) {
float tmp_2 = -1.5838E-22f;
comp += tmp_2 + log10f(var_10 + (var_11 - +1.1871E-43f - -1.0763E-37f * (+0.0f / var_12)));
}
if (comp > +1.2736E35f - (var_13 - (var_14 + (var_15 - (var_16 + var_17))))) {
comp = -1.3103E-36f - +1.1597E-36f * (var_18 / var_19 + var_20);
comp += (var_21 - +1.0217E-27f / var_22 / (var_23 * +1.8086E-41f));
comp += (var_24 / var_25);
}
if (comp < var_26 - fmodf((var_27 * cosf((var_28 + var_29 - var_30 + (var_31 / var_32 * var_33)))), -1.5462E-4f / fabsf(asinf(-1.8932E-36f)))) {
comp = (+1.7096E9f / -0.0f * +1.3261E11f);
}
}
}
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
int tmp_3 = atoi(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
float tmp_22 = atof(argv[22]);
float tmp_23 = atof(argv[23]);
float tmp_24 = atof(argv[24]);
float tmp_25 = atof(argv[25]);
float tmp_26 = atof(argv[26]);
float tmp_27 = atof(argv[27]);
float tmp_28 = atof(argv[28]);
float tmp_29 = atof(argv[29]);
float tmp_30 = atof(argv[30]);
float tmp_31 = atof(argv[31]);
float tmp_32 = atof(argv[32]);
float tmp_33 = atof(argv[33]);
float tmp_34 = atof(argv[34]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23,tmp_24,tmp_25,tmp_26,tmp_27,tmp_28,tmp_29,tmp_30,tmp_31,tmp_32,tmp_33,tmp_34);
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_00044559_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initPointerf
.type _Z11initPointerf, @function
_Z11initPointerf:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movd %xmm0, %ebx
movl $40, %edi
call malloc@PLT
movq %rax, %rdx
leaq 40(%rax), %rcx
.L4:
movl %ebx, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L4
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11initPointerf, .-_Z11initPointerf
.globl _Z58__device_stub__Z7computefiiffffffffffffffffffffffffffffffffiifffffffffffffffffffffffffffffff
.type _Z58__device_stub__Z7computefiiffffffffffffffffffffffffffffffffiifffffffffffffffffffffffffffffff, @function
_Z58__device_stub__Z7computefiiffffffffffffffffffffffffffffffffiifffffffffffffffffffffffffffffff:
.LFB2083:
.cfi_startproc
endbr64
subq $408, %rsp
.cfi_def_cfa_offset 416
movss %xmm0, 44(%rsp)
movl %edi, 40(%rsp)
movl %esi, 36(%rsp)
movss %xmm1, 32(%rsp)
movss %xmm2, 28(%rsp)
movss %xmm3, 24(%rsp)
movss %xmm4, 20(%rsp)
movss %xmm5, 16(%rsp)
movss %xmm6, 12(%rsp)
movss %xmm7, 8(%rsp)
movq %fs:40, %rax
movq %rax, 392(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
leaq 416(%rsp), %rax
movq %rax, 192(%rsp)
leaq 424(%rsp), %rax
movq %rax, 200(%rsp)
leaq 432(%rsp), %rax
movq %rax, 208(%rsp)
leaq 440(%rsp), %rax
movq %rax, 216(%rsp)
leaq 448(%rsp), %rax
movq %rax, 224(%rsp)
leaq 456(%rsp), %rax
movq %rax, 232(%rsp)
leaq 464(%rsp), %rax
movq %rax, 240(%rsp)
leaq 472(%rsp), %rax
movq %rax, 248(%rsp)
leaq 480(%rsp), %rax
movq %rax, 256(%rsp)
leaq 488(%rsp), %rax
movq %rax, 264(%rsp)
leaq 496(%rsp), %rax
movq %rax, 272(%rsp)
leaq 504(%rsp), %rax
movq %rax, 280(%rsp)
leaq 512(%rsp), %rax
movq %rax, 288(%rsp)
leaq 520(%rsp), %rax
movq %rax, 296(%rsp)
leaq 528(%rsp), %rax
movq %rax, 304(%rsp)
leaq 536(%rsp), %rax
movq %rax, 312(%rsp)
leaq 544(%rsp), %rax
movq %rax, 320(%rsp)
leaq 552(%rsp), %rax
movq %rax, 328(%rsp)
leaq 560(%rsp), %rax
movq %rax, 336(%rsp)
leaq 568(%rsp), %rax
movq %rax, 344(%rsp)
leaq 576(%rsp), %rax
movq %rax, 352(%rsp)
leaq 584(%rsp), %rax
movq %rax, 360(%rsp)
leaq 592(%rsp), %rax
movq %rax, 368(%rsp)
leaq 600(%rsp), %rax
movq %rax, 376(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 392(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $408, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 424
pushq 56(%rsp)
.cfi_def_cfa_offset 432
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7computefiifffffffffffffffffffffffffffffff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 416
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z58__device_stub__Z7computefiiffffffffffffffffffffffffffffffffiifffffffffffffffffffffffffffffff, .-_Z58__device_stub__Z7computefiiffffffffffffffffffffffffffffffffiifffffffffffffffffffffffffffffff
.globl _Z7computefiifffffffffffffffffffffffffffffff
.type _Z7computefiifffffffffffffffffffffffffffffff, @function
_Z7computefiifffffffffffffffffffffffffffffff:
.LFB2084:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movss 392(%rsp), %xmm8
movss %xmm8, 184(%rsp)
movss 384(%rsp), %xmm8
movss %xmm8, 176(%rsp)
movss 376(%rsp), %xmm8
movss %xmm8, 168(%rsp)
movss 368(%rsp), %xmm8
movss %xmm8, 160(%rsp)
movss 360(%rsp), %xmm8
movss %xmm8, 152(%rsp)
movss 352(%rsp), %xmm8
movss %xmm8, 144(%rsp)
movss 344(%rsp), %xmm8
movss %xmm8, 136(%rsp)
movss 336(%rsp), %xmm8
movss %xmm8, 128(%rsp)
movss 328(%rsp), %xmm8
movss %xmm8, 120(%rsp)
movss 320(%rsp), %xmm8
movss %xmm8, 112(%rsp)
movss 312(%rsp), %xmm8
movss %xmm8, 104(%rsp)
movss 304(%rsp), %xmm8
movss %xmm8, 96(%rsp)
movss 296(%rsp), %xmm8
movss %xmm8, 88(%rsp)
movss 288(%rsp), %xmm8
movss %xmm8, 80(%rsp)
movss 280(%rsp), %xmm8
movss %xmm8, 72(%rsp)
movss 272(%rsp), %xmm8
movss %xmm8, 64(%rsp)
movss 264(%rsp), %xmm8
movss %xmm8, 56(%rsp)
movss 256(%rsp), %xmm8
movss %xmm8, 48(%rsp)
movss 248(%rsp), %xmm8
movss %xmm8, 40(%rsp)
movss 240(%rsp), %xmm8
movss %xmm8, 32(%rsp)
movss 232(%rsp), %xmm8
movss %xmm8, 24(%rsp)
movss 224(%rsp), %xmm8
movss %xmm8, 16(%rsp)
movss 216(%rsp), %xmm8
movss %xmm8, 8(%rsp)
movss 208(%rsp), %xmm8
movss %xmm8, (%rsp)
call _Z58__device_stub__Z7computefiiffffffffffffffffffffffffffffffffiifffffffffffffffffffffffffffffff
addq $200, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7computefiifffffffffffffffffffffffffffffff, .-_Z7computefiifffffffffffffffffffffffffffffff
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $288, %rsp
.cfi_def_cfa_offset 320
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 248(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 32(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 240(%rsp)
movq 40(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 232(%rsp)
movq 48(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 224(%rsp)
movq 56(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 216(%rsp)
movq 64(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 208(%rsp)
movq 72(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 200(%rsp)
movq 80(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 192(%rsp)
movq 88(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 184(%rsp)
movq 96(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 176(%rsp)
movq 104(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 168(%rsp)
movq 112(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 160(%rsp)
movq 120(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 152(%rsp)
movq 128(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 144(%rsp)
movq 136(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 136(%rsp)
movq 144(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 128(%rsp)
movq 152(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 120(%rsp)
movq 160(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 112(%rsp)
movq 168(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 104(%rsp)
movq 176(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 96(%rsp)
movq 184(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 88(%rsp)
movq 192(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 80(%rsp)
movq 200(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 72(%rsp)
movq 208(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 64(%rsp)
movq 216(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 56(%rsp)
movq 224(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 48(%rsp)
movq 232(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 40(%rsp)
movq 240(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 32(%rsp)
movq 248(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 24(%rsp)
movq 256(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 16(%rsp)
movq 264(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 8(%rsp)
movq 272(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, (%rsp)
movl $1, 276(%rsp)
movl $1, 280(%rsp)
movl $1, 264(%rsp)
movl $1, 268(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 276(%rsp), %rdx
movl $1, %ecx
movq 264(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $288, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pxor %xmm0, %xmm0
cvtsd2ss 248(%rsp), %xmm0
pxor %xmm1, %xmm1
cvtsd2ss (%rsp), %xmm1
leaq -192(%rsp), %rsp
.cfi_def_cfa_offset 512
movss %xmm1, 184(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 200(%rsp), %xmm1
movss %xmm1, 176(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 208(%rsp), %xmm1
movss %xmm1, 168(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 216(%rsp), %xmm1
movss %xmm1, 160(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 224(%rsp), %xmm1
movss %xmm1, 152(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 232(%rsp), %xmm1
movss %xmm1, 144(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 240(%rsp), %xmm1
movss %xmm1, 136(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 248(%rsp), %xmm1
movss %xmm1, 128(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 256(%rsp), %xmm1
movss %xmm1, 120(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 264(%rsp), %xmm1
movss %xmm1, 112(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 272(%rsp), %xmm1
movss %xmm1, 104(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 280(%rsp), %xmm1
movss %xmm1, 96(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 288(%rsp), %xmm1
movss %xmm1, 88(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 296(%rsp), %xmm1
movss %xmm1, 80(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 304(%rsp), %xmm1
movss %xmm1, 72(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 312(%rsp), %xmm1
movss %xmm1, 64(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 320(%rsp), %xmm1
movss %xmm1, 56(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 328(%rsp), %xmm1
movss %xmm1, 48(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 336(%rsp), %xmm1
movss %xmm1, 40(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 344(%rsp), %xmm1
movss %xmm1, 32(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 352(%rsp), %xmm1
movss %xmm1, 24(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 360(%rsp), %xmm1
movss %xmm1, 16(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 368(%rsp), %xmm1
movss %xmm1, 8(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 376(%rsp), %xmm1
movss %xmm1, (%rsp)
pxor %xmm7, %xmm7
cvtsd2ss 384(%rsp), %xmm7
pxor %xmm6, %xmm6
cvtsd2ss 392(%rsp), %xmm6
pxor %xmm5, %xmm5
cvtsd2ss 400(%rsp), %xmm5
pxor %xmm4, %xmm4
cvtsd2ss 408(%rsp), %xmm4
pxor %xmm3, %xmm3
cvtsd2ss 416(%rsp), %xmm3
pxor %xmm2, %xmm2
cvtsd2ss 424(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtsd2ss 432(%rsp), %xmm1
movl %ebp, %esi
movl %r12d, %edi
call _Z58__device_stub__Z7computefiiffffffffffffffffffffffffffffffffiifffffffffffffffffffffffffffffff
addq $192, %rsp
.cfi_def_cfa_offset 320
jmp .L16
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z7computefiifffffffffffffffffffffffffffffff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computefiifffffffffffffffffffffffffffffff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* This is a automatically generated test. Do not modify */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,int var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20,float var_21,float var_22,float var_23,float var_24,float var_25,float var_26,float var_27,float var_28,float var_29,float var_30,float var_31,float var_32,float var_33) {
for (int i=0; i < var_1; ++i) {
for (int i=0; i < var_2; ++i) {
if (comp < +1.4268E-35f + var_3 - fmodf(var_4 + (-1.2361E-18f * (var_5 * var_6)), var_7 - var_8)) {
if (comp >= -1.7135E29f / var_9 - +1.1539E27f) {
float tmp_1 = -0.0f;
comp += tmp_1 - +1.2048E34f / +1.6050E21f;
if (comp == sqrtf(-1.1915E14f)) {
float tmp_2 = -1.5838E-22f;
comp += tmp_2 + log10f(var_10 + (var_11 - +1.1871E-43f - -1.0763E-37f * (+0.0f / var_12)));
}
if (comp > +1.2736E35f - (var_13 - (var_14 + (var_15 - (var_16 + var_17))))) {
comp = -1.3103E-36f - +1.1597E-36f * (var_18 / var_19 + var_20);
comp += (var_21 - +1.0217E-27f / var_22 / (var_23 * +1.8086E-41f));
comp += (var_24 / var_25);
}
if (comp < var_26 - fmodf((var_27 * cosf((var_28 + var_29 - var_30 + (var_31 / var_32 * var_33)))), -1.5462E-4f / fabsf(asinf(-1.8932E-36f)))) {
comp = (+1.7096E9f / -0.0f * +1.3261E11f);
}
}
}
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
int tmp_3 = atoi(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
float tmp_22 = atof(argv[22]);
float tmp_23 = atof(argv[23]);
float tmp_24 = atof(argv[24]);
float tmp_25 = atof(argv[25]);
float tmp_26 = atof(argv[26]);
float tmp_27 = atof(argv[27]);
float tmp_28 = atof(argv[28]);
float tmp_29 = atof(argv[29]);
float tmp_30 = atof(argv[30]);
float tmp_31 = atof(argv[31]);
float tmp_32 = atof(argv[32]);
float tmp_33 = atof(argv[33]);
float tmp_34 = atof(argv[34]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23,tmp_24,tmp_25,tmp_26,tmp_27,tmp_28,tmp_29,tmp_30,tmp_31,tmp_32,tmp_33,tmp_34);
cudaDeviceSynchronize();
return 0;
} | /* This is a automatically generated test. Do not modify */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,int var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20,float var_21,float var_22,float var_23,float var_24,float var_25,float var_26,float var_27,float var_28,float var_29,float var_30,float var_31,float var_32,float var_33) {
for (int i=0; i < var_1; ++i) {
for (int i=0; i < var_2; ++i) {
if (comp < +1.4268E-35f + var_3 - fmodf(var_4 + (-1.2361E-18f * (var_5 * var_6)), var_7 - var_8)) {
if (comp >= -1.7135E29f / var_9 - +1.1539E27f) {
float tmp_1 = -0.0f;
comp += tmp_1 - +1.2048E34f / +1.6050E21f;
if (comp == sqrtf(-1.1915E14f)) {
float tmp_2 = -1.5838E-22f;
comp += tmp_2 + log10f(var_10 + (var_11 - +1.1871E-43f - -1.0763E-37f * (+0.0f / var_12)));
}
if (comp > +1.2736E35f - (var_13 - (var_14 + (var_15 - (var_16 + var_17))))) {
comp = -1.3103E-36f - +1.1597E-36f * (var_18 / var_19 + var_20);
comp += (var_21 - +1.0217E-27f / var_22 / (var_23 * +1.8086E-41f));
comp += (var_24 / var_25);
}
if (comp < var_26 - fmodf((var_27 * cosf((var_28 + var_29 - var_30 + (var_31 / var_32 * var_33)))), -1.5462E-4f / fabsf(asinf(-1.8932E-36f)))) {
comp = (+1.7096E9f / -0.0f * +1.3261E11f);
}
}
}
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
int tmp_3 = atoi(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
float tmp_22 = atof(argv[22]);
float tmp_23 = atof(argv[23]);
float tmp_24 = atof(argv[24]);
float tmp_25 = atof(argv[25]);
float tmp_26 = atof(argv[26]);
float tmp_27 = atof(argv[27]);
float tmp_28 = atof(argv[28]);
float tmp_29 = atof(argv[29]);
float tmp_30 = atof(argv[30]);
float tmp_31 = atof(argv[31]);
float tmp_32 = atof(argv[32]);
float tmp_33 = atof(argv[33]);
float tmp_34 = atof(argv[34]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23,tmp_24,tmp_25,tmp_26,tmp_27,tmp_28,tmp_29,tmp_30,tmp_31,tmp_32,tmp_33,tmp_34);
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* This is a automatically generated test. Do not modify */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,int var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20,float var_21,float var_22,float var_23,float var_24,float var_25,float var_26,float var_27,float var_28,float var_29,float var_30,float var_31,float var_32,float var_33) {
for (int i=0; i < var_1; ++i) {
for (int i=0; i < var_2; ++i) {
if (comp < +1.4268E-35f + var_3 - fmodf(var_4 + (-1.2361E-18f * (var_5 * var_6)), var_7 - var_8)) {
if (comp >= -1.7135E29f / var_9 - +1.1539E27f) {
float tmp_1 = -0.0f;
comp += tmp_1 - +1.2048E34f / +1.6050E21f;
if (comp == sqrtf(-1.1915E14f)) {
float tmp_2 = -1.5838E-22f;
comp += tmp_2 + log10f(var_10 + (var_11 - +1.1871E-43f - -1.0763E-37f * (+0.0f / var_12)));
}
if (comp > +1.2736E35f - (var_13 - (var_14 + (var_15 - (var_16 + var_17))))) {
comp = -1.3103E-36f - +1.1597E-36f * (var_18 / var_19 + var_20);
comp += (var_21 - +1.0217E-27f / var_22 / (var_23 * +1.8086E-41f));
comp += (var_24 / var_25);
}
if (comp < var_26 - fmodf((var_27 * cosf((var_28 + var_29 - var_30 + (var_31 / var_32 * var_33)))), -1.5462E-4f / fabsf(asinf(-1.8932E-36f)))) {
comp = (+1.7096E9f / -0.0f * +1.3261E11f);
}
}
}
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
int tmp_3 = atoi(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
float tmp_22 = atof(argv[22]);
float tmp_23 = atof(argv[23]);
float tmp_24 = atof(argv[24]);
float tmp_25 = atof(argv[25]);
float tmp_26 = atof(argv[26]);
float tmp_27 = atof(argv[27]);
float tmp_28 = atof(argv[28]);
float tmp_29 = atof(argv[29]);
float tmp_30 = atof(argv[30]);
float tmp_31 = atof(argv[31]);
float tmp_32 = atof(argv[32]);
float tmp_33 = atof(argv[33]);
float tmp_34 = atof(argv[34]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23,tmp_24,tmp_25,tmp_26,tmp_27,tmp_28,tmp_29,tmp_30,tmp_31,tmp_32,tmp_33,tmp_34);
hipDeviceSynchronize();
return 0;
} | .text
.file "test.hip"
.globl _Z22__device_stub__computefiifffffffffffffffffffffffffffffff # -- Begin function _Z22__device_stub__computefiifffffffffffffffffffffffffffffff
.p2align 4, 0x90
.type _Z22__device_stub__computefiifffffffffffffffffffffffffffffff,@function
_Z22__device_stub__computefiifffffffffffffffffffffffffffffff: # @_Z22__device_stub__computefiifffffffffffffffffffffffffffffff
.cfi_startproc
# %bb.0:
subq $376, %rsp # imm = 0x178
.cfi_def_cfa_offset 384
movss %xmm0, 44(%rsp)
movl %edi, 40(%rsp)
movl %esi, 36(%rsp)
movss %xmm1, 32(%rsp)
movss %xmm2, 28(%rsp)
movss %xmm3, 24(%rsp)
movss %xmm4, 20(%rsp)
movss %xmm5, 16(%rsp)
movss %xmm6, 12(%rsp)
movss %xmm7, 8(%rsp)
leaq 44(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rax
movq %rax, 104(%rsp)
leaq 36(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
leaq 384(%rsp), %rax
movq %rax, 176(%rsp)
leaq 392(%rsp), %rax
movq %rax, 184(%rsp)
leaq 400(%rsp), %rax
movq %rax, 192(%rsp)
leaq 408(%rsp), %rax
movq %rax, 200(%rsp)
leaq 416(%rsp), %rax
movq %rax, 208(%rsp)
leaq 424(%rsp), %rax
movq %rax, 216(%rsp)
leaq 432(%rsp), %rax
movq %rax, 224(%rsp)
leaq 440(%rsp), %rax
movq %rax, 232(%rsp)
leaq 448(%rsp), %rax
movq %rax, 240(%rsp)
leaq 456(%rsp), %rax
movq %rax, 248(%rsp)
leaq 464(%rsp), %rax
movq %rax, 256(%rsp)
leaq 472(%rsp), %rax
movq %rax, 264(%rsp)
leaq 480(%rsp), %rax
movq %rax, 272(%rsp)
leaq 488(%rsp), %rax
movq %rax, 280(%rsp)
leaq 496(%rsp), %rax
movq %rax, 288(%rsp)
leaq 504(%rsp), %rax
movq %rax, 296(%rsp)
leaq 512(%rsp), %rax
movq %rax, 304(%rsp)
leaq 520(%rsp), %rax
movq %rax, 312(%rsp)
leaq 528(%rsp), %rax
movq %rax, 320(%rsp)
leaq 536(%rsp), %rax
movq %rax, 328(%rsp)
leaq 544(%rsp), %rax
movq %rax, 336(%rsp)
leaq 552(%rsp), %rax
movq %rax, 344(%rsp)
leaq 560(%rsp), %rax
movq %rax, 352(%rsp)
leaq 568(%rsp), %rax
movq %rax, 360(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7computefiifffffffffffffffffffffffffffffff, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $392, %rsp # imm = 0x188
.cfi_adjust_cfa_offset -392
retq
.Lfunc_end0:
.size _Z22__device_stub__computefiifffffffffffffffffffffffffffffff, .Lfunc_end0-_Z22__device_stub__computefiifffffffffffffffffffffffffffffff
.cfi_endproc
# -- End function
.globl _Z11initPointerf # -- Begin function _Z11initPointerf
.p2align 4, 0x90
.type _Z11initPointerf,@function
_Z11initPointerf: # @_Z11initPointerf
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm0, 4(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $448, %rsp # imm = 0x1C0
.cfi_def_cfa_offset 480
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %r15
movq 8(%rsi), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 440(%rsp) # 8-byte Spill
movq 16(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 24(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 32(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 432(%rsp) # 8-byte Spill
movq 40(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 424(%rsp) # 8-byte Spill
movq 48(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 312(%rsp) # 8-byte Spill
movq 56(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 304(%rsp) # 8-byte Spill
movq 64(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 296(%rsp) # 8-byte Spill
movq 72(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 288(%rsp) # 8-byte Spill
movq 80(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 280(%rsp) # 8-byte Spill
movq 88(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 272(%rsp) # 8-byte Spill
movq 96(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 264(%rsp) # 8-byte Spill
movq 104(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 256(%rsp) # 8-byte Spill
movq 112(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 248(%rsp) # 8-byte Spill
movq 120(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 240(%rsp) # 8-byte Spill
movq 128(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 232(%rsp) # 8-byte Spill
movq 136(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 224(%rsp) # 8-byte Spill
movq 144(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 216(%rsp) # 8-byte Spill
movq 152(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 208(%rsp) # 8-byte Spill
movq 160(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 200(%rsp) # 8-byte Spill
movq 168(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 192(%rsp) # 8-byte Spill
movq 176(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 416(%rsp) # 8-byte Spill
movq 184(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 408(%rsp) # 8-byte Spill
movq 192(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 400(%rsp) # 8-byte Spill
movq 200(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 392(%rsp) # 8-byte Spill
movq 208(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 384(%rsp) # 8-byte Spill
movq 216(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 376(%rsp) # 8-byte Spill
movq 224(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 368(%rsp) # 8-byte Spill
movq 232(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 360(%rsp) # 8-byte Spill
movq 240(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 352(%rsp) # 8-byte Spill
movq 248(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 344(%rsp) # 8-byte Spill
movq 256(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 336(%rsp) # 8-byte Spill
movq 264(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 328(%rsp) # 8-byte Spill
movq 272(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 320(%rsp) # 8-byte Spill
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movsd 320(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm8
movsd 328(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm9
movsd 336(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm10
movsd 344(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm11
movsd 352(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm12
movsd 360(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm13
movsd 368(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm14
movsd 376(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm15
movsd 384(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm3
movsd 392(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm4
movsd 400(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm5
movsd 408(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm6
movsd 416(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm7
movsd 192(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 192(%rsp) # 4-byte Spill
movsd 200(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 200(%rsp) # 4-byte Spill
movsd 208(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 208(%rsp) # 4-byte Spill
movsd 216(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 216(%rsp) # 4-byte Spill
movsd 224(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 224(%rsp) # 4-byte Spill
movsd 232(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 232(%rsp) # 4-byte Spill
movsd 240(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 240(%rsp) # 4-byte Spill
movsd 248(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 248(%rsp) # 4-byte Spill
movsd 256(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 256(%rsp) # 4-byte Spill
movsd 264(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 264(%rsp) # 4-byte Spill
movsd 272(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 272(%rsp) # 4-byte Spill
movsd 280(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 280(%rsp) # 4-byte Spill
movsd 288(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 288(%rsp) # 4-byte Spill
movsd 296(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 296(%rsp) # 4-byte Spill
movsd 304(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 304(%rsp) # 4-byte Spill
movsd 312(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 312(%rsp) # 4-byte Spill
movsd 424(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm2
movsd 432(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm1
movsd 440(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm8, 184(%rsp)
movss %xmm9, 176(%rsp)
movss %xmm10, 168(%rsp)
movss %xmm11, 160(%rsp)
movss %xmm12, 152(%rsp)
movss %xmm13, 144(%rsp)
movss %xmm14, 136(%rsp)
movss %xmm15, 128(%rsp)
movss %xmm3, 120(%rsp)
movss %xmm4, 112(%rsp)
movss %xmm5, 104(%rsp)
movss %xmm6, 96(%rsp)
movss %xmm7, 88(%rsp)
movss 192(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 80(%rsp)
movss 200(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 72(%rsp)
movss 208(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 64(%rsp)
movss 216(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 56(%rsp)
movss 224(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 48(%rsp)
movss 232(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 40(%rsp)
movss 240(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 32(%rsp)
movss 248(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 24(%rsp)
movss 256(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 16(%rsp)
movss 264(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 8(%rsp)
movss 272(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, (%rsp)
movl %ebx, %edi
movl %r14d, %esi
movss 312(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss 304(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss 296(%rsp), %xmm5 # 4-byte Reload
# xmm5 = mem[0],zero,zero,zero
movss 288(%rsp), %xmm6 # 4-byte Reload
# xmm6 = mem[0],zero,zero,zero
movss 280(%rsp), %xmm7 # 4-byte Reload
# xmm7 = mem[0],zero,zero,zero
callq _Z22__device_stub__computefiifffffffffffffffffffffffffffffff
.LBB2_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $448, %rsp # imm = 0x1C0
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computefiifffffffffffffffffffffffffffffff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computefiifffffffffffffffffffffffffffffff,@object # @_Z7computefiifffffffffffffffffffffffffffffff
.section .rodata,"a",@progbits
.globl _Z7computefiifffffffffffffffffffffffffffffff
.p2align 3, 0x0
_Z7computefiifffffffffffffffffffffffffffffff:
.quad _Z22__device_stub__computefiifffffffffffffffffffffffffffffff
.size _Z7computefiifffffffffffffffffffffffffffffff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7computefiifffffffffffffffffffffffffffffff"
.size .L__unnamed_1, 45
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computefiifffffffffffffffffffffffffffffff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computefiifffffffffffffffffffffffffffffff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00044559_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initPointerf
.type _Z11initPointerf, @function
_Z11initPointerf:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movd %xmm0, %ebx
movl $40, %edi
call malloc@PLT
movq %rax, %rdx
leaq 40(%rax), %rcx
.L4:
movl %ebx, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L4
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11initPointerf, .-_Z11initPointerf
.globl _Z58__device_stub__Z7computefiiffffffffffffffffffffffffffffffffiifffffffffffffffffffffffffffffff
.type _Z58__device_stub__Z7computefiiffffffffffffffffffffffffffffffffiifffffffffffffffffffffffffffffff, @function
_Z58__device_stub__Z7computefiiffffffffffffffffffffffffffffffffiifffffffffffffffffffffffffffffff:
.LFB2083:
.cfi_startproc
endbr64
subq $408, %rsp
.cfi_def_cfa_offset 416
movss %xmm0, 44(%rsp)
movl %edi, 40(%rsp)
movl %esi, 36(%rsp)
movss %xmm1, 32(%rsp)
movss %xmm2, 28(%rsp)
movss %xmm3, 24(%rsp)
movss %xmm4, 20(%rsp)
movss %xmm5, 16(%rsp)
movss %xmm6, 12(%rsp)
movss %xmm7, 8(%rsp)
movq %fs:40, %rax
movq %rax, 392(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
leaq 416(%rsp), %rax
movq %rax, 192(%rsp)
leaq 424(%rsp), %rax
movq %rax, 200(%rsp)
leaq 432(%rsp), %rax
movq %rax, 208(%rsp)
leaq 440(%rsp), %rax
movq %rax, 216(%rsp)
leaq 448(%rsp), %rax
movq %rax, 224(%rsp)
leaq 456(%rsp), %rax
movq %rax, 232(%rsp)
leaq 464(%rsp), %rax
movq %rax, 240(%rsp)
leaq 472(%rsp), %rax
movq %rax, 248(%rsp)
leaq 480(%rsp), %rax
movq %rax, 256(%rsp)
leaq 488(%rsp), %rax
movq %rax, 264(%rsp)
leaq 496(%rsp), %rax
movq %rax, 272(%rsp)
leaq 504(%rsp), %rax
movq %rax, 280(%rsp)
leaq 512(%rsp), %rax
movq %rax, 288(%rsp)
leaq 520(%rsp), %rax
movq %rax, 296(%rsp)
leaq 528(%rsp), %rax
movq %rax, 304(%rsp)
leaq 536(%rsp), %rax
movq %rax, 312(%rsp)
leaq 544(%rsp), %rax
movq %rax, 320(%rsp)
leaq 552(%rsp), %rax
movq %rax, 328(%rsp)
leaq 560(%rsp), %rax
movq %rax, 336(%rsp)
leaq 568(%rsp), %rax
movq %rax, 344(%rsp)
leaq 576(%rsp), %rax
movq %rax, 352(%rsp)
leaq 584(%rsp), %rax
movq %rax, 360(%rsp)
leaq 592(%rsp), %rax
movq %rax, 368(%rsp)
leaq 600(%rsp), %rax
movq %rax, 376(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 392(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $408, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 424
pushq 56(%rsp)
.cfi_def_cfa_offset 432
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7computefiifffffffffffffffffffffffffffffff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 416
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z58__device_stub__Z7computefiiffffffffffffffffffffffffffffffffiifffffffffffffffffffffffffffffff, .-_Z58__device_stub__Z7computefiiffffffffffffffffffffffffffffffffiifffffffffffffffffffffffffffffff
.globl _Z7computefiifffffffffffffffffffffffffffffff
.type _Z7computefiifffffffffffffffffffffffffffffff, @function
_Z7computefiifffffffffffffffffffffffffffffff:
.LFB2084:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movss 392(%rsp), %xmm8
movss %xmm8, 184(%rsp)
movss 384(%rsp), %xmm8
movss %xmm8, 176(%rsp)
movss 376(%rsp), %xmm8
movss %xmm8, 168(%rsp)
movss 368(%rsp), %xmm8
movss %xmm8, 160(%rsp)
movss 360(%rsp), %xmm8
movss %xmm8, 152(%rsp)
movss 352(%rsp), %xmm8
movss %xmm8, 144(%rsp)
movss 344(%rsp), %xmm8
movss %xmm8, 136(%rsp)
movss 336(%rsp), %xmm8
movss %xmm8, 128(%rsp)
movss 328(%rsp), %xmm8
movss %xmm8, 120(%rsp)
movss 320(%rsp), %xmm8
movss %xmm8, 112(%rsp)
movss 312(%rsp), %xmm8
movss %xmm8, 104(%rsp)
movss 304(%rsp), %xmm8
movss %xmm8, 96(%rsp)
movss 296(%rsp), %xmm8
movss %xmm8, 88(%rsp)
movss 288(%rsp), %xmm8
movss %xmm8, 80(%rsp)
movss 280(%rsp), %xmm8
movss %xmm8, 72(%rsp)
movss 272(%rsp), %xmm8
movss %xmm8, 64(%rsp)
movss 264(%rsp), %xmm8
movss %xmm8, 56(%rsp)
movss 256(%rsp), %xmm8
movss %xmm8, 48(%rsp)
movss 248(%rsp), %xmm8
movss %xmm8, 40(%rsp)
movss 240(%rsp), %xmm8
movss %xmm8, 32(%rsp)
movss 232(%rsp), %xmm8
movss %xmm8, 24(%rsp)
movss 224(%rsp), %xmm8
movss %xmm8, 16(%rsp)
movss 216(%rsp), %xmm8
movss %xmm8, 8(%rsp)
movss 208(%rsp), %xmm8
movss %xmm8, (%rsp)
call _Z58__device_stub__Z7computefiiffffffffffffffffffffffffffffffffiifffffffffffffffffffffffffffffff
addq $200, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7computefiifffffffffffffffffffffffffffffff, .-_Z7computefiifffffffffffffffffffffffffffffff
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $288, %rsp
.cfi_def_cfa_offset 320
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 248(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 32(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 240(%rsp)
movq 40(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 232(%rsp)
movq 48(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 224(%rsp)
movq 56(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 216(%rsp)
movq 64(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 208(%rsp)
movq 72(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 200(%rsp)
movq 80(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 192(%rsp)
movq 88(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 184(%rsp)
movq 96(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 176(%rsp)
movq 104(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 168(%rsp)
movq 112(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 160(%rsp)
movq 120(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 152(%rsp)
movq 128(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 144(%rsp)
movq 136(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 136(%rsp)
movq 144(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 128(%rsp)
movq 152(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 120(%rsp)
movq 160(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 112(%rsp)
movq 168(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 104(%rsp)
movq 176(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 96(%rsp)
movq 184(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 88(%rsp)
movq 192(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 80(%rsp)
movq 200(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 72(%rsp)
movq 208(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 64(%rsp)
movq 216(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 56(%rsp)
movq 224(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 48(%rsp)
movq 232(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 40(%rsp)
movq 240(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 32(%rsp)
movq 248(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 24(%rsp)
movq 256(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 16(%rsp)
movq 264(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 8(%rsp)
movq 272(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, (%rsp)
movl $1, 276(%rsp)
movl $1, 280(%rsp)
movl $1, 264(%rsp)
movl $1, 268(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 276(%rsp), %rdx
movl $1, %ecx
movq 264(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $288, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pxor %xmm0, %xmm0
cvtsd2ss 248(%rsp), %xmm0
pxor %xmm1, %xmm1
cvtsd2ss (%rsp), %xmm1
leaq -192(%rsp), %rsp
.cfi_def_cfa_offset 512
movss %xmm1, 184(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 200(%rsp), %xmm1
movss %xmm1, 176(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 208(%rsp), %xmm1
movss %xmm1, 168(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 216(%rsp), %xmm1
movss %xmm1, 160(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 224(%rsp), %xmm1
movss %xmm1, 152(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 232(%rsp), %xmm1
movss %xmm1, 144(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 240(%rsp), %xmm1
movss %xmm1, 136(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 248(%rsp), %xmm1
movss %xmm1, 128(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 256(%rsp), %xmm1
movss %xmm1, 120(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 264(%rsp), %xmm1
movss %xmm1, 112(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 272(%rsp), %xmm1
movss %xmm1, 104(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 280(%rsp), %xmm1
movss %xmm1, 96(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 288(%rsp), %xmm1
movss %xmm1, 88(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 296(%rsp), %xmm1
movss %xmm1, 80(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 304(%rsp), %xmm1
movss %xmm1, 72(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 312(%rsp), %xmm1
movss %xmm1, 64(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 320(%rsp), %xmm1
movss %xmm1, 56(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 328(%rsp), %xmm1
movss %xmm1, 48(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 336(%rsp), %xmm1
movss %xmm1, 40(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 344(%rsp), %xmm1
movss %xmm1, 32(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 352(%rsp), %xmm1
movss %xmm1, 24(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 360(%rsp), %xmm1
movss %xmm1, 16(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 368(%rsp), %xmm1
movss %xmm1, 8(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 376(%rsp), %xmm1
movss %xmm1, (%rsp)
pxor %xmm7, %xmm7
cvtsd2ss 384(%rsp), %xmm7
pxor %xmm6, %xmm6
cvtsd2ss 392(%rsp), %xmm6
pxor %xmm5, %xmm5
cvtsd2ss 400(%rsp), %xmm5
pxor %xmm4, %xmm4
cvtsd2ss 408(%rsp), %xmm4
pxor %xmm3, %xmm3
cvtsd2ss 416(%rsp), %xmm3
pxor %xmm2, %xmm2
cvtsd2ss 424(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtsd2ss 432(%rsp), %xmm1
movl %ebp, %esi
movl %r12d, %edi
call _Z58__device_stub__Z7computefiiffffffffffffffffffffffffffffffffiifffffffffffffffffffffffffffffff
addq $192, %rsp
.cfi_def_cfa_offset 320
jmp .L16
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z7computefiifffffffffffffffffffffffffffffff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computefiifffffffffffffffffffffffffffffff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
.globl _Z22__device_stub__computefiifffffffffffffffffffffffffffffff # -- Begin function _Z22__device_stub__computefiifffffffffffffffffffffffffffffff
.p2align 4, 0x90
.type _Z22__device_stub__computefiifffffffffffffffffffffffffffffff,@function
_Z22__device_stub__computefiifffffffffffffffffffffffffffffff: # @_Z22__device_stub__computefiifffffffffffffffffffffffffffffff
.cfi_startproc
# %bb.0:
subq $376, %rsp # imm = 0x178
.cfi_def_cfa_offset 384
movss %xmm0, 44(%rsp)
movl %edi, 40(%rsp)
movl %esi, 36(%rsp)
movss %xmm1, 32(%rsp)
movss %xmm2, 28(%rsp)
movss %xmm3, 24(%rsp)
movss %xmm4, 20(%rsp)
movss %xmm5, 16(%rsp)
movss %xmm6, 12(%rsp)
movss %xmm7, 8(%rsp)
leaq 44(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rax
movq %rax, 104(%rsp)
leaq 36(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
leaq 384(%rsp), %rax
movq %rax, 176(%rsp)
leaq 392(%rsp), %rax
movq %rax, 184(%rsp)
leaq 400(%rsp), %rax
movq %rax, 192(%rsp)
leaq 408(%rsp), %rax
movq %rax, 200(%rsp)
leaq 416(%rsp), %rax
movq %rax, 208(%rsp)
leaq 424(%rsp), %rax
movq %rax, 216(%rsp)
leaq 432(%rsp), %rax
movq %rax, 224(%rsp)
leaq 440(%rsp), %rax
movq %rax, 232(%rsp)
leaq 448(%rsp), %rax
movq %rax, 240(%rsp)
leaq 456(%rsp), %rax
movq %rax, 248(%rsp)
leaq 464(%rsp), %rax
movq %rax, 256(%rsp)
leaq 472(%rsp), %rax
movq %rax, 264(%rsp)
leaq 480(%rsp), %rax
movq %rax, 272(%rsp)
leaq 488(%rsp), %rax
movq %rax, 280(%rsp)
leaq 496(%rsp), %rax
movq %rax, 288(%rsp)
leaq 504(%rsp), %rax
movq %rax, 296(%rsp)
leaq 512(%rsp), %rax
movq %rax, 304(%rsp)
leaq 520(%rsp), %rax
movq %rax, 312(%rsp)
leaq 528(%rsp), %rax
movq %rax, 320(%rsp)
leaq 536(%rsp), %rax
movq %rax, 328(%rsp)
leaq 544(%rsp), %rax
movq %rax, 336(%rsp)
leaq 552(%rsp), %rax
movq %rax, 344(%rsp)
leaq 560(%rsp), %rax
movq %rax, 352(%rsp)
leaq 568(%rsp), %rax
movq %rax, 360(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7computefiifffffffffffffffffffffffffffffff, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $392, %rsp # imm = 0x188
.cfi_adjust_cfa_offset -392
retq
.Lfunc_end0:
.size _Z22__device_stub__computefiifffffffffffffffffffffffffffffff, .Lfunc_end0-_Z22__device_stub__computefiifffffffffffffffffffffffffffffff
.cfi_endproc
# -- End function
.globl _Z11initPointerf # -- Begin function _Z11initPointerf
.p2align 4, 0x90
.type _Z11initPointerf,@function
_Z11initPointerf: # @_Z11initPointerf
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm0, 4(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $448, %rsp # imm = 0x1C0
.cfi_def_cfa_offset 480
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %r15
movq 8(%rsi), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 440(%rsp) # 8-byte Spill
movq 16(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 24(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 32(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 432(%rsp) # 8-byte Spill
movq 40(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 424(%rsp) # 8-byte Spill
movq 48(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 312(%rsp) # 8-byte Spill
movq 56(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 304(%rsp) # 8-byte Spill
movq 64(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 296(%rsp) # 8-byte Spill
movq 72(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 288(%rsp) # 8-byte Spill
movq 80(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 280(%rsp) # 8-byte Spill
movq 88(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 272(%rsp) # 8-byte Spill
movq 96(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 264(%rsp) # 8-byte Spill
movq 104(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 256(%rsp) # 8-byte Spill
movq 112(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 248(%rsp) # 8-byte Spill
movq 120(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 240(%rsp) # 8-byte Spill
movq 128(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 232(%rsp) # 8-byte Spill
movq 136(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 224(%rsp) # 8-byte Spill
movq 144(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 216(%rsp) # 8-byte Spill
movq 152(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 208(%rsp) # 8-byte Spill
movq 160(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 200(%rsp) # 8-byte Spill
movq 168(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 192(%rsp) # 8-byte Spill
movq 176(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 416(%rsp) # 8-byte Spill
movq 184(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 408(%rsp) # 8-byte Spill
movq 192(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 400(%rsp) # 8-byte Spill
movq 200(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 392(%rsp) # 8-byte Spill
movq 208(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 384(%rsp) # 8-byte Spill
movq 216(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 376(%rsp) # 8-byte Spill
movq 224(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 368(%rsp) # 8-byte Spill
movq 232(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 360(%rsp) # 8-byte Spill
movq 240(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 352(%rsp) # 8-byte Spill
movq 248(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 344(%rsp) # 8-byte Spill
movq 256(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 336(%rsp) # 8-byte Spill
movq 264(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 328(%rsp) # 8-byte Spill
movq 272(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 320(%rsp) # 8-byte Spill
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movsd 320(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm8
movsd 328(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm9
movsd 336(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm10
movsd 344(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm11
movsd 352(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm12
movsd 360(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm13
movsd 368(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm14
movsd 376(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm15
movsd 384(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm3
movsd 392(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm4
movsd 400(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm5
movsd 408(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm6
movsd 416(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm7
movsd 192(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 192(%rsp) # 4-byte Spill
movsd 200(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 200(%rsp) # 4-byte Spill
movsd 208(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 208(%rsp) # 4-byte Spill
movsd 216(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 216(%rsp) # 4-byte Spill
movsd 224(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 224(%rsp) # 4-byte Spill
movsd 232(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 232(%rsp) # 4-byte Spill
movsd 240(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 240(%rsp) # 4-byte Spill
movsd 248(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 248(%rsp) # 4-byte Spill
movsd 256(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 256(%rsp) # 4-byte Spill
movsd 264(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 264(%rsp) # 4-byte Spill
movsd 272(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 272(%rsp) # 4-byte Spill
movsd 280(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 280(%rsp) # 4-byte Spill
movsd 288(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 288(%rsp) # 4-byte Spill
movsd 296(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 296(%rsp) # 4-byte Spill
movsd 304(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 304(%rsp) # 4-byte Spill
movsd 312(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 312(%rsp) # 4-byte Spill
movsd 424(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm2
movsd 432(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm1
movsd 440(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm8, 184(%rsp)
movss %xmm9, 176(%rsp)
movss %xmm10, 168(%rsp)
movss %xmm11, 160(%rsp)
movss %xmm12, 152(%rsp)
movss %xmm13, 144(%rsp)
movss %xmm14, 136(%rsp)
movss %xmm15, 128(%rsp)
movss %xmm3, 120(%rsp)
movss %xmm4, 112(%rsp)
movss %xmm5, 104(%rsp)
movss %xmm6, 96(%rsp)
movss %xmm7, 88(%rsp)
movss 192(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 80(%rsp)
movss 200(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 72(%rsp)
movss 208(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 64(%rsp)
movss 216(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 56(%rsp)
movss 224(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 48(%rsp)
movss 232(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 40(%rsp)
movss 240(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 32(%rsp)
movss 248(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 24(%rsp)
movss 256(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 16(%rsp)
movss 264(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 8(%rsp)
movss 272(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, (%rsp)
movl %ebx, %edi
movl %r14d, %esi
movss 312(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss 304(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss 296(%rsp), %xmm5 # 4-byte Reload
# xmm5 = mem[0],zero,zero,zero
movss 288(%rsp), %xmm6 # 4-byte Reload
# xmm6 = mem[0],zero,zero,zero
movss 280(%rsp), %xmm7 # 4-byte Reload
# xmm7 = mem[0],zero,zero,zero
callq _Z22__device_stub__computefiifffffffffffffffffffffffffffffff
.LBB2_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $448, %rsp # imm = 0x1C0
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computefiifffffffffffffffffffffffffffffff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computefiifffffffffffffffffffffffffffffff,@object # @_Z7computefiifffffffffffffffffffffffffffffff
.section .rodata,"a",@progbits
.globl _Z7computefiifffffffffffffffffffffffffffffff
.p2align 3, 0x0
_Z7computefiifffffffffffffffffffffffffffffff:
.quad _Z22__device_stub__computefiifffffffffffffffffffffffffffffff
.size _Z7computefiifffffffffffffffffffffffffffffff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7computefiifffffffffffffffffffffffffffffff"
.size .L__unnamed_1, 45
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computefiifffffffffffffffffffffffffffffff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computefiifffffffffffffffffffffffffffffff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime.h>
#include <stdio.h>
#include <iostream>
using namespace std;
__global__ void func(float* ptr){
int pos = blockIdx.x * blockDim.x + threadIdx.x;
if(pos == 999){
ptr[999] = 5;
}
}
int main(){
float* ptr = nullptr;
// 因为核函数是异步的，因此不会立即检查到他是否存在异常
func<<<100, 10>>>(ptr);
//func<<<100, 1050>>>(ptr);
auto code1 = cudaPeekAtLastError();
cout << cudaGetErrorString(code1) << endl;
// 对当前设备的核函数进行同步，等待执行完毕，可以发现过程是否存在异常
auto code2 = cudaDeviceSynchronize();
cout << cudaGetErrorString(code2) << endl;
// 异常会一直存在，以至于后续的函数都会失败
float* new_ptr = nullptr;
auto code3 = cudaMalloc(&new_ptr, 100);
cout << cudaGetErrorString(code3) << endl;
return 0;
} | code for sm_80
Function : _Z4funcPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.NE.AND P0, PT, R0, 0x3e7, PT ; /* 0x000003e70000780c */
/* 0x000fda0003f05270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, 0x40a00000 ; /* 0x40a00000ff057424 */
/* 0x000fe200078e00ff */
/*0070*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fca0000000f00 */
/*00a0*/ STG.E [R2.64+0xf9c], R5 ; /* 0x000f9c0502007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
#include <stdio.h>
#include <iostream>
using namespace std;
__global__ void func(float* ptr){
int pos = blockIdx.x * blockDim.x + threadIdx.x;
if(pos == 999){
ptr[999] = 5;
}
}
int main(){
float* ptr = nullptr;
// 因为核函数是异步的，因此不会立即检查到他是否存在异常
func<<<100, 10>>>(ptr);
//func<<<100, 1050>>>(ptr);
auto code1 = cudaPeekAtLastError();
cout << cudaGetErrorString(code1) << endl;
// 对当前设备的核函数进行同步，等待执行完毕，可以发现过程是否存在异常
auto code2 = cudaDeviceSynchronize();
cout << cudaGetErrorString(code2) << endl;
// 异常会一直存在，以至于后续的函数都会失败
float* new_ptr = nullptr;
auto code3 = cudaMalloc(&new_ptr, 100);
cout << cudaGetErrorString(code3) << endl;
return 0;
} | .file "tmpxft_0015bc1c_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z4funcPfPf
.type _Z23__device_stub__Z4funcPfPf, @function
_Z23__device_stub__Z4funcPfPf:
.LFB3694:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4funcPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z23__device_stub__Z4funcPfPf, .-_Z23__device_stub__Z4funcPfPf
.globl _Z4funcPf
.type _Z4funcPf, @function
_Z4funcPf:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z4funcPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z4funcPf, .-_Z4funcPf
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $10, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $100, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 12(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
call cudaPeekAtLastError@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call cudaDeviceSynchronize@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq $0, 24(%rsp)
leaq 24(%rsp), %rdi
movl $100, %esi
call cudaMalloc@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl $0, %edi
call _Z23__device_stub__Z4funcPfPf
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4funcPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4funcPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
#include <stdio.h>
#include <iostream>
using namespace std;
__global__ void func(float* ptr){
int pos = blockIdx.x * blockDim.x + threadIdx.x;
if(pos == 999){
ptr[999] = 5;
}
}
int main(){
float* ptr = nullptr;
// 因为核函数是异步的，因此不会立即检查到他是否存在异常
func<<<100, 10>>>(ptr);
//func<<<100, 1050>>>(ptr);
auto code1 = cudaPeekAtLastError();
cout << cudaGetErrorString(code1) << endl;
// 对当前设备的核函数进行同步，等待执行完毕，可以发现过程是否存在异常
auto code2 = cudaDeviceSynchronize();
cout << cudaGetErrorString(code2) << endl;
// 异常会一直存在，以至于后续的函数都会失败
float* new_ptr = nullptr;
auto code3 = cudaMalloc(&new_ptr, 100);
cout << cudaGetErrorString(code3) << endl;
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
using namespace std;
__global__ void func(float* ptr){
int pos = blockIdx.x * blockDim.x + threadIdx.x;
if(pos == 999){
ptr[999] = 5;
}
}
int main(){
float* ptr = nullptr;
// 因为核函数是异步的，因此不会立即检查到他是否存在异常
func<<<100, 10>>>(ptr);
//func<<<100, 1050>>>(ptr);
auto code1 = hipPeekAtLastError();
cout << hipGetErrorString(code1) << endl;
// 对当前设备的核函数进行同步，等待执行完毕，可以发现过程是否存在异常
auto code2 = hipDeviceSynchronize();
cout << hipGetErrorString(code2) << endl;
// 异常会一直存在，以至于后续的函数都会失败
float* new_ptr = nullptr;
auto code3 = hipMalloc(&new_ptr, 100);
cout << hipGetErrorString(code3) << endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
using namespace std;
__global__ void func(float* ptr){
int pos = blockIdx.x * blockDim.x + threadIdx.x;
if(pos == 999){
ptr[999] = 5;
}
}
int main(){
float* ptr = nullptr;
// 因为核函数是异步的，因此不会立即检查到他是否存在异常
func<<<100, 10>>>(ptr);
//func<<<100, 1050>>>(ptr);
auto code1 = hipPeekAtLastError();
cout << hipGetErrorString(code1) << endl;
// 对当前设备的核函数进行同步，等待执行完毕，可以发现过程是否存在异常
auto code2 = hipDeviceSynchronize();
cout << hipGetErrorString(code2) << endl;
// 异常会一直存在，以至于后续的函数都会失败
float* new_ptr = nullptr;
auto code3 = hipMalloc(&new_ptr, 100);
cout << hipGetErrorString(code3) << endl;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4funcPf
.globl _Z4funcPf
.p2align 8
.type _Z4funcPf,@function
_Z4funcPf:
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0x3e7, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x40a00000
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1] offset:3996
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4funcPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4funcPf, .Lfunc_end0-_Z4funcPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4funcPf
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z4funcPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
using namespace std;
__global__ void func(float* ptr){
int pos = blockIdx.x * blockDim.x + threadIdx.x;
if(pos == 999){
ptr[999] = 5;
}
}
int main(){
float* ptr = nullptr;
// 因为核函数是异步的，因此不会立即检查到他是否存在异常
func<<<100, 10>>>(ptr);
//func<<<100, 1050>>>(ptr);
auto code1 = hipPeekAtLastError();
cout << hipGetErrorString(code1) << endl;
// 对当前设备的核函数进行同步，等待执行完毕，可以发现过程是否存在异常
auto code2 = hipDeviceSynchronize();
cout << hipGetErrorString(code2) << endl;
// 异常会一直存在，以至于后续的函数都会失败
float* new_ptr = nullptr;
auto code3 = hipMalloc(&new_ptr, 100);
cout << hipGetErrorString(code3) << endl;
return 0;
} | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z19__device_stub__funcPf # -- Begin function _Z19__device_stub__funcPf
.p2align 4, 0x90
.type _Z19__device_stub__funcPf,@function
_Z19__device_stub__funcPf: # @_Z19__device_stub__funcPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z4funcPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z19__device_stub__funcPf, .Lfunc_end0-_Z19__device_stub__funcPf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $64, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -16
movabsq $4294967306, %rdx # imm = 0x10000000A
leaq 90(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq $0, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 16(%rsp)
movq %rsp, %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z4funcPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipPeekAtLastError
movl %eax, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB1_3
# %bb.4:
movq %rax, %rdi
movq %rax, %rbx
callq strlen
movl $_ZSt4cout, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_5
.LBB1_3:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_5: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_24
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_8
# %bb.7:
movzbl 67(%rbx), %eax
jmp .LBB1_9
.LBB1_8:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_9: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq hipDeviceSynchronize
movl %eax, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB1_10
# %bb.11:
movq %rax, %rdi
movq %rax, %rbx
callq strlen
movl $_ZSt4cout, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_12
.LBB1_10:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_12: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit6
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_24
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i10
cmpb $0, 56(%rbx)
je .LBB1_15
# %bb.14:
movzbl 67(%rbx), %eax
jmp .LBB1_16
.LBB1_15:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit13
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq $0, (%rsp)
movq %rsp, %rdi
movl $100, %esi
callq hipMalloc
movl %eax, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB1_17
# %bb.18:
movq %rax, %rdi
movq %rax, %rbx
callq strlen
movl $_ZSt4cout, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_19
.LBB1_17:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_19: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit8
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_24
# %bb.20: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i15
cmpb $0, 56(%rbx)
je .LBB1_22
# %bb.21:
movzbl 67(%rbx), %eax
jmp .LBB1_23
.LBB1_22:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_23: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit18
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $64, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_24:
.cfi_def_cfa_offset 80
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4funcPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4funcPf,@object # @_Z4funcPf
.section .rodata,"a",@progbits
.globl _Z4funcPf
.p2align 3, 0x0
_Z4funcPf:
.quad _Z19__device_stub__funcPf
.size _Z4funcPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4funcPf"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__funcPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4funcPf
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4funcPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.NE.AND P0, PT, R0, 0x3e7, PT ; /* 0x000003e70000780c */
/* 0x000fda0003f05270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, 0x40a00000 ; /* 0x40a00000ff057424 */
/* 0x000fe200078e00ff */
/*0070*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fca0000000f00 */
/*00a0*/ STG.E [R2.64+0xf9c], R5 ; /* 0x000f9c0502007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4funcPf
.globl _Z4funcPf
.p2align 8
.type _Z4funcPf,@function
_Z4funcPf:
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0x3e7, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x40a00000
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1] offset:3996
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4funcPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4funcPf, .Lfunc_end0-_Z4funcPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4funcPf
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z4funcPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0015bc1c_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z4funcPfPf
.type _Z23__device_stub__Z4funcPfPf, @function
_Z23__device_stub__Z4funcPfPf:
.LFB3694:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4funcPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z23__device_stub__Z4funcPfPf, .-_Z23__device_stub__Z4funcPfPf
.globl _Z4funcPf
.type _Z4funcPf, @function
_Z4funcPf:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z4funcPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z4funcPf, .-_Z4funcPf
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $10, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $100, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 12(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
call cudaPeekAtLastError@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call cudaDeviceSynchronize@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq $0, 24(%rsp)
leaq 24(%rsp), %rdi
movl $100, %esi
call cudaMalloc@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl $0, %edi
call _Z23__device_stub__Z4funcPfPf
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4funcPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4funcPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z19__device_stub__funcPf # -- Begin function _Z19__device_stub__funcPf
.p2align 4, 0x90
.type _Z19__device_stub__funcPf,@function
_Z19__device_stub__funcPf: # @_Z19__device_stub__funcPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z4funcPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z19__device_stub__funcPf, .Lfunc_end0-_Z19__device_stub__funcPf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $64, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -16
movabsq $4294967306, %rdx # imm = 0x10000000A
leaq 90(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq $0, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 16(%rsp)
movq %rsp, %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z4funcPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipPeekAtLastError
movl %eax, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB1_3
# %bb.4:
movq %rax, %rdi
movq %rax, %rbx
callq strlen
movl $_ZSt4cout, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_5
.LBB1_3:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_5: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_24
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_8
# %bb.7:
movzbl 67(%rbx), %eax
jmp .LBB1_9
.LBB1_8:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_9: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq hipDeviceSynchronize
movl %eax, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB1_10
# %bb.11:
movq %rax, %rdi
movq %rax, %rbx
callq strlen
movl $_ZSt4cout, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_12
.LBB1_10:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_12: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit6
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_24
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i10
cmpb $0, 56(%rbx)
je .LBB1_15
# %bb.14:
movzbl 67(%rbx), %eax
jmp .LBB1_16
.LBB1_15:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit13
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq $0, (%rsp)
movq %rsp, %rdi
movl $100, %esi
callq hipMalloc
movl %eax, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB1_17
# %bb.18:
movq %rax, %rdi
movq %rax, %rbx
callq strlen
movl $_ZSt4cout, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_19
.LBB1_17:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_19: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit8
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_24
# %bb.20: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i15
cmpb $0, 56(%rbx)
je .LBB1_22
# %bb.21:
movzbl 67(%rbx), %eax
jmp .LBB1_23
.LBB1_22:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_23: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit18
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $64, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_24:
.cfi_def_cfa_offset 80
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4funcPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4funcPf,@object # @_Z4funcPf
.section .rodata,"a",@progbits
.globl _Z4funcPf
.p2align 3, 0x0
_Z4funcPf:
.quad _Z19__device_stub__funcPf
.size _Z4funcPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4funcPf"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__funcPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4funcPf
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <string.h>
#include <stdio.h>
#include <iostream>
struct DataElement
{
char *name;
int value;
};
__global__
void Kernel(DataElement *elem) {
printf("On device: name=%s, value=%d\n", elem->name, elem->value);
elem->name[0] = 'd';
elem->value++;
}
void launch(DataElement *elem, cudaStream_t &stream) {
Kernel<<< 1, 1, 0, stream >>>(elem);
//cudaDeviceSynchronize();
}
void iteration(cudaStream_t &stream)
{
DataElement *e;
cudaMallocManaged((void**)&e, sizeof(DataElement));
e->value = 10;
cudaMallocManaged((void**)&(e->name), sizeof(char) * (strlen("hello") + 1) );
strcpy(e->name, "hello");
launch(e, stream);
printf("On host: name=%s, value=%d\n", e->name, e->value);
cudaFree(e->name);
cudaFree(e);
}
int main(void)
{
cudaError_t err;
int count = 0;
err = cudaGetDeviceCount(&count);
std::cout << count << " devices found." << std::endl;
for (int d=0;d<count;d++) {
err = cudaSetDevice(d);
if (err != cudaSuccess) {
std::cout << "error setting device, #=" << cudaGetErrorString(err) << std::endl;
}
cudaDeviceProp deviceProp;
err = cudaGetDeviceProperties(&deviceProp, d);
if (err != cudaSuccess) {
std::cout << "error getting device properties, #=" << cudaGetErrorString(err) << std::endl;
}
std::cout << "Using device " << d << ", name: " << deviceProp.name << std::endl;
for (int s = 0 ; s < 10 ; s++) {
cudaStream_t stream;
err = cudaStreamCreate(&stream);
if (err != cudaSuccess) {
std::cout << "error in stream creation, #=" << cudaGetErrorString(err) << std::endl;
}
iteration(stream);
cudaStreamDestroy(stream);
}
}
} | code for sm_80
Function : _Z6KernelP11DataElement
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff107624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR36, c[0x0][0x118] ; /* 0x0000460000247ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff117624 */
/* 0x000fe200078e00ff */
/*0040*/ IADD3 R1, R1, -0x10, RZ ; /* 0xfffffff001017810 */
/* 0x000fc80007ffe0ff */
/*0050*/ LDG.E.64 R8, [R16.64] ; /* 0x0000002410087981 */
/* 0x000ea8000c1e1b00 */
/*0060*/ LDG.E R0, [R16.64+0x8] ; /* 0x0000082410007981 */
/* 0x000ee2000c1e1900 */
/*0070*/ MOV R2, 0x0 ; /* 0x0000000000027802 */
/* 0x000fe20000000f00 */
/*0080*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0090*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*00a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fc600078e00ff */
/*00b0*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000e220000000a00 */
/*00c0*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*00d0*/ STL.64 [R1], R8 ; /* 0x0000000801007387 */
/* 0x0043e80000100a00 */
/*00e0*/ STL [R1+0x8], R0 ; /* 0x0000080001007387 */
/* 0x0083e60000100800 */
/*00f0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x003fe20000000000 */
/*0100*/ MOV R11, 0x170 ; /* 0x00000170000b7802 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R20, 0xf0 ; /* 0x000000f000147802 */
/* 0x000fe40000000f00 */
/*0120*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fc40000000f00 */
/*0130*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0140*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0150*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0160*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x000fea0003c00000 */
/*0170*/ LDG.E.64 R2, [R16.64] ; /* 0x0000002410027981 */
/* 0x000ea2000c1e1b00 */
/*0180*/ IMAD.MOV.U32 R4, RZ, RZ, 0x64 ; /* 0x00000064ff047424 */
/* 0x000fca00078e00ff */
/*0190*/ ST.E.U8 [R2.64], R4 ; /* 0x0000000402007985 */
/* 0x004fe8000c101124 */
/*01a0*/ LDG.E R0, [R16.64+0x8] ; /* 0x0000082410007981 */
/* 0x000ea4000c1e1900 */
/*01b0*/ IADD3 R5, R0, 0x1, RZ ; /* 0x0000000100057810 */
/* 0x004fca0007ffe0ff */
/*01c0*/ STG.E [R16.64+0x8], R5 ; /* 0x0000080510007986 */
/* 0x000fe2000c101924 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <string.h>
#include <stdio.h>
#include <iostream>
struct DataElement
{
char *name;
int value;
};
__global__
void Kernel(DataElement *elem) {
printf("On device: name=%s, value=%d\n", elem->name, elem->value);
elem->name[0] = 'd';
elem->value++;
}
void launch(DataElement *elem, cudaStream_t &stream) {
Kernel<<< 1, 1, 0, stream >>>(elem);
//cudaDeviceSynchronize();
}
void iteration(cudaStream_t &stream)
{
DataElement *e;
cudaMallocManaged((void**)&e, sizeof(DataElement));
e->value = 10;
cudaMallocManaged((void**)&(e->name), sizeof(char) * (strlen("hello") + 1) );
strcpy(e->name, "hello");
launch(e, stream);
printf("On host: name=%s, value=%d\n", e->name, e->value);
cudaFree(e->name);
cudaFree(e);
}
int main(void)
{
cudaError_t err;
int count = 0;
err = cudaGetDeviceCount(&count);
std::cout << count << " devices found." << std::endl;
for (int d=0;d<count;d++) {
err = cudaSetDevice(d);
if (err != cudaSuccess) {
std::cout << "error setting device, #=" << cudaGetErrorString(err) << std::endl;
}
cudaDeviceProp deviceProp;
err = cudaGetDeviceProperties(&deviceProp, d);
if (err != cudaSuccess) {
std::cout << "error getting device properties, #=" << cudaGetErrorString(err) << std::endl;
}
std::cout << "Using device " << d << ", name: " << deviceProp.name << std::endl;
for (int s = 0 ; s < 10 ; s++) {
cudaStream_t stream;
err = cudaStreamCreate(&stream);
if (err != cudaSuccess) {
std::cout << "error in stream creation, #=" << cudaGetErrorString(err) << std::endl;
}
iteration(stream);
cudaStreamDestroy(stream);
}
}
} | .file "tmpxft_0016eee6_00000000-6_dataElem_um.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z6KernelP11DataElementP11DataElement
.type _Z37__device_stub__Z6KernelP11DataElementP11DataElement, @function
_Z37__device_stub__Z6KernelP11DataElementP11DataElement:
.LFB3696:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6KernelP11DataElement(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z37__device_stub__Z6KernelP11DataElementP11DataElement, .-_Z37__device_stub__Z6KernelP11DataElementP11DataElement
.globl _Z6KernelP11DataElement
.type _Z6KernelP11DataElement, @function
_Z6KernelP11DataElement:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z6KernelP11DataElementP11DataElement
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z6KernelP11DataElement, .-_Z6KernelP11DataElement
.globl _Z6launchP11DataElementRP11CUstream_st
.type _Z6launchP11DataElementRP11CUstream_st, @function
_Z6launchP11DataElementRP11CUstream_st:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $32, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movq (%rsi), %r9
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movq %rbx, %rdi
call _Z37__device_stub__Z6KernelP11DataElementP11DataElement
jmp .L11
.cfi_endproc
.LFE3669:
.size _Z6launchP11DataElementRP11CUstream_st, .-_Z6launchP11DataElementRP11CUstream_st
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "On host: name=%s, value=%d\n"
.text
.globl _Z9iterationRP11CUstream_st
.type _Z9iterationRP11CUstream_st, @function
_Z9iterationRP11CUstream_st:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $1, %edx
movl $16, %esi
call cudaMallocManaged@PLT
movq (%rsp), %rdi
movl $10, 8(%rdi)
movl $1, %edx
movl $6, %esi
call cudaMallocManaged@PLT
movq (%rsp), %rax
movq (%rax), %rax
movl $1819043176, (%rax)
movw $111, 4(%rax)
movq %rbx, %rsi
movq (%rsp), %rdi
call _Z6launchP11DataElementRP11CUstream_st
movq (%rsp), %rax
movl 8(%rax), %ecx
movq (%rax), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rax
movq (%rax), %rdi
call cudaFree@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size _Z9iterationRP11CUstream_st, .-_Z9iterationRP11CUstream_st
.section .rodata.str1.1
.LC1:
.string " devices found."
.LC2:
.string "error setting device, #="
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "error getting device properties, #="
.section .rodata.str1.1
.LC4:
.string "Using device "
.LC5:
.string ", name: "
.LC6:
.string "error in stream creation, #="
.text
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1064, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
movl $0, 4(%rsp)
leaq 4(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 4(%rsp), %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
cmpl $0, 4(%rsp)
jle .L20
movl $0, %r14d
leaq _ZSt4cout(%rip), %r12
leaq .LC6(%rip), %r15
jmp .L47
.L64:
movl $24, %edx
leaq .LC2(%rip), %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rbx
testq %rax, %rax
je .L52
movq %rax, %rdi
call strlen@PLT
movq %rax, %rdx
movq %rbx, %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L23:
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %rbx
testq %rbx, %rbx
je .L53
cmpb $0, 56(%rbx)
je .L26
movzbl 67(%rbx), %esi
.L27:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L21
.L52:
leaq _ZSt4cout(%rip), %rdi
movq _ZSt4cout(%rip), %rax
addq -24(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L23
.L53:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L54
call _ZSt16__throw_bad_castv@PLT
.L54:
call __stack_chk_fail@PLT
.L26:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L27
.L65:
movl $35, %edx
leaq .LC3(%rip), %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rbx
testq %rax, %rax
je .L55
movq %rax, %rdi
call strlen@PLT
movq %rax, %rdx
movq %rbx, %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L30:
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %rbx
testq %rbx, %rbx
je .L56
cmpb $0, 56(%rbx)
je .L33
movzbl 67(%rbx), %esi
.L34:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L28
.L55:
leaq _ZSt4cout(%rip), %rdi
movq _ZSt4cout(%rip), %rax
addq -24(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L30
.L56:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L57
call _ZSt16__throw_bad_castv@PLT
.L57:
call __stack_chk_fail@PLT
.L33:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L34
.L66:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L58
call _ZSt16__throw_bad_castv@PLT
.L58:
call __stack_chk_fail@PLT
.L37:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L38
.L61:
movq (%r12), %rax
movq %r12, %rdi
addq -24(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L41
.L62:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L59
call _ZSt16__throw_bad_castv@PLT
.L59:
call __stack_chk_fail@PLT
.L63:
movzbl 67(%rbx), %esi
.L45:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.L39:
movq %r13, %rdi
call _Z9iterationRP11CUstream_st
movq 8(%rsp), %rdi
call cudaStreamDestroy@PLT
subl $1, %ebp
je .L60
.L46:
movq %r13, %rdi
call cudaStreamCreate@PLT
movl %eax, %ebx
testl %eax, %eax
je .L39
movl $28, %edx
movq %r15, %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rbx
testq %rax, %rax
je .L61
movq %rax, %rdi
call strlen@PLT
movq %rax, %rdx
movq %rbx, %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L41:
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %rbx
testq %rbx, %rbx
je .L62
cmpb $0, 56(%rbx)
jne .L63
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L45
.L60:
addl $1, %r14d
cmpl %r14d, 4(%rsp)
jle .L20
.L47:
movl %r14d, %edi
call cudaSetDevice@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L64
.L21:
leaq 16(%rsp), %rdi
movl %r14d, %esi
call cudaGetDeviceProperties_v2@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L65
.L28:
movl $13, %edx
leaq .LC4(%rip), %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r14d, %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $8, %edx
leaq .LC5(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
leaq 16(%rsp), %rbp
movq %rbp, %rdi
call strlen@PLT
movq %rax, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L66
cmpb $0, 56(%rbp)
je .L37
movzbl 67(%rbp), %esi
.L38:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $10, %ebp
leaq 8(%rsp), %r13
jmp .L46
.L20:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L67
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L67:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z6KernelP11DataElement"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z6KernelP11DataElement(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <string.h>
#include <stdio.h>
#include <iostream>
struct DataElement
{
char *name;
int value;
};
__global__
void Kernel(DataElement *elem) {
printf("On device: name=%s, value=%d\n", elem->name, elem->value);
elem->name[0] = 'd';
elem->value++;
}
void launch(DataElement *elem, cudaStream_t &stream) {
Kernel<<< 1, 1, 0, stream >>>(elem);
//cudaDeviceSynchronize();
}
void iteration(cudaStream_t &stream)
{
DataElement *e;
cudaMallocManaged((void**)&e, sizeof(DataElement));
e->value = 10;
cudaMallocManaged((void**)&(e->name), sizeof(char) * (strlen("hello") + 1) );
strcpy(e->name, "hello");
launch(e, stream);
printf("On host: name=%s, value=%d\n", e->name, e->value);
cudaFree(e->name);
cudaFree(e);
}
int main(void)
{
cudaError_t err;
int count = 0;
err = cudaGetDeviceCount(&count);
std::cout << count << " devices found." << std::endl;
for (int d=0;d<count;d++) {
err = cudaSetDevice(d);
if (err != cudaSuccess) {
std::cout << "error setting device, #=" << cudaGetErrorString(err) << std::endl;
}
cudaDeviceProp deviceProp;
err = cudaGetDeviceProperties(&deviceProp, d);
if (err != cudaSuccess) {
std::cout << "error getting device properties, #=" << cudaGetErrorString(err) << std::endl;
}
std::cout << "Using device " << d << ", name: " << deviceProp.name << std::endl;
for (int s = 0 ; s < 10 ; s++) {
cudaStream_t stream;
err = cudaStreamCreate(&stream);
if (err != cudaSuccess) {
std::cout << "error in stream creation, #=" << cudaGetErrorString(err) << std::endl;
}
iteration(stream);
cudaStreamDestroy(stream);
}
}
} | #include <hip/hip_runtime.h>
#include <string.h>
#include <stdio.h>
#include <iostream>
struct DataElement
{
char *name;
int value;
};
__global__
void Kernel(DataElement *elem) {
printf("On device: name=%s, value=%d\n", elem->name, elem->value);
elem->name[0] = 'd';
elem->value++;
}
void launch(DataElement *elem, hipStream_t &stream) {
Kernel<<< 1, 1, 0, stream >>>(elem);
//cudaDeviceSynchronize();
}
void iteration(hipStream_t &stream)
{
DataElement *e;
hipMallocManaged((void**)&e, sizeof(DataElement));
e->value = 10;
hipMallocManaged((void**)&(e->name), sizeof(char) * (strlen("hello") + 1) );
strcpy(e->name, "hello");
launch(e, stream);
printf("On host: name=%s, value=%d\n", e->name, e->value);
hipFree(e->name);
hipFree(e);
}
int main(void)
{
hipError_t err;
int count = 0;
err = hipGetDeviceCount(&count);
std::cout << count << " devices found." << std::endl;
for (int d=0;d<count;d++) {
err = hipSetDevice(d);
if (err != hipSuccess) {
std::cout << "error setting device, #=" << hipGetErrorString(err) << std::endl;
}
hipDeviceProp_t deviceProp;
err = hipGetDeviceProperties(&deviceProp, d);
if (err != hipSuccess) {
std::cout << "error getting device properties, #=" << hipGetErrorString(err) << std::endl;
}
std::cout << "Using device " << d << ", name: " << deviceProp.name << std::endl;
for (int s = 0 ; s < 10 ; s++) {
hipStream_t stream;
err = hipStreamCreate(&stream);
if (err != hipSuccess) {
std::cout << "error in stream creation, #=" << hipGetErrorString(err) << std::endl;
}
iteration(stream);
hipStreamDestroy(stream);
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <string.h>
#include <stdio.h>
#include <iostream>
struct DataElement
{
char *name;
int value;
};
__global__
void Kernel(DataElement *elem) {
printf("On device: name=%s, value=%d\n", elem->name, elem->value);
elem->name[0] = 'd';
elem->value++;
}
void launch(DataElement *elem, hipStream_t &stream) {
Kernel<<< 1, 1, 0, stream >>>(elem);
//cudaDeviceSynchronize();
}
void iteration(hipStream_t &stream)
{
DataElement *e;
hipMallocManaged((void**)&e, sizeof(DataElement));
e->value = 10;
hipMallocManaged((void**)&(e->name), sizeof(char) * (strlen("hello") + 1) );
strcpy(e->name, "hello");
launch(e, stream);
printf("On host: name=%s, value=%d\n", e->name, e->value);
hipFree(e->name);
hipFree(e);
}
int main(void)
{
hipError_t err;
int count = 0;
err = hipGetDeviceCount(&count);
std::cout << count << " devices found." << std::endl;
for (int d=0;d<count;d++) {
err = hipSetDevice(d);
if (err != hipSuccess) {
std::cout << "error setting device, #=" << hipGetErrorString(err) << std::endl;
}
hipDeviceProp_t deviceProp;
err = hipGetDeviceProperties(&deviceProp, d);
if (err != hipSuccess) {
std::cout << "error getting device properties, #=" << hipGetErrorString(err) << std::endl;
}
std::cout << "Using device " << d << ", name: " << deviceProp.name << std::endl;
for (int s = 0 ; s < 10 ; s++) {
hipStream_t stream;
err = hipStreamCreate(&stream);
if (err != hipSuccess) {
std::cout << "error in stream creation, #=" << hipGetErrorString(err) << std::endl;
}
iteration(stream);
hipStreamDestroy(stream);
}
}
} | .text
.file "dataElem_um.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__KernelP11DataElement # -- Begin function _Z21__device_stub__KernelP11DataElement
.p2align 4, 0x90
.type _Z21__device_stub__KernelP11DataElement,@function
_Z21__device_stub__KernelP11DataElement: # @_Z21__device_stub__KernelP11DataElement
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z6KernelP11DataElement, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z21__device_stub__KernelP11DataElement, .Lfunc_end0-_Z21__device_stub__KernelP11DataElement
.cfi_endproc
# -- End function
.globl _Z6launchP11DataElementRP12ihipStream_t # -- Begin function _Z6launchP11DataElementRP12ihipStream_t
.p2align 4, 0x90
.type _Z6launchP11DataElementRP12ihipStream_t,@function
_Z6launchP11DataElementRP12ihipStream_t: # @_Z6launchP11DataElementRP12ihipStream_t
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $64, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq (%rsi), %r9
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %rbx, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, (%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movq %rsp, %r9
movl $_Z6KernelP11DataElement, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $64, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z6launchP11DataElementRP12ihipStream_t, .Lfunc_end1-_Z6launchP11DataElementRP12ihipStream_t
.cfi_endproc
# -- End function
.globl _Z9iterationRP12ihipStream_t # -- Begin function _Z9iterationRP12ihipStream_t
.p2align 4, 0x90
.type _Z9iterationRP12ihipStream_t,@function
_Z9iterationRP12ihipStream_t: # @_Z9iterationRP12ihipStream_t
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $16, %rsp
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -16
movq %rdi, %rbx
leaq 8(%rsp), %rdi
movl $16, %esi
movl $1, %edx
callq hipMallocManaged
movq 8(%rsp), %rdi
movl $10, 8(%rdi)
movl $6, %esi
movl $1, %edx
callq hipMallocManaged
movq 8(%rsp), %rax
movq (%rax), %rax
movw $111, 4(%rax)
movl $1819043176, (%rax) # imm = 0x6C6C6568
movq 8(%rsp), %rdi
movq %rbx, %rsi
callq _Z6launchP11DataElementRP12ihipStream_t
movq 8(%rsp), %rax
movq (%rax), %rsi
movl 8(%rax), %edx
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rax
movq (%rax), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z9iterationRP12ihipStream_t, .Lfunc_end2-_Z9iterationRP12ihipStream_t
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1576, %rsp # imm = 0x628
.cfi_def_cfa_offset 1632
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $0, 8(%rsp)
leaq 8(%rsp), %rdi
callq hipGetDeviceCount
movl 8(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.2, %esi
movl $15, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB3_43
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB3_3
# %bb.2:
movzbl 67(%r14), %eax
jmp .LBB3_4
.LBB3_3:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
cmpl $0, 8(%rsp)
jle .LBB3_33
# %bb.5: # %.lr.ph
movabsq $4294967297, %rbx # imm = 0x100000001
leaq 104(%rsp), %r14
leaq 24(%rsp), %r15
leaq 16(%rsp), %r12
xorl %r13d, %r13d
jmp .LBB3_6
.p2align 4, 0x90
.LBB3_32: # in Loop: Header=BB3_6 Depth=1
movl 12(%rsp), %r13d # 4-byte Reload
incl %r13d
cmpl 8(%rsp), %r13d
leaq 104(%rsp), %r14
jge .LBB3_33
.LBB3_6: # =>This Loop Header: Depth=1
# Child Loop BB3_29 Depth 2
movl %r13d, %edi
callq hipSetDevice
testl %eax, %eax
movl %r13d, 12(%rsp) # 4-byte Spill
je .LBB3_15
# %bb.7: # in Loop: Header=BB3_6 Depth=1
movl %eax, %ebp
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $24, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebp, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB3_8
# %bb.9: # in Loop: Header=BB3_6 Depth=1
movq %rax, %rdi
movq %rax, %r13
callq strlen
movl $_ZSt4cout, %edi
movq %r13, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB3_10
.p2align 4, 0x90
.LBB3_8: # in Loop: Header=BB3_6 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB3_10: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
# in Loop: Header=BB3_6 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r13
testq %r13, %r13
je .LBB3_43
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i26
# in Loop: Header=BB3_6 Depth=1
cmpb $0, 56(%r13)
je .LBB3_13
# %bb.12: # in Loop: Header=BB3_6 Depth=1
movzbl 67(%r13), %eax
jmp .LBB3_14
.p2align 4, 0x90
.LBB3_13: # in Loop: Header=BB3_6 Depth=1
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit29
# in Loop: Header=BB3_6 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl 12(%rsp), %r13d # 4-byte Reload
.LBB3_15: # in Loop: Header=BB3_6 Depth=1
movq %r14, %rdi
movl %r13d, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
je .LBB3_24
# %bb.16: # in Loop: Header=BB3_6 Depth=1
movl %eax, %ebp
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $35, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebp, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB3_17
# %bb.18: # in Loop: Header=BB3_6 Depth=1
movq %rax, %rdi
movq %rax, %r13
callq strlen
movl $_ZSt4cout, %edi
movq %r13, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB3_19
.p2align 4, 0x90
.LBB3_17: # in Loop: Header=BB3_6 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB3_19: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit21
# in Loop: Header=BB3_6 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r13
testq %r13, %r13
je .LBB3_43
# %bb.20: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i31
# in Loop: Header=BB3_6 Depth=1
cmpb $0, 56(%r13)
je .LBB3_22
# %bb.21: # in Loop: Header=BB3_6 Depth=1
movzbl 67(%r13), %eax
jmp .LBB3_23
.p2align 4, 0x90
.LBB3_22: # in Loop: Header=BB3_6 Depth=1
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_23: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit34
# in Loop: Header=BB3_6 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl 12(%rsp), %r13d # 4-byte Reload
.LBB3_24: # in Loop: Header=BB3_6 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r13d, %esi
callq _ZNSolsEi
movq %rax, %r13
movl $.L.str.6, %esi
movl $8, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r14, %rdi
callq strlen
movq %r13, %rdi
movq %r14, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r13), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %rbp
testq %rbp, %rbp
je .LBB3_43
# %bb.25: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i36
# in Loop: Header=BB3_6 Depth=1
cmpb $0, 56(%rbp)
je .LBB3_27
# %bb.26: # in Loop: Header=BB3_6 Depth=1
movzbl 67(%rbp), %eax
jmp .LBB3_28
.p2align 4, 0x90
.LBB3_27: # in Loop: Header=BB3_6 Depth=1
movq %rbp, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_28: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit39
# in Loop: Header=BB3_6 Depth=1
movsbl %al, %esi
movq %r13, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $10, %r14d
jmp .LBB3_29
.p2align 4, 0x90
.LBB3_42: # %_Z6launchP11DataElementRP12ihipStream_t.exit
# in Loop: Header=BB3_29 Depth=2
movq 16(%rsp), %rax
movq (%rax), %rsi
movl 8(%rax), %edx
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rax
movq (%rax), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipStreamDestroy
decl %r14d
je .LBB3_32
.LBB3_29: # Parent Loop BB3_6 Depth=1
# => This Inner Loop Header: Depth=2
movq %r15, %rdi
callq hipStreamCreate
testl %eax, %eax
je .LBB3_40
# %bb.30: # in Loop: Header=BB3_29 Depth=2
movl %eax, %ebp
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $28, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebp, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB3_31
# %bb.34: # in Loop: Header=BB3_29 Depth=2
movq %rax, %rdi
movq %rax, %r13
callq strlen
movl $_ZSt4cout, %edi
movq %r13, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB3_35
.p2align 4, 0x90
.LBB3_31: # in Loop: Header=BB3_29 Depth=2
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB3_35: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit24
# in Loop: Header=BB3_29 Depth=2
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r13
testq %r13, %r13
je .LBB3_43
# %bb.36: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i41
# in Loop: Header=BB3_29 Depth=2
cmpb $0, 56(%r13)
je .LBB3_38
# %bb.37: # in Loop: Header=BB3_29 Depth=2
movzbl 67(%r13), %eax
jmp .LBB3_39
.p2align 4, 0x90
.LBB3_38: # in Loop: Header=BB3_29 Depth=2
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_39: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit44
# in Loop: Header=BB3_29 Depth=2
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB3_40: # in Loop: Header=BB3_29 Depth=2
movl $16, %esi
movq %r12, %rdi
movl $1, %edx
callq hipMallocManaged
movq 16(%rsp), %rdi
movl $10, 8(%rdi)
movl $6, %esi
movl $1, %edx
callq hipMallocManaged
movq 16(%rsp), %rax
movq (%rax), %rax
movw $111, 4(%rax)
movl $1819043176, (%rax) # imm = 0x6C6C6568
movq 16(%rsp), %r13
movq 24(%rsp), %r9
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_42
# %bb.41: # in Loop: Header=BB3_29 Depth=2
movq %r13, 96(%rsp)
leaq 96(%rsp), %rax
movq %rax, 32(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z6KernelP11DataElement, %edi
leaq 32(%rsp), %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_42
.LBB3_33: # %._crit_edge
xorl %eax, %eax
addq $1576, %rsp # imm = 0x628
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_43:
.cfi_def_cfa_offset 1632
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6KernelP11DataElement, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6KernelP11DataElement,@object # @_Z6KernelP11DataElement
.section .rodata,"a",@progbits
.globl _Z6KernelP11DataElement
.p2align 3, 0x0
_Z6KernelP11DataElement:
.quad _Z21__device_stub__KernelP11DataElement
.size _Z6KernelP11DataElement, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "hello"
.size .L.str, 6
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "On host: name=%s, value=%d\n"
.size .L.str.1, 28
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " devices found."
.size .L.str.2, 16
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "error setting device, #="
.size .L.str.3, 25
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "error getting device properties, #="
.size .L.str.4, 36
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Using device "
.size .L.str.5, 14
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz ", name: "
.size .L.str.6, 9
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "error in stream creation, #="
.size .L.str.7, 29
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6KernelP11DataElement"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__KernelP11DataElement
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6KernelP11DataElement
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016eee6_00000000-6_dataElem_um.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z6KernelP11DataElementP11DataElement
.type _Z37__device_stub__Z6KernelP11DataElementP11DataElement, @function
_Z37__device_stub__Z6KernelP11DataElementP11DataElement:
.LFB3696:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6KernelP11DataElement(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z37__device_stub__Z6KernelP11DataElementP11DataElement, .-_Z37__device_stub__Z6KernelP11DataElementP11DataElement
.globl _Z6KernelP11DataElement
.type _Z6KernelP11DataElement, @function
_Z6KernelP11DataElement:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z6KernelP11DataElementP11DataElement
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z6KernelP11DataElement, .-_Z6KernelP11DataElement
.globl _Z6launchP11DataElementRP11CUstream_st
.type _Z6launchP11DataElementRP11CUstream_st, @function
_Z6launchP11DataElementRP11CUstream_st:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $32, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movq (%rsi), %r9
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movq %rbx, %rdi
call _Z37__device_stub__Z6KernelP11DataElementP11DataElement
jmp .L11
.cfi_endproc
.LFE3669:
.size _Z6launchP11DataElementRP11CUstream_st, .-_Z6launchP11DataElementRP11CUstream_st
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "On host: name=%s, value=%d\n"
.text
.globl _Z9iterationRP11CUstream_st
.type _Z9iterationRP11CUstream_st, @function
_Z9iterationRP11CUstream_st:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $1, %edx
movl $16, %esi
call cudaMallocManaged@PLT
movq (%rsp), %rdi
movl $10, 8(%rdi)
movl $1, %edx
movl $6, %esi
call cudaMallocManaged@PLT
movq (%rsp), %rax
movq (%rax), %rax
movl $1819043176, (%rax)
movw $111, 4(%rax)
movq %rbx, %rsi
movq (%rsp), %rdi
call _Z6launchP11DataElementRP11CUstream_st
movq (%rsp), %rax
movl 8(%rax), %ecx
movq (%rax), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rax
movq (%rax), %rdi
call cudaFree@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size _Z9iterationRP11CUstream_st, .-_Z9iterationRP11CUstream_st
.section .rodata.str1.1
.LC1:
.string " devices found."
.LC2:
.string "error setting device, #="
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "error getting device properties, #="
.section .rodata.str1.1
.LC4:
.string "Using device "
.LC5:
.string ", name: "
.LC6:
.string "error in stream creation, #="
.text
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1064, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
movl $0, 4(%rsp)
leaq 4(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 4(%rsp), %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
cmpl $0, 4(%rsp)
jle .L20
movl $0, %r14d
leaq _ZSt4cout(%rip), %r12
leaq .LC6(%rip), %r15
jmp .L47
.L64:
movl $24, %edx
leaq .LC2(%rip), %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rbx
testq %rax, %rax
je .L52
movq %rax, %rdi
call strlen@PLT
movq %rax, %rdx
movq %rbx, %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L23:
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %rbx
testq %rbx, %rbx
je .L53
cmpb $0, 56(%rbx)
je .L26
movzbl 67(%rbx), %esi
.L27:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L21
.L52:
leaq _ZSt4cout(%rip), %rdi
movq _ZSt4cout(%rip), %rax
addq -24(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L23
.L53:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L54
call _ZSt16__throw_bad_castv@PLT
.L54:
call __stack_chk_fail@PLT
.L26:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L27
.L65:
movl $35, %edx
leaq .LC3(%rip), %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rbx
testq %rax, %rax
je .L55
movq %rax, %rdi
call strlen@PLT
movq %rax, %rdx
movq %rbx, %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L30:
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %rbx
testq %rbx, %rbx
je .L56
cmpb $0, 56(%rbx)
je .L33
movzbl 67(%rbx), %esi
.L34:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L28
.L55:
leaq _ZSt4cout(%rip), %rdi
movq _ZSt4cout(%rip), %rax
addq -24(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L30
.L56:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L57
call _ZSt16__throw_bad_castv@PLT
.L57:
call __stack_chk_fail@PLT
.L33:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L34
.L66:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L58
call _ZSt16__throw_bad_castv@PLT
.L58:
call __stack_chk_fail@PLT
.L37:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L38
.L61:
movq (%r12), %rax
movq %r12, %rdi
addq -24(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L41
.L62:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L59
call _ZSt16__throw_bad_castv@PLT
.L59:
call __stack_chk_fail@PLT
.L63:
movzbl 67(%rbx), %esi
.L45:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.L39:
movq %r13, %rdi
call _Z9iterationRP11CUstream_st
movq 8(%rsp), %rdi
call cudaStreamDestroy@PLT
subl $1, %ebp
je .L60
.L46:
movq %r13, %rdi
call cudaStreamCreate@PLT
movl %eax, %ebx
testl %eax, %eax
je .L39
movl $28, %edx
movq %r15, %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rbx
testq %rax, %rax
je .L61
movq %rax, %rdi
call strlen@PLT
movq %rax, %rdx
movq %rbx, %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L41:
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %rbx
testq %rbx, %rbx
je .L62
cmpb $0, 56(%rbx)
jne .L63
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L45
.L60:
addl $1, %r14d
cmpl %r14d, 4(%rsp)
jle .L20
.L47:
movl %r14d, %edi
call cudaSetDevice@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L64
.L21:
leaq 16(%rsp), %rdi
movl %r14d, %esi
call cudaGetDeviceProperties_v2@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L65
.L28:
movl $13, %edx
leaq .LC4(%rip), %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r14d, %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $8, %edx
leaq .LC5(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
leaq 16(%rsp), %rbp
movq %rbp, %rdi
call strlen@PLT
movq %rax, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L66
cmpb $0, 56(%rbp)
je .L37
movzbl 67(%rbp), %esi
.L38:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $10, %ebp
leaq 8(%rsp), %r13
jmp .L46
.L20:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L67
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L67:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z6KernelP11DataElement"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z6KernelP11DataElement(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "dataElem_um.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__KernelP11DataElement # -- Begin function _Z21__device_stub__KernelP11DataElement
.p2align 4, 0x90
.type _Z21__device_stub__KernelP11DataElement,@function
_Z21__device_stub__KernelP11DataElement: # @_Z21__device_stub__KernelP11DataElement
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z6KernelP11DataElement, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z21__device_stub__KernelP11DataElement, .Lfunc_end0-_Z21__device_stub__KernelP11DataElement
.cfi_endproc
# -- End function
.globl _Z6launchP11DataElementRP12ihipStream_t # -- Begin function _Z6launchP11DataElementRP12ihipStream_t
.p2align 4, 0x90
.type _Z6launchP11DataElementRP12ihipStream_t,@function
_Z6launchP11DataElementRP12ihipStream_t: # @_Z6launchP11DataElementRP12ihipStream_t
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $64, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq (%rsi), %r9
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %rbx, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, (%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movq %rsp, %r9
movl $_Z6KernelP11DataElement, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $64, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z6launchP11DataElementRP12ihipStream_t, .Lfunc_end1-_Z6launchP11DataElementRP12ihipStream_t
.cfi_endproc
# -- End function
.globl _Z9iterationRP12ihipStream_t # -- Begin function _Z9iterationRP12ihipStream_t
.p2align 4, 0x90
.type _Z9iterationRP12ihipStream_t,@function
_Z9iterationRP12ihipStream_t: # @_Z9iterationRP12ihipStream_t
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $16, %rsp
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -16
movq %rdi, %rbx
leaq 8(%rsp), %rdi
movl $16, %esi
movl $1, %edx
callq hipMallocManaged
movq 8(%rsp), %rdi
movl $10, 8(%rdi)
movl $6, %esi
movl $1, %edx
callq hipMallocManaged
movq 8(%rsp), %rax
movq (%rax), %rax
movw $111, 4(%rax)
movl $1819043176, (%rax) # imm = 0x6C6C6568
movq 8(%rsp), %rdi
movq %rbx, %rsi
callq _Z6launchP11DataElementRP12ihipStream_t
movq 8(%rsp), %rax
movq (%rax), %rsi
movl 8(%rax), %edx
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rax
movq (%rax), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z9iterationRP12ihipStream_t, .Lfunc_end2-_Z9iterationRP12ihipStream_t
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1576, %rsp # imm = 0x628
.cfi_def_cfa_offset 1632
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $0, 8(%rsp)
leaq 8(%rsp), %rdi
callq hipGetDeviceCount
movl 8(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.2, %esi
movl $15, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB3_43
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB3_3
# %bb.2:
movzbl 67(%r14), %eax
jmp .LBB3_4
.LBB3_3:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
cmpl $0, 8(%rsp)
jle .LBB3_33
# %bb.5: # %.lr.ph
movabsq $4294967297, %rbx # imm = 0x100000001
leaq 104(%rsp), %r14
leaq 24(%rsp), %r15
leaq 16(%rsp), %r12
xorl %r13d, %r13d
jmp .LBB3_6
.p2align 4, 0x90
.LBB3_32: # in Loop: Header=BB3_6 Depth=1
movl 12(%rsp), %r13d # 4-byte Reload
incl %r13d
cmpl 8(%rsp), %r13d
leaq 104(%rsp), %r14
jge .LBB3_33
.LBB3_6: # =>This Loop Header: Depth=1
# Child Loop BB3_29 Depth 2
movl %r13d, %edi
callq hipSetDevice
testl %eax, %eax
movl %r13d, 12(%rsp) # 4-byte Spill
je .LBB3_15
# %bb.7: # in Loop: Header=BB3_6 Depth=1
movl %eax, %ebp
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $24, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebp, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB3_8
# %bb.9: # in Loop: Header=BB3_6 Depth=1
movq %rax, %rdi
movq %rax, %r13
callq strlen
movl $_ZSt4cout, %edi
movq %r13, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB3_10
.p2align 4, 0x90
.LBB3_8: # in Loop: Header=BB3_6 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB3_10: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
# in Loop: Header=BB3_6 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r13
testq %r13, %r13
je .LBB3_43
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i26
# in Loop: Header=BB3_6 Depth=1
cmpb $0, 56(%r13)
je .LBB3_13
# %bb.12: # in Loop: Header=BB3_6 Depth=1
movzbl 67(%r13), %eax
jmp .LBB3_14
.p2align 4, 0x90
.LBB3_13: # in Loop: Header=BB3_6 Depth=1
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit29
# in Loop: Header=BB3_6 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl 12(%rsp), %r13d # 4-byte Reload
.LBB3_15: # in Loop: Header=BB3_6 Depth=1
movq %r14, %rdi
movl %r13d, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
je .LBB3_24
# %bb.16: # in Loop: Header=BB3_6 Depth=1
movl %eax, %ebp
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $35, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebp, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB3_17
# %bb.18: # in Loop: Header=BB3_6 Depth=1
movq %rax, %rdi
movq %rax, %r13
callq strlen
movl $_ZSt4cout, %edi
movq %r13, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB3_19
.p2align 4, 0x90
.LBB3_17: # in Loop: Header=BB3_6 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB3_19: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit21
# in Loop: Header=BB3_6 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r13
testq %r13, %r13
je .LBB3_43
# %bb.20: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i31
# in Loop: Header=BB3_6 Depth=1
cmpb $0, 56(%r13)
je .LBB3_22
# %bb.21: # in Loop: Header=BB3_6 Depth=1
movzbl 67(%r13), %eax
jmp .LBB3_23
.p2align 4, 0x90
.LBB3_22: # in Loop: Header=BB3_6 Depth=1
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_23: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit34
# in Loop: Header=BB3_6 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl 12(%rsp), %r13d # 4-byte Reload
.LBB3_24: # in Loop: Header=BB3_6 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r13d, %esi
callq _ZNSolsEi
movq %rax, %r13
movl $.L.str.6, %esi
movl $8, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r14, %rdi
callq strlen
movq %r13, %rdi
movq %r14, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r13), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %rbp
testq %rbp, %rbp
je .LBB3_43
# %bb.25: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i36
# in Loop: Header=BB3_6 Depth=1
cmpb $0, 56(%rbp)
je .LBB3_27
# %bb.26: # in Loop: Header=BB3_6 Depth=1
movzbl 67(%rbp), %eax
jmp .LBB3_28
.p2align 4, 0x90
.LBB3_27: # in Loop: Header=BB3_6 Depth=1
movq %rbp, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_28: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit39
# in Loop: Header=BB3_6 Depth=1
movsbl %al, %esi
movq %r13, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $10, %r14d
jmp .LBB3_29
.p2align 4, 0x90
.LBB3_42: # %_Z6launchP11DataElementRP12ihipStream_t.exit
# in Loop: Header=BB3_29 Depth=2
movq 16(%rsp), %rax
movq (%rax), %rsi
movl 8(%rax), %edx
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rax
movq (%rax), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipStreamDestroy
decl %r14d
je .LBB3_32
.LBB3_29: # Parent Loop BB3_6 Depth=1
# => This Inner Loop Header: Depth=2
movq %r15, %rdi
callq hipStreamCreate
testl %eax, %eax
je .LBB3_40
# %bb.30: # in Loop: Header=BB3_29 Depth=2
movl %eax, %ebp
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $28, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebp, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB3_31
# %bb.34: # in Loop: Header=BB3_29 Depth=2
movq %rax, %rdi
movq %rax, %r13
callq strlen
movl $_ZSt4cout, %edi
movq %r13, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB3_35
.p2align 4, 0x90
.LBB3_31: # in Loop: Header=BB3_29 Depth=2
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB3_35: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit24
# in Loop: Header=BB3_29 Depth=2
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r13
testq %r13, %r13
je .LBB3_43
# %bb.36: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i41
# in Loop: Header=BB3_29 Depth=2
cmpb $0, 56(%r13)
je .LBB3_38
# %bb.37: # in Loop: Header=BB3_29 Depth=2
movzbl 67(%r13), %eax
jmp .LBB3_39
.p2align 4, 0x90
.LBB3_38: # in Loop: Header=BB3_29 Depth=2
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_39: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit44
# in Loop: Header=BB3_29 Depth=2
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB3_40: # in Loop: Header=BB3_29 Depth=2
movl $16, %esi
movq %r12, %rdi
movl $1, %edx
callq hipMallocManaged
movq 16(%rsp), %rdi
movl $10, 8(%rdi)
movl $6, %esi
movl $1, %edx
callq hipMallocManaged
movq 16(%rsp), %rax
movq (%rax), %rax
movw $111, 4(%rax)
movl $1819043176, (%rax) # imm = 0x6C6C6568
movq 16(%rsp), %r13
movq 24(%rsp), %r9
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_42
# %bb.41: # in Loop: Header=BB3_29 Depth=2
movq %r13, 96(%rsp)
leaq 96(%rsp), %rax
movq %rax, 32(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z6KernelP11DataElement, %edi
leaq 32(%rsp), %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_42
.LBB3_33: # %._crit_edge
xorl %eax, %eax
addq $1576, %rsp # imm = 0x628
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_43:
.cfi_def_cfa_offset 1632
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6KernelP11DataElement, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6KernelP11DataElement,@object # @_Z6KernelP11DataElement
.section .rodata,"a",@progbits
.globl _Z6KernelP11DataElement
.p2align 3, 0x0
_Z6KernelP11DataElement:
.quad _Z21__device_stub__KernelP11DataElement
.size _Z6KernelP11DataElement, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "hello"
.size .L.str, 6
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "On host: name=%s, value=%d\n"
.size .L.str.1, 28
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " devices found."
.size .L.str.2, 16
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "error setting device, #="
.size .L.str.3, 25
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "error getting device properties, #="
.size .L.str.4, 36
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Using device "
.size .L.str.5, 14
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz ", name: "
.size .L.str.6, 9
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "error in stream creation, #="
.size .L.str.7, 29
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6KernelP11DataElement"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__KernelP11DataElement
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6KernelP11DataElement
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <time.h>
#include <unistd.h>
#include <cuda_runtime.h>
// #define PRINT // use with ROW_ELEMENTS < 50
// Cells definitions
#define ALIVE 35 // #
#define DEAD 32 // (space)
#define BORDER 66 // B
// Kernel definition
#define THREADS_PER_BLOCK 256
#define BLOCKS_PER_GRID 1
// Universe definition
#define STEPS 10
#define ROW_ELEMENTS 1000 // 3000 1x1 = 42s
#define ROW_WITH_BORDER_ELEMENTS (ROW_ELEMENTS + 2)
__device__ int getNeighboursCount(const char *universe, int i) {
int count = 0;
int startIndex = i - ROW_WITH_BORDER_ELEMENTS - 1;
for (int j = 0; j < 3; j++) {
for (int k = 0; k < 3; k++) {
int currentIndex = startIndex + k;
if (currentIndex != i && // not itself
universe[currentIndex] == ALIVE) {
count++;
}
}
startIndex += ROW_WITH_BORDER_ELEMENTS;
}
return count;
}
__global__ void computeConwayUniverse(const char *in_universe, char *out_universe, long long int numElements) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
for (; i < numElements; i += blockDim.x * gridDim.x) {
if (in_universe[i] == BORDER) {
out_universe[i] = BORDER;
} else {
int neighboursCount = getNeighboursCount(in_universe, i);
out_universe[i] =
neighboursCount == 3 ? ALIVE : neighboursCount == 2 && in_universe[i] == ALIVE ? ALIVE : DEAD;
}
}
}
void checkError(cudaError_t err, const char *format) {
if (err != cudaSuccess) {
fprintf(stderr, format, cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
}
int main(void) {
srand(time(NULL));
clock_t start, end;
cudaError_t err = cudaSuccess;
long long int numElements = (long long int) ROW_WITH_BORDER_ELEMENTS * (long long int) ROW_WITH_BORDER_ELEMENTS;
size_t universe_size = numElements * sizeof(char);
printf("[Universe of size %d x %d (%d blocks with %d threads, %d steps)]\n", ROW_ELEMENTS, ROW_ELEMENTS, BLOCKS_PER_GRID, THREADS_PER_BLOCK, STEPS);
char *h_universe = (char *) malloc(universe_size);
if (h_universe == NULL) {
fprintf(stderr, "Failed to allocate host h_universe!\n");
exit(EXIT_FAILURE);
}
// Initialize universe
for (int i = 0; i < numElements; ++i) {
if (i < ROW_WITH_BORDER_ELEMENTS || // first row
i >= numElements - ROW_WITH_BORDER_ELEMENTS || // last row
i % ROW_WITH_BORDER_ELEMENTS == 0 || // first column
i != 0 && i % ROW_WITH_BORDER_ELEMENTS == ROW_WITH_BORDER_ELEMENTS - 1) { // last column
h_universe[i] = BORDER;
} else {
h_universe[i] = rand() % 2 == 0 ? DEAD : ALIVE;
}
}
char *d_in_universe = NULL;
err = cudaMalloc((void **) &d_in_universe, universe_size);
checkError(err, "Failed to allocate device universe (error code %s)!\n");
char *d_out_universe = NULL;
err = cudaMalloc((void **) &d_out_universe, universe_size);
checkError(err, "Failed to allocate device universe (error code %s)!\n");
start = clock();
for (int i = 0; i < STEPS; i++) {
err = cudaMemcpy(d_in_universe, h_universe, universe_size, cudaMemcpyHostToDevice);
checkError(err, "Failed to copy universe from host to device (error code %s)!\n");
computeConwayUniverse<<<BLOCKS_PER_GRID, THREADS_PER_BLOCK>>>(d_in_universe, d_out_universe, numElements);
err = cudaGetLastError();
checkError(err, "Failed to launch Conway kernel (error code %s)!\n");
err = cudaMemcpy(h_universe, d_out_universe, universe_size, cudaMemcpyDeviceToHost);
checkError(err, "Failed to copy universe from device to host (error code %s)!\n");
#ifdef PRINT
printf("\e[0;1H\e[2J");
printf("Step (%d) CUDA Conway kernel launch with %d blocks of %d threads\n", i, BLOCKS_PER_GRID, THREADS_PER_BLOCK);
for (int i=0; i < numElements; ++i) {
if (i % ROW_WITH_BORDER_ELEMENTS == 0){
printf("\n");
}
printf("%c ", h_universe[i]);
}
printf("\n");
sleep(1);
#endif
}
end = clock();
printf("Computations took %f s\n", ((double) (end - start) / CLOCKS_PER_SEC));
err = cudaFree(d_in_universe);
checkError(err, "Failed to free device in universe (error code %s)!\n");
err = cudaFree(d_out_universe);
checkError(err, "Failed to free device out universe (error code %s)!\n");
free(h_universe);
err = cudaDeviceReset();
checkError(err, "Failed to deinitialize the device! error=%s\n");
return 0;
} | code for sm_80
Function : _Z21computeConwayUniversePKcPcx
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */
/* 0x000fc80000011400 */
/*0060*/ ISETP.GE.AND.EX P0, PT, R2, c[0x0][0x174], PT, P0 ; /* 0x00005d0002007a0c */
/* 0x000fda0003f06300 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R8, RZ, RZ, R2 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0002 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fca00078e0000 */
/*00b0*/ IADD3 R4, P0, R7, c[0x0][0x160], RZ ; /* 0x0000580007047a10 */
/* 0x000fc80007f1e0ff */
/*00c0*/ IADD3.X R5, R8, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590008057a10 */
/* 0x000fca00007fe4ff */
/*00d0*/ LDG.E.U8 R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ea2000c1e1100 */
/*00e0*/ IADD3 R2, P1, R7, c[0x0][0x168], RZ ; /* 0x00005a0007027a10 */
/* 0x000fe20007f3e0ff */
/*00f0*/ BSSY B0, 0x3b0 ; /* 0x000002b000007945 */
/* 0x000fe20003800000 */
/*0100*/ IMAD.MOV.U32 R6, RZ, RZ, 0x42 ; /* 0x00000042ff067424 */
/* 0x000fe400078e00ff */
/*0110*/ IADD3.X R3, R8, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0008037a10 */
/* 0x000fe20000ffe4ff */
/*0120*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0f7624 */
/* 0x000fe200078e00ff */
/*0130*/ ISETP.NE.AND P0, PT, R14, 0x42, PT ; /* 0x000000420e00780c */
/* 0x004fda0003f05270 */
/*0140*/ @!P0 BRA 0x3a0 ; /* 0x0000025000008947 */
/* 0x000fea0003800000 */
/*0150*/ LDG.E.U8 R7, [R4.64+-0x3ea] ; /* 0xfffc160404077981 */
/* 0x000ea8000c1e1100 */
/*0160*/ LDG.E.U8 R6, [R4.64+-0x3eb] ; /* 0xfffc150404067981 */
/* 0x000ee8000c1e1100 */
/*0170*/ LDG.E.U8 R8, [R4.64+-0x3e9] ; /* 0xfffc170404087981 */
/* 0x000f28000c1e1100 */
/*0180*/ LDG.E.U8 R9, [R4.64+-0x1] ; /* 0xffffff0404097981 */
/* 0x000f68000c1e1100 */
/*0190*/ LDG.E.U8 R10, [R4.64+0x1] ; /* 0x00000104040a7981 */
/* 0x000f68000c1e1100 */
/*01a0*/ LDG.E.U8 R11, [R4.64+0x3e9] ; /* 0x0003e904040b7981 */
/* 0x000168000c1e1100 */
/*01b0*/ LDG.E.U8 R12, [R4.64+0x3ea] ; /* 0x0003ea04040c7981 */
/* 0x000168000c1e1100 */
/*01c0*/ LDG.E.U8 R13, [R4.64+0x3eb] ; /* 0x0003eb04040d7981 */
/* 0x000162000c1e1100 */
/*01d0*/ ISETP.NE.AND P2, PT, R7, 0x23, PT ; /* 0x000000230700780c */
/* 0x004fe20003f45270 */
/*01e0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x2 ; /* 0x00000002ff077424 */
/* 0x000fe200078e00ff */
/*01f0*/ ISETP.NE.AND P1, PT, R6, 0x23, PT ; /* 0x000000230600780c */
/* 0x008fc40003f25270 */
/*0200*/ SEL R6, RZ, 0x1, P2 ; /* 0x00000001ff067807 */
/* 0x000fe40001000000 */
/*0210*/ ISETP.NE.AND P0, PT, R8, 0x23, PT ; /* 0x000000230800780c */
/* 0x010fce0003f05270 */
/*0220*/ @P2 IMAD.MOV R7, RZ, RZ, 0x1 ; /* 0x00000001ff072424 */
/* 0x000fe400078e02ff */
/*0230*/ @P1 IMAD.MOV R7, RZ, RZ, R6 ; /* 0x000000ffff071224 */
/* 0x000fe200078e0206 */
/*0240*/ ISETP.NE.AND P1, PT, R9, 0x23, PT ; /* 0x000000230900780c */
/* 0x020fc80003f25270 */
/*0250*/ IADD3 R6, R7, 0x1, RZ ; /* 0x0000000107067810 */
/* 0x000fe20007ffe0ff */
/*0260*/ @P0 IMAD.MOV R6, RZ, RZ, R7 ; /* 0x000000ffff060224 */
/* 0x000fe200078e0207 */
/*0270*/ ISETP.NE.AND P0, PT, R10, 0x23, PT ; /* 0x000000230a00780c */
/* 0x000fc80003f05270 */
/*0280*/ IADD3 R4, R6, 0x1, RZ ; /* 0x0000000106047810 */
/* 0x001fc60007ffe0ff */
/*0290*/ @P1 IMAD.MOV R4, RZ, RZ, R6 ; /* 0x000000ffff041224 */
/* 0x000fe200078e0206 */
/*02a0*/ ISETP.NE.AND P1, PT, R11, 0x23, PT ; /* 0x000000230b00780c */
/* 0x000fe20003f25270 */
/*02b0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x23 ; /* 0x00000023ff067424 */
/* 0x000fc600078e00ff */
/*02c0*/ IADD3 R5, R4, 0x1, RZ ; /* 0x0000000104057810 */
/* 0x000fe20007ffe0ff */
/*02d0*/ @P0 IMAD.MOV R5, RZ, RZ, R4 ; /* 0x000000ffff050224 */
/* 0x000fe200078e0204 */
/*02e0*/ ISETP.NE.AND P0, PT, R12, 0x23, PT ; /* 0x000000230c00780c */
/* 0x000fc80003f05270 */
/*02f0*/ IADD3 R4, R5, 0x1, RZ ; /* 0x0000000105047810 */
/* 0x000fc60007ffe0ff */
/*0300*/ @P1 IMAD.MOV R4, RZ, RZ, R5 ; /* 0x000000ffff041224 */
/* 0x000fe200078e0205 */
/*0310*/ ISETP.NE.AND P1, PT, R13, 0x23, PT ; /* 0x000000230d00780c */
/* 0x000fc80003f25270 */
/*0320*/ IADD3 R5, R4, 0x1, RZ ; /* 0x0000000104057810 */
/* 0x000fe20007ffe0ff */
/*0330*/ @P0 IMAD.MOV R5, RZ, RZ, R4 ; /* 0x000000ffff050224 */
/* 0x000fe200078e0204 */
/*0340*/ ISETP.NE.AND P0, PT, R14, 0x23, PT ; /* 0x000000230e00780c */
/* 0x000fc80003f05270 */
/*0350*/ IADD3 R4, R5, 0x1, RZ ; /* 0x0000000105047810 */
/* 0x000fc60007ffe0ff */
/*0360*/ @P1 IMAD.MOV R4, RZ, RZ, R5 ; /* 0x000000ffff041224 */
/* 0x000fca00078e0205 */
/*0370*/ ISETP.EQ.AND P0, PT, R4, 0x2, !P0 ; /* 0x000000020400780c */
/* 0x000fc80004702270 */
/*0380*/ ISETP.EQ.OR P0, PT, R4, 0x3, P0 ; /* 0x000000030400780c */
/* 0x000fc80000702670 */
/*0390*/ SEL R6, R6, 0x20, P0 ; /* 0x0000002006067807 */
/* 0x000fc80000000000 */
/*03a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03b0*/ IMAD R7, R15, c[0x0][0xc], R0 ; /* 0x000003000f077a24 */
/* 0x000fe200078e0200 */
/*03c0*/ STG.E.U8 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x0001e6000c101104 */
/*03d0*/ IMAD.MOV.U32 R0, RZ, RZ, R7.reuse ; /* 0x000000ffff007224 */
/* 0x100fe200078e0007 */
/*03e0*/ ISETP.GE.U32.AND P0, PT, R7, c[0x0][0x170], PT ; /* 0x00005c0007007a0c */
/* 0x000fe40003f06070 */
/*03f0*/ SHF.R.S32.HI R8, RZ, 0x1f, R7 ; /* 0x0000001fff087819 */
/* 0x000fc80000011407 */
/*0400*/ ISETP.GE.AND.EX P0, PT, R8, c[0x0][0x174], PT, P0 ; /* 0x00005d0008007a0c */
/* 0x000fda0003f06300 */
/*0410*/ @!P0 BRA 0xb0 ; /* 0xfffffc9000008947 */
/* 0x001fea000383ffff */
/*0420*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0430*/ BRA 0x430; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <time.h>
#include <unistd.h>
#include <cuda_runtime.h>
// #define PRINT // use with ROW_ELEMENTS < 50
// Cells definitions
#define ALIVE 35 // #
#define DEAD 32 // (space)
#define BORDER 66 // B
// Kernel definition
#define THREADS_PER_BLOCK 256
#define BLOCKS_PER_GRID 1
// Universe definition
#define STEPS 10
#define ROW_ELEMENTS 1000 // 3000 1x1 = 42s
#define ROW_WITH_BORDER_ELEMENTS (ROW_ELEMENTS + 2)
__device__ int getNeighboursCount(const char *universe, int i) {
int count = 0;
int startIndex = i - ROW_WITH_BORDER_ELEMENTS - 1;
for (int j = 0; j < 3; j++) {
for (int k = 0; k < 3; k++) {
int currentIndex = startIndex + k;
if (currentIndex != i && // not itself
universe[currentIndex] == ALIVE) {
count++;
}
}
startIndex += ROW_WITH_BORDER_ELEMENTS;
}
return count;
}
__global__ void computeConwayUniverse(const char *in_universe, char *out_universe, long long int numElements) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
for (; i < numElements; i += blockDim.x * gridDim.x) {
if (in_universe[i] == BORDER) {
out_universe[i] = BORDER;
} else {
int neighboursCount = getNeighboursCount(in_universe, i);
out_universe[i] =
neighboursCount == 3 ? ALIVE : neighboursCount == 2 && in_universe[i] == ALIVE ? ALIVE : DEAD;
}
}
}
void checkError(cudaError_t err, const char *format) {
if (err != cudaSuccess) {
fprintf(stderr, format, cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
}
int main(void) {
srand(time(NULL));
clock_t start, end;
cudaError_t err = cudaSuccess;
long long int numElements = (long long int) ROW_WITH_BORDER_ELEMENTS * (long long int) ROW_WITH_BORDER_ELEMENTS;
size_t universe_size = numElements * sizeof(char);
printf("[Universe of size %d x %d (%d blocks with %d threads, %d steps)]\n", ROW_ELEMENTS, ROW_ELEMENTS, BLOCKS_PER_GRID, THREADS_PER_BLOCK, STEPS);
char *h_universe = (char *) malloc(universe_size);
if (h_universe == NULL) {
fprintf(stderr, "Failed to allocate host h_universe!\n");
exit(EXIT_FAILURE);
}
// Initialize universe
for (int i = 0; i < numElements; ++i) {
if (i < ROW_WITH_BORDER_ELEMENTS || // first row
i >= numElements - ROW_WITH_BORDER_ELEMENTS || // last row
i % ROW_WITH_BORDER_ELEMENTS == 0 || // first column
i != 0 && i % ROW_WITH_BORDER_ELEMENTS == ROW_WITH_BORDER_ELEMENTS - 1) { // last column
h_universe[i] = BORDER;
} else {
h_universe[i] = rand() % 2 == 0 ? DEAD : ALIVE;
}
}
char *d_in_universe = NULL;
err = cudaMalloc((void **) &d_in_universe, universe_size);
checkError(err, "Failed to allocate device universe (error code %s)!\n");
char *d_out_universe = NULL;
err = cudaMalloc((void **) &d_out_universe, universe_size);
checkError(err, "Failed to allocate device universe (error code %s)!\n");
start = clock();
for (int i = 0; i < STEPS; i++) {
err = cudaMemcpy(d_in_universe, h_universe, universe_size, cudaMemcpyHostToDevice);
checkError(err, "Failed to copy universe from host to device (error code %s)!\n");
computeConwayUniverse<<<BLOCKS_PER_GRID, THREADS_PER_BLOCK>>>(d_in_universe, d_out_universe, numElements);
err = cudaGetLastError();
checkError(err, "Failed to launch Conway kernel (error code %s)!\n");
err = cudaMemcpy(h_universe, d_out_universe, universe_size, cudaMemcpyDeviceToHost);
checkError(err, "Failed to copy universe from device to host (error code %s)!\n");
#ifdef PRINT
printf("\e[0;1H\e[2J");
printf("Step (%d) CUDA Conway kernel launch with %d blocks of %d threads\n", i, BLOCKS_PER_GRID, THREADS_PER_BLOCK);
for (int i=0; i < numElements; ++i) {
if (i % ROW_WITH_BORDER_ELEMENTS == 0){
printf("\n");
}
printf("%c ", h_universe[i]);
}
printf("\n");
sleep(1);
#endif
}
end = clock();
printf("Computations took %f s\n", ((double) (end - start) / CLOCKS_PER_SEC));
err = cudaFree(d_in_universe);
checkError(err, "Failed to free device in universe (error code %s)!\n");
err = cudaFree(d_out_universe);
checkError(err, "Failed to free device out universe (error code %s)!\n");
free(h_universe);
err = cudaDeviceReset();
checkError(err, "Failed to deinitialize the device! error=%s\n");
return 0;
} | .file "tmpxft_00102a70_00000000-6_conway.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2075:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2075:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z18getNeighboursCountPKci
.type _Z18getNeighboursCountPKci, @function
_Z18getNeighboursCountPKci:
.LFB2070:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2070:
.size _Z18getNeighboursCountPKci, .-_Z18getNeighboursCountPKci
.globl _Z10checkError9cudaErrorPKc
.type _Z10checkError9cudaErrorPKc, @function
_Z10checkError9cudaErrorPKc:
.LFB2071:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L10
ret
.L10:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rsi, %rbx
call cudaGetErrorString@PLT
movq %rax, %rcx
movq %rbx, %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2071:
.size _Z10checkError9cudaErrorPKc, .-_Z10checkError9cudaErrorPKc
.globl _Z45__device_stub__Z21computeConwayUniversePKcPcxPKcPcx
.type _Z45__device_stub__Z21computeConwayUniversePKcPcxPKcPcx, @function
_Z45__device_stub__Z21computeConwayUniversePKcPcxPKcPcx:
.LFB2097:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21computeConwayUniversePKcPcx(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2097:
.size _Z45__device_stub__Z21computeConwayUniversePKcPcxPKcPcx, .-_Z45__device_stub__Z21computeConwayUniversePKcPcxPKcPcx
.globl _Z21computeConwayUniversePKcPcx
.type _Z21computeConwayUniversePKcPcx, @function
_Z21computeConwayUniversePKcPcx:
.LFB2098:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z21computeConwayUniversePKcPcxPKcPcx
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2098:
.size _Z21computeConwayUniversePKcPcx, .-_Z21computeConwayUniversePKcPcx
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "[Universe of size %d x %d (%d blocks with %d threads, %d steps)]\n"
.align 8
.LC1:
.string "Failed to allocate host h_universe!\n"
.align 8
.LC2:
.string "Failed to allocate device universe (error code %s)!\n"
.align 8
.LC3:
.string "Failed to copy universe from host to device (error code %s)!\n"
.align 8
.LC4:
.string "Failed to launch Conway kernel (error code %s)!\n"
.align 8
.LC5:
.string "Failed to copy universe from device to host (error code %s)!\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC7:
.string "Computations took %f s\n"
.section .rodata.str1.8
.align 8
.LC8:
.string "Failed to free device in universe (error code %s)!\n"
.align 8
.LC9:
.string "Failed to free device out universe (error code %s)!\n"
.align 8
.LC10:
.string "Failed to deinitialize the device! error=%s\n"
.text
.globl main
.type main, @function
main:
.LFB2072:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
subq $8, %rsp
.cfi_def_cfa_offset 120
pushq $10
.cfi_def_cfa_offset 128
movl $256, %r9d
movl $1, %r8d
movl $1000, %ecx
movl $1000, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1004004, %edi
call malloc@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
testq %rax, %rax
je .L34
movq %rax, %rbp
movl $0, %ebx
jmp .L20
.L34:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L21:
movb $66, 0(%rbp,%rbx)
addq $1, %rbx
cmpq $1004004, %rbx
je .L35
.L20:
leal -1002(%rbx), %eax
cmpl $1001999, %eax
ja .L21
movslq %ebx, %rax
imulq $548658497, %rax, %rax
sarq $39, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
imull $1002, %eax, %edx
movl %ebx, %eax
subl %edx, %eax
je .L21
cmpl $1001, %eax
je .L21
call rand@PLT
andl $1, %eax
cmpl $1, %eax
sbbl %eax, %eax
andl $-3, %eax
addl $35, %eax
movb %al, 0(%rbp,%rbx)
addq $1, %rbx
jmp .L20
.L35:
movq $0, (%rsp)
movq %rsp, %rdi
movl $1004004, %esi
call cudaMalloc@PLT
movl %eax, %edi
leaq .LC2(%rip), %rbx
movq %rbx, %rsi
call _Z10checkError9cudaErrorPKc
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $1004004, %esi
call cudaMalloc@PLT
movl %eax, %edi
movq %rbx, %rsi
call _Z10checkError9cudaErrorPKc
call clock@PLT
movq %rax, %r15
movl $10, %ebx
leaq .LC3(%rip), %r14
leaq .LC4(%rip), %r13
leaq .LC5(%rip), %r12
jmp .L27
.L26:
call cudaGetLastError@PLT
movl %eax, %edi
movq %r13, %rsi
call _Z10checkError9cudaErrorPKc
movl $2, %ecx
movl $1004004, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movq %r12, %rsi
call _Z10checkError9cudaErrorPKc
subl $1, %ebx
je .L36
.L27:
movl $1, %ecx
movl $1004004, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movq %r14, %rsi
call _Z10checkError9cudaErrorPKc
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L26
movl $1004004, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z45__device_stub__Z21computeConwayUniversePKcPcxPKcPcx
jmp .L26
.L36:
call clock@PLT
subq %r15, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC6(%rip), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
leaq .LC8(%rip), %rsi
call _Z10checkError9cudaErrorPKc
movq 8(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
leaq .LC9(%rip), %rsi
call _Z10checkError9cudaErrorPKc
movq %rbp, %rdi
call free@PLT
call cudaDeviceReset@PLT
movl %eax, %edi
leaq .LC10(%rip), %rsi
call _Z10checkError9cudaErrorPKc
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L37
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2072:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC11:
.string "_Z21computeConwayUniversePKcPcx"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2100:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z21computeConwayUniversePKcPcx(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2100:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC6:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <time.h>
#include <unistd.h>
#include <cuda_runtime.h>
// #define PRINT // use with ROW_ELEMENTS < 50
// Cells definitions
#define ALIVE 35 // #
#define DEAD 32 // (space)
#define BORDER 66 // B
// Kernel definition
#define THREADS_PER_BLOCK 256
#define BLOCKS_PER_GRID 1
// Universe definition
#define STEPS 10
#define ROW_ELEMENTS 1000 // 3000 1x1 = 42s
#define ROW_WITH_BORDER_ELEMENTS (ROW_ELEMENTS + 2)
__device__ int getNeighboursCount(const char *universe, int i) {
int count = 0;
int startIndex = i - ROW_WITH_BORDER_ELEMENTS - 1;
for (int j = 0; j < 3; j++) {
for (int k = 0; k < 3; k++) {
int currentIndex = startIndex + k;
if (currentIndex != i && // not itself
universe[currentIndex] == ALIVE) {
count++;
}
}
startIndex += ROW_WITH_BORDER_ELEMENTS;
}
return count;
}
__global__ void computeConwayUniverse(const char *in_universe, char *out_universe, long long int numElements) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
for (; i < numElements; i += blockDim.x * gridDim.x) {
if (in_universe[i] == BORDER) {
out_universe[i] = BORDER;
} else {
int neighboursCount = getNeighboursCount(in_universe, i);
out_universe[i] =
neighboursCount == 3 ? ALIVE : neighboursCount == 2 && in_universe[i] == ALIVE ? ALIVE : DEAD;
}
}
}
void checkError(cudaError_t err, const char *format) {
if (err != cudaSuccess) {
fprintf(stderr, format, cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
}
int main(void) {
srand(time(NULL));
clock_t start, end;
cudaError_t err = cudaSuccess;
long long int numElements = (long long int) ROW_WITH_BORDER_ELEMENTS * (long long int) ROW_WITH_BORDER_ELEMENTS;
size_t universe_size = numElements * sizeof(char);
printf("[Universe of size %d x %d (%d blocks with %d threads, %d steps)]\n", ROW_ELEMENTS, ROW_ELEMENTS, BLOCKS_PER_GRID, THREADS_PER_BLOCK, STEPS);
char *h_universe = (char *) malloc(universe_size);
if (h_universe == NULL) {
fprintf(stderr, "Failed to allocate host h_universe!\n");
exit(EXIT_FAILURE);
}
// Initialize universe
for (int i = 0; i < numElements; ++i) {
if (i < ROW_WITH_BORDER_ELEMENTS || // first row
i >= numElements - ROW_WITH_BORDER_ELEMENTS || // last row
i % ROW_WITH_BORDER_ELEMENTS == 0 || // first column
i != 0 && i % ROW_WITH_BORDER_ELEMENTS == ROW_WITH_BORDER_ELEMENTS - 1) { // last column
h_universe[i] = BORDER;
} else {
h_universe[i] = rand() % 2 == 0 ? DEAD : ALIVE;
}
}
char *d_in_universe = NULL;
err = cudaMalloc((void **) &d_in_universe, universe_size);
checkError(err, "Failed to allocate device universe (error code %s)!\n");
char *d_out_universe = NULL;
err = cudaMalloc((void **) &d_out_universe, universe_size);
checkError(err, "Failed to allocate device universe (error code %s)!\n");
start = clock();
for (int i = 0; i < STEPS; i++) {
err = cudaMemcpy(d_in_universe, h_universe, universe_size, cudaMemcpyHostToDevice);
checkError(err, "Failed to copy universe from host to device (error code %s)!\n");
computeConwayUniverse<<<BLOCKS_PER_GRID, THREADS_PER_BLOCK>>>(d_in_universe, d_out_universe, numElements);
err = cudaGetLastError();
checkError(err, "Failed to launch Conway kernel (error code %s)!\n");
err = cudaMemcpy(h_universe, d_out_universe, universe_size, cudaMemcpyDeviceToHost);
checkError(err, "Failed to copy universe from device to host (error code %s)!\n");
#ifdef PRINT
printf("\e[0;1H\e[2J");
printf("Step (%d) CUDA Conway kernel launch with %d blocks of %d threads\n", i, BLOCKS_PER_GRID, THREADS_PER_BLOCK);
for (int i=0; i < numElements; ++i) {
if (i % ROW_WITH_BORDER_ELEMENTS == 0){
printf("\n");
}
printf("%c ", h_universe[i]);
}
printf("\n");
sleep(1);
#endif
}
end = clock();
printf("Computations took %f s\n", ((double) (end - start) / CLOCKS_PER_SEC));
err = cudaFree(d_in_universe);
checkError(err, "Failed to free device in universe (error code %s)!\n");
err = cudaFree(d_out_universe);
checkError(err, "Failed to free device out universe (error code %s)!\n");
free(h_universe);
err = cudaDeviceReset();
checkError(err, "Failed to deinitialize the device! error=%s\n");
return 0;
} | #include <stdio.h>
#include <time.h>
#include <unistd.h>
#include <hip/hip_runtime.h>
// #define PRINT // use with ROW_ELEMENTS < 50
// Cells definitions
#define ALIVE 35 // #
#define DEAD 32 // (space)
#define BORDER 66 // B
// Kernel definition
#define THREADS_PER_BLOCK 256
#define BLOCKS_PER_GRID 1
// Universe definition
#define STEPS 10
#define ROW_ELEMENTS 1000 // 3000 1x1 = 42s
#define ROW_WITH_BORDER_ELEMENTS (ROW_ELEMENTS + 2)
__device__ int getNeighboursCount(const char *universe, int i) {
int count = 0;
int startIndex = i - ROW_WITH_BORDER_ELEMENTS - 1;
for (int j = 0; j < 3; j++) {
for (int k = 0; k < 3; k++) {
int currentIndex = startIndex + k;
if (currentIndex != i && // not itself
universe[currentIndex] == ALIVE) {
count++;
}
}
startIndex += ROW_WITH_BORDER_ELEMENTS;
}
return count;
}
__global__ void computeConwayUniverse(const char *in_universe, char *out_universe, long long int numElements) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
for (; i < numElements; i += blockDim.x * gridDim.x) {
if (in_universe[i] == BORDER) {
out_universe[i] = BORDER;
} else {
int neighboursCount = getNeighboursCount(in_universe, i);
out_universe[i] =
neighboursCount == 3 ? ALIVE : neighboursCount == 2 && in_universe[i] == ALIVE ? ALIVE : DEAD;
}
}
}
void checkError(hipError_t err, const char *format) {
if (err != hipSuccess) {
fprintf(stderr, format, hipGetErrorString(err));
exit(EXIT_FAILURE);
}
}
int main(void) {
srand(time(NULL));
clock_t start, end;
hipError_t err = hipSuccess;
long long int numElements = (long long int) ROW_WITH_BORDER_ELEMENTS * (long long int) ROW_WITH_BORDER_ELEMENTS;
size_t universe_size = numElements * sizeof(char);
printf("[Universe of size %d x %d (%d blocks with %d threads, %d steps)]\n", ROW_ELEMENTS, ROW_ELEMENTS, BLOCKS_PER_GRID, THREADS_PER_BLOCK, STEPS);
char *h_universe = (char *) malloc(universe_size);
if (h_universe == NULL) {
fprintf(stderr, "Failed to allocate host h_universe!\n");
exit(EXIT_FAILURE);
}
// Initialize universe
for (int i = 0; i < numElements; ++i) {
if (i < ROW_WITH_BORDER_ELEMENTS || // first row
i >= numElements - ROW_WITH_BORDER_ELEMENTS || // last row
i % ROW_WITH_BORDER_ELEMENTS == 0 || // first column
i != 0 && i % ROW_WITH_BORDER_ELEMENTS == ROW_WITH_BORDER_ELEMENTS - 1) { // last column
h_universe[i] = BORDER;
} else {
h_universe[i] = rand() % 2 == 0 ? DEAD : ALIVE;
}
}
char *d_in_universe = NULL;
err = hipMalloc((void **) &d_in_universe, universe_size);
checkError(err, "Failed to allocate device universe (error code %s)!\n");
char *d_out_universe = NULL;
err = hipMalloc((void **) &d_out_universe, universe_size);
checkError(err, "Failed to allocate device universe (error code %s)!\n");
start = clock();
for (int i = 0; i < STEPS; i++) {
err = hipMemcpy(d_in_universe, h_universe, universe_size, hipMemcpyHostToDevice);
checkError(err, "Failed to copy universe from host to device (error code %s)!\n");
computeConwayUniverse<<<BLOCKS_PER_GRID, THREADS_PER_BLOCK>>>(d_in_universe, d_out_universe, numElements);
err = hipGetLastError();
checkError(err, "Failed to launch Conway kernel (error code %s)!\n");
err = hipMemcpy(h_universe, d_out_universe, universe_size, hipMemcpyDeviceToHost);
checkError(err, "Failed to copy universe from device to host (error code %s)!\n");
#ifdef PRINT
printf("\e[0;1H\e[2J");
printf("Step (%d) CUDA Conway kernel launch with %d blocks of %d threads\n", i, BLOCKS_PER_GRID, THREADS_PER_BLOCK);
for (int i=0; i < numElements; ++i) {
if (i % ROW_WITH_BORDER_ELEMENTS == 0){
printf("\n");
}
printf("%c ", h_universe[i]);
}
printf("\n");
sleep(1);
#endif
}
end = clock();
printf("Computations took %f s\n", ((double) (end - start) / CLOCKS_PER_SEC));
err = hipFree(d_in_universe);
checkError(err, "Failed to free device in universe (error code %s)!\n");
err = hipFree(d_out_universe);
checkError(err, "Failed to free device out universe (error code %s)!\n");
free(h_universe);
err = hipDeviceReset();
checkError(err, "Failed to deinitialize the device! error=%s\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <time.h>
#include <unistd.h>
#include <hip/hip_runtime.h>
// #define PRINT // use with ROW_ELEMENTS < 50
// Cells definitions
#define ALIVE 35 // #
#define DEAD 32 // (space)
#define BORDER 66 // B
// Kernel definition
#define THREADS_PER_BLOCK 256
#define BLOCKS_PER_GRID 1
// Universe definition
#define STEPS 10
#define ROW_ELEMENTS 1000 // 3000 1x1 = 42s
#define ROW_WITH_BORDER_ELEMENTS (ROW_ELEMENTS + 2)
__device__ int getNeighboursCount(const char *universe, int i) {
int count = 0;
int startIndex = i - ROW_WITH_BORDER_ELEMENTS - 1;
for (int j = 0; j < 3; j++) {
for (int k = 0; k < 3; k++) {
int currentIndex = startIndex + k;
if (currentIndex != i && // not itself
universe[currentIndex] == ALIVE) {
count++;
}
}
startIndex += ROW_WITH_BORDER_ELEMENTS;
}
return count;
}
__global__ void computeConwayUniverse(const char *in_universe, char *out_universe, long long int numElements) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
for (; i < numElements; i += blockDim.x * gridDim.x) {
if (in_universe[i] == BORDER) {
out_universe[i] = BORDER;
} else {
int neighboursCount = getNeighboursCount(in_universe, i);
out_universe[i] =
neighboursCount == 3 ? ALIVE : neighboursCount == 2 && in_universe[i] == ALIVE ? ALIVE : DEAD;
}
}
}
void checkError(hipError_t err, const char *format) {
if (err != hipSuccess) {
fprintf(stderr, format, hipGetErrorString(err));
exit(EXIT_FAILURE);
}
}
int main(void) {
srand(time(NULL));
clock_t start, end;
hipError_t err = hipSuccess;
long long int numElements = (long long int) ROW_WITH_BORDER_ELEMENTS * (long long int) ROW_WITH_BORDER_ELEMENTS;
size_t universe_size = numElements * sizeof(char);
printf("[Universe of size %d x %d (%d blocks with %d threads, %d steps)]\n", ROW_ELEMENTS, ROW_ELEMENTS, BLOCKS_PER_GRID, THREADS_PER_BLOCK, STEPS);
char *h_universe = (char *) malloc(universe_size);
if (h_universe == NULL) {
fprintf(stderr, "Failed to allocate host h_universe!\n");
exit(EXIT_FAILURE);
}
// Initialize universe
for (int i = 0; i < numElements; ++i) {
if (i < ROW_WITH_BORDER_ELEMENTS || // first row
i >= numElements - ROW_WITH_BORDER_ELEMENTS || // last row
i % ROW_WITH_BORDER_ELEMENTS == 0 || // first column
i != 0 && i % ROW_WITH_BORDER_ELEMENTS == ROW_WITH_BORDER_ELEMENTS - 1) { // last column
h_universe[i] = BORDER;
} else {
h_universe[i] = rand() % 2 == 0 ? DEAD : ALIVE;
}
}
char *d_in_universe = NULL;
err = hipMalloc((void **) &d_in_universe, universe_size);
checkError(err, "Failed to allocate device universe (error code %s)!\n");
char *d_out_universe = NULL;
err = hipMalloc((void **) &d_out_universe, universe_size);
checkError(err, "Failed to allocate device universe (error code %s)!\n");
start = clock();
for (int i = 0; i < STEPS; i++) {
err = hipMemcpy(d_in_universe, h_universe, universe_size, hipMemcpyHostToDevice);
checkError(err, "Failed to copy universe from host to device (error code %s)!\n");
computeConwayUniverse<<<BLOCKS_PER_GRID, THREADS_PER_BLOCK>>>(d_in_universe, d_out_universe, numElements);
err = hipGetLastError();
checkError(err, "Failed to launch Conway kernel (error code %s)!\n");
err = hipMemcpy(h_universe, d_out_universe, universe_size, hipMemcpyDeviceToHost);
checkError(err, "Failed to copy universe from device to host (error code %s)!\n");
#ifdef PRINT
printf("\e[0;1H\e[2J");
printf("Step (%d) CUDA Conway kernel launch with %d blocks of %d threads\n", i, BLOCKS_PER_GRID, THREADS_PER_BLOCK);
for (int i=0; i < numElements; ++i) {
if (i % ROW_WITH_BORDER_ELEMENTS == 0){
printf("\n");
}
printf("%c ", h_universe[i]);
}
printf("\n");
sleep(1);
#endif
}
end = clock();
printf("Computations took %f s\n", ((double) (end - start) / CLOCKS_PER_SEC));
err = hipFree(d_in_universe);
checkError(err, "Failed to free device in universe (error code %s)!\n");
err = hipFree(d_out_universe);
checkError(err, "Failed to free device out universe (error code %s)!\n");
free(h_universe);
err = hipDeviceReset();
checkError(err, "Failed to deinitialize the device! error=%s\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21computeConwayUniversePKcPcx
.globl _Z21computeConwayUniversePKcPcx
.p2align 8
.type _Z21computeConwayUniversePKcPcx,@function
_Z21computeConwayUniversePKcPcx:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_mov_b32 s7, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s15, s15, s6
v_add_nc_u32_e32 v1, s15, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_cmpx_gt_i64_e64 s[4:5], v[1:2]
s_cbranch_execz .LBB0_19
s_load_b32 s8, s[2:3], 0x0
s_load_b128 s[0:3], s[0:1], 0x0
v_add3_u32 v0, v0, s15, 0xfffffc15
s_mov_b32 s9, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s8, s6
s_branch .LBB0_4
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s11
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
s_or_b32 exec_lo, exec_lo, s10
v_add_co_u32 v5, vcc_lo, s2, v1
v_add_nc_u32_e32 v1, s8, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v2, vcc_lo
v_add_nc_u32_e32 v0, s8, v0
v_ashrrev_i32_e32 v2, 31, v1
global_store_b8 v[5:6], v4, off
v_cmp_le_i64_e32 vcc_lo, s[4:5], v[1:2]
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execz .LBB0_19
.LBB0_4:
v_add_co_u32 v3, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v2, vcc_lo
s_mov_b32 s10, exec_lo
global_load_u8 v3, v[3:4], off
v_mov_b32_e32 v4, 0x42
s_waitcnt vmcnt(0)
v_cmpx_ne_u16_e32 0x42, v3
s_cbranch_execz .LBB0_3
v_ashrrev_i32_e32 v4, 31, v0
v_add_co_u32 v5, vcc_lo, s0, v0
s_mov_b32 s11, 0
s_movk_i32 s12, 0x3ea
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v4, vcc_lo
v_mov_b32_e32 v4, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_7
.p2align 6
.LBB0_6:
v_add_co_u32 v5, vcc_lo, v5, 0x3ea
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
s_add_i32 s11, s11, 1
s_addk_i32 s12, 0xfc16
s_cmp_eq_u32 s11, 3
s_cbranch_scc1 .LBB0_11
.LBB0_7:
s_add_u32 s13, s12, 1
s_mov_b64 s[6:7], 0
s_branch .LBB0_9
.LBB0_8:
s_add_u32 s6, s6, 1
s_addc_u32 s7, s7, 0
s_cmp_eq_u32 s6, 3
s_cbranch_scc1 .LBB0_6
.LBB0_9:
s_cmp_eq_u32 s13, s6
s_cbranch_scc1 .LBB0_8
v_add_co_u32 v7, vcc_lo, v5, s6
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v6, vcc_lo
global_load_u8 v7, v[7:8], off
s_waitcnt vmcnt(0)
v_cmp_eq_u16_e32 vcc_lo, 35, v7
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_branch .LBB0_8
.LBB0_11:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s7, 0
s_mov_b32 s12, exec_lo
v_cmpx_lt_i32_e32 2, v4
s_xor_b32 s12, exec_lo, s12
v_cmp_ne_u32_e32 vcc_lo, 3, v4
s_mov_b32 s6, 0
s_mov_b32 s11, 35
s_and_b32 s7, vcc_lo, exec_lo
s_and_not1_saveexec_b32 s12, s12
s_cbranch_execz .LBB0_17
s_mov_b32 s13, 0
s_mov_b32 s14, exec_lo
v_cmpx_eq_u32_e32 2, v4
v_cmp_eq_u16_e32 vcc_lo, 35, v3
s_and_b32 s13, vcc_lo, exec_lo
s_or_b32 exec_lo, exec_lo, s14
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 s6, s6, exec_lo
s_and_b32 s13, s13, exec_lo
s_or_b32 s7, s7, exec_lo
s_or_b32 s6, s6, s13
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s12
v_mov_b32_e32 v4, s11
s_and_saveexec_b32 s11, s7
s_cbranch_execz .LBB0_2
v_cndmask_b32_e64 v4, 32, 35, s6
s_branch .LBB0_2
.LBB0_19:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21computeConwayUniversePKcPcx
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21computeConwayUniversePKcPcx, .Lfunc_end0-_Z21computeConwayUniversePKcPcx
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21computeConwayUniversePKcPcx
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21computeConwayUniversePKcPcx.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <time.h>
#include <unistd.h>
#include <hip/hip_runtime.h>
// #define PRINT // use with ROW_ELEMENTS < 50
// Cells definitions
#define ALIVE 35 // #
#define DEAD 32 // (space)
#define BORDER 66 // B
// Kernel definition
#define THREADS_PER_BLOCK 256
#define BLOCKS_PER_GRID 1
// Universe definition
#define STEPS 10
#define ROW_ELEMENTS 1000 // 3000 1x1 = 42s
#define ROW_WITH_BORDER_ELEMENTS (ROW_ELEMENTS + 2)
__device__ int getNeighboursCount(const char *universe, int i) {
int count = 0;
int startIndex = i - ROW_WITH_BORDER_ELEMENTS - 1;
for (int j = 0; j < 3; j++) {
for (int k = 0; k < 3; k++) {
int currentIndex = startIndex + k;
if (currentIndex != i && // not itself
universe[currentIndex] == ALIVE) {
count++;
}
}
startIndex += ROW_WITH_BORDER_ELEMENTS;
}
return count;
}
__global__ void computeConwayUniverse(const char *in_universe, char *out_universe, long long int numElements) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
for (; i < numElements; i += blockDim.x * gridDim.x) {
if (in_universe[i] == BORDER) {
out_universe[i] = BORDER;
} else {
int neighboursCount = getNeighboursCount(in_universe, i);
out_universe[i] =
neighboursCount == 3 ? ALIVE : neighboursCount == 2 && in_universe[i] == ALIVE ? ALIVE : DEAD;
}
}
}
void checkError(hipError_t err, const char *format) {
if (err != hipSuccess) {
fprintf(stderr, format, hipGetErrorString(err));
exit(EXIT_FAILURE);
}
}
int main(void) {
srand(time(NULL));
clock_t start, end;
hipError_t err = hipSuccess;
long long int numElements = (long long int) ROW_WITH_BORDER_ELEMENTS * (long long int) ROW_WITH_BORDER_ELEMENTS;
size_t universe_size = numElements * sizeof(char);
printf("[Universe of size %d x %d (%d blocks with %d threads, %d steps)]\n", ROW_ELEMENTS, ROW_ELEMENTS, BLOCKS_PER_GRID, THREADS_PER_BLOCK, STEPS);
char *h_universe = (char *) malloc(universe_size);
if (h_universe == NULL) {
fprintf(stderr, "Failed to allocate host h_universe!\n");
exit(EXIT_FAILURE);
}
// Initialize universe
for (int i = 0; i < numElements; ++i) {
if (i < ROW_WITH_BORDER_ELEMENTS || // first row
i >= numElements - ROW_WITH_BORDER_ELEMENTS || // last row
i % ROW_WITH_BORDER_ELEMENTS == 0 || // first column
i != 0 && i % ROW_WITH_BORDER_ELEMENTS == ROW_WITH_BORDER_ELEMENTS - 1) { // last column
h_universe[i] = BORDER;
} else {
h_universe[i] = rand() % 2 == 0 ? DEAD : ALIVE;
}
}
char *d_in_universe = NULL;
err = hipMalloc((void **) &d_in_universe, universe_size);
checkError(err, "Failed to allocate device universe (error code %s)!\n");
char *d_out_universe = NULL;
err = hipMalloc((void **) &d_out_universe, universe_size);
checkError(err, "Failed to allocate device universe (error code %s)!\n");
start = clock();
for (int i = 0; i < STEPS; i++) {
err = hipMemcpy(d_in_universe, h_universe, universe_size, hipMemcpyHostToDevice);
checkError(err, "Failed to copy universe from host to device (error code %s)!\n");
computeConwayUniverse<<<BLOCKS_PER_GRID, THREADS_PER_BLOCK>>>(d_in_universe, d_out_universe, numElements);
err = hipGetLastError();
checkError(err, "Failed to launch Conway kernel (error code %s)!\n");
err = hipMemcpy(h_universe, d_out_universe, universe_size, hipMemcpyDeviceToHost);
checkError(err, "Failed to copy universe from device to host (error code %s)!\n");
#ifdef PRINT
printf("\e[0;1H\e[2J");
printf("Step (%d) CUDA Conway kernel launch with %d blocks of %d threads\n", i, BLOCKS_PER_GRID, THREADS_PER_BLOCK);
for (int i=0; i < numElements; ++i) {
if (i % ROW_WITH_BORDER_ELEMENTS == 0){
printf("\n");
}
printf("%c ", h_universe[i]);
}
printf("\n");
sleep(1);
#endif
}
end = clock();
printf("Computations took %f s\n", ((double) (end - start) / CLOCKS_PER_SEC));
err = hipFree(d_in_universe);
checkError(err, "Failed to free device in universe (error code %s)!\n");
err = hipFree(d_out_universe);
checkError(err, "Failed to free device out universe (error code %s)!\n");
free(h_universe);
err = hipDeviceReset();
checkError(err, "Failed to deinitialize the device! error=%s\n");
return 0;
} | .text
.file "conway.hip"
.globl _Z36__device_stub__computeConwayUniversePKcPcx # -- Begin function _Z36__device_stub__computeConwayUniversePKcPcx
.p2align 4, 0x90
.type _Z36__device_stub__computeConwayUniversePKcPcx,@function
_Z36__device_stub__computeConwayUniversePKcPcx: # @_Z36__device_stub__computeConwayUniversePKcPcx
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21computeConwayUniversePKcPcx, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z36__device_stub__computeConwayUniversePKcPcx, .Lfunc_end0-_Z36__device_stub__computeConwayUniversePKcPcx
.cfi_endproc
# -- End function
.globl _Z10checkError10hipError_tPKc # -- Begin function _Z10checkError10hipError_tPKc
.p2align 4, 0x90
.type _Z10checkError10hipError_tPKc,@function
_Z10checkError10hipError_tPKc: # @_Z10checkError10hipError_tPKc
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB1_2
# %bb.1:
retq
.LBB1_2:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq stderr(%rip), %rbx
movq %rsi, %r14
callq hipGetErrorString
movq %rbx, %rdi
movq %r14, %rsi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z10checkError10hipError_tPKc, .Lfunc_end1-_Z10checkError10hipError_tPKc
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl $.L.str, %edi
movl $1000, %esi # imm = 0x3E8
movl $1000, %edx # imm = 0x3E8
movl $1, %ecx
movl $256, %r8d # imm = 0x100
movl $10, %r9d
xorl %eax, %eax
callq printf
movl $1004004, %edi # imm = 0xF51E4
callq malloc
testq %rax, %rax
je .LBB2_28
# %bb.1: # %.preheader.preheader
movq %rax, %rbx
xorl %r14d, %r14d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_6: # in Loop: Header=BB2_2 Depth=1
movb %al, (%rbx,%r14)
incq %r14
cmpq $1004004, %r14 # imm = 0xF51E4
je .LBB2_7
.LBB2_2: # %.preheader
# =>This Inner Loop Header: Depth=1
leal -1003002(%r14), %ecx
movb $66, %al
cmpl $-1002000, %ecx # imm = 0xFFF0B5F0
jb .LBB2_6
# %bb.3: # in Loop: Header=BB2_2 Depth=1
movl %r14d, %ecx
imulq $548658497, %rcx, %rcx # imm = 0x20B3DD41
shrq $39, %rcx
imull $-1002, %ecx, %ecx # imm = 0xFC16
addl %r14d, %ecx
je .LBB2_6
# %bb.4: # in Loop: Header=BB2_2 Depth=1
cmpl $1001, %ecx # imm = 0x3E9
je .LBB2_6
# %bb.5: # in Loop: Header=BB2_2 Depth=1
callq rand
xorl %ecx, %ecx
testb $1, %al
setne %cl
leal (%rcx,%rcx,2), %eax
addl $32, %eax
jmp .LBB2_6
.LBB2_7:
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $1004004, %esi # imm = 0xF51E4
callq hipMalloc
testl %eax, %eax
jne .LBB2_8
# %bb.10: # %_Z10checkError10hipError_tPKc.exit
movq $0, (%rsp)
movq %rsp, %rdi
movl $1004004, %esi # imm = 0xF51E4
callq hipMalloc
testl %eax, %eax
jne .LBB2_8
# %bb.11: # %_Z10checkError10hipError_tPKc.exit42
movabsq $4294967297, %r15 # imm = 0x100000001
movl $10, %r14d
callq clock
movq %rax, 16(%rsp) # 8-byte Spill
leaq 255(%r15), %r12
leaq 24(%rsp), %r13
leaq 96(%rsp), %rbp
.p2align 4, 0x90
.LBB2_12: # =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rdi
movl $1004004, %edx # imm = 0xF51E4
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_13
# %bb.22: # %_Z10checkError10hipError_tPKc.exit50
# in Loop: Header=BB2_12 Depth=1
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_24
# %bb.23: # in Loop: Header=BB2_12 Depth=1
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq $1004004, 72(%rsp) # imm = 0xF51E4
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z21computeConwayUniversePKcPcx, %edi
movq %rbp, %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_24: # in Loop: Header=BB2_12 Depth=1
callq hipGetLastError
testl %eax, %eax
jne .LBB2_25
# %bb.26: # %_Z10checkError10hipError_tPKc.exit52
# in Loop: Header=BB2_12 Depth=1
movq (%rsp), %rsi
movl $1004004, %edx # imm = 0xF51E4
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_27
# %bb.14: # in Loop: Header=BB2_12 Depth=1
decl %r14d
jne .LBB2_12
# %bb.15:
callq clock
subq 16(%rsp), %rax # 8-byte Folded Reload
cvtsi2sd %rax, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_16
# %bb.17: # %_Z10checkError10hipError_tPKc.exit44
movq (%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_18
# %bb.19: # %_Z10checkError10hipError_tPKc.exit46
movq %rbx, %rdi
callq free
callq hipDeviceReset
testl %eax, %eax
jne .LBB2_20
# %bb.21: # %_Z10checkError10hipError_tPKc.exit48
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_27:
.cfi_def_cfa_offset 176
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
jmp .LBB2_9
.LBB2_25:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %esi
jmp .LBB2_9
.LBB2_13:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
.LBB2_9:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB2_8:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
jmp .LBB2_9
.LBB2_28:
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $36, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.LBB2_16:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %esi
jmp .LBB2_9
.LBB2_18:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
jmp .LBB2_9
.LBB2_20:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.9, %esi
jmp .LBB2_9
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21computeConwayUniversePKcPcx, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21computeConwayUniversePKcPcx,@object # @_Z21computeConwayUniversePKcPcx
.section .rodata,"a",@progbits
.globl _Z21computeConwayUniversePKcPcx
.p2align 3, 0x0
_Z21computeConwayUniversePKcPcx:
.quad _Z36__device_stub__computeConwayUniversePKcPcx
.size _Z21computeConwayUniversePKcPcx, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "[Universe of size %d x %d (%d blocks with %d threads, %d steps)]\n"
.size .L.str, 66
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Failed to allocate host h_universe!\n"
.size .L.str.1, 37
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Failed to allocate device universe (error code %s)!\n"
.size .L.str.2, 53
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Failed to copy universe from host to device (error code %s)!\n"
.size .L.str.3, 62
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Failed to launch Conway kernel (error code %s)!\n"
.size .L.str.4, 49
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Failed to copy universe from device to host (error code %s)!\n"
.size .L.str.5, 62
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Computations took %f s\n"
.size .L.str.6, 24
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Failed to free device in universe (error code %s)!\n"
.size .L.str.7, 52
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Failed to free device out universe (error code %s)!\n"
.size .L.str.8, 53
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Failed to deinitialize the device! error=%s\n"
.size .L.str.9, 45
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z21computeConwayUniversePKcPcx"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__computeConwayUniversePKcPcx
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21computeConwayUniversePKcPcx
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z21computeConwayUniversePKcPcx
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */
/* 0x000fc80000011400 */
/*0060*/ ISETP.GE.AND.EX P0, PT, R2, c[0x0][0x174], PT, P0 ; /* 0x00005d0002007a0c */
/* 0x000fda0003f06300 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R8, RZ, RZ, R2 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0002 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fca00078e0000 */
/*00b0*/ IADD3 R4, P0, R7, c[0x0][0x160], RZ ; /* 0x0000580007047a10 */
/* 0x000fc80007f1e0ff */
/*00c0*/ IADD3.X R5, R8, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590008057a10 */
/* 0x000fca00007fe4ff */
/*00d0*/ LDG.E.U8 R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ea2000c1e1100 */
/*00e0*/ IADD3 R2, P1, R7, c[0x0][0x168], RZ ; /* 0x00005a0007027a10 */
/* 0x000fe20007f3e0ff */
/*00f0*/ BSSY B0, 0x3b0 ; /* 0x000002b000007945 */
/* 0x000fe20003800000 */
/*0100*/ IMAD.MOV.U32 R6, RZ, RZ, 0x42 ; /* 0x00000042ff067424 */
/* 0x000fe400078e00ff */
/*0110*/ IADD3.X R3, R8, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0008037a10 */
/* 0x000fe20000ffe4ff */
/*0120*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0f7624 */
/* 0x000fe200078e00ff */
/*0130*/ ISETP.NE.AND P0, PT, R14, 0x42, PT ; /* 0x000000420e00780c */
/* 0x004fda0003f05270 */
/*0140*/ @!P0 BRA 0x3a0 ; /* 0x0000025000008947 */
/* 0x000fea0003800000 */
/*0150*/ LDG.E.U8 R7, [R4.64+-0x3ea] ; /* 0xfffc160404077981 */
/* 0x000ea8000c1e1100 */
/*0160*/ LDG.E.U8 R6, [R4.64+-0x3eb] ; /* 0xfffc150404067981 */
/* 0x000ee8000c1e1100 */
/*0170*/ LDG.E.U8 R8, [R4.64+-0x3e9] ; /* 0xfffc170404087981 */
/* 0x000f28000c1e1100 */
/*0180*/ LDG.E.U8 R9, [R4.64+-0x1] ; /* 0xffffff0404097981 */
/* 0x000f68000c1e1100 */
/*0190*/ LDG.E.U8 R10, [R4.64+0x1] ; /* 0x00000104040a7981 */
/* 0x000f68000c1e1100 */
/*01a0*/ LDG.E.U8 R11, [R4.64+0x3e9] ; /* 0x0003e904040b7981 */
/* 0x000168000c1e1100 */
/*01b0*/ LDG.E.U8 R12, [R4.64+0x3ea] ; /* 0x0003ea04040c7981 */
/* 0x000168000c1e1100 */
/*01c0*/ LDG.E.U8 R13, [R4.64+0x3eb] ; /* 0x0003eb04040d7981 */
/* 0x000162000c1e1100 */
/*01d0*/ ISETP.NE.AND P2, PT, R7, 0x23, PT ; /* 0x000000230700780c */
/* 0x004fe20003f45270 */
/*01e0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x2 ; /* 0x00000002ff077424 */
/* 0x000fe200078e00ff */
/*01f0*/ ISETP.NE.AND P1, PT, R6, 0x23, PT ; /* 0x000000230600780c */
/* 0x008fc40003f25270 */
/*0200*/ SEL R6, RZ, 0x1, P2 ; /* 0x00000001ff067807 */
/* 0x000fe40001000000 */
/*0210*/ ISETP.NE.AND P0, PT, R8, 0x23, PT ; /* 0x000000230800780c */
/* 0x010fce0003f05270 */
/*0220*/ @P2 IMAD.MOV R7, RZ, RZ, 0x1 ; /* 0x00000001ff072424 */
/* 0x000fe400078e02ff */
/*0230*/ @P1 IMAD.MOV R7, RZ, RZ, R6 ; /* 0x000000ffff071224 */
/* 0x000fe200078e0206 */
/*0240*/ ISETP.NE.AND P1, PT, R9, 0x23, PT ; /* 0x000000230900780c */
/* 0x020fc80003f25270 */
/*0250*/ IADD3 R6, R7, 0x1, RZ ; /* 0x0000000107067810 */
/* 0x000fe20007ffe0ff */
/*0260*/ @P0 IMAD.MOV R6, RZ, RZ, R7 ; /* 0x000000ffff060224 */
/* 0x000fe200078e0207 */
/*0270*/ ISETP.NE.AND P0, PT, R10, 0x23, PT ; /* 0x000000230a00780c */
/* 0x000fc80003f05270 */
/*0280*/ IADD3 R4, R6, 0x1, RZ ; /* 0x0000000106047810 */
/* 0x001fc60007ffe0ff */
/*0290*/ @P1 IMAD.MOV R4, RZ, RZ, R6 ; /* 0x000000ffff041224 */
/* 0x000fe200078e0206 */
/*02a0*/ ISETP.NE.AND P1, PT, R11, 0x23, PT ; /* 0x000000230b00780c */
/* 0x000fe20003f25270 */
/*02b0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x23 ; /* 0x00000023ff067424 */
/* 0x000fc600078e00ff */
/*02c0*/ IADD3 R5, R4, 0x1, RZ ; /* 0x0000000104057810 */
/* 0x000fe20007ffe0ff */
/*02d0*/ @P0 IMAD.MOV R5, RZ, RZ, R4 ; /* 0x000000ffff050224 */
/* 0x000fe200078e0204 */
/*02e0*/ ISETP.NE.AND P0, PT, R12, 0x23, PT ; /* 0x000000230c00780c */
/* 0x000fc80003f05270 */
/*02f0*/ IADD3 R4, R5, 0x1, RZ ; /* 0x0000000105047810 */
/* 0x000fc60007ffe0ff */
/*0300*/ @P1 IMAD.MOV R4, RZ, RZ, R5 ; /* 0x000000ffff041224 */
/* 0x000fe200078e0205 */
/*0310*/ ISETP.NE.AND P1, PT, R13, 0x23, PT ; /* 0x000000230d00780c */
/* 0x000fc80003f25270 */
/*0320*/ IADD3 R5, R4, 0x1, RZ ; /* 0x0000000104057810 */
/* 0x000fe20007ffe0ff */
/*0330*/ @P0 IMAD.MOV R5, RZ, RZ, R4 ; /* 0x000000ffff050224 */
/* 0x000fe200078e0204 */
/*0340*/ ISETP.NE.AND P0, PT, R14, 0x23, PT ; /* 0x000000230e00780c */
/* 0x000fc80003f05270 */
/*0350*/ IADD3 R4, R5, 0x1, RZ ; /* 0x0000000105047810 */
/* 0x000fc60007ffe0ff */
/*0360*/ @P1 IMAD.MOV R4, RZ, RZ, R5 ; /* 0x000000ffff041224 */
/* 0x000fca00078e0205 */
/*0370*/ ISETP.EQ.AND P0, PT, R4, 0x2, !P0 ; /* 0x000000020400780c */
/* 0x000fc80004702270 */
/*0380*/ ISETP.EQ.OR P0, PT, R4, 0x3, P0 ; /* 0x000000030400780c */
/* 0x000fc80000702670 */
/*0390*/ SEL R6, R6, 0x20, P0 ; /* 0x0000002006067807 */
/* 0x000fc80000000000 */
/*03a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03b0*/ IMAD R7, R15, c[0x0][0xc], R0 ; /* 0x000003000f077a24 */
/* 0x000fe200078e0200 */
/*03c0*/ STG.E.U8 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x0001e6000c101104 */
/*03d0*/ IMAD.MOV.U32 R0, RZ, RZ, R7.reuse ; /* 0x000000ffff007224 */
/* 0x100fe200078e0007 */
/*03e0*/ ISETP.GE.U32.AND P0, PT, R7, c[0x0][0x170], PT ; /* 0x00005c0007007a0c */
/* 0x000fe40003f06070 */
/*03f0*/ SHF.R.S32.HI R8, RZ, 0x1f, R7 ; /* 0x0000001fff087819 */
/* 0x000fc80000011407 */
/*0400*/ ISETP.GE.AND.EX P0, PT, R8, c[0x0][0x174], PT, P0 ; /* 0x00005d0008007a0c */
/* 0x000fda0003f06300 */
/*0410*/ @!P0 BRA 0xb0 ; /* 0xfffffc9000008947 */
/* 0x001fea000383ffff */
/*0420*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0430*/ BRA 0x430; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21computeConwayUniversePKcPcx
.globl _Z21computeConwayUniversePKcPcx
.p2align 8
.type _Z21computeConwayUniversePKcPcx,@function
_Z21computeConwayUniversePKcPcx:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_mov_b32 s7, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s15, s15, s6
v_add_nc_u32_e32 v1, s15, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_cmpx_gt_i64_e64 s[4:5], v[1:2]
s_cbranch_execz .LBB0_19
s_load_b32 s8, s[2:3], 0x0
s_load_b128 s[0:3], s[0:1], 0x0
v_add3_u32 v0, v0, s15, 0xfffffc15
s_mov_b32 s9, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s8, s6
s_branch .LBB0_4
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s11
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
s_or_b32 exec_lo, exec_lo, s10
v_add_co_u32 v5, vcc_lo, s2, v1
v_add_nc_u32_e32 v1, s8, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v2, vcc_lo
v_add_nc_u32_e32 v0, s8, v0
v_ashrrev_i32_e32 v2, 31, v1
global_store_b8 v[5:6], v4, off
v_cmp_le_i64_e32 vcc_lo, s[4:5], v[1:2]
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execz .LBB0_19
.LBB0_4:
v_add_co_u32 v3, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v2, vcc_lo
s_mov_b32 s10, exec_lo
global_load_u8 v3, v[3:4], off
v_mov_b32_e32 v4, 0x42
s_waitcnt vmcnt(0)
v_cmpx_ne_u16_e32 0x42, v3
s_cbranch_execz .LBB0_3
v_ashrrev_i32_e32 v4, 31, v0
v_add_co_u32 v5, vcc_lo, s0, v0
s_mov_b32 s11, 0
s_movk_i32 s12, 0x3ea
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v4, vcc_lo
v_mov_b32_e32 v4, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_7
.p2align 6
.LBB0_6:
v_add_co_u32 v5, vcc_lo, v5, 0x3ea
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
s_add_i32 s11, s11, 1
s_addk_i32 s12, 0xfc16
s_cmp_eq_u32 s11, 3
s_cbranch_scc1 .LBB0_11
.LBB0_7:
s_add_u32 s13, s12, 1
s_mov_b64 s[6:7], 0
s_branch .LBB0_9
.LBB0_8:
s_add_u32 s6, s6, 1
s_addc_u32 s7, s7, 0
s_cmp_eq_u32 s6, 3
s_cbranch_scc1 .LBB0_6
.LBB0_9:
s_cmp_eq_u32 s13, s6
s_cbranch_scc1 .LBB0_8
v_add_co_u32 v7, vcc_lo, v5, s6
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v6, vcc_lo
global_load_u8 v7, v[7:8], off
s_waitcnt vmcnt(0)
v_cmp_eq_u16_e32 vcc_lo, 35, v7
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_branch .LBB0_8
.LBB0_11:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s7, 0
s_mov_b32 s12, exec_lo
v_cmpx_lt_i32_e32 2, v4
s_xor_b32 s12, exec_lo, s12
v_cmp_ne_u32_e32 vcc_lo, 3, v4
s_mov_b32 s6, 0
s_mov_b32 s11, 35
s_and_b32 s7, vcc_lo, exec_lo
s_and_not1_saveexec_b32 s12, s12
s_cbranch_execz .LBB0_17
s_mov_b32 s13, 0
s_mov_b32 s14, exec_lo
v_cmpx_eq_u32_e32 2, v4
v_cmp_eq_u16_e32 vcc_lo, 35, v3
s_and_b32 s13, vcc_lo, exec_lo
s_or_b32 exec_lo, exec_lo, s14
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 s6, s6, exec_lo
s_and_b32 s13, s13, exec_lo
s_or_b32 s7, s7, exec_lo
s_or_b32 s6, s6, s13
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s12
v_mov_b32_e32 v4, s11
s_and_saveexec_b32 s11, s7
s_cbranch_execz .LBB0_2
v_cndmask_b32_e64 v4, 32, 35, s6
s_branch .LBB0_2
.LBB0_19:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21computeConwayUniversePKcPcx
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21computeConwayUniversePKcPcx, .Lfunc_end0-_Z21computeConwayUniversePKcPcx
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21computeConwayUniversePKcPcx
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21computeConwayUniversePKcPcx.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00102a70_00000000-6_conway.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2075:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2075:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z18getNeighboursCountPKci
.type _Z18getNeighboursCountPKci, @function
_Z18getNeighboursCountPKci:
.LFB2070:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2070:
.size _Z18getNeighboursCountPKci, .-_Z18getNeighboursCountPKci
.globl _Z10checkError9cudaErrorPKc
.type _Z10checkError9cudaErrorPKc, @function
_Z10checkError9cudaErrorPKc:
.LFB2071:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L10
ret
.L10:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rsi, %rbx
call cudaGetErrorString@PLT
movq %rax, %rcx
movq %rbx, %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2071:
.size _Z10checkError9cudaErrorPKc, .-_Z10checkError9cudaErrorPKc
.globl _Z45__device_stub__Z21computeConwayUniversePKcPcxPKcPcx
.type _Z45__device_stub__Z21computeConwayUniversePKcPcxPKcPcx, @function
_Z45__device_stub__Z21computeConwayUniversePKcPcxPKcPcx:
.LFB2097:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21computeConwayUniversePKcPcx(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2097:
.size _Z45__device_stub__Z21computeConwayUniversePKcPcxPKcPcx, .-_Z45__device_stub__Z21computeConwayUniversePKcPcxPKcPcx
.globl _Z21computeConwayUniversePKcPcx
.type _Z21computeConwayUniversePKcPcx, @function
_Z21computeConwayUniversePKcPcx:
.LFB2098:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z21computeConwayUniversePKcPcxPKcPcx
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2098:
.size _Z21computeConwayUniversePKcPcx, .-_Z21computeConwayUniversePKcPcx
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "[Universe of size %d x %d (%d blocks with %d threads, %d steps)]\n"
.align 8
.LC1:
.string "Failed to allocate host h_universe!\n"
.align 8
.LC2:
.string "Failed to allocate device universe (error code %s)!\n"
.align 8
.LC3:
.string "Failed to copy universe from host to device (error code %s)!\n"
.align 8
.LC4:
.string "Failed to launch Conway kernel (error code %s)!\n"
.align 8
.LC5:
.string "Failed to copy universe from device to host (error code %s)!\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC7:
.string "Computations took %f s\n"
.section .rodata.str1.8
.align 8
.LC8:
.string "Failed to free device in universe (error code %s)!\n"
.align 8
.LC9:
.string "Failed to free device out universe (error code %s)!\n"
.align 8
.LC10:
.string "Failed to deinitialize the device! error=%s\n"
.text
.globl main
.type main, @function
main:
.LFB2072:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
subq $8, %rsp
.cfi_def_cfa_offset 120
pushq $10
.cfi_def_cfa_offset 128
movl $256, %r9d
movl $1, %r8d
movl $1000, %ecx
movl $1000, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1004004, %edi
call malloc@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
testq %rax, %rax
je .L34
movq %rax, %rbp
movl $0, %ebx
jmp .L20
.L34:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L21:
movb $66, 0(%rbp,%rbx)
addq $1, %rbx
cmpq $1004004, %rbx
je .L35
.L20:
leal -1002(%rbx), %eax
cmpl $1001999, %eax
ja .L21
movslq %ebx, %rax
imulq $548658497, %rax, %rax
sarq $39, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
imull $1002, %eax, %edx
movl %ebx, %eax
subl %edx, %eax
je .L21
cmpl $1001, %eax
je .L21
call rand@PLT
andl $1, %eax
cmpl $1, %eax
sbbl %eax, %eax
andl $-3, %eax
addl $35, %eax
movb %al, 0(%rbp,%rbx)
addq $1, %rbx
jmp .L20
.L35:
movq $0, (%rsp)
movq %rsp, %rdi
movl $1004004, %esi
call cudaMalloc@PLT
movl %eax, %edi
leaq .LC2(%rip), %rbx
movq %rbx, %rsi
call _Z10checkError9cudaErrorPKc
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $1004004, %esi
call cudaMalloc@PLT
movl %eax, %edi
movq %rbx, %rsi
call _Z10checkError9cudaErrorPKc
call clock@PLT
movq %rax, %r15
movl $10, %ebx
leaq .LC3(%rip), %r14
leaq .LC4(%rip), %r13
leaq .LC5(%rip), %r12
jmp .L27
.L26:
call cudaGetLastError@PLT
movl %eax, %edi
movq %r13, %rsi
call _Z10checkError9cudaErrorPKc
movl $2, %ecx
movl $1004004, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movq %r12, %rsi
call _Z10checkError9cudaErrorPKc
subl $1, %ebx
je .L36
.L27:
movl $1, %ecx
movl $1004004, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movq %r14, %rsi
call _Z10checkError9cudaErrorPKc
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L26
movl $1004004, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z45__device_stub__Z21computeConwayUniversePKcPcxPKcPcx
jmp .L26
.L36:
call clock@PLT
subq %r15, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC6(%rip), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
leaq .LC8(%rip), %rsi
call _Z10checkError9cudaErrorPKc
movq 8(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
leaq .LC9(%rip), %rsi
call _Z10checkError9cudaErrorPKc
movq %rbp, %rdi
call free@PLT
call cudaDeviceReset@PLT
movl %eax, %edi
leaq .LC10(%rip), %rsi
call _Z10checkError9cudaErrorPKc
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L37
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2072:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC11:
.string "_Z21computeConwayUniversePKcPcx"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2100:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z21computeConwayUniversePKcPcx(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2100:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC6:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "conway.hip"
.globl _Z36__device_stub__computeConwayUniversePKcPcx # -- Begin function _Z36__device_stub__computeConwayUniversePKcPcx
.p2align 4, 0x90
.type _Z36__device_stub__computeConwayUniversePKcPcx,@function
_Z36__device_stub__computeConwayUniversePKcPcx: # @_Z36__device_stub__computeConwayUniversePKcPcx
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21computeConwayUniversePKcPcx, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z36__device_stub__computeConwayUniversePKcPcx, .Lfunc_end0-_Z36__device_stub__computeConwayUniversePKcPcx
.cfi_endproc
# -- End function
.globl _Z10checkError10hipError_tPKc # -- Begin function _Z10checkError10hipError_tPKc
.p2align 4, 0x90
.type _Z10checkError10hipError_tPKc,@function
_Z10checkError10hipError_tPKc: # @_Z10checkError10hipError_tPKc
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB1_2
# %bb.1:
retq
.LBB1_2:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq stderr(%rip), %rbx
movq %rsi, %r14
callq hipGetErrorString
movq %rbx, %rdi
movq %r14, %rsi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z10checkError10hipError_tPKc, .Lfunc_end1-_Z10checkError10hipError_tPKc
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl $.L.str, %edi
movl $1000, %esi # imm = 0x3E8
movl $1000, %edx # imm = 0x3E8
movl $1, %ecx
movl $256, %r8d # imm = 0x100
movl $10, %r9d
xorl %eax, %eax
callq printf
movl $1004004, %edi # imm = 0xF51E4
callq malloc
testq %rax, %rax
je .LBB2_28
# %bb.1: # %.preheader.preheader
movq %rax, %rbx
xorl %r14d, %r14d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_6: # in Loop: Header=BB2_2 Depth=1
movb %al, (%rbx,%r14)
incq %r14
cmpq $1004004, %r14 # imm = 0xF51E4
je .LBB2_7
.LBB2_2: # %.preheader
# =>This Inner Loop Header: Depth=1
leal -1003002(%r14), %ecx
movb $66, %al
cmpl $-1002000, %ecx # imm = 0xFFF0B5F0
jb .LBB2_6
# %bb.3: # in Loop: Header=BB2_2 Depth=1
movl %r14d, %ecx
imulq $548658497, %rcx, %rcx # imm = 0x20B3DD41
shrq $39, %rcx
imull $-1002, %ecx, %ecx # imm = 0xFC16
addl %r14d, %ecx
je .LBB2_6
# %bb.4: # in Loop: Header=BB2_2 Depth=1
cmpl $1001, %ecx # imm = 0x3E9
je .LBB2_6
# %bb.5: # in Loop: Header=BB2_2 Depth=1
callq rand
xorl %ecx, %ecx
testb $1, %al
setne %cl
leal (%rcx,%rcx,2), %eax
addl $32, %eax
jmp .LBB2_6
.LBB2_7:
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $1004004, %esi # imm = 0xF51E4
callq hipMalloc
testl %eax, %eax
jne .LBB2_8
# %bb.10: # %_Z10checkError10hipError_tPKc.exit
movq $0, (%rsp)
movq %rsp, %rdi
movl $1004004, %esi # imm = 0xF51E4
callq hipMalloc
testl %eax, %eax
jne .LBB2_8
# %bb.11: # %_Z10checkError10hipError_tPKc.exit42
movabsq $4294967297, %r15 # imm = 0x100000001
movl $10, %r14d
callq clock
movq %rax, 16(%rsp) # 8-byte Spill
leaq 255(%r15), %r12
leaq 24(%rsp), %r13
leaq 96(%rsp), %rbp
.p2align 4, 0x90
.LBB2_12: # =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rdi
movl $1004004, %edx # imm = 0xF51E4
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_13
# %bb.22: # %_Z10checkError10hipError_tPKc.exit50
# in Loop: Header=BB2_12 Depth=1
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_24
# %bb.23: # in Loop: Header=BB2_12 Depth=1
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq $1004004, 72(%rsp) # imm = 0xF51E4
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z21computeConwayUniversePKcPcx, %edi
movq %rbp, %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_24: # in Loop: Header=BB2_12 Depth=1
callq hipGetLastError
testl %eax, %eax
jne .LBB2_25
# %bb.26: # %_Z10checkError10hipError_tPKc.exit52
# in Loop: Header=BB2_12 Depth=1
movq (%rsp), %rsi
movl $1004004, %edx # imm = 0xF51E4
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_27
# %bb.14: # in Loop: Header=BB2_12 Depth=1
decl %r14d
jne .LBB2_12
# %bb.15:
callq clock
subq 16(%rsp), %rax # 8-byte Folded Reload
cvtsi2sd %rax, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_16
# %bb.17: # %_Z10checkError10hipError_tPKc.exit44
movq (%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_18
# %bb.19: # %_Z10checkError10hipError_tPKc.exit46
movq %rbx, %rdi
callq free
callq hipDeviceReset
testl %eax, %eax
jne .LBB2_20
# %bb.21: # %_Z10checkError10hipError_tPKc.exit48
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_27:
.cfi_def_cfa_offset 176
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
jmp .LBB2_9
.LBB2_25:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %esi
jmp .LBB2_9
.LBB2_13:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
.LBB2_9:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB2_8:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
jmp .LBB2_9
.LBB2_28:
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $36, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.LBB2_16:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %esi
jmp .LBB2_9
.LBB2_18:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
jmp .LBB2_9
.LBB2_20:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.9, %esi
jmp .LBB2_9
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21computeConwayUniversePKcPcx, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21computeConwayUniversePKcPcx,@object # @_Z21computeConwayUniversePKcPcx
.section .rodata,"a",@progbits
.globl _Z21computeConwayUniversePKcPcx
.p2align 3, 0x0
_Z21computeConwayUniversePKcPcx:
.quad _Z36__device_stub__computeConwayUniversePKcPcx
.size _Z21computeConwayUniversePKcPcx, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "[Universe of size %d x %d (%d blocks with %d threads, %d steps)]\n"
.size .L.str, 66
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Failed to allocate host h_universe!\n"
.size .L.str.1, 37
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Failed to allocate device universe (error code %s)!\n"
.size .L.str.2, 53
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Failed to copy universe from host to device (error code %s)!\n"
.size .L.str.3, 62
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Failed to launch Conway kernel (error code %s)!\n"
.size .L.str.4, 49
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Failed to copy universe from device to host (error code %s)!\n"
.size .L.str.5, 62
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Computations took %f s\n"
.size .L.str.6, 24
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Failed to free device in universe (error code %s)!\n"
.size .L.str.7, 52
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Failed to free device out universe (error code %s)!\n"
.size .L.str.8, 53
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Failed to deinitialize the device! error=%s\n"
.size .L.str.9, 45
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z21computeConwayUniversePKcPcx"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__computeConwayUniversePKcPcx
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21computeConwayUniversePKcPcx
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __device__ void rgb_hsv_single(unsigned char rc, unsigned char gc, unsigned char bc, float *h, float *s, float *v)
{
// Adapted and simplified from https://github.com/jakebesworth/Simple-Color-Conversions
float min, max, delta;
float r, g, b;
r = (float) rc / 255.0;
g = (float) gc / 255.0;
b = (float) bc / 255.0;
min = r < g ? r : g;
min = min < b ? min : b;
max = r > g ? r : g;
max = max > b ? max : b;
delta = max - min;
*v = max;
*s = max < 0.0001 ? 0 : delta / max;
if(*s < 0.001) *h = 0;
else if(r == max) *h = g == min ? 5 + (max - b) / delta : 1 - (max - g) / delta;
else if(g == max) *h = b == min ? 1 + (max - r) / delta : 3 - (max - b) / delta;
else if(b == max && r == min) *h = 3 + (max - g) / delta;
else *h = 5 - (max - r) / delta;
*h /= 6;
*h = *h < 1 ? *h : 1;
}
__global__ void rgb_hsv(unsigned char *img, float *result, int width, int height)
{
int y = blockIdx.y * blockDim.y + threadIdx.y;
int x = blockIdx.x * blockDim.x + threadIdx.x;
if (x < width && y < height) {
int idx = (x + y * width) * 3;
rgb_hsv_single(img[idx], img[idx + 1], img[idx + 2], &result[idx], &result[idx + 1], &result[idx + 2]);
}
} | .file "tmpxft_00149625_00000000-6_rgb2hsv.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14rgb_hsv_singlehhhPfS_S_
.type _Z14rgb_hsv_singlehhhPfS_S_, @function
_Z14rgb_hsv_singlehhhPfS_S_:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z14rgb_hsv_singlehhhPfS_S_, .-_Z14rgb_hsv_singlehhhPfS_S_
.globl _Z30__device_stub__Z7rgb_hsvPhPfiiPhPfii
.type _Z30__device_stub__Z7rgb_hsvPhPfiiPhPfii, @function
_Z30__device_stub__Z7rgb_hsvPhPfiiPhPfii:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7rgb_hsvPhPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z30__device_stub__Z7rgb_hsvPhPfiiPhPfii, .-_Z30__device_stub__Z7rgb_hsvPhPfiiPhPfii
.globl _Z7rgb_hsvPhPfii
.type _Z7rgb_hsvPhPfii, @function
_Z7rgb_hsvPhPfii:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7rgb_hsvPhPfiiPhPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z7rgb_hsvPhPfii, .-_Z7rgb_hsvPhPfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7rgb_hsvPhPfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7rgb_hsvPhPfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __device__ void rgb_hsv_single(unsigned char rc, unsigned char gc, unsigned char bc, float *h, float *s, float *v)
{
// Adapted and simplified from https://github.com/jakebesworth/Simple-Color-Conversions
float min, max, delta;
float r, g, b;
r = (float) rc / 255.0;
g = (float) gc / 255.0;
b = (float) bc / 255.0;
min = r < g ? r : g;
min = min < b ? min : b;
max = r > g ? r : g;
max = max > b ? max : b;
delta = max - min;
*v = max;
*s = max < 0.0001 ? 0 : delta / max;
if(*s < 0.001) *h = 0;
else if(r == max) *h = g == min ? 5 + (max - b) / delta : 1 - (max - g) / delta;
else if(g == max) *h = b == min ? 1 + (max - r) / delta : 3 - (max - b) / delta;
else if(b == max && r == min) *h = 3 + (max - g) / delta;
else *h = 5 - (max - r) / delta;
*h /= 6;
*h = *h < 1 ? *h : 1;
}
__global__ void rgb_hsv(unsigned char *img, float *result, int width, int height)
{
int y = blockIdx.y * blockDim.y + threadIdx.y;
int x = blockIdx.x * blockDim.x + threadIdx.x;
if (x < width && y < height) {
int idx = (x + y * width) * 3;
rgb_hsv_single(img[idx], img[idx + 1], img[idx + 2], &result[idx], &result[idx + 1], &result[idx + 2]);
}
} | #include <hip/hip_runtime.h>
__device__ void rgb_hsv_single(unsigned char rc, unsigned char gc, unsigned char bc, float *h, float *s, float *v)
{
// Adapted and simplified from https://github.com/jakebesworth/Simple-Color-Conversions
float min, max, delta;
float r, g, b;
r = (float) rc / 255.0;
g = (float) gc / 255.0;
b = (float) bc / 255.0;
min = r < g ? r : g;
min = min < b ? min : b;
max = r > g ? r : g;
max = max > b ? max : b;
delta = max - min;
*v = max;
*s = max < 0.0001 ? 0 : delta / max;
if(*s < 0.001) *h = 0;
else if(r == max) *h = g == min ? 5 + (max - b) / delta : 1 - (max - g) / delta;
else if(g == max) *h = b == min ? 1 + (max - r) / delta : 3 - (max - b) / delta;
else if(b == max && r == min) *h = 3 + (max - g) / delta;
else *h = 5 - (max - r) / delta;
*h /= 6;
*h = *h < 1 ? *h : 1;
}
__global__ void rgb_hsv(unsigned char *img, float *result, int width, int height)
{
int y = blockIdx.y * blockDim.y + threadIdx.y;
int x = blockIdx.x * blockDim.x + threadIdx.x;
if (x < width && y < height) {
int idx = (x + y * width) * 3;
rgb_hsv_single(img[idx], img[idx + 1], img[idx + 2], &result[idx], &result[idx + 1], &result[idx + 2]);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__device__ void rgb_hsv_single(unsigned char rc, unsigned char gc, unsigned char bc, float *h, float *s, float *v)
{
// Adapted and simplified from https://github.com/jakebesworth/Simple-Color-Conversions
float min, max, delta;
float r, g, b;
r = (float) rc / 255.0;
g = (float) gc / 255.0;
b = (float) bc / 255.0;
min = r < g ? r : g;
min = min < b ? min : b;
max = r > g ? r : g;
max = max > b ? max : b;
delta = max - min;
*v = max;
*s = max < 0.0001 ? 0 : delta / max;
if(*s < 0.001) *h = 0;
else if(r == max) *h = g == min ? 5 + (max - b) / delta : 1 - (max - g) / delta;
else if(g == max) *h = b == min ? 1 + (max - r) / delta : 3 - (max - b) / delta;
else if(b == max && r == min) *h = 3 + (max - g) / delta;
else *h = 5 - (max - r) / delta;
*h /= 6;
*h = *h < 1 ? *h : 1;
}
__global__ void rgb_hsv(unsigned char *img, float *result, int width, int height)
{
int y = blockIdx.y * blockDim.y + threadIdx.y;
int x = blockIdx.x * blockDim.x + threadIdx.x;
if (x < width && y < height) {
int idx = (x + y * width) * 3;
rgb_hsv_single(img[idx], img[idx + 1], img[idx + 2], &result[idx], &result[idx + 1], &result[idx + 2]);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7rgb_hsvPhPfii
.globl _Z7rgb_hsvPhPfii
.p2align 8
.type _Z7rgb_hsvPhPfii,@function
_Z7rgb_hsvPhPfii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s4, v0
v_cmp_gt_i32_e64 s2, s5, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_24
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v0, v2, 1, v2
v_add_nc_u32_e32 v9, 1, v0
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v11, 2, v0
s_delay_alu instid0(VALU_DEP_3)
v_ashrrev_i32_e32 v10, 31, v9
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v9
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v10, vcc_lo
v_ashrrev_i32_e32 v12, 31, v11
s_clause 0x1
global_load_u8 v6, v[2:3], off
global_load_u8 v4, v[4:5], off
v_add_co_u32 v2, vcc_lo, s0, v11
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v12, vcc_lo
global_load_u8 v7, v[2:3], off
s_waitcnt vmcnt(2)
v_cvt_f64_u32_e32 v[2:3], v6
s_waitcnt vmcnt(1)
v_cvt_f64_u32_e32 v[4:5], v4
s_waitcnt vmcnt(0)
v_cvt_f64_u32_e32 v[6:7], v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_scale_f64 v[13:14], null, 0x406fe000, 0x406fe000, v[2:3]
v_div_scale_f64 v[15:16], null, 0x406fe000, 0x406fe000, v[4:5]
v_div_scale_f64 v[31:32], vcc_lo, v[2:3], 0x406fe000, v[2:3]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_div_scale_f64 v[17:18], null, 0x406fe000, 0x406fe000, v[6:7]
v_rcp_f64_e32 v[19:20], v[13:14]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[21:22], v[15:16]
v_rcp_f64_e32 v[23:24], v[17:18]
s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_fma_f64 v[25:26], -v[13:14], v[19:20], 1.0
s_waitcnt_depctr 0xfff
v_fma_f64 v[27:28], -v[15:16], v[21:22], 1.0
v_fma_f64 v[29:30], -v[17:18], v[23:24], 1.0
v_fma_f64 v[19:20], v[19:20], v[25:26], v[19:20]
v_fma_f64 v[21:22], v[21:22], v[27:28], v[21:22]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[23:24], v[23:24], v[29:30], v[23:24]
v_fma_f64 v[25:26], -v[13:14], v[19:20], 1.0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[27:28], -v[15:16], v[21:22], 1.0
v_fma_f64 v[29:30], -v[17:18], v[23:24], 1.0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_fma_f64 v[19:20], v[19:20], v[25:26], v[19:20]
v_div_scale_f64 v[25:26], s0, v[4:5], 0x406fe000, v[4:5]
v_fma_f64 v[21:22], v[21:22], v[27:28], v[21:22]
v_div_scale_f64 v[27:28], s1, v[6:7], 0x406fe000, v[6:7]
v_fma_f64 v[23:24], v[23:24], v[29:30], v[23:24]
v_mul_f64 v[29:30], v[31:32], v[19:20]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[33:34], v[25:26], v[21:22]
v_mul_f64 v[35:36], v[27:28], v[23:24]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[13:14], -v[13:14], v[29:30], v[31:32]
v_fma_f64 v[15:16], -v[15:16], v[33:34], v[25:26]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[17:18], -v[17:18], v[35:36], v[27:28]
v_div_fmas_f64 v[13:14], v[13:14], v[19:20], v[29:30]
s_mov_b32 vcc_lo, s0
s_mov_b32 s0, 0xeb1c432d
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fmas_f64 v[15:16], v[15:16], v[21:22], v[33:34]
s_mov_b32 vcc_lo, s1
s_mov_b32 s1, 0x3f1a36e2
v_div_fmas_f64 v[17:18], v[17:18], v[23:24], v[35:36]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fixup_f64 v[2:3], v[13:14], 0x406fe000, v[2:3]
v_div_fixup_f64 v[4:5], v[15:16], 0x406fe000, v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fixup_f64 v[13:14], v[17:18], 0x406fe000, v[6:7]
v_cvt_f32_f64_e32 v6, v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f32_f64_e32 v7, v[4:5]
v_cvt_f32_f64_e32 v5, v[13:14]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_cmp_lt_f32_e32 vcc_lo, v6, v7
v_cndmask_b32_e32 v2, v7, v6, vcc_lo
v_cmp_gt_f32_e32 vcc_lo, v6, v7
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_cndmask_b32_e32 v3, v7, v6, vcc_lo
v_cmp_lt_f32_e32 vcc_lo, v2, v5
v_cndmask_b32_e32 v8, v5, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cmp_gt_f32_e32 vcc_lo, v3, v5
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_cndmask_b32_e32 v4, v5, v3, vcc_lo
v_sub_f32_e32 v2, v4, v8
v_cvt_f64_f32_e32 v[13:14], v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v3, null, v4, v4, v2
v_rcp_f32_e32 v15, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v16, -v3, v15, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v15, v16, v15
v_div_scale_f32 v16, vcc_lo, v2, v4, v2
v_mul_f32_e32 v17, v16, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v18, -v3, v17, v16
v_fmac_f32_e32 v17, v18, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, -v3, v17, v16
v_div_fmas_f32 v3, v3, v15, v17
v_cmp_ngt_f64_e32 vcc_lo, s[0:1], v[13:14]
s_mov_b32 s1, 0x3f50624d
s_mov_b32 s0, 0xd2f1a9fc
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v3, v3, v4, v2
v_cndmask_b32_e32 v15, 0, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[13:14], v15
v_cmp_ngt_f64_e32 vcc_lo, s[0:1], v[13:14]
v_add_co_u32 v11, s0, s2, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v12, s0, s3, v12, s0
v_add_co_u32 v9, s0, s2, v9
v_add_co_ci_u32_e64 v10, s0, s3, v10, s0
s_clause 0x1
global_store_b32 v[11:12], v4, off
global_store_b32 v[9:10], v15, off
s_and_saveexec_b32 s1, vcc_lo
s_cbranch_execz .LBB0_23
s_mov_b32 s0, exec_lo
v_cmpx_neq_f32_e32 v4, v6
s_xor_b32 s4, exec_lo, s0
s_cbranch_execz .LBB0_16
s_mov_b32 s0, exec_lo
v_cmpx_neq_f32_e32 v4, v7
s_xor_b32 s5, exec_lo, s0
s_cbranch_execz .LBB0_9
v_cmp_neq_f32_e32 vcc_lo, v4, v5
v_cmp_neq_f32_e64 s0, v8, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s6, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s6
s_cbranch_execz .LBB0_6
v_sub_f32_e32 v3, v4, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v4, null, v2, v2, v3
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, v3, v2, v3
v_mul_f32_e32 v7, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v4, v7, v6
v_fmac_f32_e32 v7, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v7, v6
v_div_fmas_f32 v4, v4, v5, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v2, v4, v2, v3
v_sub_f32_e32 v3, 0x40a00000, v2
.LBB0_6:
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB0_8
v_sub_f32_e32 v3, v4, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v4, null, v2, v2, v3
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, v3, v2, v3
v_mul_f32_e32 v7, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v4, v7, v6
v_fmac_f32_e32 v7, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v7, v6
v_div_fmas_f32 v4, v4, v5, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v2, v4, v2, v3
v_add_f32_e32 v3, 0x40400000, v2
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_9:
s_and_not1_saveexec_b32 s0, s5
s_cbranch_execz .LBB0_15
s_mov_b32 s5, exec_lo
v_cmpx_neq_f32_e32 v8, v5
s_xor_b32 s5, exec_lo, s5
s_cbranch_execz .LBB0_12
v_sub_f32_e32 v3, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v4, null, v2, v2, v3
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, v3, v2, v3
v_mul_f32_e32 v7, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v4, v7, v6
v_fmac_f32_e32 v7, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v7, v6
v_div_fmas_f32 v4, v4, v5, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v2, v4, v2, v3
v_sub_f32_e32 v3, 0x40400000, v2
.LBB0_12:
s_and_not1_saveexec_b32 s5, s5
s_cbranch_execz .LBB0_14
v_sub_f32_e32 v3, v4, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v4, null, v2, v2, v3
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, v3, v2, v3
v_mul_f32_e32 v7, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v4, v7, v6
v_fmac_f32_e32 v7, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v7, v6
v_div_fmas_f32 v4, v4, v5, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v2, v4, v2, v3
v_add_f32_e32 v3, 1.0, v2
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s5
.LBB0_15:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s0
.LBB0_16:
s_and_not1_saveexec_b32 s0, s4
s_cbranch_execz .LBB0_22
s_mov_b32 s4, exec_lo
v_cmpx_neq_f32_e32 v8, v7
s_xor_b32 s4, exec_lo, s4
s_cbranch_execz .LBB0_19
v_sub_f32_e32 v3, v4, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v4, null, v2, v2, v3
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, v3, v2, v3
v_mul_f32_e32 v7, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v4, v7, v6
v_fmac_f32_e32 v7, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v7, v6
v_div_fmas_f32 v4, v4, v5, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v2, v4, v2, v3
v_sub_f32_e32 v3, 1.0, v2
.LBB0_19:
s_and_not1_saveexec_b32 s4, s4
s_cbranch_execz .LBB0_21
v_sub_f32_e32 v3, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v4, null, v2, v2, v3
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, v3, v2, v3
v_mul_f32_e32 v7, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v4, v7, v6
v_fmac_f32_e32 v7, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v7, v6
v_div_fmas_f32 v4, v4, v5, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v2, v4, v2, v3
v_add_f32_e32 v3, 0x40a00000, v2
.LBB0_21:
s_or_b32 exec_lo, exec_lo, s4
.LBB0_22:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s0
.LBB0_23:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s1
v_div_scale_f32 v2, null, 0x40c00000, 0x40c00000, v3
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v4, v2
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v2, v4, 1.0
v_fmac_f32_e32 v4, v5, v4
v_div_scale_f32 v5, vcc_lo, v3, 0x40c00000, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, v5, v4
v_fma_f32 v7, -v2, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v7, v4
v_fma_f32 v2, -v2, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fmas_f32 v2, v2, v4, v6
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_div_fixup_f32 v2, v2, 0x40c00000, v3
s_delay_alu instid0(VALU_DEP_1)
v_min_f32_e32 v2, 1.0, v2
global_store_b32 v[0:1], v2, off
.LBB0_24:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7rgb_hsvPhPfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 37
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7rgb_hsvPhPfii, .Lfunc_end0-_Z7rgb_hsvPhPfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7rgb_hsvPhPfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7rgb_hsvPhPfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 37
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__device__ void rgb_hsv_single(unsigned char rc, unsigned char gc, unsigned char bc, float *h, float *s, float *v)
{
// Adapted and simplified from https://github.com/jakebesworth/Simple-Color-Conversions
float min, max, delta;
float r, g, b;
r = (float) rc / 255.0;
g = (float) gc / 255.0;
b = (float) bc / 255.0;
min = r < g ? r : g;
min = min < b ? min : b;
max = r > g ? r : g;
max = max > b ? max : b;
delta = max - min;
*v = max;
*s = max < 0.0001 ? 0 : delta / max;
if(*s < 0.001) *h = 0;
else if(r == max) *h = g == min ? 5 + (max - b) / delta : 1 - (max - g) / delta;
else if(g == max) *h = b == min ? 1 + (max - r) / delta : 3 - (max - b) / delta;
else if(b == max && r == min) *h = 3 + (max - g) / delta;
else *h = 5 - (max - r) / delta;
*h /= 6;
*h = *h < 1 ? *h : 1;
}
__global__ void rgb_hsv(unsigned char *img, float *result, int width, int height)
{
int y = blockIdx.y * blockDim.y + threadIdx.y;
int x = blockIdx.x * blockDim.x + threadIdx.x;
if (x < width && y < height) {
int idx = (x + y * width) * 3;
rgb_hsv_single(img[idx], img[idx + 1], img[idx + 2], &result[idx], &result[idx + 1], &result[idx + 2]);
}
} | .text
.file "rgb2hsv.hip"
.globl _Z22__device_stub__rgb_hsvPhPfii # -- Begin function _Z22__device_stub__rgb_hsvPhPfii
.p2align 4, 0x90
.type _Z22__device_stub__rgb_hsvPhPfii,@function
_Z22__device_stub__rgb_hsvPhPfii: # @_Z22__device_stub__rgb_hsvPhPfii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7rgb_hsvPhPfii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__rgb_hsvPhPfii, .Lfunc_end0-_Z22__device_stub__rgb_hsvPhPfii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7rgb_hsvPhPfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7rgb_hsvPhPfii,@object # @_Z7rgb_hsvPhPfii
.section .rodata,"a",@progbits
.globl _Z7rgb_hsvPhPfii
.p2align 3, 0x0
_Z7rgb_hsvPhPfii:
.quad _Z22__device_stub__rgb_hsvPhPfii
.size _Z7rgb_hsvPhPfii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7rgb_hsvPhPfii"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__rgb_hsvPhPfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7rgb_hsvPhPfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00149625_00000000-6_rgb2hsv.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14rgb_hsv_singlehhhPfS_S_
.type _Z14rgb_hsv_singlehhhPfS_S_, @function
_Z14rgb_hsv_singlehhhPfS_S_:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z14rgb_hsv_singlehhhPfS_S_, .-_Z14rgb_hsv_singlehhhPfS_S_
.globl _Z30__device_stub__Z7rgb_hsvPhPfiiPhPfii
.type _Z30__device_stub__Z7rgb_hsvPhPfiiPhPfii, @function
_Z30__device_stub__Z7rgb_hsvPhPfiiPhPfii:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7rgb_hsvPhPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z30__device_stub__Z7rgb_hsvPhPfiiPhPfii, .-_Z30__device_stub__Z7rgb_hsvPhPfiiPhPfii
.globl _Z7rgb_hsvPhPfii
.type _Z7rgb_hsvPhPfii, @function
_Z7rgb_hsvPhPfii:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7rgb_hsvPhPfiiPhPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z7rgb_hsvPhPfii, .-_Z7rgb_hsvPhPfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7rgb_hsvPhPfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7rgb_hsvPhPfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "rgb2hsv.hip"
.globl _Z22__device_stub__rgb_hsvPhPfii # -- Begin function _Z22__device_stub__rgb_hsvPhPfii
.p2align 4, 0x90
.type _Z22__device_stub__rgb_hsvPhPfii,@function
_Z22__device_stub__rgb_hsvPhPfii: # @_Z22__device_stub__rgb_hsvPhPfii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7rgb_hsvPhPfii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__rgb_hsvPhPfii, .Lfunc_end0-_Z22__device_stub__rgb_hsvPhPfii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7rgb_hsvPhPfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7rgb_hsvPhPfii,@object # @_Z7rgb_hsvPhPfii
.section .rodata,"a",@progbits
.globl _Z7rgb_hsvPhPfii
.p2align 3, 0x0
_Z7rgb_hsvPhPfii:
.quad _Z22__device_stub__rgb_hsvPhPfii
.size _Z7rgb_hsvPhPfii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7rgb_hsvPhPfii"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__rgb_hsvPhPfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7rgb_hsvPhPfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <stdio.h>
#include <sys/time.h>
#define BLOCK_SIZE 16
__global__ void lud_diagonal(float *m, int matrix_dim, int offset)
{
int i,j;
__shared__ float shadow[BLOCK_SIZE][BLOCK_SIZE];
/* Each thread block, i.e. 1D 16 threads, loads a
* 2D block, i.e. 16x16, of data from the diagonal
* of the matrix into shared memory 'shadow' */
int array_offset = offset*matrix_dim+offset;
for(i = 0; i < BLOCK_SIZE; i++){
shadow[i][threadIdx.x] = m[array_offset+threadIdx.x];
array_offset += matrix_dim;
}
__syncthreads();
for(i = 0; i < BLOCK_SIZE-1; i++) {
if ( threadIdx.x > i) { /* starts at 15 threads and then decrease one thread each time */
for(j = 0; j < i; j++) { /* This for loop computes cols */
shadow[threadIdx.x][i] -= shadow[threadIdx.x][j]*shadow[j][i];
}
shadow[threadIdx.x][i] /= shadow[i][i];
}
__syncthreads();
if ( threadIdx.x > i) {
for( j = 0; j < i+1; j++) { /* This for loop computes rows */
shadow[i+1][threadIdx.x] -= shadow[i+1][j]*shadow[j][threadIdx.x];
}
}
__syncthreads();
}
/* The first row is not modified, it
* is no need to write it back to the
* global memory */
array_offset = (offset+1)*matrix_dim+offset;
for(i = 1; i < BLOCK_SIZE; i++) {
m[array_offset+threadIdx.x] = shadow[i][threadIdx.x];
array_offset += matrix_dim;
}
}
__global__ void lud_diagonal_noshr(float *m, int matrix_dim, int offset)
{
int i,j;
int array_offset = offset*matrix_dim+offset;
for(i = 0; i < BLOCK_SIZE-1; i++) {
if ( threadIdx.x > i) { /* starts at 15 threads and then decrease one thread each time */
for(j = 0; j < i; j++) { /* This for loop computes cols */
m[(array_offset+threadIdx.x*matrix_dim) + i] -=
m[(array_offset+threadIdx.x*matrix_dim) + j]*
m[(array_offset+j*matrix_dim) + i];
}
m[(array_offset+threadIdx.x*matrix_dim) + i] /= m[(array_offset+i*matrix_dim) + i];
}
__syncthreads();
if ( threadIdx.x > i) {
for( j = 0; j < i+1; j++) { /* This for loop computes rows */
m[(array_offset+(i+1)*matrix_dim) + threadIdx.x] -=
m[(array_offset+(i+1)*matrix_dim) + j]*
m[(array_offset+j*matrix_dim) + threadIdx.x];
}
}
__syncthreads();
}
}
__global__ void lud_perimeter(float *m, int matrix_dim, int offset)
{
__shared__ float dia[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float peri_row[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float peri_col[BLOCK_SIZE][BLOCK_SIZE];
int i,j, array_offset;
int idx;
/* For this kernel, each block contains 32 threads */
if ( threadIdx.x < BLOCK_SIZE) { /* threads 0 ... 15 */
idx = threadIdx.x;
array_offset = offset*matrix_dim+offset;
for (i=0; i < BLOCK_SIZE/2; i++){
dia[i][idx]=m[array_offset+idx];
array_offset += matrix_dim;
}
array_offset = offset*matrix_dim+offset;
for (i=0; i < BLOCK_SIZE; i++) {
peri_row[i][idx]=m[array_offset+(blockIdx.x+1)*BLOCK_SIZE+idx];
array_offset += matrix_dim;
}
} else { /* threads 16 ... 31 */
idx = threadIdx.x-BLOCK_SIZE;
array_offset = (offset+BLOCK_SIZE/2)*matrix_dim+offset;
for (i=BLOCK_SIZE/2; i < BLOCK_SIZE; i++){
dia[i][idx]=m[array_offset+idx];
array_offset += matrix_dim;
}
array_offset = (offset+(blockIdx.x+1)*BLOCK_SIZE)*matrix_dim+offset;
for (i=0; i < BLOCK_SIZE; i++) {
peri_col[i][idx] = m[array_offset+idx];
array_offset += matrix_dim;
}
}
__syncthreads();
/* this version works ok on hardware, but not gpgpusim
**************************************************************
if (threadIdx.x < BLOCK_SIZE) { //peri-row
idx=threadIdx.x;
for(i=1; i < BLOCK_SIZE; i++){
for (j=0; j < i; j++)
peri_row[i][idx]-=dia[i][j]*peri_row[j][idx];
}
array_offset = (offset+1)*matrix_dim+offset;
for(i=1; i < BLOCK_SIZE; i++){
m[array_offset+(blockIdx.x+1)*BLOCK_SIZE+idx] = peri_row[i][idx];
array_offset += matrix_dim;
}
} else { //peri-col
idx=threadIdx.x - BLOCK_SIZE;
for(i=0; i < BLOCK_SIZE; i++){
for(j=0; j < i; j++)
peri_col[idx][i]-=peri_col[idx][j]*dia[j][i];
peri_col[idx][i] /= dia[i][i];
}
__syncthreads();
array_offset = (offset+(blockIdx.x+1)*BLOCK_SIZE)*matrix_dim+offset;
for(i=0; i < BLOCK_SIZE; i++){
m[array_offset+idx] = peri_col[i][idx];
array_offset += matrix_dim;
}
}
***************************************************************/
if (threadIdx.x < BLOCK_SIZE) { //peri-row
idx=threadIdx.x;
for(i=1; i < BLOCK_SIZE; i++){
for (j=0; j < i; j++) {
peri_row[i][idx]-=dia[i][j]*peri_row[j][idx];
}
}
} else { //peri-col
idx=threadIdx.x - BLOCK_SIZE;
for(i=0; i < BLOCK_SIZE; i++){
for(j=0; j < i; j++) {
peri_col[idx][i]-=peri_col[idx][j]*dia[j][i];
}
peri_col[idx][i] /= dia[i][i];
}
}
__syncthreads();
/* write data back to global memory */
if (threadIdx.x < BLOCK_SIZE) { //peri-row
idx=threadIdx.x;
array_offset = (offset+1)*matrix_dim+offset;
for(i=1; i < BLOCK_SIZE; i++){
m[array_offset+(blockIdx.x+1)*BLOCK_SIZE+idx] = peri_row[i][idx];
array_offset += matrix_dim;
}
} else { //peri-col
idx=threadIdx.x - BLOCK_SIZE;
array_offset = (offset+(blockIdx.x+1)*BLOCK_SIZE)*matrix_dim+offset;
for(i=0; i < BLOCK_SIZE; i++){
m[array_offset+idx] = peri_col[i][idx];
array_offset += matrix_dim;
}
}
}
__global__ void lud_perimeter_noshr(float *m, int matrix_dim, int offset)
{
int i,j, array_offset;
int idx;
if (threadIdx.x < BLOCK_SIZE) { //peri-row
array_offset = offset*matrix_dim+offset;
idx=threadIdx.x;
for(i=1; i < BLOCK_SIZE; i++){
for (j=0; j < i; j++) {
m[array_offset+i*matrix_dim+(blockIdx.x+1)*BLOCK_SIZE+idx] -=
m[array_offset+i*matrix_dim+j] * m[array_offset+j*matrix_dim+(blockIdx.x+1)*BLOCK_SIZE+idx];
}
}
} else { //peri-col
array_offset = (offset+(blockIdx.x+1)*BLOCK_SIZE)*matrix_dim+offset;
idx=threadIdx.x - BLOCK_SIZE;
for(i=0; i < BLOCK_SIZE; i++){
for(j=0; j < i; j++) {
m[array_offset+idx*matrix_dim+i] -= m[array_offset+idx*matrix_dim+j] * m[offset*matrix_dim+offset+j*matrix_dim+i];
}
m[array_offset+idx*matrix_dim+i] /= m[offset*matrix_dim+offset+i*matrix_dim+i];
}
}
}
__global__ void lud_internal(float *m, int matrix_dim, int offset)
{
__shared__ float peri_row[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float peri_col[BLOCK_SIZE][BLOCK_SIZE];
int i;
float sum;
int global_row_id = offset + (blockIdx.y+1)*BLOCK_SIZE;
int global_col_id = offset + (blockIdx.x+1)*BLOCK_SIZE;
peri_row[threadIdx.y][threadIdx.x] = m[(offset+threadIdx.y)*matrix_dim+global_col_id+threadIdx.x];
peri_col[threadIdx.y][threadIdx.x] = m[(global_row_id+threadIdx.y)*matrix_dim+offset+threadIdx.x];
__syncthreads();
sum = 0;
for (i=0; i < BLOCK_SIZE; i++) {
sum += peri_col[threadIdx.y][i] * peri_row[i][threadIdx.x];
}
m[(global_row_id+threadIdx.y)*matrix_dim+global_col_id+threadIdx.x] -= sum;
}
__global__ void lud_internal_noshr(float *m, int matrix_dim, int offset)
{
int i;
float sum;
int global_row_id = offset + (blockIdx.y+1)*BLOCK_SIZE;
int global_col_id = offset + (blockIdx.x+1)*BLOCK_SIZE;
sum = 0;
for (i=0; i < BLOCK_SIZE; i++) {
sum += m[(global_row_id+threadIdx.y)*matrix_dim+offset+i] * m[(offset+i)*matrix_dim+global_col_id+threadIdx.x];
}
m[(global_row_id+threadIdx.y)*matrix_dim+global_col_id+threadIdx.x] -= sum;
}
void lud_cuda(float *m, int matrix_dim, int do_shared)
{
int i=0;
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
/* beginning of timing point */
struct timeval tv1, tv2;
gettimeofday(&tv1, NULL);
if( do_shared) {
//printf("Executing kernels with shared memory!\n");
for (i=0; i < matrix_dim-BLOCK_SIZE; i += BLOCK_SIZE) {
lud_diagonal<<<1, BLOCK_SIZE>>>(m, matrix_dim, i);
lud_perimeter<<<(matrix_dim-i)/BLOCK_SIZE-1, BLOCK_SIZE*2>>>(m, matrix_dim, i);
dim3 dimGrid((matrix_dim-i)/BLOCK_SIZE-1, (matrix_dim-i)/BLOCK_SIZE-1);
lud_internal<<<dimGrid, dimBlock>>>(m, matrix_dim, i);
}
lud_diagonal<<<1,BLOCK_SIZE>>>(m, matrix_dim, i);
}
else {
//printf("Executing kernels without shared memory!\n");
cudaFuncSetCacheConfig("lud_diagonal_noshr", cudaFuncCachePreferL1);
cudaFuncSetCacheConfig("lud_perimeter_noshr", cudaFuncCachePreferL1);
cudaFuncSetCacheConfig("lud_internal_noshr", cudaFuncCachePreferL1);
for (i=0; i < matrix_dim-BLOCK_SIZE; i += BLOCK_SIZE) {
lud_diagonal_noshr<<<1, BLOCK_SIZE>>>(m, matrix_dim, i);
lud_perimeter_noshr<<<(matrix_dim-i)/BLOCK_SIZE-1, BLOCK_SIZE*2>>>(m, matrix_dim, i);
dim3 dimGrid((matrix_dim-i)/BLOCK_SIZE-1, (matrix_dim-i)/BLOCK_SIZE-1);
lud_internal_noshr<<<dimGrid, dimBlock>>>(m, matrix_dim, i);
}
lud_diagonal<<<1,BLOCK_SIZE>>>(m, matrix_dim, i);
}
/* end of timing point */
gettimeofday(&tv2, NULL);
double runtime = ((tv2.tv_sec*1000.0 + tv2.tv_usec/1000.0)-(tv1.tv_sec*1000.0 + tv1.tv_usec/1000.0));
printf("Runtime(milliseconds): %f\n", runtime);
} | .file "tmpxft_000b8930_00000000-6_lud_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z12lud_diagonalPfiiPfii
.type _Z34__device_stub__Z12lud_diagonalPfiiPfii, @function
_Z34__device_stub__Z12lud_diagonalPfiiPfii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12lud_diagonalPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z12lud_diagonalPfiiPfii, .-_Z34__device_stub__Z12lud_diagonalPfiiPfii
.globl _Z12lud_diagonalPfii
.type _Z12lud_diagonalPfii, @function
_Z12lud_diagonalPfii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z12lud_diagonalPfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12lud_diagonalPfii, .-_Z12lud_diagonalPfii
.globl _Z40__device_stub__Z18lud_diagonal_noshrPfiiPfii
.type _Z40__device_stub__Z18lud_diagonal_noshrPfiiPfii, @function
_Z40__device_stub__Z18lud_diagonal_noshrPfiiPfii:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z18lud_diagonal_noshrPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z40__device_stub__Z18lud_diagonal_noshrPfiiPfii, .-_Z40__device_stub__Z18lud_diagonal_noshrPfiiPfii
.globl _Z18lud_diagonal_noshrPfii
.type _Z18lud_diagonal_noshrPfii, @function
_Z18lud_diagonal_noshrPfii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z18lud_diagonal_noshrPfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z18lud_diagonal_noshrPfii, .-_Z18lud_diagonal_noshrPfii
.globl _Z35__device_stub__Z13lud_perimeterPfiiPfii
.type _Z35__device_stub__Z13lud_perimeterPfiiPfii, @function
_Z35__device_stub__Z13lud_perimeterPfiiPfii:
.LFB2086:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13lud_perimeterPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z35__device_stub__Z13lud_perimeterPfiiPfii, .-_Z35__device_stub__Z13lud_perimeterPfiiPfii
.globl _Z13lud_perimeterPfii
.type _Z13lud_perimeterPfii, @function
_Z13lud_perimeterPfii:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z13lud_perimeterPfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z13lud_perimeterPfii, .-_Z13lud_perimeterPfii
.globl _Z41__device_stub__Z19lud_perimeter_noshrPfiiPfii
.type _Z41__device_stub__Z19lud_perimeter_noshrPfiiPfii, @function
_Z41__device_stub__Z19lud_perimeter_noshrPfiiPfii:
.LFB2088:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z19lud_perimeter_noshrPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z41__device_stub__Z19lud_perimeter_noshrPfiiPfii, .-_Z41__device_stub__Z19lud_perimeter_noshrPfiiPfii
.globl _Z19lud_perimeter_noshrPfii
.type _Z19lud_perimeter_noshrPfii, @function
_Z19lud_perimeter_noshrPfii:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z19lud_perimeter_noshrPfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z19lud_perimeter_noshrPfii, .-_Z19lud_perimeter_noshrPfii
.globl _Z34__device_stub__Z12lud_internalPfiiPfii
.type _Z34__device_stub__Z12lud_internalPfiiPfii, @function
_Z34__device_stub__Z12lud_internalPfiiPfii:
.LFB2090:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12lud_internalPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z34__device_stub__Z12lud_internalPfiiPfii, .-_Z34__device_stub__Z12lud_internalPfiiPfii
.globl _Z12lud_internalPfii
.type _Z12lud_internalPfii, @function
_Z12lud_internalPfii:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z12lud_internalPfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z12lud_internalPfii, .-_Z12lud_internalPfii
.globl _Z40__device_stub__Z18lud_internal_noshrPfiiPfii
.type _Z40__device_stub__Z18lud_internal_noshrPfiiPfii, @function
_Z40__device_stub__Z18lud_internal_noshrPfiiPfii:
.LFB2092:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L47
.L43:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z18lud_internal_noshrPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L43
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2092:
.size _Z40__device_stub__Z18lud_internal_noshrPfiiPfii, .-_Z40__device_stub__Z18lud_internal_noshrPfiiPfii
.globl _Z18lud_internal_noshrPfii
.type _Z18lud_internal_noshrPfii, @function
_Z18lud_internal_noshrPfii:
.LFB2093:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z18lud_internal_noshrPfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _Z18lud_internal_noshrPfii, .-_Z18lud_internal_noshrPfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "lud_diagonal_noshr"
.LC1:
.string "lud_perimeter_noshr"
.LC2:
.string "lud_internal_noshr"
.LC4:
.string "Runtime(milliseconds): %f\n"
.text
.globl _Z8lud_cudaPfii
.type _Z8lud_cudaPfii, @function
_Z8lud_cudaPfii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %rdi, %r13
movl %esi, %r12d
movl %edx, %ebx
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $16, 24(%rsp)
movl $16, 28(%rsp)
movl $1, 32(%rsp)
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
testl %ebx, %ebx
je .L52
cmpl $16, %r12d
jle .L67
leal -17(%r12), %eax
movl %eax, 12(%rsp)
leal -16(%r12), %r15d
andl $-16, %eax
subl %eax, %r15d
movl %r12d, %ebp
jmp .L57
.L72:
movl %r14d, %edx
movl %r12d, %esi
movq %r13, %rdi
call _Z34__device_stub__Z12lud_diagonalPfiiPfii
jmp .L54
.L73:
movl %r14d, %edx
movl %r12d, %esi
movq %r13, %rdi
call _Z35__device_stub__Z13lud_perimeterPfiiPfii
jmp .L55
.L56:
subl $16, %ebp
cmpl %r15d, %ebp
je .L71
.L57:
movl %r12d, %r14d
subl %ebp, %r14d
movl $16, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L72
.L54:
movl $32, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
leal 15(%rbp), %ebx
testl %ebp, %ebp
cmovns %ebp, %ebx
sarl $4, %ebx
subl $1, %ebx
movl %ebx, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L73
.L55:
movl %ebx, 64(%rsp)
movl %ebx, 68(%rsp)
movl $1, 72(%rsp)
movl 32(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L56
movl %r14d, %edx
movl %r12d, %esi
movq %r13, %rdi
call _Z34__device_stub__Z12lud_internalPfiiPfii
jmp .L56
.L71:
movl 12(%rsp), %eax
andl $-16, %eax
leal 16(%rax), %ebx
.L53:
movl $16, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L74
.L59:
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 64(%rsp), %xmm0
movsd .LC3(%rip), %xmm2
mulsd %xmm2, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 72(%rsp), %xmm1
divsd %xmm2, %xmm1
addsd %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 48(%rsp), %xmm1
mulsd %xmm2, %xmm1
pxor %xmm3, %xmm3
cvtsi2sdq 56(%rsp), %xmm3
divsd %xmm2, %xmm3
addsd %xmm3, %xmm1
subsd %xmm1, %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L75
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L67:
.cfi_restore_state
movl $0, %ebx
jmp .L53
.L74:
movl %ebx, %edx
movl %r12d, %esi
movq %r13, %rdi
call _Z34__device_stub__Z12lud_diagonalPfiiPfii
jmp .L59
.L52:
movl $2, %esi
leaq .LC0(%rip), %rdi
call cudaFuncSetCacheConfig@PLT
movl $2, %esi
leaq .LC1(%rip), %rdi
call cudaFuncSetCacheConfig@PLT
movl $2, %esi
leaq .LC2(%rip), %rdi
call cudaFuncSetCacheConfig@PLT
cmpl $16, %r12d
jle .L60
leal -17(%r12), %eax
movl %eax, 12(%rsp)
leal -16(%r12), %r15d
andl $-16, %eax
subl %eax, %r15d
movl %r12d, %ebp
jmp .L64
.L77:
movl %r14d, %edx
movl %r12d, %esi
movq %r13, %rdi
call _Z40__device_stub__Z18lud_diagonal_noshrPfiiPfii
jmp .L61
.L78:
movl %r14d, %edx
movl %r12d, %esi
movq %r13, %rdi
call _Z41__device_stub__Z19lud_perimeter_noshrPfiiPfii
jmp .L62
.L79:
movl %r14d, %edx
movl %r12d, %esi
movq %r13, %rdi
call _Z40__device_stub__Z18lud_internal_noshrPfiiPfii
.L63:
subl $16, %ebp
cmpl %r15d, %ebp
je .L76
.L64:
movl %r12d, %r14d
subl %ebp, %r14d
movl $16, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L77
.L61:
movl $32, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
leal 15(%rbp), %ebx
testl %ebp, %ebp
cmovns %ebp, %ebx
sarl $4, %ebx
subl $1, %ebx
movl %ebx, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L78
.L62:
movl %ebx, 64(%rsp)
movl %ebx, 68(%rsp)
movl $1, 72(%rsp)
movl 32(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L63
jmp .L79
.L76:
movl 12(%rsp), %eax
andl $-16, %eax
leal 16(%rax), %ebx
.L60:
movl $16, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L59
movl %ebx, %edx
movl %r12d, %esi
movq %r13, %rdi
call _Z34__device_stub__Z12lud_diagonalPfiiPfii
jmp .L59
.L75:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z8lud_cudaPfii, .-_Z8lud_cudaPfii
.section .rodata.str1.1
.LC5:
.string "_Z18lud_internal_noshrPfii"
.LC6:
.string "_Z12lud_internalPfii"
.LC7:
.string "_Z19lud_perimeter_noshrPfii"
.LC8:
.string "_Z13lud_perimeterPfii"
.LC9:
.string "_Z18lud_diagonal_noshrPfii"
.LC10:
.string "_Z12lud_diagonalPfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2095:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z18lud_internal_noshrPfii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z12lud_internalPfii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z19lud_perimeter_noshrPfii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z13lud_perimeterPfii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z18lud_diagonal_noshrPfii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z12lud_diagonalPfii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2095:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <stdio.h>
#include <sys/time.h>
#define BLOCK_SIZE 16
__global__ void lud_diagonal(float *m, int matrix_dim, int offset)
{
int i,j;
__shared__ float shadow[BLOCK_SIZE][BLOCK_SIZE];
/* Each thread block, i.e. 1D 16 threads, loads a
* 2D block, i.e. 16x16, of data from the diagonal
* of the matrix into shared memory 'shadow' */
int array_offset = offset*matrix_dim+offset;
for(i = 0; i < BLOCK_SIZE; i++){
shadow[i][threadIdx.x] = m[array_offset+threadIdx.x];
array_offset += matrix_dim;
}
__syncthreads();
for(i = 0; i < BLOCK_SIZE-1; i++) {
if ( threadIdx.x > i) { /* starts at 15 threads and then decrease one thread each time */
for(j = 0; j < i; j++) { /* This for loop computes cols */
shadow[threadIdx.x][i] -= shadow[threadIdx.x][j]*shadow[j][i];
}
shadow[threadIdx.x][i] /= shadow[i][i];
}
__syncthreads();
if ( threadIdx.x > i) {
for( j = 0; j < i+1; j++) { /* This for loop computes rows */
shadow[i+1][threadIdx.x] -= shadow[i+1][j]*shadow[j][threadIdx.x];
}
}
__syncthreads();
}
/* The first row is not modified, it
* is no need to write it back to the
* global memory */
array_offset = (offset+1)*matrix_dim+offset;
for(i = 1; i < BLOCK_SIZE; i++) {
m[array_offset+threadIdx.x] = shadow[i][threadIdx.x];
array_offset += matrix_dim;
}
}
__global__ void lud_diagonal_noshr(float *m, int matrix_dim, int offset)
{
int i,j;
int array_offset = offset*matrix_dim+offset;
for(i = 0; i < BLOCK_SIZE-1; i++) {
if ( threadIdx.x > i) { /* starts at 15 threads and then decrease one thread each time */
for(j = 0; j < i; j++) { /* This for loop computes cols */
m[(array_offset+threadIdx.x*matrix_dim) + i] -=
m[(array_offset+threadIdx.x*matrix_dim) + j]*
m[(array_offset+j*matrix_dim) + i];
}
m[(array_offset+threadIdx.x*matrix_dim) + i] /= m[(array_offset+i*matrix_dim) + i];
}
__syncthreads();
if ( threadIdx.x > i) {
for( j = 0; j < i+1; j++) { /* This for loop computes rows */
m[(array_offset+(i+1)*matrix_dim) + threadIdx.x] -=
m[(array_offset+(i+1)*matrix_dim) + j]*
m[(array_offset+j*matrix_dim) + threadIdx.x];
}
}
__syncthreads();
}
}
__global__ void lud_perimeter(float *m, int matrix_dim, int offset)
{
__shared__ float dia[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float peri_row[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float peri_col[BLOCK_SIZE][BLOCK_SIZE];
int i,j, array_offset;
int idx;
/* For this kernel, each block contains 32 threads */
if ( threadIdx.x < BLOCK_SIZE) { /* threads 0 ... 15 */
idx = threadIdx.x;
array_offset = offset*matrix_dim+offset;
for (i=0; i < BLOCK_SIZE/2; i++){
dia[i][idx]=m[array_offset+idx];
array_offset += matrix_dim;
}
array_offset = offset*matrix_dim+offset;
for (i=0; i < BLOCK_SIZE; i++) {
peri_row[i][idx]=m[array_offset+(blockIdx.x+1)*BLOCK_SIZE+idx];
array_offset += matrix_dim;
}
} else { /* threads 16 ... 31 */
idx = threadIdx.x-BLOCK_SIZE;
array_offset = (offset+BLOCK_SIZE/2)*matrix_dim+offset;
for (i=BLOCK_SIZE/2; i < BLOCK_SIZE; i++){
dia[i][idx]=m[array_offset+idx];
array_offset += matrix_dim;
}
array_offset = (offset+(blockIdx.x+1)*BLOCK_SIZE)*matrix_dim+offset;
for (i=0; i < BLOCK_SIZE; i++) {
peri_col[i][idx] = m[array_offset+idx];
array_offset += matrix_dim;
}
}
__syncthreads();
/* this version works ok on hardware, but not gpgpusim
**************************************************************
if (threadIdx.x < BLOCK_SIZE) { //peri-row
idx=threadIdx.x;
for(i=1; i < BLOCK_SIZE; i++){
for (j=0; j < i; j++)
peri_row[i][idx]-=dia[i][j]*peri_row[j][idx];
}
array_offset = (offset+1)*matrix_dim+offset;
for(i=1; i < BLOCK_SIZE; i++){
m[array_offset+(blockIdx.x+1)*BLOCK_SIZE+idx] = peri_row[i][idx];
array_offset += matrix_dim;
}
} else { //peri-col
idx=threadIdx.x - BLOCK_SIZE;
for(i=0; i < BLOCK_SIZE; i++){
for(j=0; j < i; j++)
peri_col[idx][i]-=peri_col[idx][j]*dia[j][i];
peri_col[idx][i] /= dia[i][i];
}
__syncthreads();
array_offset = (offset+(blockIdx.x+1)*BLOCK_SIZE)*matrix_dim+offset;
for(i=0; i < BLOCK_SIZE; i++){
m[array_offset+idx] = peri_col[i][idx];
array_offset += matrix_dim;
}
}
***************************************************************/
if (threadIdx.x < BLOCK_SIZE) { //peri-row
idx=threadIdx.x;
for(i=1; i < BLOCK_SIZE; i++){
for (j=0; j < i; j++) {
peri_row[i][idx]-=dia[i][j]*peri_row[j][idx];
}
}
} else { //peri-col
idx=threadIdx.x - BLOCK_SIZE;
for(i=0; i < BLOCK_SIZE; i++){
for(j=0; j < i; j++) {
peri_col[idx][i]-=peri_col[idx][j]*dia[j][i];
}
peri_col[idx][i] /= dia[i][i];
}
}
__syncthreads();
/* write data back to global memory */
if (threadIdx.x < BLOCK_SIZE) { //peri-row
idx=threadIdx.x;
array_offset = (offset+1)*matrix_dim+offset;
for(i=1; i < BLOCK_SIZE; i++){
m[array_offset+(blockIdx.x+1)*BLOCK_SIZE+idx] = peri_row[i][idx];
array_offset += matrix_dim;
}
} else { //peri-col
idx=threadIdx.x - BLOCK_SIZE;
array_offset = (offset+(blockIdx.x+1)*BLOCK_SIZE)*matrix_dim+offset;
for(i=0; i < BLOCK_SIZE; i++){
m[array_offset+idx] = peri_col[i][idx];
array_offset += matrix_dim;
}
}
}
__global__ void lud_perimeter_noshr(float *m, int matrix_dim, int offset)
{
int i,j, array_offset;
int idx;
if (threadIdx.x < BLOCK_SIZE) { //peri-row
array_offset = offset*matrix_dim+offset;
idx=threadIdx.x;
for(i=1; i < BLOCK_SIZE; i++){
for (j=0; j < i; j++) {
m[array_offset+i*matrix_dim+(blockIdx.x+1)*BLOCK_SIZE+idx] -=
m[array_offset+i*matrix_dim+j] * m[array_offset+j*matrix_dim+(blockIdx.x+1)*BLOCK_SIZE+idx];
}
}
} else { //peri-col
array_offset = (offset+(blockIdx.x+1)*BLOCK_SIZE)*matrix_dim+offset;
idx=threadIdx.x - BLOCK_SIZE;
for(i=0; i < BLOCK_SIZE; i++){
for(j=0; j < i; j++) {
m[array_offset+idx*matrix_dim+i] -= m[array_offset+idx*matrix_dim+j] * m[offset*matrix_dim+offset+j*matrix_dim+i];
}
m[array_offset+idx*matrix_dim+i] /= m[offset*matrix_dim+offset+i*matrix_dim+i];
}
}
}
__global__ void lud_internal(float *m, int matrix_dim, int offset)
{
__shared__ float peri_row[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float peri_col[BLOCK_SIZE][BLOCK_SIZE];
int i;
float sum;
int global_row_id = offset + (blockIdx.y+1)*BLOCK_SIZE;
int global_col_id = offset + (blockIdx.x+1)*BLOCK_SIZE;
peri_row[threadIdx.y][threadIdx.x] = m[(offset+threadIdx.y)*matrix_dim+global_col_id+threadIdx.x];
peri_col[threadIdx.y][threadIdx.x] = m[(global_row_id+threadIdx.y)*matrix_dim+offset+threadIdx.x];
__syncthreads();
sum = 0;
for (i=0; i < BLOCK_SIZE; i++) {
sum += peri_col[threadIdx.y][i] * peri_row[i][threadIdx.x];
}
m[(global_row_id+threadIdx.y)*matrix_dim+global_col_id+threadIdx.x] -= sum;
}
__global__ void lud_internal_noshr(float *m, int matrix_dim, int offset)
{
int i;
float sum;
int global_row_id = offset + (blockIdx.y+1)*BLOCK_SIZE;
int global_col_id = offset + (blockIdx.x+1)*BLOCK_SIZE;
sum = 0;
for (i=0; i < BLOCK_SIZE; i++) {
sum += m[(global_row_id+threadIdx.y)*matrix_dim+offset+i] * m[(offset+i)*matrix_dim+global_col_id+threadIdx.x];
}
m[(global_row_id+threadIdx.y)*matrix_dim+global_col_id+threadIdx.x] -= sum;
}
void lud_cuda(float *m, int matrix_dim, int do_shared)
{
int i=0;
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
/* beginning of timing point */
struct timeval tv1, tv2;
gettimeofday(&tv1, NULL);
if( do_shared) {
//printf("Executing kernels with shared memory!\n");
for (i=0; i < matrix_dim-BLOCK_SIZE; i += BLOCK_SIZE) {
lud_diagonal<<<1, BLOCK_SIZE>>>(m, matrix_dim, i);
lud_perimeter<<<(matrix_dim-i)/BLOCK_SIZE-1, BLOCK_SIZE*2>>>(m, matrix_dim, i);
dim3 dimGrid((matrix_dim-i)/BLOCK_SIZE-1, (matrix_dim-i)/BLOCK_SIZE-1);
lud_internal<<<dimGrid, dimBlock>>>(m, matrix_dim, i);
}
lud_diagonal<<<1,BLOCK_SIZE>>>(m, matrix_dim, i);
}
else {
//printf("Executing kernels without shared memory!\n");
cudaFuncSetCacheConfig("lud_diagonal_noshr", cudaFuncCachePreferL1);
cudaFuncSetCacheConfig("lud_perimeter_noshr", cudaFuncCachePreferL1);
cudaFuncSetCacheConfig("lud_internal_noshr", cudaFuncCachePreferL1);
for (i=0; i < matrix_dim-BLOCK_SIZE; i += BLOCK_SIZE) {
lud_diagonal_noshr<<<1, BLOCK_SIZE>>>(m, matrix_dim, i);
lud_perimeter_noshr<<<(matrix_dim-i)/BLOCK_SIZE-1, BLOCK_SIZE*2>>>(m, matrix_dim, i);
dim3 dimGrid((matrix_dim-i)/BLOCK_SIZE-1, (matrix_dim-i)/BLOCK_SIZE-1);
lud_internal_noshr<<<dimGrid, dimBlock>>>(m, matrix_dim, i);
}
lud_diagonal<<<1,BLOCK_SIZE>>>(m, matrix_dim, i);
}
/* end of timing point */
gettimeofday(&tv2, NULL);
double runtime = ((tv2.tv_sec*1000.0 + tv2.tv_usec/1000.0)-(tv1.tv_sec*1000.0 + tv1.tv_usec/1000.0));
printf("Runtime(milliseconds): %f\n", runtime);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <sys/time.h>
#define BLOCK_SIZE 16
__global__ void lud_diagonal(float *m, int matrix_dim, int offset)
{
int i,j;
__shared__ float shadow[BLOCK_SIZE][BLOCK_SIZE];
/* Each thread block, i.e. 1D 16 threads, loads a
* 2D block, i.e. 16x16, of data from the diagonal
* of the matrix into shared memory 'shadow' */
int array_offset = offset*matrix_dim+offset;
for(i = 0; i < BLOCK_SIZE; i++){
shadow[i][threadIdx.x] = m[array_offset+threadIdx.x];
array_offset += matrix_dim;
}
__syncthreads();
for(i = 0; i < BLOCK_SIZE-1; i++) {
if ( threadIdx.x > i) { /* starts at 15 threads and then decrease one thread each time */
for(j = 0; j < i; j++) { /* This for loop computes cols */
shadow[threadIdx.x][i] -= shadow[threadIdx.x][j]*shadow[j][i];
}
shadow[threadIdx.x][i] /= shadow[i][i];
}
__syncthreads();
if ( threadIdx.x > i) {
for( j = 0; j < i+1; j++) { /* This for loop computes rows */
shadow[i+1][threadIdx.x] -= shadow[i+1][j]*shadow[j][threadIdx.x];
}
}
__syncthreads();
}
/* The first row is not modified, it
* is no need to write it back to the
* global memory */
array_offset = (offset+1)*matrix_dim+offset;
for(i = 1; i < BLOCK_SIZE; i++) {
m[array_offset+threadIdx.x] = shadow[i][threadIdx.x];
array_offset += matrix_dim;
}
}
__global__ void lud_diagonal_noshr(float *m, int matrix_dim, int offset)
{
int i,j;
int array_offset = offset*matrix_dim+offset;
for(i = 0; i < BLOCK_SIZE-1; i++) {
if ( threadIdx.x > i) { /* starts at 15 threads and then decrease one thread each time */
for(j = 0; j < i; j++) { /* This for loop computes cols */
m[(array_offset+threadIdx.x*matrix_dim) + i] -=
m[(array_offset+threadIdx.x*matrix_dim) + j]*
m[(array_offset+j*matrix_dim) + i];
}
m[(array_offset+threadIdx.x*matrix_dim) + i] /= m[(array_offset+i*matrix_dim) + i];
}
__syncthreads();
if ( threadIdx.x > i) {
for( j = 0; j < i+1; j++) { /* This for loop computes rows */
m[(array_offset+(i+1)*matrix_dim) + threadIdx.x] -=
m[(array_offset+(i+1)*matrix_dim) + j]*
m[(array_offset+j*matrix_dim) + threadIdx.x];
}
}
__syncthreads();
}
}
__global__ void lud_perimeter(float *m, int matrix_dim, int offset)
{
__shared__ float dia[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float peri_row[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float peri_col[BLOCK_SIZE][BLOCK_SIZE];
int i,j, array_offset;
int idx;
/* For this kernel, each block contains 32 threads */
if ( threadIdx.x < BLOCK_SIZE) { /* threads 0 ... 15 */
idx = threadIdx.x;
array_offset = offset*matrix_dim+offset;
for (i=0; i < BLOCK_SIZE/2; i++){
dia[i][idx]=m[array_offset+idx];
array_offset += matrix_dim;
}
array_offset = offset*matrix_dim+offset;
for (i=0; i < BLOCK_SIZE; i++) {
peri_row[i][idx]=m[array_offset+(blockIdx.x+1)*BLOCK_SIZE+idx];
array_offset += matrix_dim;
}
} else { /* threads 16 ... 31 */
idx = threadIdx.x-BLOCK_SIZE;
array_offset = (offset+BLOCK_SIZE/2)*matrix_dim+offset;
for (i=BLOCK_SIZE/2; i < BLOCK_SIZE; i++){
dia[i][idx]=m[array_offset+idx];
array_offset += matrix_dim;
}
array_offset = (offset+(blockIdx.x+1)*BLOCK_SIZE)*matrix_dim+offset;
for (i=0; i < BLOCK_SIZE; i++) {
peri_col[i][idx] = m[array_offset+idx];
array_offset += matrix_dim;
}
}
__syncthreads();
/* this version works ok on hardware, but not gpgpusim
**************************************************************
if (threadIdx.x < BLOCK_SIZE) { //peri-row
idx=threadIdx.x;
for(i=1; i < BLOCK_SIZE; i++){
for (j=0; j < i; j++)
peri_row[i][idx]-=dia[i][j]*peri_row[j][idx];
}
array_offset = (offset+1)*matrix_dim+offset;
for(i=1; i < BLOCK_SIZE; i++){
m[array_offset+(blockIdx.x+1)*BLOCK_SIZE+idx] = peri_row[i][idx];
array_offset += matrix_dim;
}
} else { //peri-col
idx=threadIdx.x - BLOCK_SIZE;
for(i=0; i < BLOCK_SIZE; i++){
for(j=0; j < i; j++)
peri_col[idx][i]-=peri_col[idx][j]*dia[j][i];
peri_col[idx][i] /= dia[i][i];
}
__syncthreads();
array_offset = (offset+(blockIdx.x+1)*BLOCK_SIZE)*matrix_dim+offset;
for(i=0; i < BLOCK_SIZE; i++){
m[array_offset+idx] = peri_col[i][idx];
array_offset += matrix_dim;
}
}
***************************************************************/
if (threadIdx.x < BLOCK_SIZE) { //peri-row
idx=threadIdx.x;
for(i=1; i < BLOCK_SIZE; i++){
for (j=0; j < i; j++) {
peri_row[i][idx]-=dia[i][j]*peri_row[j][idx];
}
}
} else { //peri-col
idx=threadIdx.x - BLOCK_SIZE;
for(i=0; i < BLOCK_SIZE; i++){
for(j=0; j < i; j++) {
peri_col[idx][i]-=peri_col[idx][j]*dia[j][i];
}
peri_col[idx][i] /= dia[i][i];
}
}
__syncthreads();
/* write data back to global memory */
if (threadIdx.x < BLOCK_SIZE) { //peri-row
idx=threadIdx.x;
array_offset = (offset+1)*matrix_dim+offset;
for(i=1; i < BLOCK_SIZE; i++){
m[array_offset+(blockIdx.x+1)*BLOCK_SIZE+idx] = peri_row[i][idx];
array_offset += matrix_dim;
}
} else { //peri-col
idx=threadIdx.x - BLOCK_SIZE;
array_offset = (offset+(blockIdx.x+1)*BLOCK_SIZE)*matrix_dim+offset;
for(i=0; i < BLOCK_SIZE; i++){
m[array_offset+idx] = peri_col[i][idx];
array_offset += matrix_dim;
}
}
}
__global__ void lud_perimeter_noshr(float *m, int matrix_dim, int offset)
{
int i,j, array_offset;
int idx;
if (threadIdx.x < BLOCK_SIZE) { //peri-row
array_offset = offset*matrix_dim+offset;
idx=threadIdx.x;
for(i=1; i < BLOCK_SIZE; i++){
for (j=0; j < i; j++) {
m[array_offset+i*matrix_dim+(blockIdx.x+1)*BLOCK_SIZE+idx] -=
m[array_offset+i*matrix_dim+j] * m[array_offset+j*matrix_dim+(blockIdx.x+1)*BLOCK_SIZE+idx];
}
}
} else { //peri-col
array_offset = (offset+(blockIdx.x+1)*BLOCK_SIZE)*matrix_dim+offset;
idx=threadIdx.x - BLOCK_SIZE;
for(i=0; i < BLOCK_SIZE; i++){
for(j=0; j < i; j++) {
m[array_offset+idx*matrix_dim+i] -= m[array_offset+idx*matrix_dim+j] * m[offset*matrix_dim+offset+j*matrix_dim+i];
}
m[array_offset+idx*matrix_dim+i] /= m[offset*matrix_dim+offset+i*matrix_dim+i];
}
}
}
__global__ void lud_internal(float *m, int matrix_dim, int offset)
{
__shared__ float peri_row[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float peri_col[BLOCK_SIZE][BLOCK_SIZE];
int i;
float sum;
int global_row_id = offset + (blockIdx.y+1)*BLOCK_SIZE;
int global_col_id = offset + (blockIdx.x+1)*BLOCK_SIZE;
peri_row[threadIdx.y][threadIdx.x] = m[(offset+threadIdx.y)*matrix_dim+global_col_id+threadIdx.x];
peri_col[threadIdx.y][threadIdx.x] = m[(global_row_id+threadIdx.y)*matrix_dim+offset+threadIdx.x];
__syncthreads();
sum = 0;
for (i=0; i < BLOCK_SIZE; i++) {
sum += peri_col[threadIdx.y][i] * peri_row[i][threadIdx.x];
}
m[(global_row_id+threadIdx.y)*matrix_dim+global_col_id+threadIdx.x] -= sum;
}
__global__ void lud_internal_noshr(float *m, int matrix_dim, int offset)
{
int i;
float sum;
int global_row_id = offset + (blockIdx.y+1)*BLOCK_SIZE;
int global_col_id = offset + (blockIdx.x+1)*BLOCK_SIZE;
sum = 0;
for (i=0; i < BLOCK_SIZE; i++) {
sum += m[(global_row_id+threadIdx.y)*matrix_dim+offset+i] * m[(offset+i)*matrix_dim+global_col_id+threadIdx.x];
}
m[(global_row_id+threadIdx.y)*matrix_dim+global_col_id+threadIdx.x] -= sum;
}
void lud_cuda(float *m, int matrix_dim, int do_shared)
{
int i=0;
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
/* beginning of timing point */
struct timeval tv1, tv2;
gettimeofday(&tv1, NULL);
if( do_shared) {
//printf("Executing kernels with shared memory!\n");
for (i=0; i < matrix_dim-BLOCK_SIZE; i += BLOCK_SIZE) {
lud_diagonal<<<1, BLOCK_SIZE>>>(m, matrix_dim, i);
lud_perimeter<<<(matrix_dim-i)/BLOCK_SIZE-1, BLOCK_SIZE*2>>>(m, matrix_dim, i);
dim3 dimGrid((matrix_dim-i)/BLOCK_SIZE-1, (matrix_dim-i)/BLOCK_SIZE-1);
lud_internal<<<dimGrid, dimBlock>>>(m, matrix_dim, i);
}
lud_diagonal<<<1,BLOCK_SIZE>>>(m, matrix_dim, i);
}
else {
//printf("Executing kernels without shared memory!\n");
hipFuncSetCacheConfig(reinterpret_cast<const void*>("lud_diagonal_noshr"), hipFuncCachePreferL1);
hipFuncSetCacheConfig(reinterpret_cast<const void*>("lud_perimeter_noshr"), hipFuncCachePreferL1);
hipFuncSetCacheConfig(reinterpret_cast<const void*>("lud_internal_noshr"), hipFuncCachePreferL1);
for (i=0; i < matrix_dim-BLOCK_SIZE; i += BLOCK_SIZE) {
lud_diagonal_noshr<<<1, BLOCK_SIZE>>>(m, matrix_dim, i);
lud_perimeter_noshr<<<(matrix_dim-i)/BLOCK_SIZE-1, BLOCK_SIZE*2>>>(m, matrix_dim, i);
dim3 dimGrid((matrix_dim-i)/BLOCK_SIZE-1, (matrix_dim-i)/BLOCK_SIZE-1);
lud_internal_noshr<<<dimGrid, dimBlock>>>(m, matrix_dim, i);
}
lud_diagonal<<<1,BLOCK_SIZE>>>(m, matrix_dim, i);
}
/* end of timing point */
gettimeofday(&tv2, NULL);
double runtime = ((tv2.tv_sec*1000.0 + tv2.tv_usec/1000.0)-(tv1.tv_sec*1000.0 + tv1.tv_usec/1000.0));
printf("Runtime(milliseconds): %f\n", runtime);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <sys/time.h>
#define BLOCK_SIZE 16
__global__ void lud_diagonal(float *m, int matrix_dim, int offset)
{
int i,j;
__shared__ float shadow[BLOCK_SIZE][BLOCK_SIZE];
/* Each thread block, i.e. 1D 16 threads, loads a
* 2D block, i.e. 16x16, of data from the diagonal
* of the matrix into shared memory 'shadow' */
int array_offset = offset*matrix_dim+offset;
for(i = 0; i < BLOCK_SIZE; i++){
shadow[i][threadIdx.x] = m[array_offset+threadIdx.x];
array_offset += matrix_dim;
}
__syncthreads();
for(i = 0; i < BLOCK_SIZE-1; i++) {
if ( threadIdx.x > i) { /* starts at 15 threads and then decrease one thread each time */
for(j = 0; j < i; j++) { /* This for loop computes cols */
shadow[threadIdx.x][i] -= shadow[threadIdx.x][j]*shadow[j][i];
}
shadow[threadIdx.x][i] /= shadow[i][i];
}
__syncthreads();
if ( threadIdx.x > i) {
for( j = 0; j < i+1; j++) { /* This for loop computes rows */
shadow[i+1][threadIdx.x] -= shadow[i+1][j]*shadow[j][threadIdx.x];
}
}
__syncthreads();
}
/* The first row is not modified, it
* is no need to write it back to the
* global memory */
array_offset = (offset+1)*matrix_dim+offset;
for(i = 1; i < BLOCK_SIZE; i++) {
m[array_offset+threadIdx.x] = shadow[i][threadIdx.x];
array_offset += matrix_dim;
}
}
__global__ void lud_diagonal_noshr(float *m, int matrix_dim, int offset)
{
int i,j;
int array_offset = offset*matrix_dim+offset;
for(i = 0; i < BLOCK_SIZE-1; i++) {
if ( threadIdx.x > i) { /* starts at 15 threads and then decrease one thread each time */
for(j = 0; j < i; j++) { /* This for loop computes cols */
m[(array_offset+threadIdx.x*matrix_dim) + i] -=
m[(array_offset+threadIdx.x*matrix_dim) + j]*
m[(array_offset+j*matrix_dim) + i];
}
m[(array_offset+threadIdx.x*matrix_dim) + i] /= m[(array_offset+i*matrix_dim) + i];
}
__syncthreads();
if ( threadIdx.x > i) {
for( j = 0; j < i+1; j++) { /* This for loop computes rows */
m[(array_offset+(i+1)*matrix_dim) + threadIdx.x] -=
m[(array_offset+(i+1)*matrix_dim) + j]*
m[(array_offset+j*matrix_dim) + threadIdx.x];
}
}
__syncthreads();
}
}
__global__ void lud_perimeter(float *m, int matrix_dim, int offset)
{
__shared__ float dia[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float peri_row[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float peri_col[BLOCK_SIZE][BLOCK_SIZE];
int i,j, array_offset;
int idx;
/* For this kernel, each block contains 32 threads */
if ( threadIdx.x < BLOCK_SIZE) { /* threads 0 ... 15 */
idx = threadIdx.x;
array_offset = offset*matrix_dim+offset;
for (i=0; i < BLOCK_SIZE/2; i++){
dia[i][idx]=m[array_offset+idx];
array_offset += matrix_dim;
}
array_offset = offset*matrix_dim+offset;
for (i=0; i < BLOCK_SIZE; i++) {
peri_row[i][idx]=m[array_offset+(blockIdx.x+1)*BLOCK_SIZE+idx];
array_offset += matrix_dim;
}
} else { /* threads 16 ... 31 */
idx = threadIdx.x-BLOCK_SIZE;
array_offset = (offset+BLOCK_SIZE/2)*matrix_dim+offset;
for (i=BLOCK_SIZE/2; i < BLOCK_SIZE; i++){
dia[i][idx]=m[array_offset+idx];
array_offset += matrix_dim;
}
array_offset = (offset+(blockIdx.x+1)*BLOCK_SIZE)*matrix_dim+offset;
for (i=0; i < BLOCK_SIZE; i++) {
peri_col[i][idx] = m[array_offset+idx];
array_offset += matrix_dim;
}
}
__syncthreads();
/* this version works ok on hardware, but not gpgpusim
**************************************************************
if (threadIdx.x < BLOCK_SIZE) { //peri-row
idx=threadIdx.x;
for(i=1; i < BLOCK_SIZE; i++){
for (j=0; j < i; j++)
peri_row[i][idx]-=dia[i][j]*peri_row[j][idx];
}
array_offset = (offset+1)*matrix_dim+offset;
for(i=1; i < BLOCK_SIZE; i++){
m[array_offset+(blockIdx.x+1)*BLOCK_SIZE+idx] = peri_row[i][idx];
array_offset += matrix_dim;
}
} else { //peri-col
idx=threadIdx.x - BLOCK_SIZE;
for(i=0; i < BLOCK_SIZE; i++){
for(j=0; j < i; j++)
peri_col[idx][i]-=peri_col[idx][j]*dia[j][i];
peri_col[idx][i] /= dia[i][i];
}
__syncthreads();
array_offset = (offset+(blockIdx.x+1)*BLOCK_SIZE)*matrix_dim+offset;
for(i=0; i < BLOCK_SIZE; i++){
m[array_offset+idx] = peri_col[i][idx];
array_offset += matrix_dim;
}
}
***************************************************************/
if (threadIdx.x < BLOCK_SIZE) { //peri-row
idx=threadIdx.x;
for(i=1; i < BLOCK_SIZE; i++){
for (j=0; j < i; j++) {
peri_row[i][idx]-=dia[i][j]*peri_row[j][idx];
}
}
} else { //peri-col
idx=threadIdx.x - BLOCK_SIZE;
for(i=0; i < BLOCK_SIZE; i++){
for(j=0; j < i; j++) {
peri_col[idx][i]-=peri_col[idx][j]*dia[j][i];
}
peri_col[idx][i] /= dia[i][i];
}
}
__syncthreads();
/* write data back to global memory */
if (threadIdx.x < BLOCK_SIZE) { //peri-row
idx=threadIdx.x;
array_offset = (offset+1)*matrix_dim+offset;
for(i=1; i < BLOCK_SIZE; i++){
m[array_offset+(blockIdx.x+1)*BLOCK_SIZE+idx] = peri_row[i][idx];
array_offset += matrix_dim;
}
} else { //peri-col
idx=threadIdx.x - BLOCK_SIZE;
array_offset = (offset+(blockIdx.x+1)*BLOCK_SIZE)*matrix_dim+offset;
for(i=0; i < BLOCK_SIZE; i++){
m[array_offset+idx] = peri_col[i][idx];
array_offset += matrix_dim;
}
}
}
__global__ void lud_perimeter_noshr(float *m, int matrix_dim, int offset)
{
int i,j, array_offset;
int idx;
if (threadIdx.x < BLOCK_SIZE) { //peri-row
array_offset = offset*matrix_dim+offset;
idx=threadIdx.x;
for(i=1; i < BLOCK_SIZE; i++){
for (j=0; j < i; j++) {
m[array_offset+i*matrix_dim+(blockIdx.x+1)*BLOCK_SIZE+idx] -=
m[array_offset+i*matrix_dim+j] * m[array_offset+j*matrix_dim+(blockIdx.x+1)*BLOCK_SIZE+idx];
}
}
} else { //peri-col
array_offset = (offset+(blockIdx.x+1)*BLOCK_SIZE)*matrix_dim+offset;
idx=threadIdx.x - BLOCK_SIZE;
for(i=0; i < BLOCK_SIZE; i++){
for(j=0; j < i; j++) {
m[array_offset+idx*matrix_dim+i] -= m[array_offset+idx*matrix_dim+j] * m[offset*matrix_dim+offset+j*matrix_dim+i];
}
m[array_offset+idx*matrix_dim+i] /= m[offset*matrix_dim+offset+i*matrix_dim+i];
}
}
}
__global__ void lud_internal(float *m, int matrix_dim, int offset)
{
__shared__ float peri_row[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float peri_col[BLOCK_SIZE][BLOCK_SIZE];
int i;
float sum;
int global_row_id = offset + (blockIdx.y+1)*BLOCK_SIZE;
int global_col_id = offset + (blockIdx.x+1)*BLOCK_SIZE;
peri_row[threadIdx.y][threadIdx.x] = m[(offset+threadIdx.y)*matrix_dim+global_col_id+threadIdx.x];
peri_col[threadIdx.y][threadIdx.x] = m[(global_row_id+threadIdx.y)*matrix_dim+offset+threadIdx.x];
__syncthreads();
sum = 0;
for (i=0; i < BLOCK_SIZE; i++) {
sum += peri_col[threadIdx.y][i] * peri_row[i][threadIdx.x];
}
m[(global_row_id+threadIdx.y)*matrix_dim+global_col_id+threadIdx.x] -= sum;
}
__global__ void lud_internal_noshr(float *m, int matrix_dim, int offset)
{
int i;
float sum;
int global_row_id = offset + (blockIdx.y+1)*BLOCK_SIZE;
int global_col_id = offset + (blockIdx.x+1)*BLOCK_SIZE;
sum = 0;
for (i=0; i < BLOCK_SIZE; i++) {
sum += m[(global_row_id+threadIdx.y)*matrix_dim+offset+i] * m[(offset+i)*matrix_dim+global_col_id+threadIdx.x];
}
m[(global_row_id+threadIdx.y)*matrix_dim+global_col_id+threadIdx.x] -= sum;
}
void lud_cuda(float *m, int matrix_dim, int do_shared)
{
int i=0;
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
/* beginning of timing point */
struct timeval tv1, tv2;
gettimeofday(&tv1, NULL);
if( do_shared) {
//printf("Executing kernels with shared memory!\n");
for (i=0; i < matrix_dim-BLOCK_SIZE; i += BLOCK_SIZE) {
lud_diagonal<<<1, BLOCK_SIZE>>>(m, matrix_dim, i);
lud_perimeter<<<(matrix_dim-i)/BLOCK_SIZE-1, BLOCK_SIZE*2>>>(m, matrix_dim, i);
dim3 dimGrid((matrix_dim-i)/BLOCK_SIZE-1, (matrix_dim-i)/BLOCK_SIZE-1);
lud_internal<<<dimGrid, dimBlock>>>(m, matrix_dim, i);
}
lud_diagonal<<<1,BLOCK_SIZE>>>(m, matrix_dim, i);
}
else {
//printf("Executing kernels without shared memory!\n");
hipFuncSetCacheConfig(reinterpret_cast<const void*>("lud_diagonal_noshr"), hipFuncCachePreferL1);
hipFuncSetCacheConfig(reinterpret_cast<const void*>("lud_perimeter_noshr"), hipFuncCachePreferL1);
hipFuncSetCacheConfig(reinterpret_cast<const void*>("lud_internal_noshr"), hipFuncCachePreferL1);
for (i=0; i < matrix_dim-BLOCK_SIZE; i += BLOCK_SIZE) {
lud_diagonal_noshr<<<1, BLOCK_SIZE>>>(m, matrix_dim, i);
lud_perimeter_noshr<<<(matrix_dim-i)/BLOCK_SIZE-1, BLOCK_SIZE*2>>>(m, matrix_dim, i);
dim3 dimGrid((matrix_dim-i)/BLOCK_SIZE-1, (matrix_dim-i)/BLOCK_SIZE-1);
lud_internal_noshr<<<dimGrid, dimBlock>>>(m, matrix_dim, i);
}
lud_diagonal<<<1,BLOCK_SIZE>>>(m, matrix_dim, i);
}
/* end of timing point */
gettimeofday(&tv2, NULL);
double runtime = ((tv2.tv_sec*1000.0 + tv2.tv_usec/1000.0)-(tv1.tv_sec*1000.0 + tv1.tv_usec/1000.0));
printf("Runtime(milliseconds): %f\n", runtime);
} | .text
.file "lud_kernel.hip"
.globl _Z27__device_stub__lud_diagonalPfii # -- Begin function _Z27__device_stub__lud_diagonalPfii
.p2align 4, 0x90
.type _Z27__device_stub__lud_diagonalPfii,@function
_Z27__device_stub__lud_diagonalPfii: # @_Z27__device_stub__lud_diagonalPfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12lud_diagonalPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z27__device_stub__lud_diagonalPfii, .Lfunc_end0-_Z27__device_stub__lud_diagonalPfii
.cfi_endproc
# -- End function
.globl _Z33__device_stub__lud_diagonal_noshrPfii # -- Begin function _Z33__device_stub__lud_diagonal_noshrPfii
.p2align 4, 0x90
.type _Z33__device_stub__lud_diagonal_noshrPfii,@function
_Z33__device_stub__lud_diagonal_noshrPfii: # @_Z33__device_stub__lud_diagonal_noshrPfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z18lud_diagonal_noshrPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z33__device_stub__lud_diagonal_noshrPfii, .Lfunc_end1-_Z33__device_stub__lud_diagonal_noshrPfii
.cfi_endproc
# -- End function
.globl _Z28__device_stub__lud_perimeterPfii # -- Begin function _Z28__device_stub__lud_perimeterPfii
.p2align 4, 0x90
.type _Z28__device_stub__lud_perimeterPfii,@function
_Z28__device_stub__lud_perimeterPfii: # @_Z28__device_stub__lud_perimeterPfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13lud_perimeterPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z28__device_stub__lud_perimeterPfii, .Lfunc_end2-_Z28__device_stub__lud_perimeterPfii
.cfi_endproc
# -- End function
.globl _Z34__device_stub__lud_perimeter_noshrPfii # -- Begin function _Z34__device_stub__lud_perimeter_noshrPfii
.p2align 4, 0x90
.type _Z34__device_stub__lud_perimeter_noshrPfii,@function
_Z34__device_stub__lud_perimeter_noshrPfii: # @_Z34__device_stub__lud_perimeter_noshrPfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z19lud_perimeter_noshrPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z34__device_stub__lud_perimeter_noshrPfii, .Lfunc_end3-_Z34__device_stub__lud_perimeter_noshrPfii
.cfi_endproc
# -- End function
.globl _Z27__device_stub__lud_internalPfii # -- Begin function _Z27__device_stub__lud_internalPfii
.p2align 4, 0x90
.type _Z27__device_stub__lud_internalPfii,@function
_Z27__device_stub__lud_internalPfii: # @_Z27__device_stub__lud_internalPfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12lud_internalPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end4:
.size _Z27__device_stub__lud_internalPfii, .Lfunc_end4-_Z27__device_stub__lud_internalPfii
.cfi_endproc
# -- End function
.globl _Z33__device_stub__lud_internal_noshrPfii # -- Begin function _Z33__device_stub__lud_internal_noshrPfii
.p2align 4, 0x90
.type _Z33__device_stub__lud_internal_noshrPfii,@function
_Z33__device_stub__lud_internal_noshrPfii: # @_Z33__device_stub__lud_internal_noshrPfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z18lud_internal_noshrPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end5:
.size _Z33__device_stub__lud_internal_noshrPfii, .Lfunc_end5-_Z33__device_stub__lud_internal_noshrPfii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z8lud_cudaPfii
.LCPI6_0:
.quad 0x408f400000000000 # double 1000
.text
.globl _Z8lud_cudaPfii
.p2align 4, 0x90
.type _Z8lud_cudaPfii,@function
_Z8lud_cudaPfii: # @_Z8lud_cudaPfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movl %esi, %ebx
movq %rdi, 96(%rsp) # 8-byte Spill
movabsq $4294967297, %r15 # imm = 0x100000001
xorl %r14d, %r14d
leaq 120(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
testl %ebp, %ebp
je .LBB6_10
# %bb.1: # %.preheader
movq %rbx, %r13
cmpl $17, %ebx
jl .LBB6_19
# %bb.2: # %.lr.ph
movq %r13, %rbx
leal -16(%r13), %eax
movl %eax, 108(%rsp) # 4-byte Spill
xorl %r14d, %r14d
leaq 15(%r15), %rax
movq %rax, 112(%rsp) # 8-byte Spill
leaq 31(%r15), %r12
# kill: def $ebx killed $ebx killed $rbx def $rbx
jmp .LBB6_3
.p2align 4, 0x90
.LBB6_9: # in Loop: Header=BB6_3 Depth=1
addl $16, %r14d
addl $-16, %ebx
cmpl 108(%rsp), %r14d # 4-byte Folded Reload
jge .LBB6_19
.LBB6_3: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movl $1, %esi
movq 112(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_5
# %bb.4: # in Loop: Header=BB6_3 Depth=1
movq 96(%rsp), %rax # 8-byte Reload
movq %rax, 56(%rsp)
movl %r13d, 4(%rsp)
movl %r14d, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movl $_Z12lud_diagonalPfii, %edi
leaq 64(%rsp), %r9
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_5: # in Loop: Header=BB6_3 Depth=1
leal 15(%rbx), %ebp
testl %ebx, %ebx
cmovnsl %ebx, %ebp
sarl $4, %ebp
decl %ebp
leaq (%r15,%rbp), %rdi
decq %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_7
# %bb.6: # in Loop: Header=BB6_3 Depth=1
movq 96(%rsp), %rax # 8-byte Reload
movq %rax, 56(%rsp)
movl %r13d, 4(%rsp)
movl %r14d, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movl $_Z13lud_perimeterPfii, %edi
leaq 64(%rsp), %r9
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_7: # in Loop: Header=BB6_3 Depth=1
imulq %r15, %rbp
movq %rbp, %rdi
movl $1, %esi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_9
# %bb.8: # in Loop: Header=BB6_3 Depth=1
movq 96(%rsp), %rax # 8-byte Reload
movq %rax, 56(%rsp)
movl %r13d, 4(%rsp)
movl %r14d, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movl $_Z12lud_internalPfii, %edi
leaq 64(%rsp), %r9
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB6_9
.LBB6_10:
movl $.L.str, %edi
movl $2, %esi
callq hipFuncSetCacheConfig
movl $.L.str.1, %edi
movl $2, %esi
callq hipFuncSetCacheConfig
movl $.L.str.2, %edi
movl $2, %esi
callq hipFuncSetCacheConfig
xorl %r14d, %r14d
movq %rbx, %r13
cmpl $17, %ebx
jl .LBB6_19
# %bb.11: # %.lr.ph173
movq %r13, %rbx
leal -16(%r13), %eax
movl %eax, 108(%rsp) # 4-byte Spill
xorl %r14d, %r14d
leaq 15(%r15), %rax
movq %rax, 112(%rsp) # 8-byte Spill
leaq 31(%r15), %r12
# kill: def $ebx killed $ebx killed $rbx def $rbx
jmp .LBB6_12
.p2align 4, 0x90
.LBB6_18: # in Loop: Header=BB6_12 Depth=1
addl $16, %r14d
addl $-16, %ebx
cmpl 108(%rsp), %r14d # 4-byte Folded Reload
jge .LBB6_19
.LBB6_12: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movl $1, %esi
movq 112(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_14
# %bb.13: # in Loop: Header=BB6_12 Depth=1
movq 96(%rsp), %rax # 8-byte Reload
movq %rax, 56(%rsp)
movl %r13d, 4(%rsp)
movl %r14d, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movl $_Z18lud_diagonal_noshrPfii, %edi
leaq 64(%rsp), %r9
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_14: # in Loop: Header=BB6_12 Depth=1
leal 15(%rbx), %ebp
testl %ebx, %ebx
cmovnsl %ebx, %ebp
sarl $4, %ebp
decl %ebp
leaq (%r15,%rbp), %rdi
decq %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_16
# %bb.15: # in Loop: Header=BB6_12 Depth=1
movq 96(%rsp), %rax # 8-byte Reload
movq %rax, 56(%rsp)
movl %r13d, 4(%rsp)
movl %r14d, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movl $_Z19lud_perimeter_noshrPfii, %edi
leaq 64(%rsp), %r9
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_16: # in Loop: Header=BB6_12 Depth=1
imulq %r15, %rbp
movq %rbp, %rdi
movl $1, %esi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_18
# %bb.17: # in Loop: Header=BB6_12 Depth=1
movq 96(%rsp), %rax # 8-byte Reload
movq %rax, 56(%rsp)
movl %r13d, 4(%rsp)
movl %r14d, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movl $_Z18lud_internal_noshrPfii, %edi
leaq 64(%rsp), %r9
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB6_18
.LBB6_19: # %._crit_edge174
leaq 15(%r15), %rdx
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_21
# %bb.20:
movq 96(%rsp), %rax # 8-byte Reload
movq %rax, 56(%rsp)
movl %r13d, 4(%rsp)
movl %r14d, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12lud_diagonalPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_21:
leaq 64(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 64(%rsp), %xmm1
movsd .LCPI6_0(%rip), %xmm2 # xmm2 = mem[0],zero
mulsd %xmm2, %xmm1
cvtsi2sdq 72(%rsp), %xmm0
divsd %xmm2, %xmm0
addsd %xmm1, %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 120(%rsp), %xmm1
cvtsi2sdq 128(%rsp), %xmm3
mulsd %xmm2, %xmm1
divsd %xmm2, %xmm3
addsd %xmm1, %xmm3
subsd %xmm3, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z8lud_cudaPfii, .Lfunc_end6-_Z8lud_cudaPfii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12lud_diagonalPfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18lud_diagonal_noshrPfii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13lud_perimeterPfii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19lud_perimeter_noshrPfii, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12lud_internalPfii, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18lud_internal_noshrPfii, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12lud_diagonalPfii,@object # @_Z12lud_diagonalPfii
.section .rodata,"a",@progbits
.globl _Z12lud_diagonalPfii
.p2align 3, 0x0
_Z12lud_diagonalPfii:
.quad _Z27__device_stub__lud_diagonalPfii
.size _Z12lud_diagonalPfii, 8
.type _Z18lud_diagonal_noshrPfii,@object # @_Z18lud_diagonal_noshrPfii
.globl _Z18lud_diagonal_noshrPfii
.p2align 3, 0x0
_Z18lud_diagonal_noshrPfii:
.quad _Z33__device_stub__lud_diagonal_noshrPfii
.size _Z18lud_diagonal_noshrPfii, 8
.type _Z13lud_perimeterPfii,@object # @_Z13lud_perimeterPfii
.globl _Z13lud_perimeterPfii
.p2align 3, 0x0
_Z13lud_perimeterPfii:
.quad _Z28__device_stub__lud_perimeterPfii
.size _Z13lud_perimeterPfii, 8
.type _Z19lud_perimeter_noshrPfii,@object # @_Z19lud_perimeter_noshrPfii
.globl _Z19lud_perimeter_noshrPfii
.p2align 3, 0x0
_Z19lud_perimeter_noshrPfii:
.quad _Z34__device_stub__lud_perimeter_noshrPfii
.size _Z19lud_perimeter_noshrPfii, 8
.type _Z12lud_internalPfii,@object # @_Z12lud_internalPfii
.globl _Z12lud_internalPfii
.p2align 3, 0x0
_Z12lud_internalPfii:
.quad _Z27__device_stub__lud_internalPfii
.size _Z12lud_internalPfii, 8
.type _Z18lud_internal_noshrPfii,@object # @_Z18lud_internal_noshrPfii
.globl _Z18lud_internal_noshrPfii
.p2align 3, 0x0
_Z18lud_internal_noshrPfii:
.quad _Z33__device_stub__lud_internal_noshrPfii
.size _Z18lud_internal_noshrPfii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "lud_diagonal_noshr"
.size .L.str, 19
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "lud_perimeter_noshr"
.size .L.str.1, 20
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "lud_internal_noshr"
.size .L.str.2, 19
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Runtime(milliseconds): %f\n"
.size .L.str.3, 27
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12lud_diagonalPfii"
.size .L__unnamed_1, 21
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z18lud_diagonal_noshrPfii"
.size .L__unnamed_2, 27
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z13lud_perimeterPfii"
.size .L__unnamed_3, 22
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z19lud_perimeter_noshrPfii"
.size .L__unnamed_4, 28
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z12lud_internalPfii"
.size .L__unnamed_5, 21
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "_Z18lud_internal_noshrPfii"
.size .L__unnamed_6, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__lud_diagonalPfii
.addrsig_sym _Z33__device_stub__lud_diagonal_noshrPfii
.addrsig_sym _Z28__device_stub__lud_perimeterPfii
.addrsig_sym _Z34__device_stub__lud_perimeter_noshrPfii
.addrsig_sym _Z27__device_stub__lud_internalPfii
.addrsig_sym _Z33__device_stub__lud_internal_noshrPfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12lud_diagonalPfii
.addrsig_sym _Z18lud_diagonal_noshrPfii
.addrsig_sym _Z13lud_perimeterPfii
.addrsig_sym _Z19lud_perimeter_noshrPfii
.addrsig_sym _Z12lud_internalPfii
.addrsig_sym _Z18lud_internal_noshrPfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b8930_00000000-6_lud_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z12lud_diagonalPfiiPfii
.type _Z34__device_stub__Z12lud_diagonalPfiiPfii, @function
_Z34__device_stub__Z12lud_diagonalPfiiPfii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12lud_diagonalPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z12lud_diagonalPfiiPfii, .-_Z34__device_stub__Z12lud_diagonalPfiiPfii
.globl _Z12lud_diagonalPfii
.type _Z12lud_diagonalPfii, @function
_Z12lud_diagonalPfii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z12lud_diagonalPfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12lud_diagonalPfii, .-_Z12lud_diagonalPfii
.globl _Z40__device_stub__Z18lud_diagonal_noshrPfiiPfii
.type _Z40__device_stub__Z18lud_diagonal_noshrPfiiPfii, @function
_Z40__device_stub__Z18lud_diagonal_noshrPfiiPfii:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z18lud_diagonal_noshrPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z40__device_stub__Z18lud_diagonal_noshrPfiiPfii, .-_Z40__device_stub__Z18lud_diagonal_noshrPfiiPfii
.globl _Z18lud_diagonal_noshrPfii
.type _Z18lud_diagonal_noshrPfii, @function
_Z18lud_diagonal_noshrPfii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z18lud_diagonal_noshrPfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z18lud_diagonal_noshrPfii, .-_Z18lud_diagonal_noshrPfii
.globl _Z35__device_stub__Z13lud_perimeterPfiiPfii
.type _Z35__device_stub__Z13lud_perimeterPfiiPfii, @function
_Z35__device_stub__Z13lud_perimeterPfiiPfii:
.LFB2086:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13lud_perimeterPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z35__device_stub__Z13lud_perimeterPfiiPfii, .-_Z35__device_stub__Z13lud_perimeterPfiiPfii
.globl _Z13lud_perimeterPfii
.type _Z13lud_perimeterPfii, @function
_Z13lud_perimeterPfii:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z13lud_perimeterPfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z13lud_perimeterPfii, .-_Z13lud_perimeterPfii
.globl _Z41__device_stub__Z19lud_perimeter_noshrPfiiPfii
.type _Z41__device_stub__Z19lud_perimeter_noshrPfiiPfii, @function
_Z41__device_stub__Z19lud_perimeter_noshrPfiiPfii:
.LFB2088:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z19lud_perimeter_noshrPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z41__device_stub__Z19lud_perimeter_noshrPfiiPfii, .-_Z41__device_stub__Z19lud_perimeter_noshrPfiiPfii
.globl _Z19lud_perimeter_noshrPfii
.type _Z19lud_perimeter_noshrPfii, @function
_Z19lud_perimeter_noshrPfii:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z19lud_perimeter_noshrPfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z19lud_perimeter_noshrPfii, .-_Z19lud_perimeter_noshrPfii
.globl _Z34__device_stub__Z12lud_internalPfiiPfii
.type _Z34__device_stub__Z12lud_internalPfiiPfii, @function
_Z34__device_stub__Z12lud_internalPfiiPfii:
.LFB2090:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12lud_internalPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z34__device_stub__Z12lud_internalPfiiPfii, .-_Z34__device_stub__Z12lud_internalPfiiPfii
.globl _Z12lud_internalPfii
.type _Z12lud_internalPfii, @function
_Z12lud_internalPfii:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z12lud_internalPfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z12lud_internalPfii, .-_Z12lud_internalPfii
.globl _Z40__device_stub__Z18lud_internal_noshrPfiiPfii
.type _Z40__device_stub__Z18lud_internal_noshrPfiiPfii, @function
_Z40__device_stub__Z18lud_internal_noshrPfiiPfii:
.LFB2092:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L47
.L43:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z18lud_internal_noshrPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L43
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2092:
.size _Z40__device_stub__Z18lud_internal_noshrPfiiPfii, .-_Z40__device_stub__Z18lud_internal_noshrPfiiPfii
.globl _Z18lud_internal_noshrPfii
.type _Z18lud_internal_noshrPfii, @function
_Z18lud_internal_noshrPfii:
.LFB2093:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z18lud_internal_noshrPfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _Z18lud_internal_noshrPfii, .-_Z18lud_internal_noshrPfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "lud_diagonal_noshr"
.LC1:
.string "lud_perimeter_noshr"
.LC2:
.string "lud_internal_noshr"
.LC4:
.string "Runtime(milliseconds): %f\n"
.text
.globl _Z8lud_cudaPfii
.type _Z8lud_cudaPfii, @function
_Z8lud_cudaPfii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %rdi, %r13
movl %esi, %r12d
movl %edx, %ebx
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $16, 24(%rsp)
movl $16, 28(%rsp)
movl $1, 32(%rsp)
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
testl %ebx, %ebx
je .L52
cmpl $16, %r12d
jle .L67
leal -17(%r12), %eax
movl %eax, 12(%rsp)
leal -16(%r12), %r15d
andl $-16, %eax
subl %eax, %r15d
movl %r12d, %ebp
jmp .L57
.L72:
movl %r14d, %edx
movl %r12d, %esi
movq %r13, %rdi
call _Z34__device_stub__Z12lud_diagonalPfiiPfii
jmp .L54
.L73:
movl %r14d, %edx
movl %r12d, %esi
movq %r13, %rdi
call _Z35__device_stub__Z13lud_perimeterPfiiPfii
jmp .L55
.L56:
subl $16, %ebp
cmpl %r15d, %ebp
je .L71
.L57:
movl %r12d, %r14d
subl %ebp, %r14d
movl $16, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L72
.L54:
movl $32, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
leal 15(%rbp), %ebx
testl %ebp, %ebp
cmovns %ebp, %ebx
sarl $4, %ebx
subl $1, %ebx
movl %ebx, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L73
.L55:
movl %ebx, 64(%rsp)
movl %ebx, 68(%rsp)
movl $1, 72(%rsp)
movl 32(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L56
movl %r14d, %edx
movl %r12d, %esi
movq %r13, %rdi
call _Z34__device_stub__Z12lud_internalPfiiPfii
jmp .L56
.L71:
movl 12(%rsp), %eax
andl $-16, %eax
leal 16(%rax), %ebx
.L53:
movl $16, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L74
.L59:
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 64(%rsp), %xmm0
movsd .LC3(%rip), %xmm2
mulsd %xmm2, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 72(%rsp), %xmm1
divsd %xmm2, %xmm1
addsd %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 48(%rsp), %xmm1
mulsd %xmm2, %xmm1
pxor %xmm3, %xmm3
cvtsi2sdq 56(%rsp), %xmm3
divsd %xmm2, %xmm3
addsd %xmm3, %xmm1
subsd %xmm1, %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L75
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L67:
.cfi_restore_state
movl $0, %ebx
jmp .L53
.L74:
movl %ebx, %edx
movl %r12d, %esi
movq %r13, %rdi
call _Z34__device_stub__Z12lud_diagonalPfiiPfii
jmp .L59
.L52:
movl $2, %esi
leaq .LC0(%rip), %rdi
call cudaFuncSetCacheConfig@PLT
movl $2, %esi
leaq .LC1(%rip), %rdi
call cudaFuncSetCacheConfig@PLT
movl $2, %esi
leaq .LC2(%rip), %rdi
call cudaFuncSetCacheConfig@PLT
cmpl $16, %r12d
jle .L60
leal -17(%r12), %eax
movl %eax, 12(%rsp)
leal -16(%r12), %r15d
andl $-16, %eax
subl %eax, %r15d
movl %r12d, %ebp
jmp .L64
.L77:
movl %r14d, %edx
movl %r12d, %esi
movq %r13, %rdi
call _Z40__device_stub__Z18lud_diagonal_noshrPfiiPfii
jmp .L61
.L78:
movl %r14d, %edx
movl %r12d, %esi
movq %r13, %rdi
call _Z41__device_stub__Z19lud_perimeter_noshrPfiiPfii
jmp .L62
.L79:
movl %r14d, %edx
movl %r12d, %esi
movq %r13, %rdi
call _Z40__device_stub__Z18lud_internal_noshrPfiiPfii
.L63:
subl $16, %ebp
cmpl %r15d, %ebp
je .L76
.L64:
movl %r12d, %r14d
subl %ebp, %r14d
movl $16, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L77
.L61:
movl $32, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
leal 15(%rbp), %ebx
testl %ebp, %ebp
cmovns %ebp, %ebx
sarl $4, %ebx
subl $1, %ebx
movl %ebx, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L78
.L62:
movl %ebx, 64(%rsp)
movl %ebx, 68(%rsp)
movl $1, 72(%rsp)
movl 32(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L63
jmp .L79
.L76:
movl 12(%rsp), %eax
andl $-16, %eax
leal 16(%rax), %ebx
.L60:
movl $16, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L59
movl %ebx, %edx
movl %r12d, %esi
movq %r13, %rdi
call _Z34__device_stub__Z12lud_diagonalPfiiPfii
jmp .L59
.L75:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z8lud_cudaPfii, .-_Z8lud_cudaPfii
.section .rodata.str1.1
.LC5:
.string "_Z18lud_internal_noshrPfii"
.LC6:
.string "_Z12lud_internalPfii"
.LC7:
.string "_Z19lud_perimeter_noshrPfii"
.LC8:
.string "_Z13lud_perimeterPfii"
.LC9:
.string "_Z18lud_diagonal_noshrPfii"
.LC10:
.string "_Z12lud_diagonalPfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2095:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z18lud_internal_noshrPfii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z12lud_internalPfii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z19lud_perimeter_noshrPfii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z13lud_perimeterPfii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z18lud_diagonal_noshrPfii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z12lud_diagonalPfii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2095:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "lud_kernel.hip"
.globl _Z27__device_stub__lud_diagonalPfii # -- Begin function _Z27__device_stub__lud_diagonalPfii
.p2align 4, 0x90
.type _Z27__device_stub__lud_diagonalPfii,@function
_Z27__device_stub__lud_diagonalPfii: # @_Z27__device_stub__lud_diagonalPfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12lud_diagonalPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z27__device_stub__lud_diagonalPfii, .Lfunc_end0-_Z27__device_stub__lud_diagonalPfii
.cfi_endproc
# -- End function
.globl _Z33__device_stub__lud_diagonal_noshrPfii # -- Begin function _Z33__device_stub__lud_diagonal_noshrPfii
.p2align 4, 0x90
.type _Z33__device_stub__lud_diagonal_noshrPfii,@function
_Z33__device_stub__lud_diagonal_noshrPfii: # @_Z33__device_stub__lud_diagonal_noshrPfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z18lud_diagonal_noshrPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z33__device_stub__lud_diagonal_noshrPfii, .Lfunc_end1-_Z33__device_stub__lud_diagonal_noshrPfii
.cfi_endproc
# -- End function
.globl _Z28__device_stub__lud_perimeterPfii # -- Begin function _Z28__device_stub__lud_perimeterPfii
.p2align 4, 0x90
.type _Z28__device_stub__lud_perimeterPfii,@function
_Z28__device_stub__lud_perimeterPfii: # @_Z28__device_stub__lud_perimeterPfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13lud_perimeterPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z28__device_stub__lud_perimeterPfii, .Lfunc_end2-_Z28__device_stub__lud_perimeterPfii
.cfi_endproc
# -- End function
.globl _Z34__device_stub__lud_perimeter_noshrPfii # -- Begin function _Z34__device_stub__lud_perimeter_noshrPfii
.p2align 4, 0x90
.type _Z34__device_stub__lud_perimeter_noshrPfii,@function
_Z34__device_stub__lud_perimeter_noshrPfii: # @_Z34__device_stub__lud_perimeter_noshrPfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z19lud_perimeter_noshrPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z34__device_stub__lud_perimeter_noshrPfii, .Lfunc_end3-_Z34__device_stub__lud_perimeter_noshrPfii
.cfi_endproc
# -- End function
.globl _Z27__device_stub__lud_internalPfii # -- Begin function _Z27__device_stub__lud_internalPfii
.p2align 4, 0x90
.type _Z27__device_stub__lud_internalPfii,@function
_Z27__device_stub__lud_internalPfii: # @_Z27__device_stub__lud_internalPfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12lud_internalPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end4:
.size _Z27__device_stub__lud_internalPfii, .Lfunc_end4-_Z27__device_stub__lud_internalPfii
.cfi_endproc
# -- End function
.globl _Z33__device_stub__lud_internal_noshrPfii # -- Begin function _Z33__device_stub__lud_internal_noshrPfii
.p2align 4, 0x90
.type _Z33__device_stub__lud_internal_noshrPfii,@function
_Z33__device_stub__lud_internal_noshrPfii: # @_Z33__device_stub__lud_internal_noshrPfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z18lud_internal_noshrPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end5:
.size _Z33__device_stub__lud_internal_noshrPfii, .Lfunc_end5-_Z33__device_stub__lud_internal_noshrPfii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z8lud_cudaPfii
.LCPI6_0:
.quad 0x408f400000000000 # double 1000
.text
.globl _Z8lud_cudaPfii
.p2align 4, 0x90
.type _Z8lud_cudaPfii,@function
_Z8lud_cudaPfii: # @_Z8lud_cudaPfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movl %esi, %ebx
movq %rdi, 96(%rsp) # 8-byte Spill
movabsq $4294967297, %r15 # imm = 0x100000001
xorl %r14d, %r14d
leaq 120(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
testl %ebp, %ebp
je .LBB6_10
# %bb.1: # %.preheader
movq %rbx, %r13
cmpl $17, %ebx
jl .LBB6_19
# %bb.2: # %.lr.ph
movq %r13, %rbx
leal -16(%r13), %eax
movl %eax, 108(%rsp) # 4-byte Spill
xorl %r14d, %r14d
leaq 15(%r15), %rax
movq %rax, 112(%rsp) # 8-byte Spill
leaq 31(%r15), %r12
# kill: def $ebx killed $ebx killed $rbx def $rbx
jmp .LBB6_3
.p2align 4, 0x90
.LBB6_9: # in Loop: Header=BB6_3 Depth=1
addl $16, %r14d
addl $-16, %ebx
cmpl 108(%rsp), %r14d # 4-byte Folded Reload
jge .LBB6_19
.LBB6_3: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movl $1, %esi
movq 112(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_5
# %bb.4: # in Loop: Header=BB6_3 Depth=1
movq 96(%rsp), %rax # 8-byte Reload
movq %rax, 56(%rsp)
movl %r13d, 4(%rsp)
movl %r14d, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movl $_Z12lud_diagonalPfii, %edi
leaq 64(%rsp), %r9
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_5: # in Loop: Header=BB6_3 Depth=1
leal 15(%rbx), %ebp
testl %ebx, %ebx
cmovnsl %ebx, %ebp
sarl $4, %ebp
decl %ebp
leaq (%r15,%rbp), %rdi
decq %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_7
# %bb.6: # in Loop: Header=BB6_3 Depth=1
movq 96(%rsp), %rax # 8-byte Reload
movq %rax, 56(%rsp)
movl %r13d, 4(%rsp)
movl %r14d, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movl $_Z13lud_perimeterPfii, %edi
leaq 64(%rsp), %r9
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_7: # in Loop: Header=BB6_3 Depth=1
imulq %r15, %rbp
movq %rbp, %rdi
movl $1, %esi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_9
# %bb.8: # in Loop: Header=BB6_3 Depth=1
movq 96(%rsp), %rax # 8-byte Reload
movq %rax, 56(%rsp)
movl %r13d, 4(%rsp)
movl %r14d, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movl $_Z12lud_internalPfii, %edi
leaq 64(%rsp), %r9
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB6_9
.LBB6_10:
movl $.L.str, %edi
movl $2, %esi
callq hipFuncSetCacheConfig
movl $.L.str.1, %edi
movl $2, %esi
callq hipFuncSetCacheConfig
movl $.L.str.2, %edi
movl $2, %esi
callq hipFuncSetCacheConfig
xorl %r14d, %r14d
movq %rbx, %r13
cmpl $17, %ebx
jl .LBB6_19
# %bb.11: # %.lr.ph173
movq %r13, %rbx
leal -16(%r13), %eax
movl %eax, 108(%rsp) # 4-byte Spill
xorl %r14d, %r14d
leaq 15(%r15), %rax
movq %rax, 112(%rsp) # 8-byte Spill
leaq 31(%r15), %r12
# kill: def $ebx killed $ebx killed $rbx def $rbx
jmp .LBB6_12
.p2align 4, 0x90
.LBB6_18: # in Loop: Header=BB6_12 Depth=1
addl $16, %r14d
addl $-16, %ebx
cmpl 108(%rsp), %r14d # 4-byte Folded Reload
jge .LBB6_19
.LBB6_12: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movl $1, %esi
movq 112(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_14
# %bb.13: # in Loop: Header=BB6_12 Depth=1
movq 96(%rsp), %rax # 8-byte Reload
movq %rax, 56(%rsp)
movl %r13d, 4(%rsp)
movl %r14d, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movl $_Z18lud_diagonal_noshrPfii, %edi
leaq 64(%rsp), %r9
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_14: # in Loop: Header=BB6_12 Depth=1
leal 15(%rbx), %ebp
testl %ebx, %ebx
cmovnsl %ebx, %ebp
sarl $4, %ebp
decl %ebp
leaq (%r15,%rbp), %rdi
decq %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_16
# %bb.15: # in Loop: Header=BB6_12 Depth=1
movq 96(%rsp), %rax # 8-byte Reload
movq %rax, 56(%rsp)
movl %r13d, 4(%rsp)
movl %r14d, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movl $_Z19lud_perimeter_noshrPfii, %edi
leaq 64(%rsp), %r9
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_16: # in Loop: Header=BB6_12 Depth=1
imulq %r15, %rbp
movq %rbp, %rdi
movl $1, %esi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_18
# %bb.17: # in Loop: Header=BB6_12 Depth=1
movq 96(%rsp), %rax # 8-byte Reload
movq %rax, 56(%rsp)
movl %r13d, 4(%rsp)
movl %r14d, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movl $_Z18lud_internal_noshrPfii, %edi
leaq 64(%rsp), %r9
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB6_18
.LBB6_19: # %._crit_edge174
leaq 15(%r15), %rdx
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_21
# %bb.20:
movq 96(%rsp), %rax # 8-byte Reload
movq %rax, 56(%rsp)
movl %r13d, 4(%rsp)
movl %r14d, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12lud_diagonalPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_21:
leaq 64(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 64(%rsp), %xmm1
movsd .LCPI6_0(%rip), %xmm2 # xmm2 = mem[0],zero
mulsd %xmm2, %xmm1
cvtsi2sdq 72(%rsp), %xmm0
divsd %xmm2, %xmm0
addsd %xmm1, %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 120(%rsp), %xmm1
cvtsi2sdq 128(%rsp), %xmm3
mulsd %xmm2, %xmm1
divsd %xmm2, %xmm3
addsd %xmm1, %xmm3
subsd %xmm3, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z8lud_cudaPfii, .Lfunc_end6-_Z8lud_cudaPfii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12lud_diagonalPfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18lud_diagonal_noshrPfii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13lud_perimeterPfii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19lud_perimeter_noshrPfii, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12lud_internalPfii, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18lud_internal_noshrPfii, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12lud_diagonalPfii,@object # @_Z12lud_diagonalPfii
.section .rodata,"a",@progbits
.globl _Z12lud_diagonalPfii
.p2align 3, 0x0
_Z12lud_diagonalPfii:
.quad _Z27__device_stub__lud_diagonalPfii
.size _Z12lud_diagonalPfii, 8
.type _Z18lud_diagonal_noshrPfii,@object # @_Z18lud_diagonal_noshrPfii
.globl _Z18lud_diagonal_noshrPfii
.p2align 3, 0x0
_Z18lud_diagonal_noshrPfii:
.quad _Z33__device_stub__lud_diagonal_noshrPfii
.size _Z18lud_diagonal_noshrPfii, 8
.type _Z13lud_perimeterPfii,@object # @_Z13lud_perimeterPfii
.globl _Z13lud_perimeterPfii
.p2align 3, 0x0
_Z13lud_perimeterPfii:
.quad _Z28__device_stub__lud_perimeterPfii
.size _Z13lud_perimeterPfii, 8
.type _Z19lud_perimeter_noshrPfii,@object # @_Z19lud_perimeter_noshrPfii
.globl _Z19lud_perimeter_noshrPfii
.p2align 3, 0x0
_Z19lud_perimeter_noshrPfii:
.quad _Z34__device_stub__lud_perimeter_noshrPfii
.size _Z19lud_perimeter_noshrPfii, 8
.type _Z12lud_internalPfii,@object # @_Z12lud_internalPfii
.globl _Z12lud_internalPfii
.p2align 3, 0x0
_Z12lud_internalPfii:
.quad _Z27__device_stub__lud_internalPfii
.size _Z12lud_internalPfii, 8
.type _Z18lud_internal_noshrPfii,@object # @_Z18lud_internal_noshrPfii
.globl _Z18lud_internal_noshrPfii
.p2align 3, 0x0
_Z18lud_internal_noshrPfii:
.quad _Z33__device_stub__lud_internal_noshrPfii
.size _Z18lud_internal_noshrPfii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "lud_diagonal_noshr"
.size .L.str, 19
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "lud_perimeter_noshr"
.size .L.str.1, 20
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "lud_internal_noshr"
.size .L.str.2, 19
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Runtime(milliseconds): %f\n"
.size .L.str.3, 27
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12lud_diagonalPfii"
.size .L__unnamed_1, 21
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z18lud_diagonal_noshrPfii"
.size .L__unnamed_2, 27
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z13lud_perimeterPfii"
.size .L__unnamed_3, 22
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z19lud_perimeter_noshrPfii"
.size .L__unnamed_4, 28
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z12lud_internalPfii"
.size .L__unnamed_5, 21
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "_Z18lud_internal_noshrPfii"
.size .L__unnamed_6, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__lud_diagonalPfii
.addrsig_sym _Z33__device_stub__lud_diagonal_noshrPfii
.addrsig_sym _Z28__device_stub__lud_perimeterPfii
.addrsig_sym _Z34__device_stub__lud_perimeter_noshrPfii
.addrsig_sym _Z27__device_stub__lud_internalPfii
.addrsig_sym _Z33__device_stub__lud_internal_noshrPfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12lud_diagonalPfii
.addrsig_sym _Z18lud_diagonal_noshrPfii
.addrsig_sym _Z13lud_perimeterPfii
.addrsig_sym _Z19lud_perimeter_noshrPfii
.addrsig_sym _Z12lud_internalPfii
.addrsig_sym _Z18lud_internal_noshrPfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* Geometric Convolution
* Original author: Shiyi Lan
* All Rights Reserved. 2019.
*/
#define get_square_euclidean_dist(x,y,z) \
((x)*(x)+(y)*(y)+(z)*(z))
#define _CUDA_NUM_THREADS 512
#define CUDA_KERNEL_LOOP(i, n) \
for (int i = blockIdx.x * blockDim.x + threadIdx.x; \
i < (n); \
i += blockDim.x * gridDim.x)
// blockDim.x * gridDim.x是1
static int _GET_BLOCKS(const int N) {
return (N + _CUDA_NUM_THREADS - 1) / _CUDA_NUM_THREADS;
}
__global__ void Normalization(const int top_count, float* aggre_feat,
const float* norm_buffer, const int num_batchs, const int num_points,
const int num_channels) {
CUDA_KERNEL_LOOP(index, top_count) {
const int base = index * num_channels;
for (int i = 0; i < num_channels; ++i)
aggre_feat[base + i] /= norm_buffer[index] + 1; //通过除以所有的边缘距离权重之和求得最终的边缘权重
}
}
__global__ void AggregateKernel(const int num_pairs, const int num_batchs, const int num_points, const int num_channels,
const float* feat, const float* xyz, float* aggre_feat, float* norm_buffer, const float std_square_dist,
const float square_decay_dist, const int delta) {
CUDA_KERNEL_LOOP(index, num_pairs) {//循环所有的线程，每一个线程做一对pair，因此index可以看作pair的下标
const int p0 = index % num_points;
const int p1 = index / num_points % num_points;
if (p0 == p1) continue;
const int b = index / (num_points * num_points);
const int pos0 = (b * num_points + p0) * 3;
const int pos1 = (b * num_points + p1) * 3;
const float x0 = xyz[pos0], y0 = xyz[pos0+1], z0 = xyz[pos0+2];
const float x1 = xyz[pos1], y1 = xyz[pos1+1], z1 = xyz[pos1+2];
const float dx = x0 - x1, dy = y0 - y1, dz = z0 - z1;
const float square_dist = get_square_euclidean_dist(dx, dy, dz);
const float dist = sqrt(square_dist);
const float r_decay = sqrt(square_decay_dist);
//if (dist < 1e-4) continue;
float dist_weight = 0;
if (square_dist < square_decay_dist) {
//if (square_dist <= std_square_dist)
// dist_weight = 1;
//else
// dist_weight = max(1 - (square_dist - std_square_dist) / (square_decay_dist - std_square_dist), 0.0);
dist_weight = (r_decay-dist)*(r_decay-dist); //将距离权重修改为论文中的形式
const float weights[3] = {abs(dx)/dist, abs(dy)/dist, abs(dz)/dist};
int act[3];
act[0] = (dx > 0) ? 1 : 0;
act[1] = (dy > 0) ? 1 : 0;
act[2] = (dz > 0) ? 1 : 0;
atomicAdd(norm_buffer + b * num_points + p1, dist_weight); //计算距离权重的分母，在normalize里面会用到
for (int i = 0; i < 3; ++i) {
int dir = (i<<1) + act[i];
int p1_idx = (b * num_points + p1) * num_channels; //注意这个在三个方向内是不变的
int p0_idx = ((b * num_points + p0) * 6 + dir) * num_channels; //边缘点的特征会随着三个方向而改变，
//并通过下面的channel的循环把每个方向对各个channel的贡献都加上去
//也就是把原本的选中的三个方向的特征(6*chennels中的其中3*channel)通过加权进行聚合，得到(1*channel)的特征
float weight = weights[i] * dist_weight;
//三个方向的循环
for (int c = 0; c < num_channels; ++c)
//每个方向num_channels维的数据的循环
if (!delta)
//由于传入的feat已经被flatten了，导致我们必须计算出他的准确的float的位置，而aggre_feat
atomicAdd(aggre_feat + p1_idx + c, feat[p0_idx + c] * weight);
else
atomicAdd(aggre_feat + p1_idx + c, (feat[p0_idx + c] - feat[((b * num_points + p1) + dir) * num_channels]) * weight);
}
}
}
}
__global__ void AggregateGradKernel(const int num_pairs, const int num_batchs, const int num_points, const int num_channels,
const float* top_feat_grad, const float* xyz, float* bottom_feat_grad, float* norm_buffer, const float std_square_dist,
const float square_decay_dist, const int delta) {
CUDA_KERNEL_LOOP(index, num_pairs) {
const int p0 = index % num_points;
const int p1 = index / num_points % num_points; //index除以n，也就是一个数据有多少个点，这样可以使得P0和P1都遍历一遍1到n
if (p0 == p1) continue;
const int b = index / (num_points * num_points); //计算到第几张图了
const int pos0 = (b * num_points + p0) * 3; //取出该张图对应的p0的存储的起始位置
const int pos1 = (b * num_points + p1) * 3; //取出该张图对应的p1的存储的起始位置
const float x0 = xyz[pos0], y0 = xyz[pos0+1], z0 = xyz[pos0+2]; //根据存储起始位置以及偏移取出xyz
const float x1 = xyz[pos1], y1 = xyz[pos1+1], z1 = xyz[pos1+2];
const float dx = x1 - x0, dy = y1 - y0, dz = z1 - z0; //计算xyz三个方向的坐标差
const float square_dist = get_square_euclidean_dist(dx, dy, dz); //计算两个点的平方距离
const float dist = sqrt(square_dist); //计算两个点的标准距离
// if (dist < 1e-4) continue; //如果距离过小，那么久不管了
float dist_weight = 0;
const float r_decay = sqrt(square_decay_dist);
if (square_dist < square_decay_dist) { //如果该点落在decay_redius之内
//if (square_dist <= std_square_dist) //如果该点落在std_redius之内，那么权重就为1
// dist_weight = 1;
//else //如果落在两个半径之内，那么就取：q到p的距离平方-内半径平方 / 内外半径平方差
// dist_weight = max(1 - (square_dist - std_square_dist) / (square_decay_dist - std_square_dist), .0);
dist_weight = (r_decay-dist)*(r_decay-dist);
//使用weights记录三个方向的cos值
const float weights[3] = {abs(dx)/dist, abs(dy)/dist, abs(dz)/dist}; //计算三个方向的cos值
int act[3];
act[0] = (dx > 0) ? 1 : 0;
act[1] = (dy > 0) ? 1 : 0;
act[2] = (dz > 0) ? 1 : 0; //根据dx dy dz的正负号确定选择哪个方向
//在norm_buffer这个batchsize*n的float内存中的 第b张图的p1位置加上上面通过判断语句计算出来的dist_weight
atomicAdd(norm_buffer + b * num_points + p1, dist_weight);
for (int i = 0; i < 3; ++i) {
int dir = (i<<1) + act[i];
int p0_idx = (b * num_points + p0) * num_channels;
int p1_idx = ((b * num_points + p1) * 6 + dir) * num_channels;
float weight = weights[i] * dist_weight;
for (int c = 0; c < num_channels; ++c)
atomicAdd(bottom_feat_grad + p1_idx + c, top_feat_grad[p0_idx + c] * weight);
}
}
}
}
void aggregateLauncher(int b, int n, int c, const float* feat, const float* xyz, float* out, float* norm_buffer, const float radius, const float decay_radius, const int delta=0) {
const int num_pair = b * n * n;
const int top_count = b * n;
cudaMemset(norm_buffer, 0, sizeof(float) * b * n); // 给normbuffer指向的前b*n*sizeof（float）个位置置0
cudaMemset(out, 0, sizeof(float) * b * n * c);
AggregateKernel<<<_GET_BLOCKS(num_pair), _CUDA_NUM_THREADS>>>(num_pair, b, n, c, feat, xyz, out, norm_buffer, radius * radius, decay_radius * decay_radius, delta);
Normalization<<<_GET_BLOCKS(top_count), _CUDA_NUM_THREADS>>>(top_count, out, norm_buffer, b, n, c);
}
void aggregategradLauncher(const int b, const int n, const int c, const float* feat, const float* xyz, const float* out, float* norm_buffer, float* grad, const float radius, const float decay_radius, const int delta=0) {
const int num_pair = b * n * n;
const int top_count = b * n;
cudaMemset(norm_buffer, 0, sizeof(float) * b * n);
cudaMemset(grad, 0, sizeof(float) * b * n * c * 6);
// 每一对都单独使用一个线程来处理，grid和block都采用1维的形式将线程分为多个block，每个block的大小维num_threads个，
AggregateGradKernel<<<_GET_BLOCKS(num_pair), _CUDA_NUM_THREADS>>>(num_pair, b, n, c, out, xyz, grad, norm_buffer, radius * radius, decay_radius * decay_radius, delta);
Normalization<<<_GET_BLOCKS(top_count), _CUDA_NUM_THREADS>>>(top_count, grad, norm_buffer, b, n, c * 6);
} | .file "tmpxft_00086454_00000000-6_tf_geoconv_g.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2032:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z13NormalizationiPfPKfiiiiPfPKfiii
.type _Z40__device_stub__Z13NormalizationiPfPKfiiiiPfPKfiii, @function
_Z40__device_stub__Z13NormalizationiPfPKfiiiiPfPKfiii:
.LFB2054:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 24(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13NormalizationiPfPKfiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z40__device_stub__Z13NormalizationiPfPKfiiiiPfPKfiii, .-_Z40__device_stub__Z13NormalizationiPfPKfiiiiPfPKfiii
.globl _Z13NormalizationiPfPKfiii
.type _Z13NormalizationiPfPKfiii, @function
_Z13NormalizationiPfPKfiii:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z13NormalizationiPfPKfiiiiPfPKfiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _Z13NormalizationiPfPKfiii, .-_Z13NormalizationiPfPKfiii
.globl _Z51__device_stub__Z15AggregateKerneliiiiPKfS0_PfS1_ffiiiiiPKfS0_PfS1_ffi
.type _Z51__device_stub__Z15AggregateKerneliiiiPKfS0_PfS1_ffiiiiiPKfS0_PfS1_ffi, @function
_Z51__device_stub__Z15AggregateKerneliiiiPKfS0_PfS1_ffiiiiiPKfS0_PfS1_ffi:
.LFB2056:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movl %edi, 60(%rsp)
movl %esi, 56(%rsp)
movl %edx, 52(%rsp)
movl %ecx, 48(%rsp)
movq %r8, 40(%rsp)
movq %r9, 32(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movq 240(%rsp), %rax
movq %rax, 24(%rsp)
movq 248(%rsp), %rax
movq %rax, 16(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
leaq 40(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
leaq 24(%rsp), %rax
movq %rax, 176(%rsp)
leaq 16(%rsp), %rax
movq %rax, 184(%rsp)
leaq 12(%rsp), %rax
movq %rax, 192(%rsp)
leaq 8(%rsp), %rax
movq %rax, 200(%rsp)
leaq 256(%rsp), %rax
movq %rax, 208(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z15AggregateKerneliiiiPKfS0_PfS1_ffi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2056:
.size _Z51__device_stub__Z15AggregateKerneliiiiPKfS0_PfS1_ffiiiiiPKfS0_PfS1_ffi, .-_Z51__device_stub__Z15AggregateKerneliiiiPKfS0_PfS1_ffiiiiiPKfS0_PfS1_ffi
.globl _Z15AggregateKerneliiiiPKfS0_PfS1_ffi
.type _Z15AggregateKerneliiiiPKfS0_PfS1_ffi, @function
_Z15AggregateKerneliiiiPKfS0_PfS1_ffi:
.LFB2057:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z51__device_stub__Z15AggregateKerneliiiiPKfS0_PfS1_ffiiiiiPKfS0_PfS1_ffi
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z15AggregateKerneliiiiPKfS0_PfS1_ffi, .-_Z15AggregateKerneliiiiPKfS0_PfS1_ffi
.globl _Z17aggregateLauncheriiiPKfS0_PfS1_ffi
.type _Z17aggregateLauncheriiiPKfS0_PfS1_ffi, @function
_Z17aggregateLauncheriiiPKfS0_PfS1_ffi:
.LFB2028:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movl %edi, %ebp
movl %esi, %ebx
movl %edx, %r14d
movq %rcx, 8(%rsp)
movq %r8, 16(%rsp)
movq %r9, (%rsp)
movss %xmm0, 24(%rsp)
movss %xmm1, 28(%rsp)
movl %edi, %r12d
imull %esi, %r12d
movl %r12d, %r15d
imull %esi, %r15d
movslq %edi, %r13
movslq %esi, %rax
imulq %rax, %r13
leaq 0(,%r13,4), %rdx
movl $0, %esi
movq 128(%rsp), %rdi
call cudaMemset@PLT
movslq %r14d, %rdx
imulq %r13, %rdx
salq $2, %rdx
movl $0, %esi
movq (%rsp), %rdi
call cudaMemset@PLT
movl $512, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
leal 1022(%r15), %eax
movl %r15d, %edx
addl $511, %edx
cmovns %edx, %eax
sarl $9, %eax
movl %eax, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L20:
movl $512, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
leal 1022(%r12), %eax
movl %r12d, %edx
addl $511, %edx
cmovns %edx, %eax
sarl $9, %eax
movl %eax, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L19:
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movss 24(%rsp), %xmm0
mulss %xmm0, %xmm0
subq $8, %rsp
.cfi_def_cfa_offset 136
movl 144(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 144
pushq 144(%rsp)
.cfi_def_cfa_offset 152
pushq 24(%rsp)
.cfi_def_cfa_offset 160
movss 60(%rsp), %xmm1
mulss %xmm1, %xmm1
movq 48(%rsp), %r9
movq 40(%rsp), %r8
movl %r14d, %ecx
movl %ebx, %edx
movl %ebp, %esi
movl %r15d, %edi
call _Z51__device_stub__Z15AggregateKerneliiiiPKfS0_PfS1_ffiiiiiPKfS0_PfS1_ffi
addq $32, %rsp
.cfi_def_cfa_offset 128
jmp .L20
.L24:
movl %r14d, %r9d
movl %ebx, %r8d
movl %ebp, %ecx
movq 128(%rsp), %rdx
movq (%rsp), %rsi
movl %r12d, %edi
call _Z40__device_stub__Z13NormalizationiPfPKfiiiiPfPKfiii
jmp .L19
.cfi_endproc
.LFE2028:
.size _Z17aggregateLauncheriiiPKfS0_PfS1_ffi, .-_Z17aggregateLauncheriiiPKfS0_PfS1_ffi
.globl _Z55__device_stub__Z19AggregateGradKerneliiiiPKfS0_PfS1_ffiiiiiPKfS0_PfS1_ffi
.type _Z55__device_stub__Z19AggregateGradKerneliiiiPKfS0_PfS1_ffiiiiiPKfS0_PfS1_ffi, @function
_Z55__device_stub__Z19AggregateGradKerneliiiiPKfS0_PfS1_ffiiiiiPKfS0_PfS1_ffi:
.LFB2058:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movl %edi, 60(%rsp)
movl %esi, 56(%rsp)
movl %edx, 52(%rsp)
movl %ecx, 48(%rsp)
movq %r8, 40(%rsp)
movq %r9, 32(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movq 240(%rsp), %rax
movq %rax, 24(%rsp)
movq 248(%rsp), %rax
movq %rax, 16(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
leaq 40(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
leaq 24(%rsp), %rax
movq %rax, 176(%rsp)
leaq 16(%rsp), %rax
movq %rax, 184(%rsp)
leaq 12(%rsp), %rax
movq %rax, 192(%rsp)
leaq 8(%rsp), %rax
movq %rax, 200(%rsp)
leaq 256(%rsp), %rax
movq %rax, 208(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z19AggregateGradKerneliiiiPKfS0_PfS1_ffi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z55__device_stub__Z19AggregateGradKerneliiiiPKfS0_PfS1_ffiiiiiPKfS0_PfS1_ffi, .-_Z55__device_stub__Z19AggregateGradKerneliiiiPKfS0_PfS1_ffiiiiiPKfS0_PfS1_ffi
.globl _Z19AggregateGradKerneliiiiPKfS0_PfS1_ffi
.type _Z19AggregateGradKerneliiiiPKfS0_PfS1_ffi, @function
_Z19AggregateGradKerneliiiiPKfS0_PfS1_ffi:
.LFB2059:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z55__device_stub__Z19AggregateGradKerneliiiiPKfS0_PfS1_ffiiiiiPKfS0_PfS1_ffi
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z19AggregateGradKerneliiiiPKfS0_PfS1_ffi, .-_Z19AggregateGradKerneliiiiPKfS0_PfS1_ffi
.globl _Z21aggregategradLauncheriiiPKfS0_S0_PfS1_ffi
.type _Z21aggregategradLauncheriiiPKfS0_S0_PfS1_ffi, @function
_Z21aggregategradLauncheriiiPKfS0_S0_PfS1_ffi:
.LFB2029:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movl %edi, %ebp
movl %esi, %ebx
movl %edx, %r14d
movq %r8, 8(%rsp)
movq %r9, 16(%rsp)
movss %xmm0, 24(%rsp)
movss %xmm1, 28(%rsp)
movl %edi, %r12d
imull %esi, %r12d
movl %r12d, %r15d
imull %esi, %r15d
movslq %edi, %r13
movslq %esi, %rax
imulq %rax, %r13
leaq 0(,%r13,4), %rdx
movl $0, %esi
movq 128(%rsp), %rdi
call cudaMemset@PLT
movslq %r14d, %rax
imulq %r13, %rax
leaq (%rax,%rax,2), %rdx
salq $3, %rdx
movl $0, %esi
movq 136(%rsp), %rdi
call cudaMemset@PLT
movl $512, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
leal 1022(%r15), %eax
movl %r15d, %edx
addl $511, %edx
cmovns %edx, %eax
sarl $9, %eax
movl %eax, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L34:
movl $512, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
leal 1022(%r12), %eax
movl %r12d, %edx
addl $511, %edx
cmovns %edx, %eax
sarl $9, %eax
movl %eax, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L33:
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
movss 24(%rsp), %xmm0
mulss %xmm0, %xmm0
subq $8, %rsp
.cfi_def_cfa_offset 136
movl 152(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 144
pushq 144(%rsp)
.cfi_def_cfa_offset 152
pushq 160(%rsp)
.cfi_def_cfa_offset 160
movss 60(%rsp), %xmm1
mulss %xmm1, %xmm1
movq 40(%rsp), %r9
movq 48(%rsp), %r8
movl %r14d, %ecx
movl %ebx, %edx
movl %ebp, %esi
movl %r15d, %edi
call _Z55__device_stub__Z19AggregateGradKerneliiiiPKfS0_PfS1_ffiiiiiPKfS0_PfS1_ffi
addq $32, %rsp
.cfi_def_cfa_offset 128
jmp .L34
.L38:
leal (%r14,%r14,2), %r9d
addl %r9d, %r9d
movl %ebx, %r8d
movl %ebp, %ecx
movq 128(%rsp), %rdx
movq 136(%rsp), %rsi
movl %r12d, %edi
call _Z40__device_stub__Z13NormalizationiPfPKfiiiiPfPKfiii
jmp .L33
.cfi_endproc
.LFE2029:
.size _Z21aggregategradLauncheriiiPKfS0_S0_PfS1_ffi, .-_Z21aggregategradLauncheriiiPKfS0_S0_PfS1_ffi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19AggregateGradKerneliiiiPKfS0_PfS1_ffi"
.align 8
.LC1:
.string "_Z15AggregateKerneliiiiPKfS0_PfS1_ffi"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z13NormalizationiPfPKfiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2061:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19AggregateGradKerneliiiiPKfS0_PfS1_ffi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z15AggregateKerneliiiiPKfS0_PfS1_ffi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z13NormalizationiPfPKfiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* Geometric Convolution
* Original author: Shiyi Lan
* All Rights Reserved. 2019.
*/
#define get_square_euclidean_dist(x,y,z) \
((x)*(x)+(y)*(y)+(z)*(z))
#define _CUDA_NUM_THREADS 512
#define CUDA_KERNEL_LOOP(i, n) \
for (int i = blockIdx.x * blockDim.x + threadIdx.x; \
i < (n); \
i += blockDim.x * gridDim.x)
// blockDim.x * gridDim.x是1
static int _GET_BLOCKS(const int N) {
return (N + _CUDA_NUM_THREADS - 1) / _CUDA_NUM_THREADS;
}
__global__ void Normalization(const int top_count, float* aggre_feat,
const float* norm_buffer, const int num_batchs, const int num_points,
const int num_channels) {
CUDA_KERNEL_LOOP(index, top_count) {
const int base = index * num_channels;
for (int i = 0; i < num_channels; ++i)
aggre_feat[base + i] /= norm_buffer[index] + 1; //通过除以所有的边缘距离权重之和求得最终的边缘权重
}
}
__global__ void AggregateKernel(const int num_pairs, const int num_batchs, const int num_points, const int num_channels,
const float* feat, const float* xyz, float* aggre_feat, float* norm_buffer, const float std_square_dist,
const float square_decay_dist, const int delta) {
CUDA_KERNEL_LOOP(index, num_pairs) {//循环所有的线程，每一个线程做一对pair，因此index可以看作pair的下标
const int p0 = index % num_points;
const int p1 = index / num_points % num_points;
if (p0 == p1) continue;
const int b = index / (num_points * num_points);
const int pos0 = (b * num_points + p0) * 3;
const int pos1 = (b * num_points + p1) * 3;
const float x0 = xyz[pos0], y0 = xyz[pos0+1], z0 = xyz[pos0+2];
const float x1 = xyz[pos1], y1 = xyz[pos1+1], z1 = xyz[pos1+2];
const float dx = x0 - x1, dy = y0 - y1, dz = z0 - z1;
const float square_dist = get_square_euclidean_dist(dx, dy, dz);
const float dist = sqrt(square_dist);
const float r_decay = sqrt(square_decay_dist);
//if (dist < 1e-4) continue;
float dist_weight = 0;
if (square_dist < square_decay_dist) {
//if (square_dist <= std_square_dist)
// dist_weight = 1;
//else
// dist_weight = max(1 - (square_dist - std_square_dist) / (square_decay_dist - std_square_dist), 0.0);
dist_weight = (r_decay-dist)*(r_decay-dist); //将距离权重修改为论文中的形式
const float weights[3] = {abs(dx)/dist, abs(dy)/dist, abs(dz)/dist};
int act[3];
act[0] = (dx > 0) ? 1 : 0;
act[1] = (dy > 0) ? 1 : 0;
act[2] = (dz > 0) ? 1 : 0;
atomicAdd(norm_buffer + b * num_points + p1, dist_weight); //计算距离权重的分母，在normalize里面会用到
for (int i = 0; i < 3; ++i) {
int dir = (i<<1) + act[i];
int p1_idx = (b * num_points + p1) * num_channels; //注意这个在三个方向内是不变的
int p0_idx = ((b * num_points + p0) * 6 + dir) * num_channels; //边缘点的特征会随着三个方向而改变，
//并通过下面的channel的循环把每个方向对各个channel的贡献都加上去
//也就是把原本的选中的三个方向的特征(6*chennels中的其中3*channel)通过加权进行聚合，得到(1*channel)的特征
float weight = weights[i] * dist_weight;
//三个方向的循环
for (int c = 0; c < num_channels; ++c)
//每个方向num_channels维的数据的循环
if (!delta)
//由于传入的feat已经被flatten了，导致我们必须计算出他的准确的float的位置，而aggre_feat
atomicAdd(aggre_feat + p1_idx + c, feat[p0_idx + c] * weight);
else
atomicAdd(aggre_feat + p1_idx + c, (feat[p0_idx + c] - feat[((b * num_points + p1) + dir) * num_channels]) * weight);
}
}
}
}
__global__ void AggregateGradKernel(const int num_pairs, const int num_batchs, const int num_points, const int num_channels,
const float* top_feat_grad, const float* xyz, float* bottom_feat_grad, float* norm_buffer, const float std_square_dist,
const float square_decay_dist, const int delta) {
CUDA_KERNEL_LOOP(index, num_pairs) {
const int p0 = index % num_points;
const int p1 = index / num_points % num_points; //index除以n，也就是一个数据有多少个点，这样可以使得P0和P1都遍历一遍1到n
if (p0 == p1) continue;
const int b = index / (num_points * num_points); //计算到第几张图了
const int pos0 = (b * num_points + p0) * 3; //取出该张图对应的p0的存储的起始位置
const int pos1 = (b * num_points + p1) * 3; //取出该张图对应的p1的存储的起始位置
const float x0 = xyz[pos0], y0 = xyz[pos0+1], z0 = xyz[pos0+2]; //根据存储起始位置以及偏移取出xyz
const float x1 = xyz[pos1], y1 = xyz[pos1+1], z1 = xyz[pos1+2];
const float dx = x1 - x0, dy = y1 - y0, dz = z1 - z0; //计算xyz三个方向的坐标差
const float square_dist = get_square_euclidean_dist(dx, dy, dz); //计算两个点的平方距离
const float dist = sqrt(square_dist); //计算两个点的标准距离
// if (dist < 1e-4) continue; //如果距离过小，那么久不管了
float dist_weight = 0;
const float r_decay = sqrt(square_decay_dist);
if (square_dist < square_decay_dist) { //如果该点落在decay_redius之内
//if (square_dist <= std_square_dist) //如果该点落在std_redius之内，那么权重就为1
// dist_weight = 1;
//else //如果落在两个半径之内，那么就取：q到p的距离平方-内半径平方 / 内外半径平方差
// dist_weight = max(1 - (square_dist - std_square_dist) / (square_decay_dist - std_square_dist), .0);
dist_weight = (r_decay-dist)*(r_decay-dist);
//使用weights记录三个方向的cos值
const float weights[3] = {abs(dx)/dist, abs(dy)/dist, abs(dz)/dist}; //计算三个方向的cos值
int act[3];
act[0] = (dx > 0) ? 1 : 0;
act[1] = (dy > 0) ? 1 : 0;
act[2] = (dz > 0) ? 1 : 0; //根据dx dy dz的正负号确定选择哪个方向
//在norm_buffer这个batchsize*n的float内存中的 第b张图的p1位置加上上面通过判断语句计算出来的dist_weight
atomicAdd(norm_buffer + b * num_points + p1, dist_weight);
for (int i = 0; i < 3; ++i) {
int dir = (i<<1) + act[i];
int p0_idx = (b * num_points + p0) * num_channels;
int p1_idx = ((b * num_points + p1) * 6 + dir) * num_channels;
float weight = weights[i] * dist_weight;
for (int c = 0; c < num_channels; ++c)
atomicAdd(bottom_feat_grad + p1_idx + c, top_feat_grad[p0_idx + c] * weight);
}
}
}
}
void aggregateLauncher(int b, int n, int c, const float* feat, const float* xyz, float* out, float* norm_buffer, const float radius, const float decay_radius, const int delta=0) {
const int num_pair = b * n * n;
const int top_count = b * n;
cudaMemset(norm_buffer, 0, sizeof(float) * b * n); // 给normbuffer指向的前b*n*sizeof（float）个位置置0
cudaMemset(out, 0, sizeof(float) * b * n * c);
AggregateKernel<<<_GET_BLOCKS(num_pair), _CUDA_NUM_THREADS>>>(num_pair, b, n, c, feat, xyz, out, norm_buffer, radius * radius, decay_radius * decay_radius, delta);
Normalization<<<_GET_BLOCKS(top_count), _CUDA_NUM_THREADS>>>(top_count, out, norm_buffer, b, n, c);
}
void aggregategradLauncher(const int b, const int n, const int c, const float* feat, const float* xyz, const float* out, float* norm_buffer, float* grad, const float radius, const float decay_radius, const int delta=0) {
const int num_pair = b * n * n;
const int top_count = b * n;
cudaMemset(norm_buffer, 0, sizeof(float) * b * n);
cudaMemset(grad, 0, sizeof(float) * b * n * c * 6);
// 每一对都单独使用一个线程来处理，grid和block都采用1维的形式将线程分为多个block，每个block的大小维num_threads个，
AggregateGradKernel<<<_GET_BLOCKS(num_pair), _CUDA_NUM_THREADS>>>(num_pair, b, n, c, out, xyz, grad, norm_buffer, radius * radius, decay_radius * decay_radius, delta);
Normalization<<<_GET_BLOCKS(top_count), _CUDA_NUM_THREADS>>>(top_count, grad, norm_buffer, b, n, c * 6);
} | #include <hip/hip_runtime.h>
/* Geometric Convolution
* Original author: Shiyi Lan
* All Rights Reserved. 2019.
*/
#define get_square_euclidean_dist(x,y,z) \
((x)*(x)+(y)*(y)+(z)*(z))
#define _CUDA_NUM_THREADS 512
#define CUDA_KERNEL_LOOP(i, n) \
for (int i = blockIdx.x * blockDim.x + threadIdx.x; \
i < (n); \
i += blockDim.x * gridDim.x)
// blockDim.x * gridDim.x是1
static int _GET_BLOCKS(const int N) {
return (N + _CUDA_NUM_THREADS - 1) / _CUDA_NUM_THREADS;
}
__global__ void Normalization(const int top_count, float* aggre_feat,
const float* norm_buffer, const int num_batchs, const int num_points,
const int num_channels) {
CUDA_KERNEL_LOOP(index, top_count) {
const int base = index * num_channels;
for (int i = 0; i < num_channels; ++i)
aggre_feat[base + i] /= norm_buffer[index] + 1; //通过除以所有的边缘距离权重之和求得最终的边缘权重
}
}
__global__ void AggregateKernel(const int num_pairs, const int num_batchs, const int num_points, const int num_channels,
const float* feat, const float* xyz, float* aggre_feat, float* norm_buffer, const float std_square_dist,
const float square_decay_dist, const int delta) {
CUDA_KERNEL_LOOP(index, num_pairs) {//循环所有的线程，每一个线程做一对pair，因此index可以看作pair的下标
const int p0 = index % num_points;
const int p1 = index / num_points % num_points;
if (p0 == p1) continue;
const int b = index / (num_points * num_points);
const int pos0 = (b * num_points + p0) * 3;
const int pos1 = (b * num_points + p1) * 3;
const float x0 = xyz[pos0], y0 = xyz[pos0+1], z0 = xyz[pos0+2];
const float x1 = xyz[pos1], y1 = xyz[pos1+1], z1 = xyz[pos1+2];
const float dx = x0 - x1, dy = y0 - y1, dz = z0 - z1;
const float square_dist = get_square_euclidean_dist(dx, dy, dz);
const float dist = sqrt(square_dist);
const float r_decay = sqrt(square_decay_dist);
//if (dist < 1e-4) continue;
float dist_weight = 0;
if (square_dist < square_decay_dist) {
//if (square_dist <= std_square_dist)
// dist_weight = 1;
//else
// dist_weight = max(1 - (square_dist - std_square_dist) / (square_decay_dist - std_square_dist), 0.0);
dist_weight = (r_decay-dist)*(r_decay-dist); //将距离权重修改为论文中的形式
const float weights[3] = {abs(dx)/dist, abs(dy)/dist, abs(dz)/dist};
int act[3];
act[0] = (dx > 0) ? 1 : 0;
act[1] = (dy > 0) ? 1 : 0;
act[2] = (dz > 0) ? 1 : 0;
atomicAdd(norm_buffer + b * num_points + p1, dist_weight); //计算距离权重的分母，在normalize里面会用到
for (int i = 0; i < 3; ++i) {
int dir = (i<<1) + act[i];
int p1_idx = (b * num_points + p1) * num_channels; //注意这个在三个方向内是不变的
int p0_idx = ((b * num_points + p0) * 6 + dir) * num_channels; //边缘点的特征会随着三个方向而改变，
//并通过下面的channel的循环把每个方向对各个channel的贡献都加上去
//也就是把原本的选中的三个方向的特征(6*chennels中的其中3*channel)通过加权进行聚合，得到(1*channel)的特征
float weight = weights[i] * dist_weight;
//三个方向的循环
for (int c = 0; c < num_channels; ++c)
//每个方向num_channels维的数据的循环
if (!delta)
//由于传入的feat已经被flatten了，导致我们必须计算出他的准确的float的位置，而aggre_feat
atomicAdd(aggre_feat + p1_idx + c, feat[p0_idx + c] * weight);
else
atomicAdd(aggre_feat + p1_idx + c, (feat[p0_idx + c] - feat[((b * num_points + p1) + dir) * num_channels]) * weight);
}
}
}
}
__global__ void AggregateGradKernel(const int num_pairs, const int num_batchs, const int num_points, const int num_channels,
const float* top_feat_grad, const float* xyz, float* bottom_feat_grad, float* norm_buffer, const float std_square_dist,
const float square_decay_dist, const int delta) {
CUDA_KERNEL_LOOP(index, num_pairs) {
const int p0 = index % num_points;
const int p1 = index / num_points % num_points; //index除以n，也就是一个数据有多少个点，这样可以使得P0和P1都遍历一遍1到n
if (p0 == p1) continue;
const int b = index / (num_points * num_points); //计算到第几张图了
const int pos0 = (b * num_points + p0) * 3; //取出该张图对应的p0的存储的起始位置
const int pos1 = (b * num_points + p1) * 3; //取出该张图对应的p1的存储的起始位置
const float x0 = xyz[pos0], y0 = xyz[pos0+1], z0 = xyz[pos0+2]; //根据存储起始位置以及偏移取出xyz
const float x1 = xyz[pos1], y1 = xyz[pos1+1], z1 = xyz[pos1+2];
const float dx = x1 - x0, dy = y1 - y0, dz = z1 - z0; //计算xyz三个方向的坐标差
const float square_dist = get_square_euclidean_dist(dx, dy, dz); //计算两个点的平方距离
const float dist = sqrt(square_dist); //计算两个点的标准距离
// if (dist < 1e-4) continue; //如果距离过小，那么久不管了
float dist_weight = 0;
const float r_decay = sqrt(square_decay_dist);
if (square_dist < square_decay_dist) { //如果该点落在decay_redius之内
//if (square_dist <= std_square_dist) //如果该点落在std_redius之内，那么权重就为1
// dist_weight = 1;
//else //如果落在两个半径之内，那么就取：q到p的距离平方-内半径平方 / 内外半径平方差
// dist_weight = max(1 - (square_dist - std_square_dist) / (square_decay_dist - std_square_dist), .0);
dist_weight = (r_decay-dist)*(r_decay-dist);
//使用weights记录三个方向的cos值
const float weights[3] = {abs(dx)/dist, abs(dy)/dist, abs(dz)/dist}; //计算三个方向的cos值
int act[3];
act[0] = (dx > 0) ? 1 : 0;
act[1] = (dy > 0) ? 1 : 0;
act[2] = (dz > 0) ? 1 : 0; //根据dx dy dz的正负号确定选择哪个方向
//在norm_buffer这个batchsize*n的float内存中的 第b张图的p1位置加上上面通过判断语句计算出来的dist_weight
atomicAdd(norm_buffer + b * num_points + p1, dist_weight);
for (int i = 0; i < 3; ++i) {
int dir = (i<<1) + act[i];
int p0_idx = (b * num_points + p0) * num_channels;
int p1_idx = ((b * num_points + p1) * 6 + dir) * num_channels;
float weight = weights[i] * dist_weight;
for (int c = 0; c < num_channels; ++c)
atomicAdd(bottom_feat_grad + p1_idx + c, top_feat_grad[p0_idx + c] * weight);
}
}
}
}
void aggregateLauncher(int b, int n, int c, const float* feat, const float* xyz, float* out, float* norm_buffer, const float radius, const float decay_radius, const int delta=0) {
const int num_pair = b * n * n;
const int top_count = b * n;
hipMemset(norm_buffer, 0, sizeof(float) * b * n); // 给normbuffer指向的前b*n*sizeof（float）个位置置0
hipMemset(out, 0, sizeof(float) * b * n * c);
AggregateKernel<<<_GET_BLOCKS(num_pair), _CUDA_NUM_THREADS>>>(num_pair, b, n, c, feat, xyz, out, norm_buffer, radius * radius, decay_radius * decay_radius, delta);
Normalization<<<_GET_BLOCKS(top_count), _CUDA_NUM_THREADS>>>(top_count, out, norm_buffer, b, n, c);
}
void aggregategradLauncher(const int b, const int n, const int c, const float* feat, const float* xyz, const float* out, float* norm_buffer, float* grad, const float radius, const float decay_radius, const int delta=0) {
const int num_pair = b * n * n;
const int top_count = b * n;
hipMemset(norm_buffer, 0, sizeof(float) * b * n);
hipMemset(grad, 0, sizeof(float) * b * n * c * 6);
// 每一对都单独使用一个线程来处理，grid和block都采用1维的形式将线程分为多个block，每个block的大小维num_threads个，
AggregateGradKernel<<<_GET_BLOCKS(num_pair), _CUDA_NUM_THREADS>>>(num_pair, b, n, c, out, xyz, grad, norm_buffer, radius * radius, decay_radius * decay_radius, delta);
Normalization<<<_GET_BLOCKS(top_count), _CUDA_NUM_THREADS>>>(top_count, grad, norm_buffer, b, n, c * 6);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/* Geometric Convolution
* Original author: Shiyi Lan
* All Rights Reserved. 2019.
*/
#define get_square_euclidean_dist(x,y,z) \
((x)*(x)+(y)*(y)+(z)*(z))
#define _CUDA_NUM_THREADS 512
#define CUDA_KERNEL_LOOP(i, n) \
for (int i = blockIdx.x * blockDim.x + threadIdx.x; \
i < (n); \
i += blockDim.x * gridDim.x)
// blockDim.x * gridDim.x是1
static int _GET_BLOCKS(const int N) {
return (N + _CUDA_NUM_THREADS - 1) / _CUDA_NUM_THREADS;
}
__global__ void Normalization(const int top_count, float* aggre_feat,
const float* norm_buffer, const int num_batchs, const int num_points,
const int num_channels) {
CUDA_KERNEL_LOOP(index, top_count) {
const int base = index * num_channels;
for (int i = 0; i < num_channels; ++i)
aggre_feat[base + i] /= norm_buffer[index] + 1; //通过除以所有的边缘距离权重之和求得最终的边缘权重
}
}
__global__ void AggregateKernel(const int num_pairs, const int num_batchs, const int num_points, const int num_channels,
const float* feat, const float* xyz, float* aggre_feat, float* norm_buffer, const float std_square_dist,
const float square_decay_dist, const int delta) {
CUDA_KERNEL_LOOP(index, num_pairs) {//循环所有的线程，每一个线程做一对pair，因此index可以看作pair的下标
const int p0 = index % num_points;
const int p1 = index / num_points % num_points;
if (p0 == p1) continue;
const int b = index / (num_points * num_points);
const int pos0 = (b * num_points + p0) * 3;
const int pos1 = (b * num_points + p1) * 3;
const float x0 = xyz[pos0], y0 = xyz[pos0+1], z0 = xyz[pos0+2];
const float x1 = xyz[pos1], y1 = xyz[pos1+1], z1 = xyz[pos1+2];
const float dx = x0 - x1, dy = y0 - y1, dz = z0 - z1;
const float square_dist = get_square_euclidean_dist(dx, dy, dz);
const float dist = sqrt(square_dist);
const float r_decay = sqrt(square_decay_dist);
//if (dist < 1e-4) continue;
float dist_weight = 0;
if (square_dist < square_decay_dist) {
//if (square_dist <= std_square_dist)
// dist_weight = 1;
//else
// dist_weight = max(1 - (square_dist - std_square_dist) / (square_decay_dist - std_square_dist), 0.0);
dist_weight = (r_decay-dist)*(r_decay-dist); //将距离权重修改为论文中的形式
const float weights[3] = {abs(dx)/dist, abs(dy)/dist, abs(dz)/dist};
int act[3];
act[0] = (dx > 0) ? 1 : 0;
act[1] = (dy > 0) ? 1 : 0;
act[2] = (dz > 0) ? 1 : 0;
atomicAdd(norm_buffer + b * num_points + p1, dist_weight); //计算距离权重的分母，在normalize里面会用到
for (int i = 0; i < 3; ++i) {
int dir = (i<<1) + act[i];
int p1_idx = (b * num_points + p1) * num_channels; //注意这个在三个方向内是不变的
int p0_idx = ((b * num_points + p0) * 6 + dir) * num_channels; //边缘点的特征会随着三个方向而改变，
//并通过下面的channel的循环把每个方向对各个channel的贡献都加上去
//也就是把原本的选中的三个方向的特征(6*chennels中的其中3*channel)通过加权进行聚合，得到(1*channel)的特征
float weight = weights[i] * dist_weight;
//三个方向的循环
for (int c = 0; c < num_channels; ++c)
//每个方向num_channels维的数据的循环
if (!delta)
//由于传入的feat已经被flatten了，导致我们必须计算出他的准确的float的位置，而aggre_feat
atomicAdd(aggre_feat + p1_idx + c, feat[p0_idx + c] * weight);
else
atomicAdd(aggre_feat + p1_idx + c, (feat[p0_idx + c] - feat[((b * num_points + p1) + dir) * num_channels]) * weight);
}
}
}
}
__global__ void AggregateGradKernel(const int num_pairs, const int num_batchs, const int num_points, const int num_channels,
const float* top_feat_grad, const float* xyz, float* bottom_feat_grad, float* norm_buffer, const float std_square_dist,
const float square_decay_dist, const int delta) {
CUDA_KERNEL_LOOP(index, num_pairs) {
const int p0 = index % num_points;
const int p1 = index / num_points % num_points; //index除以n，也就是一个数据有多少个点，这样可以使得P0和P1都遍历一遍1到n
if (p0 == p1) continue;
const int b = index / (num_points * num_points); //计算到第几张图了
const int pos0 = (b * num_points + p0) * 3; //取出该张图对应的p0的存储的起始位置
const int pos1 = (b * num_points + p1) * 3; //取出该张图对应的p1的存储的起始位置
const float x0 = xyz[pos0], y0 = xyz[pos0+1], z0 = xyz[pos0+2]; //根据存储起始位置以及偏移取出xyz
const float x1 = xyz[pos1], y1 = xyz[pos1+1], z1 = xyz[pos1+2];
const float dx = x1 - x0, dy = y1 - y0, dz = z1 - z0; //计算xyz三个方向的坐标差
const float square_dist = get_square_euclidean_dist(dx, dy, dz); //计算两个点的平方距离
const float dist = sqrt(square_dist); //计算两个点的标准距离
// if (dist < 1e-4) continue; //如果距离过小，那么久不管了
float dist_weight = 0;
const float r_decay = sqrt(square_decay_dist);
if (square_dist < square_decay_dist) { //如果该点落在decay_redius之内
//if (square_dist <= std_square_dist) //如果该点落在std_redius之内，那么权重就为1
// dist_weight = 1;
//else //如果落在两个半径之内，那么就取：q到p的距离平方-内半径平方 / 内外半径平方差
// dist_weight = max(1 - (square_dist - std_square_dist) / (square_decay_dist - std_square_dist), .0);
dist_weight = (r_decay-dist)*(r_decay-dist);
//使用weights记录三个方向的cos值
const float weights[3] = {abs(dx)/dist, abs(dy)/dist, abs(dz)/dist}; //计算三个方向的cos值
int act[3];
act[0] = (dx > 0) ? 1 : 0;
act[1] = (dy > 0) ? 1 : 0;
act[2] = (dz > 0) ? 1 : 0; //根据dx dy dz的正负号确定选择哪个方向
//在norm_buffer这个batchsize*n的float内存中的 第b张图的p1位置加上上面通过判断语句计算出来的dist_weight
atomicAdd(norm_buffer + b * num_points + p1, dist_weight);
for (int i = 0; i < 3; ++i) {
int dir = (i<<1) + act[i];
int p0_idx = (b * num_points + p0) * num_channels;
int p1_idx = ((b * num_points + p1) * 6 + dir) * num_channels;
float weight = weights[i] * dist_weight;
for (int c = 0; c < num_channels; ++c)
atomicAdd(bottom_feat_grad + p1_idx + c, top_feat_grad[p0_idx + c] * weight);
}
}
}
}
void aggregateLauncher(int b, int n, int c, const float* feat, const float* xyz, float* out, float* norm_buffer, const float radius, const float decay_radius, const int delta=0) {
const int num_pair = b * n * n;
const int top_count = b * n;
hipMemset(norm_buffer, 0, sizeof(float) * b * n); // 给normbuffer指向的前b*n*sizeof（float）个位置置0
hipMemset(out, 0, sizeof(float) * b * n * c);
AggregateKernel<<<_GET_BLOCKS(num_pair), _CUDA_NUM_THREADS>>>(num_pair, b, n, c, feat, xyz, out, norm_buffer, radius * radius, decay_radius * decay_radius, delta);
Normalization<<<_GET_BLOCKS(top_count), _CUDA_NUM_THREADS>>>(top_count, out, norm_buffer, b, n, c);
}
void aggregategradLauncher(const int b, const int n, const int c, const float* feat, const float* xyz, const float* out, float* norm_buffer, float* grad, const float radius, const float decay_radius, const int delta=0) {
const int num_pair = b * n * n;
const int top_count = b * n;
hipMemset(norm_buffer, 0, sizeof(float) * b * n);
hipMemset(grad, 0, sizeof(float) * b * n * c * 6);
// 每一对都单独使用一个线程来处理，grid和block都采用1维的形式将线程分为多个block，每个block的大小维num_threads个，
AggregateGradKernel<<<_GET_BLOCKS(num_pair), _CUDA_NUM_THREADS>>>(num_pair, b, n, c, out, xyz, grad, norm_buffer, radius * radius, decay_radius * decay_radius, delta);
Normalization<<<_GET_BLOCKS(top_count), _CUDA_NUM_THREADS>>>(top_count, grad, norm_buffer, b, n, c * 6);
} | .text
.file "tf_geoconv_g.hip"
.globl _Z28__device_stub__NormalizationiPfPKfiii # -- Begin function _Z28__device_stub__NormalizationiPfPKfiii
.p2align 4, 0x90
.type _Z28__device_stub__NormalizationiPfPKfiii,@function
_Z28__device_stub__NormalizationiPfPKfiii: # @_Z28__device_stub__NormalizationiPfPKfiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13NormalizationiPfPKfiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z28__device_stub__NormalizationiPfPKfiii, .Lfunc_end0-_Z28__device_stub__NormalizationiPfPKfiii
.cfi_endproc
# -- End function
.globl _Z30__device_stub__AggregateKerneliiiiPKfS0_PfS1_ffi # -- Begin function _Z30__device_stub__AggregateKerneliiiiPKfS0_PfS1_ffi
.p2align 4, 0x90
.type _Z30__device_stub__AggregateKerneliiiiPKfS0_PfS1_ffi,@function
_Z30__device_stub__AggregateKerneliiiiPKfS0_PfS1_ffi: # @_Z30__device_stub__AggregateKerneliiiiPKfS0_PfS1_ffi
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movq %r8, 88(%rsp)
movq %r9, 80(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
leaq 208(%rsp), %rax
movq %rax, 176(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15AggregateKerneliiiiPKfS0_PfS1_ffi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end1:
.size _Z30__device_stub__AggregateKerneliiiiPKfS0_PfS1_ffi, .Lfunc_end1-_Z30__device_stub__AggregateKerneliiiiPKfS0_PfS1_ffi
.cfi_endproc
# -- End function
.globl _Z34__device_stub__AggregateGradKerneliiiiPKfS0_PfS1_ffi # -- Begin function _Z34__device_stub__AggregateGradKerneliiiiPKfS0_PfS1_ffi
.p2align 4, 0x90
.type _Z34__device_stub__AggregateGradKerneliiiiPKfS0_PfS1_ffi,@function
_Z34__device_stub__AggregateGradKerneliiiiPKfS0_PfS1_ffi: # @_Z34__device_stub__AggregateGradKerneliiiiPKfS0_PfS1_ffi
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movq %r8, 88(%rsp)
movq %r9, 80(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
leaq 208(%rsp), %rax
movq %rax, 176(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19AggregateGradKerneliiiiPKfS0_PfS1_ffi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end2:
.size _Z34__device_stub__AggregateGradKerneliiiiPKfS0_PfS1_ffi, .Lfunc_end2-_Z34__device_stub__AggregateGradKerneliiiiPKfS0_PfS1_ffi
.cfi_endproc
# -- End function
.globl _Z17aggregateLauncheriiiPKfS0_PfS1_ffi # -- Begin function _Z17aggregateLauncheriiiPKfS0_PfS1_ffi
.p2align 4, 0x90
.type _Z17aggregateLauncheriiiPKfS0_PfS1_ffi,@function
_Z17aggregateLauncheriiiPKfS0_PfS1_ffi: # @_Z17aggregateLauncheriiiPKfS0_PfS1_ffi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movss %xmm1, 120(%rsp) # 4-byte Spill
movss %xmm0, 116(%rsp) # 4-byte Spill
movq %r9, %rbp
movq %r8, 152(%rsp) # 8-byte Spill
movq %rcx, 144(%rsp) # 8-byte Spill
movl %edx, %r15d
movq 304(%rsp), %rcx
movabsq $4294967296, %r13 # imm = 0x100000000
movl %esi, %r14d
imull %edi, %r14d
movl %r14d, %r12d
imull %esi, %r12d
movl %edi, 20(%rsp) # 4-byte Spill
movslq %edi, %rax
movl %esi, 24(%rsp) # 4-byte Spill
movslq %esi, %rbx
imulq %rax, %rbx
shlq $2, %rbx
movq %rcx, %rdi
xorl %esi, %esi
movq %rbx, %rdx
callq hipMemset
movl %r15d, 28(%rsp) # 4-byte Spill
movslq %r15d, %rdx
imulq %rbx, %rdx
movq %rbp, %rdi
xorl %esi, %esi
callq hipMemset
leal 511(%r12), %eax
leal 1022(%r12), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $9, %edi
orq %r13, %rdi
leaq 512(%r13), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movl 312(%rsp), %eax
movss 116(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm1
movss 120(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
mulss %xmm0, %xmm0
movl %r12d, 16(%rsp)
movl 20(%rsp), %ecx # 4-byte Reload
movl %ecx, 12(%rsp)
movl 24(%rsp), %ecx # 4-byte Reload
movl %ecx, 140(%rsp)
movl 28(%rsp), %ecx # 4-byte Reload
movl %ecx, 136(%rsp)
movq 144(%rsp), %rcx # 8-byte Reload
movq %rcx, 104(%rsp)
movq 152(%rsp), %rcx # 8-byte Reload
movq %rcx, 96(%rsp)
movq %rbp, 56(%rsp)
movq 304(%rsp), %rcx
movq %rcx, 48(%rsp)
movss %xmm1, 132(%rsp)
movss %xmm0, 128(%rsp)
movl %eax, 124(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 140(%rsp), %rax
movq %rax, 176(%rsp)
leaq 136(%rsp), %rax
movq %rax, 184(%rsp)
leaq 104(%rsp), %rax
movq %rax, 192(%rsp)
leaq 96(%rsp), %rax
movq %rax, 200(%rsp)
leaq 56(%rsp), %rax
movq %rax, 208(%rsp)
leaq 48(%rsp), %rax
movq %rax, 216(%rsp)
leaq 132(%rsp), %rax
movq %rax, 224(%rsp)
leaq 128(%rsp), %rax
movq %rax, 232(%rsp)
leaq 124(%rsp), %rax
movq %rax, 240(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z15AggregateKerneliiiiPKfS0_PfS1_ffi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
leal 511(%r14), %eax
leal 1022(%r14), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $9, %edi
orq %r13, %rdi
addq $512, %r13 # imm = 0x200
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3:
movl %r14d, 40(%rsp)
movq %rbp, 104(%rsp)
movq 304(%rsp), %rax
movq %rax, 96(%rsp)
movl 20(%rsp), %eax # 4-byte Reload
movl %eax, 32(%rsp)
movl 24(%rsp), %eax # 4-byte Reload
movl %eax, 16(%rsp)
movl 28(%rsp), %eax # 4-byte Reload
movl %eax, 12(%rsp)
leaq 40(%rsp), %rax
movq %rax, 160(%rsp)
leaq 104(%rsp), %rax
movq %rax, 168(%rsp)
leaq 96(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 16(%rsp), %rax
movq %rax, 192(%rsp)
leaq 12(%rsp), %rax
movq %rax, 200(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z13NormalizationiPfPKfiii, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_4:
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z17aggregateLauncheriiiPKfS0_PfS1_ffi, .Lfunc_end3-_Z17aggregateLauncheriiiPKfS0_PfS1_ffi
.cfi_endproc
# -- End function
.globl _Z21aggregategradLauncheriiiPKfS0_S0_PfS1_ffi # -- Begin function _Z21aggregategradLauncheriiiPKfS0_S0_PfS1_ffi
.p2align 4, 0x90
.type _Z21aggregategradLauncheriiiPKfS0_S0_PfS1_ffi,@function
_Z21aggregategradLauncheriiiPKfS0_S0_PfS1_ffi: # @_Z21aggregategradLauncheriiiPKfS0_S0_PfS1_ffi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movss %xmm1, 112(%rsp) # 4-byte Spill
movss %xmm0, 108(%rsp) # 4-byte Spill
movq %r9, 144(%rsp) # 8-byte Spill
movq %r8, 152(%rsp) # 8-byte Spill
movl %edx, %ebp
movl %esi, %ebx
movq 304(%rsp), %rcx
movabsq $4294967296, %r13 # imm = 0x100000000
movl %esi, %r14d
imull %edi, %r14d
movl %r14d, %r12d
imull %esi, %r12d
movl %edi, 20(%rsp) # 4-byte Spill
movslq %edi, %rax
movslq %esi, %r15
imulq %rax, %r15
shlq $2, %r15
movq %rcx, %rdi
xorl %esi, %esi
movq %r15, %rdx
callq hipMemset
movq %rbp, 136(%rsp) # 8-byte Spill
movslq %ebp, %rax
imulq %r15, %rax
movq 312(%rsp), %r15
addq %rax, %rax
leaq (%rax,%rax,2), %rdx
movq %r15, %rdi
xorl %esi, %esi
callq hipMemset
leal 511(%r12), %eax
leal 1022(%r12), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $9, %edi
orq %r13, %rdi
leaq 512(%r13), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_2
# %bb.1:
movl 320(%rsp), %eax
movss 108(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm1
movss 112(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
mulss %xmm0, %xmm0
movl %r12d, 16(%rsp)
movl 20(%rsp), %ecx # 4-byte Reload
movl %ecx, 12(%rsp)
movl %ebx, 132(%rsp)
movq 136(%rsp), %rcx # 8-byte Reload
movl %ecx, 128(%rsp)
movq 144(%rsp), %rcx # 8-byte Reload
movq %rcx, 96(%rsp)
movq 152(%rsp), %rcx # 8-byte Reload
movq %rcx, 88(%rsp)
movq %r15, 48(%rsp)
movq 304(%rsp), %rcx
movq %rcx, 40(%rsp)
movss %xmm1, 124(%rsp)
movss %xmm0, 120(%rsp)
movl %eax, 116(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 132(%rsp), %rax
movq %rax, 176(%rsp)
leaq 128(%rsp), %rax
movq %rax, 184(%rsp)
leaq 96(%rsp), %rax
movq %rax, 192(%rsp)
leaq 88(%rsp), %rax
movq %rax, 200(%rsp)
leaq 48(%rsp), %rax
movq %rax, 208(%rsp)
leaq 40(%rsp), %rax
movq %rax, 216(%rsp)
leaq 124(%rsp), %rax
movq %rax, 224(%rsp)
leaq 120(%rsp), %rax
movq %rax, 232(%rsp)
leaq 116(%rsp), %rax
movq %rax, 240(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z19AggregateGradKerneliiiiPKfS0_PfS1_ffi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_2:
leal 511(%r14), %eax
leal 1022(%r14), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $9, %edi
orq %r13, %rdi
addq $512, %r13 # imm = 0x200
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_4
# %bb.3:
movq 136(%rsp), %rax # 8-byte Reload
addl %eax, %eax
leal (%rax,%rax,2), %eax
movl %r14d, 32(%rsp)
movq %r15, 96(%rsp)
movq 304(%rsp), %rcx
movq %rcx, 88(%rsp)
movl 20(%rsp), %ecx # 4-byte Reload
movl %ecx, 24(%rsp)
movl %ebx, 16(%rsp)
movl %eax, 12(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 96(%rsp), %rax
movq %rax, 168(%rsp)
leaq 88(%rsp), %rax
movq %rax, 176(%rsp)
leaq 24(%rsp), %rax
movq %rax, 184(%rsp)
leaq 16(%rsp), %rax
movq %rax, 192(%rsp)
leaq 12(%rsp), %rax
movq %rax, 200(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z13NormalizationiPfPKfiii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_4:
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z21aggregategradLauncheriiiPKfS0_S0_PfS1_ffi, .Lfunc_end4-_Z21aggregategradLauncheriiiPKfS0_S0_PfS1_ffi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13NormalizationiPfPKfiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15AggregateKerneliiiiPKfS0_PfS1_ffi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19AggregateGradKerneliiiiPKfS0_PfS1_ffi, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13NormalizationiPfPKfiii,@object # @_Z13NormalizationiPfPKfiii
.section .rodata,"a",@progbits
.globl _Z13NormalizationiPfPKfiii
.p2align 3, 0x0
_Z13NormalizationiPfPKfiii:
.quad _Z28__device_stub__NormalizationiPfPKfiii
.size _Z13NormalizationiPfPKfiii, 8
.type _Z15AggregateKerneliiiiPKfS0_PfS1_ffi,@object # @_Z15AggregateKerneliiiiPKfS0_PfS1_ffi
.globl _Z15AggregateKerneliiiiPKfS0_PfS1_ffi
.p2align 3, 0x0
_Z15AggregateKerneliiiiPKfS0_PfS1_ffi:
.quad _Z30__device_stub__AggregateKerneliiiiPKfS0_PfS1_ffi
.size _Z15AggregateKerneliiiiPKfS0_PfS1_ffi, 8
.type _Z19AggregateGradKerneliiiiPKfS0_PfS1_ffi,@object # @_Z19AggregateGradKerneliiiiPKfS0_PfS1_ffi
.globl _Z19AggregateGradKerneliiiiPKfS0_PfS1_ffi
.p2align 3, 0x0
_Z19AggregateGradKerneliiiiPKfS0_PfS1_ffi:
.quad _Z34__device_stub__AggregateGradKerneliiiiPKfS0_PfS1_ffi
.size _Z19AggregateGradKerneliiiiPKfS0_PfS1_ffi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13NormalizationiPfPKfiii"
.size .L__unnamed_1, 27
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15AggregateKerneliiiiPKfS0_PfS1_ffi"
.size .L__unnamed_2, 38
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z19AggregateGradKerneliiiiPKfS0_PfS1_ffi"
.size .L__unnamed_3, 42
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__NormalizationiPfPKfiii
.addrsig_sym _Z30__device_stub__AggregateKerneliiiiPKfS0_PfS1_ffi
.addrsig_sym _Z34__device_stub__AggregateGradKerneliiiiPKfS0_PfS1_ffi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13NormalizationiPfPKfiii
.addrsig_sym _Z15AggregateKerneliiiiPKfS0_PfS1_ffi
.addrsig_sym _Z19AggregateGradKerneliiiiPKfS0_PfS1_ffi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00086454_00000000-6_tf_geoconv_g.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2032:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z13NormalizationiPfPKfiiiiPfPKfiii
.type _Z40__device_stub__Z13NormalizationiPfPKfiiiiPfPKfiii, @function
_Z40__device_stub__Z13NormalizationiPfPKfiiiiPfPKfiii:
.LFB2054:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 24(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13NormalizationiPfPKfiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z40__device_stub__Z13NormalizationiPfPKfiiiiPfPKfiii, .-_Z40__device_stub__Z13NormalizationiPfPKfiiiiPfPKfiii
.globl _Z13NormalizationiPfPKfiii
.type _Z13NormalizationiPfPKfiii, @function
_Z13NormalizationiPfPKfiii:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z13NormalizationiPfPKfiiiiPfPKfiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _Z13NormalizationiPfPKfiii, .-_Z13NormalizationiPfPKfiii
.globl _Z51__device_stub__Z15AggregateKerneliiiiPKfS0_PfS1_ffiiiiiPKfS0_PfS1_ffi
.type _Z51__device_stub__Z15AggregateKerneliiiiPKfS0_PfS1_ffiiiiiPKfS0_PfS1_ffi, @function
_Z51__device_stub__Z15AggregateKerneliiiiPKfS0_PfS1_ffiiiiiPKfS0_PfS1_ffi:
.LFB2056:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movl %edi, 60(%rsp)
movl %esi, 56(%rsp)
movl %edx, 52(%rsp)
movl %ecx, 48(%rsp)
movq %r8, 40(%rsp)
movq %r9, 32(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movq 240(%rsp), %rax
movq %rax, 24(%rsp)
movq 248(%rsp), %rax
movq %rax, 16(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
leaq 40(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
leaq 24(%rsp), %rax
movq %rax, 176(%rsp)
leaq 16(%rsp), %rax
movq %rax, 184(%rsp)
leaq 12(%rsp), %rax
movq %rax, 192(%rsp)
leaq 8(%rsp), %rax
movq %rax, 200(%rsp)
leaq 256(%rsp), %rax
movq %rax, 208(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z15AggregateKerneliiiiPKfS0_PfS1_ffi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2056:
.size _Z51__device_stub__Z15AggregateKerneliiiiPKfS0_PfS1_ffiiiiiPKfS0_PfS1_ffi, .-_Z51__device_stub__Z15AggregateKerneliiiiPKfS0_PfS1_ffiiiiiPKfS0_PfS1_ffi
.globl _Z15AggregateKerneliiiiPKfS0_PfS1_ffi
.type _Z15AggregateKerneliiiiPKfS0_PfS1_ffi, @function
_Z15AggregateKerneliiiiPKfS0_PfS1_ffi:
.LFB2057:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z51__device_stub__Z15AggregateKerneliiiiPKfS0_PfS1_ffiiiiiPKfS0_PfS1_ffi
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z15AggregateKerneliiiiPKfS0_PfS1_ffi, .-_Z15AggregateKerneliiiiPKfS0_PfS1_ffi
.globl _Z17aggregateLauncheriiiPKfS0_PfS1_ffi
.type _Z17aggregateLauncheriiiPKfS0_PfS1_ffi, @function
_Z17aggregateLauncheriiiPKfS0_PfS1_ffi:
.LFB2028:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movl %edi, %ebp
movl %esi, %ebx
movl %edx, %r14d
movq %rcx, 8(%rsp)
movq %r8, 16(%rsp)
movq %r9, (%rsp)
movss %xmm0, 24(%rsp)
movss %xmm1, 28(%rsp)
movl %edi, %r12d
imull %esi, %r12d
movl %r12d, %r15d
imull %esi, %r15d
movslq %edi, %r13
movslq %esi, %rax
imulq %rax, %r13
leaq 0(,%r13,4), %rdx
movl $0, %esi
movq 128(%rsp), %rdi
call cudaMemset@PLT
movslq %r14d, %rdx
imulq %r13, %rdx
salq $2, %rdx
movl $0, %esi
movq (%rsp), %rdi
call cudaMemset@PLT
movl $512, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
leal 1022(%r15), %eax
movl %r15d, %edx
addl $511, %edx
cmovns %edx, %eax
sarl $9, %eax
movl %eax, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L20:
movl $512, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
leal 1022(%r12), %eax
movl %r12d, %edx
addl $511, %edx
cmovns %edx, %eax
sarl $9, %eax
movl %eax, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L19:
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movss 24(%rsp), %xmm0
mulss %xmm0, %xmm0
subq $8, %rsp
.cfi_def_cfa_offset 136
movl 144(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 144
pushq 144(%rsp)
.cfi_def_cfa_offset 152
pushq 24(%rsp)
.cfi_def_cfa_offset 160
movss 60(%rsp), %xmm1
mulss %xmm1, %xmm1
movq 48(%rsp), %r9
movq 40(%rsp), %r8
movl %r14d, %ecx
movl %ebx, %edx
movl %ebp, %esi
movl %r15d, %edi
call _Z51__device_stub__Z15AggregateKerneliiiiPKfS0_PfS1_ffiiiiiPKfS0_PfS1_ffi
addq $32, %rsp
.cfi_def_cfa_offset 128
jmp .L20
.L24:
movl %r14d, %r9d
movl %ebx, %r8d
movl %ebp, %ecx
movq 128(%rsp), %rdx
movq (%rsp), %rsi
movl %r12d, %edi
call _Z40__device_stub__Z13NormalizationiPfPKfiiiiPfPKfiii
jmp .L19
.cfi_endproc
.LFE2028:
.size _Z17aggregateLauncheriiiPKfS0_PfS1_ffi, .-_Z17aggregateLauncheriiiPKfS0_PfS1_ffi
.globl _Z55__device_stub__Z19AggregateGradKerneliiiiPKfS0_PfS1_ffiiiiiPKfS0_PfS1_ffi
.type _Z55__device_stub__Z19AggregateGradKerneliiiiPKfS0_PfS1_ffiiiiiPKfS0_PfS1_ffi, @function
_Z55__device_stub__Z19AggregateGradKerneliiiiPKfS0_PfS1_ffiiiiiPKfS0_PfS1_ffi:
.LFB2058:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movl %edi, 60(%rsp)
movl %esi, 56(%rsp)
movl %edx, 52(%rsp)
movl %ecx, 48(%rsp)
movq %r8, 40(%rsp)
movq %r9, 32(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movq 240(%rsp), %rax
movq %rax, 24(%rsp)
movq 248(%rsp), %rax
movq %rax, 16(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
leaq 40(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
leaq 24(%rsp), %rax
movq %rax, 176(%rsp)
leaq 16(%rsp), %rax
movq %rax, 184(%rsp)
leaq 12(%rsp), %rax
movq %rax, 192(%rsp)
leaq 8(%rsp), %rax
movq %rax, 200(%rsp)
leaq 256(%rsp), %rax
movq %rax, 208(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z19AggregateGradKerneliiiiPKfS0_PfS1_ffi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z55__device_stub__Z19AggregateGradKerneliiiiPKfS0_PfS1_ffiiiiiPKfS0_PfS1_ffi, .-_Z55__device_stub__Z19AggregateGradKerneliiiiPKfS0_PfS1_ffiiiiiPKfS0_PfS1_ffi
.globl _Z19AggregateGradKerneliiiiPKfS0_PfS1_ffi
.type _Z19AggregateGradKerneliiiiPKfS0_PfS1_ffi, @function
_Z19AggregateGradKerneliiiiPKfS0_PfS1_ffi:
.LFB2059:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z55__device_stub__Z19AggregateGradKerneliiiiPKfS0_PfS1_ffiiiiiPKfS0_PfS1_ffi
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z19AggregateGradKerneliiiiPKfS0_PfS1_ffi, .-_Z19AggregateGradKerneliiiiPKfS0_PfS1_ffi
.globl _Z21aggregategradLauncheriiiPKfS0_S0_PfS1_ffi
.type _Z21aggregategradLauncheriiiPKfS0_S0_PfS1_ffi, @function
_Z21aggregategradLauncheriiiPKfS0_S0_PfS1_ffi:
.LFB2029:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movl %edi, %ebp
movl %esi, %ebx
movl %edx, %r14d
movq %r8, 8(%rsp)
movq %r9, 16(%rsp)
movss %xmm0, 24(%rsp)
movss %xmm1, 28(%rsp)
movl %edi, %r12d
imull %esi, %r12d
movl %r12d, %r15d
imull %esi, %r15d
movslq %edi, %r13
movslq %esi, %rax
imulq %rax, %r13
leaq 0(,%r13,4), %rdx
movl $0, %esi
movq 128(%rsp), %rdi
call cudaMemset@PLT
movslq %r14d, %rax
imulq %r13, %rax
leaq (%rax,%rax,2), %rdx
salq $3, %rdx
movl $0, %esi
movq 136(%rsp), %rdi
call cudaMemset@PLT
movl $512, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
leal 1022(%r15), %eax
movl %r15d, %edx
addl $511, %edx
cmovns %edx, %eax
sarl $9, %eax
movl %eax, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L34:
movl $512, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
leal 1022(%r12), %eax
movl %r12d, %edx
addl $511, %edx
cmovns %edx, %eax
sarl $9, %eax
movl %eax, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L33:
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
movss 24(%rsp), %xmm0
mulss %xmm0, %xmm0
subq $8, %rsp
.cfi_def_cfa_offset 136
movl 152(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 144
pushq 144(%rsp)
.cfi_def_cfa_offset 152
pushq 160(%rsp)
.cfi_def_cfa_offset 160
movss 60(%rsp), %xmm1
mulss %xmm1, %xmm1
movq 40(%rsp), %r9
movq 48(%rsp), %r8
movl %r14d, %ecx
movl %ebx, %edx
movl %ebp, %esi
movl %r15d, %edi
call _Z55__device_stub__Z19AggregateGradKerneliiiiPKfS0_PfS1_ffiiiiiPKfS0_PfS1_ffi
addq $32, %rsp
.cfi_def_cfa_offset 128
jmp .L34
.L38:
leal (%r14,%r14,2), %r9d
addl %r9d, %r9d
movl %ebx, %r8d
movl %ebp, %ecx
movq 128(%rsp), %rdx
movq 136(%rsp), %rsi
movl %r12d, %edi
call _Z40__device_stub__Z13NormalizationiPfPKfiiiiPfPKfiii
jmp .L33
.cfi_endproc
.LFE2029:
.size _Z21aggregategradLauncheriiiPKfS0_S0_PfS1_ffi, .-_Z21aggregategradLauncheriiiPKfS0_S0_PfS1_ffi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19AggregateGradKerneliiiiPKfS0_PfS1_ffi"
.align 8
.LC1:
.string "_Z15AggregateKerneliiiiPKfS0_PfS1_ffi"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z13NormalizationiPfPKfiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2061:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19AggregateGradKerneliiiiPKfS0_PfS1_ffi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z15AggregateKerneliiiiPKfS0_PfS1_ffi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z13NormalizationiPfPKfiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "tf_geoconv_g.hip"
.globl _Z28__device_stub__NormalizationiPfPKfiii # -- Begin function _Z28__device_stub__NormalizationiPfPKfiii
.p2align 4, 0x90
.type _Z28__device_stub__NormalizationiPfPKfiii,@function
_Z28__device_stub__NormalizationiPfPKfiii: # @_Z28__device_stub__NormalizationiPfPKfiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13NormalizationiPfPKfiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z28__device_stub__NormalizationiPfPKfiii, .Lfunc_end0-_Z28__device_stub__NormalizationiPfPKfiii
.cfi_endproc
# -- End function
.globl _Z30__device_stub__AggregateKerneliiiiPKfS0_PfS1_ffi # -- Begin function _Z30__device_stub__AggregateKerneliiiiPKfS0_PfS1_ffi
.p2align 4, 0x90
.type _Z30__device_stub__AggregateKerneliiiiPKfS0_PfS1_ffi,@function
_Z30__device_stub__AggregateKerneliiiiPKfS0_PfS1_ffi: # @_Z30__device_stub__AggregateKerneliiiiPKfS0_PfS1_ffi
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movq %r8, 88(%rsp)
movq %r9, 80(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
leaq 208(%rsp), %rax
movq %rax, 176(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15AggregateKerneliiiiPKfS0_PfS1_ffi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end1:
.size _Z30__device_stub__AggregateKerneliiiiPKfS0_PfS1_ffi, .Lfunc_end1-_Z30__device_stub__AggregateKerneliiiiPKfS0_PfS1_ffi
.cfi_endproc
# -- End function
.globl _Z34__device_stub__AggregateGradKerneliiiiPKfS0_PfS1_ffi # -- Begin function _Z34__device_stub__AggregateGradKerneliiiiPKfS0_PfS1_ffi
.p2align 4, 0x90
.type _Z34__device_stub__AggregateGradKerneliiiiPKfS0_PfS1_ffi,@function
_Z34__device_stub__AggregateGradKerneliiiiPKfS0_PfS1_ffi: # @_Z34__device_stub__AggregateGradKerneliiiiPKfS0_PfS1_ffi
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movq %r8, 88(%rsp)
movq %r9, 80(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
leaq 208(%rsp), %rax
movq %rax, 176(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19AggregateGradKerneliiiiPKfS0_PfS1_ffi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end2:
.size _Z34__device_stub__AggregateGradKerneliiiiPKfS0_PfS1_ffi, .Lfunc_end2-_Z34__device_stub__AggregateGradKerneliiiiPKfS0_PfS1_ffi
.cfi_endproc
# -- End function
.globl _Z17aggregateLauncheriiiPKfS0_PfS1_ffi # -- Begin function _Z17aggregateLauncheriiiPKfS0_PfS1_ffi
.p2align 4, 0x90
.type _Z17aggregateLauncheriiiPKfS0_PfS1_ffi,@function
_Z17aggregateLauncheriiiPKfS0_PfS1_ffi: # @_Z17aggregateLauncheriiiPKfS0_PfS1_ffi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movss %xmm1, 120(%rsp) # 4-byte Spill
movss %xmm0, 116(%rsp) # 4-byte Spill
movq %r9, %rbp
movq %r8, 152(%rsp) # 8-byte Spill
movq %rcx, 144(%rsp) # 8-byte Spill
movl %edx, %r15d
movq 304(%rsp), %rcx
movabsq $4294967296, %r13 # imm = 0x100000000
movl %esi, %r14d
imull %edi, %r14d
movl %r14d, %r12d
imull %esi, %r12d
movl %edi, 20(%rsp) # 4-byte Spill
movslq %edi, %rax
movl %esi, 24(%rsp) # 4-byte Spill
movslq %esi, %rbx
imulq %rax, %rbx
shlq $2, %rbx
movq %rcx, %rdi
xorl %esi, %esi
movq %rbx, %rdx
callq hipMemset
movl %r15d, 28(%rsp) # 4-byte Spill
movslq %r15d, %rdx
imulq %rbx, %rdx
movq %rbp, %rdi
xorl %esi, %esi
callq hipMemset
leal 511(%r12), %eax
leal 1022(%r12), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $9, %edi
orq %r13, %rdi
leaq 512(%r13), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movl 312(%rsp), %eax
movss 116(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm1
movss 120(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
mulss %xmm0, %xmm0
movl %r12d, 16(%rsp)
movl 20(%rsp), %ecx # 4-byte Reload
movl %ecx, 12(%rsp)
movl 24(%rsp), %ecx # 4-byte Reload
movl %ecx, 140(%rsp)
movl 28(%rsp), %ecx # 4-byte Reload
movl %ecx, 136(%rsp)
movq 144(%rsp), %rcx # 8-byte Reload
movq %rcx, 104(%rsp)
movq 152(%rsp), %rcx # 8-byte Reload
movq %rcx, 96(%rsp)
movq %rbp, 56(%rsp)
movq 304(%rsp), %rcx
movq %rcx, 48(%rsp)
movss %xmm1, 132(%rsp)
movss %xmm0, 128(%rsp)
movl %eax, 124(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 140(%rsp), %rax
movq %rax, 176(%rsp)
leaq 136(%rsp), %rax
movq %rax, 184(%rsp)
leaq 104(%rsp), %rax
movq %rax, 192(%rsp)
leaq 96(%rsp), %rax
movq %rax, 200(%rsp)
leaq 56(%rsp), %rax
movq %rax, 208(%rsp)
leaq 48(%rsp), %rax
movq %rax, 216(%rsp)
leaq 132(%rsp), %rax
movq %rax, 224(%rsp)
leaq 128(%rsp), %rax
movq %rax, 232(%rsp)
leaq 124(%rsp), %rax
movq %rax, 240(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z15AggregateKerneliiiiPKfS0_PfS1_ffi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
leal 511(%r14), %eax
leal 1022(%r14), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $9, %edi
orq %r13, %rdi
addq $512, %r13 # imm = 0x200
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3:
movl %r14d, 40(%rsp)
movq %rbp, 104(%rsp)
movq 304(%rsp), %rax
movq %rax, 96(%rsp)
movl 20(%rsp), %eax # 4-byte Reload
movl %eax, 32(%rsp)
movl 24(%rsp), %eax # 4-byte Reload
movl %eax, 16(%rsp)
movl 28(%rsp), %eax # 4-byte Reload
movl %eax, 12(%rsp)
leaq 40(%rsp), %rax
movq %rax, 160(%rsp)
leaq 104(%rsp), %rax
movq %rax, 168(%rsp)
leaq 96(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 16(%rsp), %rax
movq %rax, 192(%rsp)
leaq 12(%rsp), %rax
movq %rax, 200(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z13NormalizationiPfPKfiii, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_4:
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z17aggregateLauncheriiiPKfS0_PfS1_ffi, .Lfunc_end3-_Z17aggregateLauncheriiiPKfS0_PfS1_ffi
.cfi_endproc
# -- End function
.globl _Z21aggregategradLauncheriiiPKfS0_S0_PfS1_ffi # -- Begin function _Z21aggregategradLauncheriiiPKfS0_S0_PfS1_ffi
.p2align 4, 0x90
.type _Z21aggregategradLauncheriiiPKfS0_S0_PfS1_ffi,@function
_Z21aggregategradLauncheriiiPKfS0_S0_PfS1_ffi: # @_Z21aggregategradLauncheriiiPKfS0_S0_PfS1_ffi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movss %xmm1, 112(%rsp) # 4-byte Spill
movss %xmm0, 108(%rsp) # 4-byte Spill
movq %r9, 144(%rsp) # 8-byte Spill
movq %r8, 152(%rsp) # 8-byte Spill
movl %edx, %ebp
movl %esi, %ebx
movq 304(%rsp), %rcx
movabsq $4294967296, %r13 # imm = 0x100000000
movl %esi, %r14d
imull %edi, %r14d
movl %r14d, %r12d
imull %esi, %r12d
movl %edi, 20(%rsp) # 4-byte Spill
movslq %edi, %rax
movslq %esi, %r15
imulq %rax, %r15
shlq $2, %r15
movq %rcx, %rdi
xorl %esi, %esi
movq %r15, %rdx
callq hipMemset
movq %rbp, 136(%rsp) # 8-byte Spill
movslq %ebp, %rax
imulq %r15, %rax
movq 312(%rsp), %r15
addq %rax, %rax
leaq (%rax,%rax,2), %rdx
movq %r15, %rdi
xorl %esi, %esi
callq hipMemset
leal 511(%r12), %eax
leal 1022(%r12), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $9, %edi
orq %r13, %rdi
leaq 512(%r13), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_2
# %bb.1:
movl 320(%rsp), %eax
movss 108(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm1
movss 112(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
mulss %xmm0, %xmm0
movl %r12d, 16(%rsp)
movl 20(%rsp), %ecx # 4-byte Reload
movl %ecx, 12(%rsp)
movl %ebx, 132(%rsp)
movq 136(%rsp), %rcx # 8-byte Reload
movl %ecx, 128(%rsp)
movq 144(%rsp), %rcx # 8-byte Reload
movq %rcx, 96(%rsp)
movq 152(%rsp), %rcx # 8-byte Reload
movq %rcx, 88(%rsp)
movq %r15, 48(%rsp)
movq 304(%rsp), %rcx
movq %rcx, 40(%rsp)
movss %xmm1, 124(%rsp)
movss %xmm0, 120(%rsp)
movl %eax, 116(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 132(%rsp), %rax
movq %rax, 176(%rsp)
leaq 128(%rsp), %rax
movq %rax, 184(%rsp)
leaq 96(%rsp), %rax
movq %rax, 192(%rsp)
leaq 88(%rsp), %rax
movq %rax, 200(%rsp)
leaq 48(%rsp), %rax
movq %rax, 208(%rsp)
leaq 40(%rsp), %rax
movq %rax, 216(%rsp)
leaq 124(%rsp), %rax
movq %rax, 224(%rsp)
leaq 120(%rsp), %rax
movq %rax, 232(%rsp)
leaq 116(%rsp), %rax
movq %rax, 240(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z19AggregateGradKerneliiiiPKfS0_PfS1_ffi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_2:
leal 511(%r14), %eax
leal 1022(%r14), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $9, %edi
orq %r13, %rdi
addq $512, %r13 # imm = 0x200
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_4
# %bb.3:
movq 136(%rsp), %rax # 8-byte Reload
addl %eax, %eax
leal (%rax,%rax,2), %eax
movl %r14d, 32(%rsp)
movq %r15, 96(%rsp)
movq 304(%rsp), %rcx
movq %rcx, 88(%rsp)
movl 20(%rsp), %ecx # 4-byte Reload
movl %ecx, 24(%rsp)
movl %ebx, 16(%rsp)
movl %eax, 12(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 96(%rsp), %rax
movq %rax, 168(%rsp)
leaq 88(%rsp), %rax
movq %rax, 176(%rsp)
leaq 24(%rsp), %rax
movq %rax, 184(%rsp)
leaq 16(%rsp), %rax
movq %rax, 192(%rsp)
leaq 12(%rsp), %rax
movq %rax, 200(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z13NormalizationiPfPKfiii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_4:
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z21aggregategradLauncheriiiPKfS0_S0_PfS1_ffi, .Lfunc_end4-_Z21aggregategradLauncheriiiPKfS0_S0_PfS1_ffi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13NormalizationiPfPKfiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15AggregateKerneliiiiPKfS0_PfS1_ffi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19AggregateGradKerneliiiiPKfS0_PfS1_ffi, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13NormalizationiPfPKfiii,@object # @_Z13NormalizationiPfPKfiii
.section .rodata,"a",@progbits
.globl _Z13NormalizationiPfPKfiii
.p2align 3, 0x0
_Z13NormalizationiPfPKfiii:
.quad _Z28__device_stub__NormalizationiPfPKfiii
.size _Z13NormalizationiPfPKfiii, 8
.type _Z15AggregateKerneliiiiPKfS0_PfS1_ffi,@object # @_Z15AggregateKerneliiiiPKfS0_PfS1_ffi
.globl _Z15AggregateKerneliiiiPKfS0_PfS1_ffi
.p2align 3, 0x0
_Z15AggregateKerneliiiiPKfS0_PfS1_ffi:
.quad _Z30__device_stub__AggregateKerneliiiiPKfS0_PfS1_ffi
.size _Z15AggregateKerneliiiiPKfS0_PfS1_ffi, 8
.type _Z19AggregateGradKerneliiiiPKfS0_PfS1_ffi,@object # @_Z19AggregateGradKerneliiiiPKfS0_PfS1_ffi
.globl _Z19AggregateGradKerneliiiiPKfS0_PfS1_ffi
.p2align 3, 0x0
_Z19AggregateGradKerneliiiiPKfS0_PfS1_ffi:
.quad _Z34__device_stub__AggregateGradKerneliiiiPKfS0_PfS1_ffi
.size _Z19AggregateGradKerneliiiiPKfS0_PfS1_ffi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13NormalizationiPfPKfiii"
.size .L__unnamed_1, 27
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15AggregateKerneliiiiPKfS0_PfS1_ffi"
.size .L__unnamed_2, 38
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z19AggregateGradKerneliiiiPKfS0_PfS1_ffi"
.size .L__unnamed_3, 42
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__NormalizationiPfPKfiii
.addrsig_sym _Z30__device_stub__AggregateKerneliiiiPKfS0_PfS1_ffi
.addrsig_sym _Z34__device_stub__AggregateGradKerneliiiiPKfS0_PfS1_ffi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13NormalizationiPfPKfiii
.addrsig_sym _Z15AggregateKerneliiiiPKfS0_PfS1_ffi
.addrsig_sym _Z19AggregateGradKerneliiiiPKfS0_PfS1_ffi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //#include "cuda_runtime.h"
//#include "device_launch_parameters.h"
//
//#include <iostream>
//#include <time.h>
//
//#include "neural_network.hh"
//#include "layers/linear_layer.hh"
//#include "layers/relu_activation.hh"
//#include "layers/sigmoid_activation.hh"
//#include "nn_utils/nn_exception.hh"
//#include "nn_utils/bce_cost.hh"
//
//#include "coordinates_dataset.hh"
//
//float computeAccuracy(const Matrix& predictions, const Matrix& targets);
//
//int main() {
//
// srand( time(NULL) );
//
// //batch_size=100, number of batches=21, use 20 batches for training and 1 batch for testing(get accuracy score)
// CoordinatesDataset dataset(100, 21);
// BCECost bce_cost;
//
// NeuralNetwork nn;
// //linear layer with 2 input neuron and 30 output/hidden neurons
// nn.addLayer(new LinearLayer("linear_1", Shape(2, 30)));
// nn.addLayer(new ReLUActivation("relu_1"));
// //linear layer with 30 input neurons and 1 output neuron
// nn.addLayer(new LinearLayer("linear_2", Shape(30, 1)));
// nn.addLayer(new SigmoidActivation("sigmoid_output"));
//
// // network training
// Matrix Y;
// for (int epoch = 0; epoch < 1001; epoch++) {
// float cost = 0.0;
//
// for (int batch = 0; batch < dataset.getNumOfBatches() - 1; batch++) {
// //get training batches as input for forward
// Y = nn.forward(dataset.getBatches().at(batch));
// //get label/target batches as input for backprop
// nn.backprop(Y, dataset.getTargets().at(batch));
// cost += bce_cost.cost(Y, dataset.getTargets().at(batch));
// }
//
// if (epoch % 100 == 0) {
// std::cout << "Epoch: " << epoch
// << ", Cost: " << cost / dataset.getNumOfBatches()
// << std::endl;
// }
// }
//
// // compute accuracy
// Y = nn.forward(dataset.getBatches().at(dataset.getNumOfBatches() - 1));
// Y.copyDeviceToHost();
//
// float accuracy = computeAccuracy(
// Y, dataset.getTargets().at(dataset.getNumOfBatches() - 1));
// std::cout << "Accuracy: " << accuracy << std::endl;
//
// return 0;
//}
//
////count number of correctly predicted values and divide it by the size of output vector
//float computeAccuracy(const Matrix& predictions, const Matrix& targets) {
// int m = predictions.shape.x;
// int correct_predictions = 0;
//
// for (int i = 0; i < m; i++) {
// float prediction = predictions[i] > 0.5 ? 1 : 0;
// if (prediction == targets[i]) {
// correct_predictions++;
// }
// }
//
// return static_cast<float>(correct_predictions) / m;
//} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //#include "cuda_runtime.h"
//#include "device_launch_parameters.h"
//
//#include <iostream>
//#include <time.h>
//
//#include "neural_network.hh"
//#include "layers/linear_layer.hh"
//#include "layers/relu_activation.hh"
//#include "layers/sigmoid_activation.hh"
//#include "nn_utils/nn_exception.hh"
//#include "nn_utils/bce_cost.hh"
//
//#include "coordinates_dataset.hh"
//
//float computeAccuracy(const Matrix& predictions, const Matrix& targets);
//
//int main() {
//
// srand( time(NULL) );
//
// //batch_size=100, number of batches=21, use 20 batches for training and 1 batch for testing(get accuracy score)
// CoordinatesDataset dataset(100, 21);
// BCECost bce_cost;
//
// NeuralNetwork nn;
// //linear layer with 2 input neuron and 30 output/hidden neurons
// nn.addLayer(new LinearLayer("linear_1", Shape(2, 30)));
// nn.addLayer(new ReLUActivation("relu_1"));
// //linear layer with 30 input neurons and 1 output neuron
// nn.addLayer(new LinearLayer("linear_2", Shape(30, 1)));
// nn.addLayer(new SigmoidActivation("sigmoid_output"));
//
// // network training
// Matrix Y;
// for (int epoch = 0; epoch < 1001; epoch++) {
// float cost = 0.0;
//
// for (int batch = 0; batch < dataset.getNumOfBatches() - 1; batch++) {
// //get training batches as input for forward
// Y = nn.forward(dataset.getBatches().at(batch));
// //get label/target batches as input for backprop
// nn.backprop(Y, dataset.getTargets().at(batch));
// cost += bce_cost.cost(Y, dataset.getTargets().at(batch));
// }
//
// if (epoch % 100 == 0) {
// std::cout << "Epoch: " << epoch
// << ", Cost: " << cost / dataset.getNumOfBatches()
// << std::endl;
// }
// }
//
// // compute accuracy
// Y = nn.forward(dataset.getBatches().at(dataset.getNumOfBatches() - 1));
// Y.copyDeviceToHost();
//
// float accuracy = computeAccuracy(
// Y, dataset.getTargets().at(dataset.getNumOfBatches() - 1));
// std::cout << "Accuracy: " << accuracy << std::endl;
//
// return 0;
//}
//
////count number of correctly predicted values and divide it by the size of output vector
//float computeAccuracy(const Matrix& predictions, const Matrix& targets) {
// int m = predictions.shape.x;
// int correct_predictions = 0;
//
// for (int i = 0; i < m; i++) {
// float prediction = predictions[i] > 0.5 ? 1 : 0;
// if (prediction == targets[i]) {
// correct_predictions++;
// }
// }
//
// return static_cast<float>(correct_predictions) / m;
//} | .file "tmpxft_00040ec9_00000000-6_main_old.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //#include "cuda_runtime.h"
//#include "device_launch_parameters.h"
//
//#include <iostream>
//#include <time.h>
//
//#include "neural_network.hh"
//#include "layers/linear_layer.hh"
//#include "layers/relu_activation.hh"
//#include "layers/sigmoid_activation.hh"
//#include "nn_utils/nn_exception.hh"
//#include "nn_utils/bce_cost.hh"
//
//#include "coordinates_dataset.hh"
//
//float computeAccuracy(const Matrix& predictions, const Matrix& targets);
//
//int main() {
//
// srand( time(NULL) );
//
// //batch_size=100, number of batches=21, use 20 batches for training and 1 batch for testing(get accuracy score)
// CoordinatesDataset dataset(100, 21);
// BCECost bce_cost;
//
// NeuralNetwork nn;
// //linear layer with 2 input neuron and 30 output/hidden neurons
// nn.addLayer(new LinearLayer("linear_1", Shape(2, 30)));
// nn.addLayer(new ReLUActivation("relu_1"));
// //linear layer with 30 input neurons and 1 output neuron
// nn.addLayer(new LinearLayer("linear_2", Shape(30, 1)));
// nn.addLayer(new SigmoidActivation("sigmoid_output"));
//
// // network training
// Matrix Y;
// for (int epoch = 0; epoch < 1001; epoch++) {
// float cost = 0.0;
//
// for (int batch = 0; batch < dataset.getNumOfBatches() - 1; batch++) {
// //get training batches as input for forward
// Y = nn.forward(dataset.getBatches().at(batch));
// //get label/target batches as input for backprop
// nn.backprop(Y, dataset.getTargets().at(batch));
// cost += bce_cost.cost(Y, dataset.getTargets().at(batch));
// }
//
// if (epoch % 100 == 0) {
// std::cout << "Epoch: " << epoch
// << ", Cost: " << cost / dataset.getNumOfBatches()
// << std::endl;
// }
// }
//
// // compute accuracy
// Y = nn.forward(dataset.getBatches().at(dataset.getNumOfBatches() - 1));
// Y.copyDeviceToHost();
//
// float accuracy = computeAccuracy(
// Y, dataset.getTargets().at(dataset.getNumOfBatches() - 1));
// std::cout << "Accuracy: " << accuracy << std::endl;
//
// return 0;
//}
//
////count number of correctly predicted values and divide it by the size of output vector
//float computeAccuracy(const Matrix& predictions, const Matrix& targets) {
// int m = predictions.shape.x;
// int correct_predictions = 0;
//
// for (int i = 0; i < m; i++) {
// float prediction = predictions[i] > 0.5 ? 1 : 0;
// if (prediction == targets[i]) {
// correct_predictions++;
// }
// }
//
// return static_cast<float>(correct_predictions) / m;
//} | #include <hip/hip_runtime.h>
//#include "cuda_runtime.h"
//#include "device_launch_parameters.h"
//
//#include <iostream>
//#include <time.h>
//
//#include "neural_network.hh"
//#include "layers/linear_layer.hh"
//#include "layers/relu_activation.hh"
//#include "layers/sigmoid_activation.hh"
//#include "nn_utils/nn_exception.hh"
//#include "nn_utils/bce_cost.hh"
//
//#include "coordinates_dataset.hh"
//
//float computeAccuracy(const Matrix& predictions, const Matrix& targets);
//
//int main() {
//
// srand( time(NULL) );
//
// //batch_size=100, number of batches=21, use 20 batches for training and 1 batch for testing(get accuracy score)
// CoordinatesDataset dataset(100, 21);
// BCECost bce_cost;
//
// NeuralNetwork nn;
// //linear layer with 2 input neuron and 30 output/hidden neurons
// nn.addLayer(new LinearLayer("linear_1", Shape(2, 30)));
// nn.addLayer(new ReLUActivation("relu_1"));
// //linear layer with 30 input neurons and 1 output neuron
// nn.addLayer(new LinearLayer("linear_2", Shape(30, 1)));
// nn.addLayer(new SigmoidActivation("sigmoid_output"));
//
// // network training
// Matrix Y;
// for (int epoch = 0; epoch < 1001; epoch++) {
// float cost = 0.0;
//
// for (int batch = 0; batch < dataset.getNumOfBatches() - 1; batch++) {
// //get training batches as input for forward
// Y = nn.forward(dataset.getBatches().at(batch));
// //get label/target batches as input for backprop
// nn.backprop(Y, dataset.getTargets().at(batch));
// cost += bce_cost.cost(Y, dataset.getTargets().at(batch));
// }
//
// if (epoch % 100 == 0) {
// std::cout << "Epoch: " << epoch
// << ", Cost: " << cost / dataset.getNumOfBatches()
// << std::endl;
// }
// }
//
// // compute accuracy
// Y = nn.forward(dataset.getBatches().at(dataset.getNumOfBatches() - 1));
// Y.copyDeviceToHost();
//
// float accuracy = computeAccuracy(
// Y, dataset.getTargets().at(dataset.getNumOfBatches() - 1));
// std::cout << "Accuracy: " << accuracy << std::endl;
//
// return 0;
//}
//
////count number of correctly predicted values and divide it by the size of output vector
//float computeAccuracy(const Matrix& predictions, const Matrix& targets) {
// int m = predictions.shape.x;
// int correct_predictions = 0;
//
// for (int i = 0; i < m; i++) {
// float prediction = predictions[i] > 0.5 ? 1 : 0;
// if (prediction == targets[i]) {
// correct_predictions++;
// }
// }
//
// return static_cast<float>(correct_predictions) / m;
//} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
//#include "cuda_runtime.h"
//#include "device_launch_parameters.h"
//
//#include <iostream>
//#include <time.h>
//
//#include "neural_network.hh"
//#include "layers/linear_layer.hh"
//#include "layers/relu_activation.hh"
//#include "layers/sigmoid_activation.hh"
//#include "nn_utils/nn_exception.hh"
//#include "nn_utils/bce_cost.hh"
//
//#include "coordinates_dataset.hh"
//
//float computeAccuracy(const Matrix& predictions, const Matrix& targets);
//
//int main() {
//
// srand( time(NULL) );
//
// //batch_size=100, number of batches=21, use 20 batches for training and 1 batch for testing(get accuracy score)
// CoordinatesDataset dataset(100, 21);
// BCECost bce_cost;
//
// NeuralNetwork nn;
// //linear layer with 2 input neuron and 30 output/hidden neurons
// nn.addLayer(new LinearLayer("linear_1", Shape(2, 30)));
// nn.addLayer(new ReLUActivation("relu_1"));
// //linear layer with 30 input neurons and 1 output neuron
// nn.addLayer(new LinearLayer("linear_2", Shape(30, 1)));
// nn.addLayer(new SigmoidActivation("sigmoid_output"));
//
// // network training
// Matrix Y;
// for (int epoch = 0; epoch < 1001; epoch++) {
// float cost = 0.0;
//
// for (int batch = 0; batch < dataset.getNumOfBatches() - 1; batch++) {
// //get training batches as input for forward
// Y = nn.forward(dataset.getBatches().at(batch));
// //get label/target batches as input for backprop
// nn.backprop(Y, dataset.getTargets().at(batch));
// cost += bce_cost.cost(Y, dataset.getTargets().at(batch));
// }
//
// if (epoch % 100 == 0) {
// std::cout << "Epoch: " << epoch
// << ", Cost: " << cost / dataset.getNumOfBatches()
// << std::endl;
// }
// }
//
// // compute accuracy
// Y = nn.forward(dataset.getBatches().at(dataset.getNumOfBatches() - 1));
// Y.copyDeviceToHost();
//
// float accuracy = computeAccuracy(
// Y, dataset.getTargets().at(dataset.getNumOfBatches() - 1));
// std::cout << "Accuracy: " << accuracy << std::endl;
//
// return 0;
//}
//
////count number of correctly predicted values and divide it by the size of output vector
//float computeAccuracy(const Matrix& predictions, const Matrix& targets) {
// int m = predictions.shape.x;
// int correct_predictions = 0;
//
// for (int i = 0; i < m; i++) {
// float prediction = predictions[i] > 0.5 ? 1 : 0;
// if (prediction == targets[i]) {
// correct_predictions++;
// }
// }
//
// return static_cast<float>(correct_predictions) / m;
//} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
//#include "cuda_runtime.h"
//#include "device_launch_parameters.h"
//
//#include <iostream>
//#include <time.h>
//
//#include "neural_network.hh"
//#include "layers/linear_layer.hh"
//#include "layers/relu_activation.hh"
//#include "layers/sigmoid_activation.hh"
//#include "nn_utils/nn_exception.hh"
//#include "nn_utils/bce_cost.hh"
//
//#include "coordinates_dataset.hh"
//
//float computeAccuracy(const Matrix& predictions, const Matrix& targets);
//
//int main() {
//
// srand( time(NULL) );
//
// //batch_size=100, number of batches=21, use 20 batches for training and 1 batch for testing(get accuracy score)
// CoordinatesDataset dataset(100, 21);
// BCECost bce_cost;
//
// NeuralNetwork nn;
// //linear layer with 2 input neuron and 30 output/hidden neurons
// nn.addLayer(new LinearLayer("linear_1", Shape(2, 30)));
// nn.addLayer(new ReLUActivation("relu_1"));
// //linear layer with 30 input neurons and 1 output neuron
// nn.addLayer(new LinearLayer("linear_2", Shape(30, 1)));
// nn.addLayer(new SigmoidActivation("sigmoid_output"));
//
// // network training
// Matrix Y;
// for (int epoch = 0; epoch < 1001; epoch++) {
// float cost = 0.0;
//
// for (int batch = 0; batch < dataset.getNumOfBatches() - 1; batch++) {
// //get training batches as input for forward
// Y = nn.forward(dataset.getBatches().at(batch));
// //get label/target batches as input for backprop
// nn.backprop(Y, dataset.getTargets().at(batch));
// cost += bce_cost.cost(Y, dataset.getTargets().at(batch));
// }
//
// if (epoch % 100 == 0) {
// std::cout << "Epoch: " << epoch
// << ", Cost: " << cost / dataset.getNumOfBatches()
// << std::endl;
// }
// }
//
// // compute accuracy
// Y = nn.forward(dataset.getBatches().at(dataset.getNumOfBatches() - 1));
// Y.copyDeviceToHost();
//
// float accuracy = computeAccuracy(
// Y, dataset.getTargets().at(dataset.getNumOfBatches() - 1));
// std::cout << "Accuracy: " << accuracy << std::endl;
//
// return 0;
//}
//
////count number of correctly predicted values and divide it by the size of output vector
//float computeAccuracy(const Matrix& predictions, const Matrix& targets) {
// int m = predictions.shape.x;
// int correct_predictions = 0;
//
// for (int i = 0; i < m; i++) {
// float prediction = predictions[i] > 0.5 ? 1 : 0;
// if (prediction == targets[i]) {
// correct_predictions++;
// }
// }
//
// return static_cast<float>(correct_predictions) / m;
//} | .text
.file "main_old.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00040ec9_00000000-6_main_old.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main_old.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //git hello 0
//biyao test
#include<stdio.h>
//#include<stdlib.h>
//#include<cuda.h>
#include<cuda_runtime.h>//ÌṩÁËʱ¼ä¼ÆËãµÄ¹¦Äܺ¯Êý
__global__ void helloFromGPU(void)
{
printf("Hello World from GPU!\n");
}
int main()
{
printf("Hello world from CPU!\n");
helloFromGPU <<<2,10>>>();
cudaDeviceReset();
return 0;
} | code for sm_80
Function : _Z12helloFromGPUv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //git hello 0
//biyao test
#include<stdio.h>
//#include<stdlib.h>
//#include<cuda.h>
#include<cuda_runtime.h>//ÌṩÁËʱ¼ä¼ÆËãµÄ¹¦Äܺ¯Êý
__global__ void helloFromGPU(void)
{
printf("Hello World from GPU!\n");
}
int main()
{
printf("Hello world from CPU!\n");
helloFromGPU <<<2,10>>>();
cudaDeviceReset();
return 0;
} | .file "tmpxft_00150c45_00000000-6_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z12helloFromGPUvv
.type _Z31__device_stub__Z12helloFromGPUvv, @function
_Z31__device_stub__Z12helloFromGPUvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z12helloFromGPUv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z12helloFromGPUvv, .-_Z31__device_stub__Z12helloFromGPUvv
.globl _Z12helloFromGPUv
.type _Z12helloFromGPUv, @function
_Z12helloFromGPUv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z12helloFromGPUvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12helloFromGPUv, .-_Z12helloFromGPUv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello world from CPU!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $10, 20(%rsp)
movl $1, 24(%rsp)
movl $2, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z31__device_stub__Z12helloFromGPUvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z12helloFromGPUv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z12helloFromGPUv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //git hello 0
//biyao test
#include<stdio.h>
//#include<stdlib.h>
//#include<cuda.h>
#include<cuda_runtime.h>//ÌṩÁËʱ¼ä¼ÆËãµÄ¹¦Äܺ¯Êý
__global__ void helloFromGPU(void)
{
printf("Hello World from GPU!\n");
}
int main()
{
printf("Hello world from CPU!\n");
helloFromGPU <<<2,10>>>();
cudaDeviceReset();
return 0;
} | //git hello 0
//biyao test
#include<stdio.h>
//#include<stdlib.h>
//#include<cuda.h>
#include<hip/hip_runtime.h>//ÌṩÁËʱ¼ä¼ÆËãµÄ¹¦Äܺ¯Êý
__global__ void helloFromGPU(void)
{
printf("Hello World from GPU!\n");
}
int main()
{
printf("Hello world from CPU!\n");
helloFromGPU <<<2,10>>>();
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //git hello 0
//biyao test
#include<stdio.h>
//#include<stdlib.h>
//#include<cuda.h>
#include<hip/hip_runtime.h>//ÌṩÁËʱ¼ä¼ÆËãµÄ¹¦Äܺ¯Êý
__global__ void helloFromGPU(void)
{
printf("Hello World from GPU!\n");
}
int main()
{
printf("Hello world from CPU!\n");
helloFromGPU <<<2,10>>>();
hipDeviceReset();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12helloFromGPUv
.globl _Z12helloFromGPUv
.p2align 8
.type _Z12helloFromGPUv,@function
_Z12helloFromGPUv:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 23
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12helloFromGPUv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12helloFromGPUv, .Lfunc_end0-_Z12helloFromGPUv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "Hello World from GPU!\n"
.size .str, 23
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12helloFromGPUv
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z12helloFromGPUv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //git hello 0
//biyao test
#include<stdio.h>
//#include<stdlib.h>
//#include<cuda.h>
#include<hip/hip_runtime.h>//ÌṩÁËʱ¼ä¼ÆËãµÄ¹¦Äܺ¯Êý
__global__ void helloFromGPU(void)
{
printf("Hello World from GPU!\n");
}
int main()
{
printf("Hello world from CPU!\n");
helloFromGPU <<<2,10>>>();
hipDeviceReset();
return 0;
} | .text
.file "hello.hip"
.globl _Z27__device_stub__helloFromGPUv # -- Begin function _Z27__device_stub__helloFromGPUv
.p2align 4, 0x90
.type _Z27__device_stub__helloFromGPUv,@function
_Z27__device_stub__helloFromGPUv: # @_Z27__device_stub__helloFromGPUv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12helloFromGPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z27__device_stub__helloFromGPUv, .Lfunc_end0-_Z27__device_stub__helloFromGPUv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.Lstr, %edi
callq puts@PLT
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 8(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12helloFromGPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceReset
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12helloFromGPUv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12helloFromGPUv,@object # @_Z12helloFromGPUv
.section .rodata,"a",@progbits
.globl _Z12helloFromGPUv
.p2align 3, 0x0
_Z12helloFromGPUv:
.quad _Z27__device_stub__helloFromGPUv
.size _Z12helloFromGPUv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12helloFromGPUv"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello world from CPU!"
.size .Lstr, 22
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__helloFromGPUv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12helloFromGPUv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12helloFromGPUv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12helloFromGPUv
.globl _Z12helloFromGPUv
.p2align 8
.type _Z12helloFromGPUv,@function
_Z12helloFromGPUv:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 23
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12helloFromGPUv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12helloFromGPUv, .Lfunc_end0-_Z12helloFromGPUv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "Hello World from GPU!\n"
.size .str, 23
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12helloFromGPUv
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z12helloFromGPUv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00150c45_00000000-6_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z12helloFromGPUvv
.type _Z31__device_stub__Z12helloFromGPUvv, @function
_Z31__device_stub__Z12helloFromGPUvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z12helloFromGPUv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z12helloFromGPUvv, .-_Z31__device_stub__Z12helloFromGPUvv
.globl _Z12helloFromGPUv
.type _Z12helloFromGPUv, @function
_Z12helloFromGPUv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z12helloFromGPUvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12helloFromGPUv, .-_Z12helloFromGPUv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello world from CPU!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $10, 20(%rsp)
movl $1, 24(%rsp)
movl $2, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z31__device_stub__Z12helloFromGPUvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z12helloFromGPUv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z12helloFromGPUv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hello.hip"
.globl _Z27__device_stub__helloFromGPUv # -- Begin function _Z27__device_stub__helloFromGPUv
.p2align 4, 0x90
.type _Z27__device_stub__helloFromGPUv,@function
_Z27__device_stub__helloFromGPUv: # @_Z27__device_stub__helloFromGPUv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12helloFromGPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z27__device_stub__helloFromGPUv, .Lfunc_end0-_Z27__device_stub__helloFromGPUv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.Lstr, %edi
callq puts@PLT
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 8(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12helloFromGPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceReset
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12helloFromGPUv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12helloFromGPUv,@object # @_Z12helloFromGPUv
.section .rodata,"a",@progbits
.globl _Z12helloFromGPUv
.p2align 3, 0x0
_Z12helloFromGPUv:
.quad _Z27__device_stub__helloFromGPUv
.size _Z12helloFromGPUv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12helloFromGPUv"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello world from CPU!"
.size .Lstr, 22
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__helloFromGPUv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12helloFromGPUv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
#include <string.h>
//testing commit
//ensure that your code is safeguarded against segmentstion faults etc...
__global__ void cypher_thread(char * t_input, char * t_output, int length){
int idx = threadIdx.x;
if(idx < length){
char c = t_input[idx];
t_output[idx] = c-1;
}
}
int main(){
//initialize test message
const char program_input[] = "Ifmmp-!J!bn!b!tuvefou!ifsf!jo!uif!Dpnqvufs!Tdjfodf!Efqu/!J!kvtu!xboufe!up!dpohsbuvmbuf!zpv!po!zpvs!ofx!qptjujpo!bt!Dibjs!pg!uif!Efqbsunfou/!!Cftu!xjtift/";
int length = strlen(program_input);
int size = length * sizeof(char);
char program_output[length];
//declare GPU memory pointers
char * t_input;
char * t_output;
//allocate memory on GPU
cudaMalloc((void **)&t_input, size);
cudaMalloc((void **)&t_output, size);
//transfer info to GPU
cudaMemcpy(t_input, program_input, size, cudaMemcpyHostToDevice);
//kernel
cypher_thread<<<1, length>>>(t_input, t_output, length);
//get result from GPU
cudaMemcpy(program_output, t_output, size, cudaMemcpyDeviceToHost);
//print output
for(int i = 0; i < length; i++){
printf("%c", program_output[i]);
}
//free gpu memory
cudaFree(t_input);
cudaFree(t_output);
return 0;
} | code for sm_80
Function : _Z13cypher_threadPcS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ SHF.R.S32.HI R0, RZ, 0x1f, R4 ; /* 0x0000001fff007819 */
/* 0x000fe20000011404 */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0060*/ IADD3 R2, P0, R4, c[0x0][0x160], RZ ; /* 0x0000580004027a10 */
/* 0x000fc80007f1e0ff */
/*0070*/ IADD3.X R3, R0, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590000037a10 */
/* 0x000fca00007fe4ff */
/*0080*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1100 */
/*0090*/ IADD3 R4, P0, R4, c[0x0][0x168], RZ ; /* 0x00005a0004047a10 */
/* 0x000fc80007f1e0ff */
/*00a0*/ IADD3.X R5, R0, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0000057a10 */
/* 0x000fe400007fe4ff */
/*00b0*/ IADD3 R7, R2, -0x1, RZ ; /* 0xffffffff02077810 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E.U8 [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101104 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
#include <string.h>
//testing commit
//ensure that your code is safeguarded against segmentstion faults etc...
__global__ void cypher_thread(char * t_input, char * t_output, int length){
int idx = threadIdx.x;
if(idx < length){
char c = t_input[idx];
t_output[idx] = c-1;
}
}
int main(){
//initialize test message
const char program_input[] = "Ifmmp-!J!bn!b!tuvefou!ifsf!jo!uif!Dpnqvufs!Tdjfodf!Efqu/!J!kvtu!xboufe!up!dpohsbuvmbuf!zpv!po!zpvs!ofx!qptjujpo!bt!Dibjs!pg!uif!Efqbsunfou/!!Cftu!xjtift/";
int length = strlen(program_input);
int size = length * sizeof(char);
char program_output[length];
//declare GPU memory pointers
char * t_input;
char * t_output;
//allocate memory on GPU
cudaMalloc((void **)&t_input, size);
cudaMalloc((void **)&t_output, size);
//transfer info to GPU
cudaMemcpy(t_input, program_input, size, cudaMemcpyHostToDevice);
//kernel
cypher_thread<<<1, length>>>(t_input, t_output, length);
//get result from GPU
cudaMemcpy(program_output, t_output, size, cudaMemcpyDeviceToHost);
//print output
for(int i = 0; i < length; i++){
printf("%c", program_output[i]);
}
//free gpu memory
cudaFree(t_input);
cudaFree(t_output);
return 0;
} | .file "tmpxft_00169994_00000000-6_caesar.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z13cypher_threadPcS_iPcS_i
.type _Z36__device_stub__Z13cypher_threadPcS_iPcS_i, @function
_Z36__device_stub__Z13cypher_threadPcS_iPcS_i:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13cypher_threadPcS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z36__device_stub__Z13cypher_threadPcS_iPcS_i, .-_Z36__device_stub__Z13cypher_threadPcS_iPcS_i
.globl _Z13cypher_threadPcS_i
.type _Z13cypher_threadPcS_i, @function
_Z13cypher_threadPcS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z13cypher_threadPcS_iPcS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z13cypher_threadPcS_i, .-_Z13cypher_threadPcS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%c"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $384, %rsp
.cfi_def_cfa_offset 416
movq %fs:40, %rax
movq %rax, 376(%rsp)
xorl %eax, %eax
movabsq $5341600593933592137, %rax
movabsq $8463426305087398433, %rdx
movq %rax, 208(%rsp)
movq %rdx, 216(%rsp)
movabsq $7379466252687140214, %rax
movabsq $7599016708663240307, %rdx
movq %rax, 224(%rsp)
movq %rdx, 232(%rsp)
movabsq $8464077268833280358, %rax
movabsq $8027220364975240038, %rdx
movq %rax, 240(%rsp)
movq %rdx, 248(%rsp)
movabsq $3419764176118179428, %rax
movabsq $2410961227479075361, %rdx
movq %rax, 256(%rsp)
movq %rdx, 264(%rsp)
movabsq $8440138667400323704, %rax
movabsq $7094128665874932080, %rdx
movq %rax, 272(%rsp)
movq %rdx, 280(%rsp)
movabsq $8800427801207207541, %rax
movabsq $8104827241912956528, %rdx
movq %rax, 288(%rsp)
movq %rdx, 296(%rsp)
movabsq $8151929181863768950, %rax
movabsq $2409267928205259888, %rdx
movq %rax, 304(%rsp)
movq %rdx, 312(%rsp)
movabsq $8316567866147173474, %rax
movabsq $2406727002668625953, %rdx
movq %rax, 320(%rsp)
movq %rdx, 328(%rsp)
movabsq $7380965977740109381, %rax
movabsq $8387465165593867631, %rdx
movq %rax, 336(%rsp)
movq %rdx, 344(%rsp)
movabsq $2410961158088499503, %rax
movabsq $13357307110124152, %rdx
movq %rax, 346(%rsp)
movq %rdx, 354(%rsp)
leaq 8(%rsp), %rdi
movl $153, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $153, %esi
call cudaMalloc@PLT
leaq 208(%rsp), %rsi
movl $1, %ecx
movl $153, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $153, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
leaq 48(%rsp), %rbx
movl $2, %ecx
movl $153, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 201(%rsp), %r12
leaq .LC0(%rip), %rbp
.L13:
movsbl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %r12, %rbx
jne .L13
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 376(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $384, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movl $153, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z36__device_stub__Z13cypher_threadPcS_iPcS_i
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z13cypher_threadPcS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z13cypher_threadPcS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
#include <string.h>
//testing commit
//ensure that your code is safeguarded against segmentstion faults etc...
__global__ void cypher_thread(char * t_input, char * t_output, int length){
int idx = threadIdx.x;
if(idx < length){
char c = t_input[idx];
t_output[idx] = c-1;
}
}
int main(){
//initialize test message
const char program_input[] = "Ifmmp-!J!bn!b!tuvefou!ifsf!jo!uif!Dpnqvufs!Tdjfodf!Efqu/!J!kvtu!xboufe!up!dpohsbuvmbuf!zpv!po!zpvs!ofx!qptjujpo!bt!Dibjs!pg!uif!Efqbsunfou/!!Cftu!xjtift/";
int length = strlen(program_input);
int size = length * sizeof(char);
char program_output[length];
//declare GPU memory pointers
char * t_input;
char * t_output;
//allocate memory on GPU
cudaMalloc((void **)&t_input, size);
cudaMalloc((void **)&t_output, size);
//transfer info to GPU
cudaMemcpy(t_input, program_input, size, cudaMemcpyHostToDevice);
//kernel
cypher_thread<<<1, length>>>(t_input, t_output, length);
//get result from GPU
cudaMemcpy(program_output, t_output, size, cudaMemcpyDeviceToHost);
//print output
for(int i = 0; i < length; i++){
printf("%c", program_output[i]);
}
//free gpu memory
cudaFree(t_input);
cudaFree(t_output);
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <string.h>
//testing commit
//ensure that your code is safeguarded against segmentstion faults etc...
__global__ void cypher_thread(char * t_input, char * t_output, int length){
int idx = threadIdx.x;
if(idx < length){
char c = t_input[idx];
t_output[idx] = c-1;
}
}
int main(){
//initialize test message
const char program_input[] = "Ifmmp-!J!bn!b!tuvefou!ifsf!jo!uif!Dpnqvufs!Tdjfodf!Efqu/!J!kvtu!xboufe!up!dpohsbuvmbuf!zpv!po!zpvs!ofx!qptjujpo!bt!Dibjs!pg!uif!Efqbsunfou/!!Cftu!xjtift/";
int length = strlen(program_input);
int size = length * sizeof(char);
char program_output[length];
//declare GPU memory pointers
char * t_input;
char * t_output;
//allocate memory on GPU
hipMalloc((void **)&t_input, size);
hipMalloc((void **)&t_output, size);
//transfer info to GPU
hipMemcpy(t_input, program_input, size, hipMemcpyHostToDevice);
//kernel
cypher_thread<<<1, length>>>(t_input, t_output, length);
//get result from GPU
hipMemcpy(program_output, t_output, size, hipMemcpyDeviceToHost);
//print output
for(int i = 0; i < length; i++){
printf("%c", program_output[i]);
}
//free gpu memory
hipFree(t_input);
hipFree(t_output);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <string.h>
//testing commit
//ensure that your code is safeguarded against segmentstion faults etc...
__global__ void cypher_thread(char * t_input, char * t_output, int length){
int idx = threadIdx.x;
if(idx < length){
char c = t_input[idx];
t_output[idx] = c-1;
}
}
int main(){
//initialize test message
const char program_input[] = "Ifmmp-!J!bn!b!tuvefou!ifsf!jo!uif!Dpnqvufs!Tdjfodf!Efqu/!J!kvtu!xboufe!up!dpohsbuvmbuf!zpv!po!zpvs!ofx!qptjujpo!bt!Dibjs!pg!uif!Efqbsunfou/!!Cftu!xjtift/";
int length = strlen(program_input);
int size = length * sizeof(char);
char program_output[length];
//declare GPU memory pointers
char * t_input;
char * t_output;
//allocate memory on GPU
hipMalloc((void **)&t_input, size);
hipMalloc((void **)&t_output, size);
//transfer info to GPU
hipMemcpy(t_input, program_input, size, hipMemcpyHostToDevice);
//kernel
cypher_thread<<<1, length>>>(t_input, t_output, length);
//get result from GPU
hipMemcpy(program_output, t_output, size, hipMemcpyDeviceToHost);
//print output
for(int i = 0; i < length; i++){
printf("%c", program_output[i]);
}
//free gpu memory
hipFree(t_input);
hipFree(t_output);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13cypher_threadPcS_i
.globl _Z13cypher_threadPcS_i
.p2align 8
.type _Z13cypher_threadPcS_i,@function
_Z13cypher_threadPcS_i:
s_load_b32 s2, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
global_load_u8 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u16 v1, v1, -1
global_store_b8 v0, v1, s[2:3]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13cypher_threadPcS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13cypher_threadPcS_i, .Lfunc_end0-_Z13cypher_threadPcS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13cypher_threadPcS_i
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z13cypher_threadPcS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <string.h>
//testing commit
//ensure that your code is safeguarded against segmentstion faults etc...
__global__ void cypher_thread(char * t_input, char * t_output, int length){
int idx = threadIdx.x;
if(idx < length){
char c = t_input[idx];
t_output[idx] = c-1;
}
}
int main(){
//initialize test message
const char program_input[] = "Ifmmp-!J!bn!b!tuvefou!ifsf!jo!uif!Dpnqvufs!Tdjfodf!Efqu/!J!kvtu!xboufe!up!dpohsbuvmbuf!zpv!po!zpvs!ofx!qptjujpo!bt!Dibjs!pg!uif!Efqbsunfou/!!Cftu!xjtift/";
int length = strlen(program_input);
int size = length * sizeof(char);
char program_output[length];
//declare GPU memory pointers
char * t_input;
char * t_output;
//allocate memory on GPU
hipMalloc((void **)&t_input, size);
hipMalloc((void **)&t_output, size);
//transfer info to GPU
hipMemcpy(t_input, program_input, size, hipMemcpyHostToDevice);
//kernel
cypher_thread<<<1, length>>>(t_input, t_output, length);
//get result from GPU
hipMemcpy(program_output, t_output, size, hipMemcpyDeviceToHost);
//print output
for(int i = 0; i < length; i++){
printf("%c", program_output[i]);
}
//free gpu memory
hipFree(t_input);
hipFree(t_output);
return 0;
} | .text
.file "caesar.hip"
.globl _Z28__device_stub__cypher_threadPcS_i # -- Begin function _Z28__device_stub__cypher_threadPcS_i
.p2align 4, 0x90
.type _Z28__device_stub__cypher_threadPcS_i,@function
_Z28__device_stub__cypher_threadPcS_i: # @_Z28__device_stub__cypher_threadPcS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13cypher_threadPcS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z28__device_stub__cypher_threadPcS_i, .Lfunc_end0-_Z28__device_stub__cypher_threadPcS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $456, %rsp # imm = 0x1C8
.cfi_def_cfa_offset 480
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 288(%rsp), %rbx
movl $.L__const.main.program_input, %esi
movl $154, %edx
movq %rbx, %rdi
callq memcpy@PLT
movq %rsp, %r14
leaq 16(%rsp), %rdi
movl $153, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $153, %esi
callq hipMalloc
movq 16(%rsp), %rdi
movl $153, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 152(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $153, 28(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13cypher_threadPcS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
leaq 128(%rsp), %rdi
movl $153, %edx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movsbl 128(%rsp,%rbx), %edi
callq putchar@PLT
incq %rbx
cmpq $153, %rbx
jne .LBB1_3
# %bb.4:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %r14, %rsp
xorl %eax, %eax
addq $456, %rsp # imm = 0x1C8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13cypher_threadPcS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13cypher_threadPcS_i,@object # @_Z13cypher_threadPcS_i
.section .rodata,"a",@progbits
.globl _Z13cypher_threadPcS_i
.p2align 3, 0x0
_Z13cypher_threadPcS_i:
.quad _Z28__device_stub__cypher_threadPcS_i
.size _Z13cypher_threadPcS_i, 8
.type .L__const.main.program_input,@object # @__const.main.program_input
.section .rodata.str1.16,"aMS",@progbits,1
.p2align 4, 0x0
.L__const.main.program_input:
.asciz "Ifmmp-!J!bn!b!tuvefou!ifsf!jo!uif!Dpnqvufs!Tdjfodf!Efqu/!J!kvtu!xboufe!up!dpohsbuvmbuf!zpv!po!zpvs!ofx!qptjujpo!bt!Dibjs!pg!uif!Efqbsunfou/!!Cftu!xjtift/"
.size .L__const.main.program_input, 154
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13cypher_threadPcS_i"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__cypher_threadPcS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13cypher_threadPcS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13cypher_threadPcS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ SHF.R.S32.HI R0, RZ, 0x1f, R4 ; /* 0x0000001fff007819 */
/* 0x000fe20000011404 */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0060*/ IADD3 R2, P0, R4, c[0x0][0x160], RZ ; /* 0x0000580004027a10 */
/* 0x000fc80007f1e0ff */
/*0070*/ IADD3.X R3, R0, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590000037a10 */
/* 0x000fca00007fe4ff */
/*0080*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1100 */
/*0090*/ IADD3 R4, P0, R4, c[0x0][0x168], RZ ; /* 0x00005a0004047a10 */
/* 0x000fc80007f1e0ff */
/*00a0*/ IADD3.X R5, R0, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0000057a10 */
/* 0x000fe400007fe4ff */
/*00b0*/ IADD3 R7, R2, -0x1, RZ ; /* 0xffffffff02077810 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E.U8 [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101104 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13cypher_threadPcS_i
.globl _Z13cypher_threadPcS_i
.p2align 8
.type _Z13cypher_threadPcS_i,@function
_Z13cypher_threadPcS_i:
s_load_b32 s2, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
global_load_u8 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u16 v1, v1, -1
global_store_b8 v0, v1, s[2:3]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13cypher_threadPcS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13cypher_threadPcS_i, .Lfunc_end0-_Z13cypher_threadPcS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13cypher_threadPcS_i
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z13cypher_threadPcS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00169994_00000000-6_caesar.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z13cypher_threadPcS_iPcS_i
.type _Z36__device_stub__Z13cypher_threadPcS_iPcS_i, @function
_Z36__device_stub__Z13cypher_threadPcS_iPcS_i:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13cypher_threadPcS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z36__device_stub__Z13cypher_threadPcS_iPcS_i, .-_Z36__device_stub__Z13cypher_threadPcS_iPcS_i
.globl _Z13cypher_threadPcS_i
.type _Z13cypher_threadPcS_i, @function
_Z13cypher_threadPcS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z13cypher_threadPcS_iPcS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z13cypher_threadPcS_i, .-_Z13cypher_threadPcS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%c"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $384, %rsp
.cfi_def_cfa_offset 416
movq %fs:40, %rax
movq %rax, 376(%rsp)
xorl %eax, %eax
movabsq $5341600593933592137, %rax
movabsq $8463426305087398433, %rdx
movq %rax, 208(%rsp)
movq %rdx, 216(%rsp)
movabsq $7379466252687140214, %rax
movabsq $7599016708663240307, %rdx
movq %rax, 224(%rsp)
movq %rdx, 232(%rsp)
movabsq $8464077268833280358, %rax
movabsq $8027220364975240038, %rdx
movq %rax, 240(%rsp)
movq %rdx, 248(%rsp)
movabsq $3419764176118179428, %rax
movabsq $2410961227479075361, %rdx
movq %rax, 256(%rsp)
movq %rdx, 264(%rsp)
movabsq $8440138667400323704, %rax
movabsq $7094128665874932080, %rdx
movq %rax, 272(%rsp)
movq %rdx, 280(%rsp)
movabsq $8800427801207207541, %rax
movabsq $8104827241912956528, %rdx
movq %rax, 288(%rsp)
movq %rdx, 296(%rsp)
movabsq $8151929181863768950, %rax
movabsq $2409267928205259888, %rdx
movq %rax, 304(%rsp)
movq %rdx, 312(%rsp)
movabsq $8316567866147173474, %rax
movabsq $2406727002668625953, %rdx
movq %rax, 320(%rsp)
movq %rdx, 328(%rsp)
movabsq $7380965977740109381, %rax
movabsq $8387465165593867631, %rdx
movq %rax, 336(%rsp)
movq %rdx, 344(%rsp)
movabsq $2410961158088499503, %rax
movabsq $13357307110124152, %rdx
movq %rax, 346(%rsp)
movq %rdx, 354(%rsp)
leaq 8(%rsp), %rdi
movl $153, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $153, %esi
call cudaMalloc@PLT
leaq 208(%rsp), %rsi
movl $1, %ecx
movl $153, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $153, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
leaq 48(%rsp), %rbx
movl $2, %ecx
movl $153, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 201(%rsp), %r12
leaq .LC0(%rip), %rbp
.L13:
movsbl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %r12, %rbx
jne .L13
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 376(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $384, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movl $153, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z36__device_stub__Z13cypher_threadPcS_iPcS_i
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z13cypher_threadPcS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z13cypher_threadPcS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "caesar.hip"
.globl _Z28__device_stub__cypher_threadPcS_i # -- Begin function _Z28__device_stub__cypher_threadPcS_i
.p2align 4, 0x90
.type _Z28__device_stub__cypher_threadPcS_i,@function
_Z28__device_stub__cypher_threadPcS_i: # @_Z28__device_stub__cypher_threadPcS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13cypher_threadPcS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z28__device_stub__cypher_threadPcS_i, .Lfunc_end0-_Z28__device_stub__cypher_threadPcS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $456, %rsp # imm = 0x1C8
.cfi_def_cfa_offset 480
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 288(%rsp), %rbx
movl $.L__const.main.program_input, %esi
movl $154, %edx
movq %rbx, %rdi
callq memcpy@PLT
movq %rsp, %r14
leaq 16(%rsp), %rdi
movl $153, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $153, %esi
callq hipMalloc
movq 16(%rsp), %rdi
movl $153, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 152(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $153, 28(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13cypher_threadPcS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
leaq 128(%rsp), %rdi
movl $153, %edx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movsbl 128(%rsp,%rbx), %edi
callq putchar@PLT
incq %rbx
cmpq $153, %rbx
jne .LBB1_3
# %bb.4:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %r14, %rsp
xorl %eax, %eax
addq $456, %rsp # imm = 0x1C8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13cypher_threadPcS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13cypher_threadPcS_i,@object # @_Z13cypher_threadPcS_i
.section .rodata,"a",@progbits
.globl _Z13cypher_threadPcS_i
.p2align 3, 0x0
_Z13cypher_threadPcS_i:
.quad _Z28__device_stub__cypher_threadPcS_i
.size _Z13cypher_threadPcS_i, 8
.type .L__const.main.program_input,@object # @__const.main.program_input
.section .rodata.str1.16,"aMS",@progbits,1
.p2align 4, 0x0
.L__const.main.program_input:
.asciz "Ifmmp-!J!bn!b!tuvefou!ifsf!jo!uif!Dpnqvufs!Tdjfodf!Efqu/!J!kvtu!xboufe!up!dpohsbuvmbuf!zpv!po!zpvs!ofx!qptjujpo!bt!Dibjs!pg!uif!Efqbsunfou/!!Cftu!xjtift/"
.size .L__const.main.program_input, 154
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13cypher_threadPcS_i"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__cypher_threadPcS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13cypher_threadPcS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void sum_kernel(float *g_odata, float *g_idata, int n)
{
// the size is determined by the host application
extern __shared__ float sdata[];
// access thread id
const unsigned int tid = threadIdx.x;
// access number of threads in this block
//const unsigned int num_threads = blockDim.x;
// read in input data from global memory
sdata[2*tid] = g_idata[2*tid];
sdata[2*tid+1] = g_idata[2*tid+1];
// printf ("KERNEL: sdata[%d] = %f\n", (2*tid), sdata[2*tid]);
// printf ("KERNEL: sdata[%d] = %f\n", (2*tid), sdata[2*tid+1]);
__syncthreads();
// perform some computations
sdata[2*tid] = sdata[2*tid] + sdata[2*tid+1];
__syncthreads();
g_odata[tid] = sdata[tid];
} | code for sm_80
Function : _Z10sum_kernelPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ SHF.L.U32 R2, R11, 0x1, RZ ; /* 0x000000010b027819 */
/* 0x001fd000000006ff */
/*0050*/ IMAD.WIDE.U32 R2, R2, R8, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0008 */
/*0060*/ LDG.E R7, [R2.64+0x4] ; /* 0x0000040402077981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea8000c1e1900 */
/*0080*/ STS.64 [R11.X8], R6 ; /* 0x000000060b007388 */
/* 0x004fe80000008a00 */
/*0090*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00a0*/ LDS.64 R4, [R11.X8] ; /* 0x000000000b047984 */
/* 0x000e240000008a00 */
/*00b0*/ FADD R0, R4, R5 ; /* 0x0000000504007221 */
/* 0x001fc40000000000 */
/*00c0*/ IMAD.WIDE.U32 R4, R11, R8, c[0x0][0x160] ; /* 0x000058000b047625 */
/* 0x000fc600078e0008 */
/*00d0*/ STS [R11.X8], R0 ; /* 0x000000000b007388 */
/* 0x000fe80000008800 */
/*00e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00f0*/ LDS R9, [R11.X4] ; /* 0x000000000b097984 */
/* 0x000e280000004800 */
/*0100*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x001fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void sum_kernel(float *g_odata, float *g_idata, int n)
{
// the size is determined by the host application
extern __shared__ float sdata[];
// access thread id
const unsigned int tid = threadIdx.x;
// access number of threads in this block
//const unsigned int num_threads = blockDim.x;
// read in input data from global memory
sdata[2*tid] = g_idata[2*tid];
sdata[2*tid+1] = g_idata[2*tid+1];
// printf ("KERNEL: sdata[%d] = %f\n", (2*tid), sdata[2*tid]);
// printf ("KERNEL: sdata[%d] = %f\n", (2*tid), sdata[2*tid+1]);
__syncthreads();
// perform some computations
sdata[2*tid] = sdata[2*tid] + sdata[2*tid+1];
__syncthreads();
g_odata[tid] = sdata[tid];
} | .file "tmpxft_00118be8_00000000-6_sum_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z10sum_kernelPfS_iPfS_i
.type _Z33__device_stub__Z10sum_kernelPfS_iPfS_i, @function
_Z33__device_stub__Z10sum_kernelPfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10sum_kernelPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z10sum_kernelPfS_iPfS_i, .-_Z33__device_stub__Z10sum_kernelPfS_iPfS_i
.globl _Z10sum_kernelPfS_i
.type _Z10sum_kernelPfS_i, @function
_Z10sum_kernelPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10sum_kernelPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10sum_kernelPfS_i, .-_Z10sum_kernelPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10sum_kernelPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10sum_kernelPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void sum_kernel(float *g_odata, float *g_idata, int n)
{
// the size is determined by the host application
extern __shared__ float sdata[];
// access thread id
const unsigned int tid = threadIdx.x;
// access number of threads in this block
//const unsigned int num_threads = blockDim.x;
// read in input data from global memory
sdata[2*tid] = g_idata[2*tid];
sdata[2*tid+1] = g_idata[2*tid+1];
// printf ("KERNEL: sdata[%d] = %f\n", (2*tid), sdata[2*tid]);
// printf ("KERNEL: sdata[%d] = %f\n", (2*tid), sdata[2*tid+1]);
__syncthreads();
// perform some computations
sdata[2*tid] = sdata[2*tid] + sdata[2*tid+1];
__syncthreads();
g_odata[tid] = sdata[tid];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sum_kernel(float *g_odata, float *g_idata, int n)
{
// the size is determined by the host application
extern __shared__ float sdata[];
// access thread id
const unsigned int tid = threadIdx.x;
// access number of threads in this block
//const unsigned int num_threads = blockDim.x;
// read in input data from global memory
sdata[2*tid] = g_idata[2*tid];
sdata[2*tid+1] = g_idata[2*tid+1];
// printf ("KERNEL: sdata[%d] = %f\n", (2*tid), sdata[2*tid]);
// printf ("KERNEL: sdata[%d] = %f\n", (2*tid), sdata[2*tid+1]);
__syncthreads();
// perform some computations
sdata[2*tid] = sdata[2*tid] + sdata[2*tid+1];
__syncthreads();
g_odata[tid] = sdata[tid];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sum_kernel(float *g_odata, float *g_idata, int n)
{
// the size is determined by the host application
extern __shared__ float sdata[];
// access thread id
const unsigned int tid = threadIdx.x;
// access number of threads in this block
//const unsigned int num_threads = blockDim.x;
// read in input data from global memory
sdata[2*tid] = g_idata[2*tid];
sdata[2*tid+1] = g_idata[2*tid+1];
// printf ("KERNEL: sdata[%d] = %f\n", (2*tid), sdata[2*tid]);
// printf ("KERNEL: sdata[%d] = %f\n", (2*tid), sdata[2*tid+1]);
__syncthreads();
// perform some computations
sdata[2*tid] = sdata[2*tid] + sdata[2*tid+1];
__syncthreads();
g_odata[tid] = sdata[tid];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10sum_kernelPfS_i
.globl _Z10sum_kernelPfS_i
.p2align 8
.type _Z10sum_kernelPfS_i,@function
_Z10sum_kernelPfS_i:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 3, v0
v_lshlrev_b32_e32 v0, 2, v0
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v2, 4, v1
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v3, v1, s[2:3]
global_load_b32 v4, v2, s[2:3]
v_add_nc_u32_e32 v1, 0, v1
v_add_nc_u32_e32 v2, 0, v2
s_waitcnt vmcnt(1)
ds_store_b32 v1, v3
s_waitcnt vmcnt(0)
ds_store_b32 v2, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v1
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
v_dual_add_f32 v2, v3, v2 :: v_dual_add_nc_u32 v3, 0, v0
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v1, v3
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10sum_kernelPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10sum_kernelPfS_i, .Lfunc_end0-_Z10sum_kernelPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10sum_kernelPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z10sum_kernelPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sum_kernel(float *g_odata, float *g_idata, int n)
{
// the size is determined by the host application
extern __shared__ float sdata[];
// access thread id
const unsigned int tid = threadIdx.x;
// access number of threads in this block
//const unsigned int num_threads = blockDim.x;
// read in input data from global memory
sdata[2*tid] = g_idata[2*tid];
sdata[2*tid+1] = g_idata[2*tid+1];
// printf ("KERNEL: sdata[%d] = %f\n", (2*tid), sdata[2*tid]);
// printf ("KERNEL: sdata[%d] = %f\n", (2*tid), sdata[2*tid+1]);
__syncthreads();
// perform some computations
sdata[2*tid] = sdata[2*tid] + sdata[2*tid+1];
__syncthreads();
g_odata[tid] = sdata[tid];
} | .text
.file "sum_kernel.hip"
.globl _Z25__device_stub__sum_kernelPfS_i # -- Begin function _Z25__device_stub__sum_kernelPfS_i
.p2align 4, 0x90
.type _Z25__device_stub__sum_kernelPfS_i,@function
_Z25__device_stub__sum_kernelPfS_i: # @_Z25__device_stub__sum_kernelPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10sum_kernelPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__sum_kernelPfS_i, .Lfunc_end0-_Z25__device_stub__sum_kernelPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10sum_kernelPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10sum_kernelPfS_i,@object # @_Z10sum_kernelPfS_i
.section .rodata,"a",@progbits
.globl _Z10sum_kernelPfS_i
.p2align 3, 0x0
_Z10sum_kernelPfS_i:
.quad _Z25__device_stub__sum_kernelPfS_i
.size _Z10sum_kernelPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10sum_kernelPfS_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__sum_kernelPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10sum_kernelPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10sum_kernelPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ SHF.L.U32 R2, R11, 0x1, RZ ; /* 0x000000010b027819 */
/* 0x001fd000000006ff */
/*0050*/ IMAD.WIDE.U32 R2, R2, R8, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0008 */
/*0060*/ LDG.E R7, [R2.64+0x4] ; /* 0x0000040402077981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea8000c1e1900 */
/*0080*/ STS.64 [R11.X8], R6 ; /* 0x000000060b007388 */
/* 0x004fe80000008a00 */
/*0090*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00a0*/ LDS.64 R4, [R11.X8] ; /* 0x000000000b047984 */
/* 0x000e240000008a00 */
/*00b0*/ FADD R0, R4, R5 ; /* 0x0000000504007221 */
/* 0x001fc40000000000 */
/*00c0*/ IMAD.WIDE.U32 R4, R11, R8, c[0x0][0x160] ; /* 0x000058000b047625 */
/* 0x000fc600078e0008 */
/*00d0*/ STS [R11.X8], R0 ; /* 0x000000000b007388 */
/* 0x000fe80000008800 */
/*00e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00f0*/ LDS R9, [R11.X4] ; /* 0x000000000b097984 */
/* 0x000e280000004800 */
/*0100*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x001fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10sum_kernelPfS_i
.globl _Z10sum_kernelPfS_i
.p2align 8
.type _Z10sum_kernelPfS_i,@function
_Z10sum_kernelPfS_i:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 3, v0
v_lshlrev_b32_e32 v0, 2, v0
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v2, 4, v1
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v3, v1, s[2:3]
global_load_b32 v4, v2, s[2:3]
v_add_nc_u32_e32 v1, 0, v1
v_add_nc_u32_e32 v2, 0, v2
s_waitcnt vmcnt(1)
ds_store_b32 v1, v3
s_waitcnt vmcnt(0)
ds_store_b32 v2, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v1
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
v_dual_add_f32 v2, v3, v2 :: v_dual_add_nc_u32 v3, 0, v0
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v1, v3
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10sum_kernelPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10sum_kernelPfS_i, .Lfunc_end0-_Z10sum_kernelPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10sum_kernelPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z10sum_kernelPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00118be8_00000000-6_sum_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z10sum_kernelPfS_iPfS_i
.type _Z33__device_stub__Z10sum_kernelPfS_iPfS_i, @function
_Z33__device_stub__Z10sum_kernelPfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10sum_kernelPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z10sum_kernelPfS_iPfS_i, .-_Z33__device_stub__Z10sum_kernelPfS_iPfS_i
.globl _Z10sum_kernelPfS_i
.type _Z10sum_kernelPfS_i, @function
_Z10sum_kernelPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10sum_kernelPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10sum_kernelPfS_i, .-_Z10sum_kernelPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10sum_kernelPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10sum_kernelPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sum_kernel.hip"
.globl _Z25__device_stub__sum_kernelPfS_i # -- Begin function _Z25__device_stub__sum_kernelPfS_i
.p2align 4, 0x90
.type _Z25__device_stub__sum_kernelPfS_i,@function
_Z25__device_stub__sum_kernelPfS_i: # @_Z25__device_stub__sum_kernelPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10sum_kernelPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__sum_kernelPfS_i, .Lfunc_end0-_Z25__device_stub__sum_kernelPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10sum_kernelPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10sum_kernelPfS_i,@object # @_Z10sum_kernelPfS_i
.section .rodata,"a",@progbits
.globl _Z10sum_kernelPfS_i
.p2align 3, 0x0
_Z10sum_kernelPfS_i:
.quad _Z25__device_stub__sum_kernelPfS_i
.size _Z10sum_kernelPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10sum_kernelPfS_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__sum_kernelPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10sum_kernelPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
__global__ void suma_vectores_cubo(int *d_v1, int *d_v2, int *d_vr)
{
int id_vector = blockIdx.x * 8 + threadIdx.x;
printf("Id: %d\n", id_vector);
d_vr[id_vector] = d_v1[id_vector] + d_v2[id_vector];
}
int main()
{
// Variables de tamaños
const int ARRAY_SIZE = 24;
const int ARRAY_BYTES = 24 * sizeof(int);
// Declaro vectores y vector resultado
int h_v1[ARRAY_SIZE];
int h_v2[ARRAY_SIZE];
int h_vr[ARRAY_SIZE];
// Relleno v1 y v2:
for (int i = 0; i < ARRAY_SIZE; i++)
{
h_v1[i] = i;
h_v2[i] = i;
h_vr[i] = 0;
}
// Declaro punteros a memoria GPU
int * d_v1;
int * d_v2;
int * d_vr;
// Asigno memoria GPU
cudaMalloc((void**)&d_v1, ARRAY_BYTES);
cudaMalloc((void**)&d_v2, ARRAY_BYTES);
cudaMalloc((void**)&d_vr, ARRAY_BYTES);
// Transfiero los arrays a la GPU:
cudaMemcpy(d_v1, h_v1, ARRAY_BYTES, cudaMemcpyHostToDevice);
cudaMemcpy(d_v2, h_v2, ARRAY_BYTES, cudaMemcpyHostToDevice);
cudaMemcpy(d_vr, h_vr, ARRAY_BYTES, cudaMemcpyHostToDevice);
// Lanzo el kernel
suma_vectores_cubo <<< 3, 8 >>> (d_v1, d_v2, d_vr);
// Copio el resultado al HOST:
cudaMemcpy(h_vr, d_vr, ARRAY_BYTES, cudaMemcpyDeviceToHost);
for (int i = 0; i < ARRAY_SIZE; i++)
{
printf("V[%d]: %d\n", i, h_vr[i]);
}
return 0;
} | code for sm_80
Function : _Z18suma_vectores_cuboPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*0070*/ ULDC.64 UR36, c[0x0][0x118] ; /* 0x0000460000247ab9 */
/* 0x000fe20000000a00 */
/*0080*/ LDC.64 R8, c[0x4][R0] ; /* 0x0100000000087b82 */
/* 0x0002a20000000a00 */
/*0090*/ MOV R5, c[0x4][0xc] ; /* 0x0100030000057a02 */
/* 0x000fe40000000f00 */
/*00a0*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fc400000e06ff */
/*00b0*/ IMAD R2, R2, 0x8, R3 ; /* 0x0000000802027824 */
/* 0x001fca00078e0203 */
/*00c0*/ STL [R1], R2 ; /* 0x0000000201007387 */
/* 0x0003e40000100800 */
/*00d0*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x004fe40000000000 */
/*00e0*/ MOV R3, 0x150 ; /* 0x0000015000037802 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R20, 0xd0 ; /* 0x000000d000147802 */
/* 0x000fe40000000f00 */
/*0100*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x002fe40000000f00 */
/*0120*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0130*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0140*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0150*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0160*/ IMAD.WIDE R4, R2, R3, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x000fc800078e0203 */
/*0170*/ IMAD.WIDE R6, R2.reuse, R3.reuse, c[0x0][0x168] ; /* 0x00005a0002067625 */
/* 0x0c0fe400078e0203 */
/*0180*/ LDG.E R4, [R4.64] ; /* 0x0000002404047981 */
/* 0x000ea8000c1e1900 */
/*0190*/ LDG.E R7, [R6.64] ; /* 0x0000002406077981 */
/* 0x000ea2000c1e1900 */
/*01a0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fe200078e0203 */
/*01b0*/ IADD3 R9, R4, R7, RZ ; /* 0x0000000704097210 */
/* 0x004fca0007ffe0ff */
/*01c0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101924 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
__global__ void suma_vectores_cubo(int *d_v1, int *d_v2, int *d_vr)
{
int id_vector = blockIdx.x * 8 + threadIdx.x;
printf("Id: %d\n", id_vector);
d_vr[id_vector] = d_v1[id_vector] + d_v2[id_vector];
}
int main()
{
// Variables de tamaños
const int ARRAY_SIZE = 24;
const int ARRAY_BYTES = 24 * sizeof(int);
// Declaro vectores y vector resultado
int h_v1[ARRAY_SIZE];
int h_v2[ARRAY_SIZE];
int h_vr[ARRAY_SIZE];
// Relleno v1 y v2:
for (int i = 0; i < ARRAY_SIZE; i++)
{
h_v1[i] = i;
h_v2[i] = i;
h_vr[i] = 0;
}
// Declaro punteros a memoria GPU
int * d_v1;
int * d_v2;
int * d_vr;
// Asigno memoria GPU
cudaMalloc((void**)&d_v1, ARRAY_BYTES);
cudaMalloc((void**)&d_v2, ARRAY_BYTES);
cudaMalloc((void**)&d_vr, ARRAY_BYTES);
// Transfiero los arrays a la GPU:
cudaMemcpy(d_v1, h_v1, ARRAY_BYTES, cudaMemcpyHostToDevice);
cudaMemcpy(d_v2, h_v2, ARRAY_BYTES, cudaMemcpyHostToDevice);
cudaMemcpy(d_vr, h_vr, ARRAY_BYTES, cudaMemcpyHostToDevice);
// Lanzo el kernel
suma_vectores_cubo <<< 3, 8 >>> (d_v1, d_v2, d_vr);
// Copio el resultado al HOST:
cudaMemcpy(h_vr, d_vr, ARRAY_BYTES, cudaMemcpyDeviceToHost);
for (int i = 0; i < ARRAY_SIZE; i++)
{
printf("V[%d]: %d\n", i, h_vr[i]);
}
return 0;
} | .file "tmpxft_001288e8_00000000-6_5_suma_vectores_bloques.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z18suma_vectores_cuboPiS_S_PiS_S_
.type _Z42__device_stub__Z18suma_vectores_cuboPiS_S_PiS_S_, @function
_Z42__device_stub__Z18suma_vectores_cuboPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18suma_vectores_cuboPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z42__device_stub__Z18suma_vectores_cuboPiS_S_PiS_S_, .-_Z42__device_stub__Z18suma_vectores_cuboPiS_S_PiS_S_
.globl _Z18suma_vectores_cuboPiS_S_
.type _Z18suma_vectores_cuboPiS_S_, @function
_Z18suma_vectores_cuboPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z18suma_vectores_cuboPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z18suma_vectores_cuboPiS_S_, .-_Z18suma_vectores_cuboPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "V[%d]: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $360, %rsp
.cfi_def_cfa_offset 384
movq %fs:40, %rax
movq %rax, 344(%rsp)
xorl %eax, %eax
.L12:
movl %eax, 48(%rsp,%rax,4)
movl %eax, 144(%rsp,%rax,4)
movl $0, 240(%rsp,%rax,4)
addq $1, %rax
cmpq $24, %rax
jne .L12
movq %rsp, %rdi
movl $96, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $96, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $96, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $96, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 144(%rsp), %rsi
movl $1, %ecx
movl $96, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 240(%rsp), %rsi
movl $1, %ecx
movl $96, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $8, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $3, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
leaq 240(%rsp), %rdi
movl $2, %ecx
movl $96, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L14:
movl 240(%rsp,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $24, %rbx
jne .L14
movq 344(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $360, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z42__device_stub__Z18suma_vectores_cuboPiS_S_PiS_S_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z18suma_vectores_cuboPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z18suma_vectores_cuboPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
__global__ void suma_vectores_cubo(int *d_v1, int *d_v2, int *d_vr)
{
int id_vector = blockIdx.x * 8 + threadIdx.x;
printf("Id: %d\n", id_vector);
d_vr[id_vector] = d_v1[id_vector] + d_v2[id_vector];
}
int main()
{
// Variables de tamaños
const int ARRAY_SIZE = 24;
const int ARRAY_BYTES = 24 * sizeof(int);
// Declaro vectores y vector resultado
int h_v1[ARRAY_SIZE];
int h_v2[ARRAY_SIZE];
int h_vr[ARRAY_SIZE];
// Relleno v1 y v2:
for (int i = 0; i < ARRAY_SIZE; i++)
{
h_v1[i] = i;
h_v2[i] = i;
h_vr[i] = 0;
}
// Declaro punteros a memoria GPU
int * d_v1;
int * d_v2;
int * d_vr;
// Asigno memoria GPU
cudaMalloc((void**)&d_v1, ARRAY_BYTES);
cudaMalloc((void**)&d_v2, ARRAY_BYTES);
cudaMalloc((void**)&d_vr, ARRAY_BYTES);
// Transfiero los arrays a la GPU:
cudaMemcpy(d_v1, h_v1, ARRAY_BYTES, cudaMemcpyHostToDevice);
cudaMemcpy(d_v2, h_v2, ARRAY_BYTES, cudaMemcpyHostToDevice);
cudaMemcpy(d_vr, h_vr, ARRAY_BYTES, cudaMemcpyHostToDevice);
// Lanzo el kernel
suma_vectores_cubo <<< 3, 8 >>> (d_v1, d_v2, d_vr);
// Copio el resultado al HOST:
cudaMemcpy(h_vr, d_vr, ARRAY_BYTES, cudaMemcpyDeviceToHost);
for (int i = 0; i < ARRAY_SIZE; i++)
{
printf("V[%d]: %d\n", i, h_vr[i]);
}
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
__global__ void suma_vectores_cubo(int *d_v1, int *d_v2, int *d_vr)
{
int id_vector = blockIdx.x * 8 + threadIdx.x;
printf("Id: %d\n", id_vector);
d_vr[id_vector] = d_v1[id_vector] + d_v2[id_vector];
}
int main()
{
// Variables de tamaños
const int ARRAY_SIZE = 24;
const int ARRAY_BYTES = 24 * sizeof(int);
// Declaro vectores y vector resultado
int h_v1[ARRAY_SIZE];
int h_v2[ARRAY_SIZE];
int h_vr[ARRAY_SIZE];
// Relleno v1 y v2:
for (int i = 0; i < ARRAY_SIZE; i++)
{
h_v1[i] = i;
h_v2[i] = i;
h_vr[i] = 0;
}
// Declaro punteros a memoria GPU
int * d_v1;
int * d_v2;
int * d_vr;
// Asigno memoria GPU
hipMalloc((void**)&d_v1, ARRAY_BYTES);
hipMalloc((void**)&d_v2, ARRAY_BYTES);
hipMalloc((void**)&d_vr, ARRAY_BYTES);
// Transfiero los arrays a la GPU:
hipMemcpy(d_v1, h_v1, ARRAY_BYTES, hipMemcpyHostToDevice);
hipMemcpy(d_v2, h_v2, ARRAY_BYTES, hipMemcpyHostToDevice);
hipMemcpy(d_vr, h_vr, ARRAY_BYTES, hipMemcpyHostToDevice);
// Lanzo el kernel
suma_vectores_cubo <<< 3, 8 >>> (d_v1, d_v2, d_vr);
// Copio el resultado al HOST:
hipMemcpy(h_vr, d_vr, ARRAY_BYTES, hipMemcpyDeviceToHost);
for (int i = 0; i < ARRAY_SIZE; i++)
{
printf("V[%d]: %d\n", i, h_vr[i]);
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
__global__ void suma_vectores_cubo(int *d_v1, int *d_v2, int *d_vr)
{
int id_vector = blockIdx.x * 8 + threadIdx.x;
printf("Id: %d\n", id_vector);
d_vr[id_vector] = d_v1[id_vector] + d_v2[id_vector];
}
int main()
{
// Variables de tamaños
const int ARRAY_SIZE = 24;
const int ARRAY_BYTES = 24 * sizeof(int);
// Declaro vectores y vector resultado
int h_v1[ARRAY_SIZE];
int h_v2[ARRAY_SIZE];
int h_vr[ARRAY_SIZE];
// Relleno v1 y v2:
for (int i = 0; i < ARRAY_SIZE; i++)
{
h_v1[i] = i;
h_v2[i] = i;
h_vr[i] = 0;
}
// Declaro punteros a memoria GPU
int * d_v1;
int * d_v2;
int * d_vr;
// Asigno memoria GPU
hipMalloc((void**)&d_v1, ARRAY_BYTES);
hipMalloc((void**)&d_v2, ARRAY_BYTES);
hipMalloc((void**)&d_vr, ARRAY_BYTES);
// Transfiero los arrays a la GPU:
hipMemcpy(d_v1, h_v1, ARRAY_BYTES, hipMemcpyHostToDevice);
hipMemcpy(d_v2, h_v2, ARRAY_BYTES, hipMemcpyHostToDevice);
hipMemcpy(d_vr, h_vr, ARRAY_BYTES, hipMemcpyHostToDevice);
// Lanzo el kernel
suma_vectores_cubo <<< 3, 8 >>> (d_v1, d_v2, d_vr);
// Copio el resultado al HOST:
hipMemcpy(h_vr, d_vr, ARRAY_BYTES, hipMemcpyDeviceToHost);
for (int i = 0; i < ARRAY_SIZE; i++)
{
printf("V[%d]: %d\n", i, h_vr[i]);
}
return 0;
} | .text
.file "5_suma_vectores_bloques.hip"
.globl _Z33__device_stub__suma_vectores_cuboPiS_S_ # -- Begin function _Z33__device_stub__suma_vectores_cuboPiS_S_
.p2align 4, 0x90
.type _Z33__device_stub__suma_vectores_cuboPiS_S_,@function
_Z33__device_stub__suma_vectores_cuboPiS_S_: # @_Z33__device_stub__suma_vectores_cuboPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18suma_vectores_cuboPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z33__device_stub__suma_vectores_cuboPiS_S_, .Lfunc_end0-_Z33__device_stub__suma_vectores_cuboPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $416, %rsp # imm = 0x1A0
.cfi_def_cfa_offset 432
.cfi_offset %rbx, -16
xorps %xmm0, %xmm0
movaps %xmm0, 208(%rsp)
movaps %xmm0, 192(%rsp)
movaps %xmm0, 176(%rsp)
movaps %xmm0, 160(%rsp)
movaps %xmm0, 144(%rsp)
movaps %xmm0, 128(%rsp)
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, 320(%rsp,%rax,4)
movl %eax, 224(%rsp,%rax,4)
incq %rax
cmpq $24, %rax
jne .LBB1_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $96, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $96, %esi
callq hipMalloc
movq %rsp, %rdi
movl $96, %esi
callq hipMalloc
movq 16(%rsp), %rdi
leaq 320(%rsp), %rsi
movl $96, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 224(%rsp), %rsi
movl $96, %edx
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
leaq 128(%rsp), %rsi
movl $96, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967299, %rdi # imm = 0x100000003
leaq 5(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18suma_vectores_cuboPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
leaq 128(%rsp), %rdi
movl $96, %edx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 128(%rsp,%rbx,4), %edx
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $24, %rbx
jne .LBB1_5
# %bb.6:
xorl %eax, %eax
addq $416, %rsp # imm = 0x1A0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18suma_vectores_cuboPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18suma_vectores_cuboPiS_S_,@object # @_Z18suma_vectores_cuboPiS_S_
.section .rodata,"a",@progbits
.globl _Z18suma_vectores_cuboPiS_S_
.p2align 3, 0x0
_Z18suma_vectores_cuboPiS_S_:
.quad _Z33__device_stub__suma_vectores_cuboPiS_S_
.size _Z18suma_vectores_cuboPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "V[%d]: %d\n"
.size .L.str, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z18suma_vectores_cuboPiS_S_"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__suma_vectores_cuboPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18suma_vectores_cuboPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001288e8_00000000-6_5_suma_vectores_bloques.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z18suma_vectores_cuboPiS_S_PiS_S_
.type _Z42__device_stub__Z18suma_vectores_cuboPiS_S_PiS_S_, @function
_Z42__device_stub__Z18suma_vectores_cuboPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18suma_vectores_cuboPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z42__device_stub__Z18suma_vectores_cuboPiS_S_PiS_S_, .-_Z42__device_stub__Z18suma_vectores_cuboPiS_S_PiS_S_
.globl _Z18suma_vectores_cuboPiS_S_
.type _Z18suma_vectores_cuboPiS_S_, @function
_Z18suma_vectores_cuboPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z18suma_vectores_cuboPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z18suma_vectores_cuboPiS_S_, .-_Z18suma_vectores_cuboPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "V[%d]: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $360, %rsp
.cfi_def_cfa_offset 384
movq %fs:40, %rax
movq %rax, 344(%rsp)
xorl %eax, %eax
.L12:
movl %eax, 48(%rsp,%rax,4)
movl %eax, 144(%rsp,%rax,4)
movl $0, 240(%rsp,%rax,4)
addq $1, %rax
cmpq $24, %rax
jne .L12
movq %rsp, %rdi
movl $96, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $96, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $96, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $96, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 144(%rsp), %rsi
movl $1, %ecx
movl $96, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 240(%rsp), %rsi
movl $1, %ecx
movl $96, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $8, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $3, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
leaq 240(%rsp), %rdi
movl $2, %ecx
movl $96, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L14:
movl 240(%rsp,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $24, %rbx
jne .L14
movq 344(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $360, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z42__device_stub__Z18suma_vectores_cuboPiS_S_PiS_S_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z18suma_vectores_cuboPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z18suma_vectores_cuboPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "5_suma_vectores_bloques.hip"
.globl _Z33__device_stub__suma_vectores_cuboPiS_S_ # -- Begin function _Z33__device_stub__suma_vectores_cuboPiS_S_
.p2align 4, 0x90
.type _Z33__device_stub__suma_vectores_cuboPiS_S_,@function
_Z33__device_stub__suma_vectores_cuboPiS_S_: # @_Z33__device_stub__suma_vectores_cuboPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18suma_vectores_cuboPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z33__device_stub__suma_vectores_cuboPiS_S_, .Lfunc_end0-_Z33__device_stub__suma_vectores_cuboPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $416, %rsp # imm = 0x1A0
.cfi_def_cfa_offset 432
.cfi_offset %rbx, -16
xorps %xmm0, %xmm0
movaps %xmm0, 208(%rsp)
movaps %xmm0, 192(%rsp)
movaps %xmm0, 176(%rsp)
movaps %xmm0, 160(%rsp)
movaps %xmm0, 144(%rsp)
movaps %xmm0, 128(%rsp)
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, 320(%rsp,%rax,4)
movl %eax, 224(%rsp,%rax,4)
incq %rax
cmpq $24, %rax
jne .LBB1_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $96, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $96, %esi
callq hipMalloc
movq %rsp, %rdi
movl $96, %esi
callq hipMalloc
movq 16(%rsp), %rdi
leaq 320(%rsp), %rsi
movl $96, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 224(%rsp), %rsi
movl $96, %edx
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
leaq 128(%rsp), %rsi
movl $96, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967299, %rdi # imm = 0x100000003
leaq 5(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18suma_vectores_cuboPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
leaq 128(%rsp), %rdi
movl $96, %edx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 128(%rsp,%rbx,4), %edx
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $24, %rbx
jne .LBB1_5
# %bb.6:
xorl %eax, %eax
addq $416, %rsp # imm = 0x1A0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18suma_vectores_cuboPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18suma_vectores_cuboPiS_S_,@object # @_Z18suma_vectores_cuboPiS_S_
.section .rodata,"a",@progbits
.globl _Z18suma_vectores_cuboPiS_S_
.p2align 3, 0x0
_Z18suma_vectores_cuboPiS_S_:
.quad _Z33__device_stub__suma_vectores_cuboPiS_S_
.size _Z18suma_vectores_cuboPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "V[%d]: %d\n"
.size .L.str, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z18suma_vectores_cuboPiS_S_"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__suma_vectores_cuboPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18suma_vectores_cuboPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void kCorrelate(float* source, float* kernel, float* dest, int width, int height, int kwidth, int kheight) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int numThreads = blockDim.x * gridDim.x;
for (unsigned int i = idx; i < width * height; i += numThreads) {
float sum = 0;
for (int w = -kwidth/2; w <= kwidth/2; w++) {
for (int h = -kheight/2; h <= (kheight)/2; h++) {
const int x = (i / height) + w;
const int y = (i % height) + h;
const int j = i + (w * height) + h;
if (x >= 0 && x < width && y >= 0 && y < height)
sum += source[j] * kernel[(kwidth * kheight / 2) + w * kheight + h];
}
}
dest[i] = sum;
}
} | code for sm_80
Function : _Z10kCorrelatePfS_S_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R4, UR4, PT ; /* 0x0000000404007c0c */
/* 0x000fda000bf06070 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R7, RZ, RZ, 0x2 ; /* 0x00000002ff077424 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff067624 */
/* 0x000fe400078e00ff */
/*00b0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe400078e00ff */
/*00c0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff037624 */
/* 0x000fc800078e00ff */
/*00d0*/ IMAD.HI.U32 R0, R7, R6, R2 ; /* 0x0000000607007227 */
/* 0x000fc800078e0002 */
/*00e0*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0004 */
/*00f0*/ SHF.R.S32.HI R0, RZ, 0x1, R0 ; /* 0x00000001ff007819 */
/* 0x000fca0000011400 */
/*0100*/ IMAD.MOV R3, RZ, RZ, -R0 ; /* 0x000000ffff037224 */
/* 0x000fca00078e0a00 */
/*0110*/ ISETP.GT.AND P0, PT, R3, R0, PT ; /* 0x000000000300720c */
/* 0x000fda0003f04270 */
/*0120*/ @P0 BRA 0xaf0 ; /* 0x000009c000000947 */
/* 0x000fea0003800000 */
/*0130*/ MOV R5, c[0x0][0x184] ; /* 0x0000610000057a02 */
/* 0x000fe20000000f00 */
/*0140*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff097624 */
/* 0x000fe400078e00ff */
/*0150*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fc800078e00ff */
/*0160*/ IMAD.HI.U32 R3, R7, R9, R4 ; /* 0x0000000907037227 */
/* 0x000fe200078e0004 */
/*0170*/ LEA.HI R5, R6, c[0x0][0x180], RZ, 0x1 ; /* 0x0000600006057a11 */
/* 0x000fe400078f08ff */
/*0180*/ LEA.HI R7, R9.reuse, c[0x0][0x184], RZ, 0x1 ; /* 0x0000610009077a11 */
/* 0x040fe200078f08ff */
/*0190*/ IMAD R4, R9, c[0x0][0x180], RZ ; /* 0x0000600009047a24 */
/* 0x000fe200078e02ff */
/*01a0*/ SHF.R.S32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fe40000011403 */
/*01b0*/ SHF.R.S32.HI R6, RZ, 0x1, R5 ; /* 0x00000001ff067819 */
/* 0x000fe40000011405 */
/*01c0*/ SHF.R.S32.HI R7, RZ, 0x1, R7 ; /* 0x00000001ff077819 */
/* 0x000fe20000011407 */
/*01d0*/ IMAD.MOV R8, RZ, RZ, -R3 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0a03 */
/*01e0*/ LEA.HI R5, R4, R4, RZ, 0x1 ; /* 0x0000000404057211 */
/* 0x000fe200078f08ff */
/*01f0*/ IMAD.MOV R4, RZ, RZ, -R6 ; /* 0x000000ffff047224 */
/* 0x000fc400078e0a06 */
/*0200*/ IMAD.MOV R6, RZ, RZ, -R7 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0a07 */
/*0210*/ IMNMX R8, R3.reuse, R8, !PT ; /* 0x0000000803087217 */
/* 0x040fe40007800200 */
/*0220*/ SHF.R.S32.HI R5, RZ, 0x1, R5 ; /* 0x00000001ff057819 */
/* 0x000fe40000011405 */
/*0230*/ IADD3 R10, R3.reuse, 0x1, R8.reuse ; /* 0x00000001030a7810 */
/* 0x140fe20007ffe008 */
/*0240*/ IMAD.IADD R9, R3.reuse, 0x1, R8 ; /* 0x0000000103097824 */
/* 0x040fe200078e0208 */
/*0250*/ IADD3 R7, -R3.reuse, 0x1, RZ ; /* 0x0000000103077810 */
/* 0x040fe40007ffe1ff */
/*0260*/ IADD3 R8, -R3, 0x2, RZ ; /* 0x0000000203087810 */
/* 0x000fe40007ffe1ff */
/*0270*/ ISETP.GE.U32.AND P2, PT, R9, 0x3, PT ; /* 0x000000030900780c */
/* 0x000fc40003f46070 */
/*0280*/ IADD3 R9, -R3, 0x3, RZ ; /* 0x0000000303097810 */
/* 0x000fe40007ffe1ff */
/*0290*/ LOP3.LUT R10, R10, 0x3, RZ, 0xc0, !PT ; /* 0x000000030a0a7812 */
/* 0x000fe400078ec0ff */
/*02a0*/ IMAD.MOV R12, RZ, RZ, -R3 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0a03 */
/*02b0*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fc600078e00ff */
/*02c0*/ ISETP.GT.AND P0, PT, R12, R3, PT ; /* 0x000000030c00720c */
/* 0x000fda0003f04270 */
/*02d0*/ @P0 BRA 0xa70 ; /* 0x0000079000000947 */
/* 0x000fea0003800000 */
/*02e0*/ I2F.U32.RP R11, c[0x0][0x17c] ; /* 0x00005f00000b7b06 */
/* 0x000e220000209000 */
/*02f0*/ HFMA2.MMA R12, -RZ, RZ, 0, 0 ; /* 0x00000000ff0c7435 */
/* 0x000fe200000001ff */
/*0300*/ ISETP.NE.U32.AND P3, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fcc0003f65070 */
/*0310*/ MUFU.RCP R11, R11 ; /* 0x0000000b000b7308 */
/* 0x001e240000001000 */
/*0320*/ IADD3 R13, R11, 0xffffffe, RZ ; /* 0x0ffffffe0b0d7810 */
/* 0x001fcc0007ffe0ff */
/*0330*/ F2I.FTZ.U32.TRUNC.NTZ R13, R13 ; /* 0x0000000d000d7305 */
/* 0x000e24000021f000 */
/*0340*/ IMAD.MOV R15, RZ, RZ, -R13 ; /* 0x000000ffff0f7224 */
/* 0x001fc800078e0a0d */
/*0350*/ IMAD R15, R15, c[0x0][0x17c], RZ ; /* 0x00005f000f0f7a24 */
/* 0x000fc800078e02ff */
/*0360*/ IMAD.HI.U32 R15, R13, R15, R12 ; /* 0x0000000f0d0f7227 */
/* 0x000fc800078e000c */
/*0370*/ IMAD.MOV.U32 R13, RZ, RZ, R4 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0004 */
/*0380*/ IMAD.HI.U32 R12, R15, R2, RZ ; /* 0x000000020f0c7227 */
/* 0x000fc800078e00ff */
/*0390*/ IMAD.MOV R15, RZ, RZ, -R12 ; /* 0x000000ffff0f7224 */
/* 0x000fc800078e0a0c */
/*03a0*/ IMAD R14, R15, c[0x0][0x17c], R2 ; /* 0x00005f000f0e7a24 */
/* 0x000fca00078e0202 */
/*03b0*/ ISETP.GE.U32.AND P0, PT, R14, c[0x0][0x17c], PT ; /* 0x00005f000e007a0c */
/* 0x000fda0003f06070 */
/*03c0*/ @P0 IADD3 R14, R14, -c[0x0][0x17c], RZ ; /* 0x80005f000e0e0a10 */
/* 0x000fe40007ffe0ff */
/*03d0*/ @P0 IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0c0810 */
/* 0x000fe40007ffe0ff */
/*03e0*/ ISETP.GE.U32.AND P1, PT, R14, c[0x0][0x17c], PT ; /* 0x00005f000e007a0c */
/* 0x000fda0003f26070 */
/*03f0*/ @P1 IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0c1810 */
/* 0x000fe40007ffe0ff */
/*0400*/ @!P3 LOP3.LUT R12, RZ, c[0x0][0x17c], RZ, 0x33, !PT ; /* 0x00005f00ff0cba12 */
/* 0x000fca00078e33ff */
/*0410*/ IMAD.MOV R11, RZ, RZ, -R12 ; /* 0x000000ffff0b7224 */
/* 0x000fc800078e0a0c */
/*0420*/ IMAD R18, R11, c[0x0][0x17c], R2 ; /* 0x00005f000b127a24 */
/* 0x000fe400078e0202 */
/*0430*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e00ff */
/*0440*/ IMAD.IADD R19, R18, 0x1, -R3 ; /* 0x0000000112137824 */
/* 0x000fe400078e0a03 */
/*0450*/ IMAD.IADD R20, R7, 0x1, R18.reuse ; /* 0x0000000107147824 */
/* 0x100fe400078e0212 */
/*0460*/ IMAD.IADD R21, R8, 0x1, R18 ; /* 0x0000000108157824 */
/* 0x000fe400078e0212 */
/*0470*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f05270 */
/*0480*/ IMAD.IADD R22, R12, 0x1, R13 ; /* 0x000000010c167824 */
/* 0x000fe200078e020d */
/*0490*/ MOV R25, R13 ; /* 0x0000000d00197202 */
/* 0x000fe20000000f00 */
/*04a0*/ IMAD.MOV.U32 R23, RZ, RZ, R6 ; /* 0x000000ffff177224 */
/* 0x000fe200078e0006 */
/*04b0*/ IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d7810 */
/* 0x000fc40007ffe0ff */
/*04c0*/ ISETP.GE.AND P3, PT, R25, R0, PT ; /* 0x000000001900720c */
/* 0x000fce0003f66270 */
/*04d0*/ @!P0 BRA 0x760 ; /* 0x0000028000008947 */
/* 0x000fea0003800000 */
/*04e0*/ ISETP.GE.AND P0, PT, R22, c[0x0][0x178], PT ; /* 0x00005e0016007a0c */
/* 0x000fe20003f06270 */
/*04f0*/ IMAD R16, R25, c[0x0][0x184], R5 ; /* 0x0000610019107a24 */
/* 0x000fe200078e0205 */
/*0500*/ LOP3.LUT R14, R19, R22, RZ, 0xfc, !PT ; /* 0x00000016130e7212 */
/* 0x000fe200078efcff */
/*0510*/ IMAD.MOV.U32 R17, RZ, RZ, 0x4 ; /* 0x00000004ff117424 */
/* 0x000fe400078e00ff */
/*0520*/ IMAD.IADD R16, R16, 0x1, -R3 ; /* 0x0000000110107824 */
/* 0x000fe200078e0a03 */
/*0530*/ ISETP.LT.OR P1, PT, R14, RZ, P0 ; /* 0x000000ff0e00720c */
/* 0x000fe20000721670 */
/*0540*/ IMAD R14, R25, c[0x0][0x17c], R2 ; /* 0x00005f00190e7a24 */
/* 0x000fc600078e0202 */
/*0550*/ ISETP.GE.OR P1, PT, R19, c[0x0][0x17c], P1 ; /* 0x00005f0013007a0c */
/* 0x000fe20000f26670 */
/*0560*/ IMAD.IADD R14, R14, 0x1, -R3 ; /* 0x000000010e0e7824 */
/* 0x000fc800078e0a03 */
/*0570*/ IMAD.WIDE R14, R14, R17, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x000fc800078e0211 */
/*0580*/ IMAD.WIDE R16, R16, R17, c[0x0][0x168] ; /* 0x00005a0010107625 */
/* 0x000fc800078e0211 */
/*0590*/ @!P1 LDG.E R24, [R14.64] ; /* 0x000000060e189981 */
/* 0x000ea8000c1e1900 */
/*05a0*/ @!P1 LDG.E R23, [R16.64] ; /* 0x0000000610179981 */
/* 0x000ea2000c1e1900 */
/*05b0*/ ISETP.NE.AND P4, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fe20003f85270 */
/*05c0*/ BSSY B0, 0x760 ; /* 0x0000019000007945 */
/* 0x000fe20003800000 */
/*05d0*/ @!P1 FFMA R11, R24, R23, R11 ; /* 0x00000017180b9223 */
/* 0x004fe4000000000b */
/*05e0*/ IMAD.MOV.U32 R23, RZ, RZ, R7 ; /* 0x000000ffff177224 */
/* 0x000fd200078e0007 */
/*05f0*/ @!P4 BRA 0x750 ; /* 0x000001500000c947 */
/* 0x000fea0003800000 */
/*0600*/ LOP3.LUT R23, R20, R22, RZ, 0xfc, !PT ; /* 0x0000001614177212 */
/* 0x000fe200078efcff */
/*0610*/ BSSY B1, 0x6a0 ; /* 0x0000008000017945 */
/* 0x000fe20003800000 */
/*0620*/ ISETP.NE.AND P4, PT, R10, 0x2, PT ; /* 0x000000020a00780c */
/* 0x000fe40003f85270 */
/*0630*/ ISETP.LT.OR P1, PT, R23, RZ, P0 ; /* 0x000000ff1700720c */
/* 0x000fc80000721670 */
/*0640*/ ISETP.GE.OR P1, PT, R20, c[0x0][0x17c], P1 ; /* 0x00005f0014007a0c */
/* 0x000fda0000f26670 */
/*0650*/ @P1 BRA 0x690 ; /* 0x0000003000001947 */
/* 0x000fea0003800000 */
/*0660*/ LDG.E R24, [R16.64+0x4] ; /* 0x0000040610187981 */
/* 0x000ea8000c1e1900 */
/*0670*/ LDG.E R23, [R14.64+0x4] ; /* 0x000004060e177981 */
/* 0x000ea4000c1e1900 */
/*0680*/ FFMA R11, R24, R23, R11 ; /* 0x00000017180b7223 */
/* 0x004fe4000000000b */
/*0690*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*06a0*/ MOV R23, R8 ; /* 0x0000000800177202 */
/* 0x000fe20000000f00 */
/*06b0*/ @!P4 BRA 0x750 ; /* 0x000000900000c947 */
/* 0x000fea0003800000 */
/*06c0*/ LOP3.LUT R23, R21, R22, RZ, 0xfc, !PT ; /* 0x0000001615177212 */
/* 0x000fc800078efcff */
/*06d0*/ ISETP.LT.OR P0, PT, R23, RZ, P0 ; /* 0x000000ff1700720c */
/* 0x000fe20000701670 */
/*06e0*/ IMAD.MOV.U32 R23, RZ, RZ, R9 ; /* 0x000000ffff177224 */
/* 0x000fc600078e0009 */
/*06f0*/ ISETP.GE.OR P0, PT, R21, c[0x0][0x17c], P0 ; /* 0x00005f0015007a0c */
/* 0x000fda0000706670 */
/*0700*/ @P0 BRA 0x750 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0710*/ LDG.E R16, [R16.64+0x8] ; /* 0x0000080610107981 */
/* 0x000ea8000c1e1900 */
/*0720*/ LDG.E R14, [R14.64+0x8] ; /* 0x000008060e0e7981 */
/* 0x000ea2000c1e1900 */
/*0730*/ IMAD.MOV.U32 R23, RZ, RZ, R9 ; /* 0x000000ffff177224 */
/* 0x000fe400078e0009 */
/*0740*/ FFMA R11, R16, R14, R11 ; /* 0x0000000e100b7223 */
/* 0x004fe4000000000b */
/*0750*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0760*/ @!P2 BRA 0xa60 ; /* 0x000002f00000a947 */
/* 0x000fea0003800000 */
/*0770*/ IMAD.IADD R14, R23.reuse, 0x1, R2 ; /* 0x00000001170e7824 */
/* 0x040fe200078e0202 */
/*0780*/ BSSY B0, 0xa60 ; /* 0x000002d000007945 */
/* 0x000fe20003800000 */
/*0790*/ IMAD.IADD R16, R23.reuse, 0x1, R5 ; /* 0x0000000117107824 */
/* 0x040fe200078e0205 */
/*07a0*/ ISETP.GE.AND P4, PT, R22, c[0x0][0x178], PT ; /* 0x00005e0016007a0c */
/* 0x000fe20003f86270 */
/*07b0*/ IMAD.MOV.U32 R24, RZ, RZ, 0x4 ; /* 0x00000004ff187424 */
/* 0x000fe200078e00ff */
/*07c0*/ IADD3 R23, R23, -0x1, RZ ; /* 0xffffffff17177810 */
/* 0x000fe20007ffe0ff */
/*07d0*/ IMAD R14, R25, c[0x0][0x17c], R14 ; /* 0x00005f00190e7a24 */
/* 0x000fc400078e020e */
/*07e0*/ IMAD R15, R25, c[0x0][0x184], R16 ; /* 0x00006100190f7a24 */
/* 0x000fe400078e0210 */
/*07f0*/ IMAD.WIDE R16, R14, R24, c[0x0][0x160] ; /* 0x000058000e107625 */
/* 0x000fc800078e0218 */
/*0800*/ IMAD.WIDE R14, R15, R24, c[0x0][0x168] ; /* 0x00005a000f0e7625 */
/* 0x000fc800078e0218 */
/*0810*/ IMAD.IADD R24, R18, 0x1, R23 ; /* 0x0000000112187824 */
/* 0x000fca00078e0217 */
/*0820*/ IADD3 R25, R24, 0x1, RZ ; /* 0x0000000118197810 */
/* 0x000fc80007ffe0ff */
/*0830*/ LOP3.LUT R26, R25, R22, RZ, 0xfc, !PT ; /* 0x00000016191a7212 */
/* 0x000fc800078efcff */
/*0840*/ ISETP.LT.OR P0, PT, R26, RZ, P4 ; /* 0x000000ff1a00720c */
/* 0x000fc80002701670 */
/*0850*/ ISETP.GE.OR P0, PT, R25, c[0x0][0x17c], P0 ; /* 0x00005f0019007a0c */
/* 0x000fe40000706670 */
/*0860*/ IADD3 R25, R24, 0x2, RZ ; /* 0x0000000218197810 */
/* 0x000fc80007ffe0ff */
/*0870*/ LOP3.LUT R26, R25, R22, RZ, 0xfc, !PT ; /* 0x00000016191a7212 */
/* 0x000fc800078efcff */
/*0880*/ ISETP.LT.OR P1, PT, R26, RZ, P4 ; /* 0x000000ff1a00720c */
/* 0x000fc60002721670 */
/*0890*/ @!P0 LDG.E R26, [R16.64] ; /* 0x00000006101a8981 */
/* 0x000ea2000c1e1900 */
/*08a0*/ ISETP.GE.OR P1, PT, R25, c[0x0][0x17c], P1 ; /* 0x00005f0019007a0c */
/* 0x000fc60000f26670 */
/*08b0*/ @!P0 LDG.E R25, [R14.64] ; /* 0x000000060e198981 */
/* 0x000eb4000c1e1900 */
/*08c0*/ @!P1 LDG.E R28, [R14.64+0x4] ; /* 0x000004060e1c9981 */
/* 0x000ee8000c1e1900 */
/*08d0*/ @!P1 LDG.E R27, [R16.64+0x4] ; /* 0x00000406101b9981 */
/* 0x000ee2000c1e1900 */
/*08e0*/ @!P0 FFMA R11, R26, R25, R11 ; /* 0x000000191a0b8223 */
/* 0x004fe2000000000b */
/*08f0*/ IADD3 R25, R24, 0x3, RZ ; /* 0x0000000318197810 */
/* 0x000fc80007ffe0ff */
/*0900*/ LOP3.LUT R26, R25, R22, RZ, 0xfc, !PT ; /* 0x00000016191a7212 */
/* 0x000fc800078efcff */
/*0910*/ ISETP.LT.OR P0, PT, R26, RZ, P4 ; /* 0x000000ff1a00720c */
/* 0x000fe20002701670 */
/*0920*/ @!P1 FFMA R11, R28, R27, R11 ; /* 0x0000001b1c0b9223 */
/* 0x008fe2000000000b */
/*0930*/ IADD3 R27, R24, 0x4, RZ ; /* 0x00000004181b7810 */
/* 0x000fc80007ffe0ff */
/*0940*/ LOP3.LUT R24, R27, R22, RZ, 0xfc, !PT ; /* 0x000000161b187212 */
/* 0x000fe400078efcff */
/*0950*/ ISETP.GE.OR P0, PT, R25, c[0x0][0x17c], P0 ; /* 0x00005f0019007a0c */
/* 0x000fe40000706670 */
/*0960*/ ISETP.LT.OR P1, PT, R24, RZ, P4 ; /* 0x000000ff1800720c */
/* 0x000fc80002721670 */
/*0970*/ ISETP.GE.OR P1, PT, R27, c[0x0][0x17c], P1 ; /* 0x00005f001b007a0c */
/* 0x000fce0000f26670 */
/*0980*/ @!P0 LDG.E R24, [R14.64+0x8] ; /* 0x000008060e188981 */
/* 0x000ea8000c1e1900 */
/*0990*/ @!P0 LDG.E R25, [R16.64+0x8] ; /* 0x0000080610198981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ @!P1 LDG.E R26, [R14.64+0xc] ; /* 0x00000c060e1a9981 */
/* 0x0000e8000c1e1900 */
/*09b0*/ @!P1 LDG.E R27, [R16.64+0xc] ; /* 0x00000c06101b9981 */
/* 0x000ee2000c1e1900 */
/*09c0*/ IADD3 R23, R23, 0x4, RZ ; /* 0x0000000417177810 */
/* 0x000fc80007ffe0ff */
/*09d0*/ ISETP.GE.AND P5, PT, R23, R3, PT ; /* 0x000000031700720c */
/* 0x000fe20003fa6270 */
/*09e0*/ @!P0 FFMA R11, R24, R25, R11 ; /* 0x00000019180b8223 */
/* 0x004fe2000000000b */
/*09f0*/ IADD3 R14, P0, R14, 0x10, RZ ; /* 0x000000100e0e7810 */
/* 0x001fc60007f1e0ff */
/*0a00*/ @!P1 FFMA R11, R26, R27, R11 ; /* 0x0000001b1a0b9223 */
/* 0x008fe2000000000b */
/*0a10*/ IADD3 R16, P1, R16, 0x10, RZ ; /* 0x0000001010107810 */
/* 0x000fe40007f3e0ff */
/*0a20*/ IADD3.X R15, RZ, R15, RZ, P0, !PT ; /* 0x0000000fff0f7210 */
/* 0x000fc600007fe4ff */
/*0a30*/ IMAD.X R17, RZ, RZ, R17, P1 ; /* 0x000000ffff117224 */
/* 0x000fe400008e0611 */
/*0a40*/ @!P5 BRA 0x810 ; /* 0xfffffdc00000d947 */
/* 0x000fea000383ffff */
/*0a50*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0a60*/ @!P3 BRA 0x470 ; /* 0xfffffa000000b947 */
/* 0x000fea000383ffff */
/*0a70*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe400078e00ff */
/*0a80*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0f7624 */
/* 0x000fe400078e00ff */
/*0a90*/ IMAD.WIDE.U32 R12, R2, R13, c[0x0][0x170] ; /* 0x00005c00020c7625 */
/* 0x000fc800078e000d */
/*0aa0*/ IMAD R2, R15, c[0x0][0xc], R2 ; /* 0x000003000f027a24 */
/* 0x000fe200078e0202 */
/*0ab0*/ STG.E [R12.64], R11 ; /* 0x0000000b0c007986 */
/* 0x0001e8000c101906 */
/*0ac0*/ ISETP.GE.U32.AND P0, PT, R2, UR4, PT ; /* 0x0000000402007c0c */
/* 0x000fda000bf06070 */
/*0ad0*/ @!P0 BRA 0x2a0 ; /* 0xfffff7c000008947 */
/* 0x001fea000383ffff */
/*0ae0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0af0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*0b00*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff077624 */
/* 0x000fe400078e00ff */
/*0b10*/ IMAD.WIDE.U32 R4, R3, R2, c[0x0][0x170] ; /* 0x00005c0003047625 */
/* 0x000fc800078e0002 */
/*0b20*/ IMAD R2, R7, c[0x0][0xc], R2 ; /* 0x0000030007027a24 */
/* 0x000fe200078e0202 */
/*0b30*/ STG.E [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x0001e8000c101906 */
/*0b40*/ ISETP.GE.U32.AND P0, PT, R2, UR4, PT ; /* 0x0000000402007c0c */
/* 0x000fda000bf06070 */
/*0b50*/ @!P0 BRA 0xb10 ; /* 0xffffffb000008947 */
/* 0x001fea000383ffff */
/*0b60*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b70*/ BRA 0xb70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kCorrelate(float* source, float* kernel, float* dest, int width, int height, int kwidth, int kheight) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int numThreads = blockDim.x * gridDim.x;
for (unsigned int i = idx; i < width * height; i += numThreads) {
float sum = 0;
for (int w = -kwidth/2; w <= kwidth/2; w++) {
for (int h = -kheight/2; h <= (kheight)/2; h++) {
const int x = (i / height) + w;
const int y = (i % height) + h;
const int j = i + (w * height) + h;
if (x >= 0 && x < width && y >= 0 && y < height)
sum += source[j] * kernel[(kwidth * kheight / 2) + w * kheight + h];
}
}
dest[i] = sum;
}
} | .file "tmpxft_00088a71_00000000-6_kCorrelate.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z10kCorrelatePfS_S_iiiiPfS_S_iiii
.type _Z38__device_stub__Z10kCorrelatePfS_S_iiiiPfS_S_iiii, @function
_Z38__device_stub__Z10kCorrelatePfS_S_iiiiPfS_S_iiii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10kCorrelatePfS_S_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z10kCorrelatePfS_S_iiiiPfS_S_iiii, .-_Z38__device_stub__Z10kCorrelatePfS_S_iiiiPfS_S_iiii
.globl _Z10kCorrelatePfS_S_iiii
.type _Z10kCorrelatePfS_S_iiii, @function
_Z10kCorrelatePfS_S_iiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z38__device_stub__Z10kCorrelatePfS_S_iiiiPfS_S_iiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10kCorrelatePfS_S_iiii, .-_Z10kCorrelatePfS_S_iiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10kCorrelatePfS_S_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10kCorrelatePfS_S_iiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kCorrelate(float* source, float* kernel, float* dest, int width, int height, int kwidth, int kheight) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int numThreads = blockDim.x * gridDim.x;
for (unsigned int i = idx; i < width * height; i += numThreads) {
float sum = 0;
for (int w = -kwidth/2; w <= kwidth/2; w++) {
for (int h = -kheight/2; h <= (kheight)/2; h++) {
const int x = (i / height) + w;
const int y = (i % height) + h;
const int j = i + (w * height) + h;
if (x >= 0 && x < width && y >= 0 && y < height)
sum += source[j] * kernel[(kwidth * kheight / 2) + w * kheight + h];
}
}
dest[i] = sum;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kCorrelate(float* source, float* kernel, float* dest, int width, int height, int kwidth, int kheight) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int numThreads = blockDim.x * gridDim.x;
for (unsigned int i = idx; i < width * height; i += numThreads) {
float sum = 0;
for (int w = -kwidth/2; w <= kwidth/2; w++) {
for (int h = -kheight/2; h <= (kheight)/2; h++) {
const int x = (i / height) + w;
const int y = (i % height) + h;
const int j = i + (w * height) + h;
if (x >= 0 && x < width && y >= 0 && y < height)
sum += source[j] * kernel[(kwidth * kheight / 2) + w * kheight + h];
}
}
dest[i] = sum;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kCorrelate(float* source, float* kernel, float* dest, int width, int height, int kwidth, int kheight) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int numThreads = blockDim.x * gridDim.x;
for (unsigned int i = idx; i < width * height; i += numThreads) {
float sum = 0;
for (int w = -kwidth/2; w <= kwidth/2; w++) {
for (int h = -kheight/2; h <= (kheight)/2; h++) {
const int x = (i / height) + w;
const int y = (i % height) + h;
const int j = i + (w * height) + h;
if (x >= 0 && x < width && y >= 0 && y < height)
sum += source[j] * kernel[(kwidth * kheight / 2) + w * kheight + h];
}
}
dest[i] = sum;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10kCorrelatePfS_S_iiii
.globl _Z10kCorrelatePfS_S_iiii
.p2align 8
.type _Z10kCorrelatePfS_S_iiii,@function
_Z10kCorrelatePfS_S_iiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[8:9], s[0:1], 0x18
s_add_u32 s4, s0, 40
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s19, s2, 0xffff
s_mul_i32 s12, s9, s8
s_mul_i32 s20, s15, s19
s_mov_b32 s2, exec_lo
v_add_nc_u32_e32 v1, s20, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s12, v1
s_cbranch_execz .LBB0_13
s_load_b64 s[2:3], s[0:1], 0x20
v_cvt_f32_u32_e32 v2, s9
s_load_b32 s21, s[4:5], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
s_waitcnt lgkmcnt(0)
s_lshr_b32 s6, s2, 31
v_cvt_u32_f32_e32 v2, v2
s_add_i32 s6, s2, s6
s_mul_i32 s19, s21, s19
s_ashr_i32 s13, s6, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_sub_i32 s14, 0, s13
s_cmp_le_i32 s14, s13
s_cselect_b32 s15, -1, 0
s_lshr_b32 s4, s3, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s4, s3, s4
s_ashr_i32 s16, s4, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_sub_i32 s17, 0, s16
s_cmp_le_i32 s17, s16
s_cselect_b32 s18, -1, 0
s_sub_i32 s4, 0, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_mul_lo_u32 v3, s4, v2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[10:11], s[0:1], 0x10
s_mul_i32 s1, s14, s9
s_mul_i32 s0, s3, s2
s_add_i32 s20, s20, s1
s_lshr_b32 s2, s0, 31
s_sub_i32 s1, s20, s16
s_add_i32 s0, s0, s2
v_mul_hi_u32 v3, v2, v3
v_add_nc_u32_e32 v0, s1, v0
s_ashr_i32 s21, s0, 1
s_mul_i32 s0, s14, s3
s_mov_b32 s20, 0
s_add_i32 s21, s21, s0
s_delay_alu instid0(VALU_DEP_2)
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v5, v2, v3
s_branch .LBB0_3
.LBB0_2:
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s19, v1
v_add_nc_u32_e32 v0, s19, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cmp_le_u32_e32 vcc_lo, s12, v1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, s0, s10, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s0, s11, v4, s0
s_or_b32 s20, vcc_lo, s20
global_store_b32 v[3:4], v6, off
s_and_not1_b32 exec_lo, exec_lo, s20
s_cbranch_execz .LBB0_13
.LBB0_3:
v_mov_b32_e32 v6, 0
s_and_not1_b32 vcc_lo, exec_lo, s15
s_cbranch_vccnz .LBB0_2
v_mul_hi_u32 v7, v1, v5
v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v11, v0
s_mov_b32 s22, s21
s_mov_b32 s23, s14
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v9, 1, v7
v_mul_lo_u32 v3, v7, s9
v_sub_nc_u32_e32 v8, v1, v3
s_delay_alu instid0(VALU_DEP_1)
v_subrev_nc_u32_e32 v10, s9, v8
s_and_not1_b32 vcc_lo, exec_lo, s18
s_cbranch_vccnz .LBB0_11
.LBB0_5:
v_cmp_le_u32_e32 vcc_lo, s9, v8
s_mov_b32 s24, s17
v_dual_cndmask_b32 v3, v7, v9 :: v_dual_cndmask_b32 v4, v8, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v12, 1, v3
v_cmp_le_u32_e32 vcc_lo, s9, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v3, v12, vcc_lo
v_mul_lo_u32 v4, s9, v3
v_add_nc_u32_e32 v3, s23, v3
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v3
v_cmp_gt_i32_e64 s0, s8, v3
v_mov_b32_e32 v3, v11
v_sub_nc_u32_e32 v12, v1, v4
s_and_saveexec_b32 s25, vcc_lo
s_cbranch_execz .LBB0_9
.p2align 6
.LBB0_6:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, s24, v12
v_cmp_lt_i32_e64 s1, -1, v4
v_cmp_gt_i32_e64 s2, s9, v4
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s1, s0, s1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s1, s2, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s1
s_cbranch_execz .LBB0_8
v_ashrrev_i32_e32 v4, 31, v3
s_add_i32 s26, s22, s24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s27, s26, 31
s_lshl_b64 s[26:27], s[26:27], 2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[13:14], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_add_u32 s26, s6, s26
s_addc_u32 s27, s7, s27
v_add_co_u32 v13, s1, s4, v13
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v14, s1, s5, v14, s1
global_load_b32 v4, v[13:14], off
global_load_b32 v13, v2, s[26:27]
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v4, v13
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_9:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s25
v_add_nc_u32_e32 v3, 1, v3
s_add_i32 s1, s24, 1
s_cmp_ge_i32 s24, s16
s_cbranch_scc1 .LBB0_11
s_mov_b32 s24, s1
s_and_saveexec_b32 s25, vcc_lo
s_cbranch_execnz .LBB0_6
s_branch .LBB0_9
.LBB0_11:
v_add_nc_u32_e32 v11, s9, v11
s_add_i32 s0, s23, 1
s_add_i32 s22, s22, s3
s_cmp_ge_i32 s23, s13
s_cbranch_scc1 .LBB0_2
s_mov_b32 s23, s0
s_and_not1_b32 vcc_lo, exec_lo, s18
s_cbranch_vccz .LBB0_5
s_branch .LBB0_11
.LBB0_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10kCorrelatePfS_S_iiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 28
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10kCorrelatePfS_S_iiii, .Lfunc_end0-_Z10kCorrelatePfS_S_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10kCorrelatePfS_S_iiii
.private_segment_fixed_size: 0
.sgpr_count: 30
.sgpr_spill_count: 0
.symbol: _Z10kCorrelatePfS_S_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kCorrelate(float* source, float* kernel, float* dest, int width, int height, int kwidth, int kheight) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int numThreads = blockDim.x * gridDim.x;
for (unsigned int i = idx; i < width * height; i += numThreads) {
float sum = 0;
for (int w = -kwidth/2; w <= kwidth/2; w++) {
for (int h = -kheight/2; h <= (kheight)/2; h++) {
const int x = (i / height) + w;
const int y = (i % height) + h;
const int j = i + (w * height) + h;
if (x >= 0 && x < width && y >= 0 && y < height)
sum += source[j] * kernel[(kwidth * kheight / 2) + w * kheight + h];
}
}
dest[i] = sum;
}
} | .text
.file "kCorrelate.hip"
.globl _Z25__device_stub__kCorrelatePfS_S_iiii # -- Begin function _Z25__device_stub__kCorrelatePfS_S_iiii
.p2align 4, 0x90
.type _Z25__device_stub__kCorrelatePfS_S_iiii,@function
_Z25__device_stub__kCorrelatePfS_S_iiii: # @_Z25__device_stub__kCorrelatePfS_S_iiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10kCorrelatePfS_S_iiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z25__device_stub__kCorrelatePfS_S_iiii, .Lfunc_end0-_Z25__device_stub__kCorrelatePfS_S_iiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10kCorrelatePfS_S_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10kCorrelatePfS_S_iiii,@object # @_Z10kCorrelatePfS_S_iiii
.section .rodata,"a",@progbits
.globl _Z10kCorrelatePfS_S_iiii
.p2align 3, 0x0
_Z10kCorrelatePfS_S_iiii:
.quad _Z25__device_stub__kCorrelatePfS_S_iiii
.size _Z10kCorrelatePfS_S_iiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10kCorrelatePfS_S_iiii"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__kCorrelatePfS_S_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10kCorrelatePfS_S_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10kCorrelatePfS_S_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R4, UR4, PT ; /* 0x0000000404007c0c */
/* 0x000fda000bf06070 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R7, RZ, RZ, 0x2 ; /* 0x00000002ff077424 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff067624 */
/* 0x000fe400078e00ff */
/*00b0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe400078e00ff */
/*00c0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff037624 */
/* 0x000fc800078e00ff */
/*00d0*/ IMAD.HI.U32 R0, R7, R6, R2 ; /* 0x0000000607007227 */
/* 0x000fc800078e0002 */
/*00e0*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0004 */
/*00f0*/ SHF.R.S32.HI R0, RZ, 0x1, R0 ; /* 0x00000001ff007819 */
/* 0x000fca0000011400 */
/*0100*/ IMAD.MOV R3, RZ, RZ, -R0 ; /* 0x000000ffff037224 */
/* 0x000fca00078e0a00 */
/*0110*/ ISETP.GT.AND P0, PT, R3, R0, PT ; /* 0x000000000300720c */
/* 0x000fda0003f04270 */
/*0120*/ @P0 BRA 0xaf0 ; /* 0x000009c000000947 */
/* 0x000fea0003800000 */
/*0130*/ MOV R5, c[0x0][0x184] ; /* 0x0000610000057a02 */
/* 0x000fe20000000f00 */
/*0140*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff097624 */
/* 0x000fe400078e00ff */
/*0150*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fc800078e00ff */
/*0160*/ IMAD.HI.U32 R3, R7, R9, R4 ; /* 0x0000000907037227 */
/* 0x000fe200078e0004 */
/*0170*/ LEA.HI R5, R6, c[0x0][0x180], RZ, 0x1 ; /* 0x0000600006057a11 */
/* 0x000fe400078f08ff */
/*0180*/ LEA.HI R7, R9.reuse, c[0x0][0x184], RZ, 0x1 ; /* 0x0000610009077a11 */
/* 0x040fe200078f08ff */
/*0190*/ IMAD R4, R9, c[0x0][0x180], RZ ; /* 0x0000600009047a24 */
/* 0x000fe200078e02ff */
/*01a0*/ SHF.R.S32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fe40000011403 */
/*01b0*/ SHF.R.S32.HI R6, RZ, 0x1, R5 ; /* 0x00000001ff067819 */
/* 0x000fe40000011405 */
/*01c0*/ SHF.R.S32.HI R7, RZ, 0x1, R7 ; /* 0x00000001ff077819 */
/* 0x000fe20000011407 */
/*01d0*/ IMAD.MOV R8, RZ, RZ, -R3 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0a03 */
/*01e0*/ LEA.HI R5, R4, R4, RZ, 0x1 ; /* 0x0000000404057211 */
/* 0x000fe200078f08ff */
/*01f0*/ IMAD.MOV R4, RZ, RZ, -R6 ; /* 0x000000ffff047224 */
/* 0x000fc400078e0a06 */
/*0200*/ IMAD.MOV R6, RZ, RZ, -R7 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0a07 */
/*0210*/ IMNMX R8, R3.reuse, R8, !PT ; /* 0x0000000803087217 */
/* 0x040fe40007800200 */
/*0220*/ SHF.R.S32.HI R5, RZ, 0x1, R5 ; /* 0x00000001ff057819 */
/* 0x000fe40000011405 */
/*0230*/ IADD3 R10, R3.reuse, 0x1, R8.reuse ; /* 0x00000001030a7810 */
/* 0x140fe20007ffe008 */
/*0240*/ IMAD.IADD R9, R3.reuse, 0x1, R8 ; /* 0x0000000103097824 */
/* 0x040fe200078e0208 */
/*0250*/ IADD3 R7, -R3.reuse, 0x1, RZ ; /* 0x0000000103077810 */
/* 0x040fe40007ffe1ff */
/*0260*/ IADD3 R8, -R3, 0x2, RZ ; /* 0x0000000203087810 */
/* 0x000fe40007ffe1ff */
/*0270*/ ISETP.GE.U32.AND P2, PT, R9, 0x3, PT ; /* 0x000000030900780c */
/* 0x000fc40003f46070 */
/*0280*/ IADD3 R9, -R3, 0x3, RZ ; /* 0x0000000303097810 */
/* 0x000fe40007ffe1ff */
/*0290*/ LOP3.LUT R10, R10, 0x3, RZ, 0xc0, !PT ; /* 0x000000030a0a7812 */
/* 0x000fe400078ec0ff */
/*02a0*/ IMAD.MOV R12, RZ, RZ, -R3 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0a03 */
/*02b0*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fc600078e00ff */
/*02c0*/ ISETP.GT.AND P0, PT, R12, R3, PT ; /* 0x000000030c00720c */
/* 0x000fda0003f04270 */
/*02d0*/ @P0 BRA 0xa70 ; /* 0x0000079000000947 */
/* 0x000fea0003800000 */
/*02e0*/ I2F.U32.RP R11, c[0x0][0x17c] ; /* 0x00005f00000b7b06 */
/* 0x000e220000209000 */
/*02f0*/ HFMA2.MMA R12, -RZ, RZ, 0, 0 ; /* 0x00000000ff0c7435 */
/* 0x000fe200000001ff */
/*0300*/ ISETP.NE.U32.AND P3, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fcc0003f65070 */
/*0310*/ MUFU.RCP R11, R11 ; /* 0x0000000b000b7308 */
/* 0x001e240000001000 */
/*0320*/ IADD3 R13, R11, 0xffffffe, RZ ; /* 0x0ffffffe0b0d7810 */
/* 0x001fcc0007ffe0ff */
/*0330*/ F2I.FTZ.U32.TRUNC.NTZ R13, R13 ; /* 0x0000000d000d7305 */
/* 0x000e24000021f000 */
/*0340*/ IMAD.MOV R15, RZ, RZ, -R13 ; /* 0x000000ffff0f7224 */
/* 0x001fc800078e0a0d */
/*0350*/ IMAD R15, R15, c[0x0][0x17c], RZ ; /* 0x00005f000f0f7a24 */
/* 0x000fc800078e02ff */
/*0360*/ IMAD.HI.U32 R15, R13, R15, R12 ; /* 0x0000000f0d0f7227 */
/* 0x000fc800078e000c */
/*0370*/ IMAD.MOV.U32 R13, RZ, RZ, R4 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0004 */
/*0380*/ IMAD.HI.U32 R12, R15, R2, RZ ; /* 0x000000020f0c7227 */
/* 0x000fc800078e00ff */
/*0390*/ IMAD.MOV R15, RZ, RZ, -R12 ; /* 0x000000ffff0f7224 */
/* 0x000fc800078e0a0c */
/*03a0*/ IMAD R14, R15, c[0x0][0x17c], R2 ; /* 0x00005f000f0e7a24 */
/* 0x000fca00078e0202 */
/*03b0*/ ISETP.GE.U32.AND P0, PT, R14, c[0x0][0x17c], PT ; /* 0x00005f000e007a0c */
/* 0x000fda0003f06070 */
/*03c0*/ @P0 IADD3 R14, R14, -c[0x0][0x17c], RZ ; /* 0x80005f000e0e0a10 */
/* 0x000fe40007ffe0ff */
/*03d0*/ @P0 IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0c0810 */
/* 0x000fe40007ffe0ff */
/*03e0*/ ISETP.GE.U32.AND P1, PT, R14, c[0x0][0x17c], PT ; /* 0x00005f000e007a0c */
/* 0x000fda0003f26070 */
/*03f0*/ @P1 IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0c1810 */
/* 0x000fe40007ffe0ff */
/*0400*/ @!P3 LOP3.LUT R12, RZ, c[0x0][0x17c], RZ, 0x33, !PT ; /* 0x00005f00ff0cba12 */
/* 0x000fca00078e33ff */
/*0410*/ IMAD.MOV R11, RZ, RZ, -R12 ; /* 0x000000ffff0b7224 */
/* 0x000fc800078e0a0c */
/*0420*/ IMAD R18, R11, c[0x0][0x17c], R2 ; /* 0x00005f000b127a24 */
/* 0x000fe400078e0202 */
/*0430*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e00ff */
/*0440*/ IMAD.IADD R19, R18, 0x1, -R3 ; /* 0x0000000112137824 */
/* 0x000fe400078e0a03 */
/*0450*/ IMAD.IADD R20, R7, 0x1, R18.reuse ; /* 0x0000000107147824 */
/* 0x100fe400078e0212 */
/*0460*/ IMAD.IADD R21, R8, 0x1, R18 ; /* 0x0000000108157824 */
/* 0x000fe400078e0212 */
/*0470*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f05270 */
/*0480*/ IMAD.IADD R22, R12, 0x1, R13 ; /* 0x000000010c167824 */
/* 0x000fe200078e020d */
/*0490*/ MOV R25, R13 ; /* 0x0000000d00197202 */
/* 0x000fe20000000f00 */
/*04a0*/ IMAD.MOV.U32 R23, RZ, RZ, R6 ; /* 0x000000ffff177224 */
/* 0x000fe200078e0006 */
/*04b0*/ IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d7810 */
/* 0x000fc40007ffe0ff */
/*04c0*/ ISETP.GE.AND P3, PT, R25, R0, PT ; /* 0x000000001900720c */
/* 0x000fce0003f66270 */
/*04d0*/ @!P0 BRA 0x760 ; /* 0x0000028000008947 */
/* 0x000fea0003800000 */
/*04e0*/ ISETP.GE.AND P0, PT, R22, c[0x0][0x178], PT ; /* 0x00005e0016007a0c */
/* 0x000fe20003f06270 */
/*04f0*/ IMAD R16, R25, c[0x0][0x184], R5 ; /* 0x0000610019107a24 */
/* 0x000fe200078e0205 */
/*0500*/ LOP3.LUT R14, R19, R22, RZ, 0xfc, !PT ; /* 0x00000016130e7212 */
/* 0x000fe200078efcff */
/*0510*/ IMAD.MOV.U32 R17, RZ, RZ, 0x4 ; /* 0x00000004ff117424 */
/* 0x000fe400078e00ff */
/*0520*/ IMAD.IADD R16, R16, 0x1, -R3 ; /* 0x0000000110107824 */
/* 0x000fe200078e0a03 */
/*0530*/ ISETP.LT.OR P1, PT, R14, RZ, P0 ; /* 0x000000ff0e00720c */
/* 0x000fe20000721670 */
/*0540*/ IMAD R14, R25, c[0x0][0x17c], R2 ; /* 0x00005f00190e7a24 */
/* 0x000fc600078e0202 */
/*0550*/ ISETP.GE.OR P1, PT, R19, c[0x0][0x17c], P1 ; /* 0x00005f0013007a0c */
/* 0x000fe20000f26670 */
/*0560*/ IMAD.IADD R14, R14, 0x1, -R3 ; /* 0x000000010e0e7824 */
/* 0x000fc800078e0a03 */
/*0570*/ IMAD.WIDE R14, R14, R17, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x000fc800078e0211 */
/*0580*/ IMAD.WIDE R16, R16, R17, c[0x0][0x168] ; /* 0x00005a0010107625 */
/* 0x000fc800078e0211 */
/*0590*/ @!P1 LDG.E R24, [R14.64] ; /* 0x000000060e189981 */
/* 0x000ea8000c1e1900 */
/*05a0*/ @!P1 LDG.E R23, [R16.64] ; /* 0x0000000610179981 */
/* 0x000ea2000c1e1900 */
/*05b0*/ ISETP.NE.AND P4, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fe20003f85270 */
/*05c0*/ BSSY B0, 0x760 ; /* 0x0000019000007945 */
/* 0x000fe20003800000 */
/*05d0*/ @!P1 FFMA R11, R24, R23, R11 ; /* 0x00000017180b9223 */
/* 0x004fe4000000000b */
/*05e0*/ IMAD.MOV.U32 R23, RZ, RZ, R7 ; /* 0x000000ffff177224 */
/* 0x000fd200078e0007 */
/*05f0*/ @!P4 BRA 0x750 ; /* 0x000001500000c947 */
/* 0x000fea0003800000 */
/*0600*/ LOP3.LUT R23, R20, R22, RZ, 0xfc, !PT ; /* 0x0000001614177212 */
/* 0x000fe200078efcff */
/*0610*/ BSSY B1, 0x6a0 ; /* 0x0000008000017945 */
/* 0x000fe20003800000 */
/*0620*/ ISETP.NE.AND P4, PT, R10, 0x2, PT ; /* 0x000000020a00780c */
/* 0x000fe40003f85270 */
/*0630*/ ISETP.LT.OR P1, PT, R23, RZ, P0 ; /* 0x000000ff1700720c */
/* 0x000fc80000721670 */
/*0640*/ ISETP.GE.OR P1, PT, R20, c[0x0][0x17c], P1 ; /* 0x00005f0014007a0c */
/* 0x000fda0000f26670 */
/*0650*/ @P1 BRA 0x690 ; /* 0x0000003000001947 */
/* 0x000fea0003800000 */
/*0660*/ LDG.E R24, [R16.64+0x4] ; /* 0x0000040610187981 */
/* 0x000ea8000c1e1900 */
/*0670*/ LDG.E R23, [R14.64+0x4] ; /* 0x000004060e177981 */
/* 0x000ea4000c1e1900 */
/*0680*/ FFMA R11, R24, R23, R11 ; /* 0x00000017180b7223 */
/* 0x004fe4000000000b */
/*0690*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*06a0*/ MOV R23, R8 ; /* 0x0000000800177202 */
/* 0x000fe20000000f00 */
/*06b0*/ @!P4 BRA 0x750 ; /* 0x000000900000c947 */
/* 0x000fea0003800000 */
/*06c0*/ LOP3.LUT R23, R21, R22, RZ, 0xfc, !PT ; /* 0x0000001615177212 */
/* 0x000fc800078efcff */
/*06d0*/ ISETP.LT.OR P0, PT, R23, RZ, P0 ; /* 0x000000ff1700720c */
/* 0x000fe20000701670 */
/*06e0*/ IMAD.MOV.U32 R23, RZ, RZ, R9 ; /* 0x000000ffff177224 */
/* 0x000fc600078e0009 */
/*06f0*/ ISETP.GE.OR P0, PT, R21, c[0x0][0x17c], P0 ; /* 0x00005f0015007a0c */
/* 0x000fda0000706670 */
/*0700*/ @P0 BRA 0x750 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0710*/ LDG.E R16, [R16.64+0x8] ; /* 0x0000080610107981 */
/* 0x000ea8000c1e1900 */
/*0720*/ LDG.E R14, [R14.64+0x8] ; /* 0x000008060e0e7981 */
/* 0x000ea2000c1e1900 */
/*0730*/ IMAD.MOV.U32 R23, RZ, RZ, R9 ; /* 0x000000ffff177224 */
/* 0x000fe400078e0009 */
/*0740*/ FFMA R11, R16, R14, R11 ; /* 0x0000000e100b7223 */
/* 0x004fe4000000000b */
/*0750*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0760*/ @!P2 BRA 0xa60 ; /* 0x000002f00000a947 */
/* 0x000fea0003800000 */
/*0770*/ IMAD.IADD R14, R23.reuse, 0x1, R2 ; /* 0x00000001170e7824 */
/* 0x040fe200078e0202 */
/*0780*/ BSSY B0, 0xa60 ; /* 0x000002d000007945 */
/* 0x000fe20003800000 */
/*0790*/ IMAD.IADD R16, R23.reuse, 0x1, R5 ; /* 0x0000000117107824 */
/* 0x040fe200078e0205 */
/*07a0*/ ISETP.GE.AND P4, PT, R22, c[0x0][0x178], PT ; /* 0x00005e0016007a0c */
/* 0x000fe20003f86270 */
/*07b0*/ IMAD.MOV.U32 R24, RZ, RZ, 0x4 ; /* 0x00000004ff187424 */
/* 0x000fe200078e00ff */
/*07c0*/ IADD3 R23, R23, -0x1, RZ ; /* 0xffffffff17177810 */
/* 0x000fe20007ffe0ff */
/*07d0*/ IMAD R14, R25, c[0x0][0x17c], R14 ; /* 0x00005f00190e7a24 */
/* 0x000fc400078e020e */
/*07e0*/ IMAD R15, R25, c[0x0][0x184], R16 ; /* 0x00006100190f7a24 */
/* 0x000fe400078e0210 */
/*07f0*/ IMAD.WIDE R16, R14, R24, c[0x0][0x160] ; /* 0x000058000e107625 */
/* 0x000fc800078e0218 */
/*0800*/ IMAD.WIDE R14, R15, R24, c[0x0][0x168] ; /* 0x00005a000f0e7625 */
/* 0x000fc800078e0218 */
/*0810*/ IMAD.IADD R24, R18, 0x1, R23 ; /* 0x0000000112187824 */
/* 0x000fca00078e0217 */
/*0820*/ IADD3 R25, R24, 0x1, RZ ; /* 0x0000000118197810 */
/* 0x000fc80007ffe0ff */
/*0830*/ LOP3.LUT R26, R25, R22, RZ, 0xfc, !PT ; /* 0x00000016191a7212 */
/* 0x000fc800078efcff */
/*0840*/ ISETP.LT.OR P0, PT, R26, RZ, P4 ; /* 0x000000ff1a00720c */
/* 0x000fc80002701670 */
/*0850*/ ISETP.GE.OR P0, PT, R25, c[0x0][0x17c], P0 ; /* 0x00005f0019007a0c */
/* 0x000fe40000706670 */
/*0860*/ IADD3 R25, R24, 0x2, RZ ; /* 0x0000000218197810 */
/* 0x000fc80007ffe0ff */
/*0870*/ LOP3.LUT R26, R25, R22, RZ, 0xfc, !PT ; /* 0x00000016191a7212 */
/* 0x000fc800078efcff */
/*0880*/ ISETP.LT.OR P1, PT, R26, RZ, P4 ; /* 0x000000ff1a00720c */
/* 0x000fc60002721670 */
/*0890*/ @!P0 LDG.E R26, [R16.64] ; /* 0x00000006101a8981 */
/* 0x000ea2000c1e1900 */
/*08a0*/ ISETP.GE.OR P1, PT, R25, c[0x0][0x17c], P1 ; /* 0x00005f0019007a0c */
/* 0x000fc60000f26670 */
/*08b0*/ @!P0 LDG.E R25, [R14.64] ; /* 0x000000060e198981 */
/* 0x000eb4000c1e1900 */
/*08c0*/ @!P1 LDG.E R28, [R14.64+0x4] ; /* 0x000004060e1c9981 */
/* 0x000ee8000c1e1900 */
/*08d0*/ @!P1 LDG.E R27, [R16.64+0x4] ; /* 0x00000406101b9981 */
/* 0x000ee2000c1e1900 */
/*08e0*/ @!P0 FFMA R11, R26, R25, R11 ; /* 0x000000191a0b8223 */
/* 0x004fe2000000000b */
/*08f0*/ IADD3 R25, R24, 0x3, RZ ; /* 0x0000000318197810 */
/* 0x000fc80007ffe0ff */
/*0900*/ LOP3.LUT R26, R25, R22, RZ, 0xfc, !PT ; /* 0x00000016191a7212 */
/* 0x000fc800078efcff */
/*0910*/ ISETP.LT.OR P0, PT, R26, RZ, P4 ; /* 0x000000ff1a00720c */
/* 0x000fe20002701670 */
/*0920*/ @!P1 FFMA R11, R28, R27, R11 ; /* 0x0000001b1c0b9223 */
/* 0x008fe2000000000b */
/*0930*/ IADD3 R27, R24, 0x4, RZ ; /* 0x00000004181b7810 */
/* 0x000fc80007ffe0ff */
/*0940*/ LOP3.LUT R24, R27, R22, RZ, 0xfc, !PT ; /* 0x000000161b187212 */
/* 0x000fe400078efcff */
/*0950*/ ISETP.GE.OR P0, PT, R25, c[0x0][0x17c], P0 ; /* 0x00005f0019007a0c */
/* 0x000fe40000706670 */
/*0960*/ ISETP.LT.OR P1, PT, R24, RZ, P4 ; /* 0x000000ff1800720c */
/* 0x000fc80002721670 */
/*0970*/ ISETP.GE.OR P1, PT, R27, c[0x0][0x17c], P1 ; /* 0x00005f001b007a0c */
/* 0x000fce0000f26670 */
/*0980*/ @!P0 LDG.E R24, [R14.64+0x8] ; /* 0x000008060e188981 */
/* 0x000ea8000c1e1900 */
/*0990*/ @!P0 LDG.E R25, [R16.64+0x8] ; /* 0x0000080610198981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ @!P1 LDG.E R26, [R14.64+0xc] ; /* 0x00000c060e1a9981 */
/* 0x0000e8000c1e1900 */
/*09b0*/ @!P1 LDG.E R27, [R16.64+0xc] ; /* 0x00000c06101b9981 */
/* 0x000ee2000c1e1900 */
/*09c0*/ IADD3 R23, R23, 0x4, RZ ; /* 0x0000000417177810 */
/* 0x000fc80007ffe0ff */
/*09d0*/ ISETP.GE.AND P5, PT, R23, R3, PT ; /* 0x000000031700720c */
/* 0x000fe20003fa6270 */
/*09e0*/ @!P0 FFMA R11, R24, R25, R11 ; /* 0x00000019180b8223 */
/* 0x004fe2000000000b */
/*09f0*/ IADD3 R14, P0, R14, 0x10, RZ ; /* 0x000000100e0e7810 */
/* 0x001fc60007f1e0ff */
/*0a00*/ @!P1 FFMA R11, R26, R27, R11 ; /* 0x0000001b1a0b9223 */
/* 0x008fe2000000000b */
/*0a10*/ IADD3 R16, P1, R16, 0x10, RZ ; /* 0x0000001010107810 */
/* 0x000fe40007f3e0ff */
/*0a20*/ IADD3.X R15, RZ, R15, RZ, P0, !PT ; /* 0x0000000fff0f7210 */
/* 0x000fc600007fe4ff */
/*0a30*/ IMAD.X R17, RZ, RZ, R17, P1 ; /* 0x000000ffff117224 */
/* 0x000fe400008e0611 */
/*0a40*/ @!P5 BRA 0x810 ; /* 0xfffffdc00000d947 */
/* 0x000fea000383ffff */
/*0a50*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0a60*/ @!P3 BRA 0x470 ; /* 0xfffffa000000b947 */
/* 0x000fea000383ffff */
/*0a70*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe400078e00ff */
/*0a80*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0f7624 */
/* 0x000fe400078e00ff */
/*0a90*/ IMAD.WIDE.U32 R12, R2, R13, c[0x0][0x170] ; /* 0x00005c00020c7625 */
/* 0x000fc800078e000d */
/*0aa0*/ IMAD R2, R15, c[0x0][0xc], R2 ; /* 0x000003000f027a24 */
/* 0x000fe200078e0202 */
/*0ab0*/ STG.E [R12.64], R11 ; /* 0x0000000b0c007986 */
/* 0x0001e8000c101906 */
/*0ac0*/ ISETP.GE.U32.AND P0, PT, R2, UR4, PT ; /* 0x0000000402007c0c */
/* 0x000fda000bf06070 */
/*0ad0*/ @!P0 BRA 0x2a0 ; /* 0xfffff7c000008947 */
/* 0x001fea000383ffff */
/*0ae0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0af0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*0b00*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff077624 */
/* 0x000fe400078e00ff */
/*0b10*/ IMAD.WIDE.U32 R4, R3, R2, c[0x0][0x170] ; /* 0x00005c0003047625 */
/* 0x000fc800078e0002 */
/*0b20*/ IMAD R2, R7, c[0x0][0xc], R2 ; /* 0x0000030007027a24 */
/* 0x000fe200078e0202 */
/*0b30*/ STG.E [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x0001e8000c101906 */
/*0b40*/ ISETP.GE.U32.AND P0, PT, R2, UR4, PT ; /* 0x0000000402007c0c */
/* 0x000fda000bf06070 */
/*0b50*/ @!P0 BRA 0xb10 ; /* 0xffffffb000008947 */
/* 0x001fea000383ffff */
/*0b60*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b70*/ BRA 0xb70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10kCorrelatePfS_S_iiii
.globl _Z10kCorrelatePfS_S_iiii
.p2align 8
.type _Z10kCorrelatePfS_S_iiii,@function
_Z10kCorrelatePfS_S_iiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[8:9], s[0:1], 0x18
s_add_u32 s4, s0, 40
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s19, s2, 0xffff
s_mul_i32 s12, s9, s8
s_mul_i32 s20, s15, s19
s_mov_b32 s2, exec_lo
v_add_nc_u32_e32 v1, s20, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s12, v1
s_cbranch_execz .LBB0_13
s_load_b64 s[2:3], s[0:1], 0x20
v_cvt_f32_u32_e32 v2, s9
s_load_b32 s21, s[4:5], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
s_waitcnt lgkmcnt(0)
s_lshr_b32 s6, s2, 31
v_cvt_u32_f32_e32 v2, v2
s_add_i32 s6, s2, s6
s_mul_i32 s19, s21, s19
s_ashr_i32 s13, s6, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_sub_i32 s14, 0, s13
s_cmp_le_i32 s14, s13
s_cselect_b32 s15, -1, 0
s_lshr_b32 s4, s3, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s4, s3, s4
s_ashr_i32 s16, s4, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_sub_i32 s17, 0, s16
s_cmp_le_i32 s17, s16
s_cselect_b32 s18, -1, 0
s_sub_i32 s4, 0, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_mul_lo_u32 v3, s4, v2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[10:11], s[0:1], 0x10
s_mul_i32 s1, s14, s9
s_mul_i32 s0, s3, s2
s_add_i32 s20, s20, s1
s_lshr_b32 s2, s0, 31
s_sub_i32 s1, s20, s16
s_add_i32 s0, s0, s2
v_mul_hi_u32 v3, v2, v3
v_add_nc_u32_e32 v0, s1, v0
s_ashr_i32 s21, s0, 1
s_mul_i32 s0, s14, s3
s_mov_b32 s20, 0
s_add_i32 s21, s21, s0
s_delay_alu instid0(VALU_DEP_2)
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v5, v2, v3
s_branch .LBB0_3
.LBB0_2:
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s19, v1
v_add_nc_u32_e32 v0, s19, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cmp_le_u32_e32 vcc_lo, s12, v1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, s0, s10, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s0, s11, v4, s0
s_or_b32 s20, vcc_lo, s20
global_store_b32 v[3:4], v6, off
s_and_not1_b32 exec_lo, exec_lo, s20
s_cbranch_execz .LBB0_13
.LBB0_3:
v_mov_b32_e32 v6, 0
s_and_not1_b32 vcc_lo, exec_lo, s15
s_cbranch_vccnz .LBB0_2
v_mul_hi_u32 v7, v1, v5
v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v11, v0
s_mov_b32 s22, s21
s_mov_b32 s23, s14
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v9, 1, v7
v_mul_lo_u32 v3, v7, s9
v_sub_nc_u32_e32 v8, v1, v3
s_delay_alu instid0(VALU_DEP_1)
v_subrev_nc_u32_e32 v10, s9, v8
s_and_not1_b32 vcc_lo, exec_lo, s18
s_cbranch_vccnz .LBB0_11
.LBB0_5:
v_cmp_le_u32_e32 vcc_lo, s9, v8
s_mov_b32 s24, s17
v_dual_cndmask_b32 v3, v7, v9 :: v_dual_cndmask_b32 v4, v8, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v12, 1, v3
v_cmp_le_u32_e32 vcc_lo, s9, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v3, v12, vcc_lo
v_mul_lo_u32 v4, s9, v3
v_add_nc_u32_e32 v3, s23, v3
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v3
v_cmp_gt_i32_e64 s0, s8, v3
v_mov_b32_e32 v3, v11
v_sub_nc_u32_e32 v12, v1, v4
s_and_saveexec_b32 s25, vcc_lo
s_cbranch_execz .LBB0_9
.p2align 6
.LBB0_6:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, s24, v12
v_cmp_lt_i32_e64 s1, -1, v4
v_cmp_gt_i32_e64 s2, s9, v4
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s1, s0, s1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s1, s2, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s1
s_cbranch_execz .LBB0_8
v_ashrrev_i32_e32 v4, 31, v3
s_add_i32 s26, s22, s24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s27, s26, 31
s_lshl_b64 s[26:27], s[26:27], 2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[13:14], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_add_u32 s26, s6, s26
s_addc_u32 s27, s7, s27
v_add_co_u32 v13, s1, s4, v13
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v14, s1, s5, v14, s1
global_load_b32 v4, v[13:14], off
global_load_b32 v13, v2, s[26:27]
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v4, v13
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_9:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s25
v_add_nc_u32_e32 v3, 1, v3
s_add_i32 s1, s24, 1
s_cmp_ge_i32 s24, s16
s_cbranch_scc1 .LBB0_11
s_mov_b32 s24, s1
s_and_saveexec_b32 s25, vcc_lo
s_cbranch_execnz .LBB0_6
s_branch .LBB0_9
.LBB0_11:
v_add_nc_u32_e32 v11, s9, v11
s_add_i32 s0, s23, 1
s_add_i32 s22, s22, s3
s_cmp_ge_i32 s23, s13
s_cbranch_scc1 .LBB0_2
s_mov_b32 s23, s0
s_and_not1_b32 vcc_lo, exec_lo, s18
s_cbranch_vccz .LBB0_5
s_branch .LBB0_11
.LBB0_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10kCorrelatePfS_S_iiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 28
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10kCorrelatePfS_S_iiii, .Lfunc_end0-_Z10kCorrelatePfS_S_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10kCorrelatePfS_S_iiii
.private_segment_fixed_size: 0
.sgpr_count: 30
.sgpr_spill_count: 0
.symbol: _Z10kCorrelatePfS_S_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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