system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00088a71_00000000-6_kCorrelate.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z10kCorrelatePfS_S_iiiiPfS_S_iiii
.type _Z38__device_stub__Z10kCorrelatePfS_S_iiiiPfS_S_iiii, @function
_Z38__device_stub__Z10kCorrelatePfS_S_iiiiPfS_S_iiii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10kCorrelatePfS_S_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z10kCorrelatePfS_S_iiiiPfS_S_iiii, .-_Z38__device_stub__Z10kCorrelatePfS_S_iiiiPfS_S_iiii
.globl _Z10kCorrelatePfS_S_iiii
.type _Z10kCorrelatePfS_S_iiii, @function
_Z10kCorrelatePfS_S_iiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z38__device_stub__Z10kCorrelatePfS_S_iiiiPfS_S_iiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10kCorrelatePfS_S_iiii, .-_Z10kCorrelatePfS_S_iiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10kCorrelatePfS_S_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10kCorrelatePfS_S_iiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kCorrelate.hip"
.globl _Z25__device_stub__kCorrelatePfS_S_iiii # -- Begin function _Z25__device_stub__kCorrelatePfS_S_iiii
.p2align 4, 0x90
.type _Z25__device_stub__kCorrelatePfS_S_iiii,@function
_Z25__device_stub__kCorrelatePfS_S_iiii: # @_Z25__device_stub__kCorrelatePfS_S_iiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10kCorrelatePfS_S_iiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z25__device_stub__kCorrelatePfS_S_iiii, .Lfunc_end0-_Z25__device_stub__kCorrelatePfS_S_iiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10kCorrelatePfS_S_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10kCorrelatePfS_S_iiii,@object # @_Z10kCorrelatePfS_S_iiii
.section .rodata,"a",@progbits
.globl _Z10kCorrelatePfS_S_iiii
.p2align 3, 0x0
_Z10kCorrelatePfS_S_iiii:
.quad _Z25__device_stub__kCorrelatePfS_S_iiii
.size _Z10kCorrelatePfS_S_iiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10kCorrelatePfS_S_iiii"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__kCorrelatePfS_S_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10kCorrelatePfS_S_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <stdio.h>
#define N 2
__global__ void K(int *out, int *in, int size) {
unsigned id = blockIdx.x * blockDim.x + threadIdx.x;
out[id] = in[id] * in[id];
}
int main() {
cudaStream_t stream[N];
for (unsigned ii = 0; ii < N; ++ii)
cudaStreamCreate(&stream[ii]);
int *hptr, *dinptr, *doutptr;
unsigned nbytesperstream = (1<<10);
unsigned nbytes = N * nbytesperstream;
cudaHostAlloc(&hptr, nbytes, 0);
cudaMalloc(&dinptr, nbytes);
cudaMalloc(&doutptr, nbytes);
for (unsigned ii = 0; ii < N; ++ii) {
cudaMemcpyAsync(dinptr + ii * nbytesperstream, hptr + ii * nbytesperstream, nbytesperstream, cudaMemcpyHostToDevice, stream[ii]);
K<<<nbytesperstream / 512, 512, 0, stream[ii]>>>(doutptr + ii * nbytesperstream, dinptr + ii * nbytesperstream, nbytesperstream);
cudaMemcpyAsync(hptr + ii * nbytesperstream, doutptr + ii * nbytesperstream, nbytesperstream, cudaMemcpyDeviceToHost, stream[ii]);
}
return 0;
} | code for sm_80
Function : _Z1KPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE.U32 R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fcc00078e0005 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0005 */
/*0090*/ IMAD R7, R2, R2, RZ ; /* 0x0000000202077224 */
/* 0x004fca00078e02ff */
/*00a0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <stdio.h>
#define N 2
__global__ void K(int *out, int *in, int size) {
unsigned id = blockIdx.x * blockDim.x + threadIdx.x;
out[id] = in[id] * in[id];
}
int main() {
cudaStream_t stream[N];
for (unsigned ii = 0; ii < N; ++ii)
cudaStreamCreate(&stream[ii]);
int *hptr, *dinptr, *doutptr;
unsigned nbytesperstream = (1<<10);
unsigned nbytes = N * nbytesperstream;
cudaHostAlloc(&hptr, nbytes, 0);
cudaMalloc(&dinptr, nbytes);
cudaMalloc(&doutptr, nbytes);
for (unsigned ii = 0; ii < N; ++ii) {
cudaMemcpyAsync(dinptr + ii * nbytesperstream, hptr + ii * nbytesperstream, nbytesperstream, cudaMemcpyHostToDevice, stream[ii]);
K<<<nbytesperstream / 512, 512, 0, stream[ii]>>>(doutptr + ii * nbytesperstream, dinptr + ii * nbytesperstream, nbytesperstream);
cudaMemcpyAsync(hptr + ii * nbytesperstream, doutptr + ii * nbytesperstream, nbytesperstream, cudaMemcpyDeviceToHost, stream[ii]);
}
return 0;
} | .file "tmpxft_0011a106_00000000-6_stream2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z1KPiS_iPiS_i
.type _Z23__device_stub__Z1KPiS_iPiS_i, @function
_Z23__device_stub__Z1KPiS_iPiS_i:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z1KPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z23__device_stub__Z1KPiS_iPiS_i, .-_Z23__device_stub__Z1KPiS_iPiS_i
.globl _Z1KPiS_i
.type _Z1KPiS_i, @function
_Z1KPiS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z1KPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z1KPiS_i, .-_Z1KPiS_i
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 48(%rsp), %rbp
movq %rbp, %rdi
call cudaStreamCreate@PLT
leaq 56(%rsp), %rdi
call cudaStreamCreate@PLT
movq %rsp, %rdi
movl $0, %edx
movl $2048, %esi
call cudaHostAlloc@PLT
leaq 8(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
movl $0, %ebx
.L13:
movq %rbp, %r12
movq %rbx, %rsi
addq (%rsp), %rsi
movq %rbx, %rdi
addq 8(%rsp), %rdi
movq 0(%rbp), %r8
movl $1, %ecx
movl $1024, %edx
call cudaMemcpyAsync@PLT
movl $512, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $2, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movq 0(%rbp), %r9
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
movq %rbx, %rsi
addq 16(%rsp), %rsi
movq %rbx, %rdi
addq (%rsp), %rdi
movq (%r12), %r8
movl $2, %ecx
movl $1024, %edx
call cudaMemcpyAsync@PLT
addq $8, %rbp
addq $4096, %rbx
cmpq $8192, %rbx
jne .L13
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq %rbx, %rsi
addq 8(%rsp), %rsi
movq %rbx, %rdi
addq 16(%rsp), %rdi
movl $1024, %edx
call _Z23__device_stub__Z1KPiS_iPiS_i
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z1KPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z1KPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <stdio.h>
#define N 2
__global__ void K(int *out, int *in, int size) {
unsigned id = blockIdx.x * blockDim.x + threadIdx.x;
out[id] = in[id] * in[id];
}
int main() {
cudaStream_t stream[N];
for (unsigned ii = 0; ii < N; ++ii)
cudaStreamCreate(&stream[ii]);
int *hptr, *dinptr, *doutptr;
unsigned nbytesperstream = (1<<10);
unsigned nbytes = N * nbytesperstream;
cudaHostAlloc(&hptr, nbytes, 0);
cudaMalloc(&dinptr, nbytes);
cudaMalloc(&doutptr, nbytes);
for (unsigned ii = 0; ii < N; ++ii) {
cudaMemcpyAsync(dinptr + ii * nbytesperstream, hptr + ii * nbytesperstream, nbytesperstream, cudaMemcpyHostToDevice, stream[ii]);
K<<<nbytesperstream / 512, 512, 0, stream[ii]>>>(doutptr + ii * nbytesperstream, dinptr + ii * nbytesperstream, nbytesperstream);
cudaMemcpyAsync(hptr + ii * nbytesperstream, doutptr + ii * nbytesperstream, nbytesperstream, cudaMemcpyDeviceToHost, stream[ii]);
}
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define N 2
__global__ void K(int *out, int *in, int size) {
unsigned id = blockIdx.x * blockDim.x + threadIdx.x;
out[id] = in[id] * in[id];
}
int main() {
hipStream_t stream[N];
for (unsigned ii = 0; ii < N; ++ii)
hipStreamCreate(&stream[ii]);
int *hptr, *dinptr, *doutptr;
unsigned nbytesperstream = (1<<10);
unsigned nbytes = N * nbytesperstream;
hipHostAlloc(&hptr, nbytes, 0);
hipMalloc(&dinptr, nbytes);
hipMalloc(&doutptr, nbytes);
for (unsigned ii = 0; ii < N; ++ii) {
hipMemcpyAsync(dinptr + ii * nbytesperstream, hptr + ii * nbytesperstream, nbytesperstream, hipMemcpyHostToDevice, stream[ii]);
K<<<nbytesperstream / 512, 512, 0, stream[ii]>>>(doutptr + ii * nbytesperstream, dinptr + ii * nbytesperstream, nbytesperstream);
hipMemcpyAsync(hptr + ii * nbytesperstream, doutptr + ii * nbytesperstream, nbytesperstream, hipMemcpyDeviceToHost, stream[ii]);
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define N 2
__global__ void K(int *out, int *in, int size) {
unsigned id = blockIdx.x * blockDim.x + threadIdx.x;
out[id] = in[id] * in[id];
}
int main() {
hipStream_t stream[N];
for (unsigned ii = 0; ii < N; ++ii)
hipStreamCreate(&stream[ii]);
int *hptr, *dinptr, *doutptr;
unsigned nbytesperstream = (1<<10);
unsigned nbytes = N * nbytesperstream;
hipHostAlloc(&hptr, nbytes, 0);
hipMalloc(&dinptr, nbytes);
hipMalloc(&doutptr, nbytes);
for (unsigned ii = 0; ii < N; ++ii) {
hipMemcpyAsync(dinptr + ii * nbytesperstream, hptr + ii * nbytesperstream, nbytesperstream, hipMemcpyHostToDevice, stream[ii]);
K<<<nbytesperstream / 512, 512, 0, stream[ii]>>>(doutptr + ii * nbytesperstream, dinptr + ii * nbytesperstream, nbytesperstream);
hipMemcpyAsync(hptr + ii * nbytesperstream, doutptr + ii * nbytesperstream, nbytesperstream, hipMemcpyDeviceToHost, stream[ii]);
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z1KPiS_i
.globl _Z1KPiS_i
.p2align 8
.type _Z1KPiS_i,@function
_Z1KPiS_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v2, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z1KPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z1KPiS_i, .Lfunc_end0-_Z1KPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z1KPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z1KPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define N 2
__global__ void K(int *out, int *in, int size) {
unsigned id = blockIdx.x * blockDim.x + threadIdx.x;
out[id] = in[id] * in[id];
}
int main() {
hipStream_t stream[N];
for (unsigned ii = 0; ii < N; ++ii)
hipStreamCreate(&stream[ii]);
int *hptr, *dinptr, *doutptr;
unsigned nbytesperstream = (1<<10);
unsigned nbytes = N * nbytesperstream;
hipHostAlloc(&hptr, nbytes, 0);
hipMalloc(&dinptr, nbytes);
hipMalloc(&doutptr, nbytes);
for (unsigned ii = 0; ii < N; ++ii) {
hipMemcpyAsync(dinptr + ii * nbytesperstream, hptr + ii * nbytesperstream, nbytesperstream, hipMemcpyHostToDevice, stream[ii]);
K<<<nbytesperstream / 512, 512, 0, stream[ii]>>>(doutptr + ii * nbytesperstream, dinptr + ii * nbytesperstream, nbytesperstream);
hipMemcpyAsync(hptr + ii * nbytesperstream, doutptr + ii * nbytesperstream, nbytesperstream, hipMemcpyDeviceToHost, stream[ii]);
}
return 0;
} | .text
.file "stream2.hip"
.globl _Z16__device_stub__KPiS_i # -- Begin function _Z16__device_stub__KPiS_i
.p2align 4, 0x90
.type _Z16__device_stub__KPiS_i,@function
_Z16__device_stub__KPiS_i: # @_Z16__device_stub__KPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z1KPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z16__device_stub__KPiS_i, .Lfunc_end0-_Z16__device_stub__KPiS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq (%rsp,%rbx), %rdi
addq $128, %rdi
callq hipStreamCreate
addq $8, %rbx
cmpq $8, %rbx
je .LBB1_1
# %bb.2:
movabsq $4294967298, %rbx # imm = 0x100000002
leaq 24(%rsp), %rdi
xorl %r12d, %r12d
movl $2048, %esi # imm = 0x800
xorl %edx, %edx
callq hipHostAlloc
leaq 16(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
leaq 8(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
leaq 128(%rsp), %r13
leaq 510(%rbx), %r14
leaq 32(%rsp), %rbp
leaq 96(%rsp), %r15
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_3 Depth=1
movq 24(%rsp), %rdi
addq %r12, %rdi
movq 8(%rsp), %rsi
addq %r12, %rsi
movq (%r13), %r8
movl $1024, %edx # imm = 0x400
movl $2, %ecx
callq hipMemcpyAsync
addq $4096, %r12 # imm = 0x1000
addq $8, %r13
cmpq $4096, %r12 # imm = 0x1000
jne .LBB1_6
.LBB1_3: # =>This Inner Loop Header: Depth=1
movq 16(%rsp), %rdi
addq %r12, %rdi
movq 24(%rsp), %rsi
addq %r12, %rsi
movq (%r13), %r8
movl $1024, %edx # imm = 0x400
movl $1, %ecx
callq hipMemcpyAsync
movq (%r13), %r9
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4: # in Loop: Header=BB1_3 Depth=1
movq 8(%rsp), %rax
addq %r12, %rax
movq 16(%rsp), %rcx
addq %r12, %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $1024, 4(%rsp) # imm = 0x400
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z1KPiS_i, %edi
movq %r15, %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_5
.LBB1_6:
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z1KPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z1KPiS_i,@object # @_Z1KPiS_i
.section .rodata,"a",@progbits
.globl _Z1KPiS_i
.p2align 3, 0x0
_Z1KPiS_i:
.quad _Z16__device_stub__KPiS_i
.size _Z1KPiS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z1KPiS_i"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z16__device_stub__KPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z1KPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z1KPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE.U32 R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fcc00078e0005 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0005 */
/*0090*/ IMAD R7, R2, R2, RZ ; /* 0x0000000202077224 */
/* 0x004fca00078e02ff */
/*00a0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z1KPiS_i
.globl _Z1KPiS_i
.p2align 8
.type _Z1KPiS_i,@function
_Z1KPiS_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v2, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z1KPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z1KPiS_i, .Lfunc_end0-_Z1KPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z1KPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z1KPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0011a106_00000000-6_stream2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z1KPiS_iPiS_i
.type _Z23__device_stub__Z1KPiS_iPiS_i, @function
_Z23__device_stub__Z1KPiS_iPiS_i:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z1KPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z23__device_stub__Z1KPiS_iPiS_i, .-_Z23__device_stub__Z1KPiS_iPiS_i
.globl _Z1KPiS_i
.type _Z1KPiS_i, @function
_Z1KPiS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z1KPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z1KPiS_i, .-_Z1KPiS_i
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 48(%rsp), %rbp
movq %rbp, %rdi
call cudaStreamCreate@PLT
leaq 56(%rsp), %rdi
call cudaStreamCreate@PLT
movq %rsp, %rdi
movl $0, %edx
movl $2048, %esi
call cudaHostAlloc@PLT
leaq 8(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
movl $0, %ebx
.L13:
movq %rbp, %r12
movq %rbx, %rsi
addq (%rsp), %rsi
movq %rbx, %rdi
addq 8(%rsp), %rdi
movq 0(%rbp), %r8
movl $1, %ecx
movl $1024, %edx
call cudaMemcpyAsync@PLT
movl $512, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $2, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movq 0(%rbp), %r9
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
movq %rbx, %rsi
addq 16(%rsp), %rsi
movq %rbx, %rdi
addq (%rsp), %rdi
movq (%r12), %r8
movl $2, %ecx
movl $1024, %edx
call cudaMemcpyAsync@PLT
addq $8, %rbp
addq $4096, %rbx
cmpq $8192, %rbx
jne .L13
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq %rbx, %rsi
addq 8(%rsp), %rsi
movq %rbx, %rdi
addq 16(%rsp), %rdi
movl $1024, %edx
call _Z23__device_stub__Z1KPiS_iPiS_i
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z1KPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z1KPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "stream2.hip"
.globl _Z16__device_stub__KPiS_i # -- Begin function _Z16__device_stub__KPiS_i
.p2align 4, 0x90
.type _Z16__device_stub__KPiS_i,@function
_Z16__device_stub__KPiS_i: # @_Z16__device_stub__KPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z1KPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z16__device_stub__KPiS_i, .Lfunc_end0-_Z16__device_stub__KPiS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq (%rsp,%rbx), %rdi
addq $128, %rdi
callq hipStreamCreate
addq $8, %rbx
cmpq $8, %rbx
je .LBB1_1
# %bb.2:
movabsq $4294967298, %rbx # imm = 0x100000002
leaq 24(%rsp), %rdi
xorl %r12d, %r12d
movl $2048, %esi # imm = 0x800
xorl %edx, %edx
callq hipHostAlloc
leaq 16(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
leaq 8(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
leaq 128(%rsp), %r13
leaq 510(%rbx), %r14
leaq 32(%rsp), %rbp
leaq 96(%rsp), %r15
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_3 Depth=1
movq 24(%rsp), %rdi
addq %r12, %rdi
movq 8(%rsp), %rsi
addq %r12, %rsi
movq (%r13), %r8
movl $1024, %edx # imm = 0x400
movl $2, %ecx
callq hipMemcpyAsync
addq $4096, %r12 # imm = 0x1000
addq $8, %r13
cmpq $4096, %r12 # imm = 0x1000
jne .LBB1_6
.LBB1_3: # =>This Inner Loop Header: Depth=1
movq 16(%rsp), %rdi
addq %r12, %rdi
movq 24(%rsp), %rsi
addq %r12, %rsi
movq (%r13), %r8
movl $1024, %edx # imm = 0x400
movl $1, %ecx
callq hipMemcpyAsync
movq (%r13), %r9
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4: # in Loop: Header=BB1_3 Depth=1
movq 8(%rsp), %rax
addq %r12, %rax
movq 16(%rsp), %rcx
addq %r12, %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $1024, 4(%rsp) # imm = 0x400
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z1KPiS_i, %edi
movq %r15, %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_5
.LBB1_6:
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z1KPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z1KPiS_i,@object # @_Z1KPiS_i
.section .rodata,"a",@progbits
.globl _Z1KPiS_i
.p2align 3, 0x0
_Z1KPiS_i:
.quad _Z16__device_stub__KPiS_i
.size _Z1KPiS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z1KPiS_i"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z16__device_stub__KPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z1KPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void addScalarInArrayInPlace(float* in, float* add, float scale, int size) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
for (; tid < size; tid += stride)
if (tid < size) in[tid] += add[0] * scale;
} | code for sm_80
Function : _Z23addScalarInArrayInPlacePfS_fi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x174], PT ; /* 0x00005d0003007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, c[0x0][0xc] ; /* 0x0000030000007a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x320 ; /* 0x0000029000007945 */
/* 0x000fe60003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000209000 */
/*00b0*/ IMAD.MOV R9, RZ, RZ, -R0 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a00 */
/*00c0*/ IADD3 R2, R0.reuse, R3, RZ ; /* 0x0000000300027210 */
/* 0x040fe40007ffe0ff */
/*00d0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45070 */
/*00e0*/ LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff077212 */
/* 0x000fc800078e33ff */
/*00f0*/ IADD3 R7, R7, c[0x0][0x174], R0 ; /* 0x00005d0007077a10 */
/* 0x000fe20007ffe000 */
/*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0130*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0140*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x002fc800078e02ff */
/*0150*/ IMAD.HI.U32 R2, R5, R9, R4 ; /* 0x0000000905027227 */
/* 0x000fcc00078e0004 */
/*0160*/ IMAD.HI.U32 R2, R2, R7, RZ ; /* 0x0000000702027227 */
/* 0x000fca00078e00ff */
/*0170*/ IADD3 R4, -R2, RZ, RZ ; /* 0x000000ff02047210 */
/* 0x000fca0007ffe1ff */
/*0180*/ IMAD R7, R0, R4, R7 ; /* 0x0000000400077224 */
/* 0x000fca00078e0207 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f06070 */
/*01a0*/ @P0 IMAD.IADD R7, R7, 0x1, -R0 ; /* 0x0000000107070824 */
/* 0x000fe200078e0a00 */
/*01b0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fc80007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26070 */
/*01d0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*01f0*/ IADD3 R4, R2.reuse, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x040fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0210*/ LOP3.LUT P0, R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fda000780c0ff */
/*0220*/ @!P0 BRA 0x310 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0230*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0240*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0004 */
/*0250*/ MOV R6, c[0x0][0x168] ; /* 0x00005a0000067a02 */
/* 0x000fe20000000f00 */
/*0260*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff077624 */
/* 0x000fce00078e00ff */
/*0270*/ IMAD.WIDE R4, R3, R8, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fc800078e0208 */
/*0280*/ LDG.E R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000ea8000c1e1900 */
/*0290*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea2000c1e1900 */
/*02a0*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*02b0*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*02c0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*02d0*/ FFMA R9, R8, c[0x0][0x170], R9 ; /* 0x00005c0008097a23 */
/* 0x004fca0000000009 */
/*02e0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e4000c101904 */
/*02f0*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x001fca00078e0204 */
/*0300*/ @P0 BRA 0x280 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0310*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0320*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0330*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0340*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fc80000000f00 */
/*0350*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x000fe200078e00ff */
/*0360*/ LDG.E R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea6000c1e1900 */
/*0370*/ IMAD.WIDE R6, R3, R6, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x002fca00078e0206 */
/*0380*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x000ea4000c1e1900 */
/*0390*/ FFMA R15, R2, c[0x0][0x170], R9 ; /* 0x00005c00020f7a23 */
/* 0x004fe40000000009 */
/*03a0*/ IMAD.WIDE R8, R0, 0x4, R6 ; /* 0x0000000400087825 */
/* 0x000fc600078e0206 */
/*03b0*/ STG.E [R6.64], R15 ; /* 0x0000000f06007986 */
/* 0x0001e8000c101904 */
/*03c0*/ LDG.E R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea8000c1e1900 */
/*03d0*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x000ea4000c1e1900 */
/*03e0*/ FFMA R17, R2, c[0x0][0x170], R11 ; /* 0x00005c0002117a23 */
/* 0x004fc4000000000b */
/*03f0*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0208 */
/*0400*/ STG.E [R8.64], R17 ; /* 0x0000001108007986 */
/* 0x0003e8000c101904 */
/*0410*/ LDG.E R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea8000c1e1900 */
/*0420*/ LDG.E R13, [R10.64] ; /* 0x000000040a0d7981 */
/* 0x000ea4000c1e1900 */
/*0430*/ FFMA R19, R2, c[0x0][0x170], R13 ; /* 0x00005c0002137a23 */
/* 0x004fc4000000000d */
/*0440*/ IMAD.WIDE R12, R0, 0x4, R10 ; /* 0x00000004000c7825 */
/* 0x000fc600078e020a */
/*0450*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */
/* 0x0003e8000c101904 */
/*0460*/ LDG.E R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R7, [R12.64] ; /* 0x000000040c077981 */
/* 0x001ea2000c1e1900 */
/*0480*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0490*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*04a0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x174], PT ; /* 0x00005d0003007a0c */
/* 0x000fe20003f06270 */
/*04b0*/ FFMA R7, R2, c[0x0][0x170], R7 ; /* 0x00005c0002077a23 */
/* 0x004fca0000000007 */
/*04c0*/ STG.E [R12.64], R7 ; /* 0x000000070c007986 */
/* 0x0003ee000c101904 */
/*04d0*/ @!P0 BRA 0x350 ; /* 0xfffffe7000008947 */
/* 0x000fea000383ffff */
/*04e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04f0*/ BRA 0x4f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void addScalarInArrayInPlace(float* in, float* add, float scale, int size) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
for (; tid < size; tid += stride)
if (tid < size) in[tid] += add[0] * scale;
} | .file "tmpxft_0010032a_00000000-6_addScalarInArrayInPlace.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z23addScalarInArrayInPlacePfS_fiPfS_fi
.type _Z47__device_stub__Z23addScalarInArrayInPlacePfS_fiPfS_fi, @function
_Z47__device_stub__Z23addScalarInArrayInPlacePfS_fiPfS_fi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z23addScalarInArrayInPlacePfS_fi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z47__device_stub__Z23addScalarInArrayInPlacePfS_fiPfS_fi, .-_Z47__device_stub__Z23addScalarInArrayInPlacePfS_fiPfS_fi
.globl _Z23addScalarInArrayInPlacePfS_fi
.type _Z23addScalarInArrayInPlacePfS_fi, @function
_Z23addScalarInArrayInPlacePfS_fi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z23addScalarInArrayInPlacePfS_fiPfS_fi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z23addScalarInArrayInPlacePfS_fi, .-_Z23addScalarInArrayInPlacePfS_fi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z23addScalarInArrayInPlacePfS_fi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z23addScalarInArrayInPlacePfS_fi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void addScalarInArrayInPlace(float* in, float* add, float scale, int size) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
for (; tid < size; tid += stride)
if (tid < size) in[tid] += add[0] * scale;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void addScalarInArrayInPlace(float* in, float* add, float scale, int size) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
for (; tid < size; tid += stride)
if (tid < size) in[tid] += add[0] * scale;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void addScalarInArrayInPlace(float* in, float* add, float scale, int size) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
for (; tid < size; tid += stride)
if (tid < size) in[tid] += add[0] * scale;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23addScalarInArrayInPlacePfS_fi
.globl _Z23addScalarInArrayInPlacePfS_fi
.p2align 8
.type _Z23addScalarInArrayInPlacePfS_fi,@function
_Z23addScalarInArrayInPlacePfS_fi:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s8, s[0:1], 0x14
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s1, s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v0, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s9
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_ashr_i32 s3, s2, 31
s_lshl_b64 s[4:5], s[2:3], 2
s_mov_b32 s3, 0
.LBB0_2:
global_load_b32 v4, v0, s[6:7]
global_load_b32 v5, v[2:3], off
v_add_nc_u32_e32 v1, s2, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_le_i32_e32 vcc_lo, s8, v1
s_or_b32 s3, vcc_lo, s3
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v5, s1, v4
global_store_b32 v[2:3], v5, off
v_add_co_u32 v2, s0, v2, s4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s5, v3, s0
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23addScalarInArrayInPlacePfS_fi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23addScalarInArrayInPlacePfS_fi, .Lfunc_end0-_Z23addScalarInArrayInPlacePfS_fi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23addScalarInArrayInPlacePfS_fi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z23addScalarInArrayInPlacePfS_fi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void addScalarInArrayInPlace(float* in, float* add, float scale, int size) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
for (; tid < size; tid += stride)
if (tid < size) in[tid] += add[0] * scale;
} | .text
.file "addScalarInArrayInPlace.hip"
.globl _Z38__device_stub__addScalarInArrayInPlacePfS_fi # -- Begin function _Z38__device_stub__addScalarInArrayInPlacePfS_fi
.p2align 4, 0x90
.type _Z38__device_stub__addScalarInArrayInPlacePfS_fi,@function
_Z38__device_stub__addScalarInArrayInPlacePfS_fi: # @_Z38__device_stub__addScalarInArrayInPlacePfS_fi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z23addScalarInArrayInPlacePfS_fi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z38__device_stub__addScalarInArrayInPlacePfS_fi, .Lfunc_end0-_Z38__device_stub__addScalarInArrayInPlacePfS_fi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23addScalarInArrayInPlacePfS_fi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23addScalarInArrayInPlacePfS_fi,@object # @_Z23addScalarInArrayInPlacePfS_fi
.section .rodata,"a",@progbits
.globl _Z23addScalarInArrayInPlacePfS_fi
.p2align 3, 0x0
_Z23addScalarInArrayInPlacePfS_fi:
.quad _Z38__device_stub__addScalarInArrayInPlacePfS_fi
.size _Z23addScalarInArrayInPlacePfS_fi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z23addScalarInArrayInPlacePfS_fi"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__addScalarInArrayInPlacePfS_fi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23addScalarInArrayInPlacePfS_fi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z23addScalarInArrayInPlacePfS_fi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x174], PT ; /* 0x00005d0003007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, c[0x0][0xc] ; /* 0x0000030000007a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x320 ; /* 0x0000029000007945 */
/* 0x000fe60003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000209000 */
/*00b0*/ IMAD.MOV R9, RZ, RZ, -R0 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a00 */
/*00c0*/ IADD3 R2, R0.reuse, R3, RZ ; /* 0x0000000300027210 */
/* 0x040fe40007ffe0ff */
/*00d0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45070 */
/*00e0*/ LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff077212 */
/* 0x000fc800078e33ff */
/*00f0*/ IADD3 R7, R7, c[0x0][0x174], R0 ; /* 0x00005d0007077a10 */
/* 0x000fe20007ffe000 */
/*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0130*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0140*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x002fc800078e02ff */
/*0150*/ IMAD.HI.U32 R2, R5, R9, R4 ; /* 0x0000000905027227 */
/* 0x000fcc00078e0004 */
/*0160*/ IMAD.HI.U32 R2, R2, R7, RZ ; /* 0x0000000702027227 */
/* 0x000fca00078e00ff */
/*0170*/ IADD3 R4, -R2, RZ, RZ ; /* 0x000000ff02047210 */
/* 0x000fca0007ffe1ff */
/*0180*/ IMAD R7, R0, R4, R7 ; /* 0x0000000400077224 */
/* 0x000fca00078e0207 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f06070 */
/*01a0*/ @P0 IMAD.IADD R7, R7, 0x1, -R0 ; /* 0x0000000107070824 */
/* 0x000fe200078e0a00 */
/*01b0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fc80007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26070 */
/*01d0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*01f0*/ IADD3 R4, R2.reuse, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x040fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0210*/ LOP3.LUT P0, R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fda000780c0ff */
/*0220*/ @!P0 BRA 0x310 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0230*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0240*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0004 */
/*0250*/ MOV R6, c[0x0][0x168] ; /* 0x00005a0000067a02 */
/* 0x000fe20000000f00 */
/*0260*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff077624 */
/* 0x000fce00078e00ff */
/*0270*/ IMAD.WIDE R4, R3, R8, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fc800078e0208 */
/*0280*/ LDG.E R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000ea8000c1e1900 */
/*0290*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea2000c1e1900 */
/*02a0*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*02b0*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*02c0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*02d0*/ FFMA R9, R8, c[0x0][0x170], R9 ; /* 0x00005c0008097a23 */
/* 0x004fca0000000009 */
/*02e0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e4000c101904 */
/*02f0*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x001fca00078e0204 */
/*0300*/ @P0 BRA 0x280 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0310*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0320*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0330*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0340*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fc80000000f00 */
/*0350*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x000fe200078e00ff */
/*0360*/ LDG.E R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea6000c1e1900 */
/*0370*/ IMAD.WIDE R6, R3, R6, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x002fca00078e0206 */
/*0380*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x000ea4000c1e1900 */
/*0390*/ FFMA R15, R2, c[0x0][0x170], R9 ; /* 0x00005c00020f7a23 */
/* 0x004fe40000000009 */
/*03a0*/ IMAD.WIDE R8, R0, 0x4, R6 ; /* 0x0000000400087825 */
/* 0x000fc600078e0206 */
/*03b0*/ STG.E [R6.64], R15 ; /* 0x0000000f06007986 */
/* 0x0001e8000c101904 */
/*03c0*/ LDG.E R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea8000c1e1900 */
/*03d0*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x000ea4000c1e1900 */
/*03e0*/ FFMA R17, R2, c[0x0][0x170], R11 ; /* 0x00005c0002117a23 */
/* 0x004fc4000000000b */
/*03f0*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0208 */
/*0400*/ STG.E [R8.64], R17 ; /* 0x0000001108007986 */
/* 0x0003e8000c101904 */
/*0410*/ LDG.E R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea8000c1e1900 */
/*0420*/ LDG.E R13, [R10.64] ; /* 0x000000040a0d7981 */
/* 0x000ea4000c1e1900 */
/*0430*/ FFMA R19, R2, c[0x0][0x170], R13 ; /* 0x00005c0002137a23 */
/* 0x004fc4000000000d */
/*0440*/ IMAD.WIDE R12, R0, 0x4, R10 ; /* 0x00000004000c7825 */
/* 0x000fc600078e020a */
/*0450*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */
/* 0x0003e8000c101904 */
/*0460*/ LDG.E R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R7, [R12.64] ; /* 0x000000040c077981 */
/* 0x001ea2000c1e1900 */
/*0480*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0490*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*04a0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x174], PT ; /* 0x00005d0003007a0c */
/* 0x000fe20003f06270 */
/*04b0*/ FFMA R7, R2, c[0x0][0x170], R7 ; /* 0x00005c0002077a23 */
/* 0x004fca0000000007 */
/*04c0*/ STG.E [R12.64], R7 ; /* 0x000000070c007986 */
/* 0x0003ee000c101904 */
/*04d0*/ @!P0 BRA 0x350 ; /* 0xfffffe7000008947 */
/* 0x000fea000383ffff */
/*04e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04f0*/ BRA 0x4f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23addScalarInArrayInPlacePfS_fi
.globl _Z23addScalarInArrayInPlacePfS_fi
.p2align 8
.type _Z23addScalarInArrayInPlacePfS_fi,@function
_Z23addScalarInArrayInPlacePfS_fi:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s8, s[0:1], 0x14
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s1, s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v0, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s9
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_ashr_i32 s3, s2, 31
s_lshl_b64 s[4:5], s[2:3], 2
s_mov_b32 s3, 0
.LBB0_2:
global_load_b32 v4, v0, s[6:7]
global_load_b32 v5, v[2:3], off
v_add_nc_u32_e32 v1, s2, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_le_i32_e32 vcc_lo, s8, v1
s_or_b32 s3, vcc_lo, s3
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v5, s1, v4
global_store_b32 v[2:3], v5, off
v_add_co_u32 v2, s0, v2, s4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s5, v3, s0
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23addScalarInArrayInPlacePfS_fi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23addScalarInArrayInPlacePfS_fi, .Lfunc_end0-_Z23addScalarInArrayInPlacePfS_fi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23addScalarInArrayInPlacePfS_fi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z23addScalarInArrayInPlacePfS_fi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010032a_00000000-6_addScalarInArrayInPlace.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z23addScalarInArrayInPlacePfS_fiPfS_fi
.type _Z47__device_stub__Z23addScalarInArrayInPlacePfS_fiPfS_fi, @function
_Z47__device_stub__Z23addScalarInArrayInPlacePfS_fiPfS_fi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z23addScalarInArrayInPlacePfS_fi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z47__device_stub__Z23addScalarInArrayInPlacePfS_fiPfS_fi, .-_Z47__device_stub__Z23addScalarInArrayInPlacePfS_fiPfS_fi
.globl _Z23addScalarInArrayInPlacePfS_fi
.type _Z23addScalarInArrayInPlacePfS_fi, @function
_Z23addScalarInArrayInPlacePfS_fi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z23addScalarInArrayInPlacePfS_fiPfS_fi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z23addScalarInArrayInPlacePfS_fi, .-_Z23addScalarInArrayInPlacePfS_fi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z23addScalarInArrayInPlacePfS_fi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z23addScalarInArrayInPlacePfS_fi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "addScalarInArrayInPlace.hip"
.globl _Z38__device_stub__addScalarInArrayInPlacePfS_fi # -- Begin function _Z38__device_stub__addScalarInArrayInPlacePfS_fi
.p2align 4, 0x90
.type _Z38__device_stub__addScalarInArrayInPlacePfS_fi,@function
_Z38__device_stub__addScalarInArrayInPlacePfS_fi: # @_Z38__device_stub__addScalarInArrayInPlacePfS_fi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z23addScalarInArrayInPlacePfS_fi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z38__device_stub__addScalarInArrayInPlacePfS_fi, .Lfunc_end0-_Z38__device_stub__addScalarInArrayInPlacePfS_fi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23addScalarInArrayInPlacePfS_fi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23addScalarInArrayInPlacePfS_fi,@object # @_Z23addScalarInArrayInPlacePfS_fi
.section .rodata,"a",@progbits
.globl _Z23addScalarInArrayInPlacePfS_fi
.p2align 3, 0x0
_Z23addScalarInArrayInPlacePfS_fi:
.quad _Z38__device_stub__addScalarInArrayInPlacePfS_fi
.size _Z23addScalarInArrayInPlacePfS_fi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z23addScalarInArrayInPlacePfS_fi"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__addScalarInArrayInPlacePfS_fi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23addScalarInArrayInPlacePfS_fi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <ostream>
#include <sstream>
#include <iomanip>
#include <stdio.h>
#include <vector>
#include <fstream>
const unsigned int field_size = 53;
const unsigned int step = 100;
__device__ unsigned int d_field_size;
__device__ float d_dx;
__device__ float d_a;
__device__ float d_w;
__device__ float d_beta;
__device__ float d_tau;
__device__ float d_r0;
__global__ void calc_step(float *d_phase, float *d_phase_tmp) {
int x_i = blockIdx.x * blockDim.x + threadIdx.x;
int y_i = blockIdx.y * blockDim.y + threadIdx.y;
if (x_i <= 0 || x_i >= d_field_size - 1 || y_i <= 0 || y_i >= d_field_size - 1) return;
int i = y_i * d_field_size + x_i;
float ddx = d_dx * d_dx;
float rpx = (d_phase[i + 1] - 2.* d_phase[i] + d_phase[i - 1]) / ddx;
float rpy = (d_phase[i + d_field_size] - 2. * d_phase[i] + d_phase[i - d_field_size]) / ddx;
float dpi1 = d_a * d_a * (rpx + rpy);
float dpi2 = 4. * d_w * d_phase[i] * (1 - d_phase[i]) * (d_phase[i] - .5 + d_beta);
float dpi = dpi1 + dpi2;
d_phase_tmp[i] = d_phase[i] + d_tau * dpi;
}
__global__ void set_bc(float *field) {
int x_i = blockIdx.x * blockDim.x + threadIdx.x;
if ( x_i >= field_size - 2) return;
int i = x_i + 1;
// top
field[i] = field[i+field_size];
// bottom
field[field_size * (field_size - 1) + i] = field[field_size * (field_size - 2) + i];
// left
field[field_size * i] = field[field_size * i + 1];
// right
field[field_size * (i + 1) - 1] = field[field_size * (i + 1) - 2];
return;
}
__global__ void init_field(float *field) {
int x_i = blockIdx.x * blockDim.x + threadIdx.x;
int y_i = blockIdx.y * blockDim.y + threadIdx.y;
if (x_i <= 0 || x_i >= d_field_size - 1 || y_i <= 0 || y_i >= d_field_size - 1) {
return;
}
int i = y_i * d_field_size + x_i;
float y = (y_i - 1) * d_dx;
float x = (x_i - 1) * d_dx;
float r = sqrt(x*x + y*y) - d_r0;
field[i] = .5 * (1. - tanh(sqrt(2. * d_w) / (2. * d_a) * r));
printf("%f\n", field[i]);
return;
}
bool save(float *phase, unsigned int n) {
try {
std::ofstream file;
std::ostringstream filename;
filename << "datas/step_" << std::setfill('0') << std::right << std::setw(std::log10(step)+1) << n << ".dat";
file.open(filename.str(), std::ios_base::app);
file << "#x #y #phase" << std::endl;
// remove boundaries
for (unsigned int y_i = 1; y_i < field_size - 1; y_i++) {
for (unsigned int x_i = 1; x_i < field_size - 1; x_i++) {
file << y_i << ' ' << x_i << ' ' << phase[y_i * field_size + x_i] << std::endl;
}
file << std::endl;
}
file.close();
} catch(char *str) {
std::cout << str << std::endl;
return false;
}
return true;
}
int main() {
unsigned int N = field_size * field_size;
float *phase; // phase field for host
float *d_phase, *d_phase_tmp; // phase field for device
phase = (float *)malloc(N * sizeof(float));
const float dx = 5e-7;
// 界面エネルギー
float gamma = 1.;
// 界面幅
float delta = 4. * dx;
// 界面モビリティ
float M = 4e-14;
// 界面領域
float lambda = .1;
// 勾配計数
float b = 2. * std::atanh(1.-2.*lambda);
float a = std::sqrt(3. * delta * gamma / b);
// エネルギー障壁
float w = 6. * gamma * b / delta;
// フェーズフィールドモビリティ
float M_phi = M * std::sqrt(2. * w) / (6. * a);
// 時間ステップ
float dt = dx * dx / (5. * M_phi * a * a);
printf("Time Step: %.3e[s]\n", dt);
// 固相初期半径
float r0 = .5 * (field_size - 1) * dx;
float beta = .5;
float tau = M_phi * dt;
cudaMemcpyToSymbol(d_field_size, &field_size, sizeof(unsigned int));
cudaMemcpyToSymbol(d_dx, &dx, sizeof(float));
cudaMemcpyToSymbol(d_a, &a, sizeof(float));
cudaMemcpyToSymbol(d_w, &w, sizeof(float));
cudaMemcpyToSymbol(d_beta, &beta, sizeof(float));
cudaMemcpyToSymbol(d_tau, &tau, sizeof(float));
cudaMemcpyToSymbol(d_r0, &r0, sizeof(float));
// allocate memory to GPU
cudaMalloc((void**)&d_phase, N * sizeof(float));
cudaMalloc((void**)&d_phase_tmp, N * sizeof(float));
int threadsPerBlock = 32;
int blocksInGrid = (field_size + threadsPerBlock -1)/threadsPerBlock;
dim3 blocks(threadsPerBlock, threadsPerBlock);
dim3 grid(blocksInGrid, blocksInGrid);
cudaMemcpy(d_phase, phase, N * sizeof(float), cudaMemcpyHostToDevice);
init_field<<<grid, blocks>>>(d_phase);
set_bc<<<1, field_size - 2>>>(d_phase);
// メインループ
for (unsigned int n = 0; n < step; n++) {
printf("step: %d\n", n);
cudaMemcpy(phase, d_phase, N * sizeof(float), cudaMemcpyDeviceToHost);
save(phase, n);
calc_step<<<grid, blocks>>>(d_phase, d_phase_tmp);
// Swap
cudaMemcpy(d_phase, d_phase_tmp, N * sizeof(float), cudaMemcpyDeviceToDevice);
set_bc<<<1, field_size - 2>>>(d_phase);
}
free(phase);
cudaFree(d_phase);
cudaFree(d_phase_tmp);
return 0;
} | .file "tmpxft_000ea759_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4407:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4407:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z9calc_stepPfS_PfS_
.type _Z30__device_stub__Z9calc_stepPfS_PfS_, @function
_Z30__device_stub__Z9calc_stepPfS_PfS_:
.LFB4429:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9calc_stepPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4429:
.size _Z30__device_stub__Z9calc_stepPfS_PfS_, .-_Z30__device_stub__Z9calc_stepPfS_PfS_
.globl _Z9calc_stepPfS_
.type _Z9calc_stepPfS_, @function
_Z9calc_stepPfS_:
.LFB4430:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9calc_stepPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4430:
.size _Z9calc_stepPfS_, .-_Z9calc_stepPfS_
.globl _Z25__device_stub__Z6set_bcPfPf
.type _Z25__device_stub__Z6set_bcPfPf, @function
_Z25__device_stub__Z6set_bcPfPf:
.LFB4431:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6set_bcPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4431:
.size _Z25__device_stub__Z6set_bcPfPf, .-_Z25__device_stub__Z6set_bcPfPf
.globl _Z6set_bcPf
.type _Z6set_bcPf, @function
_Z6set_bcPf:
.LFB4432:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z6set_bcPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4432:
.size _Z6set_bcPf, .-_Z6set_bcPf
.globl _Z30__device_stub__Z10init_fieldPfPf
.type _Z30__device_stub__Z10init_fieldPfPf, @function
_Z30__device_stub__Z10init_fieldPfPf:
.LFB4433:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10init_fieldPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4433:
.size _Z30__device_stub__Z10init_fieldPfPf, .-_Z30__device_stub__Z10init_fieldPfPf
.globl _Z10init_fieldPf
.type _Z10init_fieldPf, @function
_Z10init_fieldPf:
.LFB4434:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10init_fieldPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4434:
.size _Z10init_fieldPf, .-_Z10init_fieldPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10init_fieldPf"
.LC1:
.string "_Z6set_bcPf"
.LC2:
.string "_Z9calc_stepPfS_"
.LC3:
.string "d_field_size"
.LC4:
.string "d_dx"
.LC5:
.string "d_a"
.LC6:
.string "d_w"
.LC7:
.string "d_beta"
.LC8:
.string "d_tau"
.LC9:
.string "d_r0"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4436:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10init_fieldPf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6set_bcPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z9calc_stepPfS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL12d_field_size(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL4d_dx(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL3d_a(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL3d_w(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6d_beta(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5d_tau(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL4d_r0(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4436:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.1
.LC10:
.string "datas/step_"
.LC11:
.string ".dat"
.LC12:
.string "#x #y #phase"
.text
.globl _Z4savePfj
.type _Z4savePfj, @function
_Z4savePfj:
.LFB4402:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4402
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $968, %rsp
.cfi_def_cfa_offset 1024
movq %rdi, %r14
movl %esi, %r12d
movq %fs:40, %rax
movq %rax, 952(%rsp)
xorl %eax, %eax
leaq 432(%rsp), %rbx
leaq 680(%rsp), %rdi
call _ZNSt8ios_baseC2Ev@PLT
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 680(%rsp)
movq $0, 896(%rsp)
movb $0, 904(%rsp)
movb $0, 905(%rsp)
movq $0, 912(%rsp)
movq $0, 920(%rsp)
movq $0, 928(%rsp)
movq $0, 936(%rsp)
movq 8+_ZTTSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 432(%rsp)
movq -24(%rax), %rax
movq 16+_ZTTSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %rcx
movq %rcx, 432(%rsp,%rax)
movq 432(%rsp), %rax
movq %rbx, %rdi
addq -24(%rax), %rdi
movl $0, %esi
.LEHB0:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE0:
leaq 24+_ZTVSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 432(%rsp)
leaq 40(%rax), %rax
movq %rax, 680(%rsp)
leaq 440(%rsp), %rdi
.LEHB1:
call _ZNSt13basic_filebufIcSt11char_traitsIcEEC1Ev@PLT
.LEHE1:
leaq 440(%rsp), %rsi
leaq 680(%rsp), %rdi
.LEHB2:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE2:
jmp .L98
.L88:
endbr64
movq %rax, %rbx
movq %rdx, %rbp
leaq 440(%rsp), %rdi
call _ZNSt13basic_filebufIcSt11char_traitsIcEED1Ev@PLT
movq %rbx, %rdi
.L32:
movq 8+_ZTTSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 432(%rsp)
movq -24(%rax), %rax
movq 16+_ZTTSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %rcx
movq %rcx, 432(%rsp,%rax)
movq %rdi, %rbx
.L33:
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 680(%rsp)
leaq 680(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq %rbx, %rdi
.L34:
cmpq $1, %rbp
je .L78
movq 952(%rsp), %rax
subq %fs:40, %rax
je .L79
call __stack_chk_fail@PLT
.L87:
endbr64
movq %rax, %rdi
movq %rdx, %rbp
jmp .L32
.L86:
endbr64
movq %rax, %rbx
movq %rdx, %rbp
jmp .L33
.L98:
leaq 48(%rsp), %rbx
leaq 160(%rsp), %rdi
call _ZNSt8ios_baseC2Ev@PLT
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 160(%rsp)
movq $0, 376(%rsp)
movb $0, 384(%rsp)
movb $0, 385(%rsp)
movq $0, 392(%rsp)
movq $0, 400(%rsp)
movq $0, 408(%rsp)
movq $0, 416(%rsp)
movq 8+_ZTTNSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 48(%rsp)
movq -24(%rax), %rax
movq 16+_ZTTNSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rcx
movq %rcx, 48(%rsp,%rax)
movq 48(%rsp), %rax
movq %rbx, %rdi
addq -24(%rax), %rdi
movl $0, %esi
.LEHB3:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE3:
leaq 24+_ZTVNSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 48(%rsp)
leaq 40(%rax), %rax
movq %rax, 160(%rsp)
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 56(%rsp)
movq $0, 64(%rsp)
movq $0, 72(%rsp)
movq $0, 80(%rsp)
movq $0, 88(%rsp)
movq $0, 96(%rsp)
movq $0, 104(%rsp)
leaq 112(%rsp), %rdi
call _ZNSt6localeC1Ev@PLT
leaq 16+_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 56(%rsp)
movl $16, 120(%rsp)
leaq 144(%rsp), %rax
movq %rax, 128(%rsp)
movq $0, 136(%rsp)
movb $0, 144(%rsp)
leaq 56(%rsp), %rsi
leaq 160(%rsp), %rdi
.LEHB4:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE4:
jmp .L99
.L90:
endbr64
movq %rax, %rbx
movq %rdx, %rbp
leaq 16+_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 56(%rsp)
movq 128(%rsp), %rdi
leaq 144(%rsp), %rax
cmpq %rax, %rdi
je .L37
movq 144(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L37:
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 56(%rsp)
leaq 112(%rsp), %rdi
call _ZNSt6localeD1Ev@PLT
movq 8+_ZTTNSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 48(%rsp)
movq -24(%rax), %rax
movq 16+_ZTTNSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rcx
movq %rcx, 48(%rsp,%rax)
.L38:
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 160(%rsp)
leaq 160(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
.L39:
leaq 432(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq %rbx, %rdi
jmp .L34
.L89:
endbr64
movq %rax, %rbx
movq %rdx, %rbp
jmp .L38
.L99:
leaq 48(%rsp), %rdi
movl $11, %edx
leaq .LC10(%rip), %rsi
.LEHB5:
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 48(%rsp), %rax
movq -24(%rax), %rax
leaq 48(%rsp,%rax), %rbp
cmpb $0, 225(%rbp)
je .L100
.L40:
movb $48, 224(%rbp)
movq 48(%rsp), %rdx
leaq 48(%rsp), %rdi
movq %rdi, %rcx
addq -24(%rdx), %rcx
movl 24(%rcx), %eax
andb $79, %al
orb $-128, %al
movl %eax, 24(%rcx)
movq -24(%rdx), %rax
movq $3, 64(%rsp,%rax)
movl %r12d, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
jmp .L101
.L100:
movq 240(%rbp), %rbx
testq %rbx, %rbx
je .L102
cmpb $0, 56(%rbx)
je .L103
.L43:
movb $1, 225(%rbp)
jmp .L40
.L102:
movq 952(%rsp), %rax
subq %fs:40, %rax
jne .L104
call _ZSt16__throw_bad_castv@PLT
.L104:
call __stack_chk_fail@PLT
.L103:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $32, %esi
movq %rbx, %rdi
call *48(%rax)
jmp .L43
.L101:
movq %rax, %rdi
movl $4, %edx
leaq .LC11(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.LEHE5:
leaq 32(%rsp), %rax
movq %rax, 16(%rsp)
movq $0, 24(%rsp)
movb $0, 32(%rsp)
movq 96(%rsp), %r8
testq %r8, %r8
je .L44
movq 80(%rsp), %rax
movq %r8, %rdx
cmpq %r8, %rax
cmovnb %rax, %r8
testq %rax, %rax
cmove %rdx, %r8
movq 88(%rsp), %rcx
leaq 16(%rsp), %rdi
subq %rcx, %r8
movl $0, %edx
movl $0, %esi
.LEHB6:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm@PLT
jmp .L46
.L44:
leaq 128(%rsp), %rsi
leaq 16(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_assignERKS4_@PLT
.LEHE6:
.L46:
leaq 440(%rsp), %rdi
movl $17, %edx
movq 16(%rsp), %rsi
.LEHB7:
call _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
testq %rax, %rax
je .L105
movq 432(%rsp), %rax
movq -24(%rax), %rax
leaq 432(%rsp,%rax), %rdi
movl $0, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L51
.L91:
endbr64
movq %rax, %rbx
movq %rdx, %rbp
leaq 16(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L49:
leaq 48(%rsp), %rdi
call _ZNSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEED1Ev@PLT
jmp .L39
.L105:
movq 432(%rsp), %rax
movq -24(%rax), %rax
leaq 432(%rsp,%rax), %rdi
movl 32(%rdi), %esi
orl $4, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
.LEHE7:
.L51:
movq 16(%rsp), %rdi
leaq 32(%rsp), %rax
cmpq %rax, %rdi
je .L52
movq 32(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L52:
leaq 432(%rsp), %rdi
movl $12, %edx
leaq .LC12(%rip), %rsi
.LEHB8:
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 432(%rsp), %rax
movq -24(%rax), %rax
movq 672(%rsp,%rax), %rbx
testq %rbx, %rbx
je .L106
cmpb $0, 56(%rbx)
je .L55
movzbl 67(%rbx), %eax
.L56:
movsbl %al, %esi
leaq 432(%rsp), %rdi
call _ZNSo3putEc@PLT
jmp .L107
.L106:
movq 952(%rsp), %rax
subq %fs:40, %rax
jne .L108
call _ZSt16__throw_bad_castv@PLT
.L108:
call __stack_chk_fail@PLT
.L55:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
jmp .L56
.L107:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $212, %r14
movl $1, %r13d
leaq 432(%rsp), %r15
jmp .L57
.L115:
movq %rax, %rbx
movb $32, 14(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rbx,%rax)
je .L58
leaq 14(%rsp), %rsi
movl $1, %edx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rbx
.L59:
movq %rbp, %rsi
movq %rbx, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
jmp .L109
.L58:
movl $32, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
jmp .L59
.L109:
movq %rax, %rbx
movb $32, 15(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rbx,%rax)
je .L60
leaq 15(%rsp), %rsi
movl $1, %edx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rbx
.L61:
pxor %xmm0, %xmm0
cvtss2sd (%r14,%rbp,4), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
jmp .L110
.L60:
movl $32, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
jmp .L61
.L110:
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .L111
cmpb $0, 56(%r12)
je .L64
movzbl 67(%r12), %esi
.L65:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
jmp .L112
.L111:
movq 952(%rsp), %rax
subq %fs:40, %rax
jne .L113
call _ZSt16__throw_bad_castv@PLT
.L83:
endbr64
movq %rax, %rbx
movq %rdx, %rbp
jmp .L49
.L113:
call __stack_chk_fail@PLT
.L64:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L65
.L112:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %rbp
cmpq $52, %rbp
je .L114
.L66:
movq %r13, %rsi
movq %r15, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
jmp .L115
.L114:
movq 432(%rsp), %rax
movq -24(%rax), %rax
movq 672(%rsp,%rax), %rbx
testq %rbx, %rbx
je .L116
cmpb $0, 56(%rbx)
je .L69
movzbl 67(%rbx), %esi
.L70:
movsbl %sil, %esi
movq %r15, %rdi
call _ZNSo3putEc@PLT
jmp .L117
.L116:
movq 952(%rsp), %rax
subq %fs:40, %rax
jne .L118
call _ZSt16__throw_bad_castv@PLT
.L118:
call __stack_chk_fail@PLT
.L69:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L70
.L117:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $212, %r14
addq $1, %r13
cmpq $52, %r13
je .L71
.L57:
movl $1, %ebp
jmp .L66
.L71:
leaq 440(%rsp), %rdi
call _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv@PLT
.LEHE8:
testq %rax, %rax
je .L119
.L72:
leaq 24+_ZTVNSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 48(%rsp)
leaq 40(%rax), %rax
movq %rax, 160(%rsp)
leaq 16+_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 56(%rsp)
movq 128(%rsp), %rdi
leaq 144(%rsp), %rax
cmpq %rax, %rdi
je .L73
movq 144(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L73:
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 56(%rsp)
leaq 112(%rsp), %rdi
call _ZNSt6localeD1Ev@PLT
movq 8+_ZTTNSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 48(%rsp)
movq -24(%rax), %rax
movq 16+_ZTTNSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rcx
movq %rcx, 48(%rsp,%rax)
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 160(%rsp)
leaq 160(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
leaq 24+_ZTVSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 432(%rsp)
leaq 40(%rax), %rax
movq %rax, 680(%rsp)
leaq 16+_ZTVSt13basic_filebufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 440(%rsp)
leaq 440(%rsp), %rdi
.LEHB9:
call _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv@PLT
.LEHE9:
jmp .L76
.L119:
movq 432(%rsp), %rax
movq -24(%rax), %rax
leaq 432(%rsp,%rax), %rdi
movl 32(%rdi), %esi
orl $4, %esi
.LEHB10:
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
.LEHE10:
jmp .L72
.L92:
endbr64
movq %rax, %rdi
call __cxa_begin_catch@PLT
call __cxa_end_catch@PLT
.L76:
leaq 544(%rsp), %rdi
call _ZNSt12__basic_fileIcED1Ev@PLT
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 440(%rsp)
leaq 496(%rsp), %rdi
call _ZNSt6localeD1Ev@PLT
movq 8+_ZTTSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 432(%rsp)
movq -24(%rax), %rax
movq 16+_ZTTSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %rcx
movq %rcx, 432(%rsp,%rax)
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 680(%rsp)
leaq 680(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movl $1, %eax
.L29:
movq 952(%rsp), %rdx
subq %fs:40, %rdx
jne .L120
addq $968, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L84:
.cfi_restore_state
endbr64
movq %rax, %rbx
movq %rdx, %rbp
leaq 16(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
jmp .L49
.L79:
.LEHB11:
call _Unwind_Resume@PLT
.LEHE11:
.L78:
call __cxa_begin_catch@PLT
movq %rax, %rsi
leaq _ZSt4cout(%rip), %rdi
.LEHB12:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE12:
call __cxa_end_catch@PLT
movl $0, %eax
jmp .L29
.L85:
endbr64
movq %rax, %rbx
call __cxa_end_catch@PLT
movq 952(%rsp), %rax
subq %fs:40, %rax
je .L81
call __stack_chk_fail@PLT
.L81:
movq %rbx, %rdi
.LEHB13:
call _Unwind_Resume@PLT
.LEHE13:
.L120:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4402:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.align 4
.LLSDA4402:
.byte 0xff
.byte 0x9b
.uleb128 .LLSDATT4402-.LLSDATTD4402
.LLSDATTD4402:
.byte 0x1
.uleb128 .LLSDACSE4402-.LLSDACSB4402
.LLSDACSB4402:
.uleb128 .LEHB0-.LFB4402
.uleb128 .LEHE0-.LEHB0
.uleb128 .L86-.LFB4402
.uleb128 0x3
.uleb128 .LEHB1-.LFB4402
.uleb128 .LEHE1-.LEHB1
.uleb128 .L87-.LFB4402
.uleb128 0x3
.uleb128 .LEHB2-.LFB4402
.uleb128 .LEHE2-.LEHB2
.uleb128 .L88-.LFB4402
.uleb128 0x3
.uleb128 .LEHB3-.LFB4402
.uleb128 .LEHE3-.LEHB3
.uleb128 .L89-.LFB4402
.uleb128 0x3
.uleb128 .LEHB4-.LFB4402
.uleb128 .LEHE4-.LEHB4
.uleb128 .L90-.LFB4402
.uleb128 0x3
.uleb128 .LEHB5-.LFB4402
.uleb128 .LEHE5-.LEHB5
.uleb128 .L83-.LFB4402
.uleb128 0x3
.uleb128 .LEHB6-.LFB4402
.uleb128 .LEHE6-.LEHB6
.uleb128 .L91-.LFB4402
.uleb128 0x3
.uleb128 .LEHB7-.LFB4402
.uleb128 .LEHE7-.LEHB7
.uleb128 .L84-.LFB4402
.uleb128 0x3
.uleb128 .LEHB8-.LFB4402
.uleb128 .LEHE8-.LEHB8
.uleb128 .L83-.LFB4402
.uleb128 0x3
.uleb128 .LEHB9-.LFB4402
.uleb128 .LEHE9-.LEHB9
.uleb128 .L92-.LFB4402
.uleb128 0x5
.uleb128 .LEHB10-.LFB4402
.uleb128 .LEHE10-.LEHB10
.uleb128 .L83-.LFB4402
.uleb128 0x3
.uleb128 .LEHB11-.LFB4402
.uleb128 .LEHE11-.LEHB11
.uleb128 0
.uleb128 0
.uleb128 .LEHB12-.LFB4402
.uleb128 .LEHE12-.LEHB12
.uleb128 .L85-.LFB4402
.uleb128 0
.uleb128 .LEHB13-.LFB4402
.uleb128 .LEHE13-.LEHB13
.uleb128 0
.uleb128 0
.LLSDACSE4402:
.byte 0x1
.byte 0
.byte 0
.byte 0x7d
.byte 0x2
.byte 0
.align 4
.long 0
.long DW.ref._ZTIPc-.
.LLSDATT4402:
.text
.size _Z4savePfj, .-_Z4savePfj
.section .rodata.str1.1
.LC17:
.string "Time Step: %.3e[s]\n"
.LC21:
.string "step: %d\n"
.text
.globl main
.type main, @function
main:
.LFB4404:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $96, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $11236, %edi
call malloc@PLT
movq %rax, %rbp
movl $0x350637bd, (%rsp)
movl $0x3ad8984f, 4(%rsp)
movl $0x4ac92974, 8(%rsp)
movsd .LC16(%rip), %xmm0
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0x375a1a93, 12(%rsp)
movl $0x3f000000, 16(%rsp)
movl $0x329d4891, 20(%rsp)
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL10field_size(%rip), %rsi
leaq _ZL12d_field_size(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movq %rsp, %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL4d_dx(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 4(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL3d_a(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 8(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL3d_w(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 16(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL6d_beta(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 20(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL5d_tau(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 12(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL4d_r0(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 24(%rsp), %rdi
movl $11236, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $11236, %esi
call cudaMalloc@PLT
movl $32, 40(%rsp)
movl $32, 44(%rsp)
movl $1, 48(%rsp)
movl $2, 52(%rsp)
movl $2, 56(%rsp)
movl $1, 60(%rsp)
movl $1, %ecx
movl $11236, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl 48(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movq 52(%rsp), %rdi
movl 60(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L130
.L122:
movl $51, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L131
.L123:
movl $0, %ebx
leaq .LC21(%rip), %r12
jmp .L126
.L130:
movq 24(%rsp), %rdi
call _Z30__device_stub__Z10init_fieldPfPf
jmp .L122
.L131:
movq 24(%rsp), %rdi
call _Z25__device_stub__Z6set_bcPfPf
jmp .L123
.L133:
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z30__device_stub__Z9calc_stepPfS_PfS_
jmp .L124
.L125:
addl $1, %ebx
cmpl $100, %ebx
je .L132
.L126:
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $11236, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl %ebx, %esi
movq %rbp, %rdi
call _Z4savePfj
movl 48(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movq 52(%rsp), %rdi
movl 60(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L133
.L124:
movl $3, %ecx
movl $11236, %edx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $51, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L125
movq 24(%rsp), %rdi
call _Z25__device_stub__Z6set_bcPfPf
jmp .L125
.L132:
movq %rbp, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L134
movl $0, %eax
addq $96, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L134:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4404:
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL4d_r0
.comm _ZL4d_r0,4,4
.local _ZL5d_tau
.comm _ZL5d_tau,4,4
.local _ZL6d_beta
.comm _ZL6d_beta,4,4
.local _ZL3d_w
.comm _ZL3d_w,4,4
.local _ZL3d_a
.comm _ZL3d_a,4,4
.local _ZL4d_dx
.comm _ZL4d_dx,4,4
.local _ZL12d_field_size
.comm _ZL12d_field_size,4,4
.section .rodata
.align 4
.type _ZL10field_size, @object
.size _ZL10field_size, 4
_ZL10field_size:
.long 53
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC16:
.long 0
.long 1072955392
.hidden DW.ref._ZTIPc
.weak DW.ref._ZTIPc
.section .data.rel.local.DW.ref._ZTIPc,"awG",@progbits,DW.ref._ZTIPc,comdat
.align 8
.type DW.ref._ZTIPc, @object
.size DW.ref._ZTIPc, 8
DW.ref._ZTIPc:
.quad _ZTIPc
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <ostream>
#include <sstream>
#include <iomanip>
#include <stdio.h>
#include <vector>
#include <fstream>
const unsigned int field_size = 53;
const unsigned int step = 100;
__device__ unsigned int d_field_size;
__device__ float d_dx;
__device__ float d_a;
__device__ float d_w;
__device__ float d_beta;
__device__ float d_tau;
__device__ float d_r0;
__global__ void calc_step(float *d_phase, float *d_phase_tmp) {
int x_i = blockIdx.x * blockDim.x + threadIdx.x;
int y_i = blockIdx.y * blockDim.y + threadIdx.y;
if (x_i <= 0 || x_i >= d_field_size - 1 || y_i <= 0 || y_i >= d_field_size - 1) return;
int i = y_i * d_field_size + x_i;
float ddx = d_dx * d_dx;
float rpx = (d_phase[i + 1] - 2.* d_phase[i] + d_phase[i - 1]) / ddx;
float rpy = (d_phase[i + d_field_size] - 2. * d_phase[i] + d_phase[i - d_field_size]) / ddx;
float dpi1 = d_a * d_a * (rpx + rpy);
float dpi2 = 4. * d_w * d_phase[i] * (1 - d_phase[i]) * (d_phase[i] - .5 + d_beta);
float dpi = dpi1 + dpi2;
d_phase_tmp[i] = d_phase[i] + d_tau * dpi;
}
__global__ void set_bc(float *field) {
int x_i = blockIdx.x * blockDim.x + threadIdx.x;
if ( x_i >= field_size - 2) return;
int i = x_i + 1;
// top
field[i] = field[i+field_size];
// bottom
field[field_size * (field_size - 1) + i] = field[field_size * (field_size - 2) + i];
// left
field[field_size * i] = field[field_size * i + 1];
// right
field[field_size * (i + 1) - 1] = field[field_size * (i + 1) - 2];
return;
}
__global__ void init_field(float *field) {
int x_i = blockIdx.x * blockDim.x + threadIdx.x;
int y_i = blockIdx.y * blockDim.y + threadIdx.y;
if (x_i <= 0 || x_i >= d_field_size - 1 || y_i <= 0 || y_i >= d_field_size - 1) {
return;
}
int i = y_i * d_field_size + x_i;
float y = (y_i - 1) * d_dx;
float x = (x_i - 1) * d_dx;
float r = sqrt(x*x + y*y) - d_r0;
field[i] = .5 * (1. - tanh(sqrt(2. * d_w) / (2. * d_a) * r));
printf("%f\n", field[i]);
return;
}
bool save(float *phase, unsigned int n) {
try {
std::ofstream file;
std::ostringstream filename;
filename << "datas/step_" << std::setfill('0') << std::right << std::setw(std::log10(step)+1) << n << ".dat";
file.open(filename.str(), std::ios_base::app);
file << "#x #y #phase" << std::endl;
// remove boundaries
for (unsigned int y_i = 1; y_i < field_size - 1; y_i++) {
for (unsigned int x_i = 1; x_i < field_size - 1; x_i++) {
file << y_i << ' ' << x_i << ' ' << phase[y_i * field_size + x_i] << std::endl;
}
file << std::endl;
}
file.close();
} catch(char *str) {
std::cout << str << std::endl;
return false;
}
return true;
}
int main() {
unsigned int N = field_size * field_size;
float *phase; // phase field for host
float *d_phase, *d_phase_tmp; // phase field for device
phase = (float *)malloc(N * sizeof(float));
const float dx = 5e-7;
// 界面エネルギー
float gamma = 1.;
// 界面幅
float delta = 4. * dx;
// 界面モビリティ
float M = 4e-14;
// 界面領域
float lambda = .1;
// 勾配計数
float b = 2. * std::atanh(1.-2.*lambda);
float a = std::sqrt(3. * delta * gamma / b);
// エネルギー障壁
float w = 6. * gamma * b / delta;
// フェーズフィールドモビリティ
float M_phi = M * std::sqrt(2. * w) / (6. * a);
// 時間ステップ
float dt = dx * dx / (5. * M_phi * a * a);
printf("Time Step: %.3e[s]\n", dt);
// 固相初期半径
float r0 = .5 * (field_size - 1) * dx;
float beta = .5;
float tau = M_phi * dt;
cudaMemcpyToSymbol(d_field_size, &field_size, sizeof(unsigned int));
cudaMemcpyToSymbol(d_dx, &dx, sizeof(float));
cudaMemcpyToSymbol(d_a, &a, sizeof(float));
cudaMemcpyToSymbol(d_w, &w, sizeof(float));
cudaMemcpyToSymbol(d_beta, &beta, sizeof(float));
cudaMemcpyToSymbol(d_tau, &tau, sizeof(float));
cudaMemcpyToSymbol(d_r0, &r0, sizeof(float));
// allocate memory to GPU
cudaMalloc((void**)&d_phase, N * sizeof(float));
cudaMalloc((void**)&d_phase_tmp, N * sizeof(float));
int threadsPerBlock = 32;
int blocksInGrid = (field_size + threadsPerBlock -1)/threadsPerBlock;
dim3 blocks(threadsPerBlock, threadsPerBlock);
dim3 grid(blocksInGrid, blocksInGrid);
cudaMemcpy(d_phase, phase, N * sizeof(float), cudaMemcpyHostToDevice);
init_field<<<grid, blocks>>>(d_phase);
set_bc<<<1, field_size - 2>>>(d_phase);
// メインループ
for (unsigned int n = 0; n < step; n++) {
printf("step: %d\n", n);
cudaMemcpy(phase, d_phase, N * sizeof(float), cudaMemcpyDeviceToHost);
save(phase, n);
calc_step<<<grid, blocks>>>(d_phase, d_phase_tmp);
// Swap
cudaMemcpy(d_phase, d_phase_tmp, N * sizeof(float), cudaMemcpyDeviceToDevice);
set_bc<<<1, field_size - 2>>>(d_phase);
}
free(phase);
cudaFree(d_phase);
cudaFree(d_phase_tmp);
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <ostream>
#include <sstream>
#include <iomanip>
#include <stdio.h>
#include <vector>
#include <fstream>
const unsigned int field_size = 53;
const unsigned int step = 100;
__device__ unsigned int d_field_size;
__device__ float d_dx;
__device__ float d_a;
__device__ float d_w;
__device__ float d_beta;
__device__ float d_tau;
__device__ float d_r0;
__global__ void calc_step(float *d_phase, float *d_phase_tmp) {
int x_i = blockIdx.x * blockDim.x + threadIdx.x;
int y_i = blockIdx.y * blockDim.y + threadIdx.y;
if (x_i <= 0 || x_i >= d_field_size - 1 || y_i <= 0 || y_i >= d_field_size - 1) return;
int i = y_i * d_field_size + x_i;
float ddx = d_dx * d_dx;
float rpx = (d_phase[i + 1] - 2.* d_phase[i] + d_phase[i - 1]) / ddx;
float rpy = (d_phase[i + d_field_size] - 2. * d_phase[i] + d_phase[i - d_field_size]) / ddx;
float dpi1 = d_a * d_a * (rpx + rpy);
float dpi2 = 4. * d_w * d_phase[i] * (1 - d_phase[i]) * (d_phase[i] - .5 + d_beta);
float dpi = dpi1 + dpi2;
d_phase_tmp[i] = d_phase[i] + d_tau * dpi;
}
__global__ void set_bc(float *field) {
int x_i = blockIdx.x * blockDim.x + threadIdx.x;
if ( x_i >= field_size - 2) return;
int i = x_i + 1;
// top
field[i] = field[i+field_size];
// bottom
field[field_size * (field_size - 1) + i] = field[field_size * (field_size - 2) + i];
// left
field[field_size * i] = field[field_size * i + 1];
// right
field[field_size * (i + 1) - 1] = field[field_size * (i + 1) - 2];
return;
}
__global__ void init_field(float *field) {
int x_i = blockIdx.x * blockDim.x + threadIdx.x;
int y_i = blockIdx.y * blockDim.y + threadIdx.y;
if (x_i <= 0 || x_i >= d_field_size - 1 || y_i <= 0 || y_i >= d_field_size - 1) {
return;
}
int i = y_i * d_field_size + x_i;
float y = (y_i - 1) * d_dx;
float x = (x_i - 1) * d_dx;
float r = sqrt(x*x + y*y) - d_r0;
field[i] = .5 * (1. - tanh(sqrt(2. * d_w) / (2. * d_a) * r));
printf("%f\n", field[i]);
return;
}
bool save(float *phase, unsigned int n) {
try {
std::ofstream file;
std::ostringstream filename;
filename << "datas/step_" << std::setfill('0') << std::right << std::setw(std::log10(step)+1) << n << ".dat";
file.open(filename.str(), std::ios_base::app);
file << "#x #y #phase" << std::endl;
// remove boundaries
for (unsigned int y_i = 1; y_i < field_size - 1; y_i++) {
for (unsigned int x_i = 1; x_i < field_size - 1; x_i++) {
file << y_i << ' ' << x_i << ' ' << phase[y_i * field_size + x_i] << std::endl;
}
file << std::endl;
}
file.close();
} catch(char *str) {
std::cout << str << std::endl;
return false;
}
return true;
}
int main() {
unsigned int N = field_size * field_size;
float *phase; // phase field for host
float *d_phase, *d_phase_tmp; // phase field for device
phase = (float *)malloc(N * sizeof(float));
const float dx = 5e-7;
// 界面エネルギー
float gamma = 1.;
// 界面幅
float delta = 4. * dx;
// 界面モビリティ
float M = 4e-14;
// 界面領域
float lambda = .1;
// 勾配計数
float b = 2. * std::atanh(1.-2.*lambda);
float a = std::sqrt(3. * delta * gamma / b);
// エネルギー障壁
float w = 6. * gamma * b / delta;
// フェーズフィールドモビリティ
float M_phi = M * std::sqrt(2. * w) / (6. * a);
// 時間ステップ
float dt = dx * dx / (5. * M_phi * a * a);
printf("Time Step: %.3e[s]\n", dt);
// 固相初期半径
float r0 = .5 * (field_size - 1) * dx;
float beta = .5;
float tau = M_phi * dt;
hipMemcpyToSymbol(HIP_SYMBOL(d_field_size), &field_size, sizeof(unsigned int));
hipMemcpyToSymbol(HIP_SYMBOL(d_dx), &dx, sizeof(float));
hipMemcpyToSymbol(HIP_SYMBOL(d_a), &a, sizeof(float));
hipMemcpyToSymbol(HIP_SYMBOL(d_w), &w, sizeof(float));
hipMemcpyToSymbol(HIP_SYMBOL(d_beta), &beta, sizeof(float));
hipMemcpyToSymbol(HIP_SYMBOL(d_tau), &tau, sizeof(float));
hipMemcpyToSymbol(HIP_SYMBOL(d_r0), &r0, sizeof(float));
// allocate memory to GPU
hipMalloc((void**)&d_phase, N * sizeof(float));
hipMalloc((void**)&d_phase_tmp, N * sizeof(float));
int threadsPerBlock = 32;
int blocksInGrid = (field_size + threadsPerBlock -1)/threadsPerBlock;
dim3 blocks(threadsPerBlock, threadsPerBlock);
dim3 grid(blocksInGrid, blocksInGrid);
hipMemcpy(d_phase, phase, N * sizeof(float), hipMemcpyHostToDevice);
init_field<<<grid, blocks>>>(d_phase);
set_bc<<<1, field_size - 2>>>(d_phase);
// メインループ
for (unsigned int n = 0; n < step; n++) {
printf("step: %d\n", n);
hipMemcpy(phase, d_phase, N * sizeof(float), hipMemcpyDeviceToHost);
save(phase, n);
calc_step<<<grid, blocks>>>(d_phase, d_phase_tmp);
// Swap
hipMemcpy(d_phase, d_phase_tmp, N * sizeof(float), hipMemcpyDeviceToDevice);
set_bc<<<1, field_size - 2>>>(d_phase);
}
free(phase);
hipFree(d_phase);
hipFree(d_phase_tmp);
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
#define BLOCK_WIDTH 8
__global__ static void mandelKernel(float upperX, float upperY, float lowerX, float lowerY, int* img, int resX, int resY, int maxIterations) {
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float stepX = (upperX - lowerX) / resX;
float stepY = (upperY - lowerY) / resY;
float x = lowerX + col * stepX;
float y = lowerY + row * stepY;
float z_re = x, z_im = y;
if (maxIterations == 100000) {
#pragma unroll
for (int val = 0; val < maxIterations; ++val) {
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
float new_re = z_re * z_re - z_im * z_im;
float new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
}
img[row * resX + col] = maxIterations;
}
else {
for (int val = 0; val < maxIterations; ++val) {
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
float new_re = z_re * z_re - z_im * z_im;
float new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
}
img[row * resX + col] = maxIterations;
}
}
// Host front-end function that allocates the memory and launches the GPU kernel
void hostFE (float upperX, float upperY, float lowerX, float lowerY, int* img, int resX, int resY, int maxIterations) {
int *temp_img;
static int x_blocks = resX / BLOCK_WIDTH;
static int y_blocks = resY / BLOCK_WIDTH;
dim3 block_size(BLOCK_WIDTH, BLOCK_WIDTH);
dim3 num_block(x_blocks, y_blocks);
cudaMalloc(&temp_img, resX * resY * sizeof(int));
mandelKernel<<<num_block, block_size>>>(upperX, upperY, lowerX, lowerY, temp_img, resX, resY, maxIterations);
cudaMemcpy(img, temp_img, resX * resY * sizeof(int), cudaMemcpyDeviceToHost);
cudaFree(temp_img);
} | .file "tmpxft_000d207b_00000000-6_kernel4.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL39__device_stub__Z12mandelKernelffffPiiiiffffPiiii, @function
_ZL39__device_stub__Z12mandelKernelffffPiiiiffffPiiii:
.LFB2082:
.cfi_startproc
subq $200, %rsp
.cfi_def_cfa_offset 208
movss %xmm0, 44(%rsp)
movss %xmm1, 40(%rsp)
movss %xmm2, 36(%rsp)
movss %xmm3, 32(%rsp)
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _ZL12mandelKernelffffPiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _ZL39__device_stub__Z12mandelKernelffffPiiiiffffPiiii, .-_ZL39__device_stub__Z12mandelKernelffffPiiiiffffPiiii
.type _ZL12mandelKernelffffPiiii, @function
_ZL12mandelKernelffffPiiii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL39__device_stub__Z12mandelKernelffffPiiiiffffPiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL12mandelKernelffffPiiii, .-_ZL12mandelKernelffffPiiii
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6hostFEffffPiiii
.type _Z6hostFEffffPiiii, @function
_Z6hostFEffffPiiii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movss %xmm0, (%rsp)
movss %xmm1, 4(%rsp)
movss %xmm2, 8(%rsp)
movss %xmm3, 12(%rsp)
movq %rdi, %r13
movl %esi, %ebp
movl %edx, %r12d
movl %ecx, %r14d
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movzbl _ZGVZ6hostFEffffPiiiiE8x_blocks(%rip), %eax
testb %al, %al
je .L17
.L12:
movzbl _ZGVZ6hostFEffffPiiiiE8y_blocks(%rip), %eax
testb %al, %al
je .L18
.L13:
movl $8, 32(%rsp)
movl $8, 36(%rsp)
movl $1, 40(%rsp)
movl _ZZ6hostFEffffPiiiiE8x_blocks(%rip), %eax
movl %eax, 44(%rsp)
movl _ZZ6hostFEffffPiiiiE8y_blocks(%rip), %eax
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl %ebp, %ebx
imull %r12d, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L14:
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
leaq _ZGVZ6hostFEffffPiiiiE8x_blocks(%rip), %rdi
call __cxa_guard_acquire@PLT
testl %eax, %eax
je .L12
leal 7(%rbp), %eax
testl %ebp, %ebp
cmovns %ebp, %eax
sarl $3, %eax
movl %eax, _ZZ6hostFEffffPiiiiE8x_blocks(%rip)
leaq _ZGVZ6hostFEffffPiiiiE8x_blocks(%rip), %rdi
call __cxa_guard_release@PLT
jmp .L12
.L18:
leaq _ZGVZ6hostFEffffPiiiiE8y_blocks(%rip), %rdi
call __cxa_guard_acquire@PLT
testl %eax, %eax
je .L13
leal 7(%r12), %eax
testl %r12d, %r12d
cmovns %r12d, %eax
sarl $3, %eax
movl %eax, _ZZ6hostFEffffPiiiiE8y_blocks(%rip)
leaq _ZGVZ6hostFEffffPiiiiE8y_blocks(%rip), %rdi
call __cxa_guard_release@PLT
jmp .L13
.L19:
movl %r14d, %ecx
movl %r12d, %edx
movl %ebp, %esi
movq 24(%rsp), %rdi
movss 12(%rsp), %xmm3
movss 8(%rsp), %xmm2
movss 4(%rsp), %xmm1
movss (%rsp), %xmm0
call _ZL39__device_stub__Z12mandelKernelffffPiiiiffffPiiii
jmp .L14
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z6hostFEffffPiiii, .-_Z6hostFEffffPiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12mandelKernelffffPiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL12mandelKernelffffPiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZGVZ6hostFEffffPiiiiE8y_blocks
.comm _ZGVZ6hostFEffffPiiiiE8y_blocks,8,8
.local _ZZ6hostFEffffPiiiiE8y_blocks
.comm _ZZ6hostFEffffPiiiiE8y_blocks,4,4
.local _ZGVZ6hostFEffffPiiiiE8x_blocks
.comm _ZGVZ6hostFEffffPiiiiE8x_blocks,8,8
.local _ZZ6hostFEffffPiiiiE8x_blocks
.comm _ZZ6hostFEffffPiiiiE8x_blocks,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
#define BLOCK_WIDTH 8
__global__ static void mandelKernel(float upperX, float upperY, float lowerX, float lowerY, int* img, int resX, int resY, int maxIterations) {
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float stepX = (upperX - lowerX) / resX;
float stepY = (upperY - lowerY) / resY;
float x = lowerX + col * stepX;
float y = lowerY + row * stepY;
float z_re = x, z_im = y;
if (maxIterations == 100000) {
#pragma unroll
for (int val = 0; val < maxIterations; ++val) {
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
float new_re = z_re * z_re - z_im * z_im;
float new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
}
img[row * resX + col] = maxIterations;
}
else {
for (int val = 0; val < maxIterations; ++val) {
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
float new_re = z_re * z_re - z_im * z_im;
float new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
}
img[row * resX + col] = maxIterations;
}
}
// Host front-end function that allocates the memory and launches the GPU kernel
void hostFE (float upperX, float upperY, float lowerX, float lowerY, int* img, int resX, int resY, int maxIterations) {
int *temp_img;
static int x_blocks = resX / BLOCK_WIDTH;
static int y_blocks = resY / BLOCK_WIDTH;
dim3 block_size(BLOCK_WIDTH, BLOCK_WIDTH);
dim3 num_block(x_blocks, y_blocks);
cudaMalloc(&temp_img, resX * resY * sizeof(int));
mandelKernel<<<num_block, block_size>>>(upperX, upperY, lowerX, lowerY, temp_img, resX, resY, maxIterations);
cudaMemcpy(img, temp_img, resX * resY * sizeof(int), cudaMemcpyDeviceToHost);
cudaFree(temp_img);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define BLOCK_WIDTH 8
__global__ static void mandelKernel(float upperX, float upperY, float lowerX, float lowerY, int* img, int resX, int resY, int maxIterations) {
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float stepX = (upperX - lowerX) / resX;
float stepY = (upperY - lowerY) / resY;
float x = lowerX + col * stepX;
float y = lowerY + row * stepY;
float z_re = x, z_im = y;
if (maxIterations == 100000) {
#pragma unroll
for (int val = 0; val < maxIterations; ++val) {
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
float new_re = z_re * z_re - z_im * z_im;
float new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
}
img[row * resX + col] = maxIterations;
}
else {
for (int val = 0; val < maxIterations; ++val) {
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
float new_re = z_re * z_re - z_im * z_im;
float new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
}
img[row * resX + col] = maxIterations;
}
}
// Host front-end function that allocates the memory and launches the GPU kernel
void hostFE (float upperX, float upperY, float lowerX, float lowerY, int* img, int resX, int resY, int maxIterations) {
int *temp_img;
static int x_blocks = resX / BLOCK_WIDTH;
static int y_blocks = resY / BLOCK_WIDTH;
dim3 block_size(BLOCK_WIDTH, BLOCK_WIDTH);
dim3 num_block(x_blocks, y_blocks);
hipMalloc(&temp_img, resX * resY * sizeof(int));
mandelKernel<<<num_block, block_size>>>(upperX, upperY, lowerX, lowerY, temp_img, resX, resY, maxIterations);
hipMemcpy(img, temp_img, resX * resY * sizeof(int), hipMemcpyDeviceToHost);
hipFree(temp_img);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define BLOCK_WIDTH 8
__global__ static void mandelKernel(float upperX, float upperY, float lowerX, float lowerY, int* img, int resX, int resY, int maxIterations) {
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float stepX = (upperX - lowerX) / resX;
float stepY = (upperY - lowerY) / resY;
float x = lowerX + col * stepX;
float y = lowerY + row * stepY;
float z_re = x, z_im = y;
if (maxIterations == 100000) {
#pragma unroll
for (int val = 0; val < maxIterations; ++val) {
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
float new_re = z_re * z_re - z_im * z_im;
float new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
}
img[row * resX + col] = maxIterations;
}
else {
for (int val = 0; val < maxIterations; ++val) {
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
float new_re = z_re * z_re - z_im * z_im;
float new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
}
img[row * resX + col] = maxIterations;
}
}
// Host front-end function that allocates the memory and launches the GPU kernel
void hostFE (float upperX, float upperY, float lowerX, float lowerY, int* img, int resX, int resY, int maxIterations) {
int *temp_img;
static int x_blocks = resX / BLOCK_WIDTH;
static int y_blocks = resY / BLOCK_WIDTH;
dim3 block_size(BLOCK_WIDTH, BLOCK_WIDTH);
dim3 num_block(x_blocks, y_blocks);
hipMalloc(&temp_img, resX * resY * sizeof(int));
mandelKernel<<<num_block, block_size>>>(upperX, upperY, lowerX, lowerY, temp_img, resX, resY, maxIterations);
hipMemcpy(img, temp_img, resX * resY * sizeof(int), hipMemcpyDeviceToHost);
hipFree(temp_img);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL12mandelKernelffffPiiii,"axG",@progbits,_ZL12mandelKernelffffPiiii,comdat
.globl _ZL12mandelKernelffffPiiii
.p2align 8
.type _ZL12mandelKernelffffPiiii,@function
_ZL12mandelKernelffffPiiii:
s_clause 0x4
s_load_b64 s[10:11], s[0:1], 0x0
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b32 s8, s[0:1], 0x20
s_load_b32 s1, s[0:1], 0x34
s_waitcnt lgkmcnt(0)
v_sub_f32_e64 v4, s10, s4
v_cvt_f32_i32_e32 v5, s2
v_sub_f32_e64 v6, s11, s5
v_cvt_f32_i32_e32 v7, s3
s_lshr_b32 s3, s1, 16
s_and_b32 s1, s1, 0xffff
v_div_scale_f32 v8, null, v5, v5, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_div_scale_f32 v9, null, v7, v7, v6
v_div_scale_f32 v12, vcc_lo, v4, v5, v4
v_rcp_f32_e32 v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_rcp_f32_e32 v11, v9
v_div_scale_f32 v13, s0, v6, v7, v6
s_cmp_eq_u32 s8, 0x186a0
s_waitcnt_depctr 0xfff
v_fma_f32 v1, -v8, v10, 1.0
v_fma_f32 v2, -v9, v11, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_fmac_f32 v10, v1, v10 :: v_dual_fmac_f32 v11, v2, v11
v_bfe_u32 v2, v0, 10, 10
v_dual_mul_f32 v14, v12, v10 :: v_dual_mul_f32 v15, v13, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v1, -v8, v14, v12
v_fma_f32 v16, -v9, v15, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_fmac_f32 v14, v1, v10 :: v_dual_and_b32 v3, 0x3ff, v0
v_fmac_f32_e32 v15, v16, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s1, v[3:4]
v_fma_f32 v8, -v8, v14, v12
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v2, -v9, v15, v13
v_div_fmas_f32 v3, v8, v10, v14
s_mov_b32 vcc_lo, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f32_i32_e32 v8, v1
v_div_fmas_f32 v2, v2, v11, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_div_fixup_f32 v3, v3, v5, v4
v_cvt_f32_i32_e32 v5, v0
v_div_fixup_f32 v2, v2, v7, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v4, v3, v8, s4
v_fma_f32 v5, v2, v5, s5
s_cbranch_scc1 .LBB0_6
v_mov_b32_e32 v8, s8
s_cmp_lt_i32 s8, 1
s_cbranch_scc1 .LBB0_8
v_dual_mov_b32 v3, v4 :: v_dual_mov_b32 v2, v5
s_mov_b32 s0, 0
s_mov_b32 s1, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s4, exec_lo, s3
s_or_b32 s0, s4, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_7
.LBB0_4:
v_mul_f32_e32 v6, v3, v3
v_mov_b32_e32 v8, s1
s_or_b32 s3, s3, exec_lo
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, v2, v2, v6
v_cmpx_nlt_f32_e32 4.0, v7
s_cbranch_execz .LBB0_3
v_dual_mul_f32 v7, v2, v2 :: v_dual_mov_b32 v8, s8
v_add_f32_e32 v3, v3, v3
s_add_i32 s1, s1, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s8, s1
v_sub_f32_e32 v6, v6, v7
s_cselect_b32 s5, -1, 0
v_fma_f32 v2, v2, v3, v5
s_and_not1_b32 s3, s3, exec_lo
s_and_b32 s5, s5, exec_lo
v_add_f32_e32 v3, v4, v6
s_or_b32 s3, s3, s5
s_branch .LBB0_3
.LBB0_6:
s_mov_b32 s0, 0
s_branch .LBB0_9
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s0
.LBB0_8:
s_mov_b32 s0, -1
s_cbranch_execnz .LBB0_96
.LBB0_9:
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v6, v5
v_mov_b32_e32 v7, v4
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
s_branch .LBB0_12
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s12
v_mov_b32_e32 v9, s11
s_and_not1_b32 s4, s4, exec_lo
s_and_b32 s8, s8, exec_lo
s_and_not1_b32 s3, s3, exec_lo
s_and_b32 s9, s10, exec_lo
s_or_b32 s4, s4, s8
s_or_b32 s3, s3, s9
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_and_b32 s5, exec_lo, s3
v_dual_mov_b32 v8, v9 :: v_dual_mov_b32 v9, v10
s_or_b32 s1, s5, s1
s_and_not1_b32 s0, s0, exec_lo
s_and_b32 s5, s4, exec_lo
s_or_b32 s0, s0, s5
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB0_95
.LBB0_12:
v_mul_f32_e32 v8, v7, v7
s_or_b32 s4, s4, exec_lo
s_or_b32 s3, s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v10, v6, v6, v8
v_cmp_nlt_f32_e32 vcc_lo, 4.0, v10
s_and_saveexec_b32 s5, vcc_lo
s_cbranch_execz .LBB0_11
v_dual_mul_f32 v10, v6, v6 :: v_dual_add_f32 v7, v7, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v8, v8, v10
v_fma_f32 v6, v6, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v7, v4, v8 :: v_dual_mul_f32 v10, v6, v6
v_fma_f32 v8, v7, v7, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_nlt_f32_e32 vcc_lo, 4.0, v8
s_and_saveexec_b32 s8, vcc_lo
s_xor_b32 s8, exec_lo, s8
s_cbranch_execz .LBB0_91
v_mul_f32_e32 v8, v7, v7
v_add_f32_e32 v7, v7, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v8, v8, v10
v_fma_f32 v6, v6, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v7, v4, v8 :: v_dual_mul_f32 v10, v6, v6
v_fma_f32 v8, v7, v7, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_nlt_f32_e32 vcc_lo, 4.0, v8
s_and_saveexec_b32 s9, vcc_lo
s_xor_b32 s9, exec_lo, s9
s_cbranch_execz .LBB0_88
v_mul_f32_e32 v8, v7, v7
v_add_f32_e32 v7, v7, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v8, v8, v10
v_fma_f32 v6, v6, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v7, v4, v8 :: v_dual_mul_f32 v10, v6, v6
v_fma_f32 v8, v7, v7, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_nlt_f32_e32 vcc_lo, 4.0, v8
s_and_saveexec_b32 s10, vcc_lo
s_xor_b32 s10, exec_lo, s10
s_cbranch_execz .LBB0_85
v_mul_f32_e32 v8, v7, v7
v_add_f32_e32 v7, v7, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v8, v8, v10
v_fma_f32 v6, v6, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v7, v4, v8 :: v_dual_mul_f32 v10, v6, v6
v_fma_f32 v8, v7, v7, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_nlt_f32_e32 vcc_lo, 4.0, v8
s_and_saveexec_b32 s11, vcc_lo
s_xor_b32 s11, exec_lo, s11
s_cbranch_execz .LBB0_82
v_mul_f32_e32 v8, v7, v7
v_add_f32_e32 v7, v7, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v8, v8, v10
v_fma_f32 v6, v6, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v7, v4, v8 :: v_dual_mul_f32 v10, v6, v6
v_fma_f32 v8, v7, v7, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_nlt_f32_e32 vcc_lo, 4.0, v8
s_and_saveexec_b32 s12, vcc_lo
s_xor_b32 s12, exec_lo, s12
s_cbranch_execz .LBB0_79
v_mul_f32_e32 v8, v7, v7
v_add_f32_e32 v7, v7, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v8, v8, v10
v_fma_f32 v6, v6, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v7, v4, v8 :: v_dual_mul_f32 v10, v6, v6
v_fma_f32 v8, v7, v7, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_nlt_f32_e32 vcc_lo, 4.0, v8
s_and_saveexec_b32 s13, vcc_lo
s_xor_b32 s13, exec_lo, s13
s_cbranch_execz .LBB0_76
v_mul_f32_e32 v8, v7, v7
v_add_f32_e32 v7, v7, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v8, v8, v10
v_fma_f32 v6, v6, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v7, v4, v8 :: v_dual_mul_f32 v10, v6, v6
v_fma_f32 v8, v7, v7, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_nlt_f32_e32 vcc_lo, 4.0, v8
s_and_saveexec_b32 s14, vcc_lo
s_xor_b32 s14, exec_lo, s14
s_cbranch_execz .LBB0_73
v_mul_f32_e32 v8, v7, v7
v_add_f32_e32 v7, v7, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v8, v8, v10
v_fma_f32 v6, v6, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v7, v4, v8 :: v_dual_mul_f32 v10, v6, v6
v_fma_f32 v8, v7, v7, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_nlt_f32_e32 vcc_lo, 4.0, v8
s_and_saveexec_b32 s15, vcc_lo
s_xor_b32 s15, exec_lo, s15
s_cbranch_execz .LBB0_70
v_mul_f32_e32 v8, v7, v7
v_add_f32_e32 v7, v7, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v8, v8, v10
v_fma_f32 v6, v6, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v7, v4, v8 :: v_dual_mul_f32 v10, v6, v6
v_fma_f32 v8, v7, v7, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_nlt_f32_e32 vcc_lo, 4.0, v8
s_and_saveexec_b32 s16, vcc_lo
s_xor_b32 s16, exec_lo, s16
s_cbranch_execz .LBB0_67
v_mul_f32_e32 v8, v7, v7
v_add_f32_e32 v7, v7, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v8, v8, v10
v_fma_f32 v6, v6, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v7, v4, v8 :: v_dual_mul_f32 v10, v6, v6
v_fma_f32 v8, v7, v7, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_nlt_f32_e32 vcc_lo, 4.0, v8
s_and_saveexec_b32 s17, vcc_lo
s_xor_b32 s17, exec_lo, s17
s_cbranch_execz .LBB0_64
v_mul_f32_e32 v8, v7, v7
v_add_f32_e32 v7, v7, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v8, v8, v10
v_fma_f32 v6, v6, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v7, v4, v8 :: v_dual_mul_f32 v10, v6, v6
v_fma_f32 v8, v7, v7, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_nlt_f32_e32 vcc_lo, 4.0, v8
s_and_saveexec_b32 s18, vcc_lo
s_xor_b32 s18, exec_lo, s18
s_cbranch_execz .LBB0_61
v_mul_f32_e32 v8, v7, v7
v_add_f32_e32 v7, v7, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v8, v8, v10
v_fma_f32 v6, v6, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v7, v4, v8 :: v_dual_mul_f32 v10, v6, v6
v_fma_f32 v8, v7, v7, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_nlt_f32_e32 vcc_lo, 4.0, v8
s_and_saveexec_b32 s19, vcc_lo
s_xor_b32 s19, exec_lo, s19
s_cbranch_execz .LBB0_58
v_mul_f32_e32 v8, v7, v7
v_add_f32_e32 v7, v7, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v8, v8, v10
v_fma_f32 v6, v6, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v7, v4, v8 :: v_dual_mul_f32 v10, v6, v6
v_fma_f32 v8, v7, v7, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_nlt_f32_e32 vcc_lo, 4.0, v8
s_and_saveexec_b32 s20, vcc_lo
s_xor_b32 s20, exec_lo, s20
s_cbranch_execz .LBB0_55
v_mul_f32_e32 v8, v7, v7
v_add_f32_e32 v7, v7, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v8, v8, v10
v_fma_f32 v6, v6, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v7, v4, v8 :: v_dual_mul_f32 v10, v6, v6
v_fma_f32 v8, v7, v7, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_nlt_f32_e32 vcc_lo, 4.0, v8
s_and_saveexec_b32 s21, vcc_lo
s_xor_b32 s21, exec_lo, s21
s_cbranch_execz .LBB0_52
v_mul_f32_e32 v8, v7, v7
v_add_f32_e32 v7, v7, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v8, v8, v10
v_fma_f32 v6, v6, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v7, v4, v8 :: v_dual_mul_f32 v10, v6, v6
v_fma_f32 v8, v7, v7, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_nlt_f32_e32 vcc_lo, 4.0, v8
s_and_saveexec_b32 s22, vcc_lo
s_xor_b32 s22, exec_lo, s22
s_cbranch_execz .LBB0_49
v_mul_f32_e32 v8, v7, v7
v_add_f32_e32 v7, v7, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v8, v8, v10
v_fma_f32 v6, v6, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v7, v4, v8 :: v_dual_mul_f32 v10, v6, v6
v_fma_f32 v8, v7, v7, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_nlt_f32_e32 vcc_lo, 4.0, v8
s_and_saveexec_b32 s23, vcc_lo
s_xor_b32 s23, exec_lo, s23
s_cbranch_execz .LBB0_46
v_mul_f32_e32 v8, v7, v7
v_add_f32_e32 v7, v7, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v8, v8, v10
v_fma_f32 v6, v6, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v7, v4, v8 :: v_dual_mul_f32 v10, v6, v6
v_fma_f32 v8, v7, v7, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_nlt_f32_e32 vcc_lo, 4.0, v8
s_and_saveexec_b32 s24, vcc_lo
s_xor_b32 s24, exec_lo, s24
s_cbranch_execz .LBB0_43
v_mul_f32_e32 v8, v7, v7
v_add_f32_e32 v7, v7, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v8, v8, v10
v_fma_f32 v6, v6, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v7, v4, v8 :: v_dual_mul_f32 v10, v6, v6
v_fma_f32 v8, v7, v7, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_nlt_f32_e32 vcc_lo, 4.0, v8
s_and_saveexec_b32 s25, vcc_lo
s_xor_b32 s25, exec_lo, s25
s_cbranch_execz .LBB0_40
v_mul_f32_e32 v8, v7, v7
v_add_f32_e32 v7, v7, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v8, v8, v10
v_fma_f32 v6, v6, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v7, v4, v8 :: v_dual_mul_f32 v10, v6, v6
v_fma_f32 v8, v7, v7, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_nlt_f32_e32 vcc_lo, 4.0, v8
s_and_saveexec_b32 s26, vcc_lo
s_xor_b32 s26, exec_lo, s26
s_cbranch_execz .LBB0_37
v_mul_f32_e32 v8, v7, v7
v_add_f32_e32 v7, v7, v7
s_mov_b32 s28, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v8, v8, v10
v_fma_f32 v6, v6, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_add_f32 v7, v4, v8 :: v_dual_mul_f32 v10, v6, v6
v_add_nc_u32_e32 v8, 20, v9
v_fma_f32 v11, v7, v7, v10
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_nlt_f32_e32 4.0, v11
s_xor_b32 s28, exec_lo, s28
v_mul_f32_e32 v9, v7, v7
s_mov_b32 s27, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v9, v9, v10 :: v_dual_add_f32 v10, v7, v7
v_add_f32_e32 v7, v4, v9
s_delay_alu instid0(VALU_DEP_2)
v_fma_f32 v6, v6, v10, v5
s_and_not1_saveexec_b32 s28, s28
s_cbranch_execz .LBB0_36
s_and_not1_b32 s27, s27, exec_lo
global_store_b32 v[2:3], v8, off
.LBB0_36:
s_or_b32 exec_lo, exec_lo, s28
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s27, s27, exec_lo
.LBB0_37:
s_and_not1_saveexec_b32 s26, s26
s_cbranch_execz .LBB0_39
v_add_nc_u32_e32 v8, 19, v9
s_and_not1_b32 s27, s27, exec_lo
global_store_b32 v[2:3], v8, off
.LBB0_39:
s_or_b32 exec_lo, exec_lo, s26
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s26, s27, exec_lo
.LBB0_40:
s_and_not1_saveexec_b32 s25, s25
s_cbranch_execz .LBB0_42
v_add_nc_u32_e32 v8, 18, v9
s_and_not1_b32 s26, s26, exec_lo
global_store_b32 v[2:3], v8, off
.LBB0_42:
s_or_b32 exec_lo, exec_lo, s25
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s25, s26, exec_lo
.LBB0_43:
s_and_not1_saveexec_b32 s24, s24
s_cbranch_execz .LBB0_45
v_add_nc_u32_e32 v8, 17, v9
s_and_not1_b32 s25, s25, exec_lo
global_store_b32 v[2:3], v8, off
.LBB0_45:
s_or_b32 exec_lo, exec_lo, s24
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s24, s25, exec_lo
.LBB0_46:
s_and_not1_saveexec_b32 s23, s23
s_cbranch_execz .LBB0_48
v_add_nc_u32_e32 v8, 16, v9
s_and_not1_b32 s24, s24, exec_lo
global_store_b32 v[2:3], v8, off
.LBB0_48:
s_or_b32 exec_lo, exec_lo, s23
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s23, s24, exec_lo
.LBB0_49:
s_and_not1_saveexec_b32 s22, s22
s_cbranch_execz .LBB0_51
v_add_nc_u32_e32 v8, 15, v9
s_and_not1_b32 s23, s23, exec_lo
global_store_b32 v[2:3], v8, off
.LBB0_51:
s_or_b32 exec_lo, exec_lo, s22
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s22, s23, exec_lo
.LBB0_52:
s_and_not1_saveexec_b32 s21, s21
s_cbranch_execz .LBB0_54
v_add_nc_u32_e32 v8, 14, v9
s_and_not1_b32 s22, s22, exec_lo
global_store_b32 v[2:3], v8, off
.LBB0_54:
s_or_b32 exec_lo, exec_lo, s21
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s21, s22, exec_lo
.LBB0_55:
s_and_not1_saveexec_b32 s20, s20
s_cbranch_execz .LBB0_57
v_add_nc_u32_e32 v8, 13, v9
s_and_not1_b32 s21, s21, exec_lo
global_store_b32 v[2:3], v8, off
.LBB0_57:
s_or_b32 exec_lo, exec_lo, s20
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s20, s21, exec_lo
.LBB0_58:
s_and_not1_saveexec_b32 s19, s19
s_cbranch_execz .LBB0_60
v_add_nc_u32_e32 v8, 12, v9
s_and_not1_b32 s20, s20, exec_lo
global_store_b32 v[2:3], v8, off
.LBB0_60:
s_or_b32 exec_lo, exec_lo, s19
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s19, s20, exec_lo
.LBB0_61:
s_and_not1_saveexec_b32 s18, s18
s_cbranch_execz .LBB0_63
v_add_nc_u32_e32 v8, 11, v9
s_and_not1_b32 s19, s19, exec_lo
global_store_b32 v[2:3], v8, off
.LBB0_63:
s_or_b32 exec_lo, exec_lo, s18
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s18, s19, exec_lo
.LBB0_64:
s_and_not1_saveexec_b32 s17, s17
s_cbranch_execz .LBB0_66
v_add_nc_u32_e32 v8, 10, v9
s_and_not1_b32 s18, s18, exec_lo
global_store_b32 v[2:3], v8, off
.LBB0_66:
s_or_b32 exec_lo, exec_lo, s17
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s17, s18, exec_lo
.LBB0_67:
s_and_not1_saveexec_b32 s16, s16
s_cbranch_execz .LBB0_69
v_add_nc_u32_e32 v8, 9, v9
s_and_not1_b32 s17, s17, exec_lo
global_store_b32 v[2:3], v8, off
.LBB0_69:
s_or_b32 exec_lo, exec_lo, s16
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s16, s17, exec_lo
.LBB0_70:
s_and_not1_saveexec_b32 s15, s15
s_cbranch_execz .LBB0_72
v_add_nc_u32_e32 v8, 8, v9
s_and_not1_b32 s16, s16, exec_lo
global_store_b32 v[2:3], v8, off
.LBB0_72:
s_or_b32 exec_lo, exec_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s15, s16, exec_lo
.LBB0_73:
s_and_not1_saveexec_b32 s14, s14
s_cbranch_execz .LBB0_75
v_add_nc_u32_e32 v8, 7, v9
s_and_not1_b32 s15, s15, exec_lo
global_store_b32 v[2:3], v8, off
.LBB0_75:
s_or_b32 exec_lo, exec_lo, s14
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s14, s15, exec_lo
.LBB0_76:
s_and_not1_saveexec_b32 s13, s13
s_cbranch_execz .LBB0_78
v_add_nc_u32_e32 v8, 6, v9
s_and_not1_b32 s14, s14, exec_lo
global_store_b32 v[2:3], v8, off
.LBB0_78:
s_or_b32 exec_lo, exec_lo, s13
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s13, s14, exec_lo
.LBB0_79:
s_and_not1_saveexec_b32 s12, s12
s_cbranch_execz .LBB0_81
v_add_nc_u32_e32 v8, 5, v9
s_and_not1_b32 s13, s13, exec_lo
global_store_b32 v[2:3], v8, off
.LBB0_81:
s_or_b32 exec_lo, exec_lo, s12
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s12, s13, exec_lo
.LBB0_82:
s_and_not1_saveexec_b32 s11, s11
s_cbranch_execz .LBB0_84
v_add_nc_u32_e32 v8, 4, v9
s_and_not1_b32 s12, s12, exec_lo
global_store_b32 v[2:3], v8, off
.LBB0_84:
s_or_b32 exec_lo, exec_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s11, s12, exec_lo
.LBB0_85:
s_and_not1_saveexec_b32 s10, s10
s_cbranch_execz .LBB0_87
v_add_nc_u32_e32 v8, 3, v9
s_and_not1_b32 s11, s11, exec_lo
global_store_b32 v[2:3], v8, off
.LBB0_87:
s_or_b32 exec_lo, exec_lo, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s10, s11, exec_lo
.LBB0_88:
s_and_not1_saveexec_b32 s9, s9
s_cbranch_execz .LBB0_90
v_add_nc_u32_e32 v8, 2, v9
s_and_not1_b32 s10, s10, exec_lo
global_store_b32 v[2:3], v8, off
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s9, s10, exec_lo
.LBB0_91:
s_and_not1_saveexec_b32 s8, s8
s_cbranch_execz .LBB0_93
v_add_nc_u32_e32 v8, 1, v9
s_and_not1_b32 s9, s9, exec_lo
global_store_b32 v[2:3], v8, off
.LBB0_93:
s_or_b32 exec_lo, exec_lo, s8
s_mov_b32 s10, -1
s_mov_b32 s8, 0
s_and_saveexec_b32 s12, s9
s_cbranch_execz .LBB0_10
v_cmp_lt_i32_e32 vcc_lo, 0x1869e, v8
v_add_nc_u32_e32 v10, 1, v8
s_mov_b32 s8, exec_lo
s_mov_b32 s11, 0x186a0
s_or_not1_b32 s10, vcc_lo, exec_lo
s_branch .LBB0_10
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
.LBB0_96:
s_and_saveexec_b32 s1, s0
s_cbranch_execnz .LBB0_98
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.LBB0_98:
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_store_b32 v[0:1], v8, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL12mandelKernelffffPiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 29
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL12mandelKernelffffPiiii,"axG",@progbits,_ZL12mandelKernelffffPiiii,comdat
.Lfunc_end0:
.size _ZL12mandelKernelffffPiiii, .Lfunc_end0-_ZL12mandelKernelffffPiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL12mandelKernelffffPiiii
.private_segment_fixed_size: 0
.sgpr_count: 31
.sgpr_spill_count: 0
.symbol: _ZL12mandelKernelffffPiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define BLOCK_WIDTH 8
__global__ static void mandelKernel(float upperX, float upperY, float lowerX, float lowerY, int* img, int resX, int resY, int maxIterations) {
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float stepX = (upperX - lowerX) / resX;
float stepY = (upperY - lowerY) / resY;
float x = lowerX + col * stepX;
float y = lowerY + row * stepY;
float z_re = x, z_im = y;
if (maxIterations == 100000) {
#pragma unroll
for (int val = 0; val < maxIterations; ++val) {
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
float new_re = z_re * z_re - z_im * z_im;
float new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
val++;
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
new_re = z_re * z_re - z_im * z_im;
new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
}
img[row * resX + col] = maxIterations;
}
else {
for (int val = 0; val < maxIterations; ++val) {
if (z_re * z_re + z_im * z_im > 4.f) {
img[row * resX + col] = val;
return;
}
float new_re = z_re * z_re - z_im * z_im;
float new_im = 2.f * z_re * z_im;
z_re = x + new_re;
z_im = y + new_im;
}
img[row * resX + col] = maxIterations;
}
}
// Host front-end function that allocates the memory and launches the GPU kernel
void hostFE (float upperX, float upperY, float lowerX, float lowerY, int* img, int resX, int resY, int maxIterations) {
int *temp_img;
static int x_blocks = resX / BLOCK_WIDTH;
static int y_blocks = resY / BLOCK_WIDTH;
dim3 block_size(BLOCK_WIDTH, BLOCK_WIDTH);
dim3 num_block(x_blocks, y_blocks);
hipMalloc(&temp_img, resX * resY * sizeof(int));
mandelKernel<<<num_block, block_size>>>(upperX, upperY, lowerX, lowerY, temp_img, resX, resY, maxIterations);
hipMemcpy(img, temp_img, resX * resY * sizeof(int), hipMemcpyDeviceToHost);
hipFree(temp_img);
} | .text
.file "kernel4.hip"
.globl _Z6hostFEffffPiiii # -- Begin function _Z6hostFEffffPiiii
.p2align 4, 0x90
.type _Z6hostFEffffPiiii,@function
_Z6hostFEffffPiiii: # @_Z6hostFEffffPiiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movl %edx, %r14d
movl %esi, %r15d
movq %rdi, %rbx
movss %xmm3, 24(%rsp) # 4-byte Spill
movss %xmm2, 20(%rsp) # 4-byte Spill
movss %xmm1, 16(%rsp) # 4-byte Spill
movss %xmm0, 12(%rsp) # 4-byte Spill
movzbl _ZGVZ6hostFEffffPiiiiE8x_blocks(%rip), %eax
testb %al, %al
je .LBB0_1
.LBB0_3:
movzbl _ZGVZ6hostFEffffPiiiiE8y_blocks(%rip), %eax
testb %al, %al
je .LBB0_4
.LBB0_6:
movl _ZZ6hostFEffffPiiiiE8x_blocks(%rip), %eax
movl _ZZ6hostFEffffPiiiiE8y_blocks(%rip), %r13d
shlq $32, %r13
orq %rax, %r13
movl %r14d, %eax
imull %r15d, %eax
movslq %eax, %r12
shlq $2, %r12
movq %rsp, %rdi
movq %r12, %rsi
callq hipMalloc
movabsq $34359738376, %rdx # imm = 0x800000008
movq %r13, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_8
# %bb.7:
movq (%rsp), %rax
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 52(%rsp)
movss 16(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 48(%rsp)
movss 20(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 44(%rsp)
movss 24(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 40(%rsp)
movq %rax, 104(%rsp)
movl %r15d, 36(%rsp)
movl %r14d, 32(%rsp)
movl %ebp, 28(%rsp)
leaq 52(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rax
movq %rax, 120(%rsp)
leaq 44(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 28(%rsp), %rax
movq %rax, 168(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_ZL12mandelKernelffffPiiii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_8:
movq (%rsp), %rsi
movq %rbx, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
callq hipFree
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_1:
.cfi_def_cfa_offset 240
movl $_ZGVZ6hostFEffffPiiiiE8x_blocks, %edi
callq __cxa_guard_acquire
testl %eax, %eax
je .LBB0_3
# %bb.2:
leal 7(%r15), %eax
testl %r15d, %r15d
cmovnsl %r15d, %eax
sarl $3, %eax
movl %eax, _ZZ6hostFEffffPiiiiE8x_blocks(%rip)
movl $_ZGVZ6hostFEffffPiiiiE8x_blocks, %edi
callq __cxa_guard_release
jmp .LBB0_3
.LBB0_4:
movl $_ZGVZ6hostFEffffPiiiiE8y_blocks, %edi
callq __cxa_guard_acquire
testl %eax, %eax
je .LBB0_6
# %bb.5:
leal 7(%r14), %eax
testl %r14d, %r14d
cmovnsl %r14d, %eax
sarl $3, %eax
movl %eax, _ZZ6hostFEffffPiiiiE8y_blocks(%rip)
movl $_ZGVZ6hostFEffffPiiiiE8y_blocks, %edi
callq __cxa_guard_release
jmp .LBB0_6
.Lfunc_end0:
.size _Z6hostFEffffPiiii, .Lfunc_end0-_Z6hostFEffffPiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL27__device_stub__mandelKernelffffPiiii
.type _ZL27__device_stub__mandelKernelffffPiiii,@function
_ZL27__device_stub__mandelKernelffffPiiii: # @_ZL27__device_stub__mandelKernelffffPiiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movss %xmm0, 36(%rsp)
movss %xmm1, 32(%rsp)
movss %xmm2, 28(%rsp)
movss %xmm3, 24(%rsp)
movq %rdi, 88(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 36(%rsp), %rax
movq %rax, 96(%rsp)
leaq 32(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_ZL12mandelKernelffffPiiii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end1:
.size _ZL27__device_stub__mandelKernelffffPiiii, .Lfunc_end1-_ZL27__device_stub__mandelKernelffffPiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZL12mandelKernelffffPiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _ZZ6hostFEffffPiiiiE8x_blocks,@object # @_ZZ6hostFEffffPiiiiE8x_blocks
.local _ZZ6hostFEffffPiiiiE8x_blocks
.comm _ZZ6hostFEffffPiiiiE8x_blocks,4,4
.type _ZGVZ6hostFEffffPiiiiE8x_blocks,@object # @_ZGVZ6hostFEffffPiiiiE8x_blocks
.local _ZGVZ6hostFEffffPiiiiE8x_blocks
.comm _ZGVZ6hostFEffffPiiiiE8x_blocks,8,8
.type _ZZ6hostFEffffPiiiiE8y_blocks,@object # @_ZZ6hostFEffffPiiiiE8y_blocks
.local _ZZ6hostFEffffPiiiiE8y_blocks
.comm _ZZ6hostFEffffPiiiiE8y_blocks,4,4
.type _ZGVZ6hostFEffffPiiiiE8y_blocks,@object # @_ZGVZ6hostFEffffPiiiiE8y_blocks
.local _ZGVZ6hostFEffffPiiiiE8y_blocks
.comm _ZGVZ6hostFEffffPiiiiE8y_blocks,8,8
.type _ZL12mandelKernelffffPiiii,@object # @_ZL12mandelKernelffffPiiii
.section .rodata,"a",@progbits
.p2align 3, 0x0
_ZL12mandelKernelffffPiiii:
.quad _ZL27__device_stub__mandelKernelffffPiiii
.size _ZL12mandelKernelffffPiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_ZL12mandelKernelffffPiiii"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZL27__device_stub__mandelKernelffffPiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZGVZ6hostFEffffPiiiiE8x_blocks
.addrsig_sym _ZGVZ6hostFEffffPiiiiE8y_blocks
.addrsig_sym _ZL12mandelKernelffffPiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d207b_00000000-6_kernel4.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL39__device_stub__Z12mandelKernelffffPiiiiffffPiiii, @function
_ZL39__device_stub__Z12mandelKernelffffPiiiiffffPiiii:
.LFB2082:
.cfi_startproc
subq $200, %rsp
.cfi_def_cfa_offset 208
movss %xmm0, 44(%rsp)
movss %xmm1, 40(%rsp)
movss %xmm2, 36(%rsp)
movss %xmm3, 32(%rsp)
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _ZL12mandelKernelffffPiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _ZL39__device_stub__Z12mandelKernelffffPiiiiffffPiiii, .-_ZL39__device_stub__Z12mandelKernelffffPiiiiffffPiiii
.type _ZL12mandelKernelffffPiiii, @function
_ZL12mandelKernelffffPiiii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL39__device_stub__Z12mandelKernelffffPiiiiffffPiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL12mandelKernelffffPiiii, .-_ZL12mandelKernelffffPiiii
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6hostFEffffPiiii
.type _Z6hostFEffffPiiii, @function
_Z6hostFEffffPiiii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movss %xmm0, (%rsp)
movss %xmm1, 4(%rsp)
movss %xmm2, 8(%rsp)
movss %xmm3, 12(%rsp)
movq %rdi, %r13
movl %esi, %ebp
movl %edx, %r12d
movl %ecx, %r14d
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movzbl _ZGVZ6hostFEffffPiiiiE8x_blocks(%rip), %eax
testb %al, %al
je .L17
.L12:
movzbl _ZGVZ6hostFEffffPiiiiE8y_blocks(%rip), %eax
testb %al, %al
je .L18
.L13:
movl $8, 32(%rsp)
movl $8, 36(%rsp)
movl $1, 40(%rsp)
movl _ZZ6hostFEffffPiiiiE8x_blocks(%rip), %eax
movl %eax, 44(%rsp)
movl _ZZ6hostFEffffPiiiiE8y_blocks(%rip), %eax
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl %ebp, %ebx
imull %r12d, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L14:
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
leaq _ZGVZ6hostFEffffPiiiiE8x_blocks(%rip), %rdi
call __cxa_guard_acquire@PLT
testl %eax, %eax
je .L12
leal 7(%rbp), %eax
testl %ebp, %ebp
cmovns %ebp, %eax
sarl $3, %eax
movl %eax, _ZZ6hostFEffffPiiiiE8x_blocks(%rip)
leaq _ZGVZ6hostFEffffPiiiiE8x_blocks(%rip), %rdi
call __cxa_guard_release@PLT
jmp .L12
.L18:
leaq _ZGVZ6hostFEffffPiiiiE8y_blocks(%rip), %rdi
call __cxa_guard_acquire@PLT
testl %eax, %eax
je .L13
leal 7(%r12), %eax
testl %r12d, %r12d
cmovns %r12d, %eax
sarl $3, %eax
movl %eax, _ZZ6hostFEffffPiiiiE8y_blocks(%rip)
leaq _ZGVZ6hostFEffffPiiiiE8y_blocks(%rip), %rdi
call __cxa_guard_release@PLT
jmp .L13
.L19:
movl %r14d, %ecx
movl %r12d, %edx
movl %ebp, %esi
movq 24(%rsp), %rdi
movss 12(%rsp), %xmm3
movss 8(%rsp), %xmm2
movss 4(%rsp), %xmm1
movss (%rsp), %xmm0
call _ZL39__device_stub__Z12mandelKernelffffPiiiiffffPiiii
jmp .L14
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z6hostFEffffPiiii, .-_Z6hostFEffffPiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12mandelKernelffffPiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL12mandelKernelffffPiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZGVZ6hostFEffffPiiiiE8y_blocks
.comm _ZGVZ6hostFEffffPiiiiE8y_blocks,8,8
.local _ZZ6hostFEffffPiiiiE8y_blocks
.comm _ZZ6hostFEffffPiiiiE8y_blocks,4,4
.local _ZGVZ6hostFEffffPiiiiE8x_blocks
.comm _ZGVZ6hostFEffffPiiiiE8x_blocks,8,8
.local _ZZ6hostFEffffPiiiiE8x_blocks
.comm _ZZ6hostFEffffPiiiiE8x_blocks,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel4.hip"
.globl _Z6hostFEffffPiiii # -- Begin function _Z6hostFEffffPiiii
.p2align 4, 0x90
.type _Z6hostFEffffPiiii,@function
_Z6hostFEffffPiiii: # @_Z6hostFEffffPiiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movl %edx, %r14d
movl %esi, %r15d
movq %rdi, %rbx
movss %xmm3, 24(%rsp) # 4-byte Spill
movss %xmm2, 20(%rsp) # 4-byte Spill
movss %xmm1, 16(%rsp) # 4-byte Spill
movss %xmm0, 12(%rsp) # 4-byte Spill
movzbl _ZGVZ6hostFEffffPiiiiE8x_blocks(%rip), %eax
testb %al, %al
je .LBB0_1
.LBB0_3:
movzbl _ZGVZ6hostFEffffPiiiiE8y_blocks(%rip), %eax
testb %al, %al
je .LBB0_4
.LBB0_6:
movl _ZZ6hostFEffffPiiiiE8x_blocks(%rip), %eax
movl _ZZ6hostFEffffPiiiiE8y_blocks(%rip), %r13d
shlq $32, %r13
orq %rax, %r13
movl %r14d, %eax
imull %r15d, %eax
movslq %eax, %r12
shlq $2, %r12
movq %rsp, %rdi
movq %r12, %rsi
callq hipMalloc
movabsq $34359738376, %rdx # imm = 0x800000008
movq %r13, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_8
# %bb.7:
movq (%rsp), %rax
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 52(%rsp)
movss 16(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 48(%rsp)
movss 20(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 44(%rsp)
movss 24(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 40(%rsp)
movq %rax, 104(%rsp)
movl %r15d, 36(%rsp)
movl %r14d, 32(%rsp)
movl %ebp, 28(%rsp)
leaq 52(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rax
movq %rax, 120(%rsp)
leaq 44(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 28(%rsp), %rax
movq %rax, 168(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_ZL12mandelKernelffffPiiii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_8:
movq (%rsp), %rsi
movq %rbx, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
callq hipFree
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_1:
.cfi_def_cfa_offset 240
movl $_ZGVZ6hostFEffffPiiiiE8x_blocks, %edi
callq __cxa_guard_acquire
testl %eax, %eax
je .LBB0_3
# %bb.2:
leal 7(%r15), %eax
testl %r15d, %r15d
cmovnsl %r15d, %eax
sarl $3, %eax
movl %eax, _ZZ6hostFEffffPiiiiE8x_blocks(%rip)
movl $_ZGVZ6hostFEffffPiiiiE8x_blocks, %edi
callq __cxa_guard_release
jmp .LBB0_3
.LBB0_4:
movl $_ZGVZ6hostFEffffPiiiiE8y_blocks, %edi
callq __cxa_guard_acquire
testl %eax, %eax
je .LBB0_6
# %bb.5:
leal 7(%r14), %eax
testl %r14d, %r14d
cmovnsl %r14d, %eax
sarl $3, %eax
movl %eax, _ZZ6hostFEffffPiiiiE8y_blocks(%rip)
movl $_ZGVZ6hostFEffffPiiiiE8y_blocks, %edi
callq __cxa_guard_release
jmp .LBB0_6
.Lfunc_end0:
.size _Z6hostFEffffPiiii, .Lfunc_end0-_Z6hostFEffffPiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL27__device_stub__mandelKernelffffPiiii
.type _ZL27__device_stub__mandelKernelffffPiiii,@function
_ZL27__device_stub__mandelKernelffffPiiii: # @_ZL27__device_stub__mandelKernelffffPiiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movss %xmm0, 36(%rsp)
movss %xmm1, 32(%rsp)
movss %xmm2, 28(%rsp)
movss %xmm3, 24(%rsp)
movq %rdi, 88(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 36(%rsp), %rax
movq %rax, 96(%rsp)
leaq 32(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_ZL12mandelKernelffffPiiii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end1:
.size _ZL27__device_stub__mandelKernelffffPiiii, .Lfunc_end1-_ZL27__device_stub__mandelKernelffffPiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZL12mandelKernelffffPiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _ZZ6hostFEffffPiiiiE8x_blocks,@object # @_ZZ6hostFEffffPiiiiE8x_blocks
.local _ZZ6hostFEffffPiiiiE8x_blocks
.comm _ZZ6hostFEffffPiiiiE8x_blocks,4,4
.type _ZGVZ6hostFEffffPiiiiE8x_blocks,@object # @_ZGVZ6hostFEffffPiiiiE8x_blocks
.local _ZGVZ6hostFEffffPiiiiE8x_blocks
.comm _ZGVZ6hostFEffffPiiiiE8x_blocks,8,8
.type _ZZ6hostFEffffPiiiiE8y_blocks,@object # @_ZZ6hostFEffffPiiiiE8y_blocks
.local _ZZ6hostFEffffPiiiiE8y_blocks
.comm _ZZ6hostFEffffPiiiiE8y_blocks,4,4
.type _ZGVZ6hostFEffffPiiiiE8y_blocks,@object # @_ZGVZ6hostFEffffPiiiiE8y_blocks
.local _ZGVZ6hostFEffffPiiiiE8y_blocks
.comm _ZGVZ6hostFEffffPiiiiE8y_blocks,8,8
.type _ZL12mandelKernelffffPiiii,@object # @_ZL12mandelKernelffffPiiii
.section .rodata,"a",@progbits
.p2align 3, 0x0
_ZL12mandelKernelffffPiiii:
.quad _ZL27__device_stub__mandelKernelffffPiiii
.size _ZL12mandelKernelffffPiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_ZL12mandelKernelffffPiiii"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZL27__device_stub__mandelKernelffffPiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZGVZ6hostFEffffPiiiiE8x_blocks
.addrsig_sym _ZGVZ6hostFEffffPiiiiE8y_blocks
.addrsig_sym _ZL12mandelKernelffffPiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <stdio.h>
// This will output the proper CUDA error strings in the event that a CUDA host call returns an error
#define checkCudaErrors(err) __checkCudaErrors (err, __FILE__, __LINE__)
inline void __checkCudaErrors(cudaError err, const char *file, const int line)
{
if (cudaSuccess != err)
{
fprintf(stderr, "%s(%i) : CUDA Runtime API error %d: %s.\n",
file, line, (int)err, cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
}
int main(int argc, char **argv)
{
printf("[%s] - Starting...\n", argv[0]);
int gpuid[2] = {1, 2}; // we want to find the first two GPU's that can support P2P
float total_time = 0.0;
bool enable_p2p = true;
if (enable_p2p)
{
// Enable peer access
printf("Enabling peer access between GPU%d and GPU%d...\n", gpuid[0], gpuid[1]);
checkCudaErrors(cudaSetDevice(gpuid[0]));
checkCudaErrors(cudaDeviceEnablePeerAccess(gpuid[1], 0));
checkCudaErrors(cudaSetDevice(gpuid[1]));
checkCudaErrors(cudaDeviceEnablePeerAccess(gpuid[0], 0));
}
for (int loop = 0; loop < 100; loop++)
{
// Allocate buffers
const size_t buf_size = 1024 * 1024 * 16 * sizeof(float);
printf("Allocating buffers (%iMB on GPU%d, GPU%d and CPU Host)...\n", int(buf_size / 1024 / 1024), gpuid[0], gpuid[1]);
checkCudaErrors(cudaSetDevice(gpuid[0]));
float *g0;
checkCudaErrors(cudaMalloc(&g0, buf_size));
checkCudaErrors(cudaSetDevice(gpuid[1]));
float *g1;
checkCudaErrors(cudaMalloc(&g1, buf_size));
// Create CUDA event handles
cudaEvent_t start_event, stop_event;
float time_memcpy;
int eventflags = cudaEventBlockingSync;
checkCudaErrors(cudaEventCreateWithFlags(&start_event, eventflags));
checkCudaErrors(cudaEventCreateWithFlags(&stop_event, eventflags));
// P2P memcopy() benchmark
checkCudaErrors(cudaEventRecord(start_event, 0));
for (int i = 0; i < 100; i++)
{
// With UVA we don't need to specify source and target devices, the
// runtime figures this out by itself from the pointers
// Ping-pong copy between GPUs
if (i % 2 == 0)
{
checkCudaErrors(cudaMemcpy(g1, g0, buf_size, cudaMemcpyDefault));
}
else
{
checkCudaErrors(cudaMemcpy(g0, g1, buf_size, cudaMemcpyDefault));
}
}
checkCudaErrors(cudaEventRecord(stop_event, 0));
checkCudaErrors(cudaEventSynchronize(stop_event));
checkCudaErrors(cudaEventElapsedTime(&time_memcpy, start_event, stop_event));
total_time += time_memcpy;
printf("cudaMemcpyPeer / cudaMemcpy (%f ms) between GPU%d and GPU%d: %.2fGB/s\n", time_memcpy, gpuid[0], gpuid[1],
(1.0f / (time_memcpy / 1000.0f)) * ((100.0f * buf_size)) / 1024.0f / 1024.0f / 1024.0f);
// Free resources
checkCudaErrors(cudaEventDestroy(start_event));
checkCudaErrors(cudaEventDestroy(stop_event));
checkCudaErrors(cudaSetDevice(gpuid[0]));
checkCudaErrors(cudaFree(g0));
checkCudaErrors(cudaSetDevice(gpuid[1]));
checkCudaErrors(cudaFree(g1));
}
if (enable_p2p)
{
// Disable peer access (also unregisters memory for non-UVA cases)
printf("Disabling peer access...\n");
checkCudaErrors(cudaSetDevice(gpuid[0]));
checkCudaErrors(cudaDeviceDisablePeerAccess(gpuid[1]));
checkCudaErrors(cudaSetDevice(gpuid[1]));
checkCudaErrors(cudaDeviceDisablePeerAccess(gpuid[0]));
}
printf("Total time is %.2fs\n", total_time / 1000);
//delete device_handler;
return (EXIT_SUCCESS);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <stdio.h>
// This will output the proper CUDA error strings in the event that a CUDA host call returns an error
#define checkCudaErrors(err) __checkCudaErrors (err, __FILE__, __LINE__)
inline void __checkCudaErrors(cudaError err, const char *file, const int line)
{
if (cudaSuccess != err)
{
fprintf(stderr, "%s(%i) : CUDA Runtime API error %d: %s.\n",
file, line, (int)err, cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
}
int main(int argc, char **argv)
{
printf("[%s] - Starting...\n", argv[0]);
int gpuid[2] = {1, 2}; // we want to find the first two GPU's that can support P2P
float total_time = 0.0;
bool enable_p2p = true;
if (enable_p2p)
{
// Enable peer access
printf("Enabling peer access between GPU%d and GPU%d...\n", gpuid[0], gpuid[1]);
checkCudaErrors(cudaSetDevice(gpuid[0]));
checkCudaErrors(cudaDeviceEnablePeerAccess(gpuid[1], 0));
checkCudaErrors(cudaSetDevice(gpuid[1]));
checkCudaErrors(cudaDeviceEnablePeerAccess(gpuid[0], 0));
}
for (int loop = 0; loop < 100; loop++)
{
// Allocate buffers
const size_t buf_size = 1024 * 1024 * 16 * sizeof(float);
printf("Allocating buffers (%iMB on GPU%d, GPU%d and CPU Host)...\n", int(buf_size / 1024 / 1024), gpuid[0], gpuid[1]);
checkCudaErrors(cudaSetDevice(gpuid[0]));
float *g0;
checkCudaErrors(cudaMalloc(&g0, buf_size));
checkCudaErrors(cudaSetDevice(gpuid[1]));
float *g1;
checkCudaErrors(cudaMalloc(&g1, buf_size));
// Create CUDA event handles
cudaEvent_t start_event, stop_event;
float time_memcpy;
int eventflags = cudaEventBlockingSync;
checkCudaErrors(cudaEventCreateWithFlags(&start_event, eventflags));
checkCudaErrors(cudaEventCreateWithFlags(&stop_event, eventflags));
// P2P memcopy() benchmark
checkCudaErrors(cudaEventRecord(start_event, 0));
for (int i = 0; i < 100; i++)
{
// With UVA we don't need to specify source and target devices, the
// runtime figures this out by itself from the pointers
// Ping-pong copy between GPUs
if (i % 2 == 0)
{
checkCudaErrors(cudaMemcpy(g1, g0, buf_size, cudaMemcpyDefault));
}
else
{
checkCudaErrors(cudaMemcpy(g0, g1, buf_size, cudaMemcpyDefault));
}
}
checkCudaErrors(cudaEventRecord(stop_event, 0));
checkCudaErrors(cudaEventSynchronize(stop_event));
checkCudaErrors(cudaEventElapsedTime(&time_memcpy, start_event, stop_event));
total_time += time_memcpy;
printf("cudaMemcpyPeer / cudaMemcpy (%f ms) between GPU%d and GPU%d: %.2fGB/s\n", time_memcpy, gpuid[0], gpuid[1],
(1.0f / (time_memcpy / 1000.0f)) * ((100.0f * buf_size)) / 1024.0f / 1024.0f / 1024.0f);
// Free resources
checkCudaErrors(cudaEventDestroy(start_event));
checkCudaErrors(cudaEventDestroy(stop_event));
checkCudaErrors(cudaSetDevice(gpuid[0]));
checkCudaErrors(cudaFree(g0));
checkCudaErrors(cudaSetDevice(gpuid[1]));
checkCudaErrors(cudaFree(g1));
}
if (enable_p2p)
{
// Disable peer access (also unregisters memory for non-UVA cases)
printf("Disabling peer access...\n");
checkCudaErrors(cudaSetDevice(gpuid[0]));
checkCudaErrors(cudaDeviceDisablePeerAccess(gpuid[1]));
checkCudaErrors(cudaSetDevice(gpuid[1]));
checkCudaErrors(cudaDeviceDisablePeerAccess(gpuid[0]));
}
printf("Total time is %.2fs\n", total_time / 1000);
//delete device_handler;
return (EXIT_SUCCESS);
} | .file "tmpxft_00167661_00000000-6_testP2P.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z17__checkCudaErrors9cudaErrorPKci.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "%s(%i) : CUDA Runtime API error %d: %s.\n"
.section .text._Z17__checkCudaErrors9cudaErrorPKci,"axG",@progbits,_Z17__checkCudaErrors9cudaErrorPKci,comdat
.weak _Z17__checkCudaErrors9cudaErrorPKci
.type _Z17__checkCudaErrors9cudaErrorPKci, @function
_Z17__checkCudaErrors9cudaErrorPKci:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L8
ret
.L8:
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl %edi, %ebx
movq %rsi, %rbp
movl %edx, %r12d
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
movl %ebx, %r9d
movl %r12d, %r8d
movq %rbp, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z17__checkCudaErrors9cudaErrorPKci, .-_Z17__checkCudaErrors9cudaErrorPKci
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "[%s] - Starting...\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Enabling peer access between GPU%d and GPU%d...\n"
.align 8
.LC4:
.string "/home/ubuntu/Datasets/stackv2/train-structured/NanXiao/code-for-my-blog/master/2018/06/testP2P/testP2P.cu"
.align 8
.LC5:
.string "Allocating buffers (%iMB on GPU%d, GPU%d and CPU Host)...\n"
.align 8
.LC10:
.string "cudaMemcpyPeer / cudaMemcpy (%f ms) between GPU%d and GPU%d: %.2fGB/s\n"
.section .rodata.str1.1
.LC11:
.string "Disabling peer access...\n"
.LC12:
.string "Total time is %.2fs\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq (%rsi), %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $2, %ecx
movl $1, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call cudaSetDevice@PLT
movl %eax, %edi
movl $28, %edx
leaq .LC4(%rip), %rbx
movq %rbx, %rsi
call _Z17__checkCudaErrors9cudaErrorPKci
movl $0, %esi
movl $2, %edi
call cudaDeviceEnablePeerAccess@PLT
movl %eax, %edi
movl $29, %edx
movq %rbx, %rsi
call _Z17__checkCudaErrors9cudaErrorPKci
movl $2, %edi
call cudaSetDevice@PLT
movl %eax, %edi
movl $30, %edx
movq %rbx, %rsi
call _Z17__checkCudaErrors9cudaErrorPKci
movl $0, %esi
movl $1, %edi
call cudaDeviceEnablePeerAccess@PLT
movl %eax, %edi
movl $31, %edx
movq %rbx, %rsi
call _Z17__checkCudaErrors9cudaErrorPKci
movl $100, %r12d
movl $0x00000000, %r13d
jmp .L28
.L46:
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 104
pushq %rax
.cfi_def_cfa_offset 112
movl %ebx, %r9d
movl $39, %r8d
leaq .LC4(%rip), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L47:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 104
pushq %rax
.cfi_def_cfa_offset 112
movl %ebx, %r9d
movl $41, %r8d
leaq .LC4(%rip), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L48:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 104
pushq %rax
.cfi_def_cfa_offset 112
movl %ebx, %r9d
movl $42, %r8d
leaq .LC4(%rip), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L49:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 104
pushq %rax
.cfi_def_cfa_offset 112
movl %ebx, %r9d
movl $44, %r8d
leaq .LC4(%rip), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L50:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 104
pushq %rax
.cfi_def_cfa_offset 112
movl %ebx, %r9d
movl $50, %r8d
leaq .LC4(%rip), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L51:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 104
pushq %rax
.cfi_def_cfa_offset 112
movl %ebx, %r9d
movl $51, %r8d
leaq .LC4(%rip), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L52:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 104
pushq %rax
.cfi_def_cfa_offset 112
movl %ebx, %r9d
movl $54, %r8d
leaq .LC4(%rip), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L17:
.cfi_restore_state
movl $4, %ecx
movl $67108864, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L34
.L18:
addl $1, %ebx
cmpl $100, %ebx
je .L35
.L16:
testb $1, %bl
jne .L17
movl $4, %ecx
movl $67108864, %edx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebp
testl %eax, %eax
je .L18
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 104
pushq %rax
.cfi_def_cfa_offset 112
movl %ebp, %r9d
movl $64, %r8d
leaq .LC4(%rip), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L34:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 104
pushq %rax
.cfi_def_cfa_offset 112
movl %ebp, %r9d
movl $68, %r8d
leaq .LC4(%rip), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L35:
.cfi_restore_state
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L36
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L37
leaq 4(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L38
movss 4(%rsp), %xmm0
movd %r13d, %xmm3
addss %xmm0, %xmm3
movd %xmm3, %r13d
movaps %xmm0, %xmm2
divss .LC6(%rip), %xmm2
movss .LC7(%rip), %xmm1
divss %xmm2, %xmm1
mulss .LC8(%rip), %xmm1
mulss .LC9(%rip), %xmm1
mulss .LC9(%rip), %xmm1
mulss .LC9(%rip), %xmm1
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $2, %ecx
movl $1, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L39
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L40
movl $1, %edi
call cudaSetDevice@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L41
movq 8(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L42
movl $2, %edi
call cudaSetDevice@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L43
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L44
subl $1, %r12d
je .L45
.L28:
movl $2, %r8d
movl $1, %ecx
movl $64, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call cudaSetDevice@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L46
leaq 8(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L47
movl $2, %edi
call cudaSetDevice@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L48
leaq 16(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L49
leaq 24(%rsp), %rdi
movl $1, %esi
call cudaEventCreateWithFlags@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L50
leaq 32(%rsp), %rdi
movl $1, %esi
call cudaEventCreateWithFlags@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L51
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L52
movl $0, %ebx
jmp .L16
.L36:
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 104
pushq %rax
.cfi_def_cfa_offset 112
movl %ebx, %r9d
movl $72, %r8d
leaq .LC4(%rip), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L37:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 104
pushq %rax
.cfi_def_cfa_offset 112
movl %ebx, %r9d
movl $73, %r8d
leaq .LC4(%rip), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L38:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 104
pushq %rax
.cfi_def_cfa_offset 112
movl %ebx, %r9d
movl $74, %r8d
leaq .LC4(%rip), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L39:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 104
pushq %rax
.cfi_def_cfa_offset 112
movl %ebx, %r9d
movl $80, %r8d
leaq .LC4(%rip), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L40:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 104
pushq %rax
.cfi_def_cfa_offset 112
movl %ebx, %r9d
movl $81, %r8d
leaq .LC4(%rip), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L41:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 104
pushq %rax
.cfi_def_cfa_offset 112
movl %ebx, %r9d
movl $82, %r8d
leaq .LC4(%rip), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L42:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 104
pushq %rax
.cfi_def_cfa_offset 112
movl %ebx, %r9d
movl $83, %r8d
leaq .LC4(%rip), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L43:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 104
pushq %rax
.cfi_def_cfa_offset 112
movl %ebx, %r9d
movl $84, %r8d
leaq .LC4(%rip), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L44:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 104
pushq %rax
.cfi_def_cfa_offset 112
movl %ebx, %r9d
movl $85, %r8d
leaq .LC4(%rip), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L45:
.cfi_restore_state
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call cudaSetDevice@PLT
movl %eax, %edi
movl $93, %edx
leaq .LC4(%rip), %rbx
movq %rbx, %rsi
call _Z17__checkCudaErrors9cudaErrorPKci
movl $2, %edi
call cudaDeviceDisablePeerAccess@PLT
movl %eax, %edi
movl $94, %edx
movq %rbx, %rsi
call _Z17__checkCudaErrors9cudaErrorPKci
movl $2, %edi
call cudaSetDevice@PLT
movl %eax, %edi
movl $95, %edx
movq %rbx, %rsi
call _Z17__checkCudaErrors9cudaErrorPKci
movl $1, %edi
call cudaDeviceDisablePeerAccess@PLT
movl %eax, %edi
movl $96, %edx
movq %rbx, %rsi
call _Z17__checkCudaErrors9cudaErrorPKci
movd %r13d, %xmm0
divss .LC6(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L53
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC6:
.long 1148846080
.align 4
.LC7:
.long 1065353216
.align 4
.LC8:
.long 1338507264
.align 4
.LC9:
.long 981467136
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <stdio.h>
// This will output the proper CUDA error strings in the event that a CUDA host call returns an error
#define checkCudaErrors(err) __checkCudaErrors (err, __FILE__, __LINE__)
inline void __checkCudaErrors(cudaError err, const char *file, const int line)
{
if (cudaSuccess != err)
{
fprintf(stderr, "%s(%i) : CUDA Runtime API error %d: %s.\n",
file, line, (int)err, cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
}
int main(int argc, char **argv)
{
printf("[%s] - Starting...\n", argv[0]);
int gpuid[2] = {1, 2}; // we want to find the first two GPU's that can support P2P
float total_time = 0.0;
bool enable_p2p = true;
if (enable_p2p)
{
// Enable peer access
printf("Enabling peer access between GPU%d and GPU%d...\n", gpuid[0], gpuid[1]);
checkCudaErrors(cudaSetDevice(gpuid[0]));
checkCudaErrors(cudaDeviceEnablePeerAccess(gpuid[1], 0));
checkCudaErrors(cudaSetDevice(gpuid[1]));
checkCudaErrors(cudaDeviceEnablePeerAccess(gpuid[0], 0));
}
for (int loop = 0; loop < 100; loop++)
{
// Allocate buffers
const size_t buf_size = 1024 * 1024 * 16 * sizeof(float);
printf("Allocating buffers (%iMB on GPU%d, GPU%d and CPU Host)...\n", int(buf_size / 1024 / 1024), gpuid[0], gpuid[1]);
checkCudaErrors(cudaSetDevice(gpuid[0]));
float *g0;
checkCudaErrors(cudaMalloc(&g0, buf_size));
checkCudaErrors(cudaSetDevice(gpuid[1]));
float *g1;
checkCudaErrors(cudaMalloc(&g1, buf_size));
// Create CUDA event handles
cudaEvent_t start_event, stop_event;
float time_memcpy;
int eventflags = cudaEventBlockingSync;
checkCudaErrors(cudaEventCreateWithFlags(&start_event, eventflags));
checkCudaErrors(cudaEventCreateWithFlags(&stop_event, eventflags));
// P2P memcopy() benchmark
checkCudaErrors(cudaEventRecord(start_event, 0));
for (int i = 0; i < 100; i++)
{
// With UVA we don't need to specify source and target devices, the
// runtime figures this out by itself from the pointers
// Ping-pong copy between GPUs
if (i % 2 == 0)
{
checkCudaErrors(cudaMemcpy(g1, g0, buf_size, cudaMemcpyDefault));
}
else
{
checkCudaErrors(cudaMemcpy(g0, g1, buf_size, cudaMemcpyDefault));
}
}
checkCudaErrors(cudaEventRecord(stop_event, 0));
checkCudaErrors(cudaEventSynchronize(stop_event));
checkCudaErrors(cudaEventElapsedTime(&time_memcpy, start_event, stop_event));
total_time += time_memcpy;
printf("cudaMemcpyPeer / cudaMemcpy (%f ms) between GPU%d and GPU%d: %.2fGB/s\n", time_memcpy, gpuid[0], gpuid[1],
(1.0f / (time_memcpy / 1000.0f)) * ((100.0f * buf_size)) / 1024.0f / 1024.0f / 1024.0f);
// Free resources
checkCudaErrors(cudaEventDestroy(start_event));
checkCudaErrors(cudaEventDestroy(stop_event));
checkCudaErrors(cudaSetDevice(gpuid[0]));
checkCudaErrors(cudaFree(g0));
checkCudaErrors(cudaSetDevice(gpuid[1]));
checkCudaErrors(cudaFree(g1));
}
if (enable_p2p)
{
// Disable peer access (also unregisters memory for non-UVA cases)
printf("Disabling peer access...\n");
checkCudaErrors(cudaSetDevice(gpuid[0]));
checkCudaErrors(cudaDeviceDisablePeerAccess(gpuid[1]));
checkCudaErrors(cudaSetDevice(gpuid[1]));
checkCudaErrors(cudaDeviceDisablePeerAccess(gpuid[0]));
}
printf("Total time is %.2fs\n", total_time / 1000);
//delete device_handler;
return (EXIT_SUCCESS);
} | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
// This will output the proper CUDA error strings in the event that a CUDA host call returns an error
#define checkCudaErrors(err) __checkCudaErrors (err, __FILE__, __LINE__)
inline void __checkCudaErrors(hipError_t err, const char *file, const int line)
{
if (hipSuccess != err)
{
fprintf(stderr, "%s(%i) : CUDA Runtime API error %d: %s.\n",
file, line, (int)err, hipGetErrorString(err));
exit(EXIT_FAILURE);
}
}
int main(int argc, char **argv)
{
printf("[%s] - Starting...\n", argv[0]);
int gpuid[2] = {1, 2}; // we want to find the first two GPU's that can support P2P
float total_time = 0.0;
bool enable_p2p = true;
if (enable_p2p)
{
// Enable peer access
printf("Enabling peer access between GPU%d and GPU%d...\n", gpuid[0], gpuid[1]);
checkCudaErrors(hipSetDevice(gpuid[0]));
checkCudaErrors(hipDeviceEnablePeerAccess(gpuid[1], 0));
checkCudaErrors(hipSetDevice(gpuid[1]));
checkCudaErrors(hipDeviceEnablePeerAccess(gpuid[0], 0));
}
for (int loop = 0; loop < 100; loop++)
{
// Allocate buffers
const size_t buf_size = 1024 * 1024 * 16 * sizeof(float);
printf("Allocating buffers (%iMB on GPU%d, GPU%d and CPU Host)...\n", int(buf_size / 1024 / 1024), gpuid[0], gpuid[1]);
checkCudaErrors(hipSetDevice(gpuid[0]));
float *g0;
checkCudaErrors(hipMalloc(&g0, buf_size));
checkCudaErrors(hipSetDevice(gpuid[1]));
float *g1;
checkCudaErrors(hipMalloc(&g1, buf_size));
// Create CUDA event handles
hipEvent_t start_event, stop_event;
float time_memcpy;
int eventflags = hipEventBlockingSync;
checkCudaErrors(hipEventCreateWithFlags(&start_event, eventflags));
checkCudaErrors(hipEventCreateWithFlags(&stop_event, eventflags));
// P2P memcopy() benchmark
checkCudaErrors(hipEventRecord(start_event, 0));
for (int i = 0; i < 100; i++)
{
// With UVA we don't need to specify source and target devices, the
// runtime figures this out by itself from the pointers
// Ping-pong copy between GPUs
if (i % 2 == 0)
{
checkCudaErrors(hipMemcpy(g1, g0, buf_size, hipMemcpyDefault));
}
else
{
checkCudaErrors(hipMemcpy(g0, g1, buf_size, hipMemcpyDefault));
}
}
checkCudaErrors(hipEventRecord(stop_event, 0));
checkCudaErrors(hipEventSynchronize(stop_event));
checkCudaErrors(hipEventElapsedTime(&time_memcpy, start_event, stop_event));
total_time += time_memcpy;
printf("hipMemcpyPeer / hipMemcpy (%f ms) between GPU%d and GPU%d: %.2fGB/s\n", time_memcpy, gpuid[0], gpuid[1],
(1.0f / (time_memcpy / 1000.0f)) * ((100.0f * buf_size)) / 1024.0f / 1024.0f / 1024.0f);
// Free resources
checkCudaErrors(hipEventDestroy(start_event));
checkCudaErrors(hipEventDestroy(stop_event));
checkCudaErrors(hipSetDevice(gpuid[0]));
checkCudaErrors(hipFree(g0));
checkCudaErrors(hipSetDevice(gpuid[1]));
checkCudaErrors(hipFree(g1));
}
if (enable_p2p)
{
// Disable peer access (also unregisters memory for non-UVA cases)
printf("Disabling peer access...\n");
checkCudaErrors(hipSetDevice(gpuid[0]));
checkCudaErrors(hipDeviceDisablePeerAccess(gpuid[1]));
checkCudaErrors(hipSetDevice(gpuid[1]));
checkCudaErrors(hipDeviceDisablePeerAccess(gpuid[0]));
}
printf("Total time is %.2fs\n", total_time / 1000);
//delete device_handler;
return (EXIT_SUCCESS);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
// This will output the proper CUDA error strings in the event that a CUDA host call returns an error
#define checkCudaErrors(err) __checkCudaErrors (err, __FILE__, __LINE__)
inline void __checkCudaErrors(hipError_t err, const char *file, const int line)
{
if (hipSuccess != err)
{
fprintf(stderr, "%s(%i) : CUDA Runtime API error %d: %s.\n",
file, line, (int)err, hipGetErrorString(err));
exit(EXIT_FAILURE);
}
}
int main(int argc, char **argv)
{
printf("[%s] - Starting...\n", argv[0]);
int gpuid[2] = {1, 2}; // we want to find the first two GPU's that can support P2P
float total_time = 0.0;
bool enable_p2p = true;
if (enable_p2p)
{
// Enable peer access
printf("Enabling peer access between GPU%d and GPU%d...\n", gpuid[0], gpuid[1]);
checkCudaErrors(hipSetDevice(gpuid[0]));
checkCudaErrors(hipDeviceEnablePeerAccess(gpuid[1], 0));
checkCudaErrors(hipSetDevice(gpuid[1]));
checkCudaErrors(hipDeviceEnablePeerAccess(gpuid[0], 0));
}
for (int loop = 0; loop < 100; loop++)
{
// Allocate buffers
const size_t buf_size = 1024 * 1024 * 16 * sizeof(float);
printf("Allocating buffers (%iMB on GPU%d, GPU%d and CPU Host)...\n", int(buf_size / 1024 / 1024), gpuid[0], gpuid[1]);
checkCudaErrors(hipSetDevice(gpuid[0]));
float *g0;
checkCudaErrors(hipMalloc(&g0, buf_size));
checkCudaErrors(hipSetDevice(gpuid[1]));
float *g1;
checkCudaErrors(hipMalloc(&g1, buf_size));
// Create CUDA event handles
hipEvent_t start_event, stop_event;
float time_memcpy;
int eventflags = hipEventBlockingSync;
checkCudaErrors(hipEventCreateWithFlags(&start_event, eventflags));
checkCudaErrors(hipEventCreateWithFlags(&stop_event, eventflags));
// P2P memcopy() benchmark
checkCudaErrors(hipEventRecord(start_event, 0));
for (int i = 0; i < 100; i++)
{
// With UVA we don't need to specify source and target devices, the
// runtime figures this out by itself from the pointers
// Ping-pong copy between GPUs
if (i % 2 == 0)
{
checkCudaErrors(hipMemcpy(g1, g0, buf_size, hipMemcpyDefault));
}
else
{
checkCudaErrors(hipMemcpy(g0, g1, buf_size, hipMemcpyDefault));
}
}
checkCudaErrors(hipEventRecord(stop_event, 0));
checkCudaErrors(hipEventSynchronize(stop_event));
checkCudaErrors(hipEventElapsedTime(&time_memcpy, start_event, stop_event));
total_time += time_memcpy;
printf("hipMemcpyPeer / hipMemcpy (%f ms) between GPU%d and GPU%d: %.2fGB/s\n", time_memcpy, gpuid[0], gpuid[1],
(1.0f / (time_memcpy / 1000.0f)) * ((100.0f * buf_size)) / 1024.0f / 1024.0f / 1024.0f);
// Free resources
checkCudaErrors(hipEventDestroy(start_event));
checkCudaErrors(hipEventDestroy(stop_event));
checkCudaErrors(hipSetDevice(gpuid[0]));
checkCudaErrors(hipFree(g0));
checkCudaErrors(hipSetDevice(gpuid[1]));
checkCudaErrors(hipFree(g1));
}
if (enable_p2p)
{
// Disable peer access (also unregisters memory for non-UVA cases)
printf("Disabling peer access...\n");
checkCudaErrors(hipSetDevice(gpuid[0]));
checkCudaErrors(hipDeviceDisablePeerAccess(gpuid[1]));
checkCudaErrors(hipSetDevice(gpuid[1]));
checkCudaErrors(hipDeviceDisablePeerAccess(gpuid[0]));
}
printf("Total time is %.2fs\n", total_time / 1000);
//delete device_handler;
return (EXIT_SUCCESS);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
// This will output the proper CUDA error strings in the event that a CUDA host call returns an error
#define checkCudaErrors(err) __checkCudaErrors (err, __FILE__, __LINE__)
inline void __checkCudaErrors(hipError_t err, const char *file, const int line)
{
if (hipSuccess != err)
{
fprintf(stderr, "%s(%i) : CUDA Runtime API error %d: %s.\n",
file, line, (int)err, hipGetErrorString(err));
exit(EXIT_FAILURE);
}
}
int main(int argc, char **argv)
{
printf("[%s] - Starting...\n", argv[0]);
int gpuid[2] = {1, 2}; // we want to find the first two GPU's that can support P2P
float total_time = 0.0;
bool enable_p2p = true;
if (enable_p2p)
{
// Enable peer access
printf("Enabling peer access between GPU%d and GPU%d...\n", gpuid[0], gpuid[1]);
checkCudaErrors(hipSetDevice(gpuid[0]));
checkCudaErrors(hipDeviceEnablePeerAccess(gpuid[1], 0));
checkCudaErrors(hipSetDevice(gpuid[1]));
checkCudaErrors(hipDeviceEnablePeerAccess(gpuid[0], 0));
}
for (int loop = 0; loop < 100; loop++)
{
// Allocate buffers
const size_t buf_size = 1024 * 1024 * 16 * sizeof(float);
printf("Allocating buffers (%iMB on GPU%d, GPU%d and CPU Host)...\n", int(buf_size / 1024 / 1024), gpuid[0], gpuid[1]);
checkCudaErrors(hipSetDevice(gpuid[0]));
float *g0;
checkCudaErrors(hipMalloc(&g0, buf_size));
checkCudaErrors(hipSetDevice(gpuid[1]));
float *g1;
checkCudaErrors(hipMalloc(&g1, buf_size));
// Create CUDA event handles
hipEvent_t start_event, stop_event;
float time_memcpy;
int eventflags = hipEventBlockingSync;
checkCudaErrors(hipEventCreateWithFlags(&start_event, eventflags));
checkCudaErrors(hipEventCreateWithFlags(&stop_event, eventflags));
// P2P memcopy() benchmark
checkCudaErrors(hipEventRecord(start_event, 0));
for (int i = 0; i < 100; i++)
{
// With UVA we don't need to specify source and target devices, the
// runtime figures this out by itself from the pointers
// Ping-pong copy between GPUs
if (i % 2 == 0)
{
checkCudaErrors(hipMemcpy(g1, g0, buf_size, hipMemcpyDefault));
}
else
{
checkCudaErrors(hipMemcpy(g0, g1, buf_size, hipMemcpyDefault));
}
}
checkCudaErrors(hipEventRecord(stop_event, 0));
checkCudaErrors(hipEventSynchronize(stop_event));
checkCudaErrors(hipEventElapsedTime(&time_memcpy, start_event, stop_event));
total_time += time_memcpy;
printf("hipMemcpyPeer / hipMemcpy (%f ms) between GPU%d and GPU%d: %.2fGB/s\n", time_memcpy, gpuid[0], gpuid[1],
(1.0f / (time_memcpy / 1000.0f)) * ((100.0f * buf_size)) / 1024.0f / 1024.0f / 1024.0f);
// Free resources
checkCudaErrors(hipEventDestroy(start_event));
checkCudaErrors(hipEventDestroy(stop_event));
checkCudaErrors(hipSetDevice(gpuid[0]));
checkCudaErrors(hipFree(g0));
checkCudaErrors(hipSetDevice(gpuid[1]));
checkCudaErrors(hipFree(g1));
}
if (enable_p2p)
{
// Disable peer access (also unregisters memory for non-UVA cases)
printf("Disabling peer access...\n");
checkCudaErrors(hipSetDevice(gpuid[0]));
checkCudaErrors(hipDeviceDisablePeerAccess(gpuid[1]));
checkCudaErrors(hipSetDevice(gpuid[1]));
checkCudaErrors(hipDeviceDisablePeerAccess(gpuid[0]));
}
printf("Total time is %.2fs\n", total_time / 1000);
//delete device_handler;
return (EXIT_SUCCESS);
} | .text
.file "testP2P.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x447a0000 # float 1000
.LCPI0_1:
.long 0x3f800000 # float 1
.LCPI0_2:
.long 0x4fc80000 # float 6.7108864E+9
.LCPI0_3:
.long 0x3a800000 # float 9.765625E-4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $56, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq (%rsi), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $1, %esi
movl $2, %edx
xorl %eax, %eax
callq printf
movl $1, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB0_1
# %bb.3: # %_Z17__checkCudaErrors10hipError_tPKci.exit
movl $2, %edi
xorl %esi, %esi
callq hipDeviceEnablePeerAccess
testl %eax, %eax
jne .LBB0_4
# %bb.5: # %_Z17__checkCudaErrors10hipError_tPKci.exit31
movl $2, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB0_6
# %bb.7: # %_Z17__checkCudaErrors10hipError_tPKci.exit33
movl $1, %edi
xorl %esi, %esi
callq hipDeviceEnablePeerAccess
testl %eax, %eax
jne .LBB0_58
# %bb.8: # %_Z17__checkCudaErrors10hipError_tPKci.exit35.preheader.preheader
xorps %xmm0, %xmm0
movss %xmm0, 12(%rsp) # 4-byte Spill
leaq 32(%rsp), %r14
leaq 24(%rsp), %r15
leaq 16(%rsp), %r12
leaq 52(%rsp), %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_9: # %_Z17__checkCudaErrors10hipError_tPKci.exit35.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_23 Depth 2
movl $.L.str.3, %edi
movl $64, %esi
movl $1, %edx
movl $2, %ecx
xorl %eax, %eax
callq printf
movl $1, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB0_10
# %bb.11: # %_Z17__checkCudaErrors10hipError_tPKci.exit37
# in Loop: Header=BB0_9 Depth=1
movl $67108864, %esi # imm = 0x4000000
leaq 40(%rsp), %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB0_12
# %bb.13: # %_Z17__checkCudaErrors10hipError_tPKci.exit39
# in Loop: Header=BB0_9 Depth=1
movl $2, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB0_14
# %bb.15: # %_Z17__checkCudaErrors10hipError_tPKci.exit41
# in Loop: Header=BB0_9 Depth=1
movl $67108864, %esi # imm = 0x4000000
movq %r14, %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB0_16
# %bb.17: # %_Z17__checkCudaErrors10hipError_tPKci.exit43
# in Loop: Header=BB0_9 Depth=1
movq %r15, %rdi
movl $1, %esi
callq hipEventCreateWithFlags
testl %eax, %eax
jne .LBB0_18
# %bb.19: # %_Z17__checkCudaErrors10hipError_tPKci.exit45
# in Loop: Header=BB0_9 Depth=1
movq %r12, %rdi
movl $1, %esi
callq hipEventCreateWithFlags
testl %eax, %eax
jne .LBB0_20
# %bb.21: # %_Z17__checkCudaErrors10hipError_tPKci.exit47
# in Loop: Header=BB0_9 Depth=1
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB0_26
# %bb.22: # %_Z17__checkCudaErrors10hipError_tPKci.exit49.preheader.preheader
# in Loop: Header=BB0_9 Depth=1
xorl %ebx, %ebx
jmp .LBB0_23
.p2align 4, 0x90
.LBB0_46: # in Loop: Header=BB0_23 Depth=2
movq 40(%rsp), %rdi
movq 32(%rsp), %rsi
movl $67108864, %edx # imm = 0x4000000
movl $4, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_47
.LBB0_27: # %_Z17__checkCudaErrors10hipError_tPKci.exit69
# in Loop: Header=BB0_23 Depth=2
incl %ebx
cmpl $100, %ebx
je .LBB0_28
.LBB0_23: # %_Z17__checkCudaErrors10hipError_tPKci.exit49.preheader
# Parent Loop BB0_9 Depth=1
# => This Inner Loop Header: Depth=2
testb $1, %bl
jne .LBB0_46
# %bb.24: # in Loop: Header=BB0_23 Depth=2
movq 32(%rsp), %rdi
movq 40(%rsp), %rsi
movl $67108864, %edx # imm = 0x4000000
movl $4, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB0_27
jmp .LBB0_25
.p2align 4, 0x90
.LBB0_28: # in Loop: Header=BB0_9 Depth=1
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB0_29
# %bb.30: # %_Z17__checkCudaErrors10hipError_tPKci.exit51
# in Loop: Header=BB0_9 Depth=1
movq 16(%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
jne .LBB0_31
# %bb.32: # %_Z17__checkCudaErrors10hipError_tPKci.exit53
# in Loop: Header=BB0_9 Depth=1
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx
movq %r13, %rdi
callq hipEventElapsedTime
testl %eax, %eax
jne .LBB0_33
# %bb.34: # %_Z17__checkCudaErrors10hipError_tPKci.exit55
# in Loop: Header=BB0_9 Depth=1
movss 52(%rsp), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm0
movss %xmm1, 48(%rsp) # 4-byte Spill
divss .LCPI0_0(%rip), %xmm1
movss .LCPI0_1(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
divss %xmm1, %xmm2
mulss .LCPI0_2(%rip), %xmm2
movss .LCPI0_3(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm2
mulss %xmm1, %xmm2
mulss %xmm1, %xmm2
xorps %xmm1, %xmm1
cvtss2sd %xmm2, %xmm1
movl $.L.str.4, %edi
movl $1, %esi
movl $2, %edx
movb $2, %al
callq printf
movq 24(%rsp), %rdi
callq hipEventDestroy
testl %eax, %eax
jne .LBB0_35
# %bb.36: # %_Z17__checkCudaErrors10hipError_tPKci.exit57
# in Loop: Header=BB0_9 Depth=1
movq 16(%rsp), %rdi
callq hipEventDestroy
testl %eax, %eax
jne .LBB0_37
# %bb.38: # %_Z17__checkCudaErrors10hipError_tPKci.exit59
# in Loop: Header=BB0_9 Depth=1
movl $1, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB0_39
# %bb.40: # %_Z17__checkCudaErrors10hipError_tPKci.exit61
# in Loop: Header=BB0_9 Depth=1
movq 40(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB0_41
# %bb.42: # %_Z17__checkCudaErrors10hipError_tPKci.exit63
# in Loop: Header=BB0_9 Depth=1
movl $2, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB0_43
# %bb.44: # %_Z17__checkCudaErrors10hipError_tPKci.exit65
# in Loop: Header=BB0_9 Depth=1
movq 32(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB0_45
# %bb.48: # %_Z17__checkCudaErrors10hipError_tPKci.exit67
# in Loop: Header=BB0_9 Depth=1
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
addss 48(%rsp), %xmm0 # 4-byte Folded Reload
movss %xmm0, 12(%rsp) # 4-byte Spill
incl %ebp
cmpl $100, %ebp
jne .LBB0_9
# %bb.49:
movl $.Lstr, %edi
callq puts@PLT
movl $1, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB0_50
# %bb.51: # %_Z17__checkCudaErrors10hipError_tPKci.exit73
movl $2, %edi
callq hipDeviceDisablePeerAccess
testl %eax, %eax
jne .LBB0_52
# %bb.53: # %_Z17__checkCudaErrors10hipError_tPKci.exit75
movl $2, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB0_54
# %bb.55: # %_Z17__checkCudaErrors10hipError_tPKci.exit77
movl $1, %edi
callq hipDeviceDisablePeerAccess
testl %eax, %eax
jne .LBB0_56
# %bb.57: # %_Z17__checkCudaErrors10hipError_tPKci.exit79
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
divss .LCPI0_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_25:
.cfi_def_cfa_offset 112
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $66, %ecx
jmp .LBB0_2
.LBB0_47:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $70, %ecx
.LBB0_2:
movl %ebp, %r8d
movq %rax, %r9
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB0_26:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $56, %ecx
jmp .LBB0_2
.LBB0_20:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $53, %ecx
jmp .LBB0_2
.LBB0_18:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $52, %ecx
jmp .LBB0_2
.LBB0_16:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $46, %ecx
jmp .LBB0_2
.LBB0_14:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $44, %ecx
jmp .LBB0_2
.LBB0_12:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $43, %ecx
jmp .LBB0_2
.LBB0_10:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $41, %ecx
jmp .LBB0_2
.LBB0_45:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $87, %ecx
jmp .LBB0_2
.LBB0_43:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $86, %ecx
jmp .LBB0_2
.LBB0_41:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $85, %ecx
jmp .LBB0_2
.LBB0_39:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $84, %ecx
jmp .LBB0_2
.LBB0_37:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $83, %ecx
jmp .LBB0_2
.LBB0_35:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $82, %ecx
jmp .LBB0_2
.LBB0_33:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $76, %ecx
jmp .LBB0_2
.LBB0_31:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $75, %ecx
jmp .LBB0_2
.LBB0_29:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $74, %ecx
jmp .LBB0_2
.LBB0_1:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $30, %ecx
jmp .LBB0_2
.LBB0_4:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $31, %ecx
jmp .LBB0_2
.LBB0_6:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $32, %ecx
jmp .LBB0_2
.LBB0_58:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $33, %ecx
jmp .LBB0_2
.LBB0_50:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $95, %ecx
jmp .LBB0_2
.LBB0_52:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $96, %ecx
jmp .LBB0_2
.LBB0_54:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $97, %ecx
jmp .LBB0_2
.LBB0_56:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $98, %ecx
jmp .LBB0_2
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "[%s] - Starting...\n"
.size .L.str, 20
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Enabling peer access between GPU%d and GPU%d...\n"
.size .L.str.1, 49
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/NanXiao/code-for-my-blog/master/2018/06/testP2P/testP2P.hip"
.size .L.str.2, 117
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Allocating buffers (%iMB on GPU%d, GPU%d and CPU Host)...\n"
.size .L.str.3, 59
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "hipMemcpyPeer / hipMemcpy (%f ms) between GPU%d and GPU%d: %.2fGB/s\n"
.size .L.str.4, 69
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Total time is %.2fs\n"
.size .L.str.6, 21
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%s(%i) : CUDA Runtime API error %d: %s.\n"
.size .L.str.7, 41
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Disabling peer access..."
.size .Lstr, 25
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00167661_00000000-6_testP2P.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z17__checkCudaErrors9cudaErrorPKci.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "%s(%i) : CUDA Runtime API error %d: %s.\n"
.section .text._Z17__checkCudaErrors9cudaErrorPKci,"axG",@progbits,_Z17__checkCudaErrors9cudaErrorPKci,comdat
.weak _Z17__checkCudaErrors9cudaErrorPKci
.type _Z17__checkCudaErrors9cudaErrorPKci, @function
_Z17__checkCudaErrors9cudaErrorPKci:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L8
ret
.L8:
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl %edi, %ebx
movq %rsi, %rbp
movl %edx, %r12d
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
movl %ebx, %r9d
movl %r12d, %r8d
movq %rbp, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z17__checkCudaErrors9cudaErrorPKci, .-_Z17__checkCudaErrors9cudaErrorPKci
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "[%s] - Starting...\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Enabling peer access between GPU%d and GPU%d...\n"
.align 8
.LC4:
.string "/home/ubuntu/Datasets/stackv2/train-structured/NanXiao/code-for-my-blog/master/2018/06/testP2P/testP2P.cu"
.align 8
.LC5:
.string "Allocating buffers (%iMB on GPU%d, GPU%d and CPU Host)...\n"
.align 8
.LC10:
.string "cudaMemcpyPeer / cudaMemcpy (%f ms) between GPU%d and GPU%d: %.2fGB/s\n"
.section .rodata.str1.1
.LC11:
.string "Disabling peer access...\n"
.LC12:
.string "Total time is %.2fs\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq (%rsi), %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $2, %ecx
movl $1, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call cudaSetDevice@PLT
movl %eax, %edi
movl $28, %edx
leaq .LC4(%rip), %rbx
movq %rbx, %rsi
call _Z17__checkCudaErrors9cudaErrorPKci
movl $0, %esi
movl $2, %edi
call cudaDeviceEnablePeerAccess@PLT
movl %eax, %edi
movl $29, %edx
movq %rbx, %rsi
call _Z17__checkCudaErrors9cudaErrorPKci
movl $2, %edi
call cudaSetDevice@PLT
movl %eax, %edi
movl $30, %edx
movq %rbx, %rsi
call _Z17__checkCudaErrors9cudaErrorPKci
movl $0, %esi
movl $1, %edi
call cudaDeviceEnablePeerAccess@PLT
movl %eax, %edi
movl $31, %edx
movq %rbx, %rsi
call _Z17__checkCudaErrors9cudaErrorPKci
movl $100, %r12d
movl $0x00000000, %r13d
jmp .L28
.L46:
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 104
pushq %rax
.cfi_def_cfa_offset 112
movl %ebx, %r9d
movl $39, %r8d
leaq .LC4(%rip), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L47:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 104
pushq %rax
.cfi_def_cfa_offset 112
movl %ebx, %r9d
movl $41, %r8d
leaq .LC4(%rip), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L48:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 104
pushq %rax
.cfi_def_cfa_offset 112
movl %ebx, %r9d
movl $42, %r8d
leaq .LC4(%rip), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L49:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 104
pushq %rax
.cfi_def_cfa_offset 112
movl %ebx, %r9d
movl $44, %r8d
leaq .LC4(%rip), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L50:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 104
pushq %rax
.cfi_def_cfa_offset 112
movl %ebx, %r9d
movl $50, %r8d
leaq .LC4(%rip), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L51:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 104
pushq %rax
.cfi_def_cfa_offset 112
movl %ebx, %r9d
movl $51, %r8d
leaq .LC4(%rip), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L52:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 104
pushq %rax
.cfi_def_cfa_offset 112
movl %ebx, %r9d
movl $54, %r8d
leaq .LC4(%rip), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L17:
.cfi_restore_state
movl $4, %ecx
movl $67108864, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L34
.L18:
addl $1, %ebx
cmpl $100, %ebx
je .L35
.L16:
testb $1, %bl
jne .L17
movl $4, %ecx
movl $67108864, %edx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebp
testl %eax, %eax
je .L18
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 104
pushq %rax
.cfi_def_cfa_offset 112
movl %ebp, %r9d
movl $64, %r8d
leaq .LC4(%rip), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L34:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 104
pushq %rax
.cfi_def_cfa_offset 112
movl %ebp, %r9d
movl $68, %r8d
leaq .LC4(%rip), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L35:
.cfi_restore_state
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L36
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L37
leaq 4(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L38
movss 4(%rsp), %xmm0
movd %r13d, %xmm3
addss %xmm0, %xmm3
movd %xmm3, %r13d
movaps %xmm0, %xmm2
divss .LC6(%rip), %xmm2
movss .LC7(%rip), %xmm1
divss %xmm2, %xmm1
mulss .LC8(%rip), %xmm1
mulss .LC9(%rip), %xmm1
mulss .LC9(%rip), %xmm1
mulss .LC9(%rip), %xmm1
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $2, %ecx
movl $1, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L39
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L40
movl $1, %edi
call cudaSetDevice@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L41
movq 8(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L42
movl $2, %edi
call cudaSetDevice@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L43
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L44
subl $1, %r12d
je .L45
.L28:
movl $2, %r8d
movl $1, %ecx
movl $64, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call cudaSetDevice@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L46
leaq 8(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L47
movl $2, %edi
call cudaSetDevice@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L48
leaq 16(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L49
leaq 24(%rsp), %rdi
movl $1, %esi
call cudaEventCreateWithFlags@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L50
leaq 32(%rsp), %rdi
movl $1, %esi
call cudaEventCreateWithFlags@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L51
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L52
movl $0, %ebx
jmp .L16
.L36:
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 104
pushq %rax
.cfi_def_cfa_offset 112
movl %ebx, %r9d
movl $72, %r8d
leaq .LC4(%rip), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L37:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 104
pushq %rax
.cfi_def_cfa_offset 112
movl %ebx, %r9d
movl $73, %r8d
leaq .LC4(%rip), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L38:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 104
pushq %rax
.cfi_def_cfa_offset 112
movl %ebx, %r9d
movl $74, %r8d
leaq .LC4(%rip), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L39:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 104
pushq %rax
.cfi_def_cfa_offset 112
movl %ebx, %r9d
movl $80, %r8d
leaq .LC4(%rip), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L40:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 104
pushq %rax
.cfi_def_cfa_offset 112
movl %ebx, %r9d
movl $81, %r8d
leaq .LC4(%rip), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L41:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 104
pushq %rax
.cfi_def_cfa_offset 112
movl %ebx, %r9d
movl $82, %r8d
leaq .LC4(%rip), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L42:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 104
pushq %rax
.cfi_def_cfa_offset 112
movl %ebx, %r9d
movl $83, %r8d
leaq .LC4(%rip), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L43:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 104
pushq %rax
.cfi_def_cfa_offset 112
movl %ebx, %r9d
movl $84, %r8d
leaq .LC4(%rip), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L44:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 104
pushq %rax
.cfi_def_cfa_offset 112
movl %ebx, %r9d
movl $85, %r8d
leaq .LC4(%rip), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L45:
.cfi_restore_state
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call cudaSetDevice@PLT
movl %eax, %edi
movl $93, %edx
leaq .LC4(%rip), %rbx
movq %rbx, %rsi
call _Z17__checkCudaErrors9cudaErrorPKci
movl $2, %edi
call cudaDeviceDisablePeerAccess@PLT
movl %eax, %edi
movl $94, %edx
movq %rbx, %rsi
call _Z17__checkCudaErrors9cudaErrorPKci
movl $2, %edi
call cudaSetDevice@PLT
movl %eax, %edi
movl $95, %edx
movq %rbx, %rsi
call _Z17__checkCudaErrors9cudaErrorPKci
movl $1, %edi
call cudaDeviceDisablePeerAccess@PLT
movl %eax, %edi
movl $96, %edx
movq %rbx, %rsi
call _Z17__checkCudaErrors9cudaErrorPKci
movd %r13d, %xmm0
divss .LC6(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L53
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC6:
.long 1148846080
.align 4
.LC7:
.long 1065353216
.align 4
.LC8:
.long 1338507264
.align 4
.LC9:
.long 981467136
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "testP2P.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x447a0000 # float 1000
.LCPI0_1:
.long 0x3f800000 # float 1
.LCPI0_2:
.long 0x4fc80000 # float 6.7108864E+9
.LCPI0_3:
.long 0x3a800000 # float 9.765625E-4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $56, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq (%rsi), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $1, %esi
movl $2, %edx
xorl %eax, %eax
callq printf
movl $1, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB0_1
# %bb.3: # %_Z17__checkCudaErrors10hipError_tPKci.exit
movl $2, %edi
xorl %esi, %esi
callq hipDeviceEnablePeerAccess
testl %eax, %eax
jne .LBB0_4
# %bb.5: # %_Z17__checkCudaErrors10hipError_tPKci.exit31
movl $2, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB0_6
# %bb.7: # %_Z17__checkCudaErrors10hipError_tPKci.exit33
movl $1, %edi
xorl %esi, %esi
callq hipDeviceEnablePeerAccess
testl %eax, %eax
jne .LBB0_58
# %bb.8: # %_Z17__checkCudaErrors10hipError_tPKci.exit35.preheader.preheader
xorps %xmm0, %xmm0
movss %xmm0, 12(%rsp) # 4-byte Spill
leaq 32(%rsp), %r14
leaq 24(%rsp), %r15
leaq 16(%rsp), %r12
leaq 52(%rsp), %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_9: # %_Z17__checkCudaErrors10hipError_tPKci.exit35.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_23 Depth 2
movl $.L.str.3, %edi
movl $64, %esi
movl $1, %edx
movl $2, %ecx
xorl %eax, %eax
callq printf
movl $1, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB0_10
# %bb.11: # %_Z17__checkCudaErrors10hipError_tPKci.exit37
# in Loop: Header=BB0_9 Depth=1
movl $67108864, %esi # imm = 0x4000000
leaq 40(%rsp), %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB0_12
# %bb.13: # %_Z17__checkCudaErrors10hipError_tPKci.exit39
# in Loop: Header=BB0_9 Depth=1
movl $2, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB0_14
# %bb.15: # %_Z17__checkCudaErrors10hipError_tPKci.exit41
# in Loop: Header=BB0_9 Depth=1
movl $67108864, %esi # imm = 0x4000000
movq %r14, %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB0_16
# %bb.17: # %_Z17__checkCudaErrors10hipError_tPKci.exit43
# in Loop: Header=BB0_9 Depth=1
movq %r15, %rdi
movl $1, %esi
callq hipEventCreateWithFlags
testl %eax, %eax
jne .LBB0_18
# %bb.19: # %_Z17__checkCudaErrors10hipError_tPKci.exit45
# in Loop: Header=BB0_9 Depth=1
movq %r12, %rdi
movl $1, %esi
callq hipEventCreateWithFlags
testl %eax, %eax
jne .LBB0_20
# %bb.21: # %_Z17__checkCudaErrors10hipError_tPKci.exit47
# in Loop: Header=BB0_9 Depth=1
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB0_26
# %bb.22: # %_Z17__checkCudaErrors10hipError_tPKci.exit49.preheader.preheader
# in Loop: Header=BB0_9 Depth=1
xorl %ebx, %ebx
jmp .LBB0_23
.p2align 4, 0x90
.LBB0_46: # in Loop: Header=BB0_23 Depth=2
movq 40(%rsp), %rdi
movq 32(%rsp), %rsi
movl $67108864, %edx # imm = 0x4000000
movl $4, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_47
.LBB0_27: # %_Z17__checkCudaErrors10hipError_tPKci.exit69
# in Loop: Header=BB0_23 Depth=2
incl %ebx
cmpl $100, %ebx
je .LBB0_28
.LBB0_23: # %_Z17__checkCudaErrors10hipError_tPKci.exit49.preheader
# Parent Loop BB0_9 Depth=1
# => This Inner Loop Header: Depth=2
testb $1, %bl
jne .LBB0_46
# %bb.24: # in Loop: Header=BB0_23 Depth=2
movq 32(%rsp), %rdi
movq 40(%rsp), %rsi
movl $67108864, %edx # imm = 0x4000000
movl $4, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB0_27
jmp .LBB0_25
.p2align 4, 0x90
.LBB0_28: # in Loop: Header=BB0_9 Depth=1
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB0_29
# %bb.30: # %_Z17__checkCudaErrors10hipError_tPKci.exit51
# in Loop: Header=BB0_9 Depth=1
movq 16(%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
jne .LBB0_31
# %bb.32: # %_Z17__checkCudaErrors10hipError_tPKci.exit53
# in Loop: Header=BB0_9 Depth=1
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx
movq %r13, %rdi
callq hipEventElapsedTime
testl %eax, %eax
jne .LBB0_33
# %bb.34: # %_Z17__checkCudaErrors10hipError_tPKci.exit55
# in Loop: Header=BB0_9 Depth=1
movss 52(%rsp), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm0
movss %xmm1, 48(%rsp) # 4-byte Spill
divss .LCPI0_0(%rip), %xmm1
movss .LCPI0_1(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
divss %xmm1, %xmm2
mulss .LCPI0_2(%rip), %xmm2
movss .LCPI0_3(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm2
mulss %xmm1, %xmm2
mulss %xmm1, %xmm2
xorps %xmm1, %xmm1
cvtss2sd %xmm2, %xmm1
movl $.L.str.4, %edi
movl $1, %esi
movl $2, %edx
movb $2, %al
callq printf
movq 24(%rsp), %rdi
callq hipEventDestroy
testl %eax, %eax
jne .LBB0_35
# %bb.36: # %_Z17__checkCudaErrors10hipError_tPKci.exit57
# in Loop: Header=BB0_9 Depth=1
movq 16(%rsp), %rdi
callq hipEventDestroy
testl %eax, %eax
jne .LBB0_37
# %bb.38: # %_Z17__checkCudaErrors10hipError_tPKci.exit59
# in Loop: Header=BB0_9 Depth=1
movl $1, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB0_39
# %bb.40: # %_Z17__checkCudaErrors10hipError_tPKci.exit61
# in Loop: Header=BB0_9 Depth=1
movq 40(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB0_41
# %bb.42: # %_Z17__checkCudaErrors10hipError_tPKci.exit63
# in Loop: Header=BB0_9 Depth=1
movl $2, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB0_43
# %bb.44: # %_Z17__checkCudaErrors10hipError_tPKci.exit65
# in Loop: Header=BB0_9 Depth=1
movq 32(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB0_45
# %bb.48: # %_Z17__checkCudaErrors10hipError_tPKci.exit67
# in Loop: Header=BB0_9 Depth=1
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
addss 48(%rsp), %xmm0 # 4-byte Folded Reload
movss %xmm0, 12(%rsp) # 4-byte Spill
incl %ebp
cmpl $100, %ebp
jne .LBB0_9
# %bb.49:
movl $.Lstr, %edi
callq puts@PLT
movl $1, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB0_50
# %bb.51: # %_Z17__checkCudaErrors10hipError_tPKci.exit73
movl $2, %edi
callq hipDeviceDisablePeerAccess
testl %eax, %eax
jne .LBB0_52
# %bb.53: # %_Z17__checkCudaErrors10hipError_tPKci.exit75
movl $2, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB0_54
# %bb.55: # %_Z17__checkCudaErrors10hipError_tPKci.exit77
movl $1, %edi
callq hipDeviceDisablePeerAccess
testl %eax, %eax
jne .LBB0_56
# %bb.57: # %_Z17__checkCudaErrors10hipError_tPKci.exit79
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
divss .LCPI0_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_25:
.cfi_def_cfa_offset 112
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $66, %ecx
jmp .LBB0_2
.LBB0_47:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $70, %ecx
.LBB0_2:
movl %ebp, %r8d
movq %rax, %r9
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB0_26:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $56, %ecx
jmp .LBB0_2
.LBB0_20:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $53, %ecx
jmp .LBB0_2
.LBB0_18:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $52, %ecx
jmp .LBB0_2
.LBB0_16:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $46, %ecx
jmp .LBB0_2
.LBB0_14:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $44, %ecx
jmp .LBB0_2
.LBB0_12:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $43, %ecx
jmp .LBB0_2
.LBB0_10:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $41, %ecx
jmp .LBB0_2
.LBB0_45:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $87, %ecx
jmp .LBB0_2
.LBB0_43:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $86, %ecx
jmp .LBB0_2
.LBB0_41:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $85, %ecx
jmp .LBB0_2
.LBB0_39:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $84, %ecx
jmp .LBB0_2
.LBB0_37:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $83, %ecx
jmp .LBB0_2
.LBB0_35:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $82, %ecx
jmp .LBB0_2
.LBB0_33:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $76, %ecx
jmp .LBB0_2
.LBB0_31:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $75, %ecx
jmp .LBB0_2
.LBB0_29:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $74, %ecx
jmp .LBB0_2
.LBB0_1:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $30, %ecx
jmp .LBB0_2
.LBB0_4:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $31, %ecx
jmp .LBB0_2
.LBB0_6:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $32, %ecx
jmp .LBB0_2
.LBB0_58:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $33, %ecx
jmp .LBB0_2
.LBB0_50:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $95, %ecx
jmp .LBB0_2
.LBB0_52:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $96, %ecx
jmp .LBB0_2
.LBB0_54:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $97, %ecx
jmp .LBB0_2
.LBB0_56:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $98, %ecx
jmp .LBB0_2
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "[%s] - Starting...\n"
.size .L.str, 20
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Enabling peer access between GPU%d and GPU%d...\n"
.size .L.str.1, 49
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/NanXiao/code-for-my-blog/master/2018/06/testP2P/testP2P.hip"
.size .L.str.2, 117
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Allocating buffers (%iMB on GPU%d, GPU%d and CPU Host)...\n"
.size .L.str.3, 59
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "hipMemcpyPeer / hipMemcpy (%f ms) between GPU%d and GPU%d: %.2fGB/s\n"
.size .L.str.4, 69
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Total time is %.2fs\n"
.size .L.str.6, 21
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%s(%i) : CUDA Runtime API error %d: %s.\n"
.size .L.str.7, 41
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Disabling peer access..."
.size .Lstr, 25
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <chrono>
#include <cmath>
#include <cstdio>
#include <cstdlib>
#include <cuda_runtime.h>
#include <iomanip>
#include <iostream>
// helper for time measurement
typedef std::chrono::duration<double, std::milli> d_ms;
const auto &now = std::chrono::high_resolution_clock::now;
// Define Error Checking Macro
#define CU_CHK(ERRORCODE) \
{ \
cudaError_t error = ERRORCODE; \
if (error != 0) { \
std::cerr << cudaGetErrorName(error) << ": " \
<< cudaGetErrorString(error) << " at " << __FILE__ << ":" \
<< __LINE__ << "\n"; \
} \
}
// Constants
const static int DEFAULT_NUM_ELEMENTS = 1024;
const static int DEFAULT_NUM_ITERATIONS = 5;
const static int DEFAULT_BLOCK_DIM = 128;
// Structures
struct StencilArray_t {
float *array;
float *tmp_array;
int size; // size == width == height
};
// Function Prototypes
void writeToFile(float *matrix, const char *name, int size);
// Stencil Code Kernel for the speed calculation
extern void simpleStencil_Kernel_Wrapper(int gridSize, int blockSize, int size,
float *grid_old, float *grid_new);
extern void optStencil_Kernel_Wrapper(int gridSize, int blockSize, int shm_size,
int size, float *grid_old,
float *grid_new);
// Main
int main(int argc, char *argv[]) {
// Process Arguments
if (argc < 2 or std::string(argv[1]) == "-h") {
std::cout << "Usage:\n\t" << argv[0] << " <problemsize> [iterations] [result.pgm]\n";
return 1;
}
int numElements = 0;
numElements = std::stoi(argv[1]);
numElements = numElements > 0 ? numElements : DEFAULT_NUM_ELEMENTS;
int numIterations = 0;
if (argc > 2)
numIterations = std::stoi(argv[2]);
numIterations = numIterations != 0 ? numIterations : DEFAULT_NUM_ITERATIONS;
// Allocate Memory
// Host Memory
StencilArray_t h_array;
h_array.size = numElements;
// Pinned Memory
CU_CHK(cudaMallocHost(
&(h_array.array),
static_cast<size_t>(h_array.size * h_array.size * sizeof(float))));
CU_CHK(cudaMallocHost(
&(h_array.tmp_array),
static_cast<size_t>(h_array.size * h_array.size * sizeof(float))));
// Init Particles
// srand(static_cast<unsigned>(time(0)));
srand(0); // Always the same random numbers
for (int i = 0; i < h_array.size; i++) {
for (int j = 0; j < h_array.size; j++) {
if (i == 0)
h_array.array[i + h_array.size * j] = 127;
else if (i > h_array.size / 4 && i < h_array.size * 3 / 4 &&
j > h_array.size / 4 && j < h_array.size * 3 / 4)
h_array.array[i + h_array.size * j] = 100;
else
h_array.array[i + h_array.size * j] = 0;
}
}
// Device Memory
StencilArray_t d_array;
d_array.size = h_array.size;
CU_CHK(cudaMalloc(
&(d_array.array),
static_cast<size_t>(d_array.size * d_array.size * sizeof(float))));
CU_CHK(cudaMalloc(
&(d_array.tmp_array),
static_cast<size_t>(d_array.size * d_array.size * sizeof(float))));
// Copy Data to the Device
auto t1 = now();
CU_CHK(cudaMemcpy(
d_array.array, h_array.array,
static_cast<size_t>(d_array.size * d_array.size * sizeof(float)),
cudaMemcpyHostToDevice));
CU_CHK(cudaMemcpy(
d_array.tmp_array, h_array.array,
static_cast<size_t>(d_array.size * d_array.size * sizeof(float)),
cudaMemcpyHostToDevice));
auto t2 = now();
// Block Dimension / Threads per Block
int block_dim = DEFAULT_BLOCK_DIM;
#ifdef OPT_KERNEL
std::cout << "Using optimized Kernel\n";
#endif
int grid_dim = ceil(static_cast<float>(d_array.size) /
static_cast<float>(block_dim - 2));
std::cout << "Computing grid with " << d_array.size << "x" << d_array.size
<< " elements and " << numIterations << " iterations\n";
std::cout << "Launch kernel with " << grid_dim << " blocks and " << block_dim
<< " threads per block\n";
auto t3 = now();
for (int i = 0; i < numIterations; i++) {
#ifdef OPT_KERNEL
optStencil_Kernel_Wrapper(grid_dim, block_dim,
block_dim * 4 * sizeof(float), d_array.size,
d_array.array, d_array.tmp_array);
#else
simpleStencil_Kernel_Wrapper(grid_dim, block_dim, d_array.size,
d_array.array, d_array.tmp_array);
#endif
float *tmp = d_array.array;
d_array.array = d_array.tmp_array;
d_array.tmp_array = tmp;
}
// Synchronize
cudaDeviceSynchronize();
auto t4 = now();
// Copy Back Data
auto t5 = now();
cudaMemcpy(h_array.array, d_array.array,
static_cast<size_t>(h_array.size * h_array.size * sizeof(float)),
cudaMemcpyDeviceToHost);
auto t6 = now();
if(argc > 3)
writeToFile(h_array.array, argv[3], h_array.size);
// Compute time for copies and kernel
d_ms time_copyH2D = t2 - t1;
d_ms time_kernel = t4 - t3;
d_ms time_copyD2H = t6 - t5;
// Free Memory
cudaFreeHost(h_array.array);
cudaFreeHost(h_array.tmp_array);
cudaFree(d_array.array);
cudaFree(d_array.tmp_array);
// Print Meassurement Results
std::cout << "Results:\n"
<< "H2D \[s], kernel [s], D2H [s]\n"
<< time_copyH2D.count() << ", " << time_kernel.count() << ", "
<< time_copyD2H.count() << "\n";
return 0;
}
void writeToFile(float *grid, const char *name, int size) {
FILE *pFile;
pFile = fopen(name, "w");
int i, j;
fprintf(pFile, "P2 %d %d %d\n", size, size, 127);
for (i = 0; i < size; i++) {
for (j = 0; j < size; j++) {
fprintf(pFile, "%d ", (int)grid[j * size + i]);
}
fprintf(pFile, "\n");
}
fclose(pFile);
return;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <chrono>
#include <cmath>
#include <cstdio>
#include <cstdlib>
#include <cuda_runtime.h>
#include <iomanip>
#include <iostream>
// helper for time measurement
typedef std::chrono::duration<double, std::milli> d_ms;
const auto &now = std::chrono::high_resolution_clock::now;
// Define Error Checking Macro
#define CU_CHK(ERRORCODE) \
{ \
cudaError_t error = ERRORCODE; \
if (error != 0) { \
std::cerr << cudaGetErrorName(error) << ": " \
<< cudaGetErrorString(error) << " at " << __FILE__ << ":" \
<< __LINE__ << "\n"; \
} \
}
// Constants
const static int DEFAULT_NUM_ELEMENTS = 1024;
const static int DEFAULT_NUM_ITERATIONS = 5;
const static int DEFAULT_BLOCK_DIM = 128;
// Structures
struct StencilArray_t {
float *array;
float *tmp_array;
int size; // size == width == height
};
// Function Prototypes
void writeToFile(float *matrix, const char *name, int size);
// Stencil Code Kernel for the speed calculation
extern void simpleStencil_Kernel_Wrapper(int gridSize, int blockSize, int size,
float *grid_old, float *grid_new);
extern void optStencil_Kernel_Wrapper(int gridSize, int blockSize, int shm_size,
int size, float *grid_old,
float *grid_new);
// Main
int main(int argc, char *argv[]) {
// Process Arguments
if (argc < 2 or std::string(argv[1]) == "-h") {
std::cout << "Usage:\n\t" << argv[0] << " <problemsize> [iterations] [result.pgm]\n";
return 1;
}
int numElements = 0;
numElements = std::stoi(argv[1]);
numElements = numElements > 0 ? numElements : DEFAULT_NUM_ELEMENTS;
int numIterations = 0;
if (argc > 2)
numIterations = std::stoi(argv[2]);
numIterations = numIterations != 0 ? numIterations : DEFAULT_NUM_ITERATIONS;
// Allocate Memory
// Host Memory
StencilArray_t h_array;
h_array.size = numElements;
// Pinned Memory
CU_CHK(cudaMallocHost(
&(h_array.array),
static_cast<size_t>(h_array.size * h_array.size * sizeof(float))));
CU_CHK(cudaMallocHost(
&(h_array.tmp_array),
static_cast<size_t>(h_array.size * h_array.size * sizeof(float))));
// Init Particles
// srand(static_cast<unsigned>(time(0)));
srand(0); // Always the same random numbers
for (int i = 0; i < h_array.size; i++) {
for (int j = 0; j < h_array.size; j++) {
if (i == 0)
h_array.array[i + h_array.size * j] = 127;
else if (i > h_array.size / 4 && i < h_array.size * 3 / 4 &&
j > h_array.size / 4 && j < h_array.size * 3 / 4)
h_array.array[i + h_array.size * j] = 100;
else
h_array.array[i + h_array.size * j] = 0;
}
}
// Device Memory
StencilArray_t d_array;
d_array.size = h_array.size;
CU_CHK(cudaMalloc(
&(d_array.array),
static_cast<size_t>(d_array.size * d_array.size * sizeof(float))));
CU_CHK(cudaMalloc(
&(d_array.tmp_array),
static_cast<size_t>(d_array.size * d_array.size * sizeof(float))));
// Copy Data to the Device
auto t1 = now();
CU_CHK(cudaMemcpy(
d_array.array, h_array.array,
static_cast<size_t>(d_array.size * d_array.size * sizeof(float)),
cudaMemcpyHostToDevice));
CU_CHK(cudaMemcpy(
d_array.tmp_array, h_array.array,
static_cast<size_t>(d_array.size * d_array.size * sizeof(float)),
cudaMemcpyHostToDevice));
auto t2 = now();
// Block Dimension / Threads per Block
int block_dim = DEFAULT_BLOCK_DIM;
#ifdef OPT_KERNEL
std::cout << "Using optimized Kernel\n";
#endif
int grid_dim = ceil(static_cast<float>(d_array.size) /
static_cast<float>(block_dim - 2));
std::cout << "Computing grid with " << d_array.size << "x" << d_array.size
<< " elements and " << numIterations << " iterations\n";
std::cout << "Launch kernel with " << grid_dim << " blocks and " << block_dim
<< " threads per block\n";
auto t3 = now();
for (int i = 0; i < numIterations; i++) {
#ifdef OPT_KERNEL
optStencil_Kernel_Wrapper(grid_dim, block_dim,
block_dim * 4 * sizeof(float), d_array.size,
d_array.array, d_array.tmp_array);
#else
simpleStencil_Kernel_Wrapper(grid_dim, block_dim, d_array.size,
d_array.array, d_array.tmp_array);
#endif
float *tmp = d_array.array;
d_array.array = d_array.tmp_array;
d_array.tmp_array = tmp;
}
// Synchronize
cudaDeviceSynchronize();
auto t4 = now();
// Copy Back Data
auto t5 = now();
cudaMemcpy(h_array.array, d_array.array,
static_cast<size_t>(h_array.size * h_array.size * sizeof(float)),
cudaMemcpyDeviceToHost);
auto t6 = now();
if(argc > 3)
writeToFile(h_array.array, argv[3], h_array.size);
// Compute time for copies and kernel
d_ms time_copyH2D = t2 - t1;
d_ms time_kernel = t4 - t3;
d_ms time_copyD2H = t6 - t5;
// Free Memory
cudaFreeHost(h_array.array);
cudaFreeHost(h_array.tmp_array);
cudaFree(d_array.array);
cudaFree(d_array.tmp_array);
// Print Meassurement Results
std::cout << "Results:\n"
<< "H2D \[s], kernel [s], D2H [s]\n"
<< time_copyH2D.count() << ", " << time_kernel.count() << ", "
<< time_copyD2H.count() << "\n";
return 0;
}
void writeToFile(float *grid, const char *name, int size) {
FILE *pFile;
pFile = fopen(name, "w");
int i, j;
fprintf(pFile, "P2 %d %d %d\n", size, size, 127);
for (i = 0; i < size; i++) {
for (j = 0; j < size; j++) {
fprintf(pFile, "%d ", (int)grid[j * size + i]);
}
fprintf(pFile, "\n");
}
fclose(pFile);
return;
} | .file "tmpxft_000e411a_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4056:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "w"
.LC1:
.string "P2 %d %d %d\n"
.LC2:
.string "%d "
.LC3:
.string "\n"
.text
.globl _Z11writeToFilePfPKci
.type _Z11writeToFilePfPKci, @function
_Z11writeToFilePfPKci:
.LFB4053:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
movq %rsi, %rdi
movl %edx, %r13d
leaq .LC0(%rip), %rsi
call fopen@PLT
movq %rax, %r12
movl $127, %r9d
movl %r13d, %r8d
movl %r13d, %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq %rax, %rdi
movl $0, %eax
call __fprintf_chk@PLT
testl %r13d, %r13d
jle .L4
movslq %r13d, %rax
movq %rax, 24(%rsp)
leaq 0(,%rax,4), %r15
movq $0, 8(%rsp)
leaq .LC2(%rip), %r14
.L5:
movq 16(%rsp), %rax
movq 8(%rsp), %rsi
leaq (%rax,%rsi,4), %rbp
movl $0, %ebx
.L6:
cvttss2sil 0(%rbp), %ecx
movq %r14, %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addl $1, %ebx
addq %r15, %rbp
cmpl %ebx, %r13d
jne .L6
leaq .LC3(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $1, 8(%rsp)
movq 8(%rsp), %rax
movq 24(%rsp), %rdx
cmpq %rdx, %rax
jne .L5
.L4:
movq %r12, %rdi
call fclose@PLT
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4053:
.size _Z11writeToFilePfPKci, .-_Z11writeToFilePfPKci
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4079:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4079:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,"axG",@progbits,_ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,comdat
.weak _ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.type _ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_, @function
_ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_:
.LFB4180:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4180
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r13
movq %rsi, 8(%rsp)
movq %rdx, %rbp
movq %rcx, %r12
movl %r8d, %r14d
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
call __errno_location@PLT
movq %rax, %rbx
movl (%rax), %r15d
movl $0, (%rax)
leaq 16(%rsp), %rsi
movl %r14d, %edx
movq %rbp, %rdi
.LEHB0:
call *%r13
movq 16(%rsp), %rcx
cmpq %rbp, %rcx
je .L25
cmpl $34, (%rbx)
je .L14
movl $2147483648, %edx
addq %rax, %rdx
shrq $32, %rdx
jne .L14
testq %r12, %r12
je .L17
subq %rbp, %rcx
movq %rcx, (%r12)
.L17:
cmpl $0, (%rbx)
jne .L11
movl %r15d, (%rbx)
.L11:
movq 24(%rsp), %rdx
subq %fs:40, %rdx
jne .L26
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L27
movq 8(%rsp), %rdi
call _ZSt24__throw_invalid_argumentPKc@PLT
.L27:
call __stack_chk_fail@PLT
.L14:
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L28
movq 8(%rsp), %rdi
call _ZSt20__throw_out_of_rangePKc@PLT
.LEHE0:
.L23:
endbr64
movq %rax, %rdi
cmpl $0, (%rbx)
jne .L20
movl %r15d, (%rbx)
.L20:
movq 24(%rsp), %rax
subq %fs:40, %rax
je .L21
call __stack_chk_fail@PLT
.L28:
call __stack_chk_fail@PLT
.L21:
.LEHB1:
call _Unwind_Resume@PLT
.LEHE1:
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4180:
.globl __gxx_personality_v0
.section .gcc_except_table._ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,"aG",@progbits,_ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,comdat
.LLSDA4180:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4180-.LLSDACSB4180
.LLSDACSB4180:
.uleb128 .LEHB0-.LFB4180
.uleb128 .LEHE0-.LEHB0
.uleb128 .L23-.LFB4180
.uleb128 0
.uleb128 .LEHB1-.LFB4180
.uleb128 .LEHE1-.LEHB1
.uleb128 0
.uleb128 0
.LLSDACSE4180:
.section .text._ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,"axG",@progbits,_ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,comdat
.size _ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_, .-_ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.section .rodata._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "basic_string: construction from null is not valid"
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC5IS3_EEPKcRKS3_,comdat
.align 2
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, @function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_:
.LFB4421:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 16(%rdi), %r12
movq %r12, (%rdi)
testq %rsi, %rsi
je .L38
movq %rdi, %rbx
movq %rsi, %r13
movq %rsi, %rdi
call strlen@PLT
movq %rax, %rbp
movq %rax, (%rsp)
cmpq $15, %rax
ja .L39
cmpq $1, %rax
jne .L34
movzbl 0(%r13), %eax
movb %al, 16(%rbx)
.L35:
movq (%rsp), %rax
movq %rax, 8(%rbx)
movq (%rbx), %rdx
movb $0, (%rdx,%rax)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L41
leaq .LC4(%rip), %rdi
call _ZSt19__throw_logic_errorPKc@PLT
.L41:
call __stack_chk_fail@PLT
.L39:
movq %rsp, %rsi
movl $0, %edx
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
movq %rax, %r12
movq %rax, (%rbx)
movq (%rsp), %rax
movq %rax, 16(%rbx)
.L33:
movq %rbp, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memcpy@PLT
jmp .L35
.L34:
testq %rax, %rax
je .L35
jmp .L33
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4421:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, .-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.set _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.section .rodata.str1.1
.LC5:
.string "-h"
.LC6:
.string "Usage:\n\t"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string " <problemsize> [iterations] [result.pgm]\n"
.section .rodata.str1.1
.LC8:
.string "stoi"
.LC9:
.string ": "
.LC10:
.string " at "
.section .rodata.str1.8
.align 8
.LC11:
.string "/home/ubuntu/Datasets/stackv2/train-structured/YannickEmonds/gpu-mangrove_exercises/main/benchmarks/time_instrumentation/5p-stencil/main.cu"
.section .rodata.str1.1
.LC12:
.string ":"
.LC17:
.string "Computing grid with "
.LC18:
.string "x"
.LC19:
.string " elements and "
.LC20:
.string " iterations\n"
.LC21:
.string "Launch kernel with "
.LC22:
.string " blocks and "
.LC23:
.string " threads per block\n"
.LC25:
.string "Results:\n"
.LC26:
.string "H2D [s], kernel [s], D2H [s]\n"
.LC27:
.string ", "
.text
.globl main
.type main, @function
main:
.LFB4048:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4048
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %rsi, %r14
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
cmpl $1, %edi
jg .L83
.L68:
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
.LEHB2:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq (%r14), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC7(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $1, %eax
jmp .L42
.L83:
movl %edi, %r13d
leaq 48(%rsp), %rdx
movq 8(%rsi), %rsi
leaq 80(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
movl $0, %ebx
cmpq $2, 88(%rsp)
je .L84
.L44:
leaq 80(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
testb %bl, %bl
jne .L68
leaq 48(%rsp), %rdx
movq 8(%r14), %rsi
leaq 80(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE2:
movl $10, %r8d
movl $0, %ecx
movq 80(%rsp), %rdx
leaq .LC8(%rip), %rsi
movq __isoc23_strtol@GOTPCREL(%rip), %rdi
.LEHB3:
call _ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.LEHE3:
jmp .L85
.L84:
movl $2, %edx
leaq .LC5(%rip), %rsi
movq 80(%rsp), %rdi
call memcmp@PLT
testl %eax, %eax
sete %bl
jmp .L44
.L85:
movl %eax, %ebx
leaq 80(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
testl %ebx, %ebx
jle .L86
.L46:
cmpl $2, %r13d
jle .L72
leaq 48(%rsp), %rdx
movq 16(%r14), %rsi
leaq 80(%rsp), %rdi
.LEHB4:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE4:
movl $10, %r8d
movl $0, %ecx
movq 80(%rsp), %rdx
leaq .LC8(%rip), %rsi
movq __isoc23_strtol@GOTPCREL(%rip), %rdi
.LEHB5:
call _ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.LEHE5:
jmp .L87
.L86:
movl $1024, %ebx
jmp .L46
.L87:
movl %eax, %ebp
leaq 80(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
testl %ebp, %ebp
jne .L47
movl $5, %ebp
jmp .L47
.L72:
movl $5, %ebp
.L47:
movl %ebx, 32(%rsp)
imull %ebx, %ebx
movslq %ebx, %rsi
salq $2, %rsi
leaq 16(%rsp), %rdi
movl $0, %edx
.LEHB6:
call cudaHostAlloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L88
.L48:
movl 32(%rsp), %eax
imull %eax, %eax
movslq %eax, %rsi
salq $2, %rsi
leaq 24(%rsp), %rdi
movl $0, %edx
call cudaHostAlloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L89
.L49:
movl $0, %edi
call srand@PLT
movl 32(%rsp), %eax
movl $0, %esi
testl %eax, %eax
jle .L51
movss .LC13(%rip), %xmm0
movss .LC14(%rip), %xmm1
jmp .L50
.L88:
movl %eax, %edi
call cudaGetErrorName@PLT
movq %rax, %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC9(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %r12
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC10(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC11(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC12(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $68, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L48
.L89:
movl %eax, %edi
call cudaGetErrorName@PLT
movq %rax, %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC9(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %r12
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC10(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC11(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC12(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $71, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L49
.L52:
leal 3(%rax), %edx
testl %eax, %eax
cmovns %eax, %edx
sarl $2, %edx
cmpl %esi, %edx
jge .L54
leal (%rax,%rax,2), %r8d
leal 3(%r8), %edi
testl %r8d, %r8d
cmovns %r8d, %edi
sarl $2, %edi
cmpl %esi, %edi
setg %r8b
cmpl %ecx, %edx
setl %dl
testb %dl, %r8b
je .L54
cmpl %ecx, %edi
jg .L90
.L54:
imull %ecx, %eax
addl %esi, %eax
cltq
movq 16(%rsp), %rdx
movl $0x00000000, (%rdx,%rax,4)
.L53:
addl $1, %ecx
movl 32(%rsp), %eax
cmpl %ecx, %eax
jle .L56
.L55:
testl %esi, %esi
jne .L52
imull %ecx, %eax
cltq
movq 16(%rsp), %rdx
movss %xmm0, (%rdx,%rax,4)
jmp .L53
.L90:
imull %ecx, %eax
addl %esi, %eax
cltq
movq 16(%rsp), %rdx
movss %xmm1, (%rdx,%rax,4)
jmp .L53
.L56:
addl $1, %esi
movl 32(%rsp), %eax
cmpl %esi, %eax
jle .L51
.L50:
movl 32(%rsp), %eax
movl $0, %ecx
testl %eax, %eax
jg .L55
jmp .L56
.L51:
movl %eax, 64(%rsp)
imull %eax, %eax
movslq %eax, %rsi
salq $2, %rsi
leaq 48(%rsp), %rdi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L91
.L57:
movl 64(%rsp), %eax
imull %eax, %eax
movslq %eax, %rsi
salq $2, %rsi
leaq 56(%rsp), %rdi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L92
.L58:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r15
movl 64(%rsp), %eax
imull %eax, %eax
movslq %eax, %rdx
salq $2, %rdx
movl $1, %ecx
movq 16(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L93
.L59:
movl 64(%rsp), %eax
imull %eax, %eax
movslq %eax, %rdx
salq $2, %rdx
movl $1, %ecx
movq 16(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L94
.L60:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, (%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl 64(%rsp), %xmm0
divss .LC16(%rip), %xmm0
call ceilf@PLT
cvttss2sil %xmm0, %r12d
leaq .LC17(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 64(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC18(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 64(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC19(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebp, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC20(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC21(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r12d, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC22(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $128, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC23(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, 8(%rsp)
testl %ebp, %ebp
jle .L61
movl $0, %ebx
.L62:
movq 56(%rsp), %r8
movq 48(%rsp), %rcx
movl 64(%rsp), %edx
movl $128, %esi
movl %r12d, %edi
call _Z28simpleStencil_Kernel_WrapperiiiPfS_@PLT
movq 48(%rsp), %rax
movq 56(%rsp), %rdx
movq %rdx, 48(%rsp)
movq %rax, 56(%rsp)
addl $1, %ebx
cmpl %ebx, %ebp
jne .L62
.L61:
call cudaDeviceSynchronize@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbp
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
movl 32(%rsp), %eax
imull %eax, %eax
movslq %eax, %rdx
salq $2, %rdx
movl $2, %ecx
movq 48(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r12
cmpl $3, %r13d
jg .L95
.L63:
movq (%rsp), %rax
subq %r15, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
movsd .LC24(%rip), %xmm0
divsd %xmm0, %xmm1
movq %xmm1, %r13
movq 8(%rsp), %rax
subq %rax, %rbp
pxor %xmm1, %xmm1
cvtsi2sdq %rbp, %xmm1
divsd %xmm0, %xmm1
movq %xmm1, %rbp
subq %rbx, %r12
pxor %xmm1, %xmm1
cvtsi2sdq %r12, %xmm1
divsd %xmm0, %xmm1
movq %xmm1, %rbx
movq 16(%rsp), %rdi
call cudaFreeHost@PLT
movq 24(%rsp), %rdi
call cudaFreeHost@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
leaq .LC25(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC26(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r13, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC27(%rip), %r12
movq %r12, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movq %r12, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $0, %eax
.L42:
movq 120(%rsp), %rdx
subq %fs:40, %rdx
jne .L96
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L91:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorName@PLT
movq %rax, %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC9(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %r12
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC10(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC11(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC12(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $93, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L57
.L92:
movl %eax, %edi
call cudaGetErrorName@PLT
movq %rax, %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC9(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %r12
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC10(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC11(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC12(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $96, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L58
.L93:
movl %eax, %edi
call cudaGetErrorName@PLT
movq %rax, %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC9(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %r12
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC10(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC11(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC12(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $102, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L59
.L94:
movl %eax, %edi
call cudaGetErrorName@PLT
movq %rax, %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC9(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %r12
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC10(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC11(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC12(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $106, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L60
.L95:
movq 24(%r14), %rsi
movl 32(%rsp), %edx
movq 16(%rsp), %rdi
call _Z11writeToFilePfPKci
jmp .L63
.L75:
endbr64
movq %rax, %rbx
leaq 80(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
je .L65
call __stack_chk_fail@PLT
.L65:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L76:
endbr64
movq %rax, %rbx
leaq 80(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
je .L67
call __stack_chk_fail@PLT
.L67:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE6:
.L96:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4048:
.section .gcc_except_table,"a",@progbits
.LLSDA4048:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4048-.LLSDACSB4048
.LLSDACSB4048:
.uleb128 .LEHB2-.LFB4048
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB4048
.uleb128 .LEHE3-.LEHB3
.uleb128 .L75-.LFB4048
.uleb128 0
.uleb128 .LEHB4-.LFB4048
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.uleb128 .LEHB5-.LFB4048
.uleb128 .LEHE5-.LEHB5
.uleb128 .L76-.LFB4048
.uleb128 0
.uleb128 .LEHB6-.LFB4048
.uleb128 .LEHE6-.LEHB6
.uleb128 0
.uleb128 0
.LLSDACSE4048:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl now
.section .data.rel.ro,"aw"
.align 8
.type now, @object
.size now, 8
now:
.quad _ZNSt6chrono3_V212system_clock3nowEv
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC13:
.long 1123942400
.align 4
.LC14:
.long 1120403456
.align 4
.LC16:
.long 1123811328
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC24:
.long 0
.long 1093567616
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <chrono>
#include <cmath>
#include <cstdio>
#include <cstdlib>
#include <cuda_runtime.h>
#include <iomanip>
#include <iostream>
// helper for time measurement
typedef std::chrono::duration<double, std::milli> d_ms;
const auto &now = std::chrono::high_resolution_clock::now;
// Define Error Checking Macro
#define CU_CHK(ERRORCODE) \
{ \
cudaError_t error = ERRORCODE; \
if (error != 0) { \
std::cerr << cudaGetErrorName(error) << ": " \
<< cudaGetErrorString(error) << " at " << __FILE__ << ":" \
<< __LINE__ << "\n"; \
} \
}
// Constants
const static int DEFAULT_NUM_ELEMENTS = 1024;
const static int DEFAULT_NUM_ITERATIONS = 5;
const static int DEFAULT_BLOCK_DIM = 128;
// Structures
struct StencilArray_t {
float *array;
float *tmp_array;
int size; // size == width == height
};
// Function Prototypes
void writeToFile(float *matrix, const char *name, int size);
// Stencil Code Kernel for the speed calculation
extern void simpleStencil_Kernel_Wrapper(int gridSize, int blockSize, int size,
float *grid_old, float *grid_new);
extern void optStencil_Kernel_Wrapper(int gridSize, int blockSize, int shm_size,
int size, float *grid_old,
float *grid_new);
// Main
int main(int argc, char *argv[]) {
// Process Arguments
if (argc < 2 or std::string(argv[1]) == "-h") {
std::cout << "Usage:\n\t" << argv[0] << " <problemsize> [iterations] [result.pgm]\n";
return 1;
}
int numElements = 0;
numElements = std::stoi(argv[1]);
numElements = numElements > 0 ? numElements : DEFAULT_NUM_ELEMENTS;
int numIterations = 0;
if (argc > 2)
numIterations = std::stoi(argv[2]);
numIterations = numIterations != 0 ? numIterations : DEFAULT_NUM_ITERATIONS;
// Allocate Memory
// Host Memory
StencilArray_t h_array;
h_array.size = numElements;
// Pinned Memory
CU_CHK(cudaMallocHost(
&(h_array.array),
static_cast<size_t>(h_array.size * h_array.size * sizeof(float))));
CU_CHK(cudaMallocHost(
&(h_array.tmp_array),
static_cast<size_t>(h_array.size * h_array.size * sizeof(float))));
// Init Particles
// srand(static_cast<unsigned>(time(0)));
srand(0); // Always the same random numbers
for (int i = 0; i < h_array.size; i++) {
for (int j = 0; j < h_array.size; j++) {
if (i == 0)
h_array.array[i + h_array.size * j] = 127;
else if (i > h_array.size / 4 && i < h_array.size * 3 / 4 &&
j > h_array.size / 4 && j < h_array.size * 3 / 4)
h_array.array[i + h_array.size * j] = 100;
else
h_array.array[i + h_array.size * j] = 0;
}
}
// Device Memory
StencilArray_t d_array;
d_array.size = h_array.size;
CU_CHK(cudaMalloc(
&(d_array.array),
static_cast<size_t>(d_array.size * d_array.size * sizeof(float))));
CU_CHK(cudaMalloc(
&(d_array.tmp_array),
static_cast<size_t>(d_array.size * d_array.size * sizeof(float))));
// Copy Data to the Device
auto t1 = now();
CU_CHK(cudaMemcpy(
d_array.array, h_array.array,
static_cast<size_t>(d_array.size * d_array.size * sizeof(float)),
cudaMemcpyHostToDevice));
CU_CHK(cudaMemcpy(
d_array.tmp_array, h_array.array,
static_cast<size_t>(d_array.size * d_array.size * sizeof(float)),
cudaMemcpyHostToDevice));
auto t2 = now();
// Block Dimension / Threads per Block
int block_dim = DEFAULT_BLOCK_DIM;
#ifdef OPT_KERNEL
std::cout << "Using optimized Kernel\n";
#endif
int grid_dim = ceil(static_cast<float>(d_array.size) /
static_cast<float>(block_dim - 2));
std::cout << "Computing grid with " << d_array.size << "x" << d_array.size
<< " elements and " << numIterations << " iterations\n";
std::cout << "Launch kernel with " << grid_dim << " blocks and " << block_dim
<< " threads per block\n";
auto t3 = now();
for (int i = 0; i < numIterations; i++) {
#ifdef OPT_KERNEL
optStencil_Kernel_Wrapper(grid_dim, block_dim,
block_dim * 4 * sizeof(float), d_array.size,
d_array.array, d_array.tmp_array);
#else
simpleStencil_Kernel_Wrapper(grid_dim, block_dim, d_array.size,
d_array.array, d_array.tmp_array);
#endif
float *tmp = d_array.array;
d_array.array = d_array.tmp_array;
d_array.tmp_array = tmp;
}
// Synchronize
cudaDeviceSynchronize();
auto t4 = now();
// Copy Back Data
auto t5 = now();
cudaMemcpy(h_array.array, d_array.array,
static_cast<size_t>(h_array.size * h_array.size * sizeof(float)),
cudaMemcpyDeviceToHost);
auto t6 = now();
if(argc > 3)
writeToFile(h_array.array, argv[3], h_array.size);
// Compute time for copies and kernel
d_ms time_copyH2D = t2 - t1;
d_ms time_kernel = t4 - t3;
d_ms time_copyD2H = t6 - t5;
// Free Memory
cudaFreeHost(h_array.array);
cudaFreeHost(h_array.tmp_array);
cudaFree(d_array.array);
cudaFree(d_array.tmp_array);
// Print Meassurement Results
std::cout << "Results:\n"
<< "H2D \[s], kernel [s], D2H [s]\n"
<< time_copyH2D.count() << ", " << time_kernel.count() << ", "
<< time_copyD2H.count() << "\n";
return 0;
}
void writeToFile(float *grid, const char *name, int size) {
FILE *pFile;
pFile = fopen(name, "w");
int i, j;
fprintf(pFile, "P2 %d %d %d\n", size, size, 127);
for (i = 0; i < size; i++) {
for (j = 0; j < size; j++) {
fprintf(pFile, "%d ", (int)grid[j * size + i]);
}
fprintf(pFile, "\n");
}
fclose(pFile);
return;
} | #include <chrono>
#include <cmath>
#include <cstdio>
#include <cstdlib>
#include <hip/hip_runtime.h>
#include <iomanip>
#include <iostream>
// helper for time measurement
typedef std::chrono::duration<double, std::milli> d_ms;
const auto &now = std::chrono::high_resolution_clock::now;
// Define Error Checking Macro
#define CU_CHK(ERRORCODE) \
{ \
hipError_t error = ERRORCODE; \
if (error != 0) { \
std::cerr << hipGetErrorName(error) << ": " \
<< hipGetErrorString(error) << " at " << __FILE__ << ":" \
<< __LINE__ << "\n"; \
} \
}
// Constants
const static int DEFAULT_NUM_ELEMENTS = 1024;
const static int DEFAULT_NUM_ITERATIONS = 5;
const static int DEFAULT_BLOCK_DIM = 128;
// Structures
struct StencilArray_t {
float *array;
float *tmp_array;
int size; // size == width == height
};
// Function Prototypes
void writeToFile(float *matrix, const char *name, int size);
// Stencil Code Kernel for the speed calculation
extern void simpleStencil_Kernel_Wrapper(int gridSize, int blockSize, int size,
float *grid_old, float *grid_new);
extern void optStencil_Kernel_Wrapper(int gridSize, int blockSize, int shm_size,
int size, float *grid_old,
float *grid_new);
// Main
int main(int argc, char *argv[]) {
// Process Arguments
if (argc < 2 or std::string(argv[1]) == "-h") {
std::cout << "Usage:\n\t" << argv[0] << " <problemsize> [iterations] [result.pgm]\n";
return 1;
}
int numElements = 0;
numElements = std::stoi(argv[1]);
numElements = numElements > 0 ? numElements : DEFAULT_NUM_ELEMENTS;
int numIterations = 0;
if (argc > 2)
numIterations = std::stoi(argv[2]);
numIterations = numIterations != 0 ? numIterations : DEFAULT_NUM_ITERATIONS;
// Allocate Memory
// Host Memory
StencilArray_t h_array;
h_array.size = numElements;
// Pinned Memory
CU_CHK(hipHostMalloc(
&(h_array.array),
static_cast<size_t>(h_array.size * h_array.size * sizeof(float)), hipHostMallocDefault));
CU_CHK(hipHostMalloc(
&(h_array.tmp_array),
static_cast<size_t>(h_array.size * h_array.size * sizeof(float)), hipHostMallocDefault));
// Init Particles
// srand(static_cast<unsigned>(time(0)));
srand(0); // Always the same random numbers
for (int i = 0; i < h_array.size; i++) {
for (int j = 0; j < h_array.size; j++) {
if (i == 0)
h_array.array[i + h_array.size * j] = 127;
else if (i > h_array.size / 4 && i < h_array.size * 3 / 4 &&
j > h_array.size / 4 && j < h_array.size * 3 / 4)
h_array.array[i + h_array.size * j] = 100;
else
h_array.array[i + h_array.size * j] = 0;
}
}
// Device Memory
StencilArray_t d_array;
d_array.size = h_array.size;
CU_CHK(hipMalloc(
&(d_array.array),
static_cast<size_t>(d_array.size * d_array.size * sizeof(float))));
CU_CHK(hipMalloc(
&(d_array.tmp_array),
static_cast<size_t>(d_array.size * d_array.size * sizeof(float))));
// Copy Data to the Device
auto t1 = now();
CU_CHK(hipMemcpy(
d_array.array, h_array.array,
static_cast<size_t>(d_array.size * d_array.size * sizeof(float)),
hipMemcpyHostToDevice));
CU_CHK(hipMemcpy(
d_array.tmp_array, h_array.array,
static_cast<size_t>(d_array.size * d_array.size * sizeof(float)),
hipMemcpyHostToDevice));
auto t2 = now();
// Block Dimension / Threads per Block
int block_dim = DEFAULT_BLOCK_DIM;
#ifdef OPT_KERNEL
std::cout << "Using optimized Kernel\n";
#endif
int grid_dim = ceil(static_cast<float>(d_array.size) /
static_cast<float>(block_dim - 2));
std::cout << "Computing grid with " << d_array.size << "x" << d_array.size
<< " elements and " << numIterations << " iterations\n";
std::cout << "Launch kernel with " << grid_dim << " blocks and " << block_dim
<< " threads per block\n";
auto t3 = now();
for (int i = 0; i < numIterations; i++) {
#ifdef OPT_KERNEL
optStencil_Kernel_Wrapper(grid_dim, block_dim,
block_dim * 4 * sizeof(float), d_array.size,
d_array.array, d_array.tmp_array);
#else
simpleStencil_Kernel_Wrapper(grid_dim, block_dim, d_array.size,
d_array.array, d_array.tmp_array);
#endif
float *tmp = d_array.array;
d_array.array = d_array.tmp_array;
d_array.tmp_array = tmp;
}
// Synchronize
hipDeviceSynchronize();
auto t4 = now();
// Copy Back Data
auto t5 = now();
hipMemcpy(h_array.array, d_array.array,
static_cast<size_t>(h_array.size * h_array.size * sizeof(float)),
hipMemcpyDeviceToHost);
auto t6 = now();
if(argc > 3)
writeToFile(h_array.array, argv[3], h_array.size);
// Compute time for copies and kernel
d_ms time_copyH2D = t2 - t1;
d_ms time_kernel = t4 - t3;
d_ms time_copyD2H = t6 - t5;
// Free Memory
hipHostFree(h_array.array);
hipHostFree(h_array.tmp_array);
hipFree(d_array.array);
hipFree(d_array.tmp_array);
// Print Meassurement Results
std::cout << "Results:\n"
<< "H2D \[s], kernel [s], D2H [s]\n"
<< time_copyH2D.count() << ", " << time_kernel.count() << ", "
<< time_copyD2H.count() << "\n";
return 0;
}
void writeToFile(float *grid, const char *name, int size) {
FILE *pFile;
pFile = fopen(name, "w");
int i, j;
fprintf(pFile, "P2 %d %d %d\n", size, size, 127);
for (i = 0; i < size; i++) {
for (j = 0; j < size; j++) {
fprintf(pFile, "%d ", (int)grid[j * size + i]);
}
fprintf(pFile, "\n");
}
fclose(pFile);
return;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <chrono>
#include <cmath>
#include <cstdio>
#include <cstdlib>
#include <hip/hip_runtime.h>
#include <iomanip>
#include <iostream>
// helper for time measurement
typedef std::chrono::duration<double, std::milli> d_ms;
const auto &now = std::chrono::high_resolution_clock::now;
// Define Error Checking Macro
#define CU_CHK(ERRORCODE) \
{ \
hipError_t error = ERRORCODE; \
if (error != 0) { \
std::cerr << hipGetErrorName(error) << ": " \
<< hipGetErrorString(error) << " at " << __FILE__ << ":" \
<< __LINE__ << "\n"; \
} \
}
// Constants
const static int DEFAULT_NUM_ELEMENTS = 1024;
const static int DEFAULT_NUM_ITERATIONS = 5;
const static int DEFAULT_BLOCK_DIM = 128;
// Structures
struct StencilArray_t {
float *array;
float *tmp_array;
int size; // size == width == height
};
// Function Prototypes
void writeToFile(float *matrix, const char *name, int size);
// Stencil Code Kernel for the speed calculation
extern void simpleStencil_Kernel_Wrapper(int gridSize, int blockSize, int size,
float *grid_old, float *grid_new);
extern void optStencil_Kernel_Wrapper(int gridSize, int blockSize, int shm_size,
int size, float *grid_old,
float *grid_new);
// Main
int main(int argc, char *argv[]) {
// Process Arguments
if (argc < 2 or std::string(argv[1]) == "-h") {
std::cout << "Usage:\n\t" << argv[0] << " <problemsize> [iterations] [result.pgm]\n";
return 1;
}
int numElements = 0;
numElements = std::stoi(argv[1]);
numElements = numElements > 0 ? numElements : DEFAULT_NUM_ELEMENTS;
int numIterations = 0;
if (argc > 2)
numIterations = std::stoi(argv[2]);
numIterations = numIterations != 0 ? numIterations : DEFAULT_NUM_ITERATIONS;
// Allocate Memory
// Host Memory
StencilArray_t h_array;
h_array.size = numElements;
// Pinned Memory
CU_CHK(hipHostMalloc(
&(h_array.array),
static_cast<size_t>(h_array.size * h_array.size * sizeof(float)), hipHostMallocDefault));
CU_CHK(hipHostMalloc(
&(h_array.tmp_array),
static_cast<size_t>(h_array.size * h_array.size * sizeof(float)), hipHostMallocDefault));
// Init Particles
// srand(static_cast<unsigned>(time(0)));
srand(0); // Always the same random numbers
for (int i = 0; i < h_array.size; i++) {
for (int j = 0; j < h_array.size; j++) {
if (i == 0)
h_array.array[i + h_array.size * j] = 127;
else if (i > h_array.size / 4 && i < h_array.size * 3 / 4 &&
j > h_array.size / 4 && j < h_array.size * 3 / 4)
h_array.array[i + h_array.size * j] = 100;
else
h_array.array[i + h_array.size * j] = 0;
}
}
// Device Memory
StencilArray_t d_array;
d_array.size = h_array.size;
CU_CHK(hipMalloc(
&(d_array.array),
static_cast<size_t>(d_array.size * d_array.size * sizeof(float))));
CU_CHK(hipMalloc(
&(d_array.tmp_array),
static_cast<size_t>(d_array.size * d_array.size * sizeof(float))));
// Copy Data to the Device
auto t1 = now();
CU_CHK(hipMemcpy(
d_array.array, h_array.array,
static_cast<size_t>(d_array.size * d_array.size * sizeof(float)),
hipMemcpyHostToDevice));
CU_CHK(hipMemcpy(
d_array.tmp_array, h_array.array,
static_cast<size_t>(d_array.size * d_array.size * sizeof(float)),
hipMemcpyHostToDevice));
auto t2 = now();
// Block Dimension / Threads per Block
int block_dim = DEFAULT_BLOCK_DIM;
#ifdef OPT_KERNEL
std::cout << "Using optimized Kernel\n";
#endif
int grid_dim = ceil(static_cast<float>(d_array.size) /
static_cast<float>(block_dim - 2));
std::cout << "Computing grid with " << d_array.size << "x" << d_array.size
<< " elements and " << numIterations << " iterations\n";
std::cout << "Launch kernel with " << grid_dim << " blocks and " << block_dim
<< " threads per block\n";
auto t3 = now();
for (int i = 0; i < numIterations; i++) {
#ifdef OPT_KERNEL
optStencil_Kernel_Wrapper(grid_dim, block_dim,
block_dim * 4 * sizeof(float), d_array.size,
d_array.array, d_array.tmp_array);
#else
simpleStencil_Kernel_Wrapper(grid_dim, block_dim, d_array.size,
d_array.array, d_array.tmp_array);
#endif
float *tmp = d_array.array;
d_array.array = d_array.tmp_array;
d_array.tmp_array = tmp;
}
// Synchronize
hipDeviceSynchronize();
auto t4 = now();
// Copy Back Data
auto t5 = now();
hipMemcpy(h_array.array, d_array.array,
static_cast<size_t>(h_array.size * h_array.size * sizeof(float)),
hipMemcpyDeviceToHost);
auto t6 = now();
if(argc > 3)
writeToFile(h_array.array, argv[3], h_array.size);
// Compute time for copies and kernel
d_ms time_copyH2D = t2 - t1;
d_ms time_kernel = t4 - t3;
d_ms time_copyD2H = t6 - t5;
// Free Memory
hipHostFree(h_array.array);
hipHostFree(h_array.tmp_array);
hipFree(d_array.array);
hipFree(d_array.tmp_array);
// Print Meassurement Results
std::cout << "Results:\n"
<< "H2D \[s], kernel [s], D2H [s]\n"
<< time_copyH2D.count() << ", " << time_kernel.count() << ", "
<< time_copyD2H.count() << "\n";
return 0;
}
void writeToFile(float *grid, const char *name, int size) {
FILE *pFile;
pFile = fopen(name, "w");
int i, j;
fprintf(pFile, "P2 %d %d %d\n", size, size, 127);
for (i = 0; i < size; i++) {
for (j = 0; j < size; j++) {
fprintf(pFile, "%d ", (int)grid[j * size + i]);
}
fprintf(pFile, "\n");
}
fclose(pFile);
return;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <chrono>
#include <cmath>
#include <cstdio>
#include <cstdlib>
#include <hip/hip_runtime.h>
#include <iomanip>
#include <iostream>
// helper for time measurement
typedef std::chrono::duration<double, std::milli> d_ms;
const auto &now = std::chrono::high_resolution_clock::now;
// Define Error Checking Macro
#define CU_CHK(ERRORCODE) \
{ \
hipError_t error = ERRORCODE; \
if (error != 0) { \
std::cerr << hipGetErrorName(error) << ": " \
<< hipGetErrorString(error) << " at " << __FILE__ << ":" \
<< __LINE__ << "\n"; \
} \
}
// Constants
const static int DEFAULT_NUM_ELEMENTS = 1024;
const static int DEFAULT_NUM_ITERATIONS = 5;
const static int DEFAULT_BLOCK_DIM = 128;
// Structures
struct StencilArray_t {
float *array;
float *tmp_array;
int size; // size == width == height
};
// Function Prototypes
void writeToFile(float *matrix, const char *name, int size);
// Stencil Code Kernel for the speed calculation
extern void simpleStencil_Kernel_Wrapper(int gridSize, int blockSize, int size,
float *grid_old, float *grid_new);
extern void optStencil_Kernel_Wrapper(int gridSize, int blockSize, int shm_size,
int size, float *grid_old,
float *grid_new);
// Main
int main(int argc, char *argv[]) {
// Process Arguments
if (argc < 2 or std::string(argv[1]) == "-h") {
std::cout << "Usage:\n\t" << argv[0] << " <problemsize> [iterations] [result.pgm]\n";
return 1;
}
int numElements = 0;
numElements = std::stoi(argv[1]);
numElements = numElements > 0 ? numElements : DEFAULT_NUM_ELEMENTS;
int numIterations = 0;
if (argc > 2)
numIterations = std::stoi(argv[2]);
numIterations = numIterations != 0 ? numIterations : DEFAULT_NUM_ITERATIONS;
// Allocate Memory
// Host Memory
StencilArray_t h_array;
h_array.size = numElements;
// Pinned Memory
CU_CHK(hipHostMalloc(
&(h_array.array),
static_cast<size_t>(h_array.size * h_array.size * sizeof(float)), hipHostMallocDefault));
CU_CHK(hipHostMalloc(
&(h_array.tmp_array),
static_cast<size_t>(h_array.size * h_array.size * sizeof(float)), hipHostMallocDefault));
// Init Particles
// srand(static_cast<unsigned>(time(0)));
srand(0); // Always the same random numbers
for (int i = 0; i < h_array.size; i++) {
for (int j = 0; j < h_array.size; j++) {
if (i == 0)
h_array.array[i + h_array.size * j] = 127;
else if (i > h_array.size / 4 && i < h_array.size * 3 / 4 &&
j > h_array.size / 4 && j < h_array.size * 3 / 4)
h_array.array[i + h_array.size * j] = 100;
else
h_array.array[i + h_array.size * j] = 0;
}
}
// Device Memory
StencilArray_t d_array;
d_array.size = h_array.size;
CU_CHK(hipMalloc(
&(d_array.array),
static_cast<size_t>(d_array.size * d_array.size * sizeof(float))));
CU_CHK(hipMalloc(
&(d_array.tmp_array),
static_cast<size_t>(d_array.size * d_array.size * sizeof(float))));
// Copy Data to the Device
auto t1 = now();
CU_CHK(hipMemcpy(
d_array.array, h_array.array,
static_cast<size_t>(d_array.size * d_array.size * sizeof(float)),
hipMemcpyHostToDevice));
CU_CHK(hipMemcpy(
d_array.tmp_array, h_array.array,
static_cast<size_t>(d_array.size * d_array.size * sizeof(float)),
hipMemcpyHostToDevice));
auto t2 = now();
// Block Dimension / Threads per Block
int block_dim = DEFAULT_BLOCK_DIM;
#ifdef OPT_KERNEL
std::cout << "Using optimized Kernel\n";
#endif
int grid_dim = ceil(static_cast<float>(d_array.size) /
static_cast<float>(block_dim - 2));
std::cout << "Computing grid with " << d_array.size << "x" << d_array.size
<< " elements and " << numIterations << " iterations\n";
std::cout << "Launch kernel with " << grid_dim << " blocks and " << block_dim
<< " threads per block\n";
auto t3 = now();
for (int i = 0; i < numIterations; i++) {
#ifdef OPT_KERNEL
optStencil_Kernel_Wrapper(grid_dim, block_dim,
block_dim * 4 * sizeof(float), d_array.size,
d_array.array, d_array.tmp_array);
#else
simpleStencil_Kernel_Wrapper(grid_dim, block_dim, d_array.size,
d_array.array, d_array.tmp_array);
#endif
float *tmp = d_array.array;
d_array.array = d_array.tmp_array;
d_array.tmp_array = tmp;
}
// Synchronize
hipDeviceSynchronize();
auto t4 = now();
// Copy Back Data
auto t5 = now();
hipMemcpy(h_array.array, d_array.array,
static_cast<size_t>(h_array.size * h_array.size * sizeof(float)),
hipMemcpyDeviceToHost);
auto t6 = now();
if(argc > 3)
writeToFile(h_array.array, argv[3], h_array.size);
// Compute time for copies and kernel
d_ms time_copyH2D = t2 - t1;
d_ms time_kernel = t4 - t3;
d_ms time_copyD2H = t6 - t5;
// Free Memory
hipHostFree(h_array.array);
hipHostFree(h_array.tmp_array);
hipFree(d_array.array);
hipFree(d_array.tmp_array);
// Print Meassurement Results
std::cout << "Results:\n"
<< "H2D \[s], kernel [s], D2H [s]\n"
<< time_copyH2D.count() << ", " << time_kernel.count() << ", "
<< time_copyD2H.count() << "\n";
return 0;
}
void writeToFile(float *grid, const char *name, int size) {
FILE *pFile;
pFile = fopen(name, "w");
int i, j;
fprintf(pFile, "P2 %d %d %d\n", size, size, 127);
for (i = 0; i < size; i++) {
for (j = 0; j < size; j++) {
fprintf(pFile, "%d ", (int)grid[j * size + i]);
}
fprintf(pFile, "\n");
}
fclose(pFile);
return;
} | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x42fc0000 # float 126
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI0_1:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbp
movl %edi, %r13d
movb $1, %bl
cmpl $2, %edi
jl .LBB0_12
# %bb.1:
movq 8(%rbp), %rbx
leaq 96(%rsp), %rax
movq %rax, 80(%rsp)
testq %rbx, %rbx
je .LBB0_128
# %bb.2:
movq %rbx, %rdi
callq strlen
movq %rax, %r14
cmpq $16, %rax
jb .LBB0_6
# %bb.3:
testq %r14, %r14
js .LBB0_135
# %bb.4:
movq %r14, %rdi
incq %rdi
js .LBB0_123
# %bb.5: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i
callq _Znwm
movq %rax, 80(%rsp)
movq %r14, 96(%rsp)
.LBB0_6:
testq %r14, %r14
je .LBB0_10
# %bb.7:
movq 80(%rsp), %rdi
cmpq $1, %r14
jne .LBB0_9
# %bb.8:
movzbl (%rbx), %eax
movb %al, (%rdi)
jmp .LBB0_10
.LBB0_9:
movq %rbx, %rsi
movq %r14, %rdx
callq memcpy@PLT
.LBB0_10: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit
movq %r14, 88(%rsp)
movq 80(%rsp), %rax
movb $0, (%rax,%r14)
movq 88(%rsp), %rdx
cmpq $2, %rdx
jne .LBB0_15
# %bb.11:
movq 80(%rsp), %rdi
movl $.L.str, %esi
callq bcmp@PLT
testl %eax, %eax
sete %bl
.LBB0_12: # %_ZSteqIcSt11char_traitsIcESaIcEEbRKNSt7__cxx1112basic_stringIT_T0_T1_EEPKS5_.exit
cmpl $2, %r13d
jl .LBB0_16
.LBB0_13: # %.critedge
movq 80(%rsp), %rdi
leaq 96(%rsp), %rax
cmpq %rax, %rdi
je .LBB0_16
# %bb.14: # %.critedge.i.i
callq _ZdlPv
jmp .LBB0_16
.LBB0_15:
xorl %ebx, %ebx
cmpl $2, %r13d
jge .LBB0_13
.LBB0_16: # %.critedge103
testb %bl, %bl
je .LBB0_19
# %bb.17:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbp), %rbx
testq %rbx, %rbx
je .LBB0_28
# %bb.18:
movq %rbx, %rdi
callq strlen
movl $_ZSt4cout, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB0_29
.LBB0_19:
movq 8(%rbp), %rbx
leaq 24(%rsp), %rax
movq %rax, 8(%rsp)
testq %rbx, %rbx
je .LBB0_129
# %bb.20:
movq %rbx, %rdi
callq strlen
movq %rax, %r14
cmpq $16, %rax
jb .LBB0_25
# %bb.21:
testq %r14, %r14
js .LBB0_136
# %bb.22:
movq %r14, %rdi
incq %rdi
js .LBB0_124
# %bb.23: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i111
.Ltmp0:
callq _Znwm
.Ltmp1:
# %bb.24: # %.noexc117
movq %rax, 8(%rsp)
movq %r14, 24(%rsp)
.LBB0_25:
testq %r14, %r14
je .LBB0_31
# %bb.26:
movq 8(%rsp), %rdi
cmpq $1, %r14
jne .LBB0_30
# %bb.27:
movzbl (%rbx), %eax
movb %al, (%rdi)
jmp .LBB0_31
.LBB0_28:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB0_29: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $41, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $1, %eax
jmp .LBB0_122
.LBB0_30:
movq %rbx, %rsi
movq %r14, %rdx
callq memcpy@PLT
.LBB0_31: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit118
movq %r14, 16(%rsp)
movq 8(%rsp), %rax
movb $0, (%rax,%r14)
movq 8(%rsp), %r15
callq __errno_location
movq %rax, %r14
movl (%rax), %r12d
movl $0, (%rax)
leaq 40(%rsp), %rsi
movq %r15, %rdi
movl $10, %edx
callq __isoc23_strtol
cmpq %r15, 40(%rsp)
je .LBB0_131
# %bb.32:
movq %rax, %rbx
movslq %ebx, %rax
cmpq %rbx, %rax
jne .LBB0_133
# %bb.33:
movl (%r14), %eax
cmpl $34, %eax
je .LBB0_133
# %bb.34:
testl %eax, %eax
jne .LBB0_36
# %bb.35:
movl %r12d, (%r14)
.LBB0_36: # %_ZNSt7__cxx114stoiERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEPmi.exit
movq 8(%rsp), %rdi
leaq 24(%rsp), %r12
cmpq %r12, %rdi
je .LBB0_38
# %bb.37: # %.critedge.i.i120
callq _ZdlPv
.LBB0_38: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit122
testl %ebx, %ebx
movl $1024, %r15d # imm = 0x400
cmovgl %ebx, %r15d
xorl %ebx, %ebx
cmpl $3, %r13d
jl .LBB0_56
# %bb.39:
movq 16(%rbp), %rbx
movq %r12, 8(%rsp)
testq %rbx, %rbx
je .LBB0_138
# %bb.40:
movq %rbx, %rdi
callq strlen
movq %rax, %r12
cmpq $16, %rax
jb .LBB0_45
# %bb.41:
testq %r12, %r12
js .LBB0_144
# %bb.42:
movq %r12, %rdi
incq %rdi
js .LBB0_126
# %bb.43: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i123
.Ltmp2:
callq _Znwm
.Ltmp3:
# %bb.44: # %.noexc129
movq %rax, 8(%rsp)
movq %r12, 24(%rsp)
.LBB0_45:
testq %r12, %r12
je .LBB0_49
# %bb.46:
movq 8(%rsp), %rdi
cmpq $1, %r12
jne .LBB0_48
# %bb.47:
movzbl (%rbx), %eax
movb %al, (%rdi)
jmp .LBB0_49
.LBB0_48:
movq %rbx, %rsi
movq %r12, %rdx
callq memcpy@PLT
.LBB0_49: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit130
movq %r12, 16(%rsp)
movq 8(%rsp), %rax
movb $0, (%rax,%r12)
movq 8(%rsp), %r12
movl (%r14), %eax
movl %eax, 64(%rsp) # 4-byte Spill
movl $0, (%r14)
leaq 40(%rsp), %rsi
movq %r12, %rdi
movl $10, %edx
callq __isoc23_strtol
cmpq %r12, 40(%rsp)
je .LBB0_140
# %bb.50:
movq %rax, %rbx
movabsq $-4294967296, %rax # imm = 0xFFFFFFFF00000000
leaq -2147483648(%rbx), %rcx
cmpq %rax, %rcx
leaq 24(%rsp), %rcx
jb .LBB0_142
# %bb.51:
movl (%r14), %eax
cmpl $34, %eax
je .LBB0_142
# %bb.52:
testl %eax, %eax
jne .LBB0_54
# %bb.53:
movl 64(%rsp), %eax # 4-byte Reload
movl %eax, (%r14)
.LBB0_54: # %_ZNSt7__cxx114stoiERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEPmi.exit136
movq 8(%rsp), %rdi
cmpq %rcx, %rdi
je .LBB0_56
# %bb.55: # %.critedge.i.i137
callq _ZdlPv
.LBB0_56:
testl %ebx, %ebx
movl $5, %r14d
cmovnel %ebx, %r14d
movl %r15d, 24(%rsp)
imull %r15d, %r15d
shlq $2, %r15
leaq 8(%rsp), %rdi
movq %r15, %rsi
xorl %edx, %edx
callq hipHostMalloc
testl %eax, %eax
je .LBB0_64
# %bb.57:
movl %eax, %ebx
movl %eax, %edi
callq hipGetErrorName
testq %rax, %rax
je .LBB0_59
# %bb.58:
movq %rax, %rdi
movq %rax, %r15
callq strlen
movl $_ZSt4cerr, %edi
movq %r15, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB0_60
.LBB0_59:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl _ZSt4cerr+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB0_60: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit147
movl $_ZSt4cerr, %edi
movl $.L.str.3, %esi
movl $2, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebx, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB0_62
# %bb.61:
movq %rax, %rdi
movq %rax, %rbx
callq strlen
movl $_ZSt4cerr, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB0_63
.LBB0_62:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl _ZSt4cerr+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB0_63: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit149
movl $_ZSt4cerr, %edi
movl $.L.str.4, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cerr, %edi
movl $.L.str.5, %esi
movl $150, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cerr, %edi
movl $.L.str.6, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cerr, %edi
movl $70, %esi
callq _ZNSolsEi
movl $.L.str.7, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB0_64:
leaq 16(%rsp), %rdi
movl 24(%rsp), %esi
imull %esi, %esi
shlq $2, %rsi
xorl %edx, %edx
callq hipHostMalloc
testl %eax, %eax
je .LBB0_72
# %bb.65:
movl %eax, %ebx
movl %eax, %edi
callq hipGetErrorName
testq %rax, %rax
je .LBB0_67
# %bb.66:
movq %rax, %rdi
movq %rax, %r15
callq strlen
movl $_ZSt4cerr, %edi
movq %r15, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB0_68
.LBB0_67:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl _ZSt4cerr+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB0_68: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit151
movl $_ZSt4cerr, %edi
movl $.L.str.3, %esi
movl $2, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebx, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB0_70
# %bb.69:
movq %rax, %rdi
movq %rax, %rbx
callq strlen
movl $_ZSt4cerr, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB0_71
.LBB0_70:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl _ZSt4cerr+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB0_71: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit153
movl $_ZSt4cerr, %edi
movl $.L.str.4, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cerr, %edi
movl $.L.str.5, %esi
movl $150, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cerr, %edi
movl $.L.str.6, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cerr, %edi
movl $73, %esi
callq _ZNSolsEi
movl $.L.str.7, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB0_72:
xorl %edi, %edi
callq srand
movl 24(%rsp), %esi
testl %esi, %esi
jle .LBB0_85
# %bb.73: # %.preheader.lr.ph
movl %esi, %eax
shrl $2, %eax
leal (%rsi,%rsi,2), %ecx
shrl $2, %ecx
leaq (,%rsi,4), %rdx
xorl %edi, %edi
xorl %r8d, %r8d
jmp .LBB0_75
.p2align 4, 0x90
.LBB0_74: # %._crit_edge
# in Loop: Header=BB0_75 Depth=1
incq %r8
addq $4, %rdi
cmpq %rsi, %r8
je .LBB0_85
.LBB0_75: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_78 Depth 2
movq 8(%rsp), %r9
xorl %r10d, %r10d
jmp .LBB0_78
.p2align 4, 0x90
.LBB0_76: # in Loop: Header=BB0_78 Depth=2
movl $0, (%r9,%rdi)
.LBB0_77: # in Loop: Header=BB0_78 Depth=2
incq %r10
addq %rdx, %r9
cmpq %r10, %rsi
je .LBB0_74
.LBB0_78: # Parent Loop BB0_75 Depth=1
# => This Inner Loop Header: Depth=2
testq %r8, %r8
je .LBB0_84
# %bb.79: # in Loop: Header=BB0_78 Depth=2
cmpq %rax, %r8
jbe .LBB0_76
# %bb.80: # in Loop: Header=BB0_78 Depth=2
cmpq %rcx, %r10
jae .LBB0_76
# %bb.81: # in Loop: Header=BB0_78 Depth=2
cmpq %rcx, %r8
jae .LBB0_76
# %bb.82: # in Loop: Header=BB0_78 Depth=2
cmpq %rax, %r10
jbe .LBB0_76
# %bb.83: # in Loop: Header=BB0_78 Depth=2
movl $1120403456, (%r9,%rdi) # imm = 0x42C80000
jmp .LBB0_77
.p2align 4, 0x90
.LBB0_84: # in Loop: Header=BB0_78 Depth=2
movl $1123942400, (%r9) # imm = 0x42FE0000
jmp .LBB0_77
.LBB0_85: # %._crit_edge191
movl %esi, 56(%rsp)
imull %esi, %esi
shlq $2, %rsi
leaq 40(%rsp), %rdi
callq hipMalloc
testl %eax, %eax
je .LBB0_93
# %bb.86:
movl %eax, %ebx
movl %eax, %edi
callq hipGetErrorName
testq %rax, %rax
je .LBB0_88
# %bb.87:
movq %rax, %rdi
movq %rax, %r15
callq strlen
movl $_ZSt4cerr, %edi
movq %r15, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB0_89
.LBB0_88:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl _ZSt4cerr+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB0_89: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit155
movl $_ZSt4cerr, %edi
movl $.L.str.3, %esi
movl $2, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebx, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB0_91
# %bb.90:
movq %rax, %rdi
movq %rax, %rbx
callq strlen
movl $_ZSt4cerr, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB0_92
.LBB0_91:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl _ZSt4cerr+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB0_92: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit157
movl $_ZSt4cerr, %edi
movl $.L.str.4, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cerr, %edi
movl $.L.str.5, %esi
movl $150, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cerr, %edi
movl $.L.str.6, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cerr, %edi
movl $95, %esi
callq _ZNSolsEi
movl $.L.str.7, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB0_93:
leaq 48(%rsp), %rdi
movl 56(%rsp), %esi
imull %esi, %esi
shlq $2, %rsi
callq hipMalloc
testl %eax, %eax
je .LBB0_101
# %bb.94:
movl %eax, %ebx
movl %eax, %edi
callq hipGetErrorName
testq %rax, %rax
je .LBB0_96
# %bb.95:
movq %rax, %rdi
movq %rax, %r15
callq strlen
movl $_ZSt4cerr, %edi
movq %r15, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB0_97
.LBB0_96:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl _ZSt4cerr+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB0_97: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit159
movl $_ZSt4cerr, %edi
movl $.L.str.3, %esi
movl $2, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebx, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB0_99
# %bb.98:
movq %rax, %rdi
movq %rax, %rbx
callq strlen
movl $_ZSt4cerr, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB0_100
.LBB0_99:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl _ZSt4cerr+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB0_100: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit161
movl $_ZSt4cerr, %edi
movl $.L.str.4, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cerr, %edi
movl $.L.str.5, %esi
movl $150, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cerr, %edi
movl $.L.str.6, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cerr, %edi
movl $98, %esi
callq _ZNSolsEi
movl $.L.str.7, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB0_101:
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, 64(%rsp) # 8-byte Spill
movq 40(%rsp), %rdi
movq 8(%rsp), %rsi
movl 56(%rsp), %edx
imull %edx, %edx
shlq $2, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB0_109
# %bb.102:
movl %eax, %ebx
movl %eax, %edi
callq hipGetErrorName
testq %rax, %rax
je .LBB0_104
# %bb.103:
movq %rax, %rdi
movq %rax, %r15
callq strlen
movl $_ZSt4cerr, %edi
movq %r15, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB0_105
.LBB0_104:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl _ZSt4cerr+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB0_105: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit163
movl $_ZSt4cerr, %edi
movl $.L.str.3, %esi
movl $2, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebx, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB0_107
# %bb.106:
movq %rax, %rdi
movq %rax, %rbx
callq strlen
movl $_ZSt4cerr, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB0_108
.LBB0_107:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl _ZSt4cerr+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB0_108: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit165
movl $_ZSt4cerr, %edi
movl $.L.str.4, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cerr, %edi
movl $.L.str.5, %esi
movl $150, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cerr, %edi
movl $.L.str.6, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cerr, %edi
movl $105, %esi
callq _ZNSolsEi
movl $.L.str.7, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB0_109:
movq 48(%rsp), %rdi
movq 8(%rsp), %rsi
movl 56(%rsp), %edx
imull %edx, %edx
shlq $2, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB0_117
# %bb.110:
movl %eax, %ebx
movl %eax, %edi
callq hipGetErrorName
testq %rax, %rax
je .LBB0_112
# %bb.111:
movq %rax, %rdi
movq %rax, %r15
callq strlen
movl $_ZSt4cerr, %edi
movq %r15, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB0_113
.LBB0_112:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl _ZSt4cerr+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB0_113: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit167
movl $_ZSt4cerr, %edi
movl $.L.str.3, %esi
movl $2, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebx, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB0_115
# %bb.114:
movq %rax, %rdi
movq %rax, %rbx
callq strlen
movl $_ZSt4cerr, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB0_116
.LBB0_115:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl _ZSt4cerr+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB0_116: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit169
movl $_ZSt4cerr, %edi
movl $.L.str.4, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cerr, %edi
movl $.L.str.5, %esi
movl $150, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cerr, %edi
movl $.L.str.6, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cerr, %edi
movl $109, %esi
callq _ZNSolsEi
movl $.L.str.7, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB0_117:
movq %rbp, 72(%rsp) # 8-byte Spill
movl %r13d, %ebp
callq _ZNSt6chrono3_V212system_clock3nowEv
cvtsi2ssl 56(%rsp), %xmm0
movq %rax, %r12
divss .LCPI0_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %r13d
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 56(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.9, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 56(%rsp), %esi
movq %rbx, %rdi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.10, %esi
movl $14, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
movl %r14d, %esi
callq _ZNSolsEi
movl $.L.str.11, %esi
movl $12, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.12, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r13d, %esi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.13, %esi
movl $12, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
movl $128, %esi
callq _ZNSolsEi
movl $.L.str.14, %esi
movl $19, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %rbx
testl %r14d, %r14d
jle .LBB0_119
.p2align 4, 0x90
.LBB0_118: # %.lr.ph194
# =>This Inner Loop Header: Depth=1
movl 56(%rsp), %edx
movq 40(%rsp), %rcx
movq 48(%rsp), %r8
movl %r13d, %edi
movl $128, %esi
callq _Z28simpleStencil_Kernel_WrapperiiiPfS_
movq 40(%rsp), %rax
movq 48(%rsp), %rcx
movq %rcx, 40(%rsp)
movq %rax, 48(%rsp)
decl %r14d
jne .LBB0_118
.LBB0_119: # %._crit_edge195
callq hipDeviceSynchronize
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r13
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r14
movq 8(%rsp), %rdi
movq 40(%rsp), %rsi
movl 24(%rsp), %edx
imull %edx, %edx
shlq $2, %rdx
movl $2, %ecx
callq hipMemcpy
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r15
cmpl $3, %ebp
jle .LBB0_121
# %bb.120:
movq 8(%rsp), %rdi
movq 72(%rsp), %rax # 8-byte Reload
movq 24(%rax), %rsi
movl 24(%rsp), %edx
callq _Z11writeToFilePfPKci
.LBB0_121:
subq 64(%rsp), %r12 # 8-byte Folded Reload
cvtsi2sd %r12, %xmm1
movsd .LCPI0_1(%rip), %xmm0 # xmm0 = mem[0],zero
divsd %xmm0, %xmm1
movsd %xmm1, 112(%rsp) # 8-byte Spill
subq %rbx, %r13
xorps %xmm1, %xmm1
cvtsi2sd %r13, %xmm1
divsd %xmm0, %xmm1
movsd %xmm1, 72(%rsp) # 8-byte Spill
subq %r14, %r15
xorps %xmm1, %xmm1
cvtsi2sd %r15, %xmm1
divsd %xmm0, %xmm1
movsd %xmm1, 64(%rsp) # 8-byte Spill
movq 8(%rsp), %rdi
callq hipHostFree
movq 16(%rsp), %rdi
callq hipHostFree
movq 40(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movl $_ZSt4cout, %edi
movl $.L.str.15, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.16, %esi
movl $29, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 112(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.17, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
movsd 72(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.17, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
movsd 64(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.7, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %eax, %eax
.LBB0_122:
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_123: # %.noexc11.i
.cfi_def_cfa_offset 176
callq _ZSt17__throw_bad_allocv
.LBB0_124: # %.noexc11.i112
.Ltmp21:
callq _ZSt17__throw_bad_allocv
.Ltmp22:
# %bb.125: # %.noexc116
.LBB0_126: # %.noexc11.i124
.Ltmp9:
callq _ZSt17__throw_bad_allocv
.Ltmp10:
# %bb.127: # %.noexc128
.LBB0_128: # %.noexc
movl $.L.str.21, %edi
callq _ZSt19__throw_logic_errorPKc
.LBB0_129:
.Ltmp25:
movl $.L.str.21, %edi
callq _ZSt19__throw_logic_errorPKc
.Ltmp26:
# %bb.130: # %.noexc114
.LBB0_131:
.Ltmp18:
movl $.L.str.23, %edi
callq _ZSt24__throw_invalid_argumentPKc
.Ltmp19:
# %bb.132:
.LBB0_133: # %.critedge.i.i119
.Ltmp16:
movl $.L.str.23, %edi
callq _ZSt20__throw_out_of_rangePKc
.Ltmp17:
# %bb.134:
.LBB0_135: # %.noexc.i
movl $.L.str.22, %edi
callq _ZSt20__throw_length_errorPKc
.LBB0_136: # %.noexc.i113
.Ltmp23:
movl $.L.str.22, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp24:
# %bb.137: # %.noexc115
.LBB0_138:
.Ltmp13:
movl $.L.str.21, %edi
callq _ZSt19__throw_logic_errorPKc
.Ltmp14:
# %bb.139: # %.noexc126
.LBB0_140:
.Ltmp6:
movl $.L.str.23, %edi
callq _ZSt24__throw_invalid_argumentPKc
.Ltmp7:
# %bb.141:
.LBB0_142: # %.critedge.i.i132
.Ltmp4:
movl $.L.str.23, %edi
callq _ZSt20__throw_out_of_rangePKc
.Ltmp5:
# %bb.143:
.LBB0_144: # %.noexc.i125
.Ltmp11:
movl $.L.str.22, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp12:
# %bb.145: # %.noexc127
.LBB0_146:
.Ltmp8:
movq %rax, %rbx
cmpl $0, (%r14)
jne .LBB0_151
# %bb.147:
movl 64(%rsp), %eax # 4-byte Reload
movl %eax, (%r14)
jmp .LBB0_151
.LBB0_149:
.Ltmp20:
movq %rax, %rbx
cmpl $0, (%r14)
jne .LBB0_151
# %bb.150:
movl %r12d, (%r14)
.LBB0_151: # %_ZZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_EN11_Save_errnoD2Ev.exit.i.i
movq 8(%rsp), %rdi
leaq 24(%rsp), %rax
cmpq %rax, %rdi
je .LBB0_153
# %bb.152: # %.critedge.i.i140
callq _ZdlPv
.LBB0_153: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit142
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.LBB0_154:
.Ltmp15:
movq %rax, %rdi
callq _Unwind_Resume@PLT
.LBB0_155:
.Ltmp27:
movq %rax, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table0:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp27-.Lfunc_begin0 # jumps to .Ltmp27
.byte 0 # On action: cleanup
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp2-.Ltmp1 # Call between .Ltmp1 and .Ltmp2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp2-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp3-.Ltmp2 # Call between .Ltmp2 and .Ltmp3
.uleb128 .Ltmp15-.Lfunc_begin0 # jumps to .Ltmp15
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp21-.Ltmp3 # Call between .Ltmp3 and .Ltmp21
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp21-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp22-.Ltmp21 # Call between .Ltmp21 and .Ltmp22
.uleb128 .Ltmp27-.Lfunc_begin0 # jumps to .Ltmp27
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp15-.Lfunc_begin0 # jumps to .Ltmp15
.byte 0 # On action: cleanup
.uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp25-.Ltmp10 # Call between .Ltmp10 and .Ltmp25
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp25-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp26-.Ltmp25 # Call between .Ltmp25 and .Ltmp26
.uleb128 .Ltmp27-.Lfunc_begin0 # jumps to .Ltmp27
.byte 0 # On action: cleanup
.uleb128 .Ltmp18-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp17-.Ltmp18 # Call between .Ltmp18 and .Ltmp17
.uleb128 .Ltmp20-.Lfunc_begin0 # jumps to .Ltmp20
.byte 0 # On action: cleanup
.uleb128 .Ltmp17-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp23-.Ltmp17 # Call between .Ltmp17 and .Ltmp23
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp23-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Ltmp24-.Ltmp23 # Call between .Ltmp23 and .Ltmp24
.uleb128 .Ltmp27-.Lfunc_begin0 # jumps to .Ltmp27
.byte 0 # On action: cleanup
.uleb128 .Ltmp13-.Lfunc_begin0 # >> Call Site 13 <<
.uleb128 .Ltmp14-.Ltmp13 # Call between .Ltmp13 and .Ltmp14
.uleb128 .Ltmp15-.Lfunc_begin0 # jumps to .Ltmp15
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 14 <<
.uleb128 .Ltmp5-.Ltmp6 # Call between .Ltmp6 and .Ltmp5
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp11-.Lfunc_begin0 # >> Call Site 15 <<
.uleb128 .Ltmp12-.Ltmp11 # Call between .Ltmp11 and .Ltmp12
.uleb128 .Ltmp15-.Lfunc_begin0 # jumps to .Ltmp15
.byte 0 # On action: cleanup
.uleb128 .Ltmp12-.Lfunc_begin0 # >> Call Site 16 <<
.uleb128 .Lfunc_end0-.Ltmp12 # Call between .Ltmp12 and .Lfunc_end0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.globl _Z11writeToFilePfPKci # -- Begin function _Z11writeToFilePfPKci
.p2align 4, 0x90
.type _Z11writeToFilePfPKci,@function
_Z11writeToFilePfPKci: # @_Z11writeToFilePfPKci
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movq %rsi, %rax
movq %rdi, %r15
movl $.L.str.18, %esi
movq %rax, %rdi
callq fopen
movq %rax, %r14
movl $.L.str.19, %esi
movq %rax, %rdi
movl %ebp, %edx
movl %ebp, %ecx
movl $127, %r8d
xorl %eax, %eax
callq fprintf
testl %ebp, %ebp
jle .LBB1_5
# %bb.1: # %.preheader.lr.ph
movl %ebp, %ebp
leaq (,%rbp,4), %r12
xorl %r13d, %r13d
movq %rbp, (%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
movq %r15, %rbx
.p2align 4, 0x90
.LBB1_3: # %.lr.ph
# Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
cvttss2si (%rbx), %edx
movl $.L.str.20, %esi
movq %r14, %rdi
xorl %eax, %eax
callq fprintf
addq %r12, %rbx
decq %rbp
jne .LBB1_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movl $10, %edi
movq %r14, %rsi
callq fputc@PLT
incq %r13
addq $4, %r15
movq (%rsp), %rbp # 8-byte Reload
cmpq %rbp, %r13
jne .LBB1_2
.LBB1_5: # %._crit_edge20
movq %r14, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end1:
.size _Z11writeToFilePfPKci, .Lfunc_end1-_Z11writeToFilePfPKci
.cfi_endproc
# -- End function
.type now,@object # @now
.section .rodata,"a",@progbits
.globl now
.p2align 3, 0x0
now:
.quad _ZNSt6chrono3_V212system_clock3nowEv
.size now, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "-h"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Usage:\n\t"
.size .L.str.1, 9
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " <problemsize> [iterations] [result.pgm]\n"
.size .L.str.2, 42
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz ": "
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " at "
.size .L.str.4, 5
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/YannickEmonds/gpu-mangrove_exercises/main/benchmarks/time_instrumentation/5p-stencil/main.hip"
.size .L.str.5, 151
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz ":"
.size .L.str.6, 2
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "\n"
.size .L.str.7, 2
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Computing grid with "
.size .L.str.8, 21
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "x"
.size .L.str.9, 2
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz " elements and "
.size .L.str.10, 15
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz " iterations\n"
.size .L.str.11, 13
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Launch kernel with "
.size .L.str.12, 20
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz " blocks and "
.size .L.str.13, 13
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz " threads per block\n"
.size .L.str.14, 20
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Results:\n"
.size .L.str.15, 10
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "H2D [s], kernel [s], D2H [s]\n"
.size .L.str.16, 30
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz ", "
.size .L.str.17, 3
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "w"
.size .L.str.18, 2
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "P2 %d %d %d\n"
.size .L.str.19, 13
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "%d "
.size .L.str.20, 4
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz "basic_string: construction from null is not valid"
.size .L.str.21, 50
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz "basic_string::_M_create"
.size .L.str.22, 24
.type .L.str.23,@object # @.str.23
.L.str.23:
.asciz "stoi"
.size .L.str.23, 5
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZNSt6chrono3_V212system_clock3nowEv
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt4cerr
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void Transpose_ker(float * dst, float * src, int size)
{
int i = blockIdx.y * blockDim.y + threadIdx.y;
int j = blockIdx.x * blockDim.x + threadIdx.x;
if (i < size && j < size)
dst[i * size + j] = src[j * size + i];
}
void cuTranspose(float * dst, float * src, int size)
{
size = (size + 16 - 1) / 16 * 16;
dim3 dimBlock(16, 16);
dim3 dimGrid(size / 16, size / 16);
Transpose_ker<<<dimGrid, dimBlock>>>(dst, src, size);
} | code for sm_80
Function : _Z13Transpose_kerPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0030*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R5, R5, c[0x0][0x0], R2 ; /* 0x0000000005057a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x170], PT ; /* 0x00005c0005007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R2, R5, c[0x0][0x170], R0 ; /* 0x00005c0005027a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R2, R2, R4, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0204 */
/*00e0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD R5, R0, c[0x0][0x170], R5 ; /* 0x00005c0000057a24 */
/* 0x000fc800078e0205 */
/*0100*/ IMAD.WIDE R4, R5, R4, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fca00078e0204 */
/*0110*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void Transpose_ker(float * dst, float * src, int size)
{
int i = blockIdx.y * blockDim.y + threadIdx.y;
int j = blockIdx.x * blockDim.x + threadIdx.x;
if (i < size && j < size)
dst[i * size + j] = src[j * size + i];
}
void cuTranspose(float * dst, float * src, int size)
{
size = (size + 16 - 1) / 16 * 16;
dim3 dimBlock(16, 16);
dim3 dimGrid(size / 16, size / 16);
Transpose_ker<<<dimGrid, dimBlock>>>(dst, src, size);
} | .file "tmpxft_0010e1e4_00000000-6_cuTranspose.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z13Transpose_kerPfS_iPfS_i
.type _Z36__device_stub__Z13Transpose_kerPfS_iPfS_i, @function
_Z36__device_stub__Z13Transpose_kerPfS_iPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13Transpose_kerPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z36__device_stub__Z13Transpose_kerPfS_iPfS_i, .-_Z36__device_stub__Z13Transpose_kerPfS_iPfS_i
.globl _Z13Transpose_kerPfS_i
.type _Z13Transpose_kerPfS_i, @function
_Z13Transpose_kerPfS_i:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z13Transpose_kerPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z13Transpose_kerPfS_i, .-_Z13Transpose_kerPfS_i
.globl _Z11cuTransposePfS_i
.type _Z11cuTransposePfS_i, @function
_Z11cuTransposePfS_i:
.LFB2027:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movq %rsi, %r12
leal 30(%rdx), %ebx
addl $15, %edx
cmovns %edx, %ebx
sarl $4, %ebx
movl $16, 8(%rsp)
movl $16, 12(%rsp)
movl %ebx, 20(%rsp)
movl %ebx, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
sall $4, %ebx
movl %ebx, %edx
movq %r12, %rsi
movq %rbp, %rdi
call _Z36__device_stub__Z13Transpose_kerPfS_iPfS_i
jmp .L11
.cfi_endproc
.LFE2027:
.size _Z11cuTransposePfS_i, .-_Z11cuTransposePfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13Transpose_kerPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13Transpose_kerPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void Transpose_ker(float * dst, float * src, int size)
{
int i = blockIdx.y * blockDim.y + threadIdx.y;
int j = blockIdx.x * blockDim.x + threadIdx.x;
if (i < size && j < size)
dst[i * size + j] = src[j * size + i];
}
void cuTranspose(float * dst, float * src, int size)
{
size = (size + 16 - 1) / 16 * 16;
dim3 dimBlock(16, 16);
dim3 dimGrid(size / 16, size / 16);
Transpose_ker<<<dimGrid, dimBlock>>>(dst, src, size);
} | #include <hip/hip_runtime.h>
__global__ void Transpose_ker(float * dst, float * src, int size)
{
int i = blockIdx.y * blockDim.y + threadIdx.y;
int j = blockIdx.x * blockDim.x + threadIdx.x;
if (i < size && j < size)
dst[i * size + j] = src[j * size + i];
}
void cuTranspose(float * dst, float * src, int size)
{
size = (size + 16 - 1) / 16 * 16;
dim3 dimBlock(16, 16);
dim3 dimGrid(size / 16, size / 16);
Transpose_ker<<<dimGrid, dimBlock>>>(dst, src, size);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void Transpose_ker(float * dst, float * src, int size)
{
int i = blockIdx.y * blockDim.y + threadIdx.y;
int j = blockIdx.x * blockDim.x + threadIdx.x;
if (i < size && j < size)
dst[i * size + j] = src[j * size + i];
}
void cuTranspose(float * dst, float * src, int size)
{
size = (size + 16 - 1) / 16 * 16;
dim3 dimBlock(16, 16);
dim3 dimGrid(size / 16, size / 16);
Transpose_ker<<<dimGrid, dimBlock>>>(dst, src, size);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13Transpose_kerPfS_i
.globl _Z13Transpose_kerPfS_i
.p2align 8
.type _Z13Transpose_kerPfS_i,@function
_Z13Transpose_kerPfS_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s2, s[0:1], 0x10
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b32 v4, v[2:3], off
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13Transpose_kerPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13Transpose_kerPfS_i, .Lfunc_end0-_Z13Transpose_kerPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13Transpose_kerPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13Transpose_kerPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void Transpose_ker(float * dst, float * src, int size)
{
int i = blockIdx.y * blockDim.y + threadIdx.y;
int j = blockIdx.x * blockDim.x + threadIdx.x;
if (i < size && j < size)
dst[i * size + j] = src[j * size + i];
}
void cuTranspose(float * dst, float * src, int size)
{
size = (size + 16 - 1) / 16 * 16;
dim3 dimBlock(16, 16);
dim3 dimGrid(size / 16, size / 16);
Transpose_ker<<<dimGrid, dimBlock>>>(dst, src, size);
} | .text
.file "cuTranspose.hip"
.globl _Z28__device_stub__Transpose_kerPfS_i # -- Begin function _Z28__device_stub__Transpose_kerPfS_i
.p2align 4, 0x90
.type _Z28__device_stub__Transpose_kerPfS_i,@function
_Z28__device_stub__Transpose_kerPfS_i: # @_Z28__device_stub__Transpose_kerPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13Transpose_kerPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z28__device_stub__Transpose_kerPfS_i, .Lfunc_end0-_Z28__device_stub__Transpose_kerPfS_i
.cfi_endproc
# -- End function
.globl _Z11cuTransposePfS_i # -- Begin function _Z11cuTransposePfS_i
.p2align 4, 0x90
.type _Z11cuTransposePfS_i,@function
_Z11cuTransposePfS_i: # @_Z11cuTransposePfS_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %edx, %ebx
movq %rsi, %r14
movq %rdi, %r15
leal 15(%rbx), %eax
addl $30, %ebx
testl %eax, %eax
cmovnsl %eax, %ebx
sarl $4, %ebx
movq %rbx, %rdi
shlq $32, %rdi
orq %rbx, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
shll $4, %ebx
movq %r15, 72(%rsp)
movq %r14, 64(%rsp)
movl %ebx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13Transpose_kerPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11cuTransposePfS_i, .Lfunc_end1-_Z11cuTransposePfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13Transpose_kerPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13Transpose_kerPfS_i,@object # @_Z13Transpose_kerPfS_i
.section .rodata,"a",@progbits
.globl _Z13Transpose_kerPfS_i
.p2align 3, 0x0
_Z13Transpose_kerPfS_i:
.quad _Z28__device_stub__Transpose_kerPfS_i
.size _Z13Transpose_kerPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13Transpose_kerPfS_i"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__Transpose_kerPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13Transpose_kerPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13Transpose_kerPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0030*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R5, R5, c[0x0][0x0], R2 ; /* 0x0000000005057a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x170], PT ; /* 0x00005c0005007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R2, R5, c[0x0][0x170], R0 ; /* 0x00005c0005027a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R2, R2, R4, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0204 */
/*00e0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD R5, R0, c[0x0][0x170], R5 ; /* 0x00005c0000057a24 */
/* 0x000fc800078e0205 */
/*0100*/ IMAD.WIDE R4, R5, R4, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fca00078e0204 */
/*0110*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13Transpose_kerPfS_i
.globl _Z13Transpose_kerPfS_i
.p2align 8
.type _Z13Transpose_kerPfS_i,@function
_Z13Transpose_kerPfS_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s2, s[0:1], 0x10
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b32 v4, v[2:3], off
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13Transpose_kerPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13Transpose_kerPfS_i, .Lfunc_end0-_Z13Transpose_kerPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13Transpose_kerPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13Transpose_kerPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010e1e4_00000000-6_cuTranspose.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z13Transpose_kerPfS_iPfS_i
.type _Z36__device_stub__Z13Transpose_kerPfS_iPfS_i, @function
_Z36__device_stub__Z13Transpose_kerPfS_iPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13Transpose_kerPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z36__device_stub__Z13Transpose_kerPfS_iPfS_i, .-_Z36__device_stub__Z13Transpose_kerPfS_iPfS_i
.globl _Z13Transpose_kerPfS_i
.type _Z13Transpose_kerPfS_i, @function
_Z13Transpose_kerPfS_i:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z13Transpose_kerPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z13Transpose_kerPfS_i, .-_Z13Transpose_kerPfS_i
.globl _Z11cuTransposePfS_i
.type _Z11cuTransposePfS_i, @function
_Z11cuTransposePfS_i:
.LFB2027:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movq %rsi, %r12
leal 30(%rdx), %ebx
addl $15, %edx
cmovns %edx, %ebx
sarl $4, %ebx
movl $16, 8(%rsp)
movl $16, 12(%rsp)
movl %ebx, 20(%rsp)
movl %ebx, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
sall $4, %ebx
movl %ebx, %edx
movq %r12, %rsi
movq %rbp, %rdi
call _Z36__device_stub__Z13Transpose_kerPfS_iPfS_i
jmp .L11
.cfi_endproc
.LFE2027:
.size _Z11cuTransposePfS_i, .-_Z11cuTransposePfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13Transpose_kerPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13Transpose_kerPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuTranspose.hip"
.globl _Z28__device_stub__Transpose_kerPfS_i # -- Begin function _Z28__device_stub__Transpose_kerPfS_i
.p2align 4, 0x90
.type _Z28__device_stub__Transpose_kerPfS_i,@function
_Z28__device_stub__Transpose_kerPfS_i: # @_Z28__device_stub__Transpose_kerPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13Transpose_kerPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z28__device_stub__Transpose_kerPfS_i, .Lfunc_end0-_Z28__device_stub__Transpose_kerPfS_i
.cfi_endproc
# -- End function
.globl _Z11cuTransposePfS_i # -- Begin function _Z11cuTransposePfS_i
.p2align 4, 0x90
.type _Z11cuTransposePfS_i,@function
_Z11cuTransposePfS_i: # @_Z11cuTransposePfS_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %edx, %ebx
movq %rsi, %r14
movq %rdi, %r15
leal 15(%rbx), %eax
addl $30, %ebx
testl %eax, %eax
cmovnsl %eax, %ebx
sarl $4, %ebx
movq %rbx, %rdi
shlq $32, %rdi
orq %rbx, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
shll $4, %ebx
movq %r15, 72(%rsp)
movq %r14, 64(%rsp)
movl %ebx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13Transpose_kerPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11cuTransposePfS_i, .Lfunc_end1-_Z11cuTransposePfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13Transpose_kerPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13Transpose_kerPfS_i,@object # @_Z13Transpose_kerPfS_i
.section .rodata,"a",@progbits
.globl _Z13Transpose_kerPfS_i
.p2align 3, 0x0
_Z13Transpose_kerPfS_i:
.quad _Z28__device_stub__Transpose_kerPfS_i
.size _Z13Transpose_kerPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13Transpose_kerPfS_i"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__Transpose_kerPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13Transpose_kerPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <iostream>
#include <cmath>
#include <time.h>
using namespace std;
class Matrix
{
private:
int rozmiar_macierzy;
double** macierz;
public:
Matrix(int rozmiar)
{
rozmiar_macierzy = rozmiar;
macierz = new double* [rozmiar];
for (int i = 0; i < rozmiar; i++) {
macierz[i] = new double[rozmiar];
}
}
void free_memory();
void random_values();
int get_size();
void set_value(int line, int column, double value);
double get_value(int line, int column);
Matrix transposition();
void write_matrix();
};
void Matrix::free_memory()
{
delete[] macierz;
}
void Matrix::random_values()
{
int rozmiar = rozmiar_macierzy;
for (int i = 0; i < rozmiar; i++) {
for (int j = 0; j < rozmiar; j++) {
macierz[i][j] = 2 * ((double)rand() / (double)RAND_MAX) - 1;
}
}
}
int Matrix::get_size()
{
return rozmiar_macierzy;
}
void Matrix::set_value(int line, int column, double value)
{
macierz[line][column] = value;
}
double Matrix::get_value(int line, int column)
{
return macierz[line][column];
}
Matrix Matrix::transposition()
{
int rozmiar = rozmiar_macierzy;
Matrix At(rozmiar);
for (int i = 0; i < rozmiar; i++) {
for (int j = 0; j < rozmiar; j++) {
At.set_value(i, j, macierz[j][i]);
}
}
return At;
}
void Matrix::write_matrix()
{
int rozmiar = rozmiar_macierzy;
for (int i = 0; i < rozmiar; i++) {
cout << "| ";
for (int j = 0; j < rozmiar; j++) {
cout << macierz[i][j] << " ";
}
cout << "|" << endl;
}
cout << endl;
}
Matrix multiplication(Matrix A, Matrix B)
{
int rozmiar = A.get_size();
double sum;
Matrix C(rozmiar);
for (int k = 0; k < rozmiar; k++) {
for (int l = 0; l < rozmiar; l++) {
sum = 0;
for (int m = 0; m < rozmiar; m++) {
sum = sum + A.get_value(k, m) * B.get_value(m, l);
}
C.set_value(k, l, sum);
}
}
return C;
}
Matrix addition(Matrix A, Matrix B)
{
int rozmiar = A.get_size();
double sum;
Matrix D(rozmiar);
for (int i = 0; i < rozmiar; i++) {
for (int j = 0; j < rozmiar; j++) {
sum = A.get_value(i, j) + B.get_value(i, j);
D.set_value(i, j, sum);
}
}
return D;
}
void copy_values(Matrix macierz1, double macierz2[])
{
int rozmiar = macierz1.get_size();
for (int i = 0; i < rozmiar*rozmiar; i++) {
macierz2[i] = macierz1.get_value(i/rozmiar, i%rozmiar);
}
}
__global__ void deviceTransposition(double* macierz1, double* macierz2, int* rozmiar)
{
unsigned long long int i = threadIdx.x + blockIdx.x * blockDim.x;
unsigned long long int siatka = blockDim.x * gridDim.x;
for (i; i < rozmiar[0]*rozmiar[0]; i += siatka) {
macierz2[i] = macierz1[(i%rozmiar[0])*rozmiar[0]+i/rozmiar[0]];
}
}
__global__ void deviceMultiplication(double* macierz1, double* macierz2, double* macierz3, int* rozmiar)
{
unsigned long long int i = threadIdx.x + blockIdx.x * blockDim.x;
unsigned long long int j = threadIdx.y + blockIdx.y * blockDim.y;
unsigned long long int siatkax = blockDim.x * gridDim.x;
unsigned long long int siatkay = blockDim.y * gridDim.y;
double sum;
for (i; i < rozmiar[0] * rozmiar[0]; i += siatkax) {
sum = 0;
for (j; j < rozmiar[0]; j += siatkay) {
sum = sum + macierz1[((i/rozmiar[0]) * rozmiar[0]) + j] * macierz2[i%rozmiar[0] + j*rozmiar[0]];
}
macierz3[i] = sum;
}
}
__global__ void deviceAddition(double* macierz1, double* macierz2, double* macierz3, int* rozmiar)
{
unsigned long long int i = threadIdx.x + blockIdx.x * blockDim.x;
unsigned long long int siatka = blockDim.x * gridDim.x;
for (i; i < rozmiar[0] * rozmiar[0]; i += siatka) {
macierz3[i] = macierz2[i] + macierz1[i];
}
}
int main()
{
srand(time(NULL));
while (true) {
int rozmiar[1];
cout << "Podaj rozmiar macierzy: ";
cin >> rozmiar[0];
Matrix A(rozmiar[0]);
Matrix B(rozmiar[0]);
Matrix C(rozmiar[0]);
Matrix D(rozmiar[0]);
A.random_values();
B.random_values();
/*cout << "macierz A:" << endl;
A.write_matrix();
cout << "macierz B:" << endl;
B.write_matrix();*/
clock_t start;
double duration_on_CPU;
start = clock();
C = multiplication(A, B);
/*cout << "Macierz C na CPU:" << endl;
C.write_matrix();*/
duration_on_CPU = 1000 * (clock() - start) / CLOCKS_PER_SEC;
cout << "A*B na CPU zajelo: " << duration_on_CPU << " milisekund." << endl;
double duration_on_CPU1;
start = clock();
D = addition(addition(multiplication(A, A.transposition()), multiplication(B, B.transposition())), multiplication(C, C.transposition()));
/*cout << "Macierz D na CPU:" << endl;
D.write_matrix();*/
duration_on_CPU1 = 1000 * (clock() - start) / CLOCKS_PER_SEC;
cout << "A*AT + B*BT + C*CT na CPU zajelo: " << duration_on_CPU1 << " milisekund." << endl;
cout << "Ostatni element C: " << C.get_value(rozmiar[0] - 1, rozmiar[0] - 1) << endl;
cout << "Ostatni element D: " << D.get_value(rozmiar[0] - 1, rozmiar[0] - 1) << endl;
double* A1 = new double[rozmiar[0] * rozmiar[0]];
double* B1 = new double[rozmiar[0] * rozmiar[0]];
double* C1 = new double[rozmiar[0] * rozmiar[0]];
double* D1 = new double[rozmiar[0] * rozmiar[0]];
copy_values(A, A1);
copy_values(B, B1);
double* dev_A;
double* dev_At;
double* dev_B;
double* dev_Bt;
double* dev_C;
double* dev_Ct;
double* dev_D;
double* dev_wynik;
double* dev_wynik1;
int* dev_rozmiar;
int rozmiarBloku = 1024;
int liczbaBlokow = (rozmiar[0] * rozmiar[0] + rozmiarBloku - 1) / rozmiarBloku;
int sization = rozmiar[0] * rozmiar[0] * sizeof(double);
cudaMalloc((void**)&dev_rozmiar, sizeof(int));
cudaMalloc((void**)&dev_A, sization);
cudaMalloc((void**)&dev_At, sization);
cudaMalloc((void**)&dev_B, sization);
cudaMalloc((void**)&dev_Bt, sization);
cudaMalloc((void**)&dev_C, sization);
cudaMalloc((void**)&dev_Ct, sization);
cudaMalloc((void**)&dev_D, sization);
cudaMalloc((void**)&dev_wynik, sization);
cudaMalloc((void**)&dev_wynik1, sization);
cudaMemcpy(dev_A, A1, sization, cudaMemcpyHostToDevice);
cudaMemcpy(dev_B, B1, sization, cudaMemcpyHostToDevice);
cudaMemcpy(dev_rozmiar, rozmiar, sizeof(int), cudaMemcpyHostToDevice);
clock_t start2;
double duration_on_GPU;
start2 = clock();
deviceMultiplication<<<liczbaBlokow, rozmiarBloku>>>(dev_A, dev_B, dev_C, dev_rozmiar);
cudaDeviceSynchronize();
duration_on_GPU = 1000 * (clock() - start2) / CLOCKS_PER_SEC;
cudaMemcpy(C1, dev_C, sization, cudaMemcpyDeviceToHost);
cout << "A*B na GPU zajelo: " << duration_on_GPU << " milisekund." << endl;
/*cout << "Macierz C na GPU:" << endl;
for (int i = 0; i < rozmiar[0] * rozmiar[0]; i++) {
if (i % rozmiar[0] == 0) cout << endl;
cout << C1[i] << " | ";
}
cout << endl;*/
double duration_on_GPU1;
start2 = clock();
deviceTransposition<<<liczbaBlokow, rozmiarBloku>>>(dev_A, dev_At, dev_rozmiar);
cudaDeviceSynchronize();
deviceMultiplication<<<liczbaBlokow, rozmiarBloku>>>(dev_A, dev_At, dev_D, dev_rozmiar);
cudaDeviceSynchronize();
deviceTransposition<<<liczbaBlokow, rozmiarBloku>>>(dev_B, dev_Bt, dev_rozmiar);
cudaDeviceSynchronize();
deviceMultiplication<<<liczbaBlokow, rozmiarBloku>>>(dev_B, dev_Bt, dev_wynik, dev_rozmiar);
cudaDeviceSynchronize();
deviceTransposition<<<liczbaBlokow, rozmiarBloku>>>(dev_C, dev_Ct, dev_rozmiar);
cudaDeviceSynchronize();
deviceMultiplication<<<liczbaBlokow, rozmiarBloku>>>(dev_C, dev_Ct, dev_wynik1, dev_rozmiar);
cudaDeviceSynchronize();
deviceAddition<<<liczbaBlokow, rozmiarBloku>>>(dev_wynik, dev_D, dev_D, dev_rozmiar);
cudaDeviceSynchronize();
deviceAddition<<<liczbaBlokow, rozmiarBloku>>>(dev_wynik1, dev_D, dev_D, dev_rozmiar);
cudaDeviceSynchronize();
duration_on_GPU1 = 1000 * (clock() - start2) / CLOCKS_PER_SEC;
cudaMemcpy(D1, dev_D, sization, cudaMemcpyDeviceToHost);
cout << "A*AT + B*BT + C*CT na GPU zajelo: " << duration_on_GPU1 << " milisekund." << endl;
cout << "Ostatni element C: " << C1[rozmiar[0] * rozmiar[0] - 1] << endl;
cout << "Ostatni element D: " << D1[rozmiar[0] * rozmiar[0] - 1] << endl;
/*cout << "Macierz D na GPU:" << endl;
for (int i = 0; i < rozmiar[0] * rozmiar[0]; i++) {
if (i % rozmiar[0] == 0) cout << endl;
cout << D1[i] << " | ";
}
cout << endl;*/
cout << endl;
double stosunek;
if (duration_on_GPU != 0) {
stosunek = duration_on_CPU / duration_on_GPU;
cout << "Pierwsze obliczenia na GPU sa " << stosunek << " raza szybsze." << endl;
}
else {
cout << "Pierwszy czas na GPU jest zerowy, niemozliwe wyliczenie stosunku" << endl;
}
if (duration_on_GPU1 != 0) {
stosunek = duration_on_CPU1 / duration_on_GPU1;
cout << "Drugie obliczenia na GPU sa " << stosunek << " raza szybsze." << endl;
}
else {
cout << "Drugi czas na GPU jest zerowy, niemozliwe wyliczenie stosunku" << endl;
}
cout << endl;
double max = 0;
for (int i = 0; i < rozmiar[0] * rozmiar[0]; i++) {
if (abs(C.get_value(i / rozmiar[0], i % rozmiar[0]) - C1[i]) > max) max = abs(C.get_value(i / rozmiar[0], i % rozmiar[0]) - C1[i]);
}
if (max == 0) cout << "Nie ma roznicy miedzy macierzami C z CPU i GPU" << endl;
else cout << "W miejscu najwiekszej rozbieznosci macierze C roznia sie o " << max << endl;
max = 0;
for (int i = 0; i < rozmiar[0] * rozmiar[0]; i++) {
if (abs(D.get_value(i / rozmiar[0], i % rozmiar[0]) - D1[i]) > max) max = abs(D.get_value(i / rozmiar[0], i % rozmiar[0]) - D1[i]);
}
if (max == 0) cout << "Nie ma roznicy miedzy macierzami D z CPU i GPU" << endl;
else cout << "W miejscu najwiekszej rozbieznosci macierze D roznia sie o " << max << endl;
cout << endl;
A.free_memory();
B.free_memory();
C.free_memory();
D.free_memory();
cudaFree(dev_rozmiar);
cudaFree(dev_A);
cudaFree(dev_B);
cudaFree(dev_C);
cudaFree(dev_D);
cudaFree(dev_wynik);
delete[] A1;
delete[] B1;
delete[] C1;
delete[] D1;
}
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <iostream>
#include <cmath>
#include <time.h>
using namespace std;
class Matrix
{
private:
int rozmiar_macierzy;
double** macierz;
public:
Matrix(int rozmiar)
{
rozmiar_macierzy = rozmiar;
macierz = new double* [rozmiar];
for (int i = 0; i < rozmiar; i++) {
macierz[i] = new double[rozmiar];
}
}
void free_memory();
void random_values();
int get_size();
void set_value(int line, int column, double value);
double get_value(int line, int column);
Matrix transposition();
void write_matrix();
};
void Matrix::free_memory()
{
delete[] macierz;
}
void Matrix::random_values()
{
int rozmiar = rozmiar_macierzy;
for (int i = 0; i < rozmiar; i++) {
for (int j = 0; j < rozmiar; j++) {
macierz[i][j] = 2 * ((double)rand() / (double)RAND_MAX) - 1;
}
}
}
int Matrix::get_size()
{
return rozmiar_macierzy;
}
void Matrix::set_value(int line, int column, double value)
{
macierz[line][column] = value;
}
double Matrix::get_value(int line, int column)
{
return macierz[line][column];
}
Matrix Matrix::transposition()
{
int rozmiar = rozmiar_macierzy;
Matrix At(rozmiar);
for (int i = 0; i < rozmiar; i++) {
for (int j = 0; j < rozmiar; j++) {
At.set_value(i, j, macierz[j][i]);
}
}
return At;
}
void Matrix::write_matrix()
{
int rozmiar = rozmiar_macierzy;
for (int i = 0; i < rozmiar; i++) {
cout << "| ";
for (int j = 0; j < rozmiar; j++) {
cout << macierz[i][j] << " ";
}
cout << "|" << endl;
}
cout << endl;
}
Matrix multiplication(Matrix A, Matrix B)
{
int rozmiar = A.get_size();
double sum;
Matrix C(rozmiar);
for (int k = 0; k < rozmiar; k++) {
for (int l = 0; l < rozmiar; l++) {
sum = 0;
for (int m = 0; m < rozmiar; m++) {
sum = sum + A.get_value(k, m) * B.get_value(m, l);
}
C.set_value(k, l, sum);
}
}
return C;
}
Matrix addition(Matrix A, Matrix B)
{
int rozmiar = A.get_size();
double sum;
Matrix D(rozmiar);
for (int i = 0; i < rozmiar; i++) {
for (int j = 0; j < rozmiar; j++) {
sum = A.get_value(i, j) + B.get_value(i, j);
D.set_value(i, j, sum);
}
}
return D;
}
void copy_values(Matrix macierz1, double macierz2[])
{
int rozmiar = macierz1.get_size();
for (int i = 0; i < rozmiar*rozmiar; i++) {
macierz2[i] = macierz1.get_value(i/rozmiar, i%rozmiar);
}
}
__global__ void deviceTransposition(double* macierz1, double* macierz2, int* rozmiar)
{
unsigned long long int i = threadIdx.x + blockIdx.x * blockDim.x;
unsigned long long int siatka = blockDim.x * gridDim.x;
for (i; i < rozmiar[0]*rozmiar[0]; i += siatka) {
macierz2[i] = macierz1[(i%rozmiar[0])*rozmiar[0]+i/rozmiar[0]];
}
}
__global__ void deviceMultiplication(double* macierz1, double* macierz2, double* macierz3, int* rozmiar)
{
unsigned long long int i = threadIdx.x + blockIdx.x * blockDim.x;
unsigned long long int j = threadIdx.y + blockIdx.y * blockDim.y;
unsigned long long int siatkax = blockDim.x * gridDim.x;
unsigned long long int siatkay = blockDim.y * gridDim.y;
double sum;
for (i; i < rozmiar[0] * rozmiar[0]; i += siatkax) {
sum = 0;
for (j; j < rozmiar[0]; j += siatkay) {
sum = sum + macierz1[((i/rozmiar[0]) * rozmiar[0]) + j] * macierz2[i%rozmiar[0] + j*rozmiar[0]];
}
macierz3[i] = sum;
}
}
__global__ void deviceAddition(double* macierz1, double* macierz2, double* macierz3, int* rozmiar)
{
unsigned long long int i = threadIdx.x + blockIdx.x * blockDim.x;
unsigned long long int siatka = blockDim.x * gridDim.x;
for (i; i < rozmiar[0] * rozmiar[0]; i += siatka) {
macierz3[i] = macierz2[i] + macierz1[i];
}
}
int main()
{
srand(time(NULL));
while (true) {
int rozmiar[1];
cout << "Podaj rozmiar macierzy: ";
cin >> rozmiar[0];
Matrix A(rozmiar[0]);
Matrix B(rozmiar[0]);
Matrix C(rozmiar[0]);
Matrix D(rozmiar[0]);
A.random_values();
B.random_values();
/*cout << "macierz A:" << endl;
A.write_matrix();
cout << "macierz B:" << endl;
B.write_matrix();*/
clock_t start;
double duration_on_CPU;
start = clock();
C = multiplication(A, B);
/*cout << "Macierz C na CPU:" << endl;
C.write_matrix();*/
duration_on_CPU = 1000 * (clock() - start) / CLOCKS_PER_SEC;
cout << "A*B na CPU zajelo: " << duration_on_CPU << " milisekund." << endl;
double duration_on_CPU1;
start = clock();
D = addition(addition(multiplication(A, A.transposition()), multiplication(B, B.transposition())), multiplication(C, C.transposition()));
/*cout << "Macierz D na CPU:" << endl;
D.write_matrix();*/
duration_on_CPU1 = 1000 * (clock() - start) / CLOCKS_PER_SEC;
cout << "A*AT + B*BT + C*CT na CPU zajelo: " << duration_on_CPU1 << " milisekund." << endl;
cout << "Ostatni element C: " << C.get_value(rozmiar[0] - 1, rozmiar[0] - 1) << endl;
cout << "Ostatni element D: " << D.get_value(rozmiar[0] - 1, rozmiar[0] - 1) << endl;
double* A1 = new double[rozmiar[0] * rozmiar[0]];
double* B1 = new double[rozmiar[0] * rozmiar[0]];
double* C1 = new double[rozmiar[0] * rozmiar[0]];
double* D1 = new double[rozmiar[0] * rozmiar[0]];
copy_values(A, A1);
copy_values(B, B1);
double* dev_A;
double* dev_At;
double* dev_B;
double* dev_Bt;
double* dev_C;
double* dev_Ct;
double* dev_D;
double* dev_wynik;
double* dev_wynik1;
int* dev_rozmiar;
int rozmiarBloku = 1024;
int liczbaBlokow = (rozmiar[0] * rozmiar[0] + rozmiarBloku - 1) / rozmiarBloku;
int sization = rozmiar[0] * rozmiar[0] * sizeof(double);
hipMalloc((void**)&dev_rozmiar, sizeof(int));
hipMalloc((void**)&dev_A, sization);
hipMalloc((void**)&dev_At, sization);
hipMalloc((void**)&dev_B, sization);
hipMalloc((void**)&dev_Bt, sization);
hipMalloc((void**)&dev_C, sization);
hipMalloc((void**)&dev_Ct, sization);
hipMalloc((void**)&dev_D, sization);
hipMalloc((void**)&dev_wynik, sization);
hipMalloc((void**)&dev_wynik1, sization);
hipMemcpy(dev_A, A1, sization, hipMemcpyHostToDevice);
hipMemcpy(dev_B, B1, sization, hipMemcpyHostToDevice);
hipMemcpy(dev_rozmiar, rozmiar, sizeof(int), hipMemcpyHostToDevice);
clock_t start2;
double duration_on_GPU;
start2 = clock();
deviceMultiplication<<<liczbaBlokow, rozmiarBloku>>>(dev_A, dev_B, dev_C, dev_rozmiar);
hipDeviceSynchronize();
duration_on_GPU = 1000 * (clock() - start2) / CLOCKS_PER_SEC;
hipMemcpy(C1, dev_C, sization, hipMemcpyDeviceToHost);
cout << "A*B na GPU zajelo: " << duration_on_GPU << " milisekund." << endl;
/*cout << "Macierz C na GPU:" << endl;
for (int i = 0; i < rozmiar[0] * rozmiar[0]; i++) {
if (i % rozmiar[0] == 0) cout << endl;
cout << C1[i] << " | ";
}
cout << endl;*/
double duration_on_GPU1;
start2 = clock();
deviceTransposition<<<liczbaBlokow, rozmiarBloku>>>(dev_A, dev_At, dev_rozmiar);
hipDeviceSynchronize();
deviceMultiplication<<<liczbaBlokow, rozmiarBloku>>>(dev_A, dev_At, dev_D, dev_rozmiar);
hipDeviceSynchronize();
deviceTransposition<<<liczbaBlokow, rozmiarBloku>>>(dev_B, dev_Bt, dev_rozmiar);
hipDeviceSynchronize();
deviceMultiplication<<<liczbaBlokow, rozmiarBloku>>>(dev_B, dev_Bt, dev_wynik, dev_rozmiar);
hipDeviceSynchronize();
deviceTransposition<<<liczbaBlokow, rozmiarBloku>>>(dev_C, dev_Ct, dev_rozmiar);
hipDeviceSynchronize();
deviceMultiplication<<<liczbaBlokow, rozmiarBloku>>>(dev_C, dev_Ct, dev_wynik1, dev_rozmiar);
hipDeviceSynchronize();
deviceAddition<<<liczbaBlokow, rozmiarBloku>>>(dev_wynik, dev_D, dev_D, dev_rozmiar);
hipDeviceSynchronize();
deviceAddition<<<liczbaBlokow, rozmiarBloku>>>(dev_wynik1, dev_D, dev_D, dev_rozmiar);
hipDeviceSynchronize();
duration_on_GPU1 = 1000 * (clock() - start2) / CLOCKS_PER_SEC;
hipMemcpy(D1, dev_D, sization, hipMemcpyDeviceToHost);
cout << "A*AT + B*BT + C*CT na GPU zajelo: " << duration_on_GPU1 << " milisekund." << endl;
cout << "Ostatni element C: " << C1[rozmiar[0] * rozmiar[0] - 1] << endl;
cout << "Ostatni element D: " << D1[rozmiar[0] * rozmiar[0] - 1] << endl;
/*cout << "Macierz D na GPU:" << endl;
for (int i = 0; i < rozmiar[0] * rozmiar[0]; i++) {
if (i % rozmiar[0] == 0) cout << endl;
cout << D1[i] << " | ";
}
cout << endl;*/
cout << endl;
double stosunek;
if (duration_on_GPU != 0) {
stosunek = duration_on_CPU / duration_on_GPU;
cout << "Pierwsze obliczenia na GPU sa " << stosunek << " raza szybsze." << endl;
}
else {
cout << "Pierwszy czas na GPU jest zerowy, niemozliwe wyliczenie stosunku" << endl;
}
if (duration_on_GPU1 != 0) {
stosunek = duration_on_CPU1 / duration_on_GPU1;
cout << "Drugie obliczenia na GPU sa " << stosunek << " raza szybsze." << endl;
}
else {
cout << "Drugi czas na GPU jest zerowy, niemozliwe wyliczenie stosunku" << endl;
}
cout << endl;
double max = 0;
for (int i = 0; i < rozmiar[0] * rozmiar[0]; i++) {
if (abs(C.get_value(i / rozmiar[0], i % rozmiar[0]) - C1[i]) > max) max = abs(C.get_value(i / rozmiar[0], i % rozmiar[0]) - C1[i]);
}
if (max == 0) cout << "Nie ma roznicy miedzy macierzami C z CPU i GPU" << endl;
else cout << "W miejscu najwiekszej rozbieznosci macierze C roznia sie o " << max << endl;
max = 0;
for (int i = 0; i < rozmiar[0] * rozmiar[0]; i++) {
if (abs(D.get_value(i / rozmiar[0], i % rozmiar[0]) - D1[i]) > max) max = abs(D.get_value(i / rozmiar[0], i % rozmiar[0]) - D1[i]);
}
if (max == 0) cout << "Nie ma roznicy miedzy macierzami D z CPU i GPU" << endl;
else cout << "W miejscu najwiekszej rozbieznosci macierze D roznia sie o " << max << endl;
cout << endl;
A.free_memory();
B.free_memory();
C.free_memory();
D.free_memory();
hipFree(dev_rozmiar);
hipFree(dev_A);
hipFree(dev_B);
hipFree(dev_C);
hipFree(dev_D);
hipFree(dev_wynik);
delete[] A1;
delete[] B1;
delete[] C1;
delete[] D1;
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <iostream>
#include <cmath>
#include <time.h>
using namespace std;
class Matrix
{
private:
int rozmiar_macierzy;
double** macierz;
public:
Matrix(int rozmiar)
{
rozmiar_macierzy = rozmiar;
macierz = new double* [rozmiar];
for (int i = 0; i < rozmiar; i++) {
macierz[i] = new double[rozmiar];
}
}
void free_memory();
void random_values();
int get_size();
void set_value(int line, int column, double value);
double get_value(int line, int column);
Matrix transposition();
void write_matrix();
};
void Matrix::free_memory()
{
delete[] macierz;
}
void Matrix::random_values()
{
int rozmiar = rozmiar_macierzy;
for (int i = 0; i < rozmiar; i++) {
for (int j = 0; j < rozmiar; j++) {
macierz[i][j] = 2 * ((double)rand() / (double)RAND_MAX) - 1;
}
}
}
int Matrix::get_size()
{
return rozmiar_macierzy;
}
void Matrix::set_value(int line, int column, double value)
{
macierz[line][column] = value;
}
double Matrix::get_value(int line, int column)
{
return macierz[line][column];
}
Matrix Matrix::transposition()
{
int rozmiar = rozmiar_macierzy;
Matrix At(rozmiar);
for (int i = 0; i < rozmiar; i++) {
for (int j = 0; j < rozmiar; j++) {
At.set_value(i, j, macierz[j][i]);
}
}
return At;
}
void Matrix::write_matrix()
{
int rozmiar = rozmiar_macierzy;
for (int i = 0; i < rozmiar; i++) {
cout << "| ";
for (int j = 0; j < rozmiar; j++) {
cout << macierz[i][j] << " ";
}
cout << "|" << endl;
}
cout << endl;
}
Matrix multiplication(Matrix A, Matrix B)
{
int rozmiar = A.get_size();
double sum;
Matrix C(rozmiar);
for (int k = 0; k < rozmiar; k++) {
for (int l = 0; l < rozmiar; l++) {
sum = 0;
for (int m = 0; m < rozmiar; m++) {
sum = sum + A.get_value(k, m) * B.get_value(m, l);
}
C.set_value(k, l, sum);
}
}
return C;
}
Matrix addition(Matrix A, Matrix B)
{
int rozmiar = A.get_size();
double sum;
Matrix D(rozmiar);
for (int i = 0; i < rozmiar; i++) {
for (int j = 0; j < rozmiar; j++) {
sum = A.get_value(i, j) + B.get_value(i, j);
D.set_value(i, j, sum);
}
}
return D;
}
void copy_values(Matrix macierz1, double macierz2[])
{
int rozmiar = macierz1.get_size();
for (int i = 0; i < rozmiar*rozmiar; i++) {
macierz2[i] = macierz1.get_value(i/rozmiar, i%rozmiar);
}
}
__global__ void deviceTransposition(double* macierz1, double* macierz2, int* rozmiar)
{
unsigned long long int i = threadIdx.x + blockIdx.x * blockDim.x;
unsigned long long int siatka = blockDim.x * gridDim.x;
for (i; i < rozmiar[0]*rozmiar[0]; i += siatka) {
macierz2[i] = macierz1[(i%rozmiar[0])*rozmiar[0]+i/rozmiar[0]];
}
}
__global__ void deviceMultiplication(double* macierz1, double* macierz2, double* macierz3, int* rozmiar)
{
unsigned long long int i = threadIdx.x + blockIdx.x * blockDim.x;
unsigned long long int j = threadIdx.y + blockIdx.y * blockDim.y;
unsigned long long int siatkax = blockDim.x * gridDim.x;
unsigned long long int siatkay = blockDim.y * gridDim.y;
double sum;
for (i; i < rozmiar[0] * rozmiar[0]; i += siatkax) {
sum = 0;
for (j; j < rozmiar[0]; j += siatkay) {
sum = sum + macierz1[((i/rozmiar[0]) * rozmiar[0]) + j] * macierz2[i%rozmiar[0] + j*rozmiar[0]];
}
macierz3[i] = sum;
}
}
__global__ void deviceAddition(double* macierz1, double* macierz2, double* macierz3, int* rozmiar)
{
unsigned long long int i = threadIdx.x + blockIdx.x * blockDim.x;
unsigned long long int siatka = blockDim.x * gridDim.x;
for (i; i < rozmiar[0] * rozmiar[0]; i += siatka) {
macierz3[i] = macierz2[i] + macierz1[i];
}
}
int main()
{
srand(time(NULL));
while (true) {
int rozmiar[1];
cout << "Podaj rozmiar macierzy: ";
cin >> rozmiar[0];
Matrix A(rozmiar[0]);
Matrix B(rozmiar[0]);
Matrix C(rozmiar[0]);
Matrix D(rozmiar[0]);
A.random_values();
B.random_values();
/*cout << "macierz A:" << endl;
A.write_matrix();
cout << "macierz B:" << endl;
B.write_matrix();*/
clock_t start;
double duration_on_CPU;
start = clock();
C = multiplication(A, B);
/*cout << "Macierz C na CPU:" << endl;
C.write_matrix();*/
duration_on_CPU = 1000 * (clock() - start) / CLOCKS_PER_SEC;
cout << "A*B na CPU zajelo: " << duration_on_CPU << " milisekund." << endl;
double duration_on_CPU1;
start = clock();
D = addition(addition(multiplication(A, A.transposition()), multiplication(B, B.transposition())), multiplication(C, C.transposition()));
/*cout << "Macierz D na CPU:" << endl;
D.write_matrix();*/
duration_on_CPU1 = 1000 * (clock() - start) / CLOCKS_PER_SEC;
cout << "A*AT + B*BT + C*CT na CPU zajelo: " << duration_on_CPU1 << " milisekund." << endl;
cout << "Ostatni element C: " << C.get_value(rozmiar[0] - 1, rozmiar[0] - 1) << endl;
cout << "Ostatni element D: " << D.get_value(rozmiar[0] - 1, rozmiar[0] - 1) << endl;
double* A1 = new double[rozmiar[0] * rozmiar[0]];
double* B1 = new double[rozmiar[0] * rozmiar[0]];
double* C1 = new double[rozmiar[0] * rozmiar[0]];
double* D1 = new double[rozmiar[0] * rozmiar[0]];
copy_values(A, A1);
copy_values(B, B1);
double* dev_A;
double* dev_At;
double* dev_B;
double* dev_Bt;
double* dev_C;
double* dev_Ct;
double* dev_D;
double* dev_wynik;
double* dev_wynik1;
int* dev_rozmiar;
int rozmiarBloku = 1024;
int liczbaBlokow = (rozmiar[0] * rozmiar[0] + rozmiarBloku - 1) / rozmiarBloku;
int sization = rozmiar[0] * rozmiar[0] * sizeof(double);
hipMalloc((void**)&dev_rozmiar, sizeof(int));
hipMalloc((void**)&dev_A, sization);
hipMalloc((void**)&dev_At, sization);
hipMalloc((void**)&dev_B, sization);
hipMalloc((void**)&dev_Bt, sization);
hipMalloc((void**)&dev_C, sization);
hipMalloc((void**)&dev_Ct, sization);
hipMalloc((void**)&dev_D, sization);
hipMalloc((void**)&dev_wynik, sization);
hipMalloc((void**)&dev_wynik1, sization);
hipMemcpy(dev_A, A1, sization, hipMemcpyHostToDevice);
hipMemcpy(dev_B, B1, sization, hipMemcpyHostToDevice);
hipMemcpy(dev_rozmiar, rozmiar, sizeof(int), hipMemcpyHostToDevice);
clock_t start2;
double duration_on_GPU;
start2 = clock();
deviceMultiplication<<<liczbaBlokow, rozmiarBloku>>>(dev_A, dev_B, dev_C, dev_rozmiar);
hipDeviceSynchronize();
duration_on_GPU = 1000 * (clock() - start2) / CLOCKS_PER_SEC;
hipMemcpy(C1, dev_C, sization, hipMemcpyDeviceToHost);
cout << "A*B na GPU zajelo: " << duration_on_GPU << " milisekund." << endl;
/*cout << "Macierz C na GPU:" << endl;
for (int i = 0; i < rozmiar[0] * rozmiar[0]; i++) {
if (i % rozmiar[0] == 0) cout << endl;
cout << C1[i] << " | ";
}
cout << endl;*/
double duration_on_GPU1;
start2 = clock();
deviceTransposition<<<liczbaBlokow, rozmiarBloku>>>(dev_A, dev_At, dev_rozmiar);
hipDeviceSynchronize();
deviceMultiplication<<<liczbaBlokow, rozmiarBloku>>>(dev_A, dev_At, dev_D, dev_rozmiar);
hipDeviceSynchronize();
deviceTransposition<<<liczbaBlokow, rozmiarBloku>>>(dev_B, dev_Bt, dev_rozmiar);
hipDeviceSynchronize();
deviceMultiplication<<<liczbaBlokow, rozmiarBloku>>>(dev_B, dev_Bt, dev_wynik, dev_rozmiar);
hipDeviceSynchronize();
deviceTransposition<<<liczbaBlokow, rozmiarBloku>>>(dev_C, dev_Ct, dev_rozmiar);
hipDeviceSynchronize();
deviceMultiplication<<<liczbaBlokow, rozmiarBloku>>>(dev_C, dev_Ct, dev_wynik1, dev_rozmiar);
hipDeviceSynchronize();
deviceAddition<<<liczbaBlokow, rozmiarBloku>>>(dev_wynik, dev_D, dev_D, dev_rozmiar);
hipDeviceSynchronize();
deviceAddition<<<liczbaBlokow, rozmiarBloku>>>(dev_wynik1, dev_D, dev_D, dev_rozmiar);
hipDeviceSynchronize();
duration_on_GPU1 = 1000 * (clock() - start2) / CLOCKS_PER_SEC;
hipMemcpy(D1, dev_D, sization, hipMemcpyDeviceToHost);
cout << "A*AT + B*BT + C*CT na GPU zajelo: " << duration_on_GPU1 << " milisekund." << endl;
cout << "Ostatni element C: " << C1[rozmiar[0] * rozmiar[0] - 1] << endl;
cout << "Ostatni element D: " << D1[rozmiar[0] * rozmiar[0] - 1] << endl;
/*cout << "Macierz D na GPU:" << endl;
for (int i = 0; i < rozmiar[0] * rozmiar[0]; i++) {
if (i % rozmiar[0] == 0) cout << endl;
cout << D1[i] << " | ";
}
cout << endl;*/
cout << endl;
double stosunek;
if (duration_on_GPU != 0) {
stosunek = duration_on_CPU / duration_on_GPU;
cout << "Pierwsze obliczenia na GPU sa " << stosunek << " raza szybsze." << endl;
}
else {
cout << "Pierwszy czas na GPU jest zerowy, niemozliwe wyliczenie stosunku" << endl;
}
if (duration_on_GPU1 != 0) {
stosunek = duration_on_CPU1 / duration_on_GPU1;
cout << "Drugie obliczenia na GPU sa " << stosunek << " raza szybsze." << endl;
}
else {
cout << "Drugi czas na GPU jest zerowy, niemozliwe wyliczenie stosunku" << endl;
}
cout << endl;
double max = 0;
for (int i = 0; i < rozmiar[0] * rozmiar[0]; i++) {
if (abs(C.get_value(i / rozmiar[0], i % rozmiar[0]) - C1[i]) > max) max = abs(C.get_value(i / rozmiar[0], i % rozmiar[0]) - C1[i]);
}
if (max == 0) cout << "Nie ma roznicy miedzy macierzami C z CPU i GPU" << endl;
else cout << "W miejscu najwiekszej rozbieznosci macierze C roznia sie o " << max << endl;
max = 0;
for (int i = 0; i < rozmiar[0] * rozmiar[0]; i++) {
if (abs(D.get_value(i / rozmiar[0], i % rozmiar[0]) - D1[i]) > max) max = abs(D.get_value(i / rozmiar[0], i % rozmiar[0]) - D1[i]);
}
if (max == 0) cout << "Nie ma roznicy miedzy macierzami D z CPU i GPU" << endl;
else cout << "W miejscu najwiekszej rozbieznosci macierze D roznia sie o " << max << endl;
cout << endl;
A.free_memory();
B.free_memory();
C.free_memory();
D.free_memory();
hipFree(dev_rozmiar);
hipFree(dev_A);
hipFree(dev_B);
hipFree(dev_C);
hipFree(dev_D);
hipFree(dev_wynik);
delete[] A1;
delete[] B1;
delete[] C1;
delete[] D1;
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19deviceTranspositionPdS_Pi
.globl _Z19deviceTranspositionPdS_Pi
.p2align 8
.type _Z19deviceTranspositionPdS_Pi,@function
_Z19deviceTranspositionPdS_Pi:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b32 s6, s[0:1], 0x24
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_load_b32 s10, s[2:3], 0x0
s_and_b32 s8, s6, 0xffff
s_mov_b32 s3, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s10, s10
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmpx_gt_u32_e64 s2, v1
s_cbranch_execz .LBB0_7
s_ashr_i32 s11, s10, 31
v_cvt_f32_u32_e32 v0, s10
v_cvt_f32_u32_e32 v2, s11
s_load_b32 s12, s[4:5], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s9, 0
s_sub_i32 s1, 0, s10
s_mov_b32 s3, s9
v_fmamk_f32 v0, v2, 0x4f800000, v0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v0, v0
v_lshlrev_b64 v[5:6], 3, v[1:2]
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x5f7ffffc, v0
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s12, s8
s_mov_b32 s12, s9
v_add_co_u32 v5, vcc_lo, s6, v5
v_mul_f32_e32 v3, 0x2f800000, v0
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
s_lshl_b64 s[6:7], s[8:9], 3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_trunc_f32_e32 v4, v3
v_dual_mov_b32 v3, 0 :: v_dual_fmamk_f32 v0, v4, 0xcf800000, v0
v_cvt_u32_f32_e32 v9, v4
s_delay_alu instid0(VALU_DEP_2)
v_cvt_u32_f32_e32 v0, v0
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v4, v8, s10
v_mul_lo_u32 v12, v7, s11
v_mad_u64_u32 v[10:11], null, v7, s10, 0
v_lshlrev_b64 v[7:8], 3, v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add3_u32 v4, v11, v12, v4
v_sub_co_u32 v12, vcc_lo, v1, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_ci_u32_e32 v4, vcc_lo, v2, v4, vcc_lo
v_mul_lo_u32 v13, v12, s11
v_mad_u64_u32 v[10:11], null, v12, s10, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v4, s10
v_add3_u32 v11, v11, v13, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], 3, v[10:11]
v_add_co_u32 v4, vcc_lo, s4, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v11, vcc_lo
v_add_co_u32 v7, vcc_lo, v4, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, v10, v8, vcc_lo
v_add_co_u32 v1, vcc_lo, v1, s8
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
global_load_b64 v[7:8], v[7:8], off
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[1:2]
s_or_b32 s12, vcc_lo, s12
s_waitcnt vmcnt(0)
global_store_b64 v[5:6], v[7:8], off
v_add_co_u32 v5, s0, v5, s6
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s0, s7, v6, s0
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execz .LBB0_7
.LBB0_3:
v_or_b32_e32 v4, s11, v2
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ne_u64_e32 0, v[3:4]
s_xor_b32 s13, exec_lo, s0
s_cbranch_execz .LBB0_5
s_sub_u32 s0, 0, s10
s_subb_u32 s14, 0, s11
v_mul_hi_u32 v4, s0, v0
v_mul_lo_u32 v7, s0, v9
v_mul_lo_u32 v8, s14, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, v4, v7
v_mul_lo_u32 v7, s0, v0
v_add_nc_u32_e32 v4, v4, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v8, v0, v7
v_mul_lo_u32 v10, v0, v4
v_mul_hi_u32 v11, v0, v4
v_mul_hi_u32 v12, v9, v7
v_mul_lo_u32 v7, v9, v7
v_mul_hi_u32 v13, v9, v4
v_mul_lo_u32 v4, v9, v4
v_add_co_u32 v8, vcc_lo, v8, v10
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, v8, v7
v_add_co_ci_u32_e32 v7, vcc_lo, v10, v12, vcc_lo
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, v7, v4
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, v0, v4
v_add_co_ci_u32_e32 v7, vcc_lo, v9, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v8, s0, v4
v_mul_lo_u32 v11, s14, v4
v_mul_lo_u32 v10, s0, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v8, v8, v10
v_mul_lo_u32 v10, s0, v4
v_add_nc_u32_e32 v8, v8, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v11, v4, v10
v_mul_lo_u32 v12, v4, v8
v_mul_hi_u32 v13, v4, v8
v_mul_hi_u32 v14, v7, v10
v_mul_lo_u32 v10, v7, v10
v_mul_hi_u32 v15, v7, v8
v_mul_lo_u32 v8, v7, v8
v_add_co_u32 v11, vcc_lo, v11, v12
v_add_co_ci_u32_e32 v12, vcc_lo, 0, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, v11, v10
v_add_co_ci_u32_e32 v10, vcc_lo, v12, v14, vcc_lo
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v15, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, v10, v8
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, v4, v8
v_add_co_ci_u32_e32 v14, vcc_lo, v7, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v15, v1, v4
v_mad_u64_u32 v[10:11], null, v2, v4, 0
v_mad_u64_u32 v[7:8], null, v1, v14, 0
v_mad_u64_u32 v[12:13], null, v2, v14, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v15, v7
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, v4, v10
v_add_co_ci_u32_e32 v4, vcc_lo, v7, v11, vcc_lo
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, v4, v12
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v11, s11, v4
v_mad_u64_u32 v[7:8], null, s10, v4, 0
v_mul_lo_u32 v12, s10, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v7, vcc_lo, v1, v7
v_add3_u32 v8, v8, v12, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v11, v2, v8
v_subrev_co_ci_u32_e64 v11, s0, s11, v11, vcc_lo
v_add_co_u32 v12, s0, v4, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v13, s0, 0, v10, s0
v_sub_co_u32 v14, s0, v7, s10
v_sub_co_ci_u32_e32 v8, vcc_lo, v2, v8, vcc_lo
v_subrev_co_ci_u32_e64 v11, s0, 0, v11, s0
v_cmp_le_u32_e32 vcc_lo, s10, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cmp_eq_u32_e64 s0, s11, v8
v_cndmask_b32_e64 v14, 0, -1, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s11, v11
v_cndmask_b32_e64 v15, 0, -1, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s10, v7
v_cndmask_b32_e64 v7, 0, -1, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s11, v8
v_cndmask_b32_e64 v16, 0, -1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, s11, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v7, v16, v7, s0
v_cndmask_b32_e32 v11, v15, v14, vcc_lo
v_add_co_u32 v14, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v15, vcc_lo, 0, v10, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v11, v14, v12 :: v_dual_cndmask_b32 v8, v15, v13
v_cmp_ne_u32_e32 vcc_lo, 0, v7
v_dual_cndmask_b32 v7, v4, v11 :: v_dual_cndmask_b32 v8, v10, v8
.LBB0_5:
s_and_not1_saveexec_b32 s0, s13
s_cbranch_execz .LBB0_2
v_cvt_f32_u32_e32 v4, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v4, 0x4f7ffffe, v4
v_cvt_u32_f32_e32 v4, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v7, s1, v4
v_mul_hi_u32 v7, v4, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v4, v7
v_mul_hi_u32 v4, v1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v7, v4, s10
v_add_nc_u32_e32 v8, 1, v4
v_sub_nc_u32_e32 v7, v1, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v10, s10, v7
v_cmp_le_u32_e32 vcc_lo, s10, v7
v_dual_cndmask_b32 v7, v7, v10 :: v_dual_cndmask_b32 v4, v4, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s10, v7
v_add_nc_u32_e32 v8, 1, v4
s_delay_alu instid0(VALU_DEP_1)
v_dual_cndmask_b32 v7, v4, v8 :: v_dual_mov_b32 v8, v3
s_branch .LBB0_2
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19deviceTranspositionPdS_Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19deviceTranspositionPdS_Pi, .Lfunc_end0-_Z19deviceTranspositionPdS_Pi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z20deviceMultiplicationPdS_S_Pi
.globl _Z20deviceMultiplicationPdS_S_Pi
.p2align 8
.type _Z20deviceMultiplicationPdS_S_Pi,@function
_Z20deviceMultiplicationPdS_S_Pi:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b32 s6, s[0:1], 0x2c
v_and_b32_e32 v3, 0x3ff, v0
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[2:3], 0x0
s_and_b32 s3, s6, 0xffff
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s2, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmpx_gt_u32_e64 s8, v1
s_cbranch_execz .LBB1_11
s_clause 0x1
s_load_b32 s9, s[4:5], 0xc
s_load_b64 s[12:13], s[4:5], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[10:11], s[0:1], 0x10
v_bfe_u32 v0, v0, 10, 10
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, 0
s_mov_b32 s1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s14, s1
s_waitcnt lgkmcnt(0)
s_lshr_b32 s0, s9, 16
s_mul_i32 s12, s12, s3
v_mad_u64_u32 v[3:4], null, s15, s0, v[0:1]
v_mov_b32_e32 v4, v2
s_mul_i32 s13, s13, s0
s_mov_b32 s9, s1
s_ashr_i32 s3, s2, 31
s_mov_b32 s15, s1
s_branch .LBB1_3
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s16
v_lshlrev_b64 v[8:9], 3, v[1:2]
v_add_co_u32 v1, vcc_lo, v1, s12
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, s0, s10, v8
v_cmp_le_u64_e32 vcc_lo, s[8:9], v[1:2]
v_add_co_ci_u32_e64 v9, s0, s11, v9, s0
s_or_b32 s15, vcc_lo, s15
global_store_b64 v[8:9], v[6:7], off
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execz .LBB1_11
.LBB1_3:
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_mov_b32 s16, exec_lo
v_cmpx_gt_u64_e64 s[2:3], v[3:4]
s_cbranch_execz .LBB1_2
v_or_b32_e32 v6, s3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ne_u64_e32 vcc_lo, 0, v[5:6]
s_and_saveexec_b32 s0, vcc_lo
s_xor_b32 s17, exec_lo, s0
s_cbranch_execz .LBB1_6
v_cvt_f32_u32_e32 v0, s2
v_cvt_f32_u32_e32 v6, s3
s_sub_u32 s0, 0, s2
s_subb_u32 s18, 0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v0, 0x4f800000, v6
v_rcp_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x5f7ffffc, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, 0x2f800000, v0
v_trunc_f32_e32 v6, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v0, 0xcf800000, v6
v_cvt_u32_f32_e32 v6, v6
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v7, s0, v6
v_mul_hi_u32 v8, s0, v0
v_mul_lo_u32 v9, s18, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v7, v8, v7
v_mul_lo_u32 v8, s0, v0
v_add_nc_u32_e32 v7, v7, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v0, v8
v_mul_lo_u32 v10, v0, v7
v_mul_hi_u32 v11, v0, v7
v_mul_hi_u32 v12, v6, v8
v_mul_lo_u32 v8, v6, v8
v_mul_hi_u32 v13, v6, v7
v_mul_lo_u32 v7, v6, v7
v_add_co_u32 v9, vcc_lo, v9, v10
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, v9, v8
v_add_co_ci_u32_e32 v8, vcc_lo, v10, v12, vcc_lo
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, v8, v7
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v7
v_add_co_ci_u32_e32 v6, vcc_lo, v6, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v7, s0, v0
v_mul_lo_u32 v9, s18, v0
v_mul_lo_u32 v8, s0, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v7, v7, v8
v_mul_lo_u32 v8, s0, v0
v_add_nc_u32_e32 v7, v7, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v0, v8
v_mul_lo_u32 v10, v0, v7
v_mul_hi_u32 v11, v0, v7
v_mul_hi_u32 v12, v6, v8
v_mul_lo_u32 v8, v6, v8
v_mul_hi_u32 v13, v6, v7
v_mul_lo_u32 v7, v6, v7
v_add_co_u32 v9, vcc_lo, v9, v10
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, v9, v8
v_add_co_ci_u32_e32 v8, vcc_lo, v10, v12, vcc_lo
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, v8, v7
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v7
v_add_co_ci_u32_e32 v12, vcc_lo, v6, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v13, v1, v0
v_mad_u64_u32 v[8:9], null, v2, v0, 0
v_mad_u64_u32 v[6:7], null, v1, v12, 0
v_mad_u64_u32 v[10:11], null, v2, v12, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, v13, v6
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v8
v_add_co_ci_u32_e32 v0, vcc_lo, v6, v9, vcc_lo
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v10
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v9, s3, v0
v_mad_u64_u32 v[6:7], null, s2, v0, 0
v_mul_lo_u32 v0, s2, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v6, vcc_lo, v1, v6
v_add3_u32 v0, v7, v0, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v7, v2, v0
v_subrev_co_ci_u32_e64 v7, s0, s3, v7, vcc_lo
v_sub_co_ci_u32_e32 v0, vcc_lo, v2, v0, vcc_lo
v_sub_co_u32 v8, vcc_lo, v6, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_subrev_co_ci_u32_e64 v9, s0, 0, v7, vcc_lo
v_cmp_le_u32_e64 s0, s2, v6
v_subrev_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s3, v0
v_cndmask_b32_e64 v10, 0, -1, s0
v_cmp_le_u32_e64 s0, s2, v8
v_cndmask_b32_e64 v13, 0, -1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, s3, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v11, 0, -1, s0
v_cmp_le_u32_e64 s0, s3, v9
v_cndmask_b32_e64 v12, 0, -1, s0
v_cmp_eq_u32_e64 s0, s3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v11, v12, v11, vcc_lo
v_sub_co_u32 v12, vcc_lo, v8, s2
v_subrev_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v11
v_cndmask_b32_e64 v10, v13, v10, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v7, v9, v7 :: v_dual_cndmask_b32 v8, v8, v12
v_cmp_ne_u32_e32 vcc_lo, 0, v10
s_delay_alu instid0(VALU_DEP_2)
v_dual_cndmask_b32 v7, v0, v7 :: v_dual_cndmask_b32 v6, v6, v8
.LBB1_6:
s_and_not1_saveexec_b32 s0, s17
s_cbranch_execz .LBB1_8
v_cvt_f32_u32_e32 v0, s2
s_sub_i32 s17, 0, s2
v_mov_b32_e32 v7, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v6, s17, v0
v_mul_hi_u32 v6, v0, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v6
v_mul_hi_u32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, s2
v_sub_nc_u32_e32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v6, s2, v0
v_cmp_le_u32_e32 vcc_lo, s2, v0
v_cndmask_b32_e32 v0, v0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v6, s2, v0
v_cmp_le_u32_e32 vcc_lo, s2, v0
v_cndmask_b32_e32 v6, v0, v6, vcc_lo
.LBB1_8:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_sub_co_u32 v8, vcc_lo, v1, v6
v_sub_co_ci_u32_e32 v9, vcc_lo, v2, v7, vcc_lo
v_lshlrev_b64 v[10:11], 3, v[6:7]
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
v_lshlrev_b64 v[8:9], 3, v[8:9]
s_mov_b32 s0, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v9, vcc_lo
v_add_co_u32 v9, vcc_lo, s6, v10
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v11, vcc_lo
.p2align 6
.LBB1_9:
v_mul_lo_u32 v15, v4, s2
v_mul_lo_u32 v16, v3, s3
v_mad_u64_u32 v[11:12], null, v3, s2, 0
v_lshlrev_b64 v[13:14], 3, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v13, vcc_lo, v0, v13
v_add3_u32 v12, v12, v16, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v14, vcc_lo, v8, v14, vcc_lo
v_lshlrev_b64 v[11:12], 3, v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v11, vcc_lo, v9, v11
v_add_co_ci_u32_e32 v12, vcc_lo, v10, v12, vcc_lo
global_load_b64 v[13:14], v[13:14], off
global_load_b64 v[11:12], v[11:12], off
v_add_co_u32 v3, vcc_lo, v3, s13
v_add_co_ci_u32_e32 v4, vcc_lo, s14, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[3:4]
s_or_b32 s0, vcc_lo, s0
s_waitcnt vmcnt(0)
v_fma_f64 v[6:7], v[13:14], v[11:12], v[6:7]
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB1_9
s_or_b32 exec_lo, exec_lo, s0
s_branch .LBB1_2
.LBB1_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20deviceMultiplicationPdS_S_Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 19
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z20deviceMultiplicationPdS_S_Pi, .Lfunc_end1-_Z20deviceMultiplicationPdS_S_Pi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z14deviceAdditionPdS_S_Pi
.globl _Z14deviceAdditionPdS_S_Pi
.p2align 8
.type _Z14deviceAdditionPdS_S_Pi,@function
_Z14deviceAdditionPdS_S_Pi:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b32 s6, s[0:1], 0x2c
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[2:3], 0x0
s_and_b32 s3, s6, 0xffff
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmpx_gt_u32_e64 s2, v1
s_cbranch_execz .LBB2_3
s_load_b32 s10, s[4:5], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
v_mov_b32_e32 v2, 0
s_mov_b32 s11, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mov_b32 s1, s11
v_lshlrev_b64 v[3:4], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s10, s10, s3
s_mov_b32 s3, s11
s_lshl_b64 s[12:13], s[10:11], 3
.p2align 6
.LBB2_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v5, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v7, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v1, vcc_lo, v1, s10
global_load_b64 v[5:6], v[5:6], off
global_load_b64 v[7:8], v[7:8], off
v_add_co_ci_u32_e32 v2, vcc_lo, s11, v2, vcc_lo
s_waitcnt vmcnt(0)
v_add_f64 v[5:6], v[5:6], v[7:8]
v_add_co_u32 v7, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s9, v4, vcc_lo
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[1:2]
v_add_co_u32 v3, s0, v3, s12
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s0, s13, v4, s0
s_or_b32 s1, vcc_lo, s1
global_store_b64 v[7:8], v[5:6], off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB2_2
.LBB2_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14deviceAdditionPdS_S_Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z14deviceAdditionPdS_S_Pi, .Lfunc_end2-_Z14deviceAdditionPdS_S_Pi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19deviceTranspositionPdS_Pi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19deviceTranspositionPdS_Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20deviceMultiplicationPdS_S_Pi
.private_segment_fixed_size: 0
.sgpr_count: 21
.sgpr_spill_count: 0
.symbol: _Z20deviceMultiplicationPdS_S_Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14deviceAdditionPdS_S_Pi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14deviceAdditionPdS_S_Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
Erick Juarez
CPSC 479 Sec 1
HOMEWORK 5 - 3/25/20
tested using nvcc - CUDA compiler driver release 9.0, V9.0.176
*/
#include <stdio.h>
#include <cuda.h>
#define P1 16 // Size of array for problem 1
#define P2 1024 // Size of array for problems 2 & 3
#define P4 8000 // Size of array for problem 4
// device function to initialize array - used in problems 1 & 2
__global__ void initialize(int *array){
array[threadIdx.x] = 0;
}
// device function will add values to array - used in problems 3 & 4
__global__ void add(int *array){
array[threadIdx.x] += threadIdx.x;
}
// Main function
int main(int argc, char * argv[]) {
int *host_array; // host copy of array
int *dev_array; // device copy of array
int byte_size; // size in bytes of an object
/////////////////////////////////////////////////////////////////////////////////////////////////////////
// Problem 1 - initialize array of size 16 to all zeroes
byte_size = P1 * sizeof(int); // get size of 16 integers in bytes
dim3 blockd(P1); // Create dim3 type with value of 16 on the first dimension
cudaMalloc((void **) &dev_array, byte_size); // Allocate memory on the device
initialize<<<1, blockd>>>(dev_array); // Launch new kernel on device with 16 threads
host_array = (int *)malloc(byte_size); // Allocate memory for the host
cudaMemcpy(host_array, dev_array, byte_size, cudaMemcpyDeviceToHost); // Copy from device to host
// Verify that array was allocated and copied properly to the host, then cleanup
try {
for(int c = 0; c < P1; c++){
if(host_array[c] != 0) {throw "NON_ZERO_ELEM";}
}
} catch (...) {
printf("Problem 1 - Elements not initialized properly!\n");
cudaFree(dev_array);
free(host_array);
return 0;
}
printf("Problem 1 - Successfully initialized array with %d elements\n", P1);
cudaFree(dev_array);
free(host_array);
/////////////////////////////////////////////////////////////////////////////////////////////////////////
// Problem 2 - initialize array of size 1024 to all zeroes
byte_size = P2 * sizeof(int); // get size of 1024 integers in bytes
dim3 bd(P2); // create dim3 object with 1024 as the first dimensoin
cudaMalloc((void**) &dev_array, byte_size); // Allocate memory on device
initialize<<<1, bd>>>(dev_array); // Launch kernel on device with 1024 threads
host_array = (int*)malloc(byte_size); // Allocate memory on the host
cudaMemcpy(host_array, dev_array, byte_size, cudaMemcpyDeviceToHost); // Copy from device to host
// Verify that array was allocated and copied properly, then cleanup
try {
for(int c = 0; c < P2; c++){
if(host_array[c] != 0) {throw "NON_ZERO_ELEM";}
}
} catch (...) {
printf("Problem 2 - Elements not initialized properly!\n");
cudaFree(dev_array);
free(host_array);
return 0;
}
printf("Problem 2 - Successfully initialized array with %d elements\n", P2);
/////////////////////////////////////////////////////////////////////////////////////////////////////////
// Problem 3 - add i to array[i]
add<<<1, bd>>>(dev_array); // Launch add kernel with array from the previous problem
cudaMemcpy(host_array, dev_array, byte_size, cudaMemcpyDeviceToHost); // Copy from modified vaues to host
// Verify values are correct
try {
for(int c = 0; c < P2; c++){
if(host_array[c] != c) {throw "ADD_OP_MATCH";}
}
} catch (...) {
printf("Problem 3 - Elements not added properly!\n");
cudaFree(dev_array);
free(host_array);
return 0;
}
printf("Problem 3 - Successfully added i to array[i] with %d elements\n", P2);
cudaFree(dev_array);
free(host_array);
///////////////////////////////////////////////////////////////////////////////////////////////////////////
// Problem 4 - same as problem 3, but with 8000 elements
byte_size = P4 * sizeof(int);
dim3 gd(P4);
cudaMalloc((void**) &dev_array, byte_size);
initialize<<<1, gd>>>(dev_array); // Initialize array
add<<<1, gd>>>(dev_array); // Add index to array
host_array = (int*)malloc(byte_size);
cudaMemcpy(host_array, dev_array, byte_size, cudaMemcpyDeviceToHost);
// Verify values are correct, 8000 threads might be too much for the device and the answer is incorrect
try {
for(int c = 0; c < P4; c++){
if(host_array[c] != c) {throw "ADD_OP_MATCH";}
}
} catch (...) {
printf("Problem 4 - Elements not added properly!\n");
cudaFree(dev_array);
free(host_array);
return 0;
}
printf("Problem 4 - Successfully added i to array[i] with %d elements\n", P4);
cudaFree(dev_array);
free(host_array);
return 0;
} | code for sm_80
Function : _Z3addPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x001fca00078e0002 */
/*0050*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0060*/ IADD3 R5, R0, R5, RZ ; /* 0x0000000500057210 */
/* 0x004fca0007ffe0ff */
/*0070*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10initializePi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x001fca00078e0003 */
/*0050*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*0060*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0070*/ BRA 0x70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
Erick Juarez
CPSC 479 Sec 1
HOMEWORK 5 - 3/25/20
tested using nvcc - CUDA compiler driver release 9.0, V9.0.176
*/
#include <stdio.h>
#include <cuda.h>
#define P1 16 // Size of array for problem 1
#define P2 1024 // Size of array for problems 2 & 3
#define P4 8000 // Size of array for problem 4
// device function to initialize array - used in problems 1 & 2
__global__ void initialize(int *array){
array[threadIdx.x] = 0;
}
// device function will add values to array - used in problems 3 & 4
__global__ void add(int *array){
array[threadIdx.x] += threadIdx.x;
}
// Main function
int main(int argc, char * argv[]) {
int *host_array; // host copy of array
int *dev_array; // device copy of array
int byte_size; // size in bytes of an object
/////////////////////////////////////////////////////////////////////////////////////////////////////////
// Problem 1 - initialize array of size 16 to all zeroes
byte_size = P1 * sizeof(int); // get size of 16 integers in bytes
dim3 blockd(P1); // Create dim3 type with value of 16 on the first dimension
cudaMalloc((void **) &dev_array, byte_size); // Allocate memory on the device
initialize<<<1, blockd>>>(dev_array); // Launch new kernel on device with 16 threads
host_array = (int *)malloc(byte_size); // Allocate memory for the host
cudaMemcpy(host_array, dev_array, byte_size, cudaMemcpyDeviceToHost); // Copy from device to host
// Verify that array was allocated and copied properly to the host, then cleanup
try {
for(int c = 0; c < P1; c++){
if(host_array[c] != 0) {throw "NON_ZERO_ELEM";}
}
} catch (...) {
printf("Problem 1 - Elements not initialized properly!\n");
cudaFree(dev_array);
free(host_array);
return 0;
}
printf("Problem 1 - Successfully initialized array with %d elements\n", P1);
cudaFree(dev_array);
free(host_array);
/////////////////////////////////////////////////////////////////////////////////////////////////////////
// Problem 2 - initialize array of size 1024 to all zeroes
byte_size = P2 * sizeof(int); // get size of 1024 integers in bytes
dim3 bd(P2); // create dim3 object with 1024 as the first dimensoin
cudaMalloc((void**) &dev_array, byte_size); // Allocate memory on device
initialize<<<1, bd>>>(dev_array); // Launch kernel on device with 1024 threads
host_array = (int*)malloc(byte_size); // Allocate memory on the host
cudaMemcpy(host_array, dev_array, byte_size, cudaMemcpyDeviceToHost); // Copy from device to host
// Verify that array was allocated and copied properly, then cleanup
try {
for(int c = 0; c < P2; c++){
if(host_array[c] != 0) {throw "NON_ZERO_ELEM";}
}
} catch (...) {
printf("Problem 2 - Elements not initialized properly!\n");
cudaFree(dev_array);
free(host_array);
return 0;
}
printf("Problem 2 - Successfully initialized array with %d elements\n", P2);
/////////////////////////////////////////////////////////////////////////////////////////////////////////
// Problem 3 - add i to array[i]
add<<<1, bd>>>(dev_array); // Launch add kernel with array from the previous problem
cudaMemcpy(host_array, dev_array, byte_size, cudaMemcpyDeviceToHost); // Copy from modified vaues to host
// Verify values are correct
try {
for(int c = 0; c < P2; c++){
if(host_array[c] != c) {throw "ADD_OP_MATCH";}
}
} catch (...) {
printf("Problem 3 - Elements not added properly!\n");
cudaFree(dev_array);
free(host_array);
return 0;
}
printf("Problem 3 - Successfully added i to array[i] with %d elements\n", P2);
cudaFree(dev_array);
free(host_array);
///////////////////////////////////////////////////////////////////////////////////////////////////////////
// Problem 4 - same as problem 3, but with 8000 elements
byte_size = P4 * sizeof(int);
dim3 gd(P4);
cudaMalloc((void**) &dev_array, byte_size);
initialize<<<1, gd>>>(dev_array); // Initialize array
add<<<1, gd>>>(dev_array); // Add index to array
host_array = (int*)malloc(byte_size);
cudaMemcpy(host_array, dev_array, byte_size, cudaMemcpyDeviceToHost);
// Verify values are correct, 8000 threads might be too much for the device and the answer is incorrect
try {
for(int c = 0; c < P4; c++){
if(host_array[c] != c) {throw "ADD_OP_MATCH";}
}
} catch (...) {
printf("Problem 4 - Elements not added properly!\n");
cudaFree(dev_array);
free(host_array);
return 0;
}
printf("Problem 4 - Successfully added i to array[i] with %d elements\n", P4);
cudaFree(dev_array);
free(host_array);
return 0;
} | .file "tmpxft_000ab854_00000000-6_cuda-threads.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z10initializePiPi
.type _Z30__device_stub__Z10initializePiPi, @function
_Z30__device_stub__Z10initializePiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10initializePi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z10initializePiPi, .-_Z30__device_stub__Z10initializePiPi
.globl _Z10initializePi
.type _Z10initializePi, @function
_Z10initializePi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10initializePiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10initializePi, .-_Z10initializePi
.globl _Z22__device_stub__Z3addPiPi
.type _Z22__device_stub__Z3addPiPi, @function
_Z22__device_stub__Z3addPiPi:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3addPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z22__device_stub__Z3addPiPi, .-_Z22__device_stub__Z3addPiPi
.globl _Z3addPi
.type _Z3addPi, @function
_Z3addPi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z3addPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z3addPi, .-_Z3addPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "NON_ZERO_ELEM"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Problem 1 - Successfully initialized array with %d elements\n"
.align 8
.LC2:
.string "Problem 2 - Successfully initialized array with %d elements\n"
.section .rodata.str1.1
.LC3:
.string "ADD_OP_MATCH"
.section .rodata.str1.8
.align 8
.LC4:
.string "Problem 3 - Successfully added i to array[i] with %d elements\n"
.align 8
.LC5:
.string "Problem 4 - Successfully added i to array[i] with %d elements\n"
.align 8
.LC6:
.string "Problem 1 - Elements not initialized properly!\n"
.align 8
.LC7:
.string "Problem 2 - Elements not initialized properly!\n"
.align 8
.LC8:
.string "Problem 3 - Elements not added properly!\n"
.align 8
.LC9:
.string "Problem 4 - Elements not added properly!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA2057
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $16, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movq %rsp, %rdi
movl $64, %esi
.LEHB0:
call cudaMalloc@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl 16(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L65
.L20:
movl $64, %edi
call malloc@PLT
movq %rax, %rbx
movl $2, %ecx
movl $64, %edx
movq (%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movq %rbx, %rax
leaq 64(%rbx), %rdx
.L23:
cmpl $0, (%rax)
jne .L66
addq $4, %rax
cmpq %rdx, %rax
jne .L23
movl $16, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movq %rsp, %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl 28(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L67
.L24:
movl $4096, %edi
call malloc@PLT
movq %rax, %rbx
movl $2, %ecx
movl $4096, %edx
movq (%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movq %rbx, %rax
leaq 4096(%rbx), %rdx
.L27:
cmpl $0, (%rax)
jne .L68
addq $4, %rax
cmpq %rdx, %rax
jne .L27
movl $1024, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl 28(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L69
.L28:
movl $2, %ecx
movl $4096, %edx
movq (%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $0, %eax
.L31:
cmpl %eax, (%rbx,%rax,4)
jne .L70
addq $1, %rax
cmpq $1024, %rax
jne .L31
movl $1024, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movl $8000, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movq %rsp, %rdi
movl $32000, %esi
call cudaMalloc@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L71
.L32:
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L72
.L33:
movl $32000, %edi
call malloc@PLT
movq %rax, %rbx
movl $2, %ecx
movl $32000, %edx
movq (%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movl $0, %eax
.L36:
cmpl %eax, (%rbx,%rax,4)
jne .L73
addq $1, %rax
cmpq $8000, %rax
jne .L36
movl $8000, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
.L38:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L74
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L65:
.cfi_restore_state
movq (%rsp), %rdi
call _Z30__device_stub__Z10initializePiPi
.LEHE0:
jmp .L20
.L66:
movl $8, %edi
call __cxa_allocate_exception@PLT
movq %rax, %rdi
leaq .LC0(%rip), %rax
movq %rax, (%rdi)
movq 56(%rsp), %rax
subq %fs:40, %rax
je .L22
call __stack_chk_fail@PLT
.L22:
movl $0, %edx
leaq _ZTIPKc(%rip), %rsi
.LEHB1:
call __cxa_throw@PLT
.LEHE1:
.L51:
endbr64
movq %rax, %rdi
call __cxa_begin_catch@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
.LEHB2:
call __printf_chk@PLT
.LEHE2:
jmp .L75
.L67:
movq (%rsp), %rdi
.LEHB3:
call _Z30__device_stub__Z10initializePiPi
.LEHE3:
jmp .L24
.L68:
movl $8, %edi
call __cxa_allocate_exception@PLT
movq %rax, %rdi
leaq .LC0(%rip), %rax
movq %rax, (%rdi)
movq 56(%rsp), %rax
subq %fs:40, %rax
je .L26
call __stack_chk_fail@PLT
.L26:
movl $0, %edx
leaq _ZTIPKc(%rip), %rsi
.LEHB4:
call __cxa_throw@PLT
.LEHE4:
.L53:
endbr64
movq %rax, %rdi
call __cxa_begin_catch@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
.LEHB5:
call __printf_chk@PLT
.LEHE5:
jmp .L76
.L69:
movq (%rsp), %rdi
.LEHB6:
call _Z22__device_stub__Z3addPiPi
.LEHE6:
jmp .L28
.L70:
movl $8, %edi
call __cxa_allocate_exception@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rax
movq %rax, (%rdi)
movq 56(%rsp), %rax
subq %fs:40, %rax
je .L30
call __stack_chk_fail@PLT
.L30:
movl $0, %edx
leaq _ZTIPKc(%rip), %rsi
.LEHB7:
call __cxa_throw@PLT
.LEHE7:
.L55:
endbr64
movq %rax, %rdi
call __cxa_begin_catch@PLT
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
.LEHB8:
call __printf_chk@PLT
.LEHE8:
jmp .L77
.L71:
movq (%rsp), %rdi
.LEHB9:
call _Z30__device_stub__Z10initializePiPi
jmp .L32
.L72:
movq (%rsp), %rdi
call _Z22__device_stub__Z3addPiPi
.LEHE9:
jmp .L33
.L73:
movl $8, %edi
call __cxa_allocate_exception@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rax
movq %rax, (%rdi)
movq 56(%rsp), %rax
subq %fs:40, %rax
je .L35
call __stack_chk_fail@PLT
.L35:
movl $0, %edx
leaq _ZTIPKc(%rip), %rsi
.LEHB10:
call __cxa_throw@PLT
.LEHE10:
.L57:
endbr64
movq %rax, %rdi
call __cxa_begin_catch@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
.LEHB11:
call __printf_chk@PLT
.LEHE11:
jmp .L78
.L75:
movq (%rsp), %rdi
.LEHB12:
call cudaFree@PLT
.LEHE12:
movq %rbx, %rdi
call free@PLT
.LEHB13:
call __cxa_end_catch@PLT
.LEHE13:
jmp .L38
.L52:
endbr64
movq %rax, %rbx
call __cxa_end_catch@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
je .L40
call __stack_chk_fail@PLT
.L40:
movq %rbx, %rdi
.LEHB14:
call _Unwind_Resume@PLT
.LEHE14:
.L76:
movq (%rsp), %rdi
.LEHB15:
call cudaFree@PLT
.LEHE15:
movq %rbx, %rdi
call free@PLT
.LEHB16:
call __cxa_end_catch@PLT
.LEHE16:
jmp .L38
.L54:
endbr64
movq %rax, %rbx
call __cxa_end_catch@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
je .L43
call __stack_chk_fail@PLT
.L43:
movq %rbx, %rdi
.LEHB17:
call _Unwind_Resume@PLT
.LEHE17:
.L77:
movq (%rsp), %rdi
.LEHB18:
call cudaFree@PLT
.LEHE18:
movq %rbx, %rdi
call free@PLT
.LEHB19:
call __cxa_end_catch@PLT
.LEHE19:
jmp .L38
.L56:
endbr64
movq %rax, %rbx
call __cxa_end_catch@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
je .L46
call __stack_chk_fail@PLT
.L46:
movq %rbx, %rdi
.LEHB20:
call _Unwind_Resume@PLT
.LEHE20:
.L78:
movq (%rsp), %rdi
.LEHB21:
call cudaFree@PLT
.LEHE21:
movq %rbx, %rdi
call free@PLT
.LEHB22:
call __cxa_end_catch@PLT
.LEHE22:
jmp .L38
.L58:
endbr64
movq %rax, %rbx
call __cxa_end_catch@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
je .L49
call __stack_chk_fail@PLT
.L49:
movq %rbx, %rdi
.LEHB23:
call _Unwind_Resume@PLT
.LEHE23:
.L74:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.align 4
.LLSDA2057:
.byte 0xff
.byte 0x9b
.uleb128 .LLSDATT2057-.LLSDATTD2057
.LLSDATTD2057:
.byte 0x1
.uleb128 .LLSDACSE2057-.LLSDACSB2057
.LLSDACSB2057:
.uleb128 .LEHB0-.LFB2057
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB2057
.uleb128 .LEHE1-.LEHB1
.uleb128 .L51-.LFB2057
.uleb128 0x1
.uleb128 .LEHB2-.LFB2057
.uleb128 .LEHE2-.LEHB2
.uleb128 .L52-.LFB2057
.uleb128 0
.uleb128 .LEHB3-.LFB2057
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.uleb128 .LEHB4-.LFB2057
.uleb128 .LEHE4-.LEHB4
.uleb128 .L53-.LFB2057
.uleb128 0x1
.uleb128 .LEHB5-.LFB2057
.uleb128 .LEHE5-.LEHB5
.uleb128 .L54-.LFB2057
.uleb128 0
.uleb128 .LEHB6-.LFB2057
.uleb128 .LEHE6-.LEHB6
.uleb128 0
.uleb128 0
.uleb128 .LEHB7-.LFB2057
.uleb128 .LEHE7-.LEHB7
.uleb128 .L55-.LFB2057
.uleb128 0x1
.uleb128 .LEHB8-.LFB2057
.uleb128 .LEHE8-.LEHB8
.uleb128 .L56-.LFB2057
.uleb128 0
.uleb128 .LEHB9-.LFB2057
.uleb128 .LEHE9-.LEHB9
.uleb128 0
.uleb128 0
.uleb128 .LEHB10-.LFB2057
.uleb128 .LEHE10-.LEHB10
.uleb128 .L57-.LFB2057
.uleb128 0x1
.uleb128 .LEHB11-.LFB2057
.uleb128 .LEHE11-.LEHB11
.uleb128 .L58-.LFB2057
.uleb128 0
.uleb128 .LEHB12-.LFB2057
.uleb128 .LEHE12-.LEHB12
.uleb128 .L52-.LFB2057
.uleb128 0
.uleb128 .LEHB13-.LFB2057
.uleb128 .LEHE13-.LEHB13
.uleb128 0
.uleb128 0
.uleb128 .LEHB14-.LFB2057
.uleb128 .LEHE14-.LEHB14
.uleb128 0
.uleb128 0
.uleb128 .LEHB15-.LFB2057
.uleb128 .LEHE15-.LEHB15
.uleb128 .L54-.LFB2057
.uleb128 0
.uleb128 .LEHB16-.LFB2057
.uleb128 .LEHE16-.LEHB16
.uleb128 0
.uleb128 0
.uleb128 .LEHB17-.LFB2057
.uleb128 .LEHE17-.LEHB17
.uleb128 0
.uleb128 0
.uleb128 .LEHB18-.LFB2057
.uleb128 .LEHE18-.LEHB18
.uleb128 .L56-.LFB2057
.uleb128 0
.uleb128 .LEHB19-.LFB2057
.uleb128 .LEHE19-.LEHB19
.uleb128 0
.uleb128 0
.uleb128 .LEHB20-.LFB2057
.uleb128 .LEHE20-.LEHB20
.uleb128 0
.uleb128 0
.uleb128 .LEHB21-.LFB2057
.uleb128 .LEHE21-.LEHB21
.uleb128 .L58-.LFB2057
.uleb128 0
.uleb128 .LEHB22-.LFB2057
.uleb128 .LEHE22-.LEHB22
.uleb128 0
.uleb128 0
.uleb128 .LEHB23-.LFB2057
.uleb128 .LEHE23-.LEHB23
.uleb128 0
.uleb128 0
.LLSDACSE2057:
.byte 0x1
.byte 0
.align 4
.long 0
.LLSDATT2057:
.text
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z3addPi"
.LC11:
.string "_Z10initializePi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z10initializePi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
Erick Juarez
CPSC 479 Sec 1
HOMEWORK 5 - 3/25/20
tested using nvcc - CUDA compiler driver release 9.0, V9.0.176
*/
#include <stdio.h>
#include <cuda.h>
#define P1 16 // Size of array for problem 1
#define P2 1024 // Size of array for problems 2 & 3
#define P4 8000 // Size of array for problem 4
// device function to initialize array - used in problems 1 & 2
__global__ void initialize(int *array){
array[threadIdx.x] = 0;
}
// device function will add values to array - used in problems 3 & 4
__global__ void add(int *array){
array[threadIdx.x] += threadIdx.x;
}
// Main function
int main(int argc, char * argv[]) {
int *host_array; // host copy of array
int *dev_array; // device copy of array
int byte_size; // size in bytes of an object
/////////////////////////////////////////////////////////////////////////////////////////////////////////
// Problem 1 - initialize array of size 16 to all zeroes
byte_size = P1 * sizeof(int); // get size of 16 integers in bytes
dim3 blockd(P1); // Create dim3 type with value of 16 on the first dimension
cudaMalloc((void **) &dev_array, byte_size); // Allocate memory on the device
initialize<<<1, blockd>>>(dev_array); // Launch new kernel on device with 16 threads
host_array = (int *)malloc(byte_size); // Allocate memory for the host
cudaMemcpy(host_array, dev_array, byte_size, cudaMemcpyDeviceToHost); // Copy from device to host
// Verify that array was allocated and copied properly to the host, then cleanup
try {
for(int c = 0; c < P1; c++){
if(host_array[c] != 0) {throw "NON_ZERO_ELEM";}
}
} catch (...) {
printf("Problem 1 - Elements not initialized properly!\n");
cudaFree(dev_array);
free(host_array);
return 0;
}
printf("Problem 1 - Successfully initialized array with %d elements\n", P1);
cudaFree(dev_array);
free(host_array);
/////////////////////////////////////////////////////////////////////////////////////////////////////////
// Problem 2 - initialize array of size 1024 to all zeroes
byte_size = P2 * sizeof(int); // get size of 1024 integers in bytes
dim3 bd(P2); // create dim3 object with 1024 as the first dimensoin
cudaMalloc((void**) &dev_array, byte_size); // Allocate memory on device
initialize<<<1, bd>>>(dev_array); // Launch kernel on device with 1024 threads
host_array = (int*)malloc(byte_size); // Allocate memory on the host
cudaMemcpy(host_array, dev_array, byte_size, cudaMemcpyDeviceToHost); // Copy from device to host
// Verify that array was allocated and copied properly, then cleanup
try {
for(int c = 0; c < P2; c++){
if(host_array[c] != 0) {throw "NON_ZERO_ELEM";}
}
} catch (...) {
printf("Problem 2 - Elements not initialized properly!\n");
cudaFree(dev_array);
free(host_array);
return 0;
}
printf("Problem 2 - Successfully initialized array with %d elements\n", P2);
/////////////////////////////////////////////////////////////////////////////////////////////////////////
// Problem 3 - add i to array[i]
add<<<1, bd>>>(dev_array); // Launch add kernel with array from the previous problem
cudaMemcpy(host_array, dev_array, byte_size, cudaMemcpyDeviceToHost); // Copy from modified vaues to host
// Verify values are correct
try {
for(int c = 0; c < P2; c++){
if(host_array[c] != c) {throw "ADD_OP_MATCH";}
}
} catch (...) {
printf("Problem 3 - Elements not added properly!\n");
cudaFree(dev_array);
free(host_array);
return 0;
}
printf("Problem 3 - Successfully added i to array[i] with %d elements\n", P2);
cudaFree(dev_array);
free(host_array);
///////////////////////////////////////////////////////////////////////////////////////////////////////////
// Problem 4 - same as problem 3, but with 8000 elements
byte_size = P4 * sizeof(int);
dim3 gd(P4);
cudaMalloc((void**) &dev_array, byte_size);
initialize<<<1, gd>>>(dev_array); // Initialize array
add<<<1, gd>>>(dev_array); // Add index to array
host_array = (int*)malloc(byte_size);
cudaMemcpy(host_array, dev_array, byte_size, cudaMemcpyDeviceToHost);
// Verify values are correct, 8000 threads might be too much for the device and the answer is incorrect
try {
for(int c = 0; c < P4; c++){
if(host_array[c] != c) {throw "ADD_OP_MATCH";}
}
} catch (...) {
printf("Problem 4 - Elements not added properly!\n");
cudaFree(dev_array);
free(host_array);
return 0;
}
printf("Problem 4 - Successfully added i to array[i] with %d elements\n", P4);
cudaFree(dev_array);
free(host_array);
return 0;
} | /*
Erick Juarez
CPSC 479 Sec 1
HOMEWORK 5 - 3/25/20
tested using nvcc - CUDA compiler driver release 9.0, V9.0.176
*/
#include <stdio.h>
#include <hip/hip_runtime.h>
#define P1 16 // Size of array for problem 1
#define P2 1024 // Size of array for problems 2 & 3
#define P4 8000 // Size of array for problem 4
// device function to initialize array - used in problems 1 & 2
__global__ void initialize(int *array){
array[threadIdx.x] = 0;
}
// device function will add values to array - used in problems 3 & 4
__global__ void add(int *array){
array[threadIdx.x] += threadIdx.x;
}
// Main function
int main(int argc, char * argv[]) {
int *host_array; // host copy of array
int *dev_array; // device copy of array
int byte_size; // size in bytes of an object
/////////////////////////////////////////////////////////////////////////////////////////////////////////
// Problem 1 - initialize array of size 16 to all zeroes
byte_size = P1 * sizeof(int); // get size of 16 integers in bytes
dim3 blockd(P1); // Create dim3 type with value of 16 on the first dimension
hipMalloc((void **) &dev_array, byte_size); // Allocate memory on the device
initialize<<<1, blockd>>>(dev_array); // Launch new kernel on device with 16 threads
host_array = (int *)malloc(byte_size); // Allocate memory for the host
hipMemcpy(host_array, dev_array, byte_size, hipMemcpyDeviceToHost); // Copy from device to host
// Verify that array was allocated and copied properly to the host, then cleanup
try {
for(int c = 0; c < P1; c++){
if(host_array[c] != 0) {throw "NON_ZERO_ELEM";}
}
} catch (...) {
printf("Problem 1 - Elements not initialized properly!\n");
hipFree(dev_array);
free(host_array);
return 0;
}
printf("Problem 1 - Successfully initialized array with %d elements\n", P1);
hipFree(dev_array);
free(host_array);
/////////////////////////////////////////////////////////////////////////////////////////////////////////
// Problem 2 - initialize array of size 1024 to all zeroes
byte_size = P2 * sizeof(int); // get size of 1024 integers in bytes
dim3 bd(P2); // create dim3 object with 1024 as the first dimensoin
hipMalloc((void**) &dev_array, byte_size); // Allocate memory on device
initialize<<<1, bd>>>(dev_array); // Launch kernel on device with 1024 threads
host_array = (int*)malloc(byte_size); // Allocate memory on the host
hipMemcpy(host_array, dev_array, byte_size, hipMemcpyDeviceToHost); // Copy from device to host
// Verify that array was allocated and copied properly, then cleanup
try {
for(int c = 0; c < P2; c++){
if(host_array[c] != 0) {throw "NON_ZERO_ELEM";}
}
} catch (...) {
printf("Problem 2 - Elements not initialized properly!\n");
hipFree(dev_array);
free(host_array);
return 0;
}
printf("Problem 2 - Successfully initialized array with %d elements\n", P2);
/////////////////////////////////////////////////////////////////////////////////////////////////////////
// Problem 3 - add i to array[i]
add<<<1, bd>>>(dev_array); // Launch add kernel with array from the previous problem
hipMemcpy(host_array, dev_array, byte_size, hipMemcpyDeviceToHost); // Copy from modified vaues to host
// Verify values are correct
try {
for(int c = 0; c < P2; c++){
if(host_array[c] != c) {throw "ADD_OP_MATCH";}
}
} catch (...) {
printf("Problem 3 - Elements not added properly!\n");
hipFree(dev_array);
free(host_array);
return 0;
}
printf("Problem 3 - Successfully added i to array[i] with %d elements\n", P2);
hipFree(dev_array);
free(host_array);
///////////////////////////////////////////////////////////////////////////////////////////////////////////
// Problem 4 - same as problem 3, but with 8000 elements
byte_size = P4 * sizeof(int);
dim3 gd(P4);
hipMalloc((void**) &dev_array, byte_size);
initialize<<<1, gd>>>(dev_array); // Initialize array
add<<<1, gd>>>(dev_array); // Add index to array
host_array = (int*)malloc(byte_size);
hipMemcpy(host_array, dev_array, byte_size, hipMemcpyDeviceToHost);
// Verify values are correct, 8000 threads might be too much for the device and the answer is incorrect
try {
for(int c = 0; c < P4; c++){
if(host_array[c] != c) {throw "ADD_OP_MATCH";}
}
} catch (...) {
printf("Problem 4 - Elements not added properly!\n");
hipFree(dev_array);
free(host_array);
return 0;
}
printf("Problem 4 - Successfully added i to array[i] with %d elements\n", P4);
hipFree(dev_array);
free(host_array);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
Erick Juarez
CPSC 479 Sec 1
HOMEWORK 5 - 3/25/20
tested using nvcc - CUDA compiler driver release 9.0, V9.0.176
*/
#include <stdio.h>
#include <hip/hip_runtime.h>
#define P1 16 // Size of array for problem 1
#define P2 1024 // Size of array for problems 2 & 3
#define P4 8000 // Size of array for problem 4
// device function to initialize array - used in problems 1 & 2
__global__ void initialize(int *array){
array[threadIdx.x] = 0;
}
// device function will add values to array - used in problems 3 & 4
__global__ void add(int *array){
array[threadIdx.x] += threadIdx.x;
}
// Main function
int main(int argc, char * argv[]) {
int *host_array; // host copy of array
int *dev_array; // device copy of array
int byte_size; // size in bytes of an object
/////////////////////////////////////////////////////////////////////////////////////////////////////////
// Problem 1 - initialize array of size 16 to all zeroes
byte_size = P1 * sizeof(int); // get size of 16 integers in bytes
dim3 blockd(P1); // Create dim3 type with value of 16 on the first dimension
hipMalloc((void **) &dev_array, byte_size); // Allocate memory on the device
initialize<<<1, blockd>>>(dev_array); // Launch new kernel on device with 16 threads
host_array = (int *)malloc(byte_size); // Allocate memory for the host
hipMemcpy(host_array, dev_array, byte_size, hipMemcpyDeviceToHost); // Copy from device to host
// Verify that array was allocated and copied properly to the host, then cleanup
try {
for(int c = 0; c < P1; c++){
if(host_array[c] != 0) {throw "NON_ZERO_ELEM";}
}
} catch (...) {
printf("Problem 1 - Elements not initialized properly!\n");
hipFree(dev_array);
free(host_array);
return 0;
}
printf("Problem 1 - Successfully initialized array with %d elements\n", P1);
hipFree(dev_array);
free(host_array);
/////////////////////////////////////////////////////////////////////////////////////////////////////////
// Problem 2 - initialize array of size 1024 to all zeroes
byte_size = P2 * sizeof(int); // get size of 1024 integers in bytes
dim3 bd(P2); // create dim3 object with 1024 as the first dimensoin
hipMalloc((void**) &dev_array, byte_size); // Allocate memory on device
initialize<<<1, bd>>>(dev_array); // Launch kernel on device with 1024 threads
host_array = (int*)malloc(byte_size); // Allocate memory on the host
hipMemcpy(host_array, dev_array, byte_size, hipMemcpyDeviceToHost); // Copy from device to host
// Verify that array was allocated and copied properly, then cleanup
try {
for(int c = 0; c < P2; c++){
if(host_array[c] != 0) {throw "NON_ZERO_ELEM";}
}
} catch (...) {
printf("Problem 2 - Elements not initialized properly!\n");
hipFree(dev_array);
free(host_array);
return 0;
}
printf("Problem 2 - Successfully initialized array with %d elements\n", P2);
/////////////////////////////////////////////////////////////////////////////////////////////////////////
// Problem 3 - add i to array[i]
add<<<1, bd>>>(dev_array); // Launch add kernel with array from the previous problem
hipMemcpy(host_array, dev_array, byte_size, hipMemcpyDeviceToHost); // Copy from modified vaues to host
// Verify values are correct
try {
for(int c = 0; c < P2; c++){
if(host_array[c] != c) {throw "ADD_OP_MATCH";}
}
} catch (...) {
printf("Problem 3 - Elements not added properly!\n");
hipFree(dev_array);
free(host_array);
return 0;
}
printf("Problem 3 - Successfully added i to array[i] with %d elements\n", P2);
hipFree(dev_array);
free(host_array);
///////////////////////////////////////////////////////////////////////////////////////////////////////////
// Problem 4 - same as problem 3, but with 8000 elements
byte_size = P4 * sizeof(int);
dim3 gd(P4);
hipMalloc((void**) &dev_array, byte_size);
initialize<<<1, gd>>>(dev_array); // Initialize array
add<<<1, gd>>>(dev_array); // Add index to array
host_array = (int*)malloc(byte_size);
hipMemcpy(host_array, dev_array, byte_size, hipMemcpyDeviceToHost);
// Verify values are correct, 8000 threads might be too much for the device and the answer is incorrect
try {
for(int c = 0; c < P4; c++){
if(host_array[c] != c) {throw "ADD_OP_MATCH";}
}
} catch (...) {
printf("Problem 4 - Elements not added properly!\n");
hipFree(dev_array);
free(host_array);
return 0;
}
printf("Problem 4 - Successfully added i to array[i] with %d elements\n", P4);
hipFree(dev_array);
free(host_array);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10initializePi
.globl _Z10initializePi
.p2align 8
.type _Z10initializePi,@function
_Z10initializePi:
s_load_b64 s[0:1], s[0:1], 0x0
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10initializePi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10initializePi, .Lfunc_end0-_Z10initializePi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3addPi
.globl _Z3addPi
.p2align 8
.type _Z3addPi,@function
_Z3addPi:
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v2, v1, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v2, v0
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z3addPi, .Lfunc_end1-_Z3addPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10initializePi
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z10initializePi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPi
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z3addPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
Erick Juarez
CPSC 479 Sec 1
HOMEWORK 5 - 3/25/20
tested using nvcc - CUDA compiler driver release 9.0, V9.0.176
*/
#include <stdio.h>
#include <hip/hip_runtime.h>
#define P1 16 // Size of array for problem 1
#define P2 1024 // Size of array for problems 2 & 3
#define P4 8000 // Size of array for problem 4
// device function to initialize array - used in problems 1 & 2
__global__ void initialize(int *array){
array[threadIdx.x] = 0;
}
// device function will add values to array - used in problems 3 & 4
__global__ void add(int *array){
array[threadIdx.x] += threadIdx.x;
}
// Main function
int main(int argc, char * argv[]) {
int *host_array; // host copy of array
int *dev_array; // device copy of array
int byte_size; // size in bytes of an object
/////////////////////////////////////////////////////////////////////////////////////////////////////////
// Problem 1 - initialize array of size 16 to all zeroes
byte_size = P1 * sizeof(int); // get size of 16 integers in bytes
dim3 blockd(P1); // Create dim3 type with value of 16 on the first dimension
hipMalloc((void **) &dev_array, byte_size); // Allocate memory on the device
initialize<<<1, blockd>>>(dev_array); // Launch new kernel on device with 16 threads
host_array = (int *)malloc(byte_size); // Allocate memory for the host
hipMemcpy(host_array, dev_array, byte_size, hipMemcpyDeviceToHost); // Copy from device to host
// Verify that array was allocated and copied properly to the host, then cleanup
try {
for(int c = 0; c < P1; c++){
if(host_array[c] != 0) {throw "NON_ZERO_ELEM";}
}
} catch (...) {
printf("Problem 1 - Elements not initialized properly!\n");
hipFree(dev_array);
free(host_array);
return 0;
}
printf("Problem 1 - Successfully initialized array with %d elements\n", P1);
hipFree(dev_array);
free(host_array);
/////////////////////////////////////////////////////////////////////////////////////////////////////////
// Problem 2 - initialize array of size 1024 to all zeroes
byte_size = P2 * sizeof(int); // get size of 1024 integers in bytes
dim3 bd(P2); // create dim3 object with 1024 as the first dimensoin
hipMalloc((void**) &dev_array, byte_size); // Allocate memory on device
initialize<<<1, bd>>>(dev_array); // Launch kernel on device with 1024 threads
host_array = (int*)malloc(byte_size); // Allocate memory on the host
hipMemcpy(host_array, dev_array, byte_size, hipMemcpyDeviceToHost); // Copy from device to host
// Verify that array was allocated and copied properly, then cleanup
try {
for(int c = 0; c < P2; c++){
if(host_array[c] != 0) {throw "NON_ZERO_ELEM";}
}
} catch (...) {
printf("Problem 2 - Elements not initialized properly!\n");
hipFree(dev_array);
free(host_array);
return 0;
}
printf("Problem 2 - Successfully initialized array with %d elements\n", P2);
/////////////////////////////////////////////////////////////////////////////////////////////////////////
// Problem 3 - add i to array[i]
add<<<1, bd>>>(dev_array); // Launch add kernel with array from the previous problem
hipMemcpy(host_array, dev_array, byte_size, hipMemcpyDeviceToHost); // Copy from modified vaues to host
// Verify values are correct
try {
for(int c = 0; c < P2; c++){
if(host_array[c] != c) {throw "ADD_OP_MATCH";}
}
} catch (...) {
printf("Problem 3 - Elements not added properly!\n");
hipFree(dev_array);
free(host_array);
return 0;
}
printf("Problem 3 - Successfully added i to array[i] with %d elements\n", P2);
hipFree(dev_array);
free(host_array);
///////////////////////////////////////////////////////////////////////////////////////////////////////////
// Problem 4 - same as problem 3, but with 8000 elements
byte_size = P4 * sizeof(int);
dim3 gd(P4);
hipMalloc((void**) &dev_array, byte_size);
initialize<<<1, gd>>>(dev_array); // Initialize array
add<<<1, gd>>>(dev_array); // Add index to array
host_array = (int*)malloc(byte_size);
hipMemcpy(host_array, dev_array, byte_size, hipMemcpyDeviceToHost);
// Verify values are correct, 8000 threads might be too much for the device and the answer is incorrect
try {
for(int c = 0; c < P4; c++){
if(host_array[c] != c) {throw "ADD_OP_MATCH";}
}
} catch (...) {
printf("Problem 4 - Elements not added properly!\n");
hipFree(dev_array);
free(host_array);
return 0;
}
printf("Problem 4 - Successfully added i to array[i] with %d elements\n", P4);
hipFree(dev_array);
free(host_array);
return 0;
} | .text
.file "cuda-threads.hip"
.globl _Z25__device_stub__initializePi # -- Begin function _Z25__device_stub__initializePi
.p2align 4, 0x90
.type _Z25__device_stub__initializePi,@function
_Z25__device_stub__initializePi: # @_Z25__device_stub__initializePi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10initializePi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z25__device_stub__initializePi, .Lfunc_end0-_Z25__device_stub__initializePi
.cfi_endproc
# -- End function
.globl _Z18__device_stub__addPi # -- Begin function _Z18__device_stub__addPi
.p2align 4, 0x90
.type _Z18__device_stub__addPi,@function
_Z18__device_stub__addPi: # @_Z18__device_stub__addPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z3addPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z18__device_stub__addPi, .Lfunc_end1-_Z18__device_stub__addPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $80, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movabsq $4294967297, %rbx # imm = 0x100000001
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
leaq 15(%rbx), %rdx
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
.cfi_escape 0x2e, 0x00
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
.cfi_escape 0x2e, 0x10
leaq 16(%rsp), %r9
movl $_Z10initializePi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
.cfi_escape 0x2e, 0x00
movl $64, %edi
callq malloc
movq %rax, %r14
movq 8(%rsp), %rsi
.cfi_escape 0x2e, 0x00
movl $64, %edx
movq %rax, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
cmpl $0, (%r14,%rax,4)
jne .LBB2_43
# %bb.4: # in Loop: Header=BB2_3 Depth=1
incq %rax
cmpq $16, %rax
jne .LBB2_3
# %bb.5:
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %edi
movl $16, %esi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq hipFree
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq free
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 1023(%rbx), %r15
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_7
# %bb.6:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
.cfi_escape 0x2e, 0x00
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
.cfi_escape 0x2e, 0x10
leaq 16(%rsp), %r9
movl $_Z10initializePi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_7:
.cfi_escape 0x2e, 0x00
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r14
movq 8(%rsp), %rsi
.cfi_escape 0x2e, 0x00
movl $4096, %edx # imm = 0x1000
movq %rax, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_8: # =>This Inner Loop Header: Depth=1
cmpl $0, (%r14,%rax,4)
jne .LBB2_9
# %bb.15: # in Loop: Header=BB2_8 Depth=1
incq %rax
cmpq $1024, %rax # imm = 0x400
jne .LBB2_8
# %bb.16:
.cfi_escape 0x2e, 0x00
movl $.L.str.4, %edi
movl $1024, %esi # imm = 0x400
xorl %eax, %eax
callq printf
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_18
# %bb.17:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
.cfi_escape 0x2e, 0x00
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
.cfi_escape 0x2e, 0x10
leaq 16(%rsp), %r9
movl $_Z3addPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_18:
movq 8(%rsp), %rsi
.cfi_escape 0x2e, 0x00
movl $4096, %edx # imm = 0x1000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_19: # =>This Inner Loop Header: Depth=1
movl (%r14,%rax,4), %ecx
cmpq %rcx, %rax
jne .LBB2_20
# %bb.24: # in Loop: Header=BB2_19 Depth=1
incq %rax
cmpq $1024, %rax # imm = 0x400
jne .LBB2_19
# %bb.25:
.cfi_escape 0x2e, 0x00
movl $.L.str.7, %edi
movl $1024, %esi # imm = 0x400
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq hipFree
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq free
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $32000, %esi # imm = 0x7D00
callq hipMalloc
leaq 7999(%rbx), %r14
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_27
# %bb.26:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
.cfi_escape 0x2e, 0x00
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
.cfi_escape 0x2e, 0x10
leaq 16(%rsp), %r9
movl $_Z10initializePi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_27:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_29
# %bb.28:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
.cfi_escape 0x2e, 0x00
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
.cfi_escape 0x2e, 0x10
leaq 16(%rsp), %r9
movl $_Z3addPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_29:
.cfi_escape 0x2e, 0x00
movl $32000, %edi # imm = 0x7D00
callq malloc
movq %rax, %rbx
movq 8(%rsp), %rsi
.cfi_escape 0x2e, 0x00
movl $32000, %edx # imm = 0x7D00
movq %rax, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_30: # =>This Inner Loop Header: Depth=1
movl (%rbx,%rax,4), %ecx
cmpq %rcx, %rax
jne .LBB2_31
# %bb.35: # in Loop: Header=BB2_30 Depth=1
incq %rax
cmpq $8000, %rax # imm = 0x1F40
jne .LBB2_30
# %bb.36:
.cfi_escape 0x2e, 0x00
movl $.L.str.9, %edi
movl $8000, %esi # imm = 0x1F40
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq hipFree
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq free
.LBB2_37:
xorl %eax, %eax
addq $80, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_43:
.cfi_def_cfa_offset 112
.cfi_escape 0x2e, 0x00
movl $8, %edi
callq __cxa_allocate_exception
movq $.L.str, (%rax)
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $_ZTIPKc, %esi
movq %rax, %rdi
xorl %edx, %edx
callq __cxa_throw
.Ltmp1:
jmp .LBB2_44
.LBB2_9:
.cfi_escape 0x2e, 0x00
movl $8, %edi
callq __cxa_allocate_exception
movq $.L.str, (%rax)
.Ltmp8:
.cfi_escape 0x2e, 0x00
movl $_ZTIPKc, %esi
movq %rax, %rdi
xorl %edx, %edx
callq __cxa_throw
.Ltmp9:
jmp .LBB2_44
.LBB2_20:
.cfi_escape 0x2e, 0x00
movl $8, %edi
callq __cxa_allocate_exception
movq $.L.str.5, (%rax)
.Ltmp16:
.cfi_escape 0x2e, 0x00
movl $_ZTIPKc, %esi
movq %rax, %rdi
xorl %edx, %edx
callq __cxa_throw
.Ltmp17:
jmp .LBB2_44
.LBB2_31:
.cfi_escape 0x2e, 0x00
movl $8, %edi
callq __cxa_allocate_exception
movq $.L.str.5, (%rax)
.Ltmp24:
.cfi_escape 0x2e, 0x00
movl $_ZTIPKc, %esi
movq %rax, %rdi
xorl %edx, %edx
callq __cxa_throw
.Ltmp25:
.LBB2_44:
.LBB2_38:
.Ltmp26:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq __cxa_begin_catch
.cfi_escape 0x2e, 0x00
movl $.Lstr, %edi
callq puts@PLT
movq 8(%rsp), %rdi
.Ltmp27:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp28:
# %bb.39:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
jmp .LBB2_13
.LBB2_40:
.Ltmp29:
movq %rax, %rbx
.Ltmp30:
.cfi_escape 0x2e, 0x00
callq __cxa_end_catch
.Ltmp31:
jmp .LBB2_41
.LBB2_32:
.Ltmp18:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq __cxa_begin_catch
.cfi_escape 0x2e, 0x00
movl $.Lstr.1, %edi
callq puts@PLT
movq 8(%rsp), %rdi
.Ltmp19:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp20:
# %bb.33:
.cfi_escape 0x2e, 0x00
jmp .LBB2_12
.LBB2_34:
.Ltmp21:
movq %rax, %rbx
.Ltmp22:
.cfi_escape 0x2e, 0x00
callq __cxa_end_catch
.Ltmp23:
jmp .LBB2_41
.LBB2_21:
.Ltmp10:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq __cxa_begin_catch
.cfi_escape 0x2e, 0x00
movl $.Lstr.2, %edi
callq puts@PLT
movq 8(%rsp), %rdi
.Ltmp11:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp12:
# %bb.22:
.cfi_escape 0x2e, 0x00
jmp .LBB2_12
.LBB2_23:
.Ltmp13:
movq %rax, %rbx
.Ltmp14:
.cfi_escape 0x2e, 0x00
callq __cxa_end_catch
.Ltmp15:
jmp .LBB2_41
.LBB2_10:
.Ltmp2:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq __cxa_begin_catch
.cfi_escape 0x2e, 0x00
movl $.Lstr.3, %edi
callq puts@PLT
movq 8(%rsp), %rdi
.Ltmp3:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp4:
# %bb.11:
.cfi_escape 0x2e, 0x00
.LBB2_12:
movq %r14, %rdi
.LBB2_13:
callq free
.cfi_escape 0x2e, 0x00
callq __cxa_end_catch
jmp .LBB2_37
.LBB2_14:
.Ltmp5:
movq %rax, %rbx
.Ltmp6:
.cfi_escape 0x2e, 0x00
callq __cxa_end_catch
.Ltmp7:
.LBB2_41:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.LBB2_42:
.Ltmp32:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq __clang_call_terminate
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 3 # @TType Encoding = udata4
.uleb128 .Lttbase0-.Lttbaseref0
.Lttbaseref0:
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 1 # On action: 1
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp8-.Ltmp1 # Call between .Ltmp1 and .Ltmp8
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp8-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp9-.Ltmp8 # Call between .Ltmp8 and .Ltmp9
.uleb128 .Ltmp10-.Lfunc_begin0 # jumps to .Ltmp10
.byte 1 # On action: 1
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp16-.Ltmp9 # Call between .Ltmp9 and .Ltmp16
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp16-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp17-.Ltmp16 # Call between .Ltmp16 and .Ltmp17
.uleb128 .Ltmp18-.Lfunc_begin0 # jumps to .Ltmp18
.byte 1 # On action: 1
.uleb128 .Ltmp17-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp24-.Ltmp17 # Call between .Ltmp17 and .Ltmp24
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp24-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp25-.Ltmp24 # Call between .Ltmp24 and .Ltmp25
.uleb128 .Ltmp26-.Lfunc_begin0 # jumps to .Ltmp26
.byte 1 # On action: 1
.uleb128 .Ltmp25-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp27-.Ltmp25 # Call between .Ltmp25 and .Ltmp27
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp27-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp28-.Ltmp27 # Call between .Ltmp27 and .Ltmp28
.uleb128 .Ltmp29-.Lfunc_begin0 # jumps to .Ltmp29
.byte 0 # On action: cleanup
.uleb128 .Ltmp30-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp31-.Ltmp30 # Call between .Ltmp30 and .Ltmp31
.uleb128 .Ltmp32-.Lfunc_begin0 # jumps to .Ltmp32
.byte 1 # On action: 1
.uleb128 .Ltmp31-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Ltmp19-.Ltmp31 # Call between .Ltmp31 and .Ltmp19
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp19-.Lfunc_begin0 # >> Call Site 13 <<
.uleb128 .Ltmp20-.Ltmp19 # Call between .Ltmp19 and .Ltmp20
.uleb128 .Ltmp21-.Lfunc_begin0 # jumps to .Ltmp21
.byte 0 # On action: cleanup
.uleb128 .Ltmp22-.Lfunc_begin0 # >> Call Site 14 <<
.uleb128 .Ltmp23-.Ltmp22 # Call between .Ltmp22 and .Ltmp23
.uleb128 .Ltmp32-.Lfunc_begin0 # jumps to .Ltmp32
.byte 1 # On action: 1
.uleb128 .Ltmp23-.Lfunc_begin0 # >> Call Site 15 <<
.uleb128 .Ltmp11-.Ltmp23 # Call between .Ltmp23 and .Ltmp11
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp11-.Lfunc_begin0 # >> Call Site 16 <<
.uleb128 .Ltmp12-.Ltmp11 # Call between .Ltmp11 and .Ltmp12
.uleb128 .Ltmp13-.Lfunc_begin0 # jumps to .Ltmp13
.byte 0 # On action: cleanup
.uleb128 .Ltmp14-.Lfunc_begin0 # >> Call Site 17 <<
.uleb128 .Ltmp15-.Ltmp14 # Call between .Ltmp14 and .Ltmp15
.uleb128 .Ltmp32-.Lfunc_begin0 # jumps to .Ltmp32
.byte 1 # On action: 1
.uleb128 .Ltmp15-.Lfunc_begin0 # >> Call Site 18 <<
.uleb128 .Ltmp3-.Ltmp15 # Call between .Ltmp15 and .Ltmp3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 19 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 20 <<
.uleb128 .Ltmp6-.Ltmp4 # Call between .Ltmp4 and .Ltmp6
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 21 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp32-.Lfunc_begin0 # jumps to .Ltmp32
.byte 1 # On action: 1
.uleb128 .Ltmp7-.Lfunc_begin0 # >> Call Site 22 <<
.uleb128 .Lfunc_end2-.Ltmp7 # Call between .Ltmp7 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.byte 1 # >> Action Record 1 <<
# Catch TypeInfo 1
.byte 0 # No further actions
.p2align 2, 0x0
# >> Catch TypeInfos <<
.long 0 # TypeInfo 1
.Lttbase0:
.p2align 2, 0x0
# -- End function
.section .text.__clang_call_terminate,"axG",@progbits,__clang_call_terminate,comdat
.hidden __clang_call_terminate # -- Begin function __clang_call_terminate
.weak __clang_call_terminate
.p2align 4, 0x90
.type __clang_call_terminate,@function
__clang_call_terminate: # @__clang_call_terminate
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq __cxa_begin_catch
callq _ZSt9terminatev
.Lfunc_end3:
.size __clang_call_terminate, .Lfunc_end3-__clang_call_terminate
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10initializePi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10initializePi,@object # @_Z10initializePi
.section .rodata,"a",@progbits
.globl _Z10initializePi
.p2align 3, 0x0
_Z10initializePi:
.quad _Z25__device_stub__initializePi
.size _Z10initializePi, 8
.type _Z3addPi,@object # @_Z3addPi
.globl _Z3addPi
.p2align 3, 0x0
_Z3addPi:
.quad _Z18__device_stub__addPi
.size _Z3addPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "NON_ZERO_ELEM"
.size .L.str, 14
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Problem 1 - Successfully initialized array with %d elements\n"
.size .L.str.2, 61
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Problem 2 - Successfully initialized array with %d elements\n"
.size .L.str.4, 61
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "ADD_OP_MATCH"
.size .L.str.5, 13
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Problem 3 - Successfully added i to array[i] with %d elements\n"
.size .L.str.7, 63
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Problem 4 - Successfully added i to array[i] with %d elements\n"
.size .L.str.9, 63
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10initializePi"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z3addPi"
.size .L__unnamed_2, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Problem 4 - Elements not added properly!"
.size .Lstr, 41
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Problem 3 - Elements not added properly!"
.size .Lstr.1, 41
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Problem 2 - Elements not initialized properly!"
.size .Lstr.2, 47
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Problem 1 - Elements not initialized properly!"
.size .Lstr.3, 47
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__initializePi
.addrsig_sym _Z18__device_stub__addPi
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z10initializePi
.addrsig_sym _Z3addPi
.addrsig_sym _ZTIPKc
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x001fca00078e0002 */
/*0050*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0060*/ IADD3 R5, R0, R5, RZ ; /* 0x0000000500057210 */
/* 0x004fca0007ffe0ff */
/*0070*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10initializePi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x001fca00078e0003 */
/*0050*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*0060*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0070*/ BRA 0x70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10initializePi
.globl _Z10initializePi
.p2align 8
.type _Z10initializePi,@function
_Z10initializePi:
s_load_b64 s[0:1], s[0:1], 0x0
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10initializePi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10initializePi, .Lfunc_end0-_Z10initializePi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3addPi
.globl _Z3addPi
.p2align 8
.type _Z3addPi,@function
_Z3addPi:
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v2, v1, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v2, v0
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z3addPi, .Lfunc_end1-_Z3addPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10initializePi
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z10initializePi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPi
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z3addPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ab854_00000000-6_cuda-threads.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z10initializePiPi
.type _Z30__device_stub__Z10initializePiPi, @function
_Z30__device_stub__Z10initializePiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10initializePi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z10initializePiPi, .-_Z30__device_stub__Z10initializePiPi
.globl _Z10initializePi
.type _Z10initializePi, @function
_Z10initializePi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10initializePiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10initializePi, .-_Z10initializePi
.globl _Z22__device_stub__Z3addPiPi
.type _Z22__device_stub__Z3addPiPi, @function
_Z22__device_stub__Z3addPiPi:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3addPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z22__device_stub__Z3addPiPi, .-_Z22__device_stub__Z3addPiPi
.globl _Z3addPi
.type _Z3addPi, @function
_Z3addPi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z3addPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z3addPi, .-_Z3addPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "NON_ZERO_ELEM"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Problem 1 - Successfully initialized array with %d elements\n"
.align 8
.LC2:
.string "Problem 2 - Successfully initialized array with %d elements\n"
.section .rodata.str1.1
.LC3:
.string "ADD_OP_MATCH"
.section .rodata.str1.8
.align 8
.LC4:
.string "Problem 3 - Successfully added i to array[i] with %d elements\n"
.align 8
.LC5:
.string "Problem 4 - Successfully added i to array[i] with %d elements\n"
.align 8
.LC6:
.string "Problem 1 - Elements not initialized properly!\n"
.align 8
.LC7:
.string "Problem 2 - Elements not initialized properly!\n"
.align 8
.LC8:
.string "Problem 3 - Elements not added properly!\n"
.align 8
.LC9:
.string "Problem 4 - Elements not added properly!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA2057
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $16, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movq %rsp, %rdi
movl $64, %esi
.LEHB0:
call cudaMalloc@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl 16(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L65
.L20:
movl $64, %edi
call malloc@PLT
movq %rax, %rbx
movl $2, %ecx
movl $64, %edx
movq (%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movq %rbx, %rax
leaq 64(%rbx), %rdx
.L23:
cmpl $0, (%rax)
jne .L66
addq $4, %rax
cmpq %rdx, %rax
jne .L23
movl $16, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movq %rsp, %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl 28(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L67
.L24:
movl $4096, %edi
call malloc@PLT
movq %rax, %rbx
movl $2, %ecx
movl $4096, %edx
movq (%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movq %rbx, %rax
leaq 4096(%rbx), %rdx
.L27:
cmpl $0, (%rax)
jne .L68
addq $4, %rax
cmpq %rdx, %rax
jne .L27
movl $1024, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl 28(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L69
.L28:
movl $2, %ecx
movl $4096, %edx
movq (%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $0, %eax
.L31:
cmpl %eax, (%rbx,%rax,4)
jne .L70
addq $1, %rax
cmpq $1024, %rax
jne .L31
movl $1024, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movl $8000, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movq %rsp, %rdi
movl $32000, %esi
call cudaMalloc@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L71
.L32:
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L72
.L33:
movl $32000, %edi
call malloc@PLT
movq %rax, %rbx
movl $2, %ecx
movl $32000, %edx
movq (%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movl $0, %eax
.L36:
cmpl %eax, (%rbx,%rax,4)
jne .L73
addq $1, %rax
cmpq $8000, %rax
jne .L36
movl $8000, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
.L38:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L74
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L65:
.cfi_restore_state
movq (%rsp), %rdi
call _Z30__device_stub__Z10initializePiPi
.LEHE0:
jmp .L20
.L66:
movl $8, %edi
call __cxa_allocate_exception@PLT
movq %rax, %rdi
leaq .LC0(%rip), %rax
movq %rax, (%rdi)
movq 56(%rsp), %rax
subq %fs:40, %rax
je .L22
call __stack_chk_fail@PLT
.L22:
movl $0, %edx
leaq _ZTIPKc(%rip), %rsi
.LEHB1:
call __cxa_throw@PLT
.LEHE1:
.L51:
endbr64
movq %rax, %rdi
call __cxa_begin_catch@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
.LEHB2:
call __printf_chk@PLT
.LEHE2:
jmp .L75
.L67:
movq (%rsp), %rdi
.LEHB3:
call _Z30__device_stub__Z10initializePiPi
.LEHE3:
jmp .L24
.L68:
movl $8, %edi
call __cxa_allocate_exception@PLT
movq %rax, %rdi
leaq .LC0(%rip), %rax
movq %rax, (%rdi)
movq 56(%rsp), %rax
subq %fs:40, %rax
je .L26
call __stack_chk_fail@PLT
.L26:
movl $0, %edx
leaq _ZTIPKc(%rip), %rsi
.LEHB4:
call __cxa_throw@PLT
.LEHE4:
.L53:
endbr64
movq %rax, %rdi
call __cxa_begin_catch@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
.LEHB5:
call __printf_chk@PLT
.LEHE5:
jmp .L76
.L69:
movq (%rsp), %rdi
.LEHB6:
call _Z22__device_stub__Z3addPiPi
.LEHE6:
jmp .L28
.L70:
movl $8, %edi
call __cxa_allocate_exception@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rax
movq %rax, (%rdi)
movq 56(%rsp), %rax
subq %fs:40, %rax
je .L30
call __stack_chk_fail@PLT
.L30:
movl $0, %edx
leaq _ZTIPKc(%rip), %rsi
.LEHB7:
call __cxa_throw@PLT
.LEHE7:
.L55:
endbr64
movq %rax, %rdi
call __cxa_begin_catch@PLT
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
.LEHB8:
call __printf_chk@PLT
.LEHE8:
jmp .L77
.L71:
movq (%rsp), %rdi
.LEHB9:
call _Z30__device_stub__Z10initializePiPi
jmp .L32
.L72:
movq (%rsp), %rdi
call _Z22__device_stub__Z3addPiPi
.LEHE9:
jmp .L33
.L73:
movl $8, %edi
call __cxa_allocate_exception@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rax
movq %rax, (%rdi)
movq 56(%rsp), %rax
subq %fs:40, %rax
je .L35
call __stack_chk_fail@PLT
.L35:
movl $0, %edx
leaq _ZTIPKc(%rip), %rsi
.LEHB10:
call __cxa_throw@PLT
.LEHE10:
.L57:
endbr64
movq %rax, %rdi
call __cxa_begin_catch@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
.LEHB11:
call __printf_chk@PLT
.LEHE11:
jmp .L78
.L75:
movq (%rsp), %rdi
.LEHB12:
call cudaFree@PLT
.LEHE12:
movq %rbx, %rdi
call free@PLT
.LEHB13:
call __cxa_end_catch@PLT
.LEHE13:
jmp .L38
.L52:
endbr64
movq %rax, %rbx
call __cxa_end_catch@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
je .L40
call __stack_chk_fail@PLT
.L40:
movq %rbx, %rdi
.LEHB14:
call _Unwind_Resume@PLT
.LEHE14:
.L76:
movq (%rsp), %rdi
.LEHB15:
call cudaFree@PLT
.LEHE15:
movq %rbx, %rdi
call free@PLT
.LEHB16:
call __cxa_end_catch@PLT
.LEHE16:
jmp .L38
.L54:
endbr64
movq %rax, %rbx
call __cxa_end_catch@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
je .L43
call __stack_chk_fail@PLT
.L43:
movq %rbx, %rdi
.LEHB17:
call _Unwind_Resume@PLT
.LEHE17:
.L77:
movq (%rsp), %rdi
.LEHB18:
call cudaFree@PLT
.LEHE18:
movq %rbx, %rdi
call free@PLT
.LEHB19:
call __cxa_end_catch@PLT
.LEHE19:
jmp .L38
.L56:
endbr64
movq %rax, %rbx
call __cxa_end_catch@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
je .L46
call __stack_chk_fail@PLT
.L46:
movq %rbx, %rdi
.LEHB20:
call _Unwind_Resume@PLT
.LEHE20:
.L78:
movq (%rsp), %rdi
.LEHB21:
call cudaFree@PLT
.LEHE21:
movq %rbx, %rdi
call free@PLT
.LEHB22:
call __cxa_end_catch@PLT
.LEHE22:
jmp .L38
.L58:
endbr64
movq %rax, %rbx
call __cxa_end_catch@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
je .L49
call __stack_chk_fail@PLT
.L49:
movq %rbx, %rdi
.LEHB23:
call _Unwind_Resume@PLT
.LEHE23:
.L74:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.align 4
.LLSDA2057:
.byte 0xff
.byte 0x9b
.uleb128 .LLSDATT2057-.LLSDATTD2057
.LLSDATTD2057:
.byte 0x1
.uleb128 .LLSDACSE2057-.LLSDACSB2057
.LLSDACSB2057:
.uleb128 .LEHB0-.LFB2057
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB2057
.uleb128 .LEHE1-.LEHB1
.uleb128 .L51-.LFB2057
.uleb128 0x1
.uleb128 .LEHB2-.LFB2057
.uleb128 .LEHE2-.LEHB2
.uleb128 .L52-.LFB2057
.uleb128 0
.uleb128 .LEHB3-.LFB2057
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.uleb128 .LEHB4-.LFB2057
.uleb128 .LEHE4-.LEHB4
.uleb128 .L53-.LFB2057
.uleb128 0x1
.uleb128 .LEHB5-.LFB2057
.uleb128 .LEHE5-.LEHB5
.uleb128 .L54-.LFB2057
.uleb128 0
.uleb128 .LEHB6-.LFB2057
.uleb128 .LEHE6-.LEHB6
.uleb128 0
.uleb128 0
.uleb128 .LEHB7-.LFB2057
.uleb128 .LEHE7-.LEHB7
.uleb128 .L55-.LFB2057
.uleb128 0x1
.uleb128 .LEHB8-.LFB2057
.uleb128 .LEHE8-.LEHB8
.uleb128 .L56-.LFB2057
.uleb128 0
.uleb128 .LEHB9-.LFB2057
.uleb128 .LEHE9-.LEHB9
.uleb128 0
.uleb128 0
.uleb128 .LEHB10-.LFB2057
.uleb128 .LEHE10-.LEHB10
.uleb128 .L57-.LFB2057
.uleb128 0x1
.uleb128 .LEHB11-.LFB2057
.uleb128 .LEHE11-.LEHB11
.uleb128 .L58-.LFB2057
.uleb128 0
.uleb128 .LEHB12-.LFB2057
.uleb128 .LEHE12-.LEHB12
.uleb128 .L52-.LFB2057
.uleb128 0
.uleb128 .LEHB13-.LFB2057
.uleb128 .LEHE13-.LEHB13
.uleb128 0
.uleb128 0
.uleb128 .LEHB14-.LFB2057
.uleb128 .LEHE14-.LEHB14
.uleb128 0
.uleb128 0
.uleb128 .LEHB15-.LFB2057
.uleb128 .LEHE15-.LEHB15
.uleb128 .L54-.LFB2057
.uleb128 0
.uleb128 .LEHB16-.LFB2057
.uleb128 .LEHE16-.LEHB16
.uleb128 0
.uleb128 0
.uleb128 .LEHB17-.LFB2057
.uleb128 .LEHE17-.LEHB17
.uleb128 0
.uleb128 0
.uleb128 .LEHB18-.LFB2057
.uleb128 .LEHE18-.LEHB18
.uleb128 .L56-.LFB2057
.uleb128 0
.uleb128 .LEHB19-.LFB2057
.uleb128 .LEHE19-.LEHB19
.uleb128 0
.uleb128 0
.uleb128 .LEHB20-.LFB2057
.uleb128 .LEHE20-.LEHB20
.uleb128 0
.uleb128 0
.uleb128 .LEHB21-.LFB2057
.uleb128 .LEHE21-.LEHB21
.uleb128 .L58-.LFB2057
.uleb128 0
.uleb128 .LEHB22-.LFB2057
.uleb128 .LEHE22-.LEHB22
.uleb128 0
.uleb128 0
.uleb128 .LEHB23-.LFB2057
.uleb128 .LEHE23-.LEHB23
.uleb128 0
.uleb128 0
.LLSDACSE2057:
.byte 0x1
.byte 0
.align 4
.long 0
.LLSDATT2057:
.text
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z3addPi"
.LC11:
.string "_Z10initializePi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z10initializePi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda-threads.hip"
.globl _Z25__device_stub__initializePi # -- Begin function _Z25__device_stub__initializePi
.p2align 4, 0x90
.type _Z25__device_stub__initializePi,@function
_Z25__device_stub__initializePi: # @_Z25__device_stub__initializePi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10initializePi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z25__device_stub__initializePi, .Lfunc_end0-_Z25__device_stub__initializePi
.cfi_endproc
# -- End function
.globl _Z18__device_stub__addPi # -- Begin function _Z18__device_stub__addPi
.p2align 4, 0x90
.type _Z18__device_stub__addPi,@function
_Z18__device_stub__addPi: # @_Z18__device_stub__addPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z3addPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z18__device_stub__addPi, .Lfunc_end1-_Z18__device_stub__addPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $80, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movabsq $4294967297, %rbx # imm = 0x100000001
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
leaq 15(%rbx), %rdx
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
.cfi_escape 0x2e, 0x00
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
.cfi_escape 0x2e, 0x10
leaq 16(%rsp), %r9
movl $_Z10initializePi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
.cfi_escape 0x2e, 0x00
movl $64, %edi
callq malloc
movq %rax, %r14
movq 8(%rsp), %rsi
.cfi_escape 0x2e, 0x00
movl $64, %edx
movq %rax, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
cmpl $0, (%r14,%rax,4)
jne .LBB2_43
# %bb.4: # in Loop: Header=BB2_3 Depth=1
incq %rax
cmpq $16, %rax
jne .LBB2_3
# %bb.5:
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %edi
movl $16, %esi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq hipFree
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq free
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 1023(%rbx), %r15
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_7
# %bb.6:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
.cfi_escape 0x2e, 0x00
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
.cfi_escape 0x2e, 0x10
leaq 16(%rsp), %r9
movl $_Z10initializePi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_7:
.cfi_escape 0x2e, 0x00
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r14
movq 8(%rsp), %rsi
.cfi_escape 0x2e, 0x00
movl $4096, %edx # imm = 0x1000
movq %rax, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_8: # =>This Inner Loop Header: Depth=1
cmpl $0, (%r14,%rax,4)
jne .LBB2_9
# %bb.15: # in Loop: Header=BB2_8 Depth=1
incq %rax
cmpq $1024, %rax # imm = 0x400
jne .LBB2_8
# %bb.16:
.cfi_escape 0x2e, 0x00
movl $.L.str.4, %edi
movl $1024, %esi # imm = 0x400
xorl %eax, %eax
callq printf
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_18
# %bb.17:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
.cfi_escape 0x2e, 0x00
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
.cfi_escape 0x2e, 0x10
leaq 16(%rsp), %r9
movl $_Z3addPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_18:
movq 8(%rsp), %rsi
.cfi_escape 0x2e, 0x00
movl $4096, %edx # imm = 0x1000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_19: # =>This Inner Loop Header: Depth=1
movl (%r14,%rax,4), %ecx
cmpq %rcx, %rax
jne .LBB2_20
# %bb.24: # in Loop: Header=BB2_19 Depth=1
incq %rax
cmpq $1024, %rax # imm = 0x400
jne .LBB2_19
# %bb.25:
.cfi_escape 0x2e, 0x00
movl $.L.str.7, %edi
movl $1024, %esi # imm = 0x400
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq hipFree
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq free
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $32000, %esi # imm = 0x7D00
callq hipMalloc
leaq 7999(%rbx), %r14
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_27
# %bb.26:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
.cfi_escape 0x2e, 0x00
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
.cfi_escape 0x2e, 0x10
leaq 16(%rsp), %r9
movl $_Z10initializePi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_27:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_29
# %bb.28:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
.cfi_escape 0x2e, 0x00
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
.cfi_escape 0x2e, 0x10
leaq 16(%rsp), %r9
movl $_Z3addPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_29:
.cfi_escape 0x2e, 0x00
movl $32000, %edi # imm = 0x7D00
callq malloc
movq %rax, %rbx
movq 8(%rsp), %rsi
.cfi_escape 0x2e, 0x00
movl $32000, %edx # imm = 0x7D00
movq %rax, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_30: # =>This Inner Loop Header: Depth=1
movl (%rbx,%rax,4), %ecx
cmpq %rcx, %rax
jne .LBB2_31
# %bb.35: # in Loop: Header=BB2_30 Depth=1
incq %rax
cmpq $8000, %rax # imm = 0x1F40
jne .LBB2_30
# %bb.36:
.cfi_escape 0x2e, 0x00
movl $.L.str.9, %edi
movl $8000, %esi # imm = 0x1F40
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq hipFree
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq free
.LBB2_37:
xorl %eax, %eax
addq $80, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_43:
.cfi_def_cfa_offset 112
.cfi_escape 0x2e, 0x00
movl $8, %edi
callq __cxa_allocate_exception
movq $.L.str, (%rax)
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $_ZTIPKc, %esi
movq %rax, %rdi
xorl %edx, %edx
callq __cxa_throw
.Ltmp1:
jmp .LBB2_44
.LBB2_9:
.cfi_escape 0x2e, 0x00
movl $8, %edi
callq __cxa_allocate_exception
movq $.L.str, (%rax)
.Ltmp8:
.cfi_escape 0x2e, 0x00
movl $_ZTIPKc, %esi
movq %rax, %rdi
xorl %edx, %edx
callq __cxa_throw
.Ltmp9:
jmp .LBB2_44
.LBB2_20:
.cfi_escape 0x2e, 0x00
movl $8, %edi
callq __cxa_allocate_exception
movq $.L.str.5, (%rax)
.Ltmp16:
.cfi_escape 0x2e, 0x00
movl $_ZTIPKc, %esi
movq %rax, %rdi
xorl %edx, %edx
callq __cxa_throw
.Ltmp17:
jmp .LBB2_44
.LBB2_31:
.cfi_escape 0x2e, 0x00
movl $8, %edi
callq __cxa_allocate_exception
movq $.L.str.5, (%rax)
.Ltmp24:
.cfi_escape 0x2e, 0x00
movl $_ZTIPKc, %esi
movq %rax, %rdi
xorl %edx, %edx
callq __cxa_throw
.Ltmp25:
.LBB2_44:
.LBB2_38:
.Ltmp26:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq __cxa_begin_catch
.cfi_escape 0x2e, 0x00
movl $.Lstr, %edi
callq puts@PLT
movq 8(%rsp), %rdi
.Ltmp27:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp28:
# %bb.39:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
jmp .LBB2_13
.LBB2_40:
.Ltmp29:
movq %rax, %rbx
.Ltmp30:
.cfi_escape 0x2e, 0x00
callq __cxa_end_catch
.Ltmp31:
jmp .LBB2_41
.LBB2_32:
.Ltmp18:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq __cxa_begin_catch
.cfi_escape 0x2e, 0x00
movl $.Lstr.1, %edi
callq puts@PLT
movq 8(%rsp), %rdi
.Ltmp19:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp20:
# %bb.33:
.cfi_escape 0x2e, 0x00
jmp .LBB2_12
.LBB2_34:
.Ltmp21:
movq %rax, %rbx
.Ltmp22:
.cfi_escape 0x2e, 0x00
callq __cxa_end_catch
.Ltmp23:
jmp .LBB2_41
.LBB2_21:
.Ltmp10:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq __cxa_begin_catch
.cfi_escape 0x2e, 0x00
movl $.Lstr.2, %edi
callq puts@PLT
movq 8(%rsp), %rdi
.Ltmp11:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp12:
# %bb.22:
.cfi_escape 0x2e, 0x00
jmp .LBB2_12
.LBB2_23:
.Ltmp13:
movq %rax, %rbx
.Ltmp14:
.cfi_escape 0x2e, 0x00
callq __cxa_end_catch
.Ltmp15:
jmp .LBB2_41
.LBB2_10:
.Ltmp2:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq __cxa_begin_catch
.cfi_escape 0x2e, 0x00
movl $.Lstr.3, %edi
callq puts@PLT
movq 8(%rsp), %rdi
.Ltmp3:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp4:
# %bb.11:
.cfi_escape 0x2e, 0x00
.LBB2_12:
movq %r14, %rdi
.LBB2_13:
callq free
.cfi_escape 0x2e, 0x00
callq __cxa_end_catch
jmp .LBB2_37
.LBB2_14:
.Ltmp5:
movq %rax, %rbx
.Ltmp6:
.cfi_escape 0x2e, 0x00
callq __cxa_end_catch
.Ltmp7:
.LBB2_41:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.LBB2_42:
.Ltmp32:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq __clang_call_terminate
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 3 # @TType Encoding = udata4
.uleb128 .Lttbase0-.Lttbaseref0
.Lttbaseref0:
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 1 # On action: 1
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp8-.Ltmp1 # Call between .Ltmp1 and .Ltmp8
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp8-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp9-.Ltmp8 # Call between .Ltmp8 and .Ltmp9
.uleb128 .Ltmp10-.Lfunc_begin0 # jumps to .Ltmp10
.byte 1 # On action: 1
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp16-.Ltmp9 # Call between .Ltmp9 and .Ltmp16
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp16-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp17-.Ltmp16 # Call between .Ltmp16 and .Ltmp17
.uleb128 .Ltmp18-.Lfunc_begin0 # jumps to .Ltmp18
.byte 1 # On action: 1
.uleb128 .Ltmp17-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp24-.Ltmp17 # Call between .Ltmp17 and .Ltmp24
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp24-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp25-.Ltmp24 # Call between .Ltmp24 and .Ltmp25
.uleb128 .Ltmp26-.Lfunc_begin0 # jumps to .Ltmp26
.byte 1 # On action: 1
.uleb128 .Ltmp25-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp27-.Ltmp25 # Call between .Ltmp25 and .Ltmp27
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp27-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp28-.Ltmp27 # Call between .Ltmp27 and .Ltmp28
.uleb128 .Ltmp29-.Lfunc_begin0 # jumps to .Ltmp29
.byte 0 # On action: cleanup
.uleb128 .Ltmp30-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp31-.Ltmp30 # Call between .Ltmp30 and .Ltmp31
.uleb128 .Ltmp32-.Lfunc_begin0 # jumps to .Ltmp32
.byte 1 # On action: 1
.uleb128 .Ltmp31-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Ltmp19-.Ltmp31 # Call between .Ltmp31 and .Ltmp19
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp19-.Lfunc_begin0 # >> Call Site 13 <<
.uleb128 .Ltmp20-.Ltmp19 # Call between .Ltmp19 and .Ltmp20
.uleb128 .Ltmp21-.Lfunc_begin0 # jumps to .Ltmp21
.byte 0 # On action: cleanup
.uleb128 .Ltmp22-.Lfunc_begin0 # >> Call Site 14 <<
.uleb128 .Ltmp23-.Ltmp22 # Call between .Ltmp22 and .Ltmp23
.uleb128 .Ltmp32-.Lfunc_begin0 # jumps to .Ltmp32
.byte 1 # On action: 1
.uleb128 .Ltmp23-.Lfunc_begin0 # >> Call Site 15 <<
.uleb128 .Ltmp11-.Ltmp23 # Call between .Ltmp23 and .Ltmp11
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp11-.Lfunc_begin0 # >> Call Site 16 <<
.uleb128 .Ltmp12-.Ltmp11 # Call between .Ltmp11 and .Ltmp12
.uleb128 .Ltmp13-.Lfunc_begin0 # jumps to .Ltmp13
.byte 0 # On action: cleanup
.uleb128 .Ltmp14-.Lfunc_begin0 # >> Call Site 17 <<
.uleb128 .Ltmp15-.Ltmp14 # Call between .Ltmp14 and .Ltmp15
.uleb128 .Ltmp32-.Lfunc_begin0 # jumps to .Ltmp32
.byte 1 # On action: 1
.uleb128 .Ltmp15-.Lfunc_begin0 # >> Call Site 18 <<
.uleb128 .Ltmp3-.Ltmp15 # Call between .Ltmp15 and .Ltmp3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 19 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 20 <<
.uleb128 .Ltmp6-.Ltmp4 # Call between .Ltmp4 and .Ltmp6
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 21 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp32-.Lfunc_begin0 # jumps to .Ltmp32
.byte 1 # On action: 1
.uleb128 .Ltmp7-.Lfunc_begin0 # >> Call Site 22 <<
.uleb128 .Lfunc_end2-.Ltmp7 # Call between .Ltmp7 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.byte 1 # >> Action Record 1 <<
# Catch TypeInfo 1
.byte 0 # No further actions
.p2align 2, 0x0
# >> Catch TypeInfos <<
.long 0 # TypeInfo 1
.Lttbase0:
.p2align 2, 0x0
# -- End function
.section .text.__clang_call_terminate,"axG",@progbits,__clang_call_terminate,comdat
.hidden __clang_call_terminate # -- Begin function __clang_call_terminate
.weak __clang_call_terminate
.p2align 4, 0x90
.type __clang_call_terminate,@function
__clang_call_terminate: # @__clang_call_terminate
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq __cxa_begin_catch
callq _ZSt9terminatev
.Lfunc_end3:
.size __clang_call_terminate, .Lfunc_end3-__clang_call_terminate
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10initializePi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10initializePi,@object # @_Z10initializePi
.section .rodata,"a",@progbits
.globl _Z10initializePi
.p2align 3, 0x0
_Z10initializePi:
.quad _Z25__device_stub__initializePi
.size _Z10initializePi, 8
.type _Z3addPi,@object # @_Z3addPi
.globl _Z3addPi
.p2align 3, 0x0
_Z3addPi:
.quad _Z18__device_stub__addPi
.size _Z3addPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "NON_ZERO_ELEM"
.size .L.str, 14
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Problem 1 - Successfully initialized array with %d elements\n"
.size .L.str.2, 61
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Problem 2 - Successfully initialized array with %d elements\n"
.size .L.str.4, 61
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "ADD_OP_MATCH"
.size .L.str.5, 13
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Problem 3 - Successfully added i to array[i] with %d elements\n"
.size .L.str.7, 63
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Problem 4 - Successfully added i to array[i] with %d elements\n"
.size .L.str.9, 63
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10initializePi"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z3addPi"
.size .L__unnamed_2, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Problem 4 - Elements not added properly!"
.size .Lstr, 41
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Problem 3 - Elements not added properly!"
.size .Lstr.1, 41
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Problem 2 - Elements not initialized properly!"
.size .Lstr.2, 47
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Problem 1 - Elements not initialized properly!"
.size .Lstr.3, 47
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__initializePi
.addrsig_sym _Z18__device_stub__addPi
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z10initializePi
.addrsig_sym _Z3addPi
.addrsig_sym _ZTIPKc
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void scale(float knot_max, int nx, int nsamples, float * x, int pitch_x)
{
int
col_idx = blockDim.x * blockIdx.x + threadIdx.x;
if(col_idx >= nx) return;
float
min, max,
* col = x + col_idx * pitch_x;
// find the min and the max
min = max = col[0];
for(int i = 1; i < nsamples; i++) {
if(col[i] < min) min = col[i];
if(col[i] > max) max = col[i];
}
float delta = max - min;
for(int i = 0; i < nsamples; i++)
col[i] = (knot_max * (col[i] - min)) / delta;
} | .file "tmpxft_0000bfcf_00000000-6_scale.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z5scalefiiPfifiiPfi
.type _Z28__device_stub__Z5scalefiiPfifiiPfi, @function
_Z28__device_stub__Z5scalefiiPfifiiPfi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movss %xmm0, 28(%rsp)
movl %edi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 16(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5scalefiiPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z5scalefiiPfifiiPfi, .-_Z28__device_stub__Z5scalefiiPfifiiPfi
.globl _Z5scalefiiPfi
.type _Z5scalefiiPfi, @function
_Z5scalefiiPfi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z5scalefiiPfifiiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z5scalefiiPfi, .-_Z5scalefiiPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5scalefiiPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5scalefiiPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void scale(float knot_max, int nx, int nsamples, float * x, int pitch_x)
{
int
col_idx = blockDim.x * blockIdx.x + threadIdx.x;
if(col_idx >= nx) return;
float
min, max,
* col = x + col_idx * pitch_x;
// find the min and the max
min = max = col[0];
for(int i = 1; i < nsamples; i++) {
if(col[i] < min) min = col[i];
if(col[i] > max) max = col[i];
}
float delta = max - min;
for(int i = 0; i < nsamples; i++)
col[i] = (knot_max * (col[i] - min)) / delta;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void scale(float knot_max, int nx, int nsamples, float * x, int pitch_x)
{
int
col_idx = blockDim.x * blockIdx.x + threadIdx.x;
if(col_idx >= nx) return;
float
min, max,
* col = x + col_idx * pitch_x;
// find the min and the max
min = max = col[0];
for(int i = 1; i < nsamples; i++) {
if(col[i] < min) min = col[i];
if(col[i] > max) max = col[i];
}
float delta = max - min;
for(int i = 0; i < nsamples; i++)
col[i] = (knot_max * (col[i] - min)) / delta;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void scale(float knot_max, int nx, int nsamples, float * x, int pitch_x)
{
int
col_idx = blockDim.x * blockIdx.x + threadIdx.x;
if(col_idx >= nx) return;
float
min, max,
* col = x + col_idx * pitch_x;
// find the min and the max
min = max = col[0];
for(int i = 1; i < nsamples; i++) {
if(col[i] < min) min = col[i];
if(col[i] > max) max = col[i];
}
float delta = max - min;
for(int i = 0; i < nsamples; i++)
col[i] = (knot_max * (col[i] - min)) / delta;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5scalefiiPfi
.globl _Z5scalefiiPfi
.p2align 8
.type _Z5scalefiiPfi,@function
_Z5scalefiiPfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x4
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_8
s_clause 0x1
s_load_b32 s4, s[0:1], 0x18
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v0, v1, s4
s_load_b32 s4, s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 2
global_load_b32 v4, v[0:1], off
s_cbranch_scc1 .LBB0_5
v_add_co_u32 v2, vcc_lo, v2, s2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_waitcnt vmcnt(0)
v_mov_b32_e32 v5, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_add_i32 s2, s4, -1
.LBB0_3:
global_load_b32 v6, v[2:3], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 0
s_waitcnt vmcnt(0)
v_cmp_lt_f32_e32 vcc_lo, v6, v4
v_cndmask_b32_e32 v4, v4, v6, vcc_lo
v_cmp_gt_f32_e32 vcc_lo, v6, v5
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
s_cbranch_scc0 .LBB0_3
s_cmp_lt_i32 s4, 1
s_cbranch_scc0 .LBB0_6
s_branch .LBB0_8
.LBB0_5:
s_waitcnt vmcnt(0)
v_mov_b32_e32 v5, v4
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_8
.LBB0_6:
s_load_b32 s0, s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1)
v_sub_f32_e32 v2, v5, v4
.p2align 6
.LBB0_7:
global_load_b32 v3, v[0:1], off
s_add_i32 s4, s4, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s4, 0
s_waitcnt vmcnt(0)
v_sub_f32_e32 v3, v3, v4
s_waitcnt lgkmcnt(0)
v_mul_f32_e32 v3, s0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v5, null, v2, v2, v3
v_rcp_f32_e32 v6, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v7, -v5, v6, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v7, v6
v_div_scale_f32 v8, vcc_lo, v3, v2, v3
v_mul_f32_e32 v7, v8, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v9, -v5, v7, v8
v_fmac_f32_e32 v7, v9, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v5, -v5, v7, v8
v_div_fmas_f32 v5, v5, v6, v7
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v3, v5, v2, v3
global_store_b32 v[0:1], v3, off
v_add_co_u32 v0, vcc_lo, v0, 4
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_cbranch_scc1 .LBB0_7
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5scalefiiPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5scalefiiPfi, .Lfunc_end0-_Z5scalefiiPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5scalefiiPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5scalefiiPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void scale(float knot_max, int nx, int nsamples, float * x, int pitch_x)
{
int
col_idx = blockDim.x * blockIdx.x + threadIdx.x;
if(col_idx >= nx) return;
float
min, max,
* col = x + col_idx * pitch_x;
// find the min and the max
min = max = col[0];
for(int i = 1; i < nsamples; i++) {
if(col[i] < min) min = col[i];
if(col[i] > max) max = col[i];
}
float delta = max - min;
for(int i = 0; i < nsamples; i++)
col[i] = (knot_max * (col[i] - min)) / delta;
} | .text
.file "scale.hip"
.globl _Z20__device_stub__scalefiiPfi # -- Begin function _Z20__device_stub__scalefiiPfi
.p2align 4, 0x90
.type _Z20__device_stub__scalefiiPfi,@function
_Z20__device_stub__scalefiiPfi: # @_Z20__device_stub__scalefiiPfi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movss %xmm0, 20(%rsp)
movl %edi, 16(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 8(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5scalefiiPfi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z20__device_stub__scalefiiPfi, .Lfunc_end0-_Z20__device_stub__scalefiiPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5scalefiiPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5scalefiiPfi,@object # @_Z5scalefiiPfi
.section .rodata,"a",@progbits
.globl _Z5scalefiiPfi
.p2align 3, 0x0
_Z5scalefiiPfi:
.quad _Z20__device_stub__scalefiiPfi
.size _Z5scalefiiPfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5scalefiiPfi"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__scalefiiPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5scalefiiPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0000bfcf_00000000-6_scale.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z5scalefiiPfifiiPfi
.type _Z28__device_stub__Z5scalefiiPfifiiPfi, @function
_Z28__device_stub__Z5scalefiiPfifiiPfi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movss %xmm0, 28(%rsp)
movl %edi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 16(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5scalefiiPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z5scalefiiPfifiiPfi, .-_Z28__device_stub__Z5scalefiiPfifiiPfi
.globl _Z5scalefiiPfi
.type _Z5scalefiiPfi, @function
_Z5scalefiiPfi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z5scalefiiPfifiiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z5scalefiiPfi, .-_Z5scalefiiPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5scalefiiPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5scalefiiPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "scale.hip"
.globl _Z20__device_stub__scalefiiPfi # -- Begin function _Z20__device_stub__scalefiiPfi
.p2align 4, 0x90
.type _Z20__device_stub__scalefiiPfi,@function
_Z20__device_stub__scalefiiPfi: # @_Z20__device_stub__scalefiiPfi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movss %xmm0, 20(%rsp)
movl %edi, 16(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 8(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5scalefiiPfi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z20__device_stub__scalefiiPfi, .Lfunc_end0-_Z20__device_stub__scalefiiPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5scalefiiPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5scalefiiPfi,@object # @_Z5scalefiiPfi
.section .rodata,"a",@progbits
.globl _Z5scalefiiPfi
.p2align 3, 0x0
_Z5scalefiiPfi:
.quad _Z20__device_stub__scalefiiPfi
.size _Z5scalefiiPfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5scalefiiPfi"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__scalefiiPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5scalefiiPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define t_max 1
#define t 1
/*
(u[0][0][0][1][0]=(a*((((u[-3][0][0][0][0]+(u[0][-3][0][0][0]+u[0][0][-3][0][0]))*-2.0)+(((u[-2][0][0][0][0]+(u[0][-2][0][0][0]+u[0][0][-2][0][0]))*15.0)+((u[-1][0][0][0][0]+(u[0][-1][0][0][0]+u[0][0][-1][0][0]))*-60.0)))+((u[0][0][0][0][0]*20.0)+(((u[1][0][0][0][0]+(u[0][1][0][0][0]+u[0][0][1][0][0]))*30.0)+((u[2][0][0][0][0]+(u[0][2][0][0][0]+u[0][0][2][0][0]))*-3.0))))))
*/
__global__ void upstream_5_3d(double * * u_0_1_out, double * u_0_0, double * u_0_1, double a, int x_max, int y_max, int z_max, int cbx)
{
// double * const u__u_0[16] = { u_0_0, u_0_1 } ;
int _idx0;
int _idx1;
int _idx10;
int _idx11;
int _idx12;
int _idx13;
int _idx14;
int _idx15;
int _idx2;
int _idx3;
int _idx4;
int _idx5;
int _idx6;
int _idx7;
int _idx8;
int _idx9;
int idx_1_2;
int pt_idx_x;
int pt_idx_y;
int pt_idx_z;
int size_1_1;
int size_1_2;
// int t;
int tmp;
int v_idx_x;
int v_idx_x_max;
int v_idx_y;
int v_idx_y_max;
int v_idx_z;
int v_idx_z_max;
/*
Initializations
*/
size_1_1=(y_max/blockDim.y);
size_1_2=(z_max/blockDim.z);
idx_1_2=(blockIdx.y/size_1_2);
tmp=(blockIdx.y-(idx_1_2*size_1_2));
v_idx_x=(cbx*(threadIdx.x+(blockDim.x*blockIdx.x)));
v_idx_x_max=(v_idx_x+cbx);
v_idx_y=(threadIdx.y+(tmp*blockDim.y));
v_idx_y_max=(v_idx_y+1);
v_idx_z=(threadIdx.z+(idx_1_2*blockDim.z));
v_idx_z_max=(v_idx_z+1);
/*
Implementation
*/
/*
for t = 1..t_max by 1 parallel 1 <level 0> schedule { ... }
*/
// for (t=1; t<=t_max; t+=1)
{
/* Index bounds calculations for iterators in v[t=t, s=(cbx, 1, 1)][0] */
/*
for POINT pt[t=t, s=(1, 1, 1)][0] of size [1, 1, 1] in v[t=t, s=(:, :, :)][0] parallel 1 <level 1> schedule default { ... }
*/
{
/* Index bounds calculations for iterators in pt[t=t, s=(1, 1, 1)][0] */
pt_idx_z=v_idx_z;
pt_idx_y=v_idx_y;
for (pt_idx_x=v_idx_x; pt_idx_x<(v_idx_x_max-0); pt_idx_x+=1)
{
/* Index bounds calculations for iterators in pt[t=t, s=(1, 1, 1)][0] */
/*
v[t=(t+1), s=pt[t=?, s=?][0]][0]=stencil(v[t=t, s=pt[t=?, s=?][0]][0])
*/
/* _idx0 = ((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x) */
_idx0=((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x);
/* _idx1 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+(((((5*pt_idx_z)+15)*t)+pt_idx_y)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+((5*pt_idx_y)*t))+pt_idx_x)+3) */
_idx1=(((_idx0-(3*x_max))-(15*t))+3);
/* _idx2 = ((((((((pt_idx_z*x_max)+((5*pt_idx_z)*t))*y_max)+(((((5*pt_idx_z)*t)+pt_idx_y)+3)*x_max))+((25*pt_idx_z)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx2=((((_idx1+(((-3*x_max)-(15*t))*y_max))+((3-(15*t))*x_max))-(75*(t*t)))+(15*t));
/* _idx3 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+1) */
_idx3=(_idx0+1);
/* _idx4 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+1)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+5)*t))+pt_idx_x)+3) */
_idx4=((_idx1+x_max)+(5*t));
/* _idx5 = (((((((((pt_idx_z+1)*x_max)+(((5*pt_idx_z)+5)*t))*y_max)+((((((5*pt_idx_z)+5)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+25)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx5=(((_idx2+((x_max+(5*t))*y_max))+((5*t)*x_max))+(25*(t*t)));
/* _idx6 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+2) */
_idx6=(_idx0+2);
/* _idx7 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+2)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+10)*t))+pt_idx_x)+3) */
_idx7=((_idx4+x_max)+(5*t));
/* _idx8 = (((((((((pt_idx_z+2)*x_max)+(((5*pt_idx_z)+10)*t))*y_max)+((((((5*pt_idx_z)+10)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+50)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx8=(((_idx5+((x_max+(5*t))*y_max))+((5*t)*x_max))+(25*(t*t)));
/* _idx9 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx9=(_idx0+3);
/* _idx10 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+4) */
_idx10=(_idx0+4);
/* _idx11 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+4)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+20)*t))+pt_idx_x)+3) */
_idx11=((_idx9+x_max)+(5*t));
/* _idx12 = (((((((((pt_idx_z+4)*x_max)+(((5*pt_idx_z)+20)*t))*y_max)+((((((5*pt_idx_z)+20)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+100)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx12=(((_idx9+((x_max+(5*t))*y_max))+((5*t)*x_max))+(25*(t*t)));
/* _idx13 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+5) */
_idx13=(_idx0+5);
/* _idx14 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+5)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+25)*t))+pt_idx_x)+3) */
_idx14=((_idx11+x_max)+(5*t));
/* _idx15 = (((((((((pt_idx_z+5)*x_max)+(((5*pt_idx_z)+25)*t))*y_max)+((((((5*pt_idx_z)+25)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+125)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx15=(((_idx12+((x_max+(5*t))*y_max))+((5*t)*x_max))+(25*(t*t)));
u_0_1[_idx9]=(a*((((u_0_0[_idx0]+(u_0_0[_idx1]+u_0_0[_idx2]))*-2.0)+(((u_0_0[_idx3]+(u_0_0[_idx4]+u_0_0[_idx5]))*15.0)+((u_0_0[_idx6]+(u_0_0[_idx7]+u_0_0[_idx8]))*-60.0)))+((u_0_0[_idx9]*20.0)+(((u_0_0[_idx10]+(u_0_0[_idx11]+u_0_0[_idx12]))*30.0)+((u_0_0[_idx13]+(u_0_0[_idx14]+u_0_0[_idx15]))*-3.0)))));
}
}
}
}
__global__ void initialize(double * u_0_0, double * u_0_1, double a, int x_max, int y_max, int z_max, int cbx)
{
double * const u__u_0[16] = { u_0_0, u_0_1 } ;
int _idx0;
int _idx1;
int _idx10;
int _idx11;
int _idx12;
int _idx13;
int _idx14;
int _idx15;
int _idx2;
int _idx3;
int _idx4;
int _idx5;
int _idx6;
int _idx7;
int _idx8;
int _idx9;
int idx_1_2;
int pt_idx_x;
int pt_idx_y;
int pt_idx_z;
int size_1_1;
int size_1_2;
//int t;
int tmp;
int v_idx_x;
int v_idx_x_max;
int v_idx_y;
int v_idx_y_max;
int v_idx_z;
int v_idx_z_max;
/*
Initializations
*/
size_1_1=(y_max/blockDim.y);
size_1_2=(z_max/blockDim.z);
idx_1_2=(blockIdx.y/size_1_2);
tmp=(blockIdx.y-(idx_1_2*size_1_2));
v_idx_x=(cbx*(threadIdx.x+(blockDim.x*blockIdx.x)));
v_idx_x_max=(v_idx_x+cbx);
v_idx_y=(threadIdx.y+(tmp*blockDim.y));
v_idx_y_max=(v_idx_y+1);
v_idx_z=(threadIdx.z+(idx_1_2*blockDim.z));
v_idx_z_max=(v_idx_z+1);
/*
Implementation
*/
/*
for t = 1..t_max by 1 parallel 1 <level 0> schedule { ... }
*/
//for (t=1; t<=t_max; t+=1)
{
/* Index bounds calculations for iterators in v[t=t, s=(cbx, 1, 1)][0] */
/*
for POINT pt[t=t, s=(1, 1, 1)][0] of size [1, 1, 1] in v[t=t, s=(:, :, :)][0] parallel 1 <level 1> schedule default { ... }
*/
{
/* Index bounds calculations for iterators in pt[t=t, s=(1, 1, 1)][0] */
pt_idx_z=v_idx_z;
pt_idx_y=v_idx_y;
for (pt_idx_x=v_idx_x; pt_idx_x<(v_idx_x_max-0); pt_idx_x+=1)
{
/* Index bounds calculations for iterators in pt[t=t, s=(1, 1, 1)][0] */
/*
v[t=(t+1), s=pt[t=?, s=?][0]][0]=stencil(v[t=t, s=pt[t=?, s=?][0]][0])
*/
/* _idx0 = ((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x) */
_idx0=((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x);
u_0_0[_idx0]=0.1;
/* _idx1 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+1) */
_idx1=(_idx0+1);
u_0_0[_idx1]=0.1;
/* _idx2 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+2) */
_idx2=(_idx0+2);
u_0_0[_idx2]=0.1;
/* _idx3 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+(((((5*pt_idx_z)+15)*t)+pt_idx_y)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+((5*pt_idx_y)*t))+pt_idx_x)+3) */
_idx3=(((_idx0-(3*x_max))-(15*t))+3);
u_0_0[_idx3]=0.1;
/* _idx4 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+1)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+5)*t))+pt_idx_x)+3) */
_idx4=((_idx3+x_max)+(5*t));
u_0_0[_idx4]=0.1;
/* _idx5 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+2)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+10)*t))+pt_idx_x)+3) */
_idx5=((_idx4+x_max)+(5*t));
u_0_0[_idx5]=0.1;
/* _idx6 = ((((((((pt_idx_z*x_max)+((5*pt_idx_z)*t))*y_max)+(((((5*pt_idx_z)*t)+pt_idx_y)+3)*x_max))+((25*pt_idx_z)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx6=((((_idx1+(((-3*x_max)-(15*t))*y_max))-((15*t)*x_max))-(75*(t*t)))+2);
u_0_0[_idx6]=0.1;
/* _idx7 = (((((((((pt_idx_z+1)*x_max)+(((5*pt_idx_z)+5)*t))*y_max)+((((((5*pt_idx_z)+5)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+25)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx7=(((_idx6+((x_max+(5*t))*y_max))+((5*t)*x_max))+(25*(t*t)));
u_0_0[_idx7]=0.1;
/* _idx8 = (((((((((pt_idx_z+2)*x_max)+(((5*pt_idx_z)+10)*t))*y_max)+((((((5*pt_idx_z)+10)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+50)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx8=(((_idx7+((x_max+(5*t))*y_max))+((5*t)*x_max))+(25*(t*t)));
u_0_0[_idx8]=0.1;
/* _idx9 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx9=(_idx0+3);
u_0_0[_idx9]=0.1;
/* _idx10 = (((((((((pt_idx_z+4)*x_max)+(((5*pt_idx_z)+20)*t))*y_max)+((((((5*pt_idx_z)+20)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+100)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx10=(((_idx9+((x_max+(5*t))*y_max))+((5*t)*x_max))+(25*(t*t)));
u_0_0[_idx10]=0.1;
/* _idx11 = (((((((((pt_idx_z+5)*x_max)+(((5*pt_idx_z)+25)*t))*y_max)+((((((5*pt_idx_z)+25)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+125)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx11=(((_idx10+((x_max+(5*t))*y_max))+((5*t)*x_max))+(25*(t*t)));
u_0_0[_idx11]=0.1;
/* _idx12 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+4)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+20)*t))+pt_idx_x)+3) */
_idx12=((_idx9+x_max)+(5*t));
u_0_0[_idx12]=0.1;
/* _idx13 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+5)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+25)*t))+pt_idx_x)+3) */
_idx13=((_idx12+x_max)+(5*t));
u_0_0[_idx13]=0.1;
/* _idx14 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+4) */
_idx14=(_idx0+4);
u_0_0[_idx14]=0.1;
/* _idx15 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+5) */
_idx15=(_idx0+5);
u_0_0[_idx15]=0.1;
u_0_1[_idx9]=1.1;
}
}
}
} | .file "tmpxft_000f5e8e_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z13upstream_5_3dPPdS_S_diiiiPPdS_S_diiii
.type _Z43__device_stub__Z13upstream_5_3dPPdS_S_diiiiPPdS_S_diiii, @function
_Z43__device_stub__Z13upstream_5_3dPPdS_S_diiiiPPdS_S_diiii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movsd %xmm0, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 4(%rsp), %rax
movq %rax, 160(%rsp)
leaq 208(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13upstream_5_3dPPdS_S_diiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z13upstream_5_3dPPdS_S_diiiiPPdS_S_diiii, .-_Z43__device_stub__Z13upstream_5_3dPPdS_S_diiiiPPdS_S_diiii
.globl _Z13upstream_5_3dPPdS_S_diiii
.type _Z13upstream_5_3dPPdS_S_diiii, @function
_Z13upstream_5_3dPPdS_S_diiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z43__device_stub__Z13upstream_5_3dPPdS_S_diiiiPPdS_S_diiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13upstream_5_3dPPdS_S_diiii, .-_Z13upstream_5_3dPPdS_S_diiii
.globl _Z37__device_stub__Z10initializePdS_diiiiPdS_diiii
.type _Z37__device_stub__Z10initializePdS_diiiiPdS_diiii, @function
_Z37__device_stub__Z10initializePdS_diiiiPdS_diiii:
.LFB2053:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movsd %xmm0, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10initializePdS_diiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z37__device_stub__Z10initializePdS_diiiiPdS_diiii, .-_Z37__device_stub__Z10initializePdS_diiiiPdS_diiii
.globl _Z10initializePdS_diiii
.type _Z10initializePdS_diiii, @function
_Z10initializePdS_diiii:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z10initializePdS_diiiiPdS_diiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z10initializePdS_diiii, .-_Z10initializePdS_diiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10initializePdS_diiii"
.LC1:
.string "_Z13upstream_5_3dPPdS_S_diiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10initializePdS_diiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z13upstream_5_3dPPdS_S_diiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define t_max 1
#define t 1
/*
(u[0][0][0][1][0]=(a*((((u[-3][0][0][0][0]+(u[0][-3][0][0][0]+u[0][0][-3][0][0]))*-2.0)+(((u[-2][0][0][0][0]+(u[0][-2][0][0][0]+u[0][0][-2][0][0]))*15.0)+((u[-1][0][0][0][0]+(u[0][-1][0][0][0]+u[0][0][-1][0][0]))*-60.0)))+((u[0][0][0][0][0]*20.0)+(((u[1][0][0][0][0]+(u[0][1][0][0][0]+u[0][0][1][0][0]))*30.0)+((u[2][0][0][0][0]+(u[0][2][0][0][0]+u[0][0][2][0][0]))*-3.0))))))
*/
__global__ void upstream_5_3d(double * * u_0_1_out, double * u_0_0, double * u_0_1, double a, int x_max, int y_max, int z_max, int cbx)
{
// double * const u__u_0[16] = { u_0_0, u_0_1 } ;
int _idx0;
int _idx1;
int _idx10;
int _idx11;
int _idx12;
int _idx13;
int _idx14;
int _idx15;
int _idx2;
int _idx3;
int _idx4;
int _idx5;
int _idx6;
int _idx7;
int _idx8;
int _idx9;
int idx_1_2;
int pt_idx_x;
int pt_idx_y;
int pt_idx_z;
int size_1_1;
int size_1_2;
// int t;
int tmp;
int v_idx_x;
int v_idx_x_max;
int v_idx_y;
int v_idx_y_max;
int v_idx_z;
int v_idx_z_max;
/*
Initializations
*/
size_1_1=(y_max/blockDim.y);
size_1_2=(z_max/blockDim.z);
idx_1_2=(blockIdx.y/size_1_2);
tmp=(blockIdx.y-(idx_1_2*size_1_2));
v_idx_x=(cbx*(threadIdx.x+(blockDim.x*blockIdx.x)));
v_idx_x_max=(v_idx_x+cbx);
v_idx_y=(threadIdx.y+(tmp*blockDim.y));
v_idx_y_max=(v_idx_y+1);
v_idx_z=(threadIdx.z+(idx_1_2*blockDim.z));
v_idx_z_max=(v_idx_z+1);
/*
Implementation
*/
/*
for t = 1..t_max by 1 parallel 1 <level 0> schedule { ... }
*/
// for (t=1; t<=t_max; t+=1)
{
/* Index bounds calculations for iterators in v[t=t, s=(cbx, 1, 1)][0] */
/*
for POINT pt[t=t, s=(1, 1, 1)][0] of size [1, 1, 1] in v[t=t, s=(:, :, :)][0] parallel 1 <level 1> schedule default { ... }
*/
{
/* Index bounds calculations for iterators in pt[t=t, s=(1, 1, 1)][0] */
pt_idx_z=v_idx_z;
pt_idx_y=v_idx_y;
for (pt_idx_x=v_idx_x; pt_idx_x<(v_idx_x_max-0); pt_idx_x+=1)
{
/* Index bounds calculations for iterators in pt[t=t, s=(1, 1, 1)][0] */
/*
v[t=(t+1), s=pt[t=?, s=?][0]][0]=stencil(v[t=t, s=pt[t=?, s=?][0]][0])
*/
/* _idx0 = ((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x) */
_idx0=((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x);
/* _idx1 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+(((((5*pt_idx_z)+15)*t)+pt_idx_y)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+((5*pt_idx_y)*t))+pt_idx_x)+3) */
_idx1=(((_idx0-(3*x_max))-(15*t))+3);
/* _idx2 = ((((((((pt_idx_z*x_max)+((5*pt_idx_z)*t))*y_max)+(((((5*pt_idx_z)*t)+pt_idx_y)+3)*x_max))+((25*pt_idx_z)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx2=((((_idx1+(((-3*x_max)-(15*t))*y_max))+((3-(15*t))*x_max))-(75*(t*t)))+(15*t));
/* _idx3 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+1) */
_idx3=(_idx0+1);
/* _idx4 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+1)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+5)*t))+pt_idx_x)+3) */
_idx4=((_idx1+x_max)+(5*t));
/* _idx5 = (((((((((pt_idx_z+1)*x_max)+(((5*pt_idx_z)+5)*t))*y_max)+((((((5*pt_idx_z)+5)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+25)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx5=(((_idx2+((x_max+(5*t))*y_max))+((5*t)*x_max))+(25*(t*t)));
/* _idx6 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+2) */
_idx6=(_idx0+2);
/* _idx7 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+2)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+10)*t))+pt_idx_x)+3) */
_idx7=((_idx4+x_max)+(5*t));
/* _idx8 = (((((((((pt_idx_z+2)*x_max)+(((5*pt_idx_z)+10)*t))*y_max)+((((((5*pt_idx_z)+10)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+50)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx8=(((_idx5+((x_max+(5*t))*y_max))+((5*t)*x_max))+(25*(t*t)));
/* _idx9 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx9=(_idx0+3);
/* _idx10 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+4) */
_idx10=(_idx0+4);
/* _idx11 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+4)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+20)*t))+pt_idx_x)+3) */
_idx11=((_idx9+x_max)+(5*t));
/* _idx12 = (((((((((pt_idx_z+4)*x_max)+(((5*pt_idx_z)+20)*t))*y_max)+((((((5*pt_idx_z)+20)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+100)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx12=(((_idx9+((x_max+(5*t))*y_max))+((5*t)*x_max))+(25*(t*t)));
/* _idx13 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+5) */
_idx13=(_idx0+5);
/* _idx14 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+5)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+25)*t))+pt_idx_x)+3) */
_idx14=((_idx11+x_max)+(5*t));
/* _idx15 = (((((((((pt_idx_z+5)*x_max)+(((5*pt_idx_z)+25)*t))*y_max)+((((((5*pt_idx_z)+25)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+125)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx15=(((_idx12+((x_max+(5*t))*y_max))+((5*t)*x_max))+(25*(t*t)));
u_0_1[_idx9]=(a*((((u_0_0[_idx0]+(u_0_0[_idx1]+u_0_0[_idx2]))*-2.0)+(((u_0_0[_idx3]+(u_0_0[_idx4]+u_0_0[_idx5]))*15.0)+((u_0_0[_idx6]+(u_0_0[_idx7]+u_0_0[_idx8]))*-60.0)))+((u_0_0[_idx9]*20.0)+(((u_0_0[_idx10]+(u_0_0[_idx11]+u_0_0[_idx12]))*30.0)+((u_0_0[_idx13]+(u_0_0[_idx14]+u_0_0[_idx15]))*-3.0)))));
}
}
}
}
__global__ void initialize(double * u_0_0, double * u_0_1, double a, int x_max, int y_max, int z_max, int cbx)
{
double * const u__u_0[16] = { u_0_0, u_0_1 } ;
int _idx0;
int _idx1;
int _idx10;
int _idx11;
int _idx12;
int _idx13;
int _idx14;
int _idx15;
int _idx2;
int _idx3;
int _idx4;
int _idx5;
int _idx6;
int _idx7;
int _idx8;
int _idx9;
int idx_1_2;
int pt_idx_x;
int pt_idx_y;
int pt_idx_z;
int size_1_1;
int size_1_2;
//int t;
int tmp;
int v_idx_x;
int v_idx_x_max;
int v_idx_y;
int v_idx_y_max;
int v_idx_z;
int v_idx_z_max;
/*
Initializations
*/
size_1_1=(y_max/blockDim.y);
size_1_2=(z_max/blockDim.z);
idx_1_2=(blockIdx.y/size_1_2);
tmp=(blockIdx.y-(idx_1_2*size_1_2));
v_idx_x=(cbx*(threadIdx.x+(blockDim.x*blockIdx.x)));
v_idx_x_max=(v_idx_x+cbx);
v_idx_y=(threadIdx.y+(tmp*blockDim.y));
v_idx_y_max=(v_idx_y+1);
v_idx_z=(threadIdx.z+(idx_1_2*blockDim.z));
v_idx_z_max=(v_idx_z+1);
/*
Implementation
*/
/*
for t = 1..t_max by 1 parallel 1 <level 0> schedule { ... }
*/
//for (t=1; t<=t_max; t+=1)
{
/* Index bounds calculations for iterators in v[t=t, s=(cbx, 1, 1)][0] */
/*
for POINT pt[t=t, s=(1, 1, 1)][0] of size [1, 1, 1] in v[t=t, s=(:, :, :)][0] parallel 1 <level 1> schedule default { ... }
*/
{
/* Index bounds calculations for iterators in pt[t=t, s=(1, 1, 1)][0] */
pt_idx_z=v_idx_z;
pt_idx_y=v_idx_y;
for (pt_idx_x=v_idx_x; pt_idx_x<(v_idx_x_max-0); pt_idx_x+=1)
{
/* Index bounds calculations for iterators in pt[t=t, s=(1, 1, 1)][0] */
/*
v[t=(t+1), s=pt[t=?, s=?][0]][0]=stencil(v[t=t, s=pt[t=?, s=?][0]][0])
*/
/* _idx0 = ((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x) */
_idx0=((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x);
u_0_0[_idx0]=0.1;
/* _idx1 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+1) */
_idx1=(_idx0+1);
u_0_0[_idx1]=0.1;
/* _idx2 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+2) */
_idx2=(_idx0+2);
u_0_0[_idx2]=0.1;
/* _idx3 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+(((((5*pt_idx_z)+15)*t)+pt_idx_y)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+((5*pt_idx_y)*t))+pt_idx_x)+3) */
_idx3=(((_idx0-(3*x_max))-(15*t))+3);
u_0_0[_idx3]=0.1;
/* _idx4 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+1)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+5)*t))+pt_idx_x)+3) */
_idx4=((_idx3+x_max)+(5*t));
u_0_0[_idx4]=0.1;
/* _idx5 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+2)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+10)*t))+pt_idx_x)+3) */
_idx5=((_idx4+x_max)+(5*t));
u_0_0[_idx5]=0.1;
/* _idx6 = ((((((((pt_idx_z*x_max)+((5*pt_idx_z)*t))*y_max)+(((((5*pt_idx_z)*t)+pt_idx_y)+3)*x_max))+((25*pt_idx_z)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx6=((((_idx1+(((-3*x_max)-(15*t))*y_max))-((15*t)*x_max))-(75*(t*t)))+2);
u_0_0[_idx6]=0.1;
/* _idx7 = (((((((((pt_idx_z+1)*x_max)+(((5*pt_idx_z)+5)*t))*y_max)+((((((5*pt_idx_z)+5)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+25)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx7=(((_idx6+((x_max+(5*t))*y_max))+((5*t)*x_max))+(25*(t*t)));
u_0_0[_idx7]=0.1;
/* _idx8 = (((((((((pt_idx_z+2)*x_max)+(((5*pt_idx_z)+10)*t))*y_max)+((((((5*pt_idx_z)+10)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+50)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx8=(((_idx7+((x_max+(5*t))*y_max))+((5*t)*x_max))+(25*(t*t)));
u_0_0[_idx8]=0.1;
/* _idx9 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx9=(_idx0+3);
u_0_0[_idx9]=0.1;
/* _idx10 = (((((((((pt_idx_z+4)*x_max)+(((5*pt_idx_z)+20)*t))*y_max)+((((((5*pt_idx_z)+20)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+100)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx10=(((_idx9+((x_max+(5*t))*y_max))+((5*t)*x_max))+(25*(t*t)));
u_0_0[_idx10]=0.1;
/* _idx11 = (((((((((pt_idx_z+5)*x_max)+(((5*pt_idx_z)+25)*t))*y_max)+((((((5*pt_idx_z)+25)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+125)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx11=(((_idx10+((x_max+(5*t))*y_max))+((5*t)*x_max))+(25*(t*t)));
u_0_0[_idx11]=0.1;
/* _idx12 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+4)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+20)*t))+pt_idx_x)+3) */
_idx12=((_idx9+x_max)+(5*t));
u_0_0[_idx12]=0.1;
/* _idx13 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+5)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+25)*t))+pt_idx_x)+3) */
_idx13=((_idx12+x_max)+(5*t));
u_0_0[_idx13]=0.1;
/* _idx14 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+4) */
_idx14=(_idx0+4);
u_0_0[_idx14]=0.1;
/* _idx15 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+5) */
_idx15=(_idx0+5);
u_0_0[_idx15]=0.1;
u_0_1[_idx9]=1.1;
}
}
}
} | #include <hip/hip_runtime.h>
#define t_max 1
#define t 1
/*
(u[0][0][0][1][0]=(a*((((u[-3][0][0][0][0]+(u[0][-3][0][0][0]+u[0][0][-3][0][0]))*-2.0)+(((u[-2][0][0][0][0]+(u[0][-2][0][0][0]+u[0][0][-2][0][0]))*15.0)+((u[-1][0][0][0][0]+(u[0][-1][0][0][0]+u[0][0][-1][0][0]))*-60.0)))+((u[0][0][0][0][0]*20.0)+(((u[1][0][0][0][0]+(u[0][1][0][0][0]+u[0][0][1][0][0]))*30.0)+((u[2][0][0][0][0]+(u[0][2][0][0][0]+u[0][0][2][0][0]))*-3.0))))))
*/
__global__ void upstream_5_3d(double * * u_0_1_out, double * u_0_0, double * u_0_1, double a, int x_max, int y_max, int z_max, int cbx)
{
// double * const u__u_0[16] = { u_0_0, u_0_1 } ;
int _idx0;
int _idx1;
int _idx10;
int _idx11;
int _idx12;
int _idx13;
int _idx14;
int _idx15;
int _idx2;
int _idx3;
int _idx4;
int _idx5;
int _idx6;
int _idx7;
int _idx8;
int _idx9;
int idx_1_2;
int pt_idx_x;
int pt_idx_y;
int pt_idx_z;
int size_1_1;
int size_1_2;
// int t;
int tmp;
int v_idx_x;
int v_idx_x_max;
int v_idx_y;
int v_idx_y_max;
int v_idx_z;
int v_idx_z_max;
/*
Initializations
*/
size_1_1=(y_max/blockDim.y);
size_1_2=(z_max/blockDim.z);
idx_1_2=(blockIdx.y/size_1_2);
tmp=(blockIdx.y-(idx_1_2*size_1_2));
v_idx_x=(cbx*(threadIdx.x+(blockDim.x*blockIdx.x)));
v_idx_x_max=(v_idx_x+cbx);
v_idx_y=(threadIdx.y+(tmp*blockDim.y));
v_idx_y_max=(v_idx_y+1);
v_idx_z=(threadIdx.z+(idx_1_2*blockDim.z));
v_idx_z_max=(v_idx_z+1);
/*
Implementation
*/
/*
for t = 1..t_max by 1 parallel 1 <level 0> schedule { ... }
*/
// for (t=1; t<=t_max; t+=1)
{
/* Index bounds calculations for iterators in v[t=t, s=(cbx, 1, 1)][0] */
/*
for POINT pt[t=t, s=(1, 1, 1)][0] of size [1, 1, 1] in v[t=t, s=(:, :, :)][0] parallel 1 <level 1> schedule default { ... }
*/
{
/* Index bounds calculations for iterators in pt[t=t, s=(1, 1, 1)][0] */
pt_idx_z=v_idx_z;
pt_idx_y=v_idx_y;
for (pt_idx_x=v_idx_x; pt_idx_x<(v_idx_x_max-0); pt_idx_x+=1)
{
/* Index bounds calculations for iterators in pt[t=t, s=(1, 1, 1)][0] */
/*
v[t=(t+1), s=pt[t=?, s=?][0]][0]=stencil(v[t=t, s=pt[t=?, s=?][0]][0])
*/
/* _idx0 = ((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x) */
_idx0=((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x);
/* _idx1 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+(((((5*pt_idx_z)+15)*t)+pt_idx_y)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+((5*pt_idx_y)*t))+pt_idx_x)+3) */
_idx1=(((_idx0-(3*x_max))-(15*t))+3);
/* _idx2 = ((((((((pt_idx_z*x_max)+((5*pt_idx_z)*t))*y_max)+(((((5*pt_idx_z)*t)+pt_idx_y)+3)*x_max))+((25*pt_idx_z)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx2=((((_idx1+(((-3*x_max)-(15*t))*y_max))+((3-(15*t))*x_max))-(75*(t*t)))+(15*t));
/* _idx3 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+1) */
_idx3=(_idx0+1);
/* _idx4 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+1)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+5)*t))+pt_idx_x)+3) */
_idx4=((_idx1+x_max)+(5*t));
/* _idx5 = (((((((((pt_idx_z+1)*x_max)+(((5*pt_idx_z)+5)*t))*y_max)+((((((5*pt_idx_z)+5)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+25)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx5=(((_idx2+((x_max+(5*t))*y_max))+((5*t)*x_max))+(25*(t*t)));
/* _idx6 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+2) */
_idx6=(_idx0+2);
/* _idx7 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+2)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+10)*t))+pt_idx_x)+3) */
_idx7=((_idx4+x_max)+(5*t));
/* _idx8 = (((((((((pt_idx_z+2)*x_max)+(((5*pt_idx_z)+10)*t))*y_max)+((((((5*pt_idx_z)+10)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+50)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx8=(((_idx5+((x_max+(5*t))*y_max))+((5*t)*x_max))+(25*(t*t)));
/* _idx9 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx9=(_idx0+3);
/* _idx10 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+4) */
_idx10=(_idx0+4);
/* _idx11 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+4)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+20)*t))+pt_idx_x)+3) */
_idx11=((_idx9+x_max)+(5*t));
/* _idx12 = (((((((((pt_idx_z+4)*x_max)+(((5*pt_idx_z)+20)*t))*y_max)+((((((5*pt_idx_z)+20)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+100)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx12=(((_idx9+((x_max+(5*t))*y_max))+((5*t)*x_max))+(25*(t*t)));
/* _idx13 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+5) */
_idx13=(_idx0+5);
/* _idx14 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+5)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+25)*t))+pt_idx_x)+3) */
_idx14=((_idx11+x_max)+(5*t));
/* _idx15 = (((((((((pt_idx_z+5)*x_max)+(((5*pt_idx_z)+25)*t))*y_max)+((((((5*pt_idx_z)+25)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+125)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx15=(((_idx12+((x_max+(5*t))*y_max))+((5*t)*x_max))+(25*(t*t)));
u_0_1[_idx9]=(a*((((u_0_0[_idx0]+(u_0_0[_idx1]+u_0_0[_idx2]))*-2.0)+(((u_0_0[_idx3]+(u_0_0[_idx4]+u_0_0[_idx5]))*15.0)+((u_0_0[_idx6]+(u_0_0[_idx7]+u_0_0[_idx8]))*-60.0)))+((u_0_0[_idx9]*20.0)+(((u_0_0[_idx10]+(u_0_0[_idx11]+u_0_0[_idx12]))*30.0)+((u_0_0[_idx13]+(u_0_0[_idx14]+u_0_0[_idx15]))*-3.0)))));
}
}
}
}
__global__ void initialize(double * u_0_0, double * u_0_1, double a, int x_max, int y_max, int z_max, int cbx)
{
double * const u__u_0[16] = { u_0_0, u_0_1 } ;
int _idx0;
int _idx1;
int _idx10;
int _idx11;
int _idx12;
int _idx13;
int _idx14;
int _idx15;
int _idx2;
int _idx3;
int _idx4;
int _idx5;
int _idx6;
int _idx7;
int _idx8;
int _idx9;
int idx_1_2;
int pt_idx_x;
int pt_idx_y;
int pt_idx_z;
int size_1_1;
int size_1_2;
//int t;
int tmp;
int v_idx_x;
int v_idx_x_max;
int v_idx_y;
int v_idx_y_max;
int v_idx_z;
int v_idx_z_max;
/*
Initializations
*/
size_1_1=(y_max/blockDim.y);
size_1_2=(z_max/blockDim.z);
idx_1_2=(blockIdx.y/size_1_2);
tmp=(blockIdx.y-(idx_1_2*size_1_2));
v_idx_x=(cbx*(threadIdx.x+(blockDim.x*blockIdx.x)));
v_idx_x_max=(v_idx_x+cbx);
v_idx_y=(threadIdx.y+(tmp*blockDim.y));
v_idx_y_max=(v_idx_y+1);
v_idx_z=(threadIdx.z+(idx_1_2*blockDim.z));
v_idx_z_max=(v_idx_z+1);
/*
Implementation
*/
/*
for t = 1..t_max by 1 parallel 1 <level 0> schedule { ... }
*/
//for (t=1; t<=t_max; t+=1)
{
/* Index bounds calculations for iterators in v[t=t, s=(cbx, 1, 1)][0] */
/*
for POINT pt[t=t, s=(1, 1, 1)][0] of size [1, 1, 1] in v[t=t, s=(:, :, :)][0] parallel 1 <level 1> schedule default { ... }
*/
{
/* Index bounds calculations for iterators in pt[t=t, s=(1, 1, 1)][0] */
pt_idx_z=v_idx_z;
pt_idx_y=v_idx_y;
for (pt_idx_x=v_idx_x; pt_idx_x<(v_idx_x_max-0); pt_idx_x+=1)
{
/* Index bounds calculations for iterators in pt[t=t, s=(1, 1, 1)][0] */
/*
v[t=(t+1), s=pt[t=?, s=?][0]][0]=stencil(v[t=t, s=pt[t=?, s=?][0]][0])
*/
/* _idx0 = ((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x) */
_idx0=((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x);
u_0_0[_idx0]=0.1;
/* _idx1 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+1) */
_idx1=(_idx0+1);
u_0_0[_idx1]=0.1;
/* _idx2 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+2) */
_idx2=(_idx0+2);
u_0_0[_idx2]=0.1;
/* _idx3 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+(((((5*pt_idx_z)+15)*t)+pt_idx_y)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+((5*pt_idx_y)*t))+pt_idx_x)+3) */
_idx3=(((_idx0-(3*x_max))-(15*t))+3);
u_0_0[_idx3]=0.1;
/* _idx4 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+1)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+5)*t))+pt_idx_x)+3) */
_idx4=((_idx3+x_max)+(5*t));
u_0_0[_idx4]=0.1;
/* _idx5 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+2)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+10)*t))+pt_idx_x)+3) */
_idx5=((_idx4+x_max)+(5*t));
u_0_0[_idx5]=0.1;
/* _idx6 = ((((((((pt_idx_z*x_max)+((5*pt_idx_z)*t))*y_max)+(((((5*pt_idx_z)*t)+pt_idx_y)+3)*x_max))+((25*pt_idx_z)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx6=((((_idx1+(((-3*x_max)-(15*t))*y_max))-((15*t)*x_max))-(75*(t*t)))+2);
u_0_0[_idx6]=0.1;
/* _idx7 = (((((((((pt_idx_z+1)*x_max)+(((5*pt_idx_z)+5)*t))*y_max)+((((((5*pt_idx_z)+5)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+25)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx7=(((_idx6+((x_max+(5*t))*y_max))+((5*t)*x_max))+(25*(t*t)));
u_0_0[_idx7]=0.1;
/* _idx8 = (((((((((pt_idx_z+2)*x_max)+(((5*pt_idx_z)+10)*t))*y_max)+((((((5*pt_idx_z)+10)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+50)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx8=(((_idx7+((x_max+(5*t))*y_max))+((5*t)*x_max))+(25*(t*t)));
u_0_0[_idx8]=0.1;
/* _idx9 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx9=(_idx0+3);
u_0_0[_idx9]=0.1;
/* _idx10 = (((((((((pt_idx_z+4)*x_max)+(((5*pt_idx_z)+20)*t))*y_max)+((((((5*pt_idx_z)+20)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+100)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx10=(((_idx9+((x_max+(5*t))*y_max))+((5*t)*x_max))+(25*(t*t)));
u_0_0[_idx10]=0.1;
/* _idx11 = (((((((((pt_idx_z+5)*x_max)+(((5*pt_idx_z)+25)*t))*y_max)+((((((5*pt_idx_z)+25)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+125)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx11=(((_idx10+((x_max+(5*t))*y_max))+((5*t)*x_max))+(25*(t*t)));
u_0_0[_idx11]=0.1;
/* _idx12 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+4)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+20)*t))+pt_idx_x)+3) */
_idx12=((_idx9+x_max)+(5*t));
u_0_0[_idx12]=0.1;
/* _idx13 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+5)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+25)*t))+pt_idx_x)+3) */
_idx13=((_idx12+x_max)+(5*t));
u_0_0[_idx13]=0.1;
/* _idx14 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+4) */
_idx14=(_idx0+4);
u_0_0[_idx14]=0.1;
/* _idx15 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+5) */
_idx15=(_idx0+5);
u_0_0[_idx15]=0.1;
u_0_1[_idx9]=1.1;
}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#define t_max 1
#define t 1
/*
(u[0][0][0][1][0]=(a*((((u[-3][0][0][0][0]+(u[0][-3][0][0][0]+u[0][0][-3][0][0]))*-2.0)+(((u[-2][0][0][0][0]+(u[0][-2][0][0][0]+u[0][0][-2][0][0]))*15.0)+((u[-1][0][0][0][0]+(u[0][-1][0][0][0]+u[0][0][-1][0][0]))*-60.0)))+((u[0][0][0][0][0]*20.0)+(((u[1][0][0][0][0]+(u[0][1][0][0][0]+u[0][0][1][0][0]))*30.0)+((u[2][0][0][0][0]+(u[0][2][0][0][0]+u[0][0][2][0][0]))*-3.0))))))
*/
__global__ void upstream_5_3d(double * * u_0_1_out, double * u_0_0, double * u_0_1, double a, int x_max, int y_max, int z_max, int cbx)
{
// double * const u__u_0[16] = { u_0_0, u_0_1 } ;
int _idx0;
int _idx1;
int _idx10;
int _idx11;
int _idx12;
int _idx13;
int _idx14;
int _idx15;
int _idx2;
int _idx3;
int _idx4;
int _idx5;
int _idx6;
int _idx7;
int _idx8;
int _idx9;
int idx_1_2;
int pt_idx_x;
int pt_idx_y;
int pt_idx_z;
int size_1_1;
int size_1_2;
// int t;
int tmp;
int v_idx_x;
int v_idx_x_max;
int v_idx_y;
int v_idx_y_max;
int v_idx_z;
int v_idx_z_max;
/*
Initializations
*/
size_1_1=(y_max/blockDim.y);
size_1_2=(z_max/blockDim.z);
idx_1_2=(blockIdx.y/size_1_2);
tmp=(blockIdx.y-(idx_1_2*size_1_2));
v_idx_x=(cbx*(threadIdx.x+(blockDim.x*blockIdx.x)));
v_idx_x_max=(v_idx_x+cbx);
v_idx_y=(threadIdx.y+(tmp*blockDim.y));
v_idx_y_max=(v_idx_y+1);
v_idx_z=(threadIdx.z+(idx_1_2*blockDim.z));
v_idx_z_max=(v_idx_z+1);
/*
Implementation
*/
/*
for t = 1..t_max by 1 parallel 1 <level 0> schedule { ... }
*/
// for (t=1; t<=t_max; t+=1)
{
/* Index bounds calculations for iterators in v[t=t, s=(cbx, 1, 1)][0] */
/*
for POINT pt[t=t, s=(1, 1, 1)][0] of size [1, 1, 1] in v[t=t, s=(:, :, :)][0] parallel 1 <level 1> schedule default { ... }
*/
{
/* Index bounds calculations for iterators in pt[t=t, s=(1, 1, 1)][0] */
pt_idx_z=v_idx_z;
pt_idx_y=v_idx_y;
for (pt_idx_x=v_idx_x; pt_idx_x<(v_idx_x_max-0); pt_idx_x+=1)
{
/* Index bounds calculations for iterators in pt[t=t, s=(1, 1, 1)][0] */
/*
v[t=(t+1), s=pt[t=?, s=?][0]][0]=stencil(v[t=t, s=pt[t=?, s=?][0]][0])
*/
/* _idx0 = ((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x) */
_idx0=((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x);
/* _idx1 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+(((((5*pt_idx_z)+15)*t)+pt_idx_y)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+((5*pt_idx_y)*t))+pt_idx_x)+3) */
_idx1=(((_idx0-(3*x_max))-(15*t))+3);
/* _idx2 = ((((((((pt_idx_z*x_max)+((5*pt_idx_z)*t))*y_max)+(((((5*pt_idx_z)*t)+pt_idx_y)+3)*x_max))+((25*pt_idx_z)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx2=((((_idx1+(((-3*x_max)-(15*t))*y_max))+((3-(15*t))*x_max))-(75*(t*t)))+(15*t));
/* _idx3 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+1) */
_idx3=(_idx0+1);
/* _idx4 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+1)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+5)*t))+pt_idx_x)+3) */
_idx4=((_idx1+x_max)+(5*t));
/* _idx5 = (((((((((pt_idx_z+1)*x_max)+(((5*pt_idx_z)+5)*t))*y_max)+((((((5*pt_idx_z)+5)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+25)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx5=(((_idx2+((x_max+(5*t))*y_max))+((5*t)*x_max))+(25*(t*t)));
/* _idx6 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+2) */
_idx6=(_idx0+2);
/* _idx7 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+2)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+10)*t))+pt_idx_x)+3) */
_idx7=((_idx4+x_max)+(5*t));
/* _idx8 = (((((((((pt_idx_z+2)*x_max)+(((5*pt_idx_z)+10)*t))*y_max)+((((((5*pt_idx_z)+10)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+50)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx8=(((_idx5+((x_max+(5*t))*y_max))+((5*t)*x_max))+(25*(t*t)));
/* _idx9 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx9=(_idx0+3);
/* _idx10 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+4) */
_idx10=(_idx0+4);
/* _idx11 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+4)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+20)*t))+pt_idx_x)+3) */
_idx11=((_idx9+x_max)+(5*t));
/* _idx12 = (((((((((pt_idx_z+4)*x_max)+(((5*pt_idx_z)+20)*t))*y_max)+((((((5*pt_idx_z)+20)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+100)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx12=(((_idx9+((x_max+(5*t))*y_max))+((5*t)*x_max))+(25*(t*t)));
/* _idx13 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+5) */
_idx13=(_idx0+5);
/* _idx14 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+5)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+25)*t))+pt_idx_x)+3) */
_idx14=((_idx11+x_max)+(5*t));
/* _idx15 = (((((((((pt_idx_z+5)*x_max)+(((5*pt_idx_z)+25)*t))*y_max)+((((((5*pt_idx_z)+25)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+125)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx15=(((_idx12+((x_max+(5*t))*y_max))+((5*t)*x_max))+(25*(t*t)));
u_0_1[_idx9]=(a*((((u_0_0[_idx0]+(u_0_0[_idx1]+u_0_0[_idx2]))*-2.0)+(((u_0_0[_idx3]+(u_0_0[_idx4]+u_0_0[_idx5]))*15.0)+((u_0_0[_idx6]+(u_0_0[_idx7]+u_0_0[_idx8]))*-60.0)))+((u_0_0[_idx9]*20.0)+(((u_0_0[_idx10]+(u_0_0[_idx11]+u_0_0[_idx12]))*30.0)+((u_0_0[_idx13]+(u_0_0[_idx14]+u_0_0[_idx15]))*-3.0)))));
}
}
}
}
__global__ void initialize(double * u_0_0, double * u_0_1, double a, int x_max, int y_max, int z_max, int cbx)
{
double * const u__u_0[16] = { u_0_0, u_0_1 } ;
int _idx0;
int _idx1;
int _idx10;
int _idx11;
int _idx12;
int _idx13;
int _idx14;
int _idx15;
int _idx2;
int _idx3;
int _idx4;
int _idx5;
int _idx6;
int _idx7;
int _idx8;
int _idx9;
int idx_1_2;
int pt_idx_x;
int pt_idx_y;
int pt_idx_z;
int size_1_1;
int size_1_2;
//int t;
int tmp;
int v_idx_x;
int v_idx_x_max;
int v_idx_y;
int v_idx_y_max;
int v_idx_z;
int v_idx_z_max;
/*
Initializations
*/
size_1_1=(y_max/blockDim.y);
size_1_2=(z_max/blockDim.z);
idx_1_2=(blockIdx.y/size_1_2);
tmp=(blockIdx.y-(idx_1_2*size_1_2));
v_idx_x=(cbx*(threadIdx.x+(blockDim.x*blockIdx.x)));
v_idx_x_max=(v_idx_x+cbx);
v_idx_y=(threadIdx.y+(tmp*blockDim.y));
v_idx_y_max=(v_idx_y+1);
v_idx_z=(threadIdx.z+(idx_1_2*blockDim.z));
v_idx_z_max=(v_idx_z+1);
/*
Implementation
*/
/*
for t = 1..t_max by 1 parallel 1 <level 0> schedule { ... }
*/
//for (t=1; t<=t_max; t+=1)
{
/* Index bounds calculations for iterators in v[t=t, s=(cbx, 1, 1)][0] */
/*
for POINT pt[t=t, s=(1, 1, 1)][0] of size [1, 1, 1] in v[t=t, s=(:, :, :)][0] parallel 1 <level 1> schedule default { ... }
*/
{
/* Index bounds calculations for iterators in pt[t=t, s=(1, 1, 1)][0] */
pt_idx_z=v_idx_z;
pt_idx_y=v_idx_y;
for (pt_idx_x=v_idx_x; pt_idx_x<(v_idx_x_max-0); pt_idx_x+=1)
{
/* Index bounds calculations for iterators in pt[t=t, s=(1, 1, 1)][0] */
/*
v[t=(t+1), s=pt[t=?, s=?][0]][0]=stencil(v[t=t, s=pt[t=?, s=?][0]][0])
*/
/* _idx0 = ((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x) */
_idx0=((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x);
u_0_0[_idx0]=0.1;
/* _idx1 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+1) */
_idx1=(_idx0+1);
u_0_0[_idx1]=0.1;
/* _idx2 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+2) */
_idx2=(_idx0+2);
u_0_0[_idx2]=0.1;
/* _idx3 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+(((((5*pt_idx_z)+15)*t)+pt_idx_y)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+((5*pt_idx_y)*t))+pt_idx_x)+3) */
_idx3=(((_idx0-(3*x_max))-(15*t))+3);
u_0_0[_idx3]=0.1;
/* _idx4 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+1)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+5)*t))+pt_idx_x)+3) */
_idx4=((_idx3+x_max)+(5*t));
u_0_0[_idx4]=0.1;
/* _idx5 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+2)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+10)*t))+pt_idx_x)+3) */
_idx5=((_idx4+x_max)+(5*t));
u_0_0[_idx5]=0.1;
/* _idx6 = ((((((((pt_idx_z*x_max)+((5*pt_idx_z)*t))*y_max)+(((((5*pt_idx_z)*t)+pt_idx_y)+3)*x_max))+((25*pt_idx_z)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx6=((((_idx1+(((-3*x_max)-(15*t))*y_max))-((15*t)*x_max))-(75*(t*t)))+2);
u_0_0[_idx6]=0.1;
/* _idx7 = (((((((((pt_idx_z+1)*x_max)+(((5*pt_idx_z)+5)*t))*y_max)+((((((5*pt_idx_z)+5)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+25)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx7=(((_idx6+((x_max+(5*t))*y_max))+((5*t)*x_max))+(25*(t*t)));
u_0_0[_idx7]=0.1;
/* _idx8 = (((((((((pt_idx_z+2)*x_max)+(((5*pt_idx_z)+10)*t))*y_max)+((((((5*pt_idx_z)+10)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+50)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx8=(((_idx7+((x_max+(5*t))*y_max))+((5*t)*x_max))+(25*(t*t)));
u_0_0[_idx8]=0.1;
/* _idx9 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx9=(_idx0+3);
u_0_0[_idx9]=0.1;
/* _idx10 = (((((((((pt_idx_z+4)*x_max)+(((5*pt_idx_z)+20)*t))*y_max)+((((((5*pt_idx_z)+20)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+100)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx10=(((_idx9+((x_max+(5*t))*y_max))+((5*t)*x_max))+(25*(t*t)));
u_0_0[_idx10]=0.1;
/* _idx11 = (((((((((pt_idx_z+5)*x_max)+(((5*pt_idx_z)+25)*t))*y_max)+((((((5*pt_idx_z)+25)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+125)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx11=(((_idx10+((x_max+(5*t))*y_max))+((5*t)*x_max))+(25*(t*t)));
u_0_0[_idx11]=0.1;
/* _idx12 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+4)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+20)*t))+pt_idx_x)+3) */
_idx12=((_idx9+x_max)+(5*t));
u_0_0[_idx12]=0.1;
/* _idx13 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+5)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+25)*t))+pt_idx_x)+3) */
_idx13=((_idx12+x_max)+(5*t));
u_0_0[_idx13]=0.1;
/* _idx14 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+4) */
_idx14=(_idx0+4);
u_0_0[_idx14]=0.1;
/* _idx15 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+5) */
_idx15=(_idx0+5);
u_0_0[_idx15]=0.1;
u_0_1[_idx9]=1.1;
}
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13upstream_5_3dPPdS_S_diiii
.globl _Z13upstream_5_3dPPdS_S_diiii
.p2align 8
.type _Z13upstream_5_3dPPdS_S_diiii,@function
_Z13upstream_5_3dPPdS_S_diiii:
s_load_b32 s18, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s18, 1
s_cbranch_scc1 .LBB0_3
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x3c
s_load_b256 s[4:11], s[0:1], 0x8
s_load_b32 s0, s[0:1], 0x28
v_bfe_u32 v6, v0, 10, 10
s_delay_alu instid0(VALU_DEP_1)
v_mul_u32_u24_e32 v12, 5, v6
s_waitcnt lgkmcnt(0)
s_and_b32 s19, s2, 0xffff
s_add_u32 s12, s4, 40
s_addc_u32 s13, s5, 0
s_add_u32 s16, s4, 0xc8
s_addc_u32 s17, s5, 0
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s3
s_sub_i32 s20, 0, s3
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_readfirstlane_b32 s1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s20, s20, s1
s_mul_hi_u32 s20, s1, s20
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s1, s1, s20
s_mul_hi_u32 s1, s0, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s20, s1, s3
s_sub_i32 s0, s0, s20
s_add_i32 s20, s1, 1
s_sub_i32 s21, s0, s3
s_cmp_ge_u32 s0, s3
s_cselect_b32 s1, s20, s1
s_cselect_b32 s0, s21, s0
s_add_i32 s20, s1, 1
s_cmp_ge_u32 s0, s3
s_cselect_b32 s0, s20, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s0
s_sub_i32 s20, 0, s0
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_readfirstlane_b32 s1, v1
v_and_b32_e32 v1, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_i32 s20, s20, s1
v_mad_u64_u32 v[2:3], null, s14, s19, v[1:2]
s_mul_hi_u32 s14, s1, s20
v_bfe_u32 v3, v0, 20, 10
s_add_i32 s1, s1, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s1, s15, s1
s_mul_i32 s14, s1, s0
s_add_i32 s19, s1, 1
s_sub_i32 s14, s15, s14
v_mul_lo_u32 v0, v2, s18
s_sub_i32 s20, s14, s0
s_cmp_ge_u32 s14, s0
s_cselect_b32 s1, s19, s1
s_cselect_b32 s14, s20, s14
s_add_i32 s19, s1, 1
s_cmp_ge_u32 s14, s0
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v1, s18, v0
s_cselect_b32 s1, s19, s1
s_add_i32 s14, s10, 5
v_mad_u64_u32 v[4:5], null, s1, s3, v[3:4]
s_mul_i32 s1, s1, s0
s_mul_i32 s3, s14, s11
s_lshr_b32 s2, s2, 16
s_sub_i32 s0, s15, s1
s_add_i32 s14, s3, 25
s_mul_i32 s2, s0, s2
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v3, 3, v4
v_add_nc_u32_e32 v5, 5, v4
v_add_nc_u32_e32 v7, 4, v4
v_lshl_add_u32 v2, v4, 2, v4
v_mul_lo_u32 v13, v4, 25
v_mul_lo_u32 v8, v4, s14
v_mul_lo_u32 v3, v3, s10
v_mul_lo_u32 v4, s10, v5
v_mul_lo_u32 v5, s10, v7
v_add3_u32 v6, v6, s2, v2
s_lshl_b32 s1, s3, 1
s_mul_i32 s0, s2, 5
s_mov_b32 s2, 0
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v14, 3, v6
v_add_nc_u32_e32 v7, 17, v6
v_add_nc_u32_e32 v9, 16, v6
v_add_nc_u32_e32 v10, 13, v6
v_add_nc_u32_e32 v11, 8, v6
v_add_nc_u32_e32 v15, 15, v6
v_add_nc_u32_e32 v16, 28, v6
v_add_nc_u32_e32 v17, 23, v6
v_add_nc_u32_e32 v18, 20, v6
v_add_nc_u32_e32 v19, 19, v6
v_add_nc_u32_e32 v6, 18, v6
v_add3_u32 v20, v2, v3, 15
v_add3_u32 v21, v4, v2, 25
v_add3_u32 v5, v5, v2, 20
v_mad_u64_u32 v[2:3], null, s10, v14, s[0:1]
v_mad_u64_u32 v[3:4], null, s10, v6, s[0:1]
v_mul_lo_u32 v7, s10, v7
v_mul_lo_u32 v9, s10, v9
v_mul_lo_u32 v10, s10, v10
v_mul_lo_u32 v11, s10, v11
v_mul_lo_u32 v14, s10, v15
v_mul_lo_u32 v15, s10, v16
v_mul_lo_u32 v16, s10, v17
v_mul_lo_u32 v17, s10, v18
v_mul_lo_u32 v18, s10, v19
v_mul_lo_u32 v19, s11, v20
v_mul_lo_u32 v4, s11, v21
v_mul_lo_u32 v5, s11, v5
v_add3_u32 v6, s0, s1, v10
v_add3_u32 v10, s0, v11, v0
v_add3_u32 v2, v2, v0, v8
s_mov_b32 s1, 0
v_add3_u32 v7, s0, v7, v19
v_add3_u32 v9, s0, v9, v19
v_add3_u32 v11, s0, v14, v19
v_add3_u32 v4, s0, v15, v4
v_add3_u32 v5, s0, v16, v5
v_add3_u32 v14, s0, v17, v19
v_add3_u32 v15, s0, v18, v19
v_add3_u32 v16, v3, v19, v0
v_add3_u32 v3, v6, v0, v8
v_add3_u32 v6, v10, v8, s3
v_add3_u32 v7, v7, v0, v13
v_add3_u32 v8, v9, v0, v13
v_add3_u32 v9, v11, v0, v13
v_add3_u32 v10, v4, v0, v13
v_add3_u32 v11, v5, v0, v13
v_add3_u32 v14, v14, v0, v13
v_add3_u32 v15, v15, v0, v13
v_add3_u32 v2, v2, v12, 18
v_add3_u32 v3, v3, v12, 43
v_add3_u32 v4, v6, v12, 43
v_add3_u32 v5, v7, v12, 0x53
v_add3_u32 v6, v8, v12, 0x53
v_add3_u32 v7, v9, v12, 0x4e
v_add3_u32 v8, v10, v12, 0x76
v_add3_u32 v9, v11, v12, 0x76
v_add3_u32 v10, v14, v12, 0x62
v_add3_u32 v11, v15, v12, 0x62
v_add3_u32 v12, v16, v13, v12
.LBB0_2:
v_add_nc_u32_e32 v14, s2, v2
v_add_nc_u32_e32 v16, s2, v6
v_add_nc_u32_e32 v18, s2, v4
v_add_nc_u32_e32 v20, s2, v5
v_add_nc_u32_e32 v22, s2, v3
v_ashrrev_i32_e32 v15, 31, v14
v_ashrrev_i32_e32 v17, 31, v16
v_ashrrev_i32_e32 v19, 31, v18
v_ashrrev_i32_e32 v21, 31, v20
v_add_nc_u32_e32 v25, s2, v10
v_lshlrev_b64 v[14:15], 3, v[14:15]
v_lshlrev_b64 v[16:17], 3, v[16:17]
v_lshlrev_b64 v[18:19], 3, v[18:19]
v_ashrrev_i32_e32 v23, 31, v22
v_add_nc_u32_e32 v27, s2, v8
v_lshlrev_b64 v[20:21], 3, v[20:21]
v_add_co_u32 v14, vcc_lo, s4, v14
v_add_co_ci_u32_e32 v15, vcc_lo, s5, v15, vcc_lo
v_add_co_u32 v16, vcc_lo, s4, v16
v_ashrrev_i32_e32 v26, 31, v25
v_add_co_ci_u32_e32 v17, vcc_lo, s5, v17, vcc_lo
v_lshlrev_b64 v[22:23], 3, v[22:23]
v_add_co_u32 v18, vcc_lo, s4, v18
v_ashrrev_i32_e32 v28, 31, v27
v_add_co_ci_u32_e32 v19, vcc_lo, s5, v19, vcc_lo
v_lshlrev_b64 v[25:26], 3, v[25:26]
v_add_co_u32 v20, vcc_lo, s12, v20
v_add_co_ci_u32_e32 v21, vcc_lo, s13, v21, vcc_lo
v_lshlrev_b64 v[27:28], 3, v[27:28]
v_add_co_u32 v22, vcc_lo, s16, v22
v_add_co_ci_u32_e32 v23, vcc_lo, s17, v23, vcc_lo
v_add_co_u32 v25, vcc_lo, s12, v25
v_add_co_ci_u32_e32 v26, vcc_lo, s13, v26, vcc_lo
v_add_co_u32 v27, vcc_lo, s16, v27
v_add_co_ci_u32_e32 v28, vcc_lo, s17, v28, vcc_lo
s_clause 0x6
global_load_b64 v[29:30], v[14:15], off
global_load_b64 v[31:32], v[16:17], off
global_load_b64 v[33:34], v[18:19], off
global_load_b64 v[35:36], v[20:21], off
global_load_b64 v[21:22], v[22:23], off
global_load_b64 v[37:38], v[25:26], off
global_load_b64 v[26:27], v[27:28], off
v_add_nc_u32_e32 v13, s2, v7
v_add_nc_u32_e32 v24, s2, v11
v_add_nc_u32_e32 v39, s2, v12
v_add_nc_u32_e32 v15, s2, v9
s_add_i32 s2, s2, 1
v_ashrrev_i32_e32 v14, 31, v13
v_ashrrev_i32_e32 v25, 31, v24
v_add_nc_u32_e32 v17, 0x5a, v39
v_add_nc_u32_e32 v19, 0x5d, v39
v_ashrrev_i32_e32 v16, 31, v15
v_lshlrev_b64 v[13:14], 3, v[13:14]
v_lshlrev_b64 v[23:24], 3, v[24:25]
v_ashrrev_i32_e32 v18, 31, v17
v_ashrrev_i32_e32 v20, 31, v19
v_lshlrev_b64 v[15:16], 3, v[15:16]
v_add_co_u32 v13, vcc_lo, s4, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s5, v14, vcc_lo
v_lshlrev_b64 v[17:18], 3, v[17:18]
v_lshlrev_b64 v[39:40], 3, v[19:20]
v_add_co_u32 v19, vcc_lo, s4, v23
v_add_co_ci_u32_e32 v20, vcc_lo, s5, v24, vcc_lo
v_add_co_u32 v15, vcc_lo, s4, v15
v_add_co_ci_u32_e32 v16, vcc_lo, s5, v16, vcc_lo
v_add_co_u32 v17, vcc_lo, s4, v17
v_add_co_ci_u32_e32 v18, vcc_lo, s5, v18, vcc_lo
v_add_co_u32 v23, vcc_lo, s4, v39
v_add_co_ci_u32_e32 v24, vcc_lo, s5, v40, vcc_lo
s_clause 0x6
global_load_b64 v[41:42], v[13:14], off
global_load_b64 v[43:44], v[19:20], off
global_load_b64 v[45:46], v[15:16], off
global_load_b64 v[47:48], v[17:18], off offset:16
global_load_b128 v[13:16], v[17:18], off offset:32
global_load_b128 v[17:20], v[17:18], off
global_load_b64 v[23:24], v[23:24], off
s_waitcnt vmcnt(9)
v_add_f64 v[21:22], v[35:36], v[21:22]
s_waitcnt vmcnt(7)
v_add_f64 v[25:26], v[37:38], v[26:27]
v_add_f64 v[27:28], v[31:32], v[33:34]
s_waitcnt vmcnt(4)
v_add_f64 v[31:32], v[43:44], v[45:46]
s_waitcnt vmcnt(3)
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_f64 v[21:22], v[47:48], v[21:22]
s_waitcnt vmcnt(2)
v_add_f64 v[15:16], v[15:16], v[25:26]
v_add_f64 v[25:26], v[41:42], v[29:30]
s_waitcnt vmcnt(1)
v_add_f64 v[19:20], v[19:20], v[27:28]
v_add_f64 v[13:14], v[13:14], v[31:32]
v_mul_f64 v[21:22], v[21:22], 0xc04e0000
v_mul_f64 v[15:16], v[15:16], 0xc0080000
v_add_f64 v[17:18], v[17:18], v[25:26]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[19:20], v[19:20], 0x402e0000, v[21:22]
v_fma_f64 v[13:14], v[13:14], 0x403e0000, v[15:16]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[15:16], v[17:18], -2.0, v[19:20]
s_waitcnt vmcnt(0)
v_fma_f64 v[13:14], v[23:24], 0x40340000, v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[13:14], v[15:16], v[13:14]
v_add_nc_u32_e32 v15, s2, v0
v_cmp_ge_i32_e32 vcc_lo, v15, v1
v_add_co_u32 v15, s0, s6, v39
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v16, s0, s7, v40, s0
s_or_b32 s1, vcc_lo, s1
v_mul_f64 v[13:14], v[13:14], s[8:9]
global_store_b64 v[15:16], v[13:14], off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13upstream_5_3dPPdS_S_diiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 49
.amdhsa_next_free_sgpr 22
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13upstream_5_3dPPdS_S_diiii, .Lfunc_end0-_Z13upstream_5_3dPPdS_S_diiii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10initializePdS_diiii
.globl _Z10initializePdS_diiii
.p2align 8
.type _Z10initializePdS_diiii,@function
_Z10initializePdS_diiii:
s_load_b32 s16, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s16, 1
s_cbranch_scc1 .LBB1_3
s_clause 0x3
s_load_b64 s[8:9], s[0:1], 0x34
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b32 s0, s[0:1], 0x20
v_bfe_u32 v2, v0, 20, 10
v_bfe_u32 v5, v0, 10, 10
s_delay_alu instid0(VALU_DEP_1)
v_mul_u32_u24_e32 v18, 5, v5
s_waitcnt lgkmcnt(0)
s_and_b32 s17, s8, 0xffff
s_add_u32 s10, s4, 40
s_addc_u32 s11, s5, 0
s_add_u32 s12, s4, 0xc8
s_addc_u32 s13, s5, 0
s_and_b32 s18, s9, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s18
s_sub_i32 s9, 0, s18
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_readfirstlane_b32 s1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s9, s9, s1
s_mul_hi_u32 s9, s1, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s1, s1, s9
s_mul_hi_u32 s1, s0, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s9, s1, s18
s_sub_i32 s0, s0, s9
s_add_i32 s9, s1, 1
s_sub_i32 s19, s0, s18
s_cmp_ge_u32 s0, s18
s_cselect_b32 s1, s9, s1
s_cselect_b32 s0, s19, s0
s_add_i32 s9, s1, 1
s_cmp_ge_u32 s0, s18
s_cselect_b32 s0, s9, s1
s_mov_b32 s9, 0
v_cvt_f32_u32_e32 v1, s0
s_sub_i32 s19, 0, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_readfirstlane_b32 s1, v1
v_and_b32_e32 v1, 0x3ff, v0
s_mul_i32 s19, s19, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, s14, s17, v[1:2]
s_mul_hi_u32 s14, s1, s19
s_add_i32 s1, s1, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s1, s15, s1
s_mul_i32 s14, s1, s0
s_add_i32 s17, s1, 1
s_sub_i32 s14, s15, s14
s_delay_alu instid0(VALU_DEP_1)
v_mul_lo_u32 v6, v3, s16
s_sub_i32 s19, s14, s0
s_cmp_ge_u32 s14, s0
v_mov_b32_e32 v0, 0x9999999a
s_cselect_b32 s1, s17, s1
s_cselect_b32 s14, s19, s14
s_add_i32 s17, s1, 1
s_cmp_ge_u32 s14, s0
v_add_nc_u32_e32 v7, s16, v6
s_cselect_b32 s1, s17, s1
s_add_i32 s14, s2, 5
v_mad_u64_u32 v[3:4], null, s1, s18, v[2:3]
s_mul_i32 s1, s1, s0
s_mul_i32 s14, s14, s3
s_lshr_b32 s8, s8, 16
s_sub_i32 s0, s15, s1
s_add_i32 s15, s14, 25
s_mul_i32 s8, s0, s8
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v4, 3, v3
v_add_nc_u32_e32 v8, 5, v3
v_add_nc_u32_e32 v9, 4, v3
v_lshl_add_u32 v2, v3, 2, v3
v_mul_lo_u32 v10, v3, 25
v_mul_lo_u32 v11, v3, s15
v_mul_lo_u32 v3, v4, s2
v_mul_lo_u32 v4, s2, v8
v_mul_lo_u32 v8, s2, v9
v_add3_u32 v5, v5, s8, v2
v_mov_b32_e32 v1, 0x3fb99999
s_lshl_b32 s1, s14, 1
s_mul_i32 s0, s8, 5
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v12, 17, v5
v_add_nc_u32_e32 v14, 18, v5
v_add_nc_u32_e32 v17, 3, v5
v_add_nc_u32_e32 v9, 16, v5
v_add_nc_u32_e32 v13, 15, v5
v_add_nc_u32_e32 v15, 13, v5
v_add_nc_u32_e32 v16, 8, v5
v_add_nc_u32_e32 v19, 19, v5
v_add_nc_u32_e32 v20, 20, v5
v_add_nc_u32_e32 v21, 28, v5
v_add_nc_u32_e32 v5, 23, v5
v_add3_u32 v22, v2, v3, 15
v_add3_u32 v23, v4, v2, 25
v_add3_u32 v8, v8, v2, 20
v_mad_u64_u32 v[2:3], null, s2, v14, s[0:1]
v_mad_u64_u32 v[3:4], null, s2, v17, s[0:1]
v_mul_lo_u32 v9, s2, v9
v_mul_lo_u32 v12, s2, v12
v_mul_lo_u32 v13, s2, v13
v_mul_lo_u32 v14, s2, v15
v_mul_lo_u32 v15, s2, v16
v_mul_lo_u32 v4, s2, v19
v_mul_lo_u32 v16, s2, v20
v_mul_lo_u32 v17, s3, v22
v_mul_lo_u32 v19, s2, v21
v_mul_lo_u32 v5, s2, v5
v_mul_lo_u32 v20, s3, v23
v_mul_lo_u32 v8, s3, v8
v_add3_u32 v14, s0, s1, v14
v_add3_u32 v15, s0, v15, v6
v_add3_u32 v3, v3, v6, v11
v_add3_u32 v9, s0, v9, v17
v_add3_u32 v12, s0, v12, v17
v_add3_u32 v13, s0, v13, v17
v_add3_u32 v2, v2, v17, v6
v_add3_u32 v4, s0, v4, v17
v_add3_u32 v16, s0, v16, v17
v_add3_u32 v17, s0, v19, v20
v_add3_u32 v5, s0, v5, v8
v_add3_u32 v14, v14, v6, v11
v_add3_u32 v11, v15, v11, s14
v_add3_u32 v8, v3, v18, 18
v_add3_u32 v3, v9, v6, v10
v_add3_u32 v15, v12, v6, v10
v_add3_u32 v19, v13, v6, v10
v_add3_u32 v9, v2, v10, v18
v_add3_u32 v2, v4, v6, v10
v_add3_u32 v4, v16, v6, v10
v_add3_u32 v17, v17, v6, v10
v_add3_u32 v5, v5, v6, v10
v_add3_u32 v10, v14, v18, 43
v_add3_u32 v11, v11, v18, 43
v_add3_u32 v12, v3, v18, 0x53
v_add3_u32 v13, v15, v18, 0x53
v_add3_u32 v14, v19, v18, 0x4e
v_add3_u32 v15, v2, v18, 0x62
v_add3_u32 v16, v4, v18, 0x62
v_add3_u32 v17, v17, v18, 0x76
v_add3_u32 v18, v5, v18, 0x76
v_mov_b32_e32 v5, 0x3ff19999
s_mov_b32 s1, 0x3fb99999
s_mov_b32 s0, 0x9999999a
s_mov_b32 s2, 0
.LBB1_2:
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v20, s1 :: v_dual_add_nc_u32 v21, s2, v14
v_dual_mov_b32 v2, v0 :: v_dual_add_nc_u32 v23, s2, v12
v_dual_mov_b32 v19, s0 :: v_dual_add_nc_u32 v34, s2, v9
v_dual_mov_b32 v4, v0 :: v_dual_add_nc_u32 v25, s2, v13
v_add_nc_u32_e32 v27, s2, v8
v_add_nc_u32_e32 v29, s2, v11
v_add_nc_u32_e32 v31, s2, v10
v_add_nc_u32_e32 v33, s2, v18
v_add_nc_u32_e32 v35, s2, v17
v_add_nc_u32_e32 v37, s2, v15
v_add_nc_u32_e32 v39, s2, v16
s_add_i32 s2, s2, 1
v_ashrrev_i32_e32 v22, 31, v21
v_dual_mov_b32 v3, v1 :: v_dual_add_nc_u32 v42, s2, v6
v_ashrrev_i32_e32 v24, 31, v23
v_ashrrev_i32_e32 v26, 31, v25
s_delay_alu instid0(VALU_DEP_4)
v_lshlrev_b64 v[21:22], 3, v[21:22]
v_ashrrev_i32_e32 v28, 31, v27
v_cmp_ge_i32_e32 vcc_lo, v42, v7
v_lshlrev_b64 v[23:24], 3, v[23:24]
v_lshlrev_b64 v[25:26], 3, v[25:26]
v_ashrrev_i32_e32 v30, 31, v29
v_lshlrev_b64 v[27:28], 3, v[27:28]
s_or_b32 s9, vcc_lo, s9
v_add_co_u32 v21, vcc_lo, s4, v21
v_add_co_ci_u32_e32 v22, vcc_lo, s5, v22, vcc_lo
v_add_co_u32 v23, vcc_lo, s4, v23
v_ashrrev_i32_e32 v32, 31, v31
v_add_co_ci_u32_e32 v24, vcc_lo, s5, v24, vcc_lo
v_lshlrev_b64 v[29:30], 3, v[29:30]
v_add_co_u32 v25, vcc_lo, s10, v25
v_add_nc_u32_e32 v41, 0x5a, v34
v_add_nc_u32_e32 v43, 0x5b, v34
v_add_nc_u32_e32 v45, 0x5d, v34
v_ashrrev_i32_e32 v34, 31, v33
v_add_co_ci_u32_e32 v26, vcc_lo, s11, v26, vcc_lo
v_lshlrev_b64 v[31:32], 3, v[31:32]
v_add_co_u32 v27, vcc_lo, s4, v27
v_ashrrev_i32_e32 v36, 31, v35
v_add_co_ci_u32_e32 v28, vcc_lo, s5, v28, vcc_lo
v_lshlrev_b64 v[33:34], 3, v[33:34]
v_add_co_u32 v29, vcc_lo, s4, v29
v_ashrrev_i32_e32 v38, 31, v37
v_add_co_ci_u32_e32 v30, vcc_lo, s5, v30, vcc_lo
v_lshlrev_b64 v[35:36], 3, v[35:36]
v_add_co_u32 v31, vcc_lo, s12, v31
v_ashrrev_i32_e32 v40, 31, v39
v_add_co_ci_u32_e32 v32, vcc_lo, s13, v32, vcc_lo
v_lshlrev_b64 v[37:38], 3, v[37:38]
v_add_co_u32 v33, vcc_lo, s4, v33
v_ashrrev_i32_e32 v42, 31, v41
v_add_co_ci_u32_e32 v34, vcc_lo, s5, v34, vcc_lo
v_lshlrev_b64 v[39:40], 3, v[39:40]
v_add_co_u32 v35, vcc_lo, s12, v35
v_ashrrev_i32_e32 v44, 31, v43
v_add_co_ci_u32_e32 v36, vcc_lo, s13, v36, vcc_lo
v_lshlrev_b64 v[41:42], 3, v[41:42]
v_add_co_u32 v37, vcc_lo, s4, v37
v_ashrrev_i32_e32 v46, 31, v45
v_add_co_ci_u32_e32 v38, vcc_lo, s5, v38, vcc_lo
v_lshlrev_b64 v[43:44], 3, v[43:44]
v_add_co_u32 v39, vcc_lo, s10, v39
v_add_co_ci_u32_e32 v40, vcc_lo, s11, v40, vcc_lo
v_lshlrev_b64 v[45:46], 3, v[45:46]
v_add_co_u32 v41, vcc_lo, s4, v41
v_add_co_ci_u32_e32 v42, vcc_lo, s5, v42, vcc_lo
v_add_co_u32 v43, vcc_lo, s4, v43
v_add_co_ci_u32_e32 v44, vcc_lo, s5, v44, vcc_lo
v_add_co_u32 v47, vcc_lo, s4, v45
v_add_co_ci_u32_e32 v48, vcc_lo, s5, v46, vcc_lo
v_add_co_u32 v45, vcc_lo, s6, v45
v_add_co_ci_u32_e32 v46, vcc_lo, s7, v46, vcc_lo
s_clause 0xe
global_store_b64 v[43:44], v[19:20], off
global_store_b64 v[41:42], v[19:20], off
global_store_b64 v[41:42], v[19:20], off offset:16
global_store_b64 v[21:22], v[19:20], off
global_store_b64 v[23:24], v[19:20], off
global_store_b64 v[25:26], v[19:20], off
global_store_b64 v[27:28], v[19:20], off
global_store_b64 v[29:30], v[19:20], off
global_store_b64 v[31:32], v[19:20], off
global_store_b64 v[47:48], v[19:20], off
global_store_b64 v[33:34], v[19:20], off
global_store_b64 v[35:36], v[19:20], off
global_store_b64 v[37:38], v[19:20], off
global_store_b64 v[39:40], v[19:20], off
global_store_b128 v[41:42], v[0:3], off offset:32
global_store_b64 v[45:46], v[4:5], off
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB1_2
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10initializePdS_diiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 49
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10initializePdS_diiii, .Lfunc_end1-_Z10initializePdS_diiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13upstream_5_3dPPdS_S_diiii
.private_segment_fixed_size: 0
.sgpr_count: 24
.sgpr_spill_count: 0
.symbol: _Z13upstream_5_3dPPdS_S_diiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 49
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10initializePdS_diiii
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z10initializePdS_diiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 49
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#define t_max 1
#define t 1
/*
(u[0][0][0][1][0]=(a*((((u[-3][0][0][0][0]+(u[0][-3][0][0][0]+u[0][0][-3][0][0]))*-2.0)+(((u[-2][0][0][0][0]+(u[0][-2][0][0][0]+u[0][0][-2][0][0]))*15.0)+((u[-1][0][0][0][0]+(u[0][-1][0][0][0]+u[0][0][-1][0][0]))*-60.0)))+((u[0][0][0][0][0]*20.0)+(((u[1][0][0][0][0]+(u[0][1][0][0][0]+u[0][0][1][0][0]))*30.0)+((u[2][0][0][0][0]+(u[0][2][0][0][0]+u[0][0][2][0][0]))*-3.0))))))
*/
__global__ void upstream_5_3d(double * * u_0_1_out, double * u_0_0, double * u_0_1, double a, int x_max, int y_max, int z_max, int cbx)
{
// double * const u__u_0[16] = { u_0_0, u_0_1 } ;
int _idx0;
int _idx1;
int _idx10;
int _idx11;
int _idx12;
int _idx13;
int _idx14;
int _idx15;
int _idx2;
int _idx3;
int _idx4;
int _idx5;
int _idx6;
int _idx7;
int _idx8;
int _idx9;
int idx_1_2;
int pt_idx_x;
int pt_idx_y;
int pt_idx_z;
int size_1_1;
int size_1_2;
// int t;
int tmp;
int v_idx_x;
int v_idx_x_max;
int v_idx_y;
int v_idx_y_max;
int v_idx_z;
int v_idx_z_max;
/*
Initializations
*/
size_1_1=(y_max/blockDim.y);
size_1_2=(z_max/blockDim.z);
idx_1_2=(blockIdx.y/size_1_2);
tmp=(blockIdx.y-(idx_1_2*size_1_2));
v_idx_x=(cbx*(threadIdx.x+(blockDim.x*blockIdx.x)));
v_idx_x_max=(v_idx_x+cbx);
v_idx_y=(threadIdx.y+(tmp*blockDim.y));
v_idx_y_max=(v_idx_y+1);
v_idx_z=(threadIdx.z+(idx_1_2*blockDim.z));
v_idx_z_max=(v_idx_z+1);
/*
Implementation
*/
/*
for t = 1..t_max by 1 parallel 1 <level 0> schedule { ... }
*/
// for (t=1; t<=t_max; t+=1)
{
/* Index bounds calculations for iterators in v[t=t, s=(cbx, 1, 1)][0] */
/*
for POINT pt[t=t, s=(1, 1, 1)][0] of size [1, 1, 1] in v[t=t, s=(:, :, :)][0] parallel 1 <level 1> schedule default { ... }
*/
{
/* Index bounds calculations for iterators in pt[t=t, s=(1, 1, 1)][0] */
pt_idx_z=v_idx_z;
pt_idx_y=v_idx_y;
for (pt_idx_x=v_idx_x; pt_idx_x<(v_idx_x_max-0); pt_idx_x+=1)
{
/* Index bounds calculations for iterators in pt[t=t, s=(1, 1, 1)][0] */
/*
v[t=(t+1), s=pt[t=?, s=?][0]][0]=stencil(v[t=t, s=pt[t=?, s=?][0]][0])
*/
/* _idx0 = ((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x) */
_idx0=((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x);
/* _idx1 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+(((((5*pt_idx_z)+15)*t)+pt_idx_y)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+((5*pt_idx_y)*t))+pt_idx_x)+3) */
_idx1=(((_idx0-(3*x_max))-(15*t))+3);
/* _idx2 = ((((((((pt_idx_z*x_max)+((5*pt_idx_z)*t))*y_max)+(((((5*pt_idx_z)*t)+pt_idx_y)+3)*x_max))+((25*pt_idx_z)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx2=((((_idx1+(((-3*x_max)-(15*t))*y_max))+((3-(15*t))*x_max))-(75*(t*t)))+(15*t));
/* _idx3 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+1) */
_idx3=(_idx0+1);
/* _idx4 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+1)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+5)*t))+pt_idx_x)+3) */
_idx4=((_idx1+x_max)+(5*t));
/* _idx5 = (((((((((pt_idx_z+1)*x_max)+(((5*pt_idx_z)+5)*t))*y_max)+((((((5*pt_idx_z)+5)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+25)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx5=(((_idx2+((x_max+(5*t))*y_max))+((5*t)*x_max))+(25*(t*t)));
/* _idx6 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+2) */
_idx6=(_idx0+2);
/* _idx7 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+2)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+10)*t))+pt_idx_x)+3) */
_idx7=((_idx4+x_max)+(5*t));
/* _idx8 = (((((((((pt_idx_z+2)*x_max)+(((5*pt_idx_z)+10)*t))*y_max)+((((((5*pt_idx_z)+10)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+50)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx8=(((_idx5+((x_max+(5*t))*y_max))+((5*t)*x_max))+(25*(t*t)));
/* _idx9 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx9=(_idx0+3);
/* _idx10 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+4) */
_idx10=(_idx0+4);
/* _idx11 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+4)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+20)*t))+pt_idx_x)+3) */
_idx11=((_idx9+x_max)+(5*t));
/* _idx12 = (((((((((pt_idx_z+4)*x_max)+(((5*pt_idx_z)+20)*t))*y_max)+((((((5*pt_idx_z)+20)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+100)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx12=(((_idx9+((x_max+(5*t))*y_max))+((5*t)*x_max))+(25*(t*t)));
/* _idx13 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+5) */
_idx13=(_idx0+5);
/* _idx14 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+5)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+25)*t))+pt_idx_x)+3) */
_idx14=((_idx11+x_max)+(5*t));
/* _idx15 = (((((((((pt_idx_z+5)*x_max)+(((5*pt_idx_z)+25)*t))*y_max)+((((((5*pt_idx_z)+25)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+125)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx15=(((_idx12+((x_max+(5*t))*y_max))+((5*t)*x_max))+(25*(t*t)));
u_0_1[_idx9]=(a*((((u_0_0[_idx0]+(u_0_0[_idx1]+u_0_0[_idx2]))*-2.0)+(((u_0_0[_idx3]+(u_0_0[_idx4]+u_0_0[_idx5]))*15.0)+((u_0_0[_idx6]+(u_0_0[_idx7]+u_0_0[_idx8]))*-60.0)))+((u_0_0[_idx9]*20.0)+(((u_0_0[_idx10]+(u_0_0[_idx11]+u_0_0[_idx12]))*30.0)+((u_0_0[_idx13]+(u_0_0[_idx14]+u_0_0[_idx15]))*-3.0)))));
}
}
}
}
__global__ void initialize(double * u_0_0, double * u_0_1, double a, int x_max, int y_max, int z_max, int cbx)
{
double * const u__u_0[16] = { u_0_0, u_0_1 } ;
int _idx0;
int _idx1;
int _idx10;
int _idx11;
int _idx12;
int _idx13;
int _idx14;
int _idx15;
int _idx2;
int _idx3;
int _idx4;
int _idx5;
int _idx6;
int _idx7;
int _idx8;
int _idx9;
int idx_1_2;
int pt_idx_x;
int pt_idx_y;
int pt_idx_z;
int size_1_1;
int size_1_2;
//int t;
int tmp;
int v_idx_x;
int v_idx_x_max;
int v_idx_y;
int v_idx_y_max;
int v_idx_z;
int v_idx_z_max;
/*
Initializations
*/
size_1_1=(y_max/blockDim.y);
size_1_2=(z_max/blockDim.z);
idx_1_2=(blockIdx.y/size_1_2);
tmp=(blockIdx.y-(idx_1_2*size_1_2));
v_idx_x=(cbx*(threadIdx.x+(blockDim.x*blockIdx.x)));
v_idx_x_max=(v_idx_x+cbx);
v_idx_y=(threadIdx.y+(tmp*blockDim.y));
v_idx_y_max=(v_idx_y+1);
v_idx_z=(threadIdx.z+(idx_1_2*blockDim.z));
v_idx_z_max=(v_idx_z+1);
/*
Implementation
*/
/*
for t = 1..t_max by 1 parallel 1 <level 0> schedule { ... }
*/
//for (t=1; t<=t_max; t+=1)
{
/* Index bounds calculations for iterators in v[t=t, s=(cbx, 1, 1)][0] */
/*
for POINT pt[t=t, s=(1, 1, 1)][0] of size [1, 1, 1] in v[t=t, s=(:, :, :)][0] parallel 1 <level 1> schedule default { ... }
*/
{
/* Index bounds calculations for iterators in pt[t=t, s=(1, 1, 1)][0] */
pt_idx_z=v_idx_z;
pt_idx_y=v_idx_y;
for (pt_idx_x=v_idx_x; pt_idx_x<(v_idx_x_max-0); pt_idx_x+=1)
{
/* Index bounds calculations for iterators in pt[t=t, s=(1, 1, 1)][0] */
/*
v[t=(t+1), s=pt[t=?, s=?][0]][0]=stencil(v[t=t, s=pt[t=?, s=?][0]][0])
*/
/* _idx0 = ((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x) */
_idx0=((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x);
u_0_0[_idx0]=0.1;
/* _idx1 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+1) */
_idx1=(_idx0+1);
u_0_0[_idx1]=0.1;
/* _idx2 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+2) */
_idx2=(_idx0+2);
u_0_0[_idx2]=0.1;
/* _idx3 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+(((((5*pt_idx_z)+15)*t)+pt_idx_y)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+((5*pt_idx_y)*t))+pt_idx_x)+3) */
_idx3=(((_idx0-(3*x_max))-(15*t))+3);
u_0_0[_idx3]=0.1;
/* _idx4 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+1)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+5)*t))+pt_idx_x)+3) */
_idx4=((_idx3+x_max)+(5*t));
u_0_0[_idx4]=0.1;
/* _idx5 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+2)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+10)*t))+pt_idx_x)+3) */
_idx5=((_idx4+x_max)+(5*t));
u_0_0[_idx5]=0.1;
/* _idx6 = ((((((((pt_idx_z*x_max)+((5*pt_idx_z)*t))*y_max)+(((((5*pt_idx_z)*t)+pt_idx_y)+3)*x_max))+((25*pt_idx_z)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx6=((((_idx1+(((-3*x_max)-(15*t))*y_max))-((15*t)*x_max))-(75*(t*t)))+2);
u_0_0[_idx6]=0.1;
/* _idx7 = (((((((((pt_idx_z+1)*x_max)+(((5*pt_idx_z)+5)*t))*y_max)+((((((5*pt_idx_z)+5)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+25)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx7=(((_idx6+((x_max+(5*t))*y_max))+((5*t)*x_max))+(25*(t*t)));
u_0_0[_idx7]=0.1;
/* _idx8 = (((((((((pt_idx_z+2)*x_max)+(((5*pt_idx_z)+10)*t))*y_max)+((((((5*pt_idx_z)+10)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+50)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx8=(((_idx7+((x_max+(5*t))*y_max))+((5*t)*x_max))+(25*(t*t)));
u_0_0[_idx8]=0.1;
/* _idx9 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx9=(_idx0+3);
u_0_0[_idx9]=0.1;
/* _idx10 = (((((((((pt_idx_z+4)*x_max)+(((5*pt_idx_z)+20)*t))*y_max)+((((((5*pt_idx_z)+20)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+100)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx10=(((_idx9+((x_max+(5*t))*y_max))+((5*t)*x_max))+(25*(t*t)));
u_0_0[_idx10]=0.1;
/* _idx11 = (((((((((pt_idx_z+5)*x_max)+(((5*pt_idx_z)+25)*t))*y_max)+((((((5*pt_idx_z)+25)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+125)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+3) */
_idx11=(((_idx10+((x_max+(5*t))*y_max))+((5*t)*x_max))+(25*(t*t)));
u_0_0[_idx11]=0.1;
/* _idx12 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+4)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+20)*t))+pt_idx_x)+3) */
_idx12=((_idx9+x_max)+(5*t));
u_0_0[_idx12]=0.1;
/* _idx13 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+5)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+25)*t))+pt_idx_x)+3) */
_idx13=((_idx12+x_max)+(5*t));
u_0_0[_idx13]=0.1;
/* _idx14 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+4) */
_idx14=(_idx0+4);
u_0_0[_idx14]=0.1;
/* _idx15 = (((((((((pt_idx_z+3)*x_max)+(((5*pt_idx_z)+15)*t))*y_max)+((((((5*pt_idx_z)+15)*t)+pt_idx_y)+3)*x_max))+(((25*pt_idx_z)+75)*(t*t)))+(((5*pt_idx_y)+15)*t))+pt_idx_x)+5) */
_idx15=(_idx0+5);
u_0_0[_idx15]=0.1;
u_0_1[_idx9]=1.1;
}
}
}
} | .text
.file "kernel.hip"
.globl _Z28__device_stub__upstream_5_3dPPdS_S_diiii # -- Begin function _Z28__device_stub__upstream_5_3dPPdS_S_diiii
.p2align 4, 0x90
.type _Z28__device_stub__upstream_5_3dPPdS_S_diiii,@function
_Z28__device_stub__upstream_5_3dPPdS_S_diiii: # @_Z28__device_stub__upstream_5_3dPPdS_S_diiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movsd %xmm0, 64(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
leaq 176(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13upstream_5_3dPPdS_S_diiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z28__device_stub__upstream_5_3dPPdS_S_diiii, .Lfunc_end0-_Z28__device_stub__upstream_5_3dPPdS_S_diiii
.cfi_endproc
# -- End function
.globl _Z25__device_stub__initializePdS_diiii # -- Begin function _Z25__device_stub__initializePdS_diiii
.p2align 4, 0x90
.type _Z25__device_stub__initializePdS_diiii,@function
_Z25__device_stub__initializePdS_diiii: # @_Z25__device_stub__initializePdS_diiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movsd %xmm0, 72(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10initializePdS_diiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z25__device_stub__initializePdS_diiii, .Lfunc_end1-_Z25__device_stub__initializePdS_diiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13upstream_5_3dPPdS_S_diiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10initializePdS_diiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13upstream_5_3dPPdS_S_diiii,@object # @_Z13upstream_5_3dPPdS_S_diiii
.section .rodata,"a",@progbits
.globl _Z13upstream_5_3dPPdS_S_diiii
.p2align 3, 0x0
_Z13upstream_5_3dPPdS_S_diiii:
.quad _Z28__device_stub__upstream_5_3dPPdS_S_diiii
.size _Z13upstream_5_3dPPdS_S_diiii, 8
.type _Z10initializePdS_diiii,@object # @_Z10initializePdS_diiii
.globl _Z10initializePdS_diiii
.p2align 3, 0x0
_Z10initializePdS_diiii:
.quad _Z25__device_stub__initializePdS_diiii
.size _Z10initializePdS_diiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13upstream_5_3dPPdS_S_diiii"
.size .L__unnamed_1, 30
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10initializePdS_diiii"
.size .L__unnamed_2, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__upstream_5_3dPPdS_S_diiii
.addrsig_sym _Z25__device_stub__initializePdS_diiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13upstream_5_3dPPdS_S_diiii
.addrsig_sym _Z10initializePdS_diiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f5e8e_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z13upstream_5_3dPPdS_S_diiiiPPdS_S_diiii
.type _Z43__device_stub__Z13upstream_5_3dPPdS_S_diiiiPPdS_S_diiii, @function
_Z43__device_stub__Z13upstream_5_3dPPdS_S_diiiiPPdS_S_diiii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movsd %xmm0, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 4(%rsp), %rax
movq %rax, 160(%rsp)
leaq 208(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13upstream_5_3dPPdS_S_diiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z13upstream_5_3dPPdS_S_diiiiPPdS_S_diiii, .-_Z43__device_stub__Z13upstream_5_3dPPdS_S_diiiiPPdS_S_diiii
.globl _Z13upstream_5_3dPPdS_S_diiii
.type _Z13upstream_5_3dPPdS_S_diiii, @function
_Z13upstream_5_3dPPdS_S_diiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z43__device_stub__Z13upstream_5_3dPPdS_S_diiiiPPdS_S_diiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13upstream_5_3dPPdS_S_diiii, .-_Z13upstream_5_3dPPdS_S_diiii
.globl _Z37__device_stub__Z10initializePdS_diiiiPdS_diiii
.type _Z37__device_stub__Z10initializePdS_diiiiPdS_diiii, @function
_Z37__device_stub__Z10initializePdS_diiiiPdS_diiii:
.LFB2053:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movsd %xmm0, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10initializePdS_diiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z37__device_stub__Z10initializePdS_diiiiPdS_diiii, .-_Z37__device_stub__Z10initializePdS_diiiiPdS_diiii
.globl _Z10initializePdS_diiii
.type _Z10initializePdS_diiii, @function
_Z10initializePdS_diiii:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z10initializePdS_diiiiPdS_diiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z10initializePdS_diiii, .-_Z10initializePdS_diiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10initializePdS_diiii"
.LC1:
.string "_Z13upstream_5_3dPPdS_S_diiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10initializePdS_diiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z13upstream_5_3dPPdS_S_diiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z28__device_stub__upstream_5_3dPPdS_S_diiii # -- Begin function _Z28__device_stub__upstream_5_3dPPdS_S_diiii
.p2align 4, 0x90
.type _Z28__device_stub__upstream_5_3dPPdS_S_diiii,@function
_Z28__device_stub__upstream_5_3dPPdS_S_diiii: # @_Z28__device_stub__upstream_5_3dPPdS_S_diiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movsd %xmm0, 64(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
leaq 176(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13upstream_5_3dPPdS_S_diiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z28__device_stub__upstream_5_3dPPdS_S_diiii, .Lfunc_end0-_Z28__device_stub__upstream_5_3dPPdS_S_diiii
.cfi_endproc
# -- End function
.globl _Z25__device_stub__initializePdS_diiii # -- Begin function _Z25__device_stub__initializePdS_diiii
.p2align 4, 0x90
.type _Z25__device_stub__initializePdS_diiii,@function
_Z25__device_stub__initializePdS_diiii: # @_Z25__device_stub__initializePdS_diiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movsd %xmm0, 72(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10initializePdS_diiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z25__device_stub__initializePdS_diiii, .Lfunc_end1-_Z25__device_stub__initializePdS_diiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13upstream_5_3dPPdS_S_diiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10initializePdS_diiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13upstream_5_3dPPdS_S_diiii,@object # @_Z13upstream_5_3dPPdS_S_diiii
.section .rodata,"a",@progbits
.globl _Z13upstream_5_3dPPdS_S_diiii
.p2align 3, 0x0
_Z13upstream_5_3dPPdS_S_diiii:
.quad _Z28__device_stub__upstream_5_3dPPdS_S_diiii
.size _Z13upstream_5_3dPPdS_S_diiii, 8
.type _Z10initializePdS_diiii,@object # @_Z10initializePdS_diiii
.globl _Z10initializePdS_diiii
.p2align 3, 0x0
_Z10initializePdS_diiii:
.quad _Z25__device_stub__initializePdS_diiii
.size _Z10initializePdS_diiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13upstream_5_3dPPdS_S_diiii"
.size .L__unnamed_1, 30
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10initializePdS_diiii"
.size .L__unnamed_2, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__upstream_5_3dPPdS_S_diiii
.addrsig_sym _Z25__device_stub__initializePdS_diiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13upstream_5_3dPPdS_S_diiii
.addrsig_sym _Z10initializePdS_diiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "job.cuh"
#include "common.cuh"
int calc_jobs(int real_job_num)
{
return (real_job_num / THREADS_PER_BLOCK) * THREADS_PER_BLOCK + ((real_job_num % THREADS_PER_BLOCK) ? THREADS_PER_BLOCK : 0);
}
job_t allocate_host_job(job_t job)
{
job_t host_job = job;
int jobs_num = calc_jobs(host_job.image_width * host_job.image_height);
safeMalloc((void **) &host_job.gather_arr, sizeof(int) * jobs_num);
safeMalloc((void **)&host_job.target_idx, sizeof(int) * jobs_num);
safeMalloc((void **)&host_job.image_dest, sizeof(float) * jobs_num * 3);
safeMalloc((void **)&host_job.ray_pos, sizeof(float) * jobs_num * 3);
safeMalloc((void **)&host_job.ray_dir, sizeof(float) * jobs_num * 3);
return host_job;
}
void free_host_job(job_t *host_job)
{
safeFree(host_job->gather_arr);
host_job->gather_arr = NULL;
safeFree(host_job->target_idx);
host_job->target_idx = NULL;
safeFree(host_job->image_dest);
host_job->image_dest = NULL;
safeFree(host_job->ray_pos);
host_job->ray_pos = NULL;
safeFree(host_job->ray_dir);
host_job->ray_dir = NULL;
}
job_t allocate_device_job(job_t job)
{
job_t dev_job = job;
int jobs_num = calc_jobs(dev_job.image_width * dev_job.image_height);
cudaSafeMalloc((void **)&dev_job.gather_arr, sizeof(int) * jobs_num);
cudaSafeMalloc((void **)&dev_job.target_idx, sizeof(int) * jobs_num);
cudaSafeMalloc((void **)&dev_job.image_dest, sizeof(float) * jobs_num * 3);
cudaSafeMalloc((void **)&dev_job.ray_pos, sizeof(float) * jobs_num * 3);
cudaSafeMalloc((void **)&dev_job.ray_dir, sizeof(float) * jobs_num * 3);
return dev_job;
}
void free_device_job(job_t *dev_job)
{
cudaSafeFree(dev_job->gather_arr);
dev_job->gather_arr = NULL;
cudaSafeFree(dev_job->target_idx);
dev_job->target_idx = NULL;
cudaSafeFree(dev_job->image_dest);
dev_job->image_dest = NULL;
cudaSafeFree(dev_job->ray_pos);
dev_job->ray_pos = NULL;
cudaSafeFree(dev_job->ray_dir);
dev_job->ray_dir = NULL;
}
void copy_job_to_dev(job_t *dev_dest, job_t *host_src)
{
dev_dest->image_width = host_src->image_width;
dev_dest->image_height = host_src->image_height;
dev_dest->pass_count = host_src->pass_count;
int hc = calc_jobs(host_src->image_width * host_src->image_height);
cudaMemcpy(dev_dest->gather_arr, host_src->gather_arr, hc * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_dest->target_idx, host_src->target_idx, hc * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_dest->image_dest, host_src->image_dest, hc * sizeof(float) * 3, cudaMemcpyHostToDevice);
cudaMemcpy(dev_dest->ray_pos, host_src->ray_pos, hc * sizeof(float) * 3, cudaMemcpyHostToDevice);
cudaMemcpy(dev_dest->ray_dir, host_src->ray_dir, hc * sizeof(float) * 3, cudaMemcpyHostToDevice);
}
void copy_job_to_host(job_t *host_dest, job_t *dev_src)
{
host_dest->image_width = dev_src->image_width;
host_dest->image_height = dev_src->image_height;
host_dest->pass_count = dev_src->pass_count;
int hc = calc_jobs(dev_src->image_width * dev_src->image_height);
cudaMemcpy(host_dest->gather_arr, dev_src->gather_arr, hc * sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy(host_dest->target_idx, dev_src->target_idx, hc * sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy(host_dest->image_dest, dev_src->image_dest, hc * sizeof(float) * 3, cudaMemcpyDeviceToHost);
cudaMemcpy(host_dest->ray_pos, dev_src->ray_pos, hc * sizeof(float) * 3, cudaMemcpyDeviceToHost);
cudaMemcpy(host_dest->ray_dir, dev_src->ray_dir, hc * sizeof(float) * 3, cudaMemcpyDeviceToHost);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "job.cuh"
#include "common.cuh"
int calc_jobs(int real_job_num)
{
return (real_job_num / THREADS_PER_BLOCK) * THREADS_PER_BLOCK + ((real_job_num % THREADS_PER_BLOCK) ? THREADS_PER_BLOCK : 0);
}
job_t allocate_host_job(job_t job)
{
job_t host_job = job;
int jobs_num = calc_jobs(host_job.image_width * host_job.image_height);
safeMalloc((void **) &host_job.gather_arr, sizeof(int) * jobs_num);
safeMalloc((void **)&host_job.target_idx, sizeof(int) * jobs_num);
safeMalloc((void **)&host_job.image_dest, sizeof(float) * jobs_num * 3);
safeMalloc((void **)&host_job.ray_pos, sizeof(float) * jobs_num * 3);
safeMalloc((void **)&host_job.ray_dir, sizeof(float) * jobs_num * 3);
return host_job;
}
void free_host_job(job_t *host_job)
{
safeFree(host_job->gather_arr);
host_job->gather_arr = NULL;
safeFree(host_job->target_idx);
host_job->target_idx = NULL;
safeFree(host_job->image_dest);
host_job->image_dest = NULL;
safeFree(host_job->ray_pos);
host_job->ray_pos = NULL;
safeFree(host_job->ray_dir);
host_job->ray_dir = NULL;
}
job_t allocate_device_job(job_t job)
{
job_t dev_job = job;
int jobs_num = calc_jobs(dev_job.image_width * dev_job.image_height);
cudaSafeMalloc((void **)&dev_job.gather_arr, sizeof(int) * jobs_num);
cudaSafeMalloc((void **)&dev_job.target_idx, sizeof(int) * jobs_num);
cudaSafeMalloc((void **)&dev_job.image_dest, sizeof(float) * jobs_num * 3);
cudaSafeMalloc((void **)&dev_job.ray_pos, sizeof(float) * jobs_num * 3);
cudaSafeMalloc((void **)&dev_job.ray_dir, sizeof(float) * jobs_num * 3);
return dev_job;
}
void free_device_job(job_t *dev_job)
{
cudaSafeFree(dev_job->gather_arr);
dev_job->gather_arr = NULL;
cudaSafeFree(dev_job->target_idx);
dev_job->target_idx = NULL;
cudaSafeFree(dev_job->image_dest);
dev_job->image_dest = NULL;
cudaSafeFree(dev_job->ray_pos);
dev_job->ray_pos = NULL;
cudaSafeFree(dev_job->ray_dir);
dev_job->ray_dir = NULL;
}
void copy_job_to_dev(job_t *dev_dest, job_t *host_src)
{
dev_dest->image_width = host_src->image_width;
dev_dest->image_height = host_src->image_height;
dev_dest->pass_count = host_src->pass_count;
int hc = calc_jobs(host_src->image_width * host_src->image_height);
cudaMemcpy(dev_dest->gather_arr, host_src->gather_arr, hc * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_dest->target_idx, host_src->target_idx, hc * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_dest->image_dest, host_src->image_dest, hc * sizeof(float) * 3, cudaMemcpyHostToDevice);
cudaMemcpy(dev_dest->ray_pos, host_src->ray_pos, hc * sizeof(float) * 3, cudaMemcpyHostToDevice);
cudaMemcpy(dev_dest->ray_dir, host_src->ray_dir, hc * sizeof(float) * 3, cudaMemcpyHostToDevice);
}
void copy_job_to_host(job_t *host_dest, job_t *dev_src)
{
host_dest->image_width = dev_src->image_width;
host_dest->image_height = dev_src->image_height;
host_dest->pass_count = dev_src->pass_count;
int hc = calc_jobs(dev_src->image_width * dev_src->image_height);
cudaMemcpy(host_dest->gather_arr, dev_src->gather_arr, hc * sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy(host_dest->target_idx, dev_src->target_idx, hc * sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy(host_dest->image_dest, dev_src->image_dest, hc * sizeof(float) * 3, cudaMemcpyDeviceToHost);
cudaMemcpy(host_dest->ray_pos, dev_src->ray_pos, hc * sizeof(float) * 3, cudaMemcpyDeviceToHost);
cudaMemcpy(host_dest->ray_dir, dev_src->ray_dir, hc * sizeof(float) * 3, cudaMemcpyDeviceToHost);
} | .file "tmpxft_000ade49_00000000-6_job.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3782:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3782:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9calc_jobsi
.type _Z9calc_jobsi, @function
_Z9calc_jobsi:
.LFB3773:
.cfi_startproc
endbr64
testb $63, %dil
setne %al
movzbl %al, %eax
sall $6, %eax
leal 63(%rdi), %edx
testl %edi, %edi
cmovns %edi, %edx
andl $-64, %edx
addl %edx, %eax
ret
.cfi_endproc
.LFE3773:
.size _Z9calc_jobsi, .-_Z9calc_jobsi
.globl _Z17allocate_host_job5job_t
.type _Z17allocate_host_job5job_t, @function
_Z17allocate_host_job5job_t:
.LFB3774:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbx
movq 32(%rsp), %rax
movl %eax, %edi
movq %rax, (%rbx)
movq 40(%rsp), %rax
movq %rax, 8(%rbx)
movdqu 48(%rsp), %xmm0
movups %xmm0, 16(%rbx)
movdqu 64(%rsp), %xmm1
movups %xmm1, 32(%rbx)
movq 80(%rsp), %rax
movq %rax, 48(%rbx)
imull 4(%rbx), %edi
call _Z9calc_jobsi
movslq %eax, %rbp
leaq 0(,%rbp,4), %r12
leaq 16(%rbx), %rdi
movq %r12, %rsi
call _Z10safeMallocPPvm@PLT
leaq 48(%rbx), %rdi
movq %r12, %rsi
call _Z10safeMallocPPvm@PLT
leaq 0(%rbp,%rbp,2), %rbp
salq $2, %rbp
leaq 24(%rbx), %rdi
movq %rbp, %rsi
call _Z10safeMallocPPvm@PLT
leaq 32(%rbx), %rdi
movq %rbp, %rsi
call _Z10safeMallocPPvm@PLT
leaq 40(%rbx), %rdi
movq %rbp, %rsi
call _Z10safeMallocPPvm@PLT
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3774:
.size _Z17allocate_host_job5job_t, .-_Z17allocate_host_job5job_t
.globl _Z13free_host_jobP5job_t
.type _Z13free_host_jobP5job_t, @function
_Z13free_host_jobP5job_t:
.LFB3775:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq 16(%rdi), %rdi
call _Z8safeFreePv@PLT
movq $0, 16(%rbx)
movq 48(%rbx), %rdi
call _Z8safeFreePv@PLT
movq $0, 48(%rbx)
movq 24(%rbx), %rdi
call _Z8safeFreePv@PLT
movq $0, 24(%rbx)
movq 32(%rbx), %rdi
call _Z8safeFreePv@PLT
movq $0, 32(%rbx)
movq 40(%rbx), %rdi
call _Z8safeFreePv@PLT
movq $0, 40(%rbx)
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3775:
.size _Z13free_host_jobP5job_t, .-_Z13free_host_jobP5job_t
.globl _Z19allocate_device_job5job_t
.type _Z19allocate_device_job5job_t, @function
_Z19allocate_device_job5job_t:
.LFB3776:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbx
movq 32(%rsp), %rax
movl %eax, %edi
movq %rax, (%rbx)
movq 40(%rsp), %rax
movq %rax, 8(%rbx)
movdqu 48(%rsp), %xmm0
movups %xmm0, 16(%rbx)
movdqu 64(%rsp), %xmm1
movups %xmm1, 32(%rbx)
movq 80(%rsp), %rax
movq %rax, 48(%rbx)
imull 4(%rbx), %edi
call _Z9calc_jobsi
movslq %eax, %rbp
leaq 0(,%rbp,4), %r12
leaq 16(%rbx), %rdi
movq %r12, %rsi
call _Z14cudaSafeMallocPPvm@PLT
leaq 48(%rbx), %rdi
movq %r12, %rsi
call _Z14cudaSafeMallocPPvm@PLT
leaq 0(%rbp,%rbp,2), %rbp
salq $2, %rbp
leaq 24(%rbx), %rdi
movq %rbp, %rsi
call _Z14cudaSafeMallocPPvm@PLT
leaq 32(%rbx), %rdi
movq %rbp, %rsi
call _Z14cudaSafeMallocPPvm@PLT
leaq 40(%rbx), %rdi
movq %rbp, %rsi
call _Z14cudaSafeMallocPPvm@PLT
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3776:
.size _Z19allocate_device_job5job_t, .-_Z19allocate_device_job5job_t
.globl _Z15free_device_jobP5job_t
.type _Z15free_device_jobP5job_t, @function
_Z15free_device_jobP5job_t:
.LFB3777:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq 16(%rdi), %rdi
call _Z12cudaSafeFreePv@PLT
movq $0, 16(%rbx)
movq 48(%rbx), %rdi
call _Z12cudaSafeFreePv@PLT
movq $0, 48(%rbx)
movq 24(%rbx), %rdi
call _Z12cudaSafeFreePv@PLT
movq $0, 24(%rbx)
movq 32(%rbx), %rdi
call _Z12cudaSafeFreePv@PLT
movq $0, 32(%rbx)
movq 40(%rbx), %rdi
call _Z12cudaSafeFreePv@PLT
movq $0, 40(%rbx)
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3777:
.size _Z15free_device_jobP5job_t, .-_Z15free_device_jobP5job_t
.globl _Z15copy_job_to_devP5job_tS0_
.type _Z15copy_job_to_devP5job_tS0_, @function
_Z15copy_job_to_devP5job_tS0_:
.LFB3778:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
movq %rsi, %rbx
movl (%rsi), %eax
movl %eax, (%rdi)
movl 4(%rsi), %eax
movl %eax, 4(%rdi)
movl 8(%rsi), %eax
movl %eax, 8(%rdi)
movl (%rsi), %edi
imull 4(%rsi), %edi
call _Z9calc_jobsi
movslq %eax, %r12
leaq 0(,%r12,4), %r13
movq 16(%rbx), %rsi
movq 16(%rbp), %rdi
movl $1, %ecx
movq %r13, %rdx
call cudaMemcpy@PLT
movq 48(%rbx), %rsi
movq 48(%rbp), %rdi
movl $1, %ecx
movq %r13, %rdx
call cudaMemcpy@PLT
leaq (%r12,%r12,2), %r12
salq $2, %r12
movq 24(%rbx), %rsi
movq 24(%rbp), %rdi
movl $1, %ecx
movq %r12, %rdx
call cudaMemcpy@PLT
movq 32(%rbx), %rsi
movq 32(%rbp), %rdi
movl $1, %ecx
movq %r12, %rdx
call cudaMemcpy@PLT
movq 40(%rbx), %rsi
movq 40(%rbp), %rdi
movl $1, %ecx
movq %r12, %rdx
call cudaMemcpy@PLT
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3778:
.size _Z15copy_job_to_devP5job_tS0_, .-_Z15copy_job_to_devP5job_tS0_
.globl _Z16copy_job_to_hostP5job_tS0_
.type _Z16copy_job_to_hostP5job_tS0_, @function
_Z16copy_job_to_hostP5job_tS0_:
.LFB3779:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
movq %rsi, %rbx
movl (%rsi), %eax
movl %eax, (%rdi)
movl 4(%rsi), %eax
movl %eax, 4(%rdi)
movl 8(%rsi), %eax
movl %eax, 8(%rdi)
movl (%rsi), %edi
imull 4(%rsi), %edi
call _Z9calc_jobsi
movslq %eax, %r12
leaq 0(,%r12,4), %r13
movq 16(%rbx), %rsi
movq 16(%rbp), %rdi
movl $2, %ecx
movq %r13, %rdx
call cudaMemcpy@PLT
movq 48(%rbx), %rsi
movq 48(%rbp), %rdi
movl $2, %ecx
movq %r13, %rdx
call cudaMemcpy@PLT
leaq (%r12,%r12,2), %r12
salq $2, %r12
movq 24(%rbx), %rsi
movq 24(%rbp), %rdi
movl $2, %ecx
movq %r12, %rdx
call cudaMemcpy@PLT
movq 32(%rbx), %rsi
movq 32(%rbp), %rdi
movl $2, %ecx
movq %r12, %rdx
call cudaMemcpy@PLT
movq 40(%rbx), %rsi
movq 40(%rbp), %rdi
movl $2, %ecx
movq %r12, %rdx
call cudaMemcpy@PLT
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3779:
.size _Z16copy_job_to_hostP5job_tS0_, .-_Z16copy_job_to_hostP5job_tS0_
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3805:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3805:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "job.cuh"
#include "common.cuh"
int calc_jobs(int real_job_num)
{
return (real_job_num / THREADS_PER_BLOCK) * THREADS_PER_BLOCK + ((real_job_num % THREADS_PER_BLOCK) ? THREADS_PER_BLOCK : 0);
}
job_t allocate_host_job(job_t job)
{
job_t host_job = job;
int jobs_num = calc_jobs(host_job.image_width * host_job.image_height);
safeMalloc((void **) &host_job.gather_arr, sizeof(int) * jobs_num);
safeMalloc((void **)&host_job.target_idx, sizeof(int) * jobs_num);
safeMalloc((void **)&host_job.image_dest, sizeof(float) * jobs_num * 3);
safeMalloc((void **)&host_job.ray_pos, sizeof(float) * jobs_num * 3);
safeMalloc((void **)&host_job.ray_dir, sizeof(float) * jobs_num * 3);
return host_job;
}
void free_host_job(job_t *host_job)
{
safeFree(host_job->gather_arr);
host_job->gather_arr = NULL;
safeFree(host_job->target_idx);
host_job->target_idx = NULL;
safeFree(host_job->image_dest);
host_job->image_dest = NULL;
safeFree(host_job->ray_pos);
host_job->ray_pos = NULL;
safeFree(host_job->ray_dir);
host_job->ray_dir = NULL;
}
job_t allocate_device_job(job_t job)
{
job_t dev_job = job;
int jobs_num = calc_jobs(dev_job.image_width * dev_job.image_height);
cudaSafeMalloc((void **)&dev_job.gather_arr, sizeof(int) * jobs_num);
cudaSafeMalloc((void **)&dev_job.target_idx, sizeof(int) * jobs_num);
cudaSafeMalloc((void **)&dev_job.image_dest, sizeof(float) * jobs_num * 3);
cudaSafeMalloc((void **)&dev_job.ray_pos, sizeof(float) * jobs_num * 3);
cudaSafeMalloc((void **)&dev_job.ray_dir, sizeof(float) * jobs_num * 3);
return dev_job;
}
void free_device_job(job_t *dev_job)
{
cudaSafeFree(dev_job->gather_arr);
dev_job->gather_arr = NULL;
cudaSafeFree(dev_job->target_idx);
dev_job->target_idx = NULL;
cudaSafeFree(dev_job->image_dest);
dev_job->image_dest = NULL;
cudaSafeFree(dev_job->ray_pos);
dev_job->ray_pos = NULL;
cudaSafeFree(dev_job->ray_dir);
dev_job->ray_dir = NULL;
}
void copy_job_to_dev(job_t *dev_dest, job_t *host_src)
{
dev_dest->image_width = host_src->image_width;
dev_dest->image_height = host_src->image_height;
dev_dest->pass_count = host_src->pass_count;
int hc = calc_jobs(host_src->image_width * host_src->image_height);
cudaMemcpy(dev_dest->gather_arr, host_src->gather_arr, hc * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_dest->target_idx, host_src->target_idx, hc * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_dest->image_dest, host_src->image_dest, hc * sizeof(float) * 3, cudaMemcpyHostToDevice);
cudaMemcpy(dev_dest->ray_pos, host_src->ray_pos, hc * sizeof(float) * 3, cudaMemcpyHostToDevice);
cudaMemcpy(dev_dest->ray_dir, host_src->ray_dir, hc * sizeof(float) * 3, cudaMemcpyHostToDevice);
}
void copy_job_to_host(job_t *host_dest, job_t *dev_src)
{
host_dest->image_width = dev_src->image_width;
host_dest->image_height = dev_src->image_height;
host_dest->pass_count = dev_src->pass_count;
int hc = calc_jobs(dev_src->image_width * dev_src->image_height);
cudaMemcpy(host_dest->gather_arr, dev_src->gather_arr, hc * sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy(host_dest->target_idx, dev_src->target_idx, hc * sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy(host_dest->image_dest, dev_src->image_dest, hc * sizeof(float) * 3, cudaMemcpyDeviceToHost);
cudaMemcpy(host_dest->ray_pos, dev_src->ray_pos, hc * sizeof(float) * 3, cudaMemcpyDeviceToHost);
cudaMemcpy(host_dest->ray_dir, dev_src->ray_dir, hc * sizeof(float) * 3, cudaMemcpyDeviceToHost);
} | #ifndef JOB_CUH
#define JOB_CUH
#include "hip/hip_runtime.h"
typedef struct
{
int image_width;
int image_height;
int pass_count;
int *gather_arr;
float *image_dest;
float *ray_pos;
float *ray_dir;
int *target_idx;
} job_t;
#define THREADS_PER_BLOCK 64
//#define THREADS_PER_BLOCK 64
#define BLOCKS_PER_JOB(size) ((size) / (THREADS_PER_BLOCK))
int calc_jobs(int real_job_num);
job_t allocate_host_job(job_t job);
void free_host_job(job_t *host_job);
void copy_job_to_dev(job_t *dev_dest, job_t *host_src);
void copy_job_to_host(job_t *host_dest, job_t *dev_src);
job_t allocate_device_job(job_t job);
void free_device_job(job_t *dev_job);
#endif |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #ifndef JOB_CUH
#define JOB_CUH
#include "hip/hip_runtime.h"
typedef struct
{
int image_width;
int image_height;
int pass_count;
int *gather_arr;
float *image_dest;
float *ray_pos;
float *ray_dir;
int *target_idx;
} job_t;
#define THREADS_PER_BLOCK 64
//#define THREADS_PER_BLOCK 64
#define BLOCKS_PER_JOB(size) ((size) / (THREADS_PER_BLOCK))
int calc_jobs(int real_job_num);
job_t allocate_host_job(job_t job);
void free_host_job(job_t *host_job);
void copy_job_to_dev(job_t *dev_dest, job_t *host_src);
void copy_job_to_host(job_t *host_dest, job_t *dev_src);
job_t allocate_device_job(job_t job);
void free_device_job(job_t *dev_job);
#endif | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #ifndef JOB_CUH
#define JOB_CUH
#include "hip/hip_runtime.h"
typedef struct
{
int image_width;
int image_height;
int pass_count;
int *gather_arr;
float *image_dest;
float *ray_pos;
float *ray_dir;
int *target_idx;
} job_t;
#define THREADS_PER_BLOCK 64
//#define THREADS_PER_BLOCK 64
#define BLOCKS_PER_JOB(size) ((size) / (THREADS_PER_BLOCK))
int calc_jobs(int real_job_num);
job_t allocate_host_job(job_t job);
void free_host_job(job_t *host_job);
void copy_job_to_dev(job_t *dev_dest, job_t *host_src);
void copy_job_to_host(job_t *host_dest, job_t *dev_src);
job_t allocate_device_job(job_t job);
void free_device_job(job_t *dev_job);
#endif | .text
.file "job.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ade49_00000000-6_job.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3782:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3782:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9calc_jobsi
.type _Z9calc_jobsi, @function
_Z9calc_jobsi:
.LFB3773:
.cfi_startproc
endbr64
testb $63, %dil
setne %al
movzbl %al, %eax
sall $6, %eax
leal 63(%rdi), %edx
testl %edi, %edi
cmovns %edi, %edx
andl $-64, %edx
addl %edx, %eax
ret
.cfi_endproc
.LFE3773:
.size _Z9calc_jobsi, .-_Z9calc_jobsi
.globl _Z17allocate_host_job5job_t
.type _Z17allocate_host_job5job_t, @function
_Z17allocate_host_job5job_t:
.LFB3774:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbx
movq 32(%rsp), %rax
movl %eax, %edi
movq %rax, (%rbx)
movq 40(%rsp), %rax
movq %rax, 8(%rbx)
movdqu 48(%rsp), %xmm0
movups %xmm0, 16(%rbx)
movdqu 64(%rsp), %xmm1
movups %xmm1, 32(%rbx)
movq 80(%rsp), %rax
movq %rax, 48(%rbx)
imull 4(%rbx), %edi
call _Z9calc_jobsi
movslq %eax, %rbp
leaq 0(,%rbp,4), %r12
leaq 16(%rbx), %rdi
movq %r12, %rsi
call _Z10safeMallocPPvm@PLT
leaq 48(%rbx), %rdi
movq %r12, %rsi
call _Z10safeMallocPPvm@PLT
leaq 0(%rbp,%rbp,2), %rbp
salq $2, %rbp
leaq 24(%rbx), %rdi
movq %rbp, %rsi
call _Z10safeMallocPPvm@PLT
leaq 32(%rbx), %rdi
movq %rbp, %rsi
call _Z10safeMallocPPvm@PLT
leaq 40(%rbx), %rdi
movq %rbp, %rsi
call _Z10safeMallocPPvm@PLT
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3774:
.size _Z17allocate_host_job5job_t, .-_Z17allocate_host_job5job_t
.globl _Z13free_host_jobP5job_t
.type _Z13free_host_jobP5job_t, @function
_Z13free_host_jobP5job_t:
.LFB3775:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq 16(%rdi), %rdi
call _Z8safeFreePv@PLT
movq $0, 16(%rbx)
movq 48(%rbx), %rdi
call _Z8safeFreePv@PLT
movq $0, 48(%rbx)
movq 24(%rbx), %rdi
call _Z8safeFreePv@PLT
movq $0, 24(%rbx)
movq 32(%rbx), %rdi
call _Z8safeFreePv@PLT
movq $0, 32(%rbx)
movq 40(%rbx), %rdi
call _Z8safeFreePv@PLT
movq $0, 40(%rbx)
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3775:
.size _Z13free_host_jobP5job_t, .-_Z13free_host_jobP5job_t
.globl _Z19allocate_device_job5job_t
.type _Z19allocate_device_job5job_t, @function
_Z19allocate_device_job5job_t:
.LFB3776:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbx
movq 32(%rsp), %rax
movl %eax, %edi
movq %rax, (%rbx)
movq 40(%rsp), %rax
movq %rax, 8(%rbx)
movdqu 48(%rsp), %xmm0
movups %xmm0, 16(%rbx)
movdqu 64(%rsp), %xmm1
movups %xmm1, 32(%rbx)
movq 80(%rsp), %rax
movq %rax, 48(%rbx)
imull 4(%rbx), %edi
call _Z9calc_jobsi
movslq %eax, %rbp
leaq 0(,%rbp,4), %r12
leaq 16(%rbx), %rdi
movq %r12, %rsi
call _Z14cudaSafeMallocPPvm@PLT
leaq 48(%rbx), %rdi
movq %r12, %rsi
call _Z14cudaSafeMallocPPvm@PLT
leaq 0(%rbp,%rbp,2), %rbp
salq $2, %rbp
leaq 24(%rbx), %rdi
movq %rbp, %rsi
call _Z14cudaSafeMallocPPvm@PLT
leaq 32(%rbx), %rdi
movq %rbp, %rsi
call _Z14cudaSafeMallocPPvm@PLT
leaq 40(%rbx), %rdi
movq %rbp, %rsi
call _Z14cudaSafeMallocPPvm@PLT
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3776:
.size _Z19allocate_device_job5job_t, .-_Z19allocate_device_job5job_t
.globl _Z15free_device_jobP5job_t
.type _Z15free_device_jobP5job_t, @function
_Z15free_device_jobP5job_t:
.LFB3777:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq 16(%rdi), %rdi
call _Z12cudaSafeFreePv@PLT
movq $0, 16(%rbx)
movq 48(%rbx), %rdi
call _Z12cudaSafeFreePv@PLT
movq $0, 48(%rbx)
movq 24(%rbx), %rdi
call _Z12cudaSafeFreePv@PLT
movq $0, 24(%rbx)
movq 32(%rbx), %rdi
call _Z12cudaSafeFreePv@PLT
movq $0, 32(%rbx)
movq 40(%rbx), %rdi
call _Z12cudaSafeFreePv@PLT
movq $0, 40(%rbx)
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3777:
.size _Z15free_device_jobP5job_t, .-_Z15free_device_jobP5job_t
.globl _Z15copy_job_to_devP5job_tS0_
.type _Z15copy_job_to_devP5job_tS0_, @function
_Z15copy_job_to_devP5job_tS0_:
.LFB3778:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
movq %rsi, %rbx
movl (%rsi), %eax
movl %eax, (%rdi)
movl 4(%rsi), %eax
movl %eax, 4(%rdi)
movl 8(%rsi), %eax
movl %eax, 8(%rdi)
movl (%rsi), %edi
imull 4(%rsi), %edi
call _Z9calc_jobsi
movslq %eax, %r12
leaq 0(,%r12,4), %r13
movq 16(%rbx), %rsi
movq 16(%rbp), %rdi
movl $1, %ecx
movq %r13, %rdx
call cudaMemcpy@PLT
movq 48(%rbx), %rsi
movq 48(%rbp), %rdi
movl $1, %ecx
movq %r13, %rdx
call cudaMemcpy@PLT
leaq (%r12,%r12,2), %r12
salq $2, %r12
movq 24(%rbx), %rsi
movq 24(%rbp), %rdi
movl $1, %ecx
movq %r12, %rdx
call cudaMemcpy@PLT
movq 32(%rbx), %rsi
movq 32(%rbp), %rdi
movl $1, %ecx
movq %r12, %rdx
call cudaMemcpy@PLT
movq 40(%rbx), %rsi
movq 40(%rbp), %rdi
movl $1, %ecx
movq %r12, %rdx
call cudaMemcpy@PLT
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3778:
.size _Z15copy_job_to_devP5job_tS0_, .-_Z15copy_job_to_devP5job_tS0_
.globl _Z16copy_job_to_hostP5job_tS0_
.type _Z16copy_job_to_hostP5job_tS0_, @function
_Z16copy_job_to_hostP5job_tS0_:
.LFB3779:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
movq %rsi, %rbx
movl (%rsi), %eax
movl %eax, (%rdi)
movl 4(%rsi), %eax
movl %eax, 4(%rdi)
movl 8(%rsi), %eax
movl %eax, 8(%rdi)
movl (%rsi), %edi
imull 4(%rsi), %edi
call _Z9calc_jobsi
movslq %eax, %r12
leaq 0(,%r12,4), %r13
movq 16(%rbx), %rsi
movq 16(%rbp), %rdi
movl $2, %ecx
movq %r13, %rdx
call cudaMemcpy@PLT
movq 48(%rbx), %rsi
movq 48(%rbp), %rdi
movl $2, %ecx
movq %r13, %rdx
call cudaMemcpy@PLT
leaq (%r12,%r12,2), %r12
salq $2, %r12
movq 24(%rbx), %rsi
movq 24(%rbp), %rdi
movl $2, %ecx
movq %r12, %rdx
call cudaMemcpy@PLT
movq 32(%rbx), %rsi
movq 32(%rbp), %rdi
movl $2, %ecx
movq %r12, %rdx
call cudaMemcpy@PLT
movq 40(%rbx), %rsi
movq 40(%rbp), %rdi
movl $2, %ecx
movq %r12, %rdx
call cudaMemcpy@PLT
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3779:
.size _Z16copy_job_to_hostP5job_tS0_, .-_Z16copy_job_to_hostP5job_tS0_
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3805:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3805:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "job.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
__global__ void mem_trs_test(int * input){
int gid = blockIdx.x * blockDim.x + threadIdx.x;
printf("tid = %d, gid = %d, value = %d\n", threadIdx.x, gid, input[gid]);
}
__global__ void mem_trs_test2(int * input, int size){
int gid = blockIdx.x * blockDim.x + threadIdx.x;
if (gid < size) {
printf("tid = %d, gid = %d, value = %d\n", threadIdx.x, gid, input[gid]);
}
}
int main(int argc, char ** argv) {
int size = 150;
int byte_size = size * sizeof(int);
int *h_input;
h_input = (int *)malloc(byte_size);
time_t t;
srand((unsigned)time(&t));
for (int i=0; i<size; i++) {
h_input[i] = (int) (rand() & 0xff);
}
int * d_input;
cudaMalloc((void**)&d_input, byte_size);
cudaMemcpy(d_input, h_input, byte_size, cudaMemcpyHostToDevice);
dim3 block(32);
dim3 grid(5);
mem_trs_test2 <<<grid, block>>>(d_input, size);
cudaDeviceSynchronize();
cudaDeviceReset();
return 0;
} | code for sm_80
Function : _Z13mem_trs_test2Pii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R11, SR_CTAID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002500 */
/*0020*/ IADD3 R1, R1, -0x10, RZ ; /* 0xfffffff001017810 */
/* 0x000fc60007ffe0ff */
/*0030*/ S2R R10, SR_TID.X ; /* 0x00000000000a7919 */
/* 0x000e220000002100 */
/*0040*/ IADD3 R6, P1, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f3e0ff */
/*0050*/ IMAD R11, R11, c[0x0][0x0], R10 ; /* 0x000000000b0b7a24 */
/* 0x001fca00078e020a */
/*0060*/ ISETP.GE.AND P0, PT, R11, c[0x0][0x168], PT ; /* 0x00005a000b007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ IMAD.WIDE R8, R11, R8, c[0x0][0x160] ; /* 0x000058000b087625 */
/* 0x000fcc00078e0208 */
/*00b0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ MOV R2, 0x0 ; /* 0x0000000000027802 */
/* 0x000fe20000000f00 */
/*00d0*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P1 ; /* 0x00000900ff077624 */
/* 0x000fe400008e06ff */
/*00e0*/ STL.64 [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0001e20000100a00 */
/*00f0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe400078e00ff */
/*0100*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000e620000000a00 */
/*0110*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0120*/ STL [R1+0x8], R8 ; /* 0x0000080801007387 */
/* 0x0041ec0000100800 */
/*0130*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x003fe40000000000 */
/*0140*/ MOV R11, 0x1b0 ; /* 0x000001b0000b7802 */
/* 0x000fe40000000f00 */
/*0150*/ MOV R20, 0x130 ; /* 0x0000013000147802 */
/* 0x000fc40000000f00 */
/*0160*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0170*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0180*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0190*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*01a0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x000fea0003c00000 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z12mem_trs_testPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R11, SR_CTAID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IADD3 R1, R1, -0x10, RZ ; /* 0xfffffff001017810 */
/* 0x000fe20007ffe0ff */
/*0050*/ S2R R10, SR_TID.X ; /* 0x00000000000a7919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R11, R11, c[0x0][0x0], R10 ; /* 0x000000000b0b7a24 */
/* 0x001fc800078e020a */
/*0070*/ IMAD.WIDE R2, R11, R2, c[0x0][0x160] ; /* 0x000058000b027625 */
/* 0x000fcc00078e0202 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0090*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*00a0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*00b0*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*00c0*/ STL.64 [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0001e20000100a00 */
/*00d0*/ LDC.64 R8, c[0x4][R0] ; /* 0x0100000000087b82 */
/* 0x0000620000000a00 */
/*00e0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*00f0*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*0100*/ STL [R1+0x8], R2 ; /* 0x0000080201007387 */
/* 0x0041e80000100800 */
/*0110*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x003fc60000000000 */
/*0120*/ MOV R11, 0x190 ; /* 0x00000190000b7802 */
/* 0x000fe40000000f00 */
/*0130*/ MOV R20, 0x110 ; /* 0x0000011000147802 */
/* 0x000fc40000000f00 */
/*0140*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0150*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0160*/ IADD3 R20, P0, P1, -R20, R11, R2 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e102 */
/*0170*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*0180*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
__global__ void mem_trs_test(int * input){
int gid = blockIdx.x * blockDim.x + threadIdx.x;
printf("tid = %d, gid = %d, value = %d\n", threadIdx.x, gid, input[gid]);
}
__global__ void mem_trs_test2(int * input, int size){
int gid = blockIdx.x * blockDim.x + threadIdx.x;
if (gid < size) {
printf("tid = %d, gid = %d, value = %d\n", threadIdx.x, gid, input[gid]);
}
}
int main(int argc, char ** argv) {
int size = 150;
int byte_size = size * sizeof(int);
int *h_input;
h_input = (int *)malloc(byte_size);
time_t t;
srand((unsigned)time(&t));
for (int i=0; i<size; i++) {
h_input[i] = (int) (rand() & 0xff);
}
int * d_input;
cudaMalloc((void**)&d_input, byte_size);
cudaMemcpy(d_input, h_input, byte_size, cudaMemcpyHostToDevice);
dim3 block(32);
dim3 grid(5);
mem_trs_test2 <<<grid, block>>>(d_input, size);
cudaDeviceSynchronize();
cudaDeviceReset();
return 0;
} | .file "tmpxft_00164e12_00000000-6_mem_ex.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z12mem_trs_testPiPi
.type _Z32__device_stub__Z12mem_trs_testPiPi, @function
_Z32__device_stub__Z12mem_trs_testPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12mem_trs_testPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z12mem_trs_testPiPi, .-_Z32__device_stub__Z12mem_trs_testPiPi
.globl _Z12mem_trs_testPi
.type _Z12mem_trs_testPi, @function
_Z12mem_trs_testPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z12mem_trs_testPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12mem_trs_testPi, .-_Z12mem_trs_testPi
.globl _Z34__device_stub__Z13mem_trs_test2PiiPii
.type _Z34__device_stub__Z13mem_trs_test2PiiPii, @function
_Z34__device_stub__Z13mem_trs_test2PiiPii:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13mem_trs_test2Pii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z34__device_stub__Z13mem_trs_test2PiiPii, .-_Z34__device_stub__Z13mem_trs_test2PiiPii
.globl _Z13mem_trs_test2Pii
.type _Z13mem_trs_test2Pii, @function
_Z13mem_trs_test2Pii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z13mem_trs_test2PiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z13mem_trs_test2Pii, .-_Z13mem_trs_test2Pii
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $600, %edi
call malloc@PLT
movq %rax, %r12
movq %rsp, %rdi
call time@PLT
movl %eax, %edi
call srand@PLT
movq %r12, %rbx
leaq 600(%r12), %rbp
.L20:
call rand@PLT
movzbl %al, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L20
leaq 8(%rsp), %rdi
movl $600, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $600, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 16(%rsp)
movl $1, 20(%rsp)
movl $5, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
call cudaDeviceSynchronize@PLT
call cudaDeviceReset@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movl $150, %esi
movq 8(%rsp), %rdi
call _Z34__device_stub__Z13mem_trs_test2PiiPii
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13mem_trs_test2Pii"
.LC1:
.string "_Z12mem_trs_testPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13mem_trs_test2Pii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z12mem_trs_testPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
__global__ void mem_trs_test(int * input){
int gid = blockIdx.x * blockDim.x + threadIdx.x;
printf("tid = %d, gid = %d, value = %d\n", threadIdx.x, gid, input[gid]);
}
__global__ void mem_trs_test2(int * input, int size){
int gid = blockIdx.x * blockDim.x + threadIdx.x;
if (gid < size) {
printf("tid = %d, gid = %d, value = %d\n", threadIdx.x, gid, input[gid]);
}
}
int main(int argc, char ** argv) {
int size = 150;
int byte_size = size * sizeof(int);
int *h_input;
h_input = (int *)malloc(byte_size);
time_t t;
srand((unsigned)time(&t));
for (int i=0; i<size; i++) {
h_input[i] = (int) (rand() & 0xff);
}
int * d_input;
cudaMalloc((void**)&d_input, byte_size);
cudaMemcpy(d_input, h_input, byte_size, cudaMemcpyHostToDevice);
dim3 block(32);
dim3 grid(5);
mem_trs_test2 <<<grid, block>>>(d_input, size);
cudaDeviceSynchronize();
cudaDeviceReset();
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include "hip/hip_runtime.h"
__global__ void mem_trs_test(int * input){
int gid = blockIdx.x * blockDim.x + threadIdx.x;
printf("tid = %d, gid = %d, value = %d\n", threadIdx.x, gid, input[gid]);
}
__global__ void mem_trs_test2(int * input, int size){
int gid = blockIdx.x * blockDim.x + threadIdx.x;
if (gid < size) {
printf("tid = %d, gid = %d, value = %d\n", threadIdx.x, gid, input[gid]);
}
}
int main(int argc, char ** argv) {
int size = 150;
int byte_size = size * sizeof(int);
int *h_input;
h_input = (int *)malloc(byte_size);
time_t t;
srand((unsigned)time(&t));
for (int i=0; i<size; i++) {
h_input[i] = (int) (rand() & 0xff);
}
int * d_input;
hipMalloc((void**)&d_input, byte_size);
hipMemcpy(d_input, h_input, byte_size, hipMemcpyHostToDevice);
dim3 block(32);
dim3 grid(5);
mem_trs_test2 <<<grid, block>>>(d_input, size);
hipDeviceSynchronize();
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include "hip/hip_runtime.h"
__global__ void mem_trs_test(int * input){
int gid = blockIdx.x * blockDim.x + threadIdx.x;
printf("tid = %d, gid = %d, value = %d\n", threadIdx.x, gid, input[gid]);
}
__global__ void mem_trs_test2(int * input, int size){
int gid = blockIdx.x * blockDim.x + threadIdx.x;
if (gid < size) {
printf("tid = %d, gid = %d, value = %d\n", threadIdx.x, gid, input[gid]);
}
}
int main(int argc, char ** argv) {
int size = 150;
int byte_size = size * sizeof(int);
int *h_input;
h_input = (int *)malloc(byte_size);
time_t t;
srand((unsigned)time(&t));
for (int i=0; i<size; i++) {
h_input[i] = (int) (rand() & 0xff);
}
int * d_input;
hipMalloc((void**)&d_input, byte_size);
hipMemcpy(d_input, h_input, byte_size, hipMemcpyHostToDevice);
dim3 block(32);
dim3 grid(5);
mem_trs_test2 <<<grid, block>>>(d_input, size);
hipDeviceSynchronize();
hipDeviceReset();
return 0;
} | .text
.file "mem_ex.hip"
.globl _Z27__device_stub__mem_trs_testPi # -- Begin function _Z27__device_stub__mem_trs_testPi
.p2align 4, 0x90
.type _Z27__device_stub__mem_trs_testPi,@function
_Z27__device_stub__mem_trs_testPi: # @_Z27__device_stub__mem_trs_testPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z12mem_trs_testPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z27__device_stub__mem_trs_testPi, .Lfunc_end0-_Z27__device_stub__mem_trs_testPi
.cfi_endproc
# -- End function
.globl _Z28__device_stub__mem_trs_test2Pii # -- Begin function _Z28__device_stub__mem_trs_test2Pii
.p2align 4, 0x90
.type _Z28__device_stub__mem_trs_test2Pii,@function
_Z28__device_stub__mem_trs_test2Pii: # @_Z28__device_stub__mem_trs_test2Pii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13mem_trs_test2Pii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z28__device_stub__mem_trs_test2Pii, .Lfunc_end1-_Z28__device_stub__mem_trs_test2Pii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $600, %edi # imm = 0x258
callq malloc
movq %rax, %rbx
leaq 96(%rsp), %rdi
callq time
movl %eax, %edi
callq srand
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $150, %r14
jne .LBB2_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $600, %esi # imm = 0x258
callq hipMalloc
movq 16(%rsp), %rdi
movl $600, %edx # imm = 0x258
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967301, %rdi # imm = 0x100000005
leaq 27(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl $150, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13mem_trs_test2Pii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
callq hipDeviceReset
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12mem_trs_testPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13mem_trs_test2Pii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12mem_trs_testPi,@object # @_Z12mem_trs_testPi
.section .rodata,"a",@progbits
.globl _Z12mem_trs_testPi
.p2align 3, 0x0
_Z12mem_trs_testPi:
.quad _Z27__device_stub__mem_trs_testPi
.size _Z12mem_trs_testPi, 8
.type _Z13mem_trs_test2Pii,@object # @_Z13mem_trs_test2Pii
.globl _Z13mem_trs_test2Pii
.p2align 3, 0x0
_Z13mem_trs_test2Pii:
.quad _Z28__device_stub__mem_trs_test2Pii
.size _Z13mem_trs_test2Pii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12mem_trs_testPi"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z13mem_trs_test2Pii"
.size .L__unnamed_2, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__mem_trs_testPi
.addrsig_sym _Z28__device_stub__mem_trs_test2Pii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12mem_trs_testPi
.addrsig_sym _Z13mem_trs_test2Pii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00164e12_00000000-6_mem_ex.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z12mem_trs_testPiPi
.type _Z32__device_stub__Z12mem_trs_testPiPi, @function
_Z32__device_stub__Z12mem_trs_testPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12mem_trs_testPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z12mem_trs_testPiPi, .-_Z32__device_stub__Z12mem_trs_testPiPi
.globl _Z12mem_trs_testPi
.type _Z12mem_trs_testPi, @function
_Z12mem_trs_testPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z12mem_trs_testPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12mem_trs_testPi, .-_Z12mem_trs_testPi
.globl _Z34__device_stub__Z13mem_trs_test2PiiPii
.type _Z34__device_stub__Z13mem_trs_test2PiiPii, @function
_Z34__device_stub__Z13mem_trs_test2PiiPii:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13mem_trs_test2Pii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z34__device_stub__Z13mem_trs_test2PiiPii, .-_Z34__device_stub__Z13mem_trs_test2PiiPii
.globl _Z13mem_trs_test2Pii
.type _Z13mem_trs_test2Pii, @function
_Z13mem_trs_test2Pii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z13mem_trs_test2PiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z13mem_trs_test2Pii, .-_Z13mem_trs_test2Pii
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $600, %edi
call malloc@PLT
movq %rax, %r12
movq %rsp, %rdi
call time@PLT
movl %eax, %edi
call srand@PLT
movq %r12, %rbx
leaq 600(%r12), %rbp
.L20:
call rand@PLT
movzbl %al, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L20
leaq 8(%rsp), %rdi
movl $600, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $600, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 16(%rsp)
movl $1, 20(%rsp)
movl $5, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
call cudaDeviceSynchronize@PLT
call cudaDeviceReset@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movl $150, %esi
movq 8(%rsp), %rdi
call _Z34__device_stub__Z13mem_trs_test2PiiPii
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13mem_trs_test2Pii"
.LC1:
.string "_Z12mem_trs_testPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13mem_trs_test2Pii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z12mem_trs_testPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mem_ex.hip"
.globl _Z27__device_stub__mem_trs_testPi # -- Begin function _Z27__device_stub__mem_trs_testPi
.p2align 4, 0x90
.type _Z27__device_stub__mem_trs_testPi,@function
_Z27__device_stub__mem_trs_testPi: # @_Z27__device_stub__mem_trs_testPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z12mem_trs_testPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z27__device_stub__mem_trs_testPi, .Lfunc_end0-_Z27__device_stub__mem_trs_testPi
.cfi_endproc
# -- End function
.globl _Z28__device_stub__mem_trs_test2Pii # -- Begin function _Z28__device_stub__mem_trs_test2Pii
.p2align 4, 0x90
.type _Z28__device_stub__mem_trs_test2Pii,@function
_Z28__device_stub__mem_trs_test2Pii: # @_Z28__device_stub__mem_trs_test2Pii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13mem_trs_test2Pii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z28__device_stub__mem_trs_test2Pii, .Lfunc_end1-_Z28__device_stub__mem_trs_test2Pii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $600, %edi # imm = 0x258
callq malloc
movq %rax, %rbx
leaq 96(%rsp), %rdi
callq time
movl %eax, %edi
callq srand
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $150, %r14
jne .LBB2_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $600, %esi # imm = 0x258
callq hipMalloc
movq 16(%rsp), %rdi
movl $600, %edx # imm = 0x258
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967301, %rdi # imm = 0x100000005
leaq 27(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl $150, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13mem_trs_test2Pii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
callq hipDeviceReset
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12mem_trs_testPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13mem_trs_test2Pii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12mem_trs_testPi,@object # @_Z12mem_trs_testPi
.section .rodata,"a",@progbits
.globl _Z12mem_trs_testPi
.p2align 3, 0x0
_Z12mem_trs_testPi:
.quad _Z27__device_stub__mem_trs_testPi
.size _Z12mem_trs_testPi, 8
.type _Z13mem_trs_test2Pii,@object # @_Z13mem_trs_test2Pii
.globl _Z13mem_trs_test2Pii
.p2align 3, 0x0
_Z13mem_trs_test2Pii:
.quad _Z28__device_stub__mem_trs_test2Pii
.size _Z13mem_trs_test2Pii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12mem_trs_testPi"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z13mem_trs_test2Pii"
.size .L__unnamed_2, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__mem_trs_testPi
.addrsig_sym _Z28__device_stub__mem_trs_test2Pii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12mem_trs_testPi
.addrsig_sym _Z13mem_trs_test2Pii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void kern_Lbl(float* lbl, float* flo, float* cap, const int size)
{
int idx = CUDASTDOFFSET;
float value1 = cap[idx];
float value2 = flo[idx];
float minVal = (value2 == value1) ? 1.0f : 0.0f;
if( idx < size )
{
lbl[idx] = minVal;
}
} | code for sm_80
Function : _Z8kern_LblPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Z ; /* 0x0000000000007919 */
/* 0x000e280000002700 */
/*0020*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0030*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000ea20000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x10], R3 ; /* 0x0000040000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD R0, R0, c[0x0][0xc], R5 ; /* 0x0000030000007a24 */
/* 0x002fc800078e0205 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x004fca00078e0207 */
/*0080*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00c0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fc800078e0207 */
/*00d0*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0207 */
/*00e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0100*/ IMAD.WIDE R6, R0, R7, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fe200078e0207 */
/*0110*/ FSET.BF.EQ.AND R9, R5, R2, PT ; /* 0x000000020509720a */
/* 0x004fca0003802000 */
/*0120*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kern_Lbl(float* lbl, float* flo, float* cap, const int size)
{
int idx = CUDASTDOFFSET;
float value1 = cap[idx];
float value2 = flo[idx];
float minVal = (value2 == value1) ? 1.0f : 0.0f;
if( idx < size )
{
lbl[idx] = minVal;
}
} | .file "tmpxft_000d5f26_00000000-6_kern_Lbl.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z8kern_LblPfS_S_iPfS_S_i
.type _Z32__device_stub__Z8kern_LblPfS_S_iPfS_S_i, @function
_Z32__device_stub__Z8kern_LblPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8kern_LblPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z8kern_LblPfS_S_iPfS_S_i, .-_Z32__device_stub__Z8kern_LblPfS_S_iPfS_S_i
.globl _Z8kern_LblPfS_S_i
.type _Z8kern_LblPfS_S_i, @function
_Z8kern_LblPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8kern_LblPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8kern_LblPfS_S_i, .-_Z8kern_LblPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8kern_LblPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8kern_LblPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kern_Lbl(float* lbl, float* flo, float* cap, const int size)
{
int idx = CUDASTDOFFSET;
float value1 = cap[idx];
float value2 = flo[idx];
float minVal = (value2 == value1) ? 1.0f : 0.0f;
if( idx < size )
{
lbl[idx] = minVal;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kern_Lbl(float* lbl, float* flo, float* cap, const int size)
{
int idx = CUDASTDOFFSET;
float value1 = cap[idx];
float value2 = flo[idx];
float minVal = (value2 == value1) ? 1.0f : 0.0f;
if( idx < size )
{
lbl[idx] = minVal;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kern_Lbl(float* lbl, float* flo, float* cap, const int size)
{
int idx = CUDASTDOFFSET;
float value1 = cap[idx];
float value2 = flo[idx];
float minVal = (value2 == value1) ? 1.0f : 0.0f;
if( idx < size )
{
lbl[idx] = minVal;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8kern_LblPfS_S_i
.globl _Z8kern_LblPfS_S_i
.p2align 8
.type _Z8kern_LblPfS_S_i,@function
_Z8kern_LblPfS_S_i:
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x20
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s5, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, s14
s_mul_i32 s2, s3, s2
s_and_b32 s3, s4, 0xffff
s_add_i32 s2, s2, s13
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s5, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
s_waitcnt vmcnt(0)
v_cmp_eq_f32_e32 vcc_lo, v2, v3
v_cndmask_b32_e64 v2, 0, 1.0, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8kern_LblPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8kern_LblPfS_S_i, .Lfunc_end0-_Z8kern_LblPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8kern_LblPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8kern_LblPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kern_Lbl(float* lbl, float* flo, float* cap, const int size)
{
int idx = CUDASTDOFFSET;
float value1 = cap[idx];
float value2 = flo[idx];
float minVal = (value2 == value1) ? 1.0f : 0.0f;
if( idx < size )
{
lbl[idx] = minVal;
}
} | .text
.file "kern_Lbl.hip"
.globl _Z23__device_stub__kern_LblPfS_S_i # -- Begin function _Z23__device_stub__kern_LblPfS_S_i
.p2align 4, 0x90
.type _Z23__device_stub__kern_LblPfS_S_i,@function
_Z23__device_stub__kern_LblPfS_S_i: # @_Z23__device_stub__kern_LblPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8kern_LblPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__kern_LblPfS_S_i, .Lfunc_end0-_Z23__device_stub__kern_LblPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8kern_LblPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8kern_LblPfS_S_i,@object # @_Z8kern_LblPfS_S_i
.section .rodata,"a",@progbits
.globl _Z8kern_LblPfS_S_i
.p2align 3, 0x0
_Z8kern_LblPfS_S_i:
.quad _Z23__device_stub__kern_LblPfS_S_i
.size _Z8kern_LblPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8kern_LblPfS_S_i"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__kern_LblPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8kern_LblPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8kern_LblPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Z ; /* 0x0000000000007919 */
/* 0x000e280000002700 */
/*0020*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0030*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000ea20000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x10], R3 ; /* 0x0000040000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD R0, R0, c[0x0][0xc], R5 ; /* 0x0000030000007a24 */
/* 0x002fc800078e0205 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x004fca00078e0207 */
/*0080*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00c0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fc800078e0207 */
/*00d0*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0207 */
/*00e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0100*/ IMAD.WIDE R6, R0, R7, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fe200078e0207 */
/*0110*/ FSET.BF.EQ.AND R9, R5, R2, PT ; /* 0x000000020509720a */
/* 0x004fca0003802000 */
/*0120*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8kern_LblPfS_S_i
.globl _Z8kern_LblPfS_S_i
.p2align 8
.type _Z8kern_LblPfS_S_i,@function
_Z8kern_LblPfS_S_i:
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x20
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s5, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, s14
s_mul_i32 s2, s3, s2
s_and_b32 s3, s4, 0xffff
s_add_i32 s2, s2, s13
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s5, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
s_waitcnt vmcnt(0)
v_cmp_eq_f32_e32 vcc_lo, v2, v3
v_cndmask_b32_e64 v2, 0, 1.0, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8kern_LblPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8kern_LblPfS_S_i, .Lfunc_end0-_Z8kern_LblPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8kern_LblPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8kern_LblPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d5f26_00000000-6_kern_Lbl.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z8kern_LblPfS_S_iPfS_S_i
.type _Z32__device_stub__Z8kern_LblPfS_S_iPfS_S_i, @function
_Z32__device_stub__Z8kern_LblPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8kern_LblPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z8kern_LblPfS_S_iPfS_S_i, .-_Z32__device_stub__Z8kern_LblPfS_S_iPfS_S_i
.globl _Z8kern_LblPfS_S_i
.type _Z8kern_LblPfS_S_i, @function
_Z8kern_LblPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8kern_LblPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8kern_LblPfS_S_i, .-_Z8kern_LblPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8kern_LblPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8kern_LblPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kern_Lbl.hip"
.globl _Z23__device_stub__kern_LblPfS_S_i # -- Begin function _Z23__device_stub__kern_LblPfS_S_i
.p2align 4, 0x90
.type _Z23__device_stub__kern_LblPfS_S_i,@function
_Z23__device_stub__kern_LblPfS_S_i: # @_Z23__device_stub__kern_LblPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8kern_LblPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__kern_LblPfS_S_i, .Lfunc_end0-_Z23__device_stub__kern_LblPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8kern_LblPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8kern_LblPfS_S_i,@object # @_Z8kern_LblPfS_S_i
.section .rodata,"a",@progbits
.globl _Z8kern_LblPfS_S_i
.p2align 3, 0x0
_Z8kern_LblPfS_S_i:
.quad _Z23__device_stub__kern_LblPfS_S_i
.size _Z8kern_LblPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8kern_LblPfS_S_i"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__kern_LblPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8kern_LblPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
FLUIDS v.3 - SPH Fluid Simulator for CPU and GPU
Copyright (C) 2012. Rama Hoetzlein, http://fluids3.com
Fluids-ZLib license (* see part 1 below)
This software is provided 'as-is', without any express or implied
warranty. In no event will the authors be held liable for any damages
arising from the use of this software.
Permission is granted to anyone to use this software for any purpose,
including commercial applications, and to alter it and redistribute it
freely, subject to the following restrictions:
1. The origin of this software must not be misrepresented; you must not
claim that you wrote the original software. Acknowledgement of the
original author is required if you publish this in a paper, or use it
in a product. (See fluids3.com for details)
2. Altered source versions must be plainly marked as such, and must not be
misrepresented as being the original software.
3. This notice may not be removed or altered from any source distribution.
*/ | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
FLUIDS v.3 - SPH Fluid Simulator for CPU and GPU
Copyright (C) 2012. Rama Hoetzlein, http://fluids3.com
Fluids-ZLib license (* see part 1 below)
This software is provided 'as-is', without any express or implied
warranty. In no event will the authors be held liable for any damages
arising from the use of this software.
Permission is granted to anyone to use this software for any purpose,
including commercial applications, and to alter it and redistribute it
freely, subject to the following restrictions:
1. The origin of this software must not be misrepresented; you must not
claim that you wrote the original software. Acknowledgement of the
original author is required if you publish this in a paper, or use it
in a product. (See fluids3.com for details)
2. Altered source versions must be plainly marked as such, and must not be
misrepresented as being the original software.
3. This notice may not be removed or altered from any source distribution.
*/ | .file "tmpxft_0000db4b_00000000-6_fluid_system_kern.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
FLUIDS v.3 - SPH Fluid Simulator for CPU and GPU
Copyright (C) 2012. Rama Hoetzlein, http://fluids3.com
Fluids-ZLib license (* see part 1 below)
This software is provided 'as-is', without any express or implied
warranty. In no event will the authors be held liable for any damages
arising from the use of this software.
Permission is granted to anyone to use this software for any purpose,
including commercial applications, and to alter it and redistribute it
freely, subject to the following restrictions:
1. The origin of this software must not be misrepresented; you must not
claim that you wrote the original software. Acknowledgement of the
original author is required if you publish this in a paper, or use it
in a product. (See fluids3.com for details)
2. Altered source versions must be plainly marked as such, and must not be
misrepresented as being the original software.
3. This notice may not be removed or altered from any source distribution.
*/ | #include <hip/hip_runtime.h>
/*
FLUIDS v.3 - SPH Fluid Simulator for CPU and GPU
Copyright (C) 2012. Rama Hoetzlein, http://fluids3.com
Fluids-ZLib license (* see part 1 below)
This software is provided 'as-is', without any express or implied
warranty. In no event will the authors be held liable for any damages
arising from the use of this software.
Permission is granted to anyone to use this software for any purpose,
including commercial applications, and to alter it and redistribute it
freely, subject to the following restrictions:
1. The origin of this software must not be misrepresented; you must not
claim that you wrote the original software. Acknowledgement of the
original author is required if you publish this in a paper, or use it
in a product. (See fluids3.com for details)
2. Altered source versions must be plainly marked as such, and must not be
misrepresented as being the original software.
3. This notice may not be removed or altered from any source distribution.
*/ |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/*
FLUIDS v.3 - SPH Fluid Simulator for CPU and GPU
Copyright (C) 2012. Rama Hoetzlein, http://fluids3.com
Fluids-ZLib license (* see part 1 below)
This software is provided 'as-is', without any express or implied
warranty. In no event will the authors be held liable for any damages
arising from the use of this software.
Permission is granted to anyone to use this software for any purpose,
including commercial applications, and to alter it and redistribute it
freely, subject to the following restrictions:
1. The origin of this software must not be misrepresented; you must not
claim that you wrote the original software. Acknowledgement of the
original author is required if you publish this in a paper, or use it
in a product. (See fluids3.com for details)
2. Altered source versions must be plainly marked as such, and must not be
misrepresented as being the original software.
3. This notice may not be removed or altered from any source distribution.
*/ | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/*
FLUIDS v.3 - SPH Fluid Simulator for CPU and GPU
Copyright (C) 2012. Rama Hoetzlein, http://fluids3.com
Fluids-ZLib license (* see part 1 below)
This software is provided 'as-is', without any express or implied
warranty. In no event will the authors be held liable for any damages
arising from the use of this software.
Permission is granted to anyone to use this software for any purpose,
including commercial applications, and to alter it and redistribute it
freely, subject to the following restrictions:
1. The origin of this software must not be misrepresented; you must not
claim that you wrote the original software. Acknowledgement of the
original author is required if you publish this in a paper, or use it
in a product. (See fluids3.com for details)
2. Altered source versions must be plainly marked as such, and must not be
misrepresented as being the original software.
3. This notice may not be removed or altered from any source distribution.
*/ | .text
.file "fluid_system_kern.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0000db4b_00000000-6_fluid_system_kern.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "fluid_system_kern.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | extern "C" __global__
void cu_hysteresis_low(float* final_img, float* edge_img, float* strong_edge_mask,
float* weak_edge_mask, float t_low, int img_height, int img_width)
{
int n, s, e, w;
int nw, ne, sw, se;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (weak_edge_mask[idx] > 0)
{
n = idx - img_width;
nw = n - 1;
ne = n + 1;
s = idx + img_width;
sw = s - 1;
se = s + 1;
w = idx - 1;
e = idx + 1;
if (strong_edge_mask[nw] > 0) {
final_img[idx] = 1;
}
if (strong_edge_mask[n] > 0) {
final_img[idx] = 1;
}
if (strong_edge_mask[ne] > 0) {
final_img[idx] = 1;
}
if (strong_edge_mask[w] > 0) {
final_img[idx] = 1;
}
if (strong_edge_mask[e] > 0) {
final_img[idx] = 1;
}
if (strong_edge_mask[sw] > 0) {
final_img[idx] = 1;
}
if (strong_edge_mask[s] > 0) {
final_img[idx] = 1;
}
if (strong_edge_mask[se] > 0) {
final_img[idx] = 1;
}
}
// if ((idx > img_width) /* skip first row */
// && (idx < (img_height * img_width) - img_width) /* skip last row */
// && ((idx % img_width) < (img_width - 1)) /* skip last column */
// && ((idx % img_width) > 0)) /* skip first column */
// {
// if (strong_edge_mask[idx]>0) { /* if this pixel was previously found to be a strong edge */
// // get indices
// n = idx - img_width;
// nw = n - 1;
// ne = n + 1;
// s = idx + img_width;
// sw = s - 1;
// se = s + 1;
// w = idx - 1;
// e = idx + 1;
// if (edge_img[nw] >= t_low) {
// final_img[idx] = 1;
// }
// if (edge_img[n] >= t_low) {
// final_img[idx] = 1;
// }
// if (edge_img[ne] >= t_low) {
// final_img[idx] = 1;
// }
// if (edge_img[w] >= t_low) {
// final_img[idx] = 1;
// }
// if (edge_img[e] >= t_low) {
// final_img[idx] = 1;
// }
// if (edge_img[sw] >= t_low) {
// final_img[idx] = 1;
// }
// if (edge_img[s] >= t_low) {
// final_img[idx] = 1;
// }
// if (edge_img[se] >= t_low) {
// final_img[idx] = 1;
// }
// }//end if(1 == strong_edge_mask[idx])
// }//end if ((idx > img_width)
} | code for sm_80
Function : cu_hysteresis_low
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R11, SR_CTAID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, 0x4 ; /* 0x00000004ff007424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R11, R11, c[0x0][0x0], R2 ; /* 0x000000000b0b7a24 */
/* 0x001fc800078e0202 */
/*0060*/ IMAD.WIDE R2, R11, R0, c[0x0][0x178] ; /* 0x00005e000b027625 */
/* 0x000fcc00078e0200 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*0080*/ FSETP.GT.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720b */
/* 0x004fda0003f04000 */
/*0090*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R7, R11, -c[0x0][0x188], RZ ; /* 0x800062000b077a10 */
/* 0x000fc80007ffe0ff */
/*00b0*/ IADD3 R5, R7, -0x1, RZ ; /* 0xffffffff07057810 */
/* 0x000fca0007ffe0ff */
/*00c0*/ IMAD.WIDE R4, R5, R0, c[0x0][0x170] ; /* 0x00005c0005047625 */
/* 0x000fca00078e0200 */
/*00d0*/ LDG.E R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ SHF.R.S32.HI R6, RZ, 0x1f, R11 ; /* 0x0000001fff067819 */
/* 0x000fe4000001140b */
/*00f0*/ FSETP.GT.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720b */
/* 0x004fe40003f04000 */
/*0100*/ LEA R2, P1, R11, c[0x0][0x160], 0x2 ; /* 0x000058000b027a11 */
/* 0x000fc800078210ff */
/*0110*/ LEA.HI.X R3, R11, c[0x0][0x164], R6, 0x2, P1 ; /* 0x000059000b037a11 */
/* 0x000fe200008f1406 */
/*0120*/ IMAD.WIDE R6, R7, R0, c[0x0][0x170] ; /* 0x00005c0007067625 */
/* 0x000fcc00078e0200 */
/*0130*/ @P0 IMAD.MOV.U32 R13, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff0d0424 */
/* 0x000fca00078e00ff */
/*0140*/ @P0 STG.E [R2.64], R13 ; /* 0x0000000d02000986 */
/* 0x0001e8000c101904 */
/*0150*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea4000c1e1900 */
/*0160*/ FSETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720b */
/* 0x004fda0003f04000 */
/*0170*/ @P0 IMAD.MOV.U32 R15, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff0f0424 */
/* 0x000fca00078e00ff */
/*0180*/ @P0 STG.E [R2.64], R15 ; /* 0x0000000f02000986 */
/* 0x000fe8000c101904 */
/*0190*/ LDG.E R4, [R4.64+0x8] ; /* 0x0000080404047981 */
/* 0x000ea2000c1e1900 */
/*01a0*/ IADD3 R9, R11, -0x1, RZ ; /* 0xffffffff0b097810 */
/* 0x000fca0007ffe0ff */
/*01b0*/ IMAD.WIDE R8, R9, R0, c[0x0][0x170] ; /* 0x00005c0009087625 */
/* 0x000fe200078e0200 */
/*01c0*/ FSETP.GT.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720b */
/* 0x004fda0003f04000 */
/*01d0*/ @P0 IMAD.MOV.U32 R17, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff110424 */
/* 0x000fca00078e00ff */
/*01e0*/ @P0 STG.E [R2.64], R17 ; /* 0x0000001102000986 */
/* 0x000fe8000c101904 */
/*01f0*/ LDG.E R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x000ea4000c1e1900 */
/*0200*/ FSETP.GT.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720b */
/* 0x004fda0003f04000 */
/*0210*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff070424 */
/* 0x000fca00078e00ff */
/*0220*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */
/* 0x0003e8000c101904 */
/*0230*/ LDG.E R6, [R8.64+0x8] ; /* 0x0000080408067981 */
/* 0x000ea2000c1e1900 */
/*0240*/ IADD3 R5, R11, c[0x0][0x188], RZ ; /* 0x000062000b057a10 */
/* 0x000fca0007ffe0ff */
/*0250*/ IMAD.WIDE R4, R5, R0, c[0x0][0x170] ; /* 0x00005c0005047625 */
/* 0x000fe200078e0200 */
/*0260*/ FSETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720b */
/* 0x004fda0003f04000 */
/*0270*/ @P0 IMAD.MOV.U32 R11, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff0b0424 */
/* 0x000fca00078e00ff */
/*0280*/ @P0 STG.E [R2.64], R11 ; /* 0x0000000b02000986 */
/* 0x0005e8000c101904 */
/*0290*/ LDG.E R0, [R4.64+-0x4] ; /* 0xfffffc0404007981 */
/* 0x000ee4000c1e1900 */
/*02a0*/ FSETP.GT.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720b */
/* 0x008fda0003f04000 */
/*02b0*/ @P0 IMAD.MOV.U32 R13, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff0d0424 */
/* 0x001fca00078e00ff */
/*02c0*/ @P0 STG.E [R2.64], R13 ; /* 0x0000000d02000986 */
/* 0x0005e8000c101904 */
/*02d0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ee4000c1e1900 */
/*02e0*/ FSETP.GT.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720b */
/* 0x008fda0003f04000 */
/*02f0*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff070424 */
/* 0x002fca00078e00ff */
/*0300*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */
/* 0x0005e8000c101904 */
/*0310*/ LDG.E R0, [R4.64+0x4] ; /* 0x0000040404007981 */
/* 0x000ee4000c1e1900 */
/*0320*/ FSETP.GT.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720b */
/* 0x008fda0003f04000 */
/*0330*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0340*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff057424 */
/* 0x004fca00078e00ff */
/*0350*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0360*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0370*/ BRA 0x370; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C" __global__
void cu_hysteresis_low(float* final_img, float* edge_img, float* strong_edge_mask,
float* weak_edge_mask, float t_low, int img_height, int img_width)
{
int n, s, e, w;
int nw, ne, sw, se;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (weak_edge_mask[idx] > 0)
{
n = idx - img_width;
nw = n - 1;
ne = n + 1;
s = idx + img_width;
sw = s - 1;
se = s + 1;
w = idx - 1;
e = idx + 1;
if (strong_edge_mask[nw] > 0) {
final_img[idx] = 1;
}
if (strong_edge_mask[n] > 0) {
final_img[idx] = 1;
}
if (strong_edge_mask[ne] > 0) {
final_img[idx] = 1;
}
if (strong_edge_mask[w] > 0) {
final_img[idx] = 1;
}
if (strong_edge_mask[e] > 0) {
final_img[idx] = 1;
}
if (strong_edge_mask[sw] > 0) {
final_img[idx] = 1;
}
if (strong_edge_mask[s] > 0) {
final_img[idx] = 1;
}
if (strong_edge_mask[se] > 0) {
final_img[idx] = 1;
}
}
// if ((idx > img_width) /* skip first row */
// && (idx < (img_height * img_width) - img_width) /* skip last row */
// && ((idx % img_width) < (img_width - 1)) /* skip last column */
// && ((idx % img_width) > 0)) /* skip first column */
// {
// if (strong_edge_mask[idx]>0) { /* if this pixel was previously found to be a strong edge */
// // get indices
// n = idx - img_width;
// nw = n - 1;
// ne = n + 1;
// s = idx + img_width;
// sw = s - 1;
// se = s + 1;
// w = idx - 1;
// e = idx + 1;
// if (edge_img[nw] >= t_low) {
// final_img[idx] = 1;
// }
// if (edge_img[n] >= t_low) {
// final_img[idx] = 1;
// }
// if (edge_img[ne] >= t_low) {
// final_img[idx] = 1;
// }
// if (edge_img[w] >= t_low) {
// final_img[idx] = 1;
// }
// if (edge_img[e] >= t_low) {
// final_img[idx] = 1;
// }
// if (edge_img[sw] >= t_low) {
// final_img[idx] = 1;
// }
// if (edge_img[s] >= t_low) {
// final_img[idx] = 1;
// }
// if (edge_img[se] >= t_low) {
// final_img[idx] = 1;
// }
// }//end if(1 == strong_edge_mask[idx])
// }//end if ((idx > img_width)
} | .file "tmpxft_0010425f_00000000-6_cu_hysteresis_low.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z17cu_hysteresis_lowPfS_S_S_fiiPfS_S_S_fii
.type _Z46__device_stub__Z17cu_hysteresis_lowPfS_S_S_fiiPfS_S_S_fii, @function
_Z46__device_stub__Z17cu_hysteresis_lowPfS_S_S_fiiPfS_S_S_fii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movss %xmm0, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 4(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq cu_hysteresis_low(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z17cu_hysteresis_lowPfS_S_S_fiiPfS_S_S_fii, .-_Z46__device_stub__Z17cu_hysteresis_lowPfS_S_S_fiiPfS_S_S_fii
.globl cu_hysteresis_low
.type cu_hysteresis_low, @function
cu_hysteresis_low:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z17cu_hysteresis_lowPfS_S_S_fiiPfS_S_S_fii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size cu_hysteresis_low, .-cu_hysteresis_low
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "cu_hysteresis_low"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq cu_hysteresis_low(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C" __global__
void cu_hysteresis_low(float* final_img, float* edge_img, float* strong_edge_mask,
float* weak_edge_mask, float t_low, int img_height, int img_width)
{
int n, s, e, w;
int nw, ne, sw, se;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (weak_edge_mask[idx] > 0)
{
n = idx - img_width;
nw = n - 1;
ne = n + 1;
s = idx + img_width;
sw = s - 1;
se = s + 1;
w = idx - 1;
e = idx + 1;
if (strong_edge_mask[nw] > 0) {
final_img[idx] = 1;
}
if (strong_edge_mask[n] > 0) {
final_img[idx] = 1;
}
if (strong_edge_mask[ne] > 0) {
final_img[idx] = 1;
}
if (strong_edge_mask[w] > 0) {
final_img[idx] = 1;
}
if (strong_edge_mask[e] > 0) {
final_img[idx] = 1;
}
if (strong_edge_mask[sw] > 0) {
final_img[idx] = 1;
}
if (strong_edge_mask[s] > 0) {
final_img[idx] = 1;
}
if (strong_edge_mask[se] > 0) {
final_img[idx] = 1;
}
}
// if ((idx > img_width) /* skip first row */
// && (idx < (img_height * img_width) - img_width) /* skip last row */
// && ((idx % img_width) < (img_width - 1)) /* skip last column */
// && ((idx % img_width) > 0)) /* skip first column */
// {
// if (strong_edge_mask[idx]>0) { /* if this pixel was previously found to be a strong edge */
// // get indices
// n = idx - img_width;
// nw = n - 1;
// ne = n + 1;
// s = idx + img_width;
// sw = s - 1;
// se = s + 1;
// w = idx - 1;
// e = idx + 1;
// if (edge_img[nw] >= t_low) {
// final_img[idx] = 1;
// }
// if (edge_img[n] >= t_low) {
// final_img[idx] = 1;
// }
// if (edge_img[ne] >= t_low) {
// final_img[idx] = 1;
// }
// if (edge_img[w] >= t_low) {
// final_img[idx] = 1;
// }
// if (edge_img[e] >= t_low) {
// final_img[idx] = 1;
// }
// if (edge_img[sw] >= t_low) {
// final_img[idx] = 1;
// }
// if (edge_img[s] >= t_low) {
// final_img[idx] = 1;
// }
// if (edge_img[se] >= t_low) {
// final_img[idx] = 1;
// }
// }//end if(1 == strong_edge_mask[idx])
// }//end if ((idx > img_width)
} | #include <hip/hip_runtime.h>
extern "C" __global__
void cu_hysteresis_low(float* final_img, float* edge_img, float* strong_edge_mask,
float* weak_edge_mask, float t_low, int img_height, int img_width)
{
int n, s, e, w;
int nw, ne, sw, se;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (weak_edge_mask[idx] > 0)
{
n = idx - img_width;
nw = n - 1;
ne = n + 1;
s = idx + img_width;
sw = s - 1;
se = s + 1;
w = idx - 1;
e = idx + 1;
if (strong_edge_mask[nw] > 0) {
final_img[idx] = 1;
}
if (strong_edge_mask[n] > 0) {
final_img[idx] = 1;
}
if (strong_edge_mask[ne] > 0) {
final_img[idx] = 1;
}
if (strong_edge_mask[w] > 0) {
final_img[idx] = 1;
}
if (strong_edge_mask[e] > 0) {
final_img[idx] = 1;
}
if (strong_edge_mask[sw] > 0) {
final_img[idx] = 1;
}
if (strong_edge_mask[s] > 0) {
final_img[idx] = 1;
}
if (strong_edge_mask[se] > 0) {
final_img[idx] = 1;
}
}
// if ((idx > img_width) /* skip first row */
// && (idx < (img_height * img_width) - img_width) /* skip last row */
// && ((idx % img_width) < (img_width - 1)) /* skip last column */
// && ((idx % img_width) > 0)) /* skip first column */
// {
// if (strong_edge_mask[idx]>0) { /* if this pixel was previously found to be a strong edge */
// // get indices
// n = idx - img_width;
// nw = n - 1;
// ne = n + 1;
// s = idx + img_width;
// sw = s - 1;
// se = s + 1;
// w = idx - 1;
// e = idx + 1;
// if (edge_img[nw] >= t_low) {
// final_img[idx] = 1;
// }
// if (edge_img[n] >= t_low) {
// final_img[idx] = 1;
// }
// if (edge_img[ne] >= t_low) {
// final_img[idx] = 1;
// }
// if (edge_img[w] >= t_low) {
// final_img[idx] = 1;
// }
// if (edge_img[e] >= t_low) {
// final_img[idx] = 1;
// }
// if (edge_img[sw] >= t_low) {
// final_img[idx] = 1;
// }
// if (edge_img[s] >= t_low) {
// final_img[idx] = 1;
// }
// if (edge_img[se] >= t_low) {
// final_img[idx] = 1;
// }
// }//end if(1 == strong_edge_mask[idx])
// }//end if ((idx > img_width)
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C" __global__
void cu_hysteresis_low(float* final_img, float* edge_img, float* strong_edge_mask,
float* weak_edge_mask, float t_low, int img_height, int img_width)
{
int n, s, e, w;
int nw, ne, sw, se;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (weak_edge_mask[idx] > 0)
{
n = idx - img_width;
nw = n - 1;
ne = n + 1;
s = idx + img_width;
sw = s - 1;
se = s + 1;
w = idx - 1;
e = idx + 1;
if (strong_edge_mask[nw] > 0) {
final_img[idx] = 1;
}
if (strong_edge_mask[n] > 0) {
final_img[idx] = 1;
}
if (strong_edge_mask[ne] > 0) {
final_img[idx] = 1;
}
if (strong_edge_mask[w] > 0) {
final_img[idx] = 1;
}
if (strong_edge_mask[e] > 0) {
final_img[idx] = 1;
}
if (strong_edge_mask[sw] > 0) {
final_img[idx] = 1;
}
if (strong_edge_mask[s] > 0) {
final_img[idx] = 1;
}
if (strong_edge_mask[se] > 0) {
final_img[idx] = 1;
}
}
// if ((idx > img_width) /* skip first row */
// && (idx < (img_height * img_width) - img_width) /* skip last row */
// && ((idx % img_width) < (img_width - 1)) /* skip last column */
// && ((idx % img_width) > 0)) /* skip first column */
// {
// if (strong_edge_mask[idx]>0) { /* if this pixel was previously found to be a strong edge */
// // get indices
// n = idx - img_width;
// nw = n - 1;
// ne = n + 1;
// s = idx + img_width;
// sw = s - 1;
// se = s + 1;
// w = idx - 1;
// e = idx + 1;
// if (edge_img[nw] >= t_low) {
// final_img[idx] = 1;
// }
// if (edge_img[n] >= t_low) {
// final_img[idx] = 1;
// }
// if (edge_img[ne] >= t_low) {
// final_img[idx] = 1;
// }
// if (edge_img[w] >= t_low) {
// final_img[idx] = 1;
// }
// if (edge_img[e] >= t_low) {
// final_img[idx] = 1;
// }
// if (edge_img[sw] >= t_low) {
// final_img[idx] = 1;
// }
// if (edge_img[s] >= t_low) {
// final_img[idx] = 1;
// }
// if (edge_img[se] >= t_low) {
// final_img[idx] = 1;
// }
// }//end if(1 == strong_edge_mask[idx])
// }//end if ((idx > img_width)
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected cu_hysteresis_low
.globl cu_hysteresis_low
.p2align 8
.type cu_hysteresis_low,@function
cu_hysteresis_low:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x3c
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_mov_b32 s2, exec_lo
global_load_b32 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_cmpx_lt_f32_e32 0, v0
s_cbranch_execz .LBB0_17
s_clause 0x2
s_load_b32 s4, s[0:1], 0x28
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
v_subrev_nc_u32_e32 v3, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v0, v[3:4], off offset:-4
s_waitcnt vmcnt(0)
v_cmpx_lt_f32_e32 0, v0
s_cbranch_execz .LBB0_3
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_mov_b32_e32 v0, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
global_store_b32 v[5:6], v0, off
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s5
global_load_b32 v0, v[3:4], off
s_mov_b32 s5, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_lt_f32_e32 0, v0
s_cbranch_execz .LBB0_5
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_mov_b32_e32 v0, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
global_store_b32 v[5:6], v0, off
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s5
global_load_b32 v0, v[3:4], off offset:4
s_mov_b32 s5, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_lt_f32_e32 0, v0
s_cbranch_execz .LBB0_7
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_mov_b32_e32 v0, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_store_b32 v[3:4], v0, off
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s5
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v6, vcc_lo
global_load_b32 v0, v[3:4], off offset:-4
s_waitcnt vmcnt(0)
v_cmpx_lt_f32_e32 0, v0
s_cbranch_execz .LBB0_9
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
v_mov_b32_e32 v0, 1.0
global_store_b32 v[5:6], v0, off
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s5
global_load_b32 v0, v[3:4], off offset:4
s_mov_b32 s5, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_lt_f32_e32 0, v0
s_cbranch_execz .LBB0_11
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_mov_b32_e32 v0, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_store_b32 v[3:4], v0, off
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s5
v_add_nc_u32_e32 v3, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_mov_b32 s2, exec_lo
global_load_b32 v0, v[3:4], off offset:-4
s_waitcnt vmcnt(0)
v_cmpx_lt_f32_e32 0, v0
s_cbranch_execz .LBB0_13
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_mov_b32_e32 v0, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
global_store_b32 v[5:6], v0, off
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s2
global_load_b32 v0, v[3:4], off
s_mov_b32 s2, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_lt_f32_e32 0, v0
s_cbranch_execz .LBB0_15
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_mov_b32_e32 v0, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
global_store_b32 v[5:6], v0, off
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s2
global_load_b32 v0, v[3:4], off offset:4
s_waitcnt vmcnt(0)
v_cmp_lt_f32_e32 vcc_lo, 0, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_17
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_17:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel cu_hysteresis_low
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size cu_hysteresis_low, .Lfunc_end0-cu_hysteresis_low
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: cu_hysteresis_low
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: cu_hysteresis_low.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C" __global__
void cu_hysteresis_low(float* final_img, float* edge_img, float* strong_edge_mask,
float* weak_edge_mask, float t_low, int img_height, int img_width)
{
int n, s, e, w;
int nw, ne, sw, se;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (weak_edge_mask[idx] > 0)
{
n = idx - img_width;
nw = n - 1;
ne = n + 1;
s = idx + img_width;
sw = s - 1;
se = s + 1;
w = idx - 1;
e = idx + 1;
if (strong_edge_mask[nw] > 0) {
final_img[idx] = 1;
}
if (strong_edge_mask[n] > 0) {
final_img[idx] = 1;
}
if (strong_edge_mask[ne] > 0) {
final_img[idx] = 1;
}
if (strong_edge_mask[w] > 0) {
final_img[idx] = 1;
}
if (strong_edge_mask[e] > 0) {
final_img[idx] = 1;
}
if (strong_edge_mask[sw] > 0) {
final_img[idx] = 1;
}
if (strong_edge_mask[s] > 0) {
final_img[idx] = 1;
}
if (strong_edge_mask[se] > 0) {
final_img[idx] = 1;
}
}
// if ((idx > img_width) /* skip first row */
// && (idx < (img_height * img_width) - img_width) /* skip last row */
// && ((idx % img_width) < (img_width - 1)) /* skip last column */
// && ((idx % img_width) > 0)) /* skip first column */
// {
// if (strong_edge_mask[idx]>0) { /* if this pixel was previously found to be a strong edge */
// // get indices
// n = idx - img_width;
// nw = n - 1;
// ne = n + 1;
// s = idx + img_width;
// sw = s - 1;
// se = s + 1;
// w = idx - 1;
// e = idx + 1;
// if (edge_img[nw] >= t_low) {
// final_img[idx] = 1;
// }
// if (edge_img[n] >= t_low) {
// final_img[idx] = 1;
// }
// if (edge_img[ne] >= t_low) {
// final_img[idx] = 1;
// }
// if (edge_img[w] >= t_low) {
// final_img[idx] = 1;
// }
// if (edge_img[e] >= t_low) {
// final_img[idx] = 1;
// }
// if (edge_img[sw] >= t_low) {
// final_img[idx] = 1;
// }
// if (edge_img[s] >= t_low) {
// final_img[idx] = 1;
// }
// if (edge_img[se] >= t_low) {
// final_img[idx] = 1;
// }
// }//end if(1 == strong_edge_mask[idx])
// }//end if ((idx > img_width)
} | .text
.file "cu_hysteresis_low.hip"
.globl __device_stub__cu_hysteresis_low # -- Begin function __device_stub__cu_hysteresis_low
.p2align 4, 0x90
.type __device_stub__cu_hysteresis_low,@function
__device_stub__cu_hysteresis_low: # @__device_stub__cu_hysteresis_low
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movss %xmm0, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $cu_hysteresis_low, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size __device_stub__cu_hysteresis_low, .Lfunc_end0-__device_stub__cu_hysteresis_low
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $cu_hysteresis_low, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type cu_hysteresis_low,@object # @cu_hysteresis_low
.section .rodata,"a",@progbits
.globl cu_hysteresis_low
.p2align 3, 0x0
cu_hysteresis_low:
.quad __device_stub__cu_hysteresis_low
.size cu_hysteresis_low, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "cu_hysteresis_low"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__cu_hysteresis_low
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym cu_hysteresis_low
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : cu_hysteresis_low
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R11, SR_CTAID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, 0x4 ; /* 0x00000004ff007424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R11, R11, c[0x0][0x0], R2 ; /* 0x000000000b0b7a24 */
/* 0x001fc800078e0202 */
/*0060*/ IMAD.WIDE R2, R11, R0, c[0x0][0x178] ; /* 0x00005e000b027625 */
/* 0x000fcc00078e0200 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*0080*/ FSETP.GT.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720b */
/* 0x004fda0003f04000 */
/*0090*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R7, R11, -c[0x0][0x188], RZ ; /* 0x800062000b077a10 */
/* 0x000fc80007ffe0ff */
/*00b0*/ IADD3 R5, R7, -0x1, RZ ; /* 0xffffffff07057810 */
/* 0x000fca0007ffe0ff */
/*00c0*/ IMAD.WIDE R4, R5, R0, c[0x0][0x170] ; /* 0x00005c0005047625 */
/* 0x000fca00078e0200 */
/*00d0*/ LDG.E R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ SHF.R.S32.HI R6, RZ, 0x1f, R11 ; /* 0x0000001fff067819 */
/* 0x000fe4000001140b */
/*00f0*/ FSETP.GT.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720b */
/* 0x004fe40003f04000 */
/*0100*/ LEA R2, P1, R11, c[0x0][0x160], 0x2 ; /* 0x000058000b027a11 */
/* 0x000fc800078210ff */
/*0110*/ LEA.HI.X R3, R11, c[0x0][0x164], R6, 0x2, P1 ; /* 0x000059000b037a11 */
/* 0x000fe200008f1406 */
/*0120*/ IMAD.WIDE R6, R7, R0, c[0x0][0x170] ; /* 0x00005c0007067625 */
/* 0x000fcc00078e0200 */
/*0130*/ @P0 IMAD.MOV.U32 R13, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff0d0424 */
/* 0x000fca00078e00ff */
/*0140*/ @P0 STG.E [R2.64], R13 ; /* 0x0000000d02000986 */
/* 0x0001e8000c101904 */
/*0150*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea4000c1e1900 */
/*0160*/ FSETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720b */
/* 0x004fda0003f04000 */
/*0170*/ @P0 IMAD.MOV.U32 R15, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff0f0424 */
/* 0x000fca00078e00ff */
/*0180*/ @P0 STG.E [R2.64], R15 ; /* 0x0000000f02000986 */
/* 0x000fe8000c101904 */
/*0190*/ LDG.E R4, [R4.64+0x8] ; /* 0x0000080404047981 */
/* 0x000ea2000c1e1900 */
/*01a0*/ IADD3 R9, R11, -0x1, RZ ; /* 0xffffffff0b097810 */
/* 0x000fca0007ffe0ff */
/*01b0*/ IMAD.WIDE R8, R9, R0, c[0x0][0x170] ; /* 0x00005c0009087625 */
/* 0x000fe200078e0200 */
/*01c0*/ FSETP.GT.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720b */
/* 0x004fda0003f04000 */
/*01d0*/ @P0 IMAD.MOV.U32 R17, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff110424 */
/* 0x000fca00078e00ff */
/*01e0*/ @P0 STG.E [R2.64], R17 ; /* 0x0000001102000986 */
/* 0x000fe8000c101904 */
/*01f0*/ LDG.E R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x000ea4000c1e1900 */
/*0200*/ FSETP.GT.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720b */
/* 0x004fda0003f04000 */
/*0210*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff070424 */
/* 0x000fca00078e00ff */
/*0220*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */
/* 0x0003e8000c101904 */
/*0230*/ LDG.E R6, [R8.64+0x8] ; /* 0x0000080408067981 */
/* 0x000ea2000c1e1900 */
/*0240*/ IADD3 R5, R11, c[0x0][0x188], RZ ; /* 0x000062000b057a10 */
/* 0x000fca0007ffe0ff */
/*0250*/ IMAD.WIDE R4, R5, R0, c[0x0][0x170] ; /* 0x00005c0005047625 */
/* 0x000fe200078e0200 */
/*0260*/ FSETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720b */
/* 0x004fda0003f04000 */
/*0270*/ @P0 IMAD.MOV.U32 R11, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff0b0424 */
/* 0x000fca00078e00ff */
/*0280*/ @P0 STG.E [R2.64], R11 ; /* 0x0000000b02000986 */
/* 0x0005e8000c101904 */
/*0290*/ LDG.E R0, [R4.64+-0x4] ; /* 0xfffffc0404007981 */
/* 0x000ee4000c1e1900 */
/*02a0*/ FSETP.GT.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720b */
/* 0x008fda0003f04000 */
/*02b0*/ @P0 IMAD.MOV.U32 R13, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff0d0424 */
/* 0x001fca00078e00ff */
/*02c0*/ @P0 STG.E [R2.64], R13 ; /* 0x0000000d02000986 */
/* 0x0005e8000c101904 */
/*02d0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ee4000c1e1900 */
/*02e0*/ FSETP.GT.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720b */
/* 0x008fda0003f04000 */
/*02f0*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff070424 */
/* 0x002fca00078e00ff */
/*0300*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */
/* 0x0005e8000c101904 */
/*0310*/ LDG.E R0, [R4.64+0x4] ; /* 0x0000040404007981 */
/* 0x000ee4000c1e1900 */
/*0320*/ FSETP.GT.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720b */
/* 0x008fda0003f04000 */
/*0330*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0340*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff057424 */
/* 0x004fca00078e00ff */
/*0350*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0360*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0370*/ BRA 0x370; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected cu_hysteresis_low
.globl cu_hysteresis_low
.p2align 8
.type cu_hysteresis_low,@function
cu_hysteresis_low:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x3c
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_mov_b32 s2, exec_lo
global_load_b32 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_cmpx_lt_f32_e32 0, v0
s_cbranch_execz .LBB0_17
s_clause 0x2
s_load_b32 s4, s[0:1], 0x28
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
v_subrev_nc_u32_e32 v3, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v0, v[3:4], off offset:-4
s_waitcnt vmcnt(0)
v_cmpx_lt_f32_e32 0, v0
s_cbranch_execz .LBB0_3
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_mov_b32_e32 v0, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
global_store_b32 v[5:6], v0, off
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s5
global_load_b32 v0, v[3:4], off
s_mov_b32 s5, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_lt_f32_e32 0, v0
s_cbranch_execz .LBB0_5
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_mov_b32_e32 v0, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
global_store_b32 v[5:6], v0, off
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s5
global_load_b32 v0, v[3:4], off offset:4
s_mov_b32 s5, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_lt_f32_e32 0, v0
s_cbranch_execz .LBB0_7
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_mov_b32_e32 v0, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_store_b32 v[3:4], v0, off
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s5
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v6, vcc_lo
global_load_b32 v0, v[3:4], off offset:-4
s_waitcnt vmcnt(0)
v_cmpx_lt_f32_e32 0, v0
s_cbranch_execz .LBB0_9
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
v_mov_b32_e32 v0, 1.0
global_store_b32 v[5:6], v0, off
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s5
global_load_b32 v0, v[3:4], off offset:4
s_mov_b32 s5, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_lt_f32_e32 0, v0
s_cbranch_execz .LBB0_11
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_mov_b32_e32 v0, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_store_b32 v[3:4], v0, off
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s5
v_add_nc_u32_e32 v3, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_mov_b32 s2, exec_lo
global_load_b32 v0, v[3:4], off offset:-4
s_waitcnt vmcnt(0)
v_cmpx_lt_f32_e32 0, v0
s_cbranch_execz .LBB0_13
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_mov_b32_e32 v0, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
global_store_b32 v[5:6], v0, off
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s2
global_load_b32 v0, v[3:4], off
s_mov_b32 s2, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_lt_f32_e32 0, v0
s_cbranch_execz .LBB0_15
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_mov_b32_e32 v0, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
global_store_b32 v[5:6], v0, off
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s2
global_load_b32 v0, v[3:4], off offset:4
s_waitcnt vmcnt(0)
v_cmp_lt_f32_e32 vcc_lo, 0, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_17
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_17:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel cu_hysteresis_low
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size cu_hysteresis_low, .Lfunc_end0-cu_hysteresis_low
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: cu_hysteresis_low
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: cu_hysteresis_low.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010425f_00000000-6_cu_hysteresis_low.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z17cu_hysteresis_lowPfS_S_S_fiiPfS_S_S_fii
.type _Z46__device_stub__Z17cu_hysteresis_lowPfS_S_S_fiiPfS_S_S_fii, @function
_Z46__device_stub__Z17cu_hysteresis_lowPfS_S_S_fiiPfS_S_S_fii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movss %xmm0, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 4(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq cu_hysteresis_low(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z17cu_hysteresis_lowPfS_S_S_fiiPfS_S_S_fii, .-_Z46__device_stub__Z17cu_hysteresis_lowPfS_S_S_fiiPfS_S_S_fii
.globl cu_hysteresis_low
.type cu_hysteresis_low, @function
cu_hysteresis_low:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z17cu_hysteresis_lowPfS_S_S_fiiPfS_S_S_fii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size cu_hysteresis_low, .-cu_hysteresis_low
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "cu_hysteresis_low"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq cu_hysteresis_low(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cu_hysteresis_low.hip"
.globl __device_stub__cu_hysteresis_low # -- Begin function __device_stub__cu_hysteresis_low
.p2align 4, 0x90
.type __device_stub__cu_hysteresis_low,@function
__device_stub__cu_hysteresis_low: # @__device_stub__cu_hysteresis_low
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movss %xmm0, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $cu_hysteresis_low, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size __device_stub__cu_hysteresis_low, .Lfunc_end0-__device_stub__cu_hysteresis_low
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $cu_hysteresis_low, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type cu_hysteresis_low,@object # @cu_hysteresis_low
.section .rodata,"a",@progbits
.globl cu_hysteresis_low
.p2align 3, 0x0
cu_hysteresis_low:
.quad __device_stub__cu_hysteresis_low
.size cu_hysteresis_low, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "cu_hysteresis_low"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__cu_hysteresis_low
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym cu_hysteresis_low
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* Kazi Ahmed
* Problem 3 - HW9
* ME759 Fall 2015
*/
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <thrust/device_ptr.h>
#include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <thrust/count.h>
#include <thrust/sort.h>
int main( int argc, char** argv)
{
//day 0 0 1 2 5 5 6 6 7 8 9 9 9 10 11
thrust::host_vector<int> hday(15,0);
//site 2 3 0 1 1 2 0 1 2 1 3 4 0 1 2
thrust::host_vector<int> hsit(15,0);
//msrmnt 9 5 6 3 3 8 2 6 5 10 9 11 8 4 1
thrust::host_vector<int> hmsr(15,0);
hday[ 0]= 0; hday[ 1]= 0; hday[ 2]= 1;
hday[ 3]= 2; hday[ 4]= 5; hday[ 5]= 5;
hday[ 6]= 6; hday[ 7]= 6; hday[ 8]= 7;
hday[ 9]= 8; hday[10]= 9; hday[11]= 9;
hday[12]= 9; hday[13]=10; hday[14]=11;
hsit[ 0]= 2; hsit[ 1]= 3; hsit[ 2]= 0;
hsit[ 3]= 1; hsit[ 4]= 1; hsit[ 5]= 2;
hsit[ 6]= 0; hsit[ 7]= 1; hsit[ 8]= 2;
hsit[ 9]= 1; hsit[10]= 3; hsit[11]= 4;
hsit[12]= 0; hsit[13]= 1; hsit[14]= 2;
hmsr[ 0]= 9; hmsr[ 1]= 5; hmsr[ 2]= 6;
hmsr[ 3]= 3; hmsr[ 4]= 3; hmsr[ 5]= 8;
hmsr[ 6]= 2; hmsr[ 7]= 6; hmsr[ 8]= 5;
hmsr[ 9]=10; hmsr[10]= 9; hmsr[11]=11;
hmsr[12]= 8; hmsr[13]= 4; hmsr[14]= 1;
//Now make the device vectors
thrust::device_vector<int> dday(15,0);
thrust::device_vector<int> dsit(15,0);
thrust::device_vector<int> dmsr(15,0);
thrust::copy(hday.begin(),hday.end(),dday.begin());
thrust::copy(hsit.begin(),hsit.end(),dsit.begin());
thrust::copy(hmsr.begin(),hmsr.end(),dmsr.begin());
using namespace thrust::placeholders;
printf("See comments for explanation of logic \n");
/* Number of days for which rainfall exceeded 5 at any one location
*
* According to the prof, this should be # of days at a given location
* that rainfall exceeded 5, then that number summed over all locations.
* Therefore the answer should be 8.
* We asked this in class and so I made the code only to calculate based
* on that interpretation.
*
* Alternatively if days should not be counted twice, answer is 6.
* This would require additional code, didn't think about it.
*/
int n5;
n5 = thrust::count_if(dmsr.begin(), dmsr.end(), _1>5);
printf("Sum over locations of days > 5 rain: %d \n",n5);
/* Total rainfall at each site
*
* Expected answer 16, 26, 23, 14, 11
*
* Sort by site, then reduce by key. Use copied versions of the data since
* this doesn't zip and so won't keep the dates in tact as well.
*/
thrust::device_vector<int> sit(15,0);
thrust::device_vector<int> msr(15,0);
thrust::copy(dsit.begin(),dsit.end(),sit.begin());
thrust::copy(dmsr.begin(),dmsr.end(),msr.begin());
thrust::sort_by_key(sit.begin(), sit.end(), msr.begin());
thrust::reduce_by_key(sit.begin(),sit.end(),msr.begin(),dsit.begin(),dmsr.begin());
thrust::copy(dsit.begin(),dsit.end(),hsit.begin());
thrust::copy(dmsr.begin(),dmsr.end(),hmsr.begin());
for (int i=0; i<5; i++)
{
printf("Site %d rainfall is %d \n", hsit[i], hmsr[i]);
}
return EXIT_SUCCESS;
} | /*
* Kazi Ahmed
* Problem 3 - HW9
* ME759 Fall 2015
*/
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <thrust/device_ptr.h>
#include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <thrust/count.h>
#include <thrust/sort.h>
int main( int argc, char** argv)
{
//day 0 0 1 2 5 5 6 6 7 8 9 9 9 10 11
thrust::host_vector<int> hday(15,0);
//site 2 3 0 1 1 2 0 1 2 1 3 4 0 1 2
thrust::host_vector<int> hsit(15,0);
//msrmnt 9 5 6 3 3 8 2 6 5 10 9 11 8 4 1
thrust::host_vector<int> hmsr(15,0);
hday[ 0]= 0; hday[ 1]= 0; hday[ 2]= 1;
hday[ 3]= 2; hday[ 4]= 5; hday[ 5]= 5;
hday[ 6]= 6; hday[ 7]= 6; hday[ 8]= 7;
hday[ 9]= 8; hday[10]= 9; hday[11]= 9;
hday[12]= 9; hday[13]=10; hday[14]=11;
hsit[ 0]= 2; hsit[ 1]= 3; hsit[ 2]= 0;
hsit[ 3]= 1; hsit[ 4]= 1; hsit[ 5]= 2;
hsit[ 6]= 0; hsit[ 7]= 1; hsit[ 8]= 2;
hsit[ 9]= 1; hsit[10]= 3; hsit[11]= 4;
hsit[12]= 0; hsit[13]= 1; hsit[14]= 2;
hmsr[ 0]= 9; hmsr[ 1]= 5; hmsr[ 2]= 6;
hmsr[ 3]= 3; hmsr[ 4]= 3; hmsr[ 5]= 8;
hmsr[ 6]= 2; hmsr[ 7]= 6; hmsr[ 8]= 5;
hmsr[ 9]=10; hmsr[10]= 9; hmsr[11]=11;
hmsr[12]= 8; hmsr[13]= 4; hmsr[14]= 1;
//Now make the device vectors
thrust::device_vector<int> dday(15,0);
thrust::device_vector<int> dsit(15,0);
thrust::device_vector<int> dmsr(15,0);
thrust::copy(hday.begin(),hday.end(),dday.begin());
thrust::copy(hsit.begin(),hsit.end(),dsit.begin());
thrust::copy(hmsr.begin(),hmsr.end(),dmsr.begin());
using namespace thrust::placeholders;
printf("See comments for explanation of logic \n");
/* Number of days for which rainfall exceeded 5 at any one location
*
* According to the prof, this should be # of days at a given location
* that rainfall exceeded 5, then that number summed over all locations.
* Therefore the answer should be 8.
* We asked this in class and so I made the code only to calculate based
* on that interpretation.
*
* Alternatively if days should not be counted twice, answer is 6.
* This would require additional code, didn't think about it.
*/
int n5;
n5 = thrust::count_if(dmsr.begin(), dmsr.end(), _1>5);
printf("Sum over locations of days > 5 rain: %d \n",n5);
/* Total rainfall at each site
*
* Expected answer 16, 26, 23, 14, 11
*
* Sort by site, then reduce by key. Use copied versions of the data since
* this doesn't zip and so won't keep the dates in tact as well.
*/
thrust::device_vector<int> sit(15,0);
thrust::device_vector<int> msr(15,0);
thrust::copy(dsit.begin(),dsit.end(),sit.begin());
thrust::copy(dmsr.begin(),dmsr.end(),msr.begin());
thrust::sort_by_key(sit.begin(), sit.end(), msr.begin());
thrust::reduce_by_key(sit.begin(),sit.end(),msr.begin(),dsit.begin(),dmsr.begin());
thrust::copy(dsit.begin(),dsit.end(),hsit.begin());
thrust::copy(dmsr.begin(),dmsr.end(),hmsr.begin());
for (int i=0; i<5; i++)
{
printf("Site %d rainfall is %d \n", hsit[i], hmsr[i]);
}
return EXIT_SUCCESS;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #define WARP_SIZE 32
#define HALF_WARP_SIZE (WARP_SIZE >> 1)
__global__ void refCounter_kernel(unsigned int * d_counters0,
unsigned int * d_counters1,
unsigned int * d_del0,
unsigned int * d_del1,
const unsigned int numRepeats,
const unsigned int numSharersPerGroup,
const unsigned int numCounters,
const unsigned int numSharingGroups,
const unsigned int numCounters_perSharingGroup) {
// local variables
const unsigned int myBaseLoc = ((blockIdx.x * blockDim.x) + threadIdx.x);
const unsigned int mySharingGroup = (blockIdx.x % numSharingGroups);
const unsigned int myCounterLoc = ((mySharingGroup * numCounters_perSharingGroup) + threadIdx.x);
unsigned int * counterAddr0, * counterAddr1;
__shared__ volatile int dummyLocal[256]; // for doing local dummy calculations, assumes blockDim.x <= 256
dummyLocal[threadIdx.x] = 0;
__syncthreads();
// the counters each thread accesses is fixed, regardless of the number of loop iterations
counterAddr0 = &(d_counters0[myCounterLoc]);
counterAddr1 = &(d_counters1[myCounterLoc]);
// repeat this process a few times
for (int i = 0; i < numRepeats; ++i) {
// these atomics can be reordered with each other
atomicAdd(counterAddr0, 1);
atomicAdd(counterAddr1, 1);
// Do accesses in scratchpad here to space inc and dec out
for (int j = 0; j < numRepeats * 2; ++j) {
dummyLocal[threadIdx.x] += j;
__syncthreads();
}
// If the shared counter == 0 (old value == 1), then mark the "object" to
// be deleted
// use atomicDec's with threadfences to ensure that we have acquire-release
// semantics for DRF1 and DRF0
unsigned int currCount0 = atomicDec(counterAddr0, 1000000000);
__threadfence();
unsigned int currCount1 = atomicDec(counterAddr1, 1000000000);
__threadfence();
if (currCount0 <= 1) {
d_del0[myBaseLoc] = true;
}
if (currCount1 <= 1) {
d_del1[myBaseLoc] = true;
}
}
} | code for sm_80
Function : _Z17refCounter_kernelPjS_S_S_jjjjj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x180], PT ; /* 0x00006000ff007a0c */
/* 0x000fc60003f05270 */
/*0030*/ STS [R0.X4], RZ ; /* 0x000000ff00007388 */
/* 0x0011e80000004800 */
/*0040*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0050*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0060*/ I2F.U32.RP R4, c[0x0][0x18c] ; /* 0x0000630000047b06 */
/* 0x001e220000209000 */
/*0070*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e620000002500 */
/*0080*/ ISETP.NE.U32.AND P1, PT, RZ, c[0x0][0x18c], PT ; /* 0x00006300ff007a0c */
/* 0x000fe20003f25070 */
/*0090*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff0a7624 */
/* 0x000fe200078e00ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fc400078e00ff */
/*00c0*/ IMAD.SHL.U32 R10, R10, 0x2, RZ ; /* 0x000000020a0a7824 */
/* 0x000fe400078e00ff */
/*00d0*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fc600078e00ff */
/*00e0*/ LOP3.LUT R13, R10.reuse, 0x2, RZ, 0xc0, !PT ; /* 0x000000020a0d7812 */
/* 0x040fe200078ec0ff */
/*00f0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e280000001000 */
/*0100*/ IMAD.IADD R12, R10, 0x1, -R13 ; /* 0x000000010a0c7824 */
/* 0x000fe200078e0a0d */
/*0110*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fe20007ffe0ff */
/*0120*/ IMAD R4, R5, c[0x0][0x0], R0 ; /* 0x0000000005047a24 */
/* 0x002fc600078e0200 */
/*0130*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0140*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0150*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a03 */
/*0160*/ IMAD R7, R7, c[0x0][0x18c], RZ ; /* 0x0000630007077a24 */
/* 0x000fc800078e02ff */
/*0170*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fe200078e0002 */
/*0180*/ IADD3 R2, R10, -0x1, RZ ; /* 0xffffffff0a027810 */
/* 0x000fc80007ffe0ff */
/*0190*/ ISETP.GE.U32.AND P2, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f46070 */
/*01a0*/ IMAD.HI.U32 R3, R3, R5, RZ ; /* 0x0000000503037227 */
/* 0x000fc800078e00ff */
/*01b0*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x000fc800078e0a03 */
/*01c0*/ IMAD R3, R6, c[0x0][0x18c], R5 ; /* 0x0000630006037a24 */
/* 0x000fca00078e0205 */
/*01d0*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x18c], PT ; /* 0x0000630003007a0c */
/* 0x000fda0003f06070 */
/*01e0*/ @P0 IADD3 R3, R3, -c[0x0][0x18c], RZ ; /* 0x8000630003030a10 */
/* 0x000fc80007ffe0ff */
/*01f0*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x18c], PT ; /* 0x0000630003007a0c */
/* 0x000fda0003f06070 */
/*0200*/ @P0 IADD3 R3, R3, -c[0x0][0x18c], RZ ; /* 0x8000630003030a10 */
/* 0x000fe40007ffe0ff */
/*0210*/ @!P1 LOP3.LUT R3, RZ, c[0x0][0x18c], RZ, 0x33, !PT ; /* 0x00006300ff039a12 */
/* 0x000fca00078e33ff */
/*0220*/ IMAD R8, R3, c[0x0][0x190], R0 ; /* 0x0000640003087a24 */
/* 0x000fe400078e0200 */
/*0230*/ IMAD.WIDE.U32 R2, R4, R9, c[0x0][0x170] ; /* 0x00005c0004027625 */
/* 0x000fc800078e0009 */
/*0240*/ IMAD.WIDE.U32 R4, R4, R9, c[0x0][0x178] ; /* 0x00005e0004047625 */
/* 0x000fc800078e0009 */
/*0250*/ IMAD.WIDE.U32 R6, R8, R9, c[0x0][0x160] ; /* 0x0000580008067625 */
/* 0x000fc800078e0009 */
/*0260*/ IMAD.WIDE.U32 R8, R8, R9, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fc800078e0009 */
/*0270*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f05270 */
/*0280*/ IMAD.MOV.U32 R15, RZ, RZ, 0x1 ; /* 0x00000001ff0f7424 */
/* 0x009fe200078e00ff */
/*0290*/ IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b7810 */
/* 0x000fc80007ffe0ff */
/*02a0*/ RED.E.ADD.STRONG.GPU [R6.64], R15 ; /* 0x0000000f0600798e */
/* 0x0001e2000c10e184 */
/*02b0*/ ISETP.GE.U32.AND P1, PT, R11, c[0x0][0x180], PT ; /* 0x000060000b007a0c */
/* 0x000fc60003f26070 */
/*02c0*/ RED.E.ADD.STRONG.GPU [R8.64], R15 ; /* 0x0000000f0800798e */
/* 0x0001e6000c10e184 */
/*02d0*/ @!P0 BRA 0xc50 ; /* 0x0000097000008947 */
/* 0x006fea0003800000 */
/*02e0*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e00ff */
/*02f0*/ @!P2 BRA 0xbb0 ; /* 0x000008b00000a947 */
/* 0x000fea0003800000 */
/*0300*/ ISETP.GT.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f04270 */
/*0310*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e00ff */
/*0320*/ IMAD.MOV.U32 R16, RZ, RZ, R12 ; /* 0x000000ffff107224 */
/* 0x000fd400078e000c */
/*0330*/ @!P0 BRA 0xa70 ; /* 0x0000073000008947 */
/* 0x000fea0003800000 */
/*0340*/ ISETP.GT.AND P3, PT, R16, 0xc, PT ; /* 0x0000000c1000780c */
/* 0x000fe40003f64270 */
/*0350*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0360*/ @!P3 BRA 0x7f0 ; /* 0x000004800000b947 */
/* 0x000fea0003800000 */
/*0370*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0380*/ LDS R17, [R0.X4] ; /* 0x0000000000117984 */
/* 0x000e620000004800 */
/*0390*/ IADD3 R16, R16, -0x10, RZ ; /* 0xfffffff010107810 */
/* 0x000fc80007ffe0ff */
/*03a0*/ ISETP.GT.AND P3, PT, R16, 0xc, PT ; /* 0x0000000c1000780c */
/* 0x000fe20003f64270 */
/*03b0*/ IMAD.IADD R17, R17, 0x1, R14 ; /* 0x0000000111117824 */
/* 0x002fca00078e020e */
/*03c0*/ STS [R0.X4], R17 ; /* 0x0000001100007388 */
/* 0x0003e80000004800 */
/*03d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*03e0*/ IADD3 R17, R14, 0x4, RZ ; /* 0x000000040e117810 */
/* 0x002fca0007ffe0ff */
/*03f0*/ LDS R19, [R0.X4] ; /* 0x0000000000137984 */
/* 0x000e640000004800 */
/*0400*/ IADD3 R19, R14, 0x1, R19 ; /* 0x000000010e137810 */
/* 0x002fca0007ffe013 */
/*0410*/ STS [R0.X4], R19 ; /* 0x0000001300007388 */
/* 0x000fe80000004800 */
/*0420*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0430*/ LDS R21, [R0.X4] ; /* 0x0000000000157984 */
/* 0x000e640000004800 */
/*0440*/ IADD3 R21, R14, 0x2, R21 ; /* 0x000000020e157810 */
/* 0x002fca0007ffe015 */
/*0450*/ STS [R0.X4], R21 ; /* 0x0000001500007388 */
/* 0x000fe80000004800 */
/*0460*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0470*/ LDS R23, [R0.X4] ; /* 0x0000000000177984 */
/* 0x000e640000004800 */
/*0480*/ IADD3 R23, R14, 0x3, R23 ; /* 0x000000030e177810 */
/* 0x002fca0007ffe017 */
/*0490*/ STS [R0.X4], R23 ; /* 0x0000001700007388 */
/* 0x000fe80000004800 */
/*04a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04b0*/ LDS R18, [R0.X4] ; /* 0x0000000000127984 */
/* 0x000e640000004800 */
/*04c0*/ IMAD.IADD R19, R17, 0x1, R18 ; /* 0x0000000111137824 */
/* 0x002fca00078e0212 */
/*04d0*/ STS [R0.X4], R19 ; /* 0x0000001300007388 */
/* 0x000fe80000004800 */
/*04e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04f0*/ LDS R18, [R0.X4] ; /* 0x0000000000127984 */
/* 0x000e640000004800 */
/*0500*/ IADD3 R21, R17, 0x1, R18 ; /* 0x0000000111157810 */
/* 0x002fca0007ffe012 */
/*0510*/ STS [R0.X4], R21 ; /* 0x0000001500007388 */
/* 0x000fe80000004800 */
/*0520*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0530*/ LDS R18, [R0.X4] ; /* 0x0000000000127984 */
/* 0x000e640000004800 */
/*0540*/ IADD3 R23, R17, 0x2, R18 ; /* 0x0000000211177810 */
/* 0x002fca0007ffe012 */
/*0550*/ STS [R0.X4], R23 ; /* 0x0000001700007388 */
/* 0x000fe80000004800 */
/*0560*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0570*/ LDS R18, [R0.X4] ; /* 0x0000000000127984 */
/* 0x000e640000004800 */
/*0580*/ IADD3 R17, R17, 0x3, R18 ; /* 0x0000000311117810 */
/* 0x002fc40007ffe012 */
/*0590*/ IADD3 R18, R14, 0x8, RZ ; /* 0x000000080e127810 */
/* 0x000fc60007ffe0ff */
/*05a0*/ STS [R0.X4], R17 ; /* 0x0000001100007388 */
/* 0x000fe80000004800 */
/*05b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*05c0*/ LDS R19, [R0.X4] ; /* 0x0000000000137984 */
/* 0x000e640000004800 */
/*05d0*/ IMAD.IADD R19, R18, 0x1, R19 ; /* 0x0000000112137824 */
/* 0x002fca00078e0213 */
/*05e0*/ STS [R0.X4], R19 ; /* 0x0000001300007388 */
/* 0x000fe80000004800 */
/*05f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0600*/ LDS R21, [R0.X4] ; /* 0x0000000000157984 */
/* 0x000e640000004800 */
/*0610*/ IADD3 R21, R18, 0x1, R21 ; /* 0x0000000112157810 */
/* 0x002fca0007ffe015 */
/*0620*/ STS [R0.X4], R21 ; /* 0x0000001500007388 */
/* 0x000fe80000004800 */
/*0630*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0640*/ LDS R17, [R0.X4] ; /* 0x0000000000117984 */
/* 0x000e640000004800 */
/*0650*/ IADD3 R17, R18, 0x2, R17 ; /* 0x0000000212117810 */
/* 0x002fca0007ffe011 */
/*0660*/ STS [R0.X4], R17 ; /* 0x0000001100007388 */
/* 0x000fe80000004800 */
/*0670*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0680*/ LDS R23, [R0.X4] ; /* 0x0000000000177984 */
/* 0x000e640000004800 */
/*0690*/ IADD3 R23, R18, 0x3, R23 ; /* 0x0000000312177810 */
/* 0x002fc40007ffe017 */
/*06a0*/ IADD3 R18, R14.reuse, 0xc, RZ ; /* 0x0000000c0e127810 */
/* 0x040fe40007ffe0ff */
/*06b0*/ IADD3 R14, R14, 0x10, RZ ; /* 0x000000100e0e7810 */
/* 0x000fe20007ffe0ff */
/*06c0*/ STS [R0.X4], R23 ; /* 0x0000001700007388 */
/* 0x000fe80000004800 */
/*06d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*06e0*/ LDS R19, [R0.X4] ; /* 0x0000000000137984 */
/* 0x000e640000004800 */
/*06f0*/ IMAD.IADD R19, R18, 0x1, R19 ; /* 0x0000000112137824 */
/* 0x002fca00078e0213 */
/*0700*/ STS [R0.X4], R19 ; /* 0x0000001300007388 */
/* 0x000fe80000004800 */
/*0710*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0720*/ LDS R17, [R0.X4] ; /* 0x0000000000117984 */
/* 0x000e640000004800 */
/*0730*/ IADD3 R17, R18, 0x1, R17 ; /* 0x0000000112117810 */
/* 0x002fca0007ffe011 */
/*0740*/ STS [R0.X4], R17 ; /* 0x0000001100007388 */
/* 0x000fe80000004800 */
/*0750*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0760*/ LDS R21, [R0.X4] ; /* 0x0000000000157984 */
/* 0x000e640000004800 */
/*0770*/ IADD3 R21, R18, 0x2, R21 ; /* 0x0000000212157810 */
/* 0x002fca0007ffe015 */
/*0780*/ STS [R0.X4], R21 ; /* 0x0000001500007388 */
/* 0x000fe80000004800 */
/*0790*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*07a0*/ LDS R23, [R0.X4] ; /* 0x0000000000177984 */
/* 0x000e640000004800 */
/*07b0*/ IADD3 R23, R18, 0x3, R23 ; /* 0x0000000312177810 */
/* 0x002fca0007ffe017 */
/*07c0*/ STS [R0.X4], R23 ; /* 0x0000001700007388 */
/* 0x0003e80000004800 */
/*07d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*07e0*/ @P3 BRA 0x380 ; /* 0xfffffb9000003947 */
/* 0x002fea000383ffff */
/*07f0*/ ISETP.GT.AND P3, PT, R16, 0x4, PT ; /* 0x000000041000780c */
/* 0x000fda0003f64270 */
/*0800*/ @!P3 BRA 0xa50 ; /* 0x000002400000b947 */
/* 0x000fea0003800000 */
/*0810*/ LDS R17, [R0.X4] ; /* 0x0000000000117984 */
/* 0x000e620000004800 */
/*0820*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0830*/ IADD3 R16, R16, -0x8, RZ ; /* 0xfffffff810107810 */
/* 0x000fe20007ffe0ff */
/*0840*/ IMAD.IADD R17, R14, 0x1, R17 ; /* 0x000000010e117824 */
/* 0x002fca00078e0211 */
/*0850*/ STS [R0.X4], R17 ; /* 0x0000001100007388 */
/* 0x0003e80000004800 */
/*0860*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0870*/ IADD3 R17, R14, 0x4, RZ ; /* 0x000000040e117810 */
/* 0x002fca0007ffe0ff */
/*0880*/ LDS R19, [R0.X4] ; /* 0x0000000000137984 */
/* 0x000e640000004800 */
/*0890*/ IADD3 R19, R14, 0x1, R19 ; /* 0x000000010e137810 */
/* 0x002fca0007ffe013 */
/*08a0*/ STS [R0.X4], R19 ; /* 0x0000001300007388 */
/* 0x000fe80000004800 */
/*08b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*08c0*/ LDS R21, [R0.X4] ; /* 0x0000000000157984 */
/* 0x000e640000004800 */
/*08d0*/ IADD3 R21, R14, 0x2, R21 ; /* 0x000000020e157810 */
/* 0x002fca0007ffe015 */
/*08e0*/ STS [R0.X4], R21 ; /* 0x0000001500007388 */
/* 0x000fe80000004800 */
/*08f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0900*/ LDS R23, [R0.X4] ; /* 0x0000000000177984 */
/* 0x000e640000004800 */
/*0910*/ IADD3 R23, R14, 0x3, R23 ; /* 0x000000030e177810 */
/* 0x002fc40007ffe017 */
/*0920*/ IADD3 R14, R14, 0x8, RZ ; /* 0x000000080e0e7810 */
/* 0x000fc60007ffe0ff */
/*0930*/ STS [R0.X4], R23 ; /* 0x0000001700007388 */
/* 0x000fe80000004800 */
/*0940*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0950*/ LDS R18, [R0.X4] ; /* 0x0000000000127984 */
/* 0x000e640000004800 */
/*0960*/ IMAD.IADD R19, R17, 0x1, R18 ; /* 0x0000000111137824 */
/* 0x002fca00078e0212 */
/*0970*/ STS [R0.X4], R19 ; /* 0x0000001300007388 */
/* 0x000fe80000004800 */
/*0980*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0990*/ LDS R18, [R0.X4] ; /* 0x0000000000127984 */
/* 0x000e640000004800 */
/*09a0*/ IADD3 R21, R17, 0x1, R18 ; /* 0x0000000111157810 */
/* 0x002fca0007ffe012 */
/*09b0*/ STS [R0.X4], R21 ; /* 0x0000001500007388 */
/* 0x000fe80000004800 */
/*09c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*09d0*/ LDS R18, [R0.X4] ; /* 0x0000000000127984 */
/* 0x000e640000004800 */
/*09e0*/ IADD3 R23, R17, 0x2, R18 ; /* 0x0000000211177810 */
/* 0x002fca0007ffe012 */
/*09f0*/ STS [R0.X4], R23 ; /* 0x0000001700007388 */
/* 0x000fe80000004800 */
/*0a00*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0a10*/ LDS R18, [R0.X4] ; /* 0x0000000000127984 */
/* 0x000e640000004800 */
/*0a20*/ IADD3 R17, R17, 0x3, R18 ; /* 0x0000000311117810 */
/* 0x002fca0007ffe012 */
/*0a30*/ STS [R0.X4], R17 ; /* 0x0000001100007388 */
/* 0x0003e80000004800 */
/*0a40*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0a50*/ ISETP.NE.OR P0, PT, R16, RZ, P0 ; /* 0x000000ff1000720c */
/* 0x000fda0000705670 */
/*0a60*/ @!P0 BRA 0xbb0 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*0a70*/ LDS R17, [R0.X4] ; /* 0x0000000000117984 */
/* 0x002e620000004800 */
/*0a80*/ IADD3 R16, R16, -0x4, RZ ; /* 0xfffffffc10107810 */
/* 0x000fc80007ffe0ff */
/*0a90*/ ISETP.NE.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe20003f05270 */
/*0aa0*/ IMAD.IADD R17, R17, 0x1, R14 ; /* 0x0000000111117824 */
/* 0x002fca00078e020e */
/*0ab0*/ STS [R0.X4], R17 ; /* 0x0000001100007388 */
/* 0x000fe80000004800 */
/*0ac0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0ad0*/ LDS R19, [R0.X4] ; /* 0x0000000000137984 */
/* 0x000e640000004800 */
/*0ae0*/ IADD3 R19, R14, 0x1, R19 ; /* 0x000000010e137810 */
/* 0x002fca0007ffe013 */
/*0af0*/ STS [R0.X4], R19 ; /* 0x0000001300007388 */
/* 0x000fe80000004800 */
/*0b00*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0b10*/ LDS R21, [R0.X4] ; /* 0x0000000000157984 */
/* 0x000e640000004800 */
/*0b20*/ IADD3 R21, R14, 0x2, R21 ; /* 0x000000020e157810 */
/* 0x002fca0007ffe015 */
/*0b30*/ STS [R0.X4], R21 ; /* 0x0000001500007388 */
/* 0x000fe80000004800 */
/*0b40*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0b50*/ LDS R23, [R0.X4] ; /* 0x0000000000177984 */
/* 0x000e640000004800 */
/*0b60*/ IADD3 R23, R14, 0x3, R23 ; /* 0x000000030e177810 */
/* 0x002fc40007ffe017 */
/*0b70*/ IADD3 R14, R14, 0x4, RZ ; /* 0x000000040e0e7810 */
/* 0x000fc60007ffe0ff */
/*0b80*/ STS [R0.X4], R23 ; /* 0x0000001700007388 */
/* 0x0003e80000004800 */
/*0b90*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0ba0*/ @P0 BRA 0xa70 ; /* 0xfffffec000000947 */
/* 0x003fea000383ffff */
/*0bb0*/ ISETP.NE.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fda0003f05270 */
/*0bc0*/ @!P0 BRA 0xc50 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0bd0*/ LDS R17, [R0.X4] ; /* 0x0000000000117984 */
/* 0x002e640000004800 */
/*0be0*/ IMAD.IADD R17, R17, 0x1, R14 ; /* 0x0000000111117824 */
/* 0x002fca00078e020e */
/*0bf0*/ STS [R0.X4], R17 ; /* 0x0000001100007388 */
/* 0x000fe80000004800 */
/*0c00*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0c10*/ LDS R19, [R0.X4] ; /* 0x0000000000137984 */
/* 0x000e640000004800 */
/*0c20*/ IADD3 R19, R19, 0x1, R14 ; /* 0x0000000113137810 */
/* 0x002fca0007ffe00e */
/*0c30*/ STS [R0.X4], R19 ; /* 0x0000001300007388 */
/* 0x0003e80000004800 */
/*0c40*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0c50*/ IMAD.MOV.U32 R17, RZ, RZ, 0x3b9aca00 ; /* 0x3b9aca00ff117424 */
/* 0x002fca00078e00ff */
/*0c60*/ ATOMG.E.DEC.STRONG.GPU PT, R16, [R6.64], R17 ; /* 0x00000011061079a8 */
/* 0x000362000a1ee1c4 */
/*0c70*/ MEMBAR.SC.GPU ; /* 0x0000000000007992 */
/* 0x000fec0000002000 */
/*0c80*/ ERRBAR; /* 0x00000000000079ab */
/* 0x000fc00000000000 */
/*0c90*/ CCTL.IVALL ; /* 0x00000000ff00798f */
/* 0x000fca0002000000 */
/*0ca0*/ ATOMG.E.DEC.STRONG.GPU PT, R14, [R8.64], R17 ; /* 0x00000011080e79a8 */
/* 0x000562000a1ee1c4 */
/*0cb0*/ MEMBAR.SC.GPU ; /* 0x0000000000007992 */
/* 0x000fec0000002000 */
/*0cc0*/ ERRBAR; /* 0x00000000000079ab */
/* 0x000fc00000000000 */
/*0cd0*/ ISETP.GT.U32.AND P0, PT, R16, 0x1, PT ; /* 0x000000011000780c */
/* 0x020fe20003f04070 */
/*0ce0*/ CCTL.IVALL ; /* 0x00000000ff00798f */
/* 0x000fca0002000000 */
/*0cf0*/ ISETP.GT.U32.AND P3, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fce0003f64070 */
/*0d00*/ @!P0 STG.E [R2.64], R15 ; /* 0x0000000f02008986 */
/* 0x0007ec000c101904 */
/*0d10*/ @!P3 STG.E [R4.64], R15 ; /* 0x0000000f0400b986 */
/* 0x0007e2000c101904 */
/*0d20*/ @!P1 BRA 0x270 ; /* 0xfffff54000009947 */
/* 0x000fea000383ffff */
/*0d30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d40*/ BRA 0xd40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define WARP_SIZE 32
#define HALF_WARP_SIZE (WARP_SIZE >> 1)
__global__ void refCounter_kernel(unsigned int * d_counters0,
unsigned int * d_counters1,
unsigned int * d_del0,
unsigned int * d_del1,
const unsigned int numRepeats,
const unsigned int numSharersPerGroup,
const unsigned int numCounters,
const unsigned int numSharingGroups,
const unsigned int numCounters_perSharingGroup) {
// local variables
const unsigned int myBaseLoc = ((blockIdx.x * blockDim.x) + threadIdx.x);
const unsigned int mySharingGroup = (blockIdx.x % numSharingGroups);
const unsigned int myCounterLoc = ((mySharingGroup * numCounters_perSharingGroup) + threadIdx.x);
unsigned int * counterAddr0, * counterAddr1;
__shared__ volatile int dummyLocal[256]; // for doing local dummy calculations, assumes blockDim.x <= 256
dummyLocal[threadIdx.x] = 0;
__syncthreads();
// the counters each thread accesses is fixed, regardless of the number of loop iterations
counterAddr0 = &(d_counters0[myCounterLoc]);
counterAddr1 = &(d_counters1[myCounterLoc]);
// repeat this process a few times
for (int i = 0; i < numRepeats; ++i) {
// these atomics can be reordered with each other
atomicAdd(counterAddr0, 1);
atomicAdd(counterAddr1, 1);
// Do accesses in scratchpad here to space inc and dec out
for (int j = 0; j < numRepeats * 2; ++j) {
dummyLocal[threadIdx.x] += j;
__syncthreads();
}
// If the shared counter == 0 (old value == 1), then mark the "object" to
// be deleted
// use atomicDec's with threadfences to ensure that we have acquire-release
// semantics for DRF1 and DRF0
unsigned int currCount0 = atomicDec(counterAddr0, 1000000000);
__threadfence();
unsigned int currCount1 = atomicDec(counterAddr1, 1000000000);
__threadfence();
if (currCount0 <= 1) {
d_del0[myBaseLoc] = true;
}
if (currCount1 <= 1) {
d_del1[myBaseLoc] = true;
}
}
} | .file "tmpxft_000a1184_00000000-6_refCounter_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z17refCounter_kernelPjS_S_S_jjjjjPjS_S_S_jjjjj
.type _Z48__device_stub__Z17refCounter_kernelPjS_S_S_jjjjjPjS_S_S_jjjjj, @function
_Z48__device_stub__Z17refCounter_kernelPjS_S_S_jjjjjPjS_S_S_jjjjj:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z17refCounter_kernelPjS_S_S_jjjjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z48__device_stub__Z17refCounter_kernelPjS_S_S_jjjjjPjS_S_S_jjjjj, .-_Z48__device_stub__Z17refCounter_kernelPjS_S_S_jjjjjPjS_S_S_jjjjj
.globl _Z17refCounter_kernelPjS_S_S_jjjjj
.type _Z17refCounter_kernelPjS_S_S_jjjjj, @function
_Z17refCounter_kernelPjS_S_S_jjjjj:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z48__device_stub__Z17refCounter_kernelPjS_S_S_jjjjjPjS_S_S_jjjjj
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17refCounter_kernelPjS_S_S_jjjjj, .-_Z17refCounter_kernelPjS_S_S_jjjjj
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z17refCounter_kernelPjS_S_S_jjjjj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17refCounter_kernelPjS_S_S_jjjjj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define WARP_SIZE 32
#define HALF_WARP_SIZE (WARP_SIZE >> 1)
__global__ void refCounter_kernel(unsigned int * d_counters0,
unsigned int * d_counters1,
unsigned int * d_del0,
unsigned int * d_del1,
const unsigned int numRepeats,
const unsigned int numSharersPerGroup,
const unsigned int numCounters,
const unsigned int numSharingGroups,
const unsigned int numCounters_perSharingGroup) {
// local variables
const unsigned int myBaseLoc = ((blockIdx.x * blockDim.x) + threadIdx.x);
const unsigned int mySharingGroup = (blockIdx.x % numSharingGroups);
const unsigned int myCounterLoc = ((mySharingGroup * numCounters_perSharingGroup) + threadIdx.x);
unsigned int * counterAddr0, * counterAddr1;
__shared__ volatile int dummyLocal[256]; // for doing local dummy calculations, assumes blockDim.x <= 256
dummyLocal[threadIdx.x] = 0;
__syncthreads();
// the counters each thread accesses is fixed, regardless of the number of loop iterations
counterAddr0 = &(d_counters0[myCounterLoc]);
counterAddr1 = &(d_counters1[myCounterLoc]);
// repeat this process a few times
for (int i = 0; i < numRepeats; ++i) {
// these atomics can be reordered with each other
atomicAdd(counterAddr0, 1);
atomicAdd(counterAddr1, 1);
// Do accesses in scratchpad here to space inc and dec out
for (int j = 0; j < numRepeats * 2; ++j) {
dummyLocal[threadIdx.x] += j;
__syncthreads();
}
// If the shared counter == 0 (old value == 1), then mark the "object" to
// be deleted
// use atomicDec's with threadfences to ensure that we have acquire-release
// semantics for DRF1 and DRF0
unsigned int currCount0 = atomicDec(counterAddr0, 1000000000);
__threadfence();
unsigned int currCount1 = atomicDec(counterAddr1, 1000000000);
__threadfence();
if (currCount0 <= 1) {
d_del0[myBaseLoc] = true;
}
if (currCount1 <= 1) {
d_del1[myBaseLoc] = true;
}
}
} | #include <hip/hip_runtime.h>
#define WARP_SIZE 32
#define HALF_WARP_SIZE (WARP_SIZE >> 1)
__global__ void refCounter_kernel(unsigned int * d_counters0,
unsigned int * d_counters1,
unsigned int * d_del0,
unsigned int * d_del1,
const unsigned int numRepeats,
const unsigned int numSharersPerGroup,
const unsigned int numCounters,
const unsigned int numSharingGroups,
const unsigned int numCounters_perSharingGroup) {
// local variables
const unsigned int myBaseLoc = ((blockIdx.x * blockDim.x) + threadIdx.x);
const unsigned int mySharingGroup = (blockIdx.x % numSharingGroups);
const unsigned int myCounterLoc = ((mySharingGroup * numCounters_perSharingGroup) + threadIdx.x);
unsigned int * counterAddr0, * counterAddr1;
__shared__ volatile int dummyLocal[256]; // for doing local dummy calculations, assumes blockDim.x <= 256
dummyLocal[threadIdx.x] = 0;
__syncthreads();
// the counters each thread accesses is fixed, regardless of the number of loop iterations
counterAddr0 = &(d_counters0[myCounterLoc]);
counterAddr1 = &(d_counters1[myCounterLoc]);
// repeat this process a few times
for (int i = 0; i < numRepeats; ++i) {
// these atomics can be reordered with each other
atomicAdd(counterAddr0, 1);
atomicAdd(counterAddr1, 1);
// Do accesses in scratchpad here to space inc and dec out
for (int j = 0; j < numRepeats * 2; ++j) {
dummyLocal[threadIdx.x] += j;
__syncthreads();
}
// If the shared counter == 0 (old value == 1), then mark the "object" to
// be deleted
// use atomicDec's with threadfences to ensure that we have acquire-release
// semantics for DRF1 and DRF0
unsigned int currCount0 = atomicDec(counterAddr0, 1000000000);
__threadfence();
unsigned int currCount1 = atomicDec(counterAddr1, 1000000000);
__threadfence();
if (currCount0 <= 1) {
d_del0[myBaseLoc] = true;
}
if (currCount1 <= 1) {
d_del1[myBaseLoc] = true;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#define WARP_SIZE 32
#define HALF_WARP_SIZE (WARP_SIZE >> 1)
__global__ void refCounter_kernel(unsigned int * d_counters0,
unsigned int * d_counters1,
unsigned int * d_del0,
unsigned int * d_del1,
const unsigned int numRepeats,
const unsigned int numSharersPerGroup,
const unsigned int numCounters,
const unsigned int numSharingGroups,
const unsigned int numCounters_perSharingGroup) {
// local variables
const unsigned int myBaseLoc = ((blockIdx.x * blockDim.x) + threadIdx.x);
const unsigned int mySharingGroup = (blockIdx.x % numSharingGroups);
const unsigned int myCounterLoc = ((mySharingGroup * numCounters_perSharingGroup) + threadIdx.x);
unsigned int * counterAddr0, * counterAddr1;
__shared__ volatile int dummyLocal[256]; // for doing local dummy calculations, assumes blockDim.x <= 256
dummyLocal[threadIdx.x] = 0;
__syncthreads();
// the counters each thread accesses is fixed, regardless of the number of loop iterations
counterAddr0 = &(d_counters0[myCounterLoc]);
counterAddr1 = &(d_counters1[myCounterLoc]);
// repeat this process a few times
for (int i = 0; i < numRepeats; ++i) {
// these atomics can be reordered with each other
atomicAdd(counterAddr0, 1);
atomicAdd(counterAddr1, 1);
// Do accesses in scratchpad here to space inc and dec out
for (int j = 0; j < numRepeats * 2; ++j) {
dummyLocal[threadIdx.x] += j;
__syncthreads();
}
// If the shared counter == 0 (old value == 1), then mark the "object" to
// be deleted
// use atomicDec's with threadfences to ensure that we have acquire-release
// semantics for DRF1 and DRF0
unsigned int currCount0 = atomicDec(counterAddr0, 1000000000);
__threadfence();
unsigned int currCount1 = atomicDec(counterAddr1, 1000000000);
__threadfence();
if (currCount0 <= 1) {
d_del0[myBaseLoc] = true;
}
if (currCount1 <= 1) {
d_del1[myBaseLoc] = true;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17refCounter_kernelPjS_S_S_jjjjj
.globl _Z17refCounter_kernelPjS_S_S_jjjjj
.p2align 8
.type _Z17refCounter_kernelPjS_S_S_jjjjj,@function
_Z17refCounter_kernelPjS_S_S_jjjjj:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x20
s_mov_b64 s[2:3], src_shared_base
s_add_u32 s2, s0, 56
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v1, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v3, 0x4f7ffffe, v1 :: v_dual_lshlrev_b32 v2, 2, v0
v_cmp_ne_u32_e32 vcc_lo, -1, v2
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_3)
v_cvt_u32_f32_e32 v3, v3
v_cndmask_b32_e32 v1, 0, v2, vcc_lo
v_cndmask_b32_e64 v2, 0, s3, vcc_lo
s_addc_u32 s3, s1, 0
s_cmp_eq_u32 s4, 0
v_readfirstlane_b32 s6, v3
flat_store_b32 v[1:2], v4 dlc
s_waitcnt_vscnt null, 0x0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_10
s_load_b32 s2, s[2:3], 0xc
s_sub_i32 s3, 0, s5
s_load_b32 s7, s[0:1], 0x30
s_mul_i32 s3, s3, s6
s_load_b256 s[16:23], s[0:1], 0x0
s_mul_hi_u32 s3, s6, s3
v_mov_b32_e32 v11, 0x3b9aca00
s_add_i32 s6, s6, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s3, s15, s6
s_mul_i32 s3, s3, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_sub_i32 s3, s15, s3
s_sub_i32 s6, s3, s5
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_cmp_ge_u32 s3, s5
v_mad_u64_u32 v[5:6], null, s15, s2, v[0:1]
s_cselect_b32 s3, s6, s3
s_mov_b32 s2, 0
s_sub_i32 s0, s3, s5
s_cmp_ge_u32 s3, s5
s_cselect_b32 s0, s0, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[3:4], null, s0, s7, v[0:1]
v_mov_b32_e32 v4, 0
s_lshl_b32 s0, s4, 1
v_mov_b32_e32 v0, 1
s_cmp_lg_u32 s0, 0
v_mov_b32_e32 v6, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[3:4]
s_cselect_b32 s1, -1, 0
v_lshlrev_b64 v[9:10], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s16, v7
v_add_co_ci_u32_e32 v4, vcc_lo, s17, v8, vcc_lo
v_add_co_u32 v5, vcc_lo, s18, v7
v_add_co_ci_u32_e32 v6, vcc_lo, s19, v8, vcc_lo
v_add_co_u32 v7, vcc_lo, s20, v9
v_add_co_ci_u32_e32 v8, vcc_lo, s21, v10, vcc_lo
v_add_co_u32 v9, vcc_lo, s22, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s23, v10, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
s_add_i32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, s4
s_cbranch_scc1 .LBB0_10
.LBB0_3:
global_atomic_add_u32 v[3:4], v0, off
global_atomic_add_u32 v[5:6], v0, off
s_and_not1_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB0_6
s_mov_b32 s3, 0
.LBB0_5:
flat_load_b32 v12, v[1:2] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v12, s3, v12
s_add_i32 s3, s3, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s0, s3
flat_store_b32 v[1:2], v12 dlc
s_waitcnt_vscnt null, 0x0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_5
.LBB0_6:
global_atomic_dec_u32 v13, v[3:4], v11, off glc
s_waitcnt vmcnt(0)
s_waitcnt_vscnt null, 0x0
buffer_gl1_inv
buffer_gl0_inv
global_atomic_dec_u32 v12, v[5:6], v11, off glc
s_mov_b32 s3, exec_lo
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_gt_u32_e32 2, v13
s_cbranch_execz .LBB0_8
global_store_b32 v[7:8], v0, off
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
v_cmpx_gt_u32_e32 2, v12
s_cbranch_execz .LBB0_2
global_store_b32 v[9:10], v0, off
s_branch .LBB0_2
.LBB0_10:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17refCounter_kernelPjS_S_S_jjjjj
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 24
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17refCounter_kernelPjS_S_S_jjjjj, .Lfunc_end0-_Z17refCounter_kernelPjS_S_S_jjjjj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17refCounter_kernelPjS_S_S_jjjjj
.private_segment_fixed_size: 0
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: _Z17refCounter_kernelPjS_S_S_jjjjj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#define WARP_SIZE 32
#define HALF_WARP_SIZE (WARP_SIZE >> 1)
__global__ void refCounter_kernel(unsigned int * d_counters0,
unsigned int * d_counters1,
unsigned int * d_del0,
unsigned int * d_del1,
const unsigned int numRepeats,
const unsigned int numSharersPerGroup,
const unsigned int numCounters,
const unsigned int numSharingGroups,
const unsigned int numCounters_perSharingGroup) {
// local variables
const unsigned int myBaseLoc = ((blockIdx.x * blockDim.x) + threadIdx.x);
const unsigned int mySharingGroup = (blockIdx.x % numSharingGroups);
const unsigned int myCounterLoc = ((mySharingGroup * numCounters_perSharingGroup) + threadIdx.x);
unsigned int * counterAddr0, * counterAddr1;
__shared__ volatile int dummyLocal[256]; // for doing local dummy calculations, assumes blockDim.x <= 256
dummyLocal[threadIdx.x] = 0;
__syncthreads();
// the counters each thread accesses is fixed, regardless of the number of loop iterations
counterAddr0 = &(d_counters0[myCounterLoc]);
counterAddr1 = &(d_counters1[myCounterLoc]);
// repeat this process a few times
for (int i = 0; i < numRepeats; ++i) {
// these atomics can be reordered with each other
atomicAdd(counterAddr0, 1);
atomicAdd(counterAddr1, 1);
// Do accesses in scratchpad here to space inc and dec out
for (int j = 0; j < numRepeats * 2; ++j) {
dummyLocal[threadIdx.x] += j;
__syncthreads();
}
// If the shared counter == 0 (old value == 1), then mark the "object" to
// be deleted
// use atomicDec's with threadfences to ensure that we have acquire-release
// semantics for DRF1 and DRF0
unsigned int currCount0 = atomicDec(counterAddr0, 1000000000);
__threadfence();
unsigned int currCount1 = atomicDec(counterAddr1, 1000000000);
__threadfence();
if (currCount0 <= 1) {
d_del0[myBaseLoc] = true;
}
if (currCount1 <= 1) {
d_del1[myBaseLoc] = true;
}
}
} | .text
.file "refCounter_kernel.hip"
.globl _Z32__device_stub__refCounter_kernelPjS_S_S_jjjjj # -- Begin function _Z32__device_stub__refCounter_kernelPjS_S_S_jjjjj
.p2align 4, 0x90
.type _Z32__device_stub__refCounter_kernelPjS_S_S_jjjjj,@function
_Z32__device_stub__refCounter_kernelPjS_S_S_jjjjj: # @_Z32__device_stub__refCounter_kernelPjS_S_S_jjjjj
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17refCounter_kernelPjS_S_S_jjjjj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z32__device_stub__refCounter_kernelPjS_S_S_jjjjj, .Lfunc_end0-_Z32__device_stub__refCounter_kernelPjS_S_S_jjjjj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17refCounter_kernelPjS_S_S_jjjjj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17refCounter_kernelPjS_S_S_jjjjj,@object # @_Z17refCounter_kernelPjS_S_S_jjjjj
.section .rodata,"a",@progbits
.globl _Z17refCounter_kernelPjS_S_S_jjjjj
.p2align 3, 0x0
_Z17refCounter_kernelPjS_S_S_jjjjj:
.quad _Z32__device_stub__refCounter_kernelPjS_S_S_jjjjj
.size _Z17refCounter_kernelPjS_S_S_jjjjj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17refCounter_kernelPjS_S_S_jjjjj"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__refCounter_kernelPjS_S_S_jjjjj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17refCounter_kernelPjS_S_S_jjjjj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
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